diff --git a/components/esp_adc/adc_continuous.c b/components/esp_adc/adc_continuous.c index 77550efaa5..ad8e25c6da 100644 --- a/components/esp_adc/adc_continuous.c +++ b/components/esp_adc/adc_continuous.c @@ -344,6 +344,10 @@ esp_err_t adc_continuous_start(adc_continuous_handle_t handle) adc_hal_digi_connect(true); adc_hal_digi_enable(true); +#if ADC_LL_DEFAULT_CONV_LIMIT_EN + adc_ll_digi_convert_limit_enable(false); +#endif + return ESP_OK; } diff --git a/components/hal/esp32/include/hal/adc_ll.h b/components/hal/esp32/include/hal/adc_ll.h index a2ce7aaa5d..4cc4b8a9dd 100644 --- a/components/hal/esp32/include/hal/adc_ll.h +++ b/components/hal/esp32/include/hal/adc_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #pragma once #include +#include "esp_rom_sys.h" #include "hal/adc_types.h" #include "hal/misc.h" #include "hal/assert.h" @@ -49,7 +50,7 @@ extern "C" { //On esp32, ADC can only be continuously triggered when `ADC_LL_DEFAULT_CONV_LIMIT_EN == 1`, `ADC_LL_DEFAULT_CONV_LIMIT_NUM != 0` #define ADC_LL_DEFAULT_CONV_LIMIT_EN 1 -#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 +#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255 /*--------------------------------------------------------------- PWDET (Power Detect) @@ -159,6 +160,8 @@ static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num) */ static inline void adc_ll_digi_convert_limit_enable(bool enable) { + //ESP32 has a hardware limitaton, meas_num_limit can only be cleared after ADC enters sample phase(10~15us after start) + esp_rom_delay_us(60); SYSCON.saradc_ctrl2.meas_num_limit = enable; } diff --git a/components/hal/esp32c3/include/hal/adc_ll.h b/components/hal/esp32c3/include/hal/adc_ll.h index 0a1b4f568c..526eccbcd1 100644 --- a/components/hal/esp32c3/include/hal/adc_ll.h +++ b/components/hal/esp32c3/include/hal/adc_ll.h @@ -61,7 +61,7 @@ extern "C" { #define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 -#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 +#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255 /** * Workaround: on ESP32C3, the internal hardware counter that counts ADC samples will not be automatically cleared, diff --git a/components/hal/esp32c6/include/hal/adc_ll.h b/components/hal/esp32c6/include/hal/adc_ll.h index 8f869e3488..32e314047c 100644 --- a/components/hal/esp32c6/include/hal/adc_ll.h +++ b/components/hal/esp32c6/include/hal/adc_ll.h @@ -62,7 +62,7 @@ extern "C" { #define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 -#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 +#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255 #define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32C6 supported to manage power mode /*--------------------------------------------------------------- diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h index 9e36c9e727..bccaa19504 100644 --- a/components/hal/esp32h2/include/hal/adc_ll.h +++ b/components/hal/esp32h2/include/hal/adc_ll.h @@ -63,7 +63,7 @@ extern "C" { #define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 -#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 +#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255 #define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32H2 supported to manage power mode /*--------------------------------------------------------------- diff --git a/components/hal/esp32p4/include/hal/adc_ll.h b/components/hal/esp32p4/include/hal/adc_ll.h index d444031156..db87da4389 100644 --- a/components/hal/esp32p4/include/hal/adc_ll.h +++ b/components/hal/esp32p4/include/hal/adc_ll.h @@ -60,7 +60,7 @@ extern "C" { #define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 -#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 +#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255 #define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32P4 supported to manage power mode /*--------------------------------------------------------------- diff --git a/components/hal/esp32s2/include/hal/adc_ll.h b/components/hal/esp32s2/include/hal/adc_ll.h index a54b76c784..4c5658638f 100644 --- a/components/hal/esp32s2/include/hal/adc_ll.h +++ b/components/hal/esp32s2/include/hal/adc_ll.h @@ -62,7 +62,7 @@ extern "C" { #define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 -#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 +#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255 /*--------------------------------------------------------------- PWDET (Power Detect) diff --git a/components/hal/esp32s3/include/hal/adc_ll.h b/components/hal/esp32s3/include/hal/adc_ll.h index 21edb2878f..ff7f658252 100644 --- a/components/hal/esp32s3/include/hal/adc_ll.h +++ b/components/hal/esp32s3/include/hal/adc_ll.h @@ -64,7 +64,7 @@ extern "C" { #define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 -#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 +#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255 /*--------------------------------------------------------------- PWDET (Power Detect)