diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in index 0055bf514d..dcb618806e 100644 --- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in @@ -539,6 +539,10 @@ config SOC_RCC_IS_INDEPENDENT bool default y +config SOC_ASYNCHRONOUS_BUS_ERROR_MODE + bool + default y + config SOC_PM_SUPPORT_EXT1_WAKEUP bool default y diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h index e6113dd6c5..f6fd5fb156 100644 --- a/components/soc/esp32s31/include/soc/soc_caps.h +++ b/components/soc/esp32s31/include/soc/soc_caps.h @@ -310,7 +310,8 @@ #define SOC_CLK_LP_FAST_SUPPORT_XTAL (1) /*!< Support XTAL clock as the LP_FAST clock source */ #define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control has own registers for each module */ - +/*-------------------------- Memory CAPS --------------------------*/ +#define SOC_ASYNCHRONOUS_BUS_ERROR_MODE (1) /*-------------------------- Power Management CAPS ----------------------------*/ #define SOC_PM_SUPPORT_EXT1_WAKEUP (1) #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*! Any: @pytest.mark.generic -@idf_parametrize('target', ['esp32p4'], indirect=['target']) +@idf_parametrize('target', ['esp32p4', 'esp32s31'], indirect=['target']) def test_hwloop_jump(dut: PanicTestDut) -> None: start_gdb(dut) @@ -275,7 +275,7 @@ def coproc_registers_test(dut: PanicTestDut, regs_type: str, set_registers: Call @pytest.mark.generic -@idf_parametrize('target', ['esp32', 'esp32s3', 'esp32p4'], indirect=['target']) +@idf_parametrize('target', ['esp32', 'esp32s3', 'esp32p4', 'esp32s31'], indirect=['target']) def test_coproc_registers(dut: PanicTestDut) -> None: start_gdb(dut)