diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
index 3951544fd4..f087890a86 100644
--- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
@@ -423,6 +423,10 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     bool
     default y
 
+config SOC_SDM_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_ETM_SUPPORT_SLEEP_RETENTION
     bool
     default y
diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h
index 0da3cd1571..9c62c663f4 100644
--- a/components/soc/esp32h21/include/soc/soc_caps.h
+++ b/components/soc/esp32h21/include/soc/soc_caps.h
@@ -226,7 +226,7 @@
 // #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM       (3)
 
 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/
-// #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 //TODO [ESP32H21] IDF-14159
+#define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
 
 /*-------------------------- ETM CAPS -----------------------------------*/
 #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
diff --git a/components/soc/esp32h21/register/soc/gpio_ext_reg.h b/components/soc/esp32h21/register/soc/gpio_ext_reg.h
index 07014d3462..91e5fb79fa 100644
--- a/components/soc/esp32h21/register/soc/gpio_ext_reg.h
+++ b/components/soc/esp32h21/register/soc/gpio_ext_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0 OR MIT
  */
@@ -14,7 +14,7 @@ extern "C" {
 /** GPIO_EXT_SIGMADELTA_MISC_REG register
  *  MISC Register
  */
-#define GPIO_EXT_SIGMADELTA_MISC_REG (DR_REG_GPIO_BASE + 0x4)
+#define GPIO_EXT_SIGMADELTA_MISC_REG (DR_REG_GPIO_EXT_BASE + 0x4)
 /** GPIO_EXT_SIGMADELTA_CLK_EN : R/W; bitpos: [0]; default: 0;
  *  Clock enable bit of sigma delta modulation.
  */
@@ -26,7 +26,7 @@ extern "C" {
 /** GPIO_EXT_SIGMADELTA0_REG register
  *  Duty Cycle Configure Register of SDM0
  */
-#define GPIO_EXT_SIGMADELTA0_REG (DR_REG_GPIO_BASE + 0x8)
+#define GPIO_EXT_SIGMADELTA0_REG (DR_REG_GPIO_EXT_BASE + 0x8)
 /** GPIO_EXT_SD0_IN : R/W; bitpos: [7:0]; default: 0;
  *  This field is used to configure the duty cycle of sigma delta modulation output.
  */
@@ -45,7 +45,7 @@ extern "C" {
 /** GPIO_EXT_SIGMADELTA1_REG register
  *  Duty Cycle Configure Register of SDM1
  */
-#define GPIO_EXT_SIGMADELTA1_REG (DR_REG_GPIO_BASE + 0xc)
+#define GPIO_EXT_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0xc)
 /** GPIO_EXT_SD1_IN : R/W; bitpos: [7:0]; default: 0;
  *  This field is used to configure the duty cycle of sigma delta modulation output.
  */
@@ -64,7 +64,7 @@ extern "C" {
 /** GPIO_EXT_SIGMADELTA2_REG register
  *  Duty Cycle Configure Register of SDM2
  */
-#define GPIO_EXT_SIGMADELTA2_REG (DR_REG_GPIO_BASE + 0x10)
+#define GPIO_EXT_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x10)
 /** GPIO_EXT_SD2_IN : R/W; bitpos: [7:0]; default: 0;
  *  This field is used to configure the duty cycle of sigma delta modulation output.
  */
@@ -83,7 +83,7 @@ extern "C" {
 /** GPIO_EXT_SIGMADELTA3_REG register
  *  Duty Cycle Configure Register of SDM3
  */
-#define GPIO_EXT_SIGMADELTA3_REG (DR_REG_GPIO_BASE + 0x14)
+#define GPIO_EXT_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0x14)
 /** GPIO_EXT_SD3_IN : R/W; bitpos: [7:0]; default: 0;
  *  This field is used to configure the duty cycle of sigma delta modulation output.
  */
@@ -102,7 +102,7 @@ extern "C" {
 /** GPIO_EXT_PAD_COMP_CONFIG_0_REG register
  *  PAD Compare configure Register
  */
-#define GPIO_EXT_PAD_COMP_CONFIG_0_REG (DR_REG_GPIO_BASE + 0x58)
+#define GPIO_EXT_PAD_COMP_CONFIG_0_REG (DR_REG_GPIO_EXT_BASE + 0x58)
 /** GPIO_EXT_XPD_COMP_0 : R/W; bitpos: [0]; default: 0;
  *  Pad compare enable bit.
  */
@@ -129,7 +129,7 @@ extern "C" {
 /** GPIO_EXT_PAD_COMP_FILTER_0_REG register
  *  Zero Detect filter Register
  */
-#define GPIO_EXT_PAD_COMP_FILTER_0_REG (DR_REG_GPIO_BASE + 0x5c)
+#define GPIO_EXT_PAD_COMP_FILTER_0_REG (DR_REG_GPIO_EXT_BASE + 0x5c)
 /** GPIO_EXT_ZERO_DET_FILTER_CNT_0 : R/W; bitpos: [31:0]; default: 0;
  *  Zero Detect filter cycle length
  */
@@ -141,7 +141,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH0_REG register
  *  Glitch Filter Configure Register of Channel0
  */
-#define GPIO_EXT_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_BASE + 0xd8)
+#define GPIO_EXT_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_EXT_BASE + 0xd8)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -174,7 +174,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH1_REG register
  *  Glitch Filter Configure Register of Channel1
  */
-#define GPIO_EXT_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_BASE + 0xdc)
+#define GPIO_EXT_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_EXT_BASE + 0xdc)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -207,7 +207,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH2_REG register
  *  Glitch Filter Configure Register of Channel2
  */
-#define GPIO_EXT_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_BASE + 0xe0)
+#define GPIO_EXT_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_EXT_BASE + 0xe0)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -240,7 +240,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH3_REG register
  *  Glitch Filter Configure Register of Channel3
  */
-#define GPIO_EXT_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_BASE + 0xe4)
+#define GPIO_EXT_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_EXT_BASE + 0xe4)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -273,7 +273,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH4_REG register
  *  Glitch Filter Configure Register of Channel4
  */
-#define GPIO_EXT_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_BASE + 0xe8)
+#define GPIO_EXT_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_EXT_BASE + 0xe8)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -306,7 +306,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH5_REG register
  *  Glitch Filter Configure Register of Channel5
  */
-#define GPIO_EXT_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_BASE + 0xec)
+#define GPIO_EXT_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_EXT_BASE + 0xec)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -339,7 +339,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH6_REG register
  *  Glitch Filter Configure Register of Channel6
  */
-#define GPIO_EXT_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_BASE + 0xf0)
+#define GPIO_EXT_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_EXT_BASE + 0xf0)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -372,7 +372,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH7_REG register
  *  Glitch Filter Configure Register of Channel7
  */
-#define GPIO_EXT_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_BASE + 0xf4)
+#define GPIO_EXT_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_EXT_BASE + 0xf4)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Glitch Filter channel enable bit.
  */
@@ -405,7 +405,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH0_CFG_REG register
  *  Etm Config register of Channel0
  */
-#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_BASE + 0x118)
+#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x118)
 /** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -424,7 +424,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH1_CFG_REG register
  *  Etm Config register of Channel1
  */
-#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_BASE + 0x11c)
+#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x11c)
 /** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -443,7 +443,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH2_CFG_REG register
  *  Etm Config register of Channel2
  */
-#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_BASE + 0x120)
+#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x120)
 /** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -462,7 +462,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH3_CFG_REG register
  *  Etm Config register of Channel3
  */
-#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_BASE + 0x124)
+#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x124)
 /** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -481,7 +481,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH4_CFG_REG register
  *  Etm Config register of Channel4
  */
-#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_BASE + 0x128)
+#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x128)
 /** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -500,7 +500,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH5_CFG_REG register
  *  Etm Config register of Channel5
  */
-#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_BASE + 0x12c)
+#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x12c)
 /** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -519,7 +519,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH6_CFG_REG register
  *  Etm Config register of Channel6
  */
-#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_BASE + 0x130)
+#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x130)
 /** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -538,7 +538,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH7_CFG_REG register
  *  Etm Config register of Channel7
  */
-#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_BASE + 0x134)
+#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x134)
 /** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
  *  Etm event channel select gpio.
  */
@@ -557,7 +557,7 @@ extern "C" {
 /** GPIO_EXT_ETM_TASK_P0_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_BASE + 0x158)
+#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x158)
 /** GPIO_EXT_ETM_TASK_GPIO0_SEL : R/W; bitpos: [2:0]; default: 0;
  *  GPIO choose a etm task channel.
  */
@@ -632,7 +632,7 @@ extern "C" {
 /** GPIO_EXT_ETM_TASK_P1_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_BASE + 0x15c)
+#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x15c)
 /** GPIO_EXT_ETM_TASK_GPIO5_SEL : R/W; bitpos: [2:0]; default: 0;
  *  GPIO choose a etm task channel.
  */
@@ -707,7 +707,7 @@ extern "C" {
 /** GPIO_EXT_ETM_TASK_P2_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_BASE + 0x160)
+#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x160)
 /** GPIO_EXT_ETM_TASK_GPIO10_SEL : R/W; bitpos: [2:0]; default: 0;
  *  GPIO choose a etm task channel.
  */
@@ -782,7 +782,7 @@ extern "C" {
 /** GPIO_EXT_ETM_TASK_P3_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_BASE + 0x164)
+#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x164)
 /** GPIO_EXT_ETM_TASK_GPIO15_SEL : R/W; bitpos: [2:0]; default: 0;
  *  GPIO choose a etm task channel.
  */
@@ -857,7 +857,7 @@ extern "C" {
 /** GPIO_EXT_ETM_TASK_P4_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_BASE + 0x168)
+#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x168)
 /** GPIO_EXT_ETM_TASK_GPIO20_SEL : R/W; bitpos: [2:0]; default: 0;
  *  GPIO choose a etm task channel.
  */
@@ -932,7 +932,7 @@ extern "C" {
 /** GPIO_EXT_ETM_TASK_P5_CFG_REG register
  *  Etm Configure Register to decide which GPIO been chosen
  */
-#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_BASE + 0x16c)
+#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x16c)
 /** GPIO_EXT_ETM_TASK_GPIO25_SEL : R/W; bitpos: [2:0]; default: 0;
  *  GPIO choose a etm task channel.
  */
@@ -951,7 +951,7 @@ extern "C" {
 /** GPIO_EXT_INT_RAW_REG register
  *  GPIO_EXT interrupt raw register
  */
-#define GPIO_EXT_INT_RAW_REG (DR_REG_GPIO_BASE + 0x1d0)
+#define GPIO_EXT_INT_RAW_REG (DR_REG_GPIO_EXT_BASE + 0x1d0)
 /** GPIO_EXT_COMP_NEG_0_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
  *  analog comparator pos edge interrupt raw
  */
@@ -977,7 +977,7 @@ extern "C" {
 /** GPIO_EXT_INT_ST_REG register
  *  GPIO_EXT interrupt masked register
  */
-#define GPIO_EXT_INT_ST_REG (DR_REG_GPIO_BASE + 0x1d4)
+#define GPIO_EXT_INT_ST_REG (DR_REG_GPIO_EXT_BASE + 0x1d4)
 /** GPIO_EXT_COMP_NEG_0_INT_ST : RO; bitpos: [0]; default: 0;
  *  analog comparator pos edge interrupt status
  */
@@ -1003,7 +1003,7 @@ extern "C" {
 /** GPIO_EXT_INT_ENA_REG register
  *  GPIO_EXT interrupt enable register
  */
-#define GPIO_EXT_INT_ENA_REG (DR_REG_GPIO_BASE + 0x1d8)
+#define GPIO_EXT_INT_ENA_REG (DR_REG_GPIO_EXT_BASE + 0x1d8)
 /** GPIO_EXT_COMP_NEG_0_INT_ENA : R/W; bitpos: [0]; default: 1;
  *  analog comparator pos edge interrupt enable
  */
@@ -1029,7 +1029,7 @@ extern "C" {
 /** GPIO_EXT_INT_CLR_REG register
  *  GPIO_EXT interrupt clear register
  */
-#define GPIO_EXT_INT_CLR_REG (DR_REG_GPIO_BASE + 0x1dc)
+#define GPIO_EXT_INT_CLR_REG (DR_REG_GPIO_EXT_BASE + 0x1dc)
 /** GPIO_EXT_COMP_NEG_0_INT_CLR : WT; bitpos: [0]; default: 0;
  *  analog comparator pos edge interrupt clear
  */
@@ -1055,7 +1055,7 @@ extern "C" {
 /** GPIO_EXT_PIN_CTRL_REG register
  *  Clock Output Configuration Register
  */
-#define GPIO_EXT_PIN_CTRL_REG (DR_REG_GPIO_BASE + 0x1e0)
+#define GPIO_EXT_PIN_CTRL_REG (DR_REG_GPIO_EXT_BASE + 0x1e0)
 /** GPIO_EXT_CLK_OUT1 : R/W; bitpos: [4:0]; default: 15;
  *  If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
  *  CLK_OUT_out1 can be found in peripheral output signals.
@@ -1084,7 +1084,7 @@ extern "C" {
 /** GPIO_EXT_VERSION_REG register
  *  Version Control Register
  */
-#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_BASE + 0x1fc)
+#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0x1fc)
 /** GPIO_EXT_DATE : R/W; bitpos: [27:0]; default: 37781840;
  *  Version control register.
  */
diff --git a/examples/system/README.md b/examples/system/README.md
index 55c41cce55..d2b47f8db2 100644
--- a/examples/system/README.md
+++ b/examples/system/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
 
 # System Examples