diff --git a/components/bootloader_support/src/bootloader_random_esp32c5.c b/components/bootloader_support/src/bootloader_random_esp32c5.c
index dd6fcc2698..ca937422d7 100644
--- a/components/bootloader_support/src/bootloader_random_esp32c5.c
+++ b/components/bootloader_support/src/bootloader_random_esp32c5.c
@@ -8,8 +8,8 @@
 #include "hal/regi2c_ctrl_ll.h"
 #include "hal/adc_ll.h"
 #include "hal/adc_types.h"
+#include "hal/rng_ll.h"
 #include "esp_private/regi2c_ctrl.h"
-#include "soc/lpperi_reg.h"
 #include "hal/temperature_sensor_ll.h"
 #include "esp_private/sar_periph_ctrl.h"
 
@@ -67,9 +67,9 @@ void bootloader_random_enable(void)
     adc_ll_digi_set_trigger_interval(200);
     adc_ll_digi_trigger_enable();
 
-    SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_SAMPLE_ENABLE);
-    REG_SET_FIELD(LPPERI_RNG_CFG_REG, LPPERI_RTC_TIMER_EN, 0x3);
-    SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_TIMER_EN);
+    rng_ll_enable_sample(true);
+    rng_ll_enable_rtc_timer(true);
+    rng_ll_enable_rng_timer(true);
 }
 
 void bootloader_random_disable(void)
diff --git a/components/esp_hw_support/hw_random.c b/components/esp_hw_support/hw_random.c
index f451189ff0..064de2d4d9 100644
--- a/components/esp_hw_support/hw_random.c
+++ b/components/esp_hw_support/hw_random.c
@@ -25,6 +25,9 @@
 
 #if SOC_RNG_CLOCK_IS_INDEPENDENT
 #include "hal/lp_clkrst_ll.h"
+#if SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE || SOC_RNG_RTC_TIMER_ENTROPY_SOURCE
+#include "hal/rng_ll.h"
+#endif
 #endif
 
 #if defined CONFIG_IDF_TARGET_ESP32S3
@@ -106,15 +109,10 @@ void esp_fill_random(void *buf, size_t len)
 #if SOC_RNG_CLOCK_IS_INDEPENDENT && !ESP_TEE_BUILD
 ESP_SYSTEM_INIT_FN(init_rng, SECONDARY, BIT(0), 102)
 {
+#if SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE || SOC_RNG_RTC_TIMER_ENTROPY_SOURCE
+    rng_ll_enable();
+#else
     _lp_clkrst_ll_enable_rng_clock(true);
-#if SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE
-    SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_SAMPLE_ENABLE);
-#endif
-
-#if SOC_RNG_RTC_TIMER_ENTROPY_SOURCE
-    // This would only be effective if the RTC clock is enabled
-    REG_SET_FIELD(LPPERI_RNG_CFG_REG, LPPERI_RTC_TIMER_EN, 0x3);
-    SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_TIMER_EN);
 #endif
     return ESP_OK;
 }
diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index 80e848b18c..83c1deef29 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -41,6 +41,10 @@
 #include "hal/rtc_io_hal.h"
 #include "hal/clk_tree_hal.h"
 
+#if SOC_IS(ESP32C5) // Remove after all chips rng_ll.h implemented
+#include "hal/rng_ll.h"
+#endif
+
 #if SOC_SLEEP_SYSTIMER_STALL_WORKAROUND
 #include "hal/systimer_ll.h"
 #endif
@@ -856,6 +860,13 @@ static SLEEP_FN_ATTR void misc_modules_wake_prepare(uint32_t sleep_flags)
 #if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
     regi2c_tsens_reg_write();
 #endif
+#if RNG_LL_DEPENDS_ON_LP_PERIPH
+    if (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) {
+        // Re-enable the RNG module.
+        rng_ll_reset();
+        rng_ll_enable();
+    }
+#endif
 }
 
 static SLEEP_FN_ATTR void sleep_low_power_clock_calibration(bool is_dslp)
diff --git a/components/hal/esp32c5/include/hal/rng_ll.h b/components/hal/esp32c5/include/hal/rng_ll.h
new file mode 100644
index 0000000000..fd3cd432fe
--- /dev/null
+++ b/components/hal/esp32c5/include/hal/rng_ll.h
@@ -0,0 +1,88 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "soc/lpperi_struct.h"
+#include "hal/lp_clkrst_ll.h"
+
+#define RNG_LL_DEPENDS_ON_LP_PERIPH 1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Enable or disable RNG sampling.
+ *
+ * @param enable True to enable, False to disable
+ */
+static inline void rng_ll_enable_sample(bool enable)
+{
+    LPPERI.rng_cfg.rng_sample_enable = enable;
+}
+
+/**
+ * @brief Enable or disable rng xor rtc timer.
+ *
+ * @param enable True to enable, False to disable
+ */
+static inline void rng_ll_enable_rtc_timer(bool enable)
+{
+    LPPERI.rng_cfg.rtc_timer_en = enable ? 0x3 : 0x0;
+}
+
+/**
+ * @brief Enable or disable rng xor async rng timer.
+ *
+ * @param enable True to enable, False to disable
+ */
+static inline void rng_ll_enable_rng_timer(bool enable)
+{
+    LPPERI.rng_cfg.rng_timer_en = enable;
+}
+
+/**
+ * @brief Reset RNG.
+ */
+static inline void rng_ll_reset(void)
+{
+    LPPERI.reset_en.lp_rng_reset_en = 1;
+    LPPERI.reset_en.lp_rng_reset_en = 0;
+}
+
+/**
+ * @brief Enable RNG module
+ *
+ * TODO: unify in rng_hal.c
+ */
+static inline void rng_ll_enable(void)
+{
+    _lp_clkrst_ll_enable_rng_clock(true);
+    rng_ll_enable_sample(true);
+    rng_ll_enable_rtc_timer(true);
+    rng_ll_enable_rng_timer(true);
+}
+
+/**
+ * @brief Disable RNG module
+ *
+ * TODO: unify in rng_hal.c
+ */
+static inline void rng_ll_disable(void)
+{
+    rng_ll_enable_sample(false);
+    rng_ll_enable_rtc_timer(false);
+    rng_ll_enable_rng_timer(false);
+    _lp_clkrst_ll_enable_rng_clock(false);
+}
+
+
+#ifdef __cplusplus
+}
+#endif