diff --git a/components/app_update/test_apps/test_app_update/.build-test-rules.yml b/components/app_update/test_apps/test_app_update/.build-test-rules.yml index b0fce92576..ce361079ee 100644 --- a/components/app_update/test_apps/test_app_update/.build-test-rules.yml +++ b/components/app_update/test_apps/test_app_update/.build-test-rules.yml @@ -15,6 +15,9 @@ components/app_update/test_apps: - if: IDF_TARGET == "esp32c61" and CONFIG_NAME == "xip_psram_with_rom_impl" temporary: true reason: not supported yet # TODO: [ESP32C61] IDF-12784 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14401 disable_test: - if: CONFIG_NAME == "recovery_bootloader" and SOC_RECOVERY_BOOTLOADER_SUPPORTED == 1 and IDF_TARGET == "esp32c61" temporary: true diff --git a/components/app_update/test_apps/test_app_update/README.md b/components/app_update/test_apps/test_app_update/README.md index 7b96141437..3c34983dd5 100644 --- a/components/app_update/test_apps/test_app_update/README.md +++ b/components/app_update/test_apps/test_app_update/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | diff --git a/components/cxx/test_apps/.build-test-rules.yml b/components/cxx/test_apps/.build-test-rules.yml index 787715d396..701669fcbd 100644 --- a/components/cxx/test_apps/.build-test-rules.yml +++ b/components/cxx/test_apps/.build-test-rules.yml @@ -5,3 +5,7 @@ components/cxx/test_apps: - if: IDF_TARGET in ["esp32", "esp32c3", "esp32c61", "esp32p4"] temporary: true reason: the other targets are not tested yet + disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14402 diff --git a/components/cxx/test_apps/exception/README.md b/components/cxx/test_apps/exception/README.md index c68d6f39e8..702b3425ef 100644 --- a/components/cxx/test_apps/exception/README.md +++ b/components/cxx/test_apps/exception/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 | ESP32-P4 | -| ----------------- | ----- | -------- | --------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 | +| ----------------- | ----- | -------- | --------- | diff --git a/components/cxx/test_apps/exception_no_except/README.md b/components/cxx/test_apps/exception_no_except/README.md index c68d6f39e8..702b3425ef 100644 --- a/components/cxx/test_apps/exception_no_except/README.md +++ b/components/cxx/test_apps/exception_no_except/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 | ESP32-P4 | -| ----------------- | ----- | -------- | --------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 | +| ----------------- | ----- | -------- | --------- | diff --git a/components/cxx/test_apps/general/README.md b/components/cxx/test_apps/general/README.md index c68d6f39e8..702b3425ef 100644 --- a/components/cxx/test_apps/general/README.md +++ b/components/cxx/test_apps/general/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 | ESP32-P4 | -| ----------------- | ----- | -------- | --------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 | +| ----------------- | ----- | -------- | --------- | diff --git a/components/cxx/test_apps/rtti/README.md b/components/cxx/test_apps/rtti/README.md index c68d6f39e8..702b3425ef 100644 --- a/components/cxx/test_apps/rtti/README.md +++ b/components/cxx/test_apps/rtti/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 | ESP32-P4 | -| ----------------- | ----- | -------- | --------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C61 | +| ----------------- | ----- | -------- | --------- | diff --git a/components/driver/test_apps/.build-test-rules.yml b/components/driver/test_apps/.build-test-rules.yml index 2e2732dd8c..1b3de67e68 100644 --- a/components/driver/test_apps/.build-test-rules.yml +++ b/components/driver/test_apps/.build-test-rules.yml @@ -12,6 +12,9 @@ components/driver/test_apps/legacy_twai: disable: - if: SOC_TWAI_SUPPORTED != 1 or SOC_TWAI_SUPPORT_FD == 1 reason: legacy driver doesn't support FD + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14393 depends_filepatterns: - components/driver/twai/**/* depends_components: diff --git a/components/driver/test_apps/legacy_twai/README.md b/components/driver/test_apps/legacy_twai/README.md index 5edaa3c4ca..3717871adf 100644 --- a/components/driver/test_apps/legacy_twai/README.md +++ b/components/driver/test_apps/legacy_twai/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | # Enable Socket CAN Device with bitrate 250Kbps diff --git a/components/efuse/esp32p4/sources.cmake b/components/efuse/esp32p4/sources.cmake index c05edde119..ddbdc18da5 100644 --- a/components/efuse/esp32p4/sources.cmake +++ b/components/efuse/esp32p4/sources.cmake @@ -6,6 +6,7 @@ set(EFUSE_SOC_SRCS if(CONFIG_ESP32P4_REV_MIN_FULL GREATER_EQUAL 300) list(APPEND EFUSE_SOC_SRCS "esp_efuse_table_v3.0.c" + "esp_efuse_rtc_calib.c" ) else() list(APPEND EFUSE_SOC_SRCS diff --git a/components/efuse/test_apps/.build-test-rules.yml b/components/efuse/test_apps/.build-test-rules.yml index 22eeea2060..b3c80820a0 100644 --- a/components/efuse/test_apps/.build-test-rules.yml +++ b/components/efuse/test_apps/.build-test-rules.yml @@ -3,6 +3,10 @@ components/efuse/test_apps: enable: - if: (INCLUDE_DEFAULT == 1 and SOC_EFUSE_SUPPORTED == 1) or IDF_TARGET == "linux") + disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14403 disable_test: - if: IDF_TARGET in ["esp32s2", "esp32s3"] reason: eFuse for S2 and S3 is similar to the C3 chip, so we only test for C3. diff --git a/components/efuse/test_apps/README.md b/components/efuse/test_apps/README.md index 8b53053b43..c694e797c7 100644 --- a/components/efuse/test_apps/README.md +++ b/components/efuse/test_apps/README.md @@ -1,3 +1,3 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | ----- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | Linux | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | ----- | diff --git a/components/esp_adc/test_apps/.build-test-rules.yml b/components/esp_adc/test_apps/.build-test-rules.yml index aa97546c7d..3a0b9ebae5 100644 --- a/components/esp_adc/test_apps/.build-test-rules.yml +++ b/components/esp_adc/test_apps/.build-test-rules.yml @@ -4,6 +4,10 @@ components/esp_adc/test_apps/adc: disable: - if: SOC_ADC_SUPPORTED != 1 - if: CONFIG_NAME == "gdma_iram_safe" and IDF_TARGET in ["esp32", "esp32s2", "esp32c2"] + disable_test: + - if: IDF_TARGET == "esp32p4" and CONFIG_NAME != "esp32p4_eco4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14357 depends_components: - esp_adc - esp_driver_gpio diff --git a/components/esp_adc/test_apps/adc/pytest_adc.py b/components/esp_adc/test_apps/adc/pytest_adc.py index d44ee01691..91659bf030 100644 --- a/components/esp_adc/test_apps/adc/pytest_adc.py +++ b/components/esp_adc/test_apps/adc/pytest_adc.py @@ -12,6 +12,7 @@ from pytest_embedded_idf.utils import idf_parametrize ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c5', 'esp32p4', 'esp32c61'], indirect=['target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14357') def test_adc(dut: Dut) -> None: dut.run_all_single_board_cases(timeout=120, reset=True) @@ -30,3 +31,16 @@ def test_adc(dut: Dut) -> None: @idf_parametrize('target', ['esp32c2'], indirect=['target']) def test_adc_esp32c2_xtal_26mhz(dut: Dut) -> None: dut.run_all_single_board_cases(timeout=120, reset=True) + + +# P4 REV2 adc +@pytest.mark.adc +@pytest.mark.esp32p4_eco4 +@pytest.mark.parametrize('config', ['esp32p4_eco4'], indirect=True) +@idf_parametrize( + 'target', + ['esp32p4'], + indirect=['target'], +) +def test_adc_p4_rev2(dut: Dut) -> None: + dut.run_all_single_board_cases(timeout=120, reset=True) diff --git a/components/esp_adc/test_apps/adc/sdkconfig.ci.esp32p4_eco4 b/components/esp_adc/test_apps/adc/sdkconfig.ci.esp32p4_eco4 new file mode 100644 index 0000000000..2c6c907fab --- /dev/null +++ b/components/esp_adc/test_apps/adc/sdkconfig.ci.esp32p4_eco4 @@ -0,0 +1,2 @@ +CONFIG_IDF_TARGET="esp32p4" +CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y diff --git a/components/esp_common/test_apps/.build-test-rules.yml b/components/esp_common/test_apps/.build-test-rules.yml index eea2257c6a..6c909aef19 100644 --- a/components/esp_common/test_apps/.build-test-rules.yml +++ b/components/esp_common/test_apps/.build-test-rules.yml @@ -5,3 +5,6 @@ components/esp_common/test_apps/esp_common: - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1 - if: CONFIG_NAME == "psram_noinit" and SOC_SPIRAM_SUPPORTED != 1 - if: CONFIG_NAME == "xip_psram" and SOC_SPIRAM_XIP_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14404 diff --git a/components/esp_common/test_apps/esp_common/README.md b/components/esp_common/test_apps/esp_common/README.md index 44f3780f1d..7f28f609e6 100644 --- a/components/esp_common/test_apps/esp_common/README.md +++ b/components/esp_common/test_apps/esp_common/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | diff --git a/components/esp_driver_cam/test_apps/.build-test-rules.yml b/components/esp_driver_cam/test_apps/.build-test-rules.yml index 0d419e7609..6be395b4ec 100644 --- a/components/esp_driver_cam/test_apps/.build-test-rules.yml +++ b/components/esp_driver_cam/test_apps/.build-test-rules.yml @@ -1,6 +1,9 @@ components/esp_driver_cam/test_apps/csi: disable: - if: SOC_MIPI_CSI_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" # TODO: IDF-14358 + temporary: true + reason: p4 rev3 migration depends_components: - esp_driver_cam diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py b/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py index 174b3fae7f..1b9b211547 100644 --- a/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py @@ -21,6 +21,7 @@ def test_i2c(dut: Dut) -> None: @pytest.mark.generic_multi_device +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14395') @pytest.mark.parametrize( 'count, config', [ diff --git a/components/esp_driver_i2s/test_apps/.build-test-rules.yml b/components/esp_driver_i2s/test_apps/.build-test-rules.yml index 78e2a417f1..2d699e78db 100644 --- a/components/esp_driver_i2s/test_apps/.build-test-rules.yml +++ b/components/esp_driver_i2s/test_apps/.build-test-rules.yml @@ -12,7 +12,7 @@ components/esp_driver_i2s/test_apps/i2s_multi_dev: - if: SOC_I2S_SUPPORTED != 1 - if: SOC_I2S_HW_VERSION_2 != 1 disable_test: - - if: IDF_TARGET in ["esp32c61"] # TODO: [ESP32C61] IDF-11442 + - if: IDF_TARGET in ["esp32c61", "esp32p4"] # TODO: [ESP32C61] IDF-11442, TODO: IDF-14396 temporary: true reason: lack of runners depends_components: diff --git a/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py b/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py index d07ece199c..d0d94ae389 100644 --- a/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py +++ b/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py @@ -6,6 +6,7 @@ from pytest_embedded_idf.utils import soc_filtered_targets @pytest.mark.generic_multi_device +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14396') @pytest.mark.parametrize('count', [2], indirect=True) @idf_parametrize('target', soc_filtered_targets('SOC_I2S_SUPPORTS_TDM == 1'), indirect=['target']) def test_i2s_multi_dev(case_tester) -> None: # type: ignore diff --git a/components/esp_driver_i3c/test_apps/i3c_test_apps/pytest_i3c.py b/components/esp_driver_i3c/test_apps/i3c_test_apps/pytest_i3c.py index 670f670b1f..9dcefabb2d 100644 --- a/components/esp_driver_i3c/test_apps/i3c_test_apps/pytest_i3c.py +++ b/components/esp_driver_i3c/test_apps/i3c_test_apps/pytest_i3c.py @@ -21,6 +21,7 @@ def test_i3c(dut: Dut) -> None: @pytest.mark.generic_multi_device +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14397') @pytest.mark.parametrize( 'count, config', [ diff --git a/components/esp_driver_ledc/test_apps/.build-test-rules.yml b/components/esp_driver_ledc/test_apps/.build-test-rules.yml index 50e40b72c0..c9446e000a 100644 --- a/components/esp_driver_ledc/test_apps/.build-test-rules.yml +++ b/components/esp_driver_ledc/test_apps/.build-test-rules.yml @@ -3,5 +3,9 @@ components/esp_driver_ledc/test_apps/ledc: disable: - if: SOC_LEDC_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14398 depends_components: - esp_driver_ledc diff --git a/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py b/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py index 70d71e0826..42f19403bf 100644 --- a/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py +++ b/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py @@ -16,6 +16,7 @@ from pytest_embedded_idf.utils import idf_parametrize indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14398') def test_ledc(dut: IdfDut) -> None: dut.run_all_single_board_cases(reset=True) @@ -35,6 +36,7 @@ def test_ledc_psram(dut: IdfDut) -> None: @pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='s3 multi device runner has no psram') +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14398') @pytest.mark.generic_multi_device @pytest.mark.parametrize( 'count, config', diff --git a/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml b/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml index cbc941233c..85658d61ff 100644 --- a/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml +++ b/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml @@ -3,5 +3,9 @@ components/esp_driver_mcpwm/test_apps/mcpwm: disable: - if: SOC_MCPWM_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14412 depends_components: - esp_driver_mcpwm diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py b/components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py index 8d910fffa8..fc6313a7e2 100644 --- a/components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py @@ -15,5 +15,6 @@ from pytest_embedded_idf.utils import idf_parametrize indirect=True, ) @idf_parametrize('target', ['esp32', 'esp32s3', 'esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14412') def test_mcpwm(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_driver_parlio/test_apps/.build-test-rules.yml b/components/esp_driver_parlio/test_apps/.build-test-rules.yml index efce473ee7..f748dc7351 100644 --- a/components/esp_driver_parlio/test_apps/.build-test-rules.yml +++ b/components/esp_driver_parlio/test_apps/.build-test-rules.yml @@ -3,5 +3,9 @@ components/esp_driver_parlio/test_apps/parlio: disable: - if: SOC_PARLIO_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14413 depends_components: - esp_driver_parlio diff --git a/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py b/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py index b275afc55c..55b9dbb6c9 100644 --- a/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py +++ b/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py @@ -15,5 +15,6 @@ from pytest_embedded_idf.utils import idf_parametrize indirect=True, ) @idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14413') def test_parlio(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_driver_rmt/test_apps/.build-test-rules.yml b/components/esp_driver_rmt/test_apps/.build-test-rules.yml index 2a97c6cdec..b737b52f8f 100644 --- a/components/esp_driver_rmt/test_apps/.build-test-rules.yml +++ b/components/esp_driver_rmt/test_apps/.build-test-rules.yml @@ -3,5 +3,9 @@ components/esp_driver_rmt/test_apps/rmt: disable: - if: SOC_RMT_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14414 depends_components: - esp_driver_rmt diff --git a/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py b/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py index 4a9612aa79..1ef07f27e3 100644 --- a/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py +++ b/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py @@ -17,6 +17,7 @@ from pytest_embedded_idf.utils import idf_parametrize @idf_parametrize( 'target', ['esp32', 'esp32s2', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], indirect=['target'] ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14414') def test_rmt(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_driver_sdio/test_apps/.build-test-rules.yml b/components/esp_driver_sdio/test_apps/.build-test-rules.yml index 4b34b45429..7c2d3e4321 100644 --- a/components/esp_driver_sdio/test_apps/.build-test-rules.yml +++ b/components/esp_driver_sdio/test_apps/.build-test-rules.yml @@ -2,6 +2,10 @@ components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc: enable: - if: IDF_TARGET in ["esp32", "esp32p4"] reason: runners use ESP32 / ESP32P4 SDMMC as host + disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14359 depends_components: - sdmmc - esp_driver_sdmmc diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/README.md b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/README.md index cbe7d02b07..abb7f3c223 100644 --- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/README.md +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-P4 | -| ----------------- | ----- | -------- | +| Supported Targets | ESP32 | +| ----------------- | ----- | # SDIO Cross Chips Test Apps: SDMMC Host App diff --git a/components/esp_driver_sdspi/test_apps/.build-test-rules.yml b/components/esp_driver_sdspi/test_apps/.build-test-rules.yml index 57fdd2e11c..fdfaa7e107 100644 --- a/components/esp_driver_sdspi/test_apps/.build-test-rules.yml +++ b/components/esp_driver_sdspi/test_apps/.build-test-rules.yml @@ -1,6 +1,9 @@ components/esp_driver_sdspi/test_apps/sdspi: disable: - if: SOC_GPSPI_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14363 disable_test: - if: IDF_TARGET not in ["esp32", "esp32s3", "esp32c3", "esp32c5", "esp32p4"] reason: needs special runner, select few typical targets for testing diff --git a/components/esp_driver_sdspi/test_apps/sdspi/README.md b/components/esp_driver_sdspi/test_apps/sdspi/README.md index 44f3780f1d..7f28f609e6 100644 --- a/components/esp_driver_sdspi/test_apps/sdspi/README.md +++ b/components/esp_driver_sdspi/test_apps/sdspi/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | diff --git a/components/esp_driver_spi/test_apps/.build-test-rules.yml b/components/esp_driver_spi/test_apps/.build-test-rules.yml index 9b605ff855..15a8fc81b5 100644 --- a/components/esp_driver_spi/test_apps/.build-test-rules.yml +++ b/components/esp_driver_spi/test_apps/.build-test-rules.yml @@ -9,6 +9,10 @@ components/esp_driver_spi/test_apps/master: disable: - if: SOC_GPSPI_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14399 <<: *spi_depends_default components/esp_driver_spi/test_apps/param: diff --git a/components/esp_driver_spi/test_apps/master/pytest_spi_master.py b/components/esp_driver_spi/test_apps/master/pytest_spi_master.py index a141e21900..24b40d0dd9 100644 --- a/components/esp_driver_spi/test_apps/master/pytest_spi_master.py +++ b/components/esp_driver_spi/test_apps/master/pytest_spi_master.py @@ -14,6 +14,7 @@ from pytest_embedded_idf.utils import idf_parametrize indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14399') def test_master_single_dev(case_tester) -> None: # type: ignore for case in case_tester.test_menu: if 'test_env' in case.attributes: @@ -39,6 +40,7 @@ def test_master_esp_flash(case_tester) -> None: # type: ignore @pytest.mark.generic_multi_device +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14399') @pytest.mark.parametrize( 'count, config', [ diff --git a/components/esp_driver_spi/test_apps/param/pytest_spi_param.py b/components/esp_driver_spi/test_apps/param/pytest_spi_param.py index bd55a0ab78..5eb348b567 100644 --- a/components/esp_driver_spi/test_apps/param/pytest_spi_param.py +++ b/components/esp_driver_spi/test_apps/param/pytest_spi_param.py @@ -13,5 +13,6 @@ def test_param_single_dev(case_tester) -> None: # type: ignore @pytest.mark.generic_multi_device @pytest.mark.parametrize('count', [2], indirect=True) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14399') def test_param_multi_dev(case_tester) -> None: # type: ignore case_tester.run_all_multi_dev_cases(reset=True) diff --git a/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py b/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py index 0b0adc8cbb..cb22fca656 100644 --- a/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py +++ b/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py @@ -13,6 +13,7 @@ def test_slave_single_dev(case_tester) -> None: # type: ignore @pytest.mark.generic_multi_device @pytest.mark.parametrize('count, config', [(2, 'release'), (2, 'iram_safe')], indirect=True) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14399') @idf_parametrize('target', ['supported_targets'], indirect=['target']) def test_slave_multi_dev(case_tester) -> None: # type: ignore case_tester.run_all_multi_dev_cases(reset=True) diff --git a/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py b/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py index 3654ca7585..1965bdbdb9 100644 --- a/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py +++ b/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py @@ -15,6 +15,7 @@ def test_slave_hd_single_dev(case_tester) -> None: # type: ignore @pytest.mark.generic_multi_device @pytest.mark.parametrize('count, config', [(2, 'release')], indirect=True) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14399') @idf_parametrize('target', soc_filtered_targets('SOC_SPI_SUPPORT_SLAVE_HD_VER2 == 1'), indirect=['target']) def test_slave_hd_multi_dev(case_tester) -> None: # type: ignore case_tester.run_all_multi_dev_cases(reset=True) diff --git a/components/esp_driver_twai/test_apps/.build-test-rules.yml b/components/esp_driver_twai/test_apps/.build-test-rules.yml index 3cae20b47d..96a4646be0 100644 --- a/components/esp_driver_twai/test_apps/.build-test-rules.yml +++ b/components/esp_driver_twai/test_apps/.build-test-rules.yml @@ -1,5 +1,8 @@ components/esp_driver_twai/test_apps/test_twai: disable: - if: SOC_TWAI_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14393 depends_components: - esp_driver_twai diff --git a/components/esp_driver_twai/test_apps/test_twai/README.md b/components/esp_driver_twai/test_apps/test_twai/README.md index c3221d0779..d79d63dadf 100644 --- a/components/esp_driver_twai/test_apps/test_twai/README.md +++ b/components/esp_driver_twai/test_apps/test_twai/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | diff --git a/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml b/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml index dda2baa2e7..796eb4eaa0 100644 --- a/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml +++ b/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml @@ -3,6 +3,9 @@ components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag: disable: - if: SOC_USB_SERIAL_JTAG_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14364 disable_test: - if: IDF_TARGET in ["esp32c5", "esp32h4", "esp32h21"] temporary: true @@ -15,6 +18,9 @@ components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag: components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag_vfs: disable: - if: SOC_USB_SERIAL_JTAG_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14364 disable_test: - if: IDF_TARGET in ["esp32c5", "esp32h4", "esp32h21"] temporary: true diff --git a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/README.md b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/README.md index 1fd60c328e..f7cc913548 100644 --- a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/README.md +++ b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | diff --git a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag_vfs/README.md b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag_vfs/README.md index 1fd60c328e..f7cc913548 100644 --- a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag_vfs/README.md +++ b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag_vfs/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | diff --git a/components/esp_eth/test_apps/.build-test-rules.yml b/components/esp_eth/test_apps/.build-test-rules.yml index dc4d00c17b..3d07cc18a3 100644 --- a/components/esp_eth/test_apps/.build-test-rules.yml +++ b/components/esp_eth/test_apps/.build-test-rules.yml @@ -2,7 +2,7 @@ components/esp_eth/test_apps: enable: - - if: IDF_TARGET in ["esp32", "esp32p4"] + - if: IDF_TARGET in ["esp32"] # TODO: IDF-14365 reason: ESP32 and ESP32P4 have internal EMAC. SPI Ethernet runners are based on ESP32. depends_components: - esp_eth diff --git a/components/esp_eth/test_apps/README.md b/components/esp_eth/test_apps/README.md index 9747c000db..0e2cf8cb13 100644 --- a/components/esp_eth/test_apps/README.md +++ b/components/esp_eth/test_apps/README.md @@ -1,6 +1,6 @@ # EMAC Test -| Supported Targets | ESP32 | ESP32-P4 | -| ----------------- | ----- | -------- | +| Supported Targets | ESP32 | +| ----------------- | ----- | This test app is used to test Ethernet MAC behavior with different chips. diff --git a/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c b/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c index 02ea0f6c5f..eaabbcb419 100644 --- a/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c +++ b/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c @@ -387,6 +387,7 @@ static TCM_IRAM_ATTR void smp_core_do_retention(void) // Wait another core start to do retention bool smp_skip_retention = false; smp_retention_state_t another_core_state; + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-infinite-loop") while (1) { another_core_state = atomic_load(&s_smp_retention_state[!core_id]); if (another_core_state == SMP_SKIP_RETENTION) { @@ -397,6 +398,7 @@ static TCM_IRAM_ATTR void smp_core_do_retention(void) break; } } + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-infinite-loop") if (!smp_skip_retention) { atomic_store(&s_smp_retention_state[core_id], SMP_BACKUP_START); @@ -458,9 +460,11 @@ void sleep_smp_cpu_wakeup_prepare(void) #if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU uint8_t core_id = esp_cpu_get_core_id(); if (atomic_load(&s_smp_retention_state[core_id]) == SMP_RESTORE_DONE) { + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-infinite-loop") while (atomic_load(&s_smp_retention_state[!core_id]) != SMP_RESTORE_DONE) { ; } + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-infinite-loop") } atomic_store(&s_smp_retention_state[core_id], SMP_IDLE); #else diff --git a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support index f1d582651d..7a87e70b91 100644 --- a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support +++ b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support @@ -3,7 +3,7 @@ comment "Read the help text of the option below for explanation" config ESP32P4_SELECTS_REV_LESS_V3 bool "Select ESP32-P4 revisions <3.0 (No >=3.x Support)" - default y + default n help Select this option to support ESP32-P4 revisions 0.x and 1.x. Revisions higher than 3.0 (included) and revisions less than 3.0 diff --git a/components/esp_hw_support/test_apps/.build-test-rules.yml b/components/esp_hw_support/test_apps/.build-test-rules.yml index f7d56155f5..671cb1ff69 100644 --- a/components/esp_hw_support/test_apps/.build-test-rules.yml +++ b/components/esp_hw_support/test_apps/.build-test-rules.yml @@ -13,6 +13,10 @@ components/esp_hw_support/test_apps/dma: components/esp_hw_support/test_apps/dma2d: disable: - if: SOC_DMA2D_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14471 depends_filepatterns: - components/esp_hw_support/dma/**/* depends_components: @@ -25,6 +29,9 @@ components/esp_hw_support/test_apps/host_test_linux: components/esp_hw_support/test_apps/mspi: disable: - if: IDF_TARGET not in ["esp32s3", "esp32p4"] + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14366 components/esp_hw_support/test_apps/mspi_psram_with_dfs: disable: @@ -37,6 +44,10 @@ components/esp_hw_support/test_apps/rtc_8md256: components/esp_hw_support/test_apps/rtc_clk: disable: - if: SOC_CLK_TREE_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14441 components/esp_hw_support/test_apps/rtc_power_modes: enable: @@ -65,11 +76,14 @@ components/esp_hw_support/test_apps/usb_phy: components/esp_hw_support/test_apps/vad_wakeup: disable: - if: SOC_LP_VAD_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14368 components/esp_hw_support/test_apps/wakeup_tests: enable: - if: SOC_DEEP_SLEEP_SUPPORTED == 1 and SOC_LIGHT_SLEEP_SUPPORTED == 1 disable_test: - - if: IDF_TARGET in ["esp32c61", "esp32h21", "esp32h4"] + - if: IDF_TARGET in ["esp32c61", "esp32h21", "esp32h4", "esp32p4"] temporary: true - reason: lack of runners + reason: lack of runners # TODO: IDF-14400 diff --git a/components/esp_hw_support/test_apps/dma2d/pytest_dma2d.py b/components/esp_hw_support/test_apps/dma2d/pytest_dma2d.py index 8f02215a63..e6b4ca263f 100644 --- a/components/esp_hw_support/test_apps/dma2d/pytest_dma2d.py +++ b/components/esp_hw_support/test_apps/dma2d/pytest_dma2d.py @@ -15,5 +15,6 @@ from pytest_embedded_idf.utils import soc_filtered_targets indirect=True, ) @idf_parametrize('target', soc_filtered_targets('SOC_DMA2D_SUPPORTED == 1'), indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14471') def test_dma2d(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_hw_support/test_apps/mspi/README.md b/components/esp_hw_support/test_apps/mspi/README.md index 3a9d77fcb9..3677101481 100644 --- a/components/esp_hw_support/test_apps/mspi/README.md +++ b/components/esp_hw_support/test_apps/mspi/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-P4 | ESP32-S3 | -| ----------------- | -------- | -------- | +| Supported Targets | ESP32-S3 | +| ----------------- | -------- | This project tests if Flash and PSRAM can work under different configurations. To add new configuration, create one more sdkconfig.ci.NAME file in this directory. diff --git a/components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py b/components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py index bd3bb67f91..5597c11ba6 100644 --- a/components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py +++ b/components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py @@ -10,6 +10,7 @@ from pytest_embedded_idf.utils import soc_filtered_targets @pytest.mark.generic @idf_parametrize('target', soc_filtered_targets('SOC_CLK_TREE_SUPPORTED == 1'), indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14441') def test_rtc_clk(case_tester: CaseTester) -> None: for case in case_tester.test_menu: if 'test_env' in case.attributes: diff --git a/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py b/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py index 3560100cc7..d4ec93a77f 100644 --- a/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py +++ b/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py @@ -1,7 +1,6 @@ # SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 from time import sleep -from typing import Tuple import pytest from pytest_embedded_idf.dut import IdfDut @@ -40,6 +39,7 @@ available_rtcio_nums = { @pytest.mark.generic_multi_device +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14400') @pytest.mark.parametrize('count', [2], indirect=True) @pytest.mark.parametrize('config', TEST_CONFIGS, indirect=True) @idf_parametrize( @@ -47,7 +47,7 @@ available_rtcio_nums = { ['esp32', 'esp32s2', 'esp32s3', 'esp32c6', 'esp32h2', 'esp32p4', 'esp32c5'], indirect=['target'], ) -def test_ext1_deepsleep(dut: Tuple[IdfDut, IdfDut]) -> None: +def test_ext1_deepsleep(dut: tuple[IdfDut, IdfDut]) -> None: wakee = dut[0] waker = dut[1] @@ -97,8 +97,9 @@ def test_ext1_deepsleep(dut: Tuple[IdfDut, IdfDut]) -> None: @pytest.mark.generic_multi_device @pytest.mark.parametrize('count', [2], indirect=True) @pytest.mark.parametrize('config', TEST_CONFIGS, indirect=True) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14400') @idf_parametrize('target', ['esp32c2', 'esp32c3', 'esp32c6', 'esp32p4', 'esp32c5'], indirect=['target']) -def test_rtcio_deepsleep(dut: Tuple[IdfDut, IdfDut]) -> None: +def test_rtcio_deepsleep(dut: tuple[IdfDut, IdfDut]) -> None: wakee = dut[0] waker = dut[1] @@ -142,8 +143,9 @@ def test_rtcio_deepsleep(dut: Tuple[IdfDut, IdfDut]) -> None: @pytest.mark.generic_multi_device @pytest.mark.parametrize('count', [2], indirect=True) @pytest.mark.parametrize('config', TEST_CONFIGS, indirect=True) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14400') @idf_parametrize('target', ['supported_targets'], indirect=['target']) -def test_gpio_wakeup_enable_lightsleep(dut: Tuple[IdfDut, IdfDut]) -> None: +def test_gpio_wakeup_enable_lightsleep(dut: tuple[IdfDut, IdfDut]) -> None: wakee = dut[0] waker = dut[1] diff --git a/components/esp_libc/test_apps/.build-test-rules.yml b/components/esp_libc/test_apps/.build-test-rules.yml index 6f79760bde..37507a6cfe 100644 --- a/components/esp_libc/test_apps/.build-test-rules.yml +++ b/components/esp_libc/test_apps/.build-test-rules.yml @@ -1,5 +1,11 @@ # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps +components/esp_libc/test_apps/newlib: + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14415 + components/esp_libc/test_apps/no_rvfplib: disable: - if: ESP_ROM_HAS_RVFPLIB != 1 diff --git a/components/esp_libc/test_apps/newlib/pytest_newlib.py b/components/esp_libc/test_apps/newlib/pytest_newlib.py index 96d5e4ac1c..de750e938b 100644 --- a/components/esp_libc/test_apps/newlib/pytest_newlib.py +++ b/components/esp_libc/test_apps/newlib/pytest_newlib.py @@ -20,5 +20,6 @@ from pytest_embedded_idf.utils import idf_parametrize ], indirect=['config', 'target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14415') def test_newlib(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_mm/test_apps/.build-test-rules.yml b/components/esp_mm/test_apps/.build-test-rules.yml new file mode 100644 index 0000000000..a879b36b54 --- /dev/null +++ b/components/esp_mm/test_apps/.build-test-rules.yml @@ -0,0 +1,7 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/esp_mm/test_apps/mm: + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14470 diff --git a/components/esp_mm/test_apps/mm/pytest_mmap.py b/components/esp_mm/test_apps/mm/pytest_mmap.py index 134dff6b8a..fbf9db982f 100644 --- a/components/esp_mm/test_apps/mm/pytest_mmap.py +++ b/components/esp_mm/test_apps/mm/pytest_mmap.py @@ -71,6 +71,7 @@ def test_cache(dut: Dut) -> None: ], indirect=['config', 'target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='h4 rev3 migration # TODO: IDF-14470') def test_cache_psram(dut: Dut) -> None: dut.run_all_single_board_cases(group='cache') diff --git a/components/esp_netif/test_apps/.build-test-rules.yml b/components/esp_netif/test_apps/.build-test-rules.yml index 7baad88301..9e37eaeb54 100644 --- a/components/esp_netif/test_apps/.build-test-rules.yml +++ b/components/esp_netif/test_apps/.build-test-rules.yml @@ -13,7 +13,7 @@ components/esp_netif/test_apps/test_app_esp_netif: components/esp_netif/test_apps/test_app_vfs_l2tap: disable: - - if: IDF_TARGET not in ["esp32", "esp32p4"] + - if: IDF_TARGET not in ["esp32"] # TODO: IDF-14365 temporary: true reason: Not needed to test on all targets (chosen two, one for each architecture plus P4 tests time stamping) depends_components: diff --git a/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md b/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md index 4873c15b15..f708a1985a 100644 --- a/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md +++ b/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-P4 | -| ----------------- | ----- | -------- | +| Supported Targets | ESP32 | +| ----------------- | ----- | diff --git a/components/esp_pm/test_apps/.build-test-rules.yml b/components/esp_pm/test_apps/.build-test-rules.yml index 22379b9328..6a59d41af7 100644 --- a/components/esp_pm/test_apps/.build-test-rules.yml +++ b/components/esp_pm/test_apps/.build-test-rules.yml @@ -8,5 +8,9 @@ components/esp_pm/test_apps: - if: IDF_TARGET in ["esp32c61", "esp32h21", "esp32h4"] temporary: true reason: not support yet # TODO: [ESP32C61] IDF-9250, [ESP32H21] IDF-11522, [ESP32H4] IDF-12286 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14416 depends_components: - esp_pm diff --git a/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py b/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py index 2cd49b5884..b8f96b6f9c 100644 --- a/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py +++ b/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py @@ -18,6 +18,7 @@ from pytest_embedded_idf.utils import idf_parametrize indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14416') def test_esp_pm(dut: Dut) -> None: dut.run_all_single_board_cases() @@ -53,5 +54,6 @@ def test_esp_attr_xip_psram_esp32s3(dut: Dut) -> None: ['pm_pd_top_sleep'], ) @idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14416') def test_esp_pd_top_and_cpu_sleep(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_rom/test_apps/.build-test-rules.yml b/components/esp_rom/test_apps/.build-test-rules.yml index 7d6745313d..8365d06340 100644 --- a/components/esp_rom/test_apps/.build-test-rules.yml +++ b/components/esp_rom/test_apps/.build-test-rules.yml @@ -10,6 +10,10 @@ components/esp_rom/test_apps/rom_impl_components: - if: CONFIG_NAME == "rom_impl_components" and ((ESP_ROM_HAS_HAL_WDT != 1 and ESP_ROM_HAS_HAL_SYSTIMER != 1) and (ESP_ROM_HAS_HEAP_TLSF != 1 and ESP_ROM_HAS_SPI_FLASH != 1)) - if: CONFIG_NAME == "no_rom_impl_components" and ((ESP_ROM_HAS_HAL_WDT != 1 and ESP_ROM_HAS_HAL_SYSTIMER != 1) and (ESP_ROM_HAS_HEAP_TLSF != 1 and ESP_ROM_HAS_SPI_FLASH != 1)) - if: SOC_WDT_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14417 components/esp_rom/test_apps/rom_tests: disable_test: diff --git a/components/esp_rom/test_apps/rom_impl_components/pytest_esp_rom_impl_components.py b/components/esp_rom/test_apps/rom_impl_components/pytest_esp_rom_impl_components.py index 4efbe677c0..be167655ba 100644 --- a/components/esp_rom/test_apps/rom_impl_components/pytest_esp_rom_impl_components.py +++ b/components/esp_rom/test_apps/rom_impl_components/pytest_esp_rom_impl_components.py @@ -15,5 +15,6 @@ from pytest_embedded_idf.utils import idf_parametrize indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14417') def test_esp_rom_impl_components(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_security/test_apps/.build-test-rules.yml b/components/esp_security/test_apps/.build-test-rules.yml index 6802faf753..5a6cdf0da0 100644 --- a/components/esp_security/test_apps/.build-test-rules.yml +++ b/components/esp_security/test_apps/.build-test-rules.yml @@ -3,5 +3,9 @@ components/esp_security/test_apps/crypto_drivers: enable: - if: ((SOC_HMAC_SUPPORTED == 1) or (SOC_DIG_SIGN_SUPPORTED == 1)) or (SOC_KEY_MANAGER_SUPPORTED == 1) + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14418 depends_components: - esp_security diff --git a/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py b/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py index 8e697da9af..59dc1fdf66 100644 --- a/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py +++ b/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py @@ -9,5 +9,6 @@ from pytest_embedded_idf.utils import idf_parametrize @idf_parametrize( 'target', ['esp32s2', 'esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32p4', 'esp32c5'], indirect=['target'] ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14418') def test_crypto_drivers(dut: Dut) -> None: dut.run_all_single_board_cases(timeout=180) diff --git a/components/esp_stdio/test_apps/.build-test-rules.yml b/components/esp_stdio/test_apps/.build-test-rules.yml index 2aa7e0fb88..e963d326d1 100644 --- a/components/esp_stdio/test_apps/.build-test-rules.yml +++ b/components/esp_stdio/test_apps/.build-test-rules.yml @@ -4,5 +4,6 @@ components/esp_stdio/test_apps/stdio: - if: CONFIG_NAME == "serial_jtag_only" and SOC_USB_SERIAL_JTAG_SUPPORTED != 1 - if: CONFIG_NAME == "serial_jtag_only_no_vfs" and SOC_USB_SERIAL_JTAG_SUPPORTED != 1 - if: CONFIG_NAME == "stdio_no_vfs" and SOC_USB_SERIAL_JTAG_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" # TODO: IDF-14364 disable_test: - if: CONFIG_NAME == "simple" and IDF_TARGET != "esp32" diff --git a/components/esp_stdio/test_apps/stdio/README.md b/components/esp_stdio/test_apps/stdio/README.md index 44f3780f1d..7f28f609e6 100644 --- a/components/esp_stdio/test_apps/stdio/README.md +++ b/components/esp_stdio/test_apps/stdio/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | diff --git a/components/esp_system/ld/esp32p4/memory.ld.in b/components/esp_system/ld/esp32p4/memory.ld.in index 107b00d98b..4154b9369a 100644 --- a/components/esp_system/ld/esp32p4/memory.ld.in +++ b/components/esp_system/ld/esp32p4/memory.ld.in @@ -142,15 +142,22 @@ REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg ); #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS REGION_ALIAS("text_seg_low", irom_seg); #else +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 REGION_ALIAS("text_seg_low", sram_low); - REGION_ALIAS("text_seg_high", sram_high); +#else + REGION_ALIAS("text_seg_low", sram_seg); +#endif //CONFIG_ESP32P4_SELECTS_REV_LESS_V3 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS REGION_ALIAS("rodata_seg_low", drom_seg); #else +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 REGION_ALIAS("rodata_seg_low", sram_low); REGION_ALIAS("rodata_seg_high", sram_high); +#else + REGION_ALIAS("rodata_seg_low", sram_seg); +#endif //CONFIG_ESP32P4_SELECTS_REV_LESS_V3 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS #if CONFIG_SPIRAM_XIP_FROM_PSRAM diff --git a/components/esp_system/test_apps/.build-test-rules.yml b/components/esp_system/test_apps/.build-test-rules.yml index 7fe49e38be..03fb8cb986 100644 --- a/components/esp_system/test_apps/.build-test-rules.yml +++ b/components/esp_system/test_apps/.build-test-rules.yml @@ -8,6 +8,10 @@ components/esp_system/test_apps/esp_system_unity_tests: disable: - if: (CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1) - if: (CONFIG_NAME == "psram_with_pd_top" and (SOC_SPIRAM_SUPPORTED != 1 or SOC_PM_SUPPORT_TOP_PD != 1)) + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14419 components/esp_system/test_apps/linux_apis: enable: diff --git a/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py b/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py index 9882eb7ef0..01677562cc 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py +++ b/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py @@ -21,6 +21,7 @@ from pytest_embedded_idf.utils import soc_filtered_targets ], indirect=['config', 'target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14419') def test_esp_system(dut: Dut) -> None: # esp32p4 32MB PSRAM initialize in startup takes more than 30 sec dut.run_all_single_board_cases(timeout=60) @@ -29,6 +30,7 @@ def test_esp_system(dut: Dut) -> None: @pytest.mark.generic @idf_parametrize('config', ['default'], indirect=['config']) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14419') def test_stack_smash_protection(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') dut.write('"stack smashing protection"') diff --git a/components/esp_timer/test_apps/.build-test-rules.yml b/components/esp_timer/test_apps/.build-test-rules.yml index b62f794ee4..027881f6be 100644 --- a/components/esp_timer/test_apps/.build-test-rules.yml +++ b/components/esp_timer/test_apps/.build-test-rules.yml @@ -4,3 +4,7 @@ components/esp_timer/test_apps: disable: - if: CONFIG_NAME == "dfs" and SOC_CLK_XTAL32K_SUPPORTED != 1 reason: The test requires the XTAL32K clock to measure the esp_timer timing accuracy + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14420 diff --git a/components/esp_timer/test_apps/pytest_esp_timer_ut.py b/components/esp_timer/test_apps/pytest_esp_timer_ut.py index 1c3c991fbe..2ab8928b19 100644 --- a/components/esp_timer/test_apps/pytest_esp_timer_ut.py +++ b/components/esp_timer/test_apps/pytest_esp_timer_ut.py @@ -22,6 +22,7 @@ from pytest_embedded_idf.utils import idf_parametrize ], indirect=['config', 'target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14420') def test_esp_timer(dut: Dut) -> None: dut.run_all_single_board_cases(timeout=120) @@ -36,6 +37,7 @@ def test_esp_timer(dut: Dut) -> None: indirect=True, ) @idf_parametrize('target', ['esp32'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14420') def test_esp_timer_psram(dut: Dut) -> None: dut.run_all_single_board_cases(timeout=120) diff --git a/components/freertos/test_apps/.build-test-rules.yml b/components/freertos/test_apps/.build-test-rules.yml index 5f04e72ac7..7c83c8e104 100644 --- a/components/freertos/test_apps/.build-test-rules.yml +++ b/components/freertos/test_apps/.build-test-rules.yml @@ -8,8 +8,13 @@ components/freertos/test_apps/build_tests/orig_inc_path: enable: - if: IDF_TARGET in ["esp32"] reason: The feature only depends on the build system, nothing target-specific that needs to be tested + components/freertos/test_apps/freertos: disable: - if: CONFIG_NAME == "smp" and IDF_TARGET == "esp32p4" temporary: true reason: target(s) not supported yet + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14421 diff --git a/components/freertos/test_apps/freertos/pytest_freertos.py b/components/freertos/test_apps/freertos/pytest_freertos.py index 81ba168122..8df27ba877 100644 --- a/components/freertos/test_apps/freertos/pytest_freertos.py +++ b/components/freertos/test_apps/freertos/pytest_freertos.py @@ -9,9 +9,21 @@ from pytest_embedded_idf.utils import idf_parametrize @idf_parametrize( 'config,target,markers', [ - ('default', 'supported_targets'), - ('freertos_options', 'supported_targets'), - ('tickless_idle', 'supported_targets'), + ( + 'default', + 'supported_targets', + (pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421'),), + ), + ( + 'freertos_options', + 'supported_targets', + (pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421'),), + ), + ( + 'tickless_idle', + 'supported_targets', + (pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421'),), + ), ('psram', 'esp32'), ('psram', 'esp32c5'), ('psram', 'esp32p4'), @@ -52,6 +64,7 @@ def test_freertos_flash_auto_suspend(dut: Dut) -> None: @pytest.mark.generic @pytest.mark.parametrize('config', ['freertos_options'], indirect=True) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421') def test_task_notify_too_high_index_fails(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests.') dut.write('"Notify too high index fails"') @@ -63,6 +76,7 @@ def test_task_notify_too_high_index_fails(dut: Dut) -> None: @pytest.mark.generic @pytest.mark.parametrize('config', ['freertos_options'], indirect=True) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421') def test_task_notify_wait_too_high_index_fails(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests.') dut.write('"Notify Wait too high index fails"') @@ -74,6 +88,7 @@ def test_task_notify_wait_too_high_index_fails(dut: Dut) -> None: @pytest.mark.generic @pytest.mark.parametrize('config', ['default'], indirect=True) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421') def test_port_must_assert_in_isr(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests.') dut.write('"port must assert if in ISR context"') diff --git a/components/mbedtls/test_apps/.build-test-rules.yml b/components/mbedtls/test_apps/.build-test-rules.yml index 5c97f3c763..0855b0b85d 100644 --- a/components/mbedtls/test_apps/.build-test-rules.yml +++ b/components/mbedtls/test_apps/.build-test-rules.yml @@ -6,6 +6,9 @@ components/mbedtls/test_apps: - if: CONFIG_NAME == "psram_all_ext" and SOC_SPIRAM_SUPPORTED != 1 - if: CONFIG_NAME == "ecdsa_sign" and SOC_ECDSA_SUPPORTED != 1 - if: CONFIG_NAME == "psram_all_ext_flash_enc" and SOC_SPIRAM_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14367 disable_test: - if: CONFIG_NAME == "psram_all_ext_flash_enc" and IDF_TARGET not in ["esp32"] reason: lack of runners diff --git a/components/mbedtls/test_apps/README.md b/components/mbedtls/test_apps/README.md index 44f3780f1d..7f28f609e6 100644 --- a/components/mbedtls/test_apps/README.md +++ b/components/mbedtls/test_apps/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | diff --git a/components/pthread/test_apps/pthread_unity_tests/pytest_pthread_unity_tests.py b/components/pthread/test_apps/pthread_unity_tests/pytest_pthread_unity_tests.py index 5e6aba09c9..2cf9732abd 100644 --- a/components/pthread/test_apps/pthread_unity_tests/pytest_pthread_unity_tests.py +++ b/components/pthread/test_apps/pthread_unity_tests/pytest_pthread_unity_tests.py @@ -14,6 +14,7 @@ from pytest_embedded_idf.utils import idf_parametrize indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421') def test_pthread(dut: Dut) -> None: dut.run_all_single_board_cases(group='!thread-specific', timeout=300) diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h index e7b75d50a4..6545f51a1f 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h @@ -11,1183 +11,1183 @@ extern "C" { #endif -/** I2C_SCL_LOW_PERIOD_REG register +/** LP_I2C_SCL_LOW_PERIOD_REG register * Configures the low level width of the SCL * Clock */ -#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0) -/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SCL_LOW_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x0) +/** LP_I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; * This register is used to configure for how long SCL remains low in master mode, in * I2C module clock cycles. */ -#define I2C_SCL_LOW_PERIOD 0x000001FFU -#define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) -#define I2C_SCL_LOW_PERIOD_V 0x000001FFU -#define I2C_SCL_LOW_PERIOD_S 0 +#define LP_I2C_SCL_LOW_PERIOD 0x000001FFU +#define LP_I2C_SCL_LOW_PERIOD_M (LP_I2C_SCL_LOW_PERIOD_V << LP_I2C_SCL_LOW_PERIOD_S) +#define LP_I2C_SCL_LOW_PERIOD_V 0x000001FFU +#define LP_I2C_SCL_LOW_PERIOD_S 0 -/** I2C_CTR_REG register +/** LP_I2C_CTR_REG register * Transmission setting */ -#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4) -/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; +#define LP_I2C_CTR_REG (DR_REG_LP_I2C_BASE + 0x4) +/** LP_I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; * This register is used to select the sample mode.1: sample SDA data on the SCL low * level.0: sample SDA data on the SCL high level. */ -#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) -#define I2C_SAMPLE_SCL_LEVEL_V 0x00000001U -#define I2C_SAMPLE_SCL_LEVEL_S 2 -/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; +#define LP_I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define LP_I2C_SAMPLE_SCL_LEVEL_M (LP_I2C_SAMPLE_SCL_LEVEL_V << LP_I2C_SAMPLE_SCL_LEVEL_S) +#define LP_I2C_SAMPLE_SCL_LEVEL_V 0x00000001U +#define LP_I2C_SAMPLE_SCL_LEVEL_S 2 +/** LP_I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; * This register is used to configure the ACK value that need to sent by master when * the rx_fifo_cnt has reached the threshold. */ -#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) -#define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) -#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U -#define I2C_RX_FULL_ACK_LEVEL_S 3 -/** I2C_TRANS_START : WT; bitpos: [5]; default: 0; +#define LP_I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define LP_I2C_RX_FULL_ACK_LEVEL_M (LP_I2C_RX_FULL_ACK_LEVEL_V << LP_I2C_RX_FULL_ACK_LEVEL_S) +#define LP_I2C_RX_FULL_ACK_LEVEL_V 0x00000001U +#define LP_I2C_RX_FULL_ACK_LEVEL_S 3 +/** LP_I2C_TRANS_START : WT; bitpos: [5]; default: 0; * Set this bit to start sending the data in txfifo. */ -#define I2C_TRANS_START (BIT(5)) -#define I2C_TRANS_START_M (I2C_TRANS_START_V << I2C_TRANS_START_S) -#define I2C_TRANS_START_V 0x00000001U -#define I2C_TRANS_START_S 5 -/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; +#define LP_I2C_TRANS_START (BIT(5)) +#define LP_I2C_TRANS_START_M (LP_I2C_TRANS_START_V << LP_I2C_TRANS_START_S) +#define LP_I2C_TRANS_START_V 0x00000001U +#define LP_I2C_TRANS_START_S 5 +/** LP_I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; * This bit is used to control the sending mode for data needing to be sent. 1: send * data from the least significant bit,0: send data from the most significant bit. */ -#define I2C_TX_LSB_FIRST (BIT(6)) -#define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) -#define I2C_TX_LSB_FIRST_V 0x00000001U -#define I2C_TX_LSB_FIRST_S 6 -/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; +#define LP_I2C_TX_LSB_FIRST (BIT(6)) +#define LP_I2C_TX_LSB_FIRST_M (LP_I2C_TX_LSB_FIRST_V << LP_I2C_TX_LSB_FIRST_S) +#define LP_I2C_TX_LSB_FIRST_V 0x00000001U +#define LP_I2C_TX_LSB_FIRST_S 6 +/** LP_I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; * This bit is used to control the storage mode for received data.1: receive data from * the least significant bit,0: receive data from the most significant bit. */ -#define I2C_RX_LSB_FIRST (BIT(7)) -#define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) -#define I2C_RX_LSB_FIRST_V 0x00000001U -#define I2C_RX_LSB_FIRST_S 7 -/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; +#define LP_I2C_RX_LSB_FIRST (BIT(7)) +#define LP_I2C_RX_LSB_FIRST_M (LP_I2C_RX_LSB_FIRST_V << LP_I2C_RX_LSB_FIRST_S) +#define LP_I2C_RX_LSB_FIRST_V 0x00000001U +#define LP_I2C_RX_LSB_FIRST_S 7 +/** LP_I2C_CLK_EN : R/W; bitpos: [8]; default: 0; * Reserved */ -#define I2C_CLK_EN (BIT(8)) -#define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) -#define I2C_CLK_EN_V 0x00000001U -#define I2C_CLK_EN_S 8 -/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; +#define LP_I2C_CLK_EN (BIT(8)) +#define LP_I2C_CLK_EN_M (LP_I2C_CLK_EN_V << LP_I2C_CLK_EN_S) +#define LP_I2C_CLK_EN_V 0x00000001U +#define LP_I2C_CLK_EN_S 8 +/** LP_I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; * This is the enable bit for arbitration_lost. */ -#define I2C_ARBITRATION_EN (BIT(9)) -#define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) -#define I2C_ARBITRATION_EN_V 0x00000001U -#define I2C_ARBITRATION_EN_S 9 -/** I2C_FSM_RST : WT; bitpos: [10]; default: 0; +#define LP_I2C_ARBITRATION_EN (BIT(9)) +#define LP_I2C_ARBITRATION_EN_M (LP_I2C_ARBITRATION_EN_V << LP_I2C_ARBITRATION_EN_S) +#define LP_I2C_ARBITRATION_EN_V 0x00000001U +#define LP_I2C_ARBITRATION_EN_S 9 +/** LP_I2C_FSM_RST : WT; bitpos: [10]; default: 0; * This register is used to reset the scl FMS. */ -#define I2C_FSM_RST (BIT(10)) -#define I2C_FSM_RST_M (I2C_FSM_RST_V << I2C_FSM_RST_S) -#define I2C_FSM_RST_V 0x00000001U -#define I2C_FSM_RST_S 10 -/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; +#define LP_I2C_FSM_RST (BIT(10)) +#define LP_I2C_FSM_RST_M (LP_I2C_FSM_RST_V << LP_I2C_FSM_RST_S) +#define LP_I2C_FSM_RST_V 0x00000001U +#define LP_I2C_FSM_RST_S 10 +/** LP_I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; * synchronization bit */ -#define I2C_CONF_UPGATE (BIT(11)) -#define I2C_CONF_UPGATE_M (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S) -#define I2C_CONF_UPGATE_V 0x00000001U -#define I2C_CONF_UPGATE_S 11 +#define LP_I2C_CONF_UPGATE (BIT(11)) +#define LP_I2C_CONF_UPGATE_M (LP_I2C_CONF_UPGATE_V << LP_I2C_CONF_UPGATE_S) +#define LP_I2C_CONF_UPGATE_V 0x00000001U +#define LP_I2C_CONF_UPGATE_S 11 -/** I2C_SR_REG register +/** LP_I2C_SR_REG register * Describe I2C work status. */ -#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8) -/** I2C_RESP_REC : RO; bitpos: [0]; default: 0; +#define LP_I2C_SR_REG (DR_REG_LP_I2C_BASE + 0x8) +/** LP_I2C_RESP_REC : RO; bitpos: [0]; default: 0; * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. */ -#define I2C_RESP_REC (BIT(0)) -#define I2C_RESP_REC_M (I2C_RESP_REC_V << I2C_RESP_REC_S) -#define I2C_RESP_REC_V 0x00000001U -#define I2C_RESP_REC_S 0 -/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; +#define LP_I2C_RESP_REC (BIT(0)) +#define LP_I2C_RESP_REC_M (LP_I2C_RESP_REC_V << LP_I2C_RESP_REC_S) +#define LP_I2C_RESP_REC_V 0x00000001U +#define LP_I2C_RESP_REC_S 0 +/** LP_I2C_ARB_LOST : RO; bitpos: [3]; default: 0; * When the I2C controller loses control of SCL line, this register changes to 1. */ -#define I2C_ARB_LOST (BIT(3)) -#define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) -#define I2C_ARB_LOST_V 0x00000001U -#define I2C_ARB_LOST_S 3 -/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; +#define LP_I2C_ARB_LOST (BIT(3)) +#define LP_I2C_ARB_LOST_M (LP_I2C_ARB_LOST_V << LP_I2C_ARB_LOST_S) +#define LP_I2C_ARB_LOST_V 0x00000001U +#define LP_I2C_ARB_LOST_S 3 +/** LP_I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. */ -#define I2C_BUS_BUSY (BIT(4)) -#define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) -#define I2C_BUS_BUSY_V 0x00000001U -#define I2C_BUS_BUSY_S 4 -/** I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0; +#define LP_I2C_BUS_BUSY (BIT(4)) +#define LP_I2C_BUS_BUSY_M (LP_I2C_BUS_BUSY_V << LP_I2C_BUS_BUSY_S) +#define LP_I2C_BUS_BUSY_V 0x00000001U +#define LP_I2C_BUS_BUSY_S 4 +/** LP_I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0; * This field represents the amount of data needed to be sent. */ -#define I2C_RXFIFO_CNT 0x0000001FU -#define I2C_RXFIFO_CNT_M (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S) -#define I2C_RXFIFO_CNT_V 0x0000001FU -#define I2C_RXFIFO_CNT_S 8 -/** I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0; +#define LP_I2C_RXFIFO_CNT 0x0000001FU +#define LP_I2C_RXFIFO_CNT_M (LP_I2C_RXFIFO_CNT_V << LP_I2C_RXFIFO_CNT_S) +#define LP_I2C_RXFIFO_CNT_V 0x0000001FU +#define LP_I2C_RXFIFO_CNT_S 8 +/** LP_I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0; * This field stores the amount of received data in RAM. */ -#define I2C_TXFIFO_CNT 0x0000001FU -#define I2C_TXFIFO_CNT_M (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S) -#define I2C_TXFIFO_CNT_V 0x0000001FU -#define I2C_TXFIFO_CNT_S 18 -/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; +#define LP_I2C_TXFIFO_CNT 0x0000001FU +#define LP_I2C_TXFIFO_CNT_M (LP_I2C_TXFIFO_CNT_V << LP_I2C_TXFIFO_CNT_S) +#define LP_I2C_TXFIFO_CNT_V 0x0000001FU +#define LP_I2C_TXFIFO_CNT_S 18 +/** LP_I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; * This field indicates the states of the I2C module state machine. 0: Idle, 1: * Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK */ -#define I2C_SCL_MAIN_STATE_LAST 0x00000007U -#define I2C_SCL_MAIN_STATE_LAST_M (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S) -#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U -#define I2C_SCL_MAIN_STATE_LAST_S 24 -/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; +#define LP_I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define LP_I2C_SCL_MAIN_STATE_LAST_M (LP_I2C_SCL_MAIN_STATE_LAST_V << LP_I2C_SCL_MAIN_STATE_LAST_S) +#define LP_I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define LP_I2C_SCL_MAIN_STATE_LAST_S 24 +/** LP_I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; * This field indicates the states of the state machine used to produce SCL.0: Idle, * 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop */ -#define I2C_SCL_STATE_LAST 0x00000007U -#define I2C_SCL_STATE_LAST_M (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S) -#define I2C_SCL_STATE_LAST_V 0x00000007U -#define I2C_SCL_STATE_LAST_S 28 +#define LP_I2C_SCL_STATE_LAST 0x00000007U +#define LP_I2C_SCL_STATE_LAST_M (LP_I2C_SCL_STATE_LAST_V << LP_I2C_SCL_STATE_LAST_S) +#define LP_I2C_SCL_STATE_LAST_V 0x00000007U +#define LP_I2C_SCL_STATE_LAST_S 28 -/** I2C_TO_REG register +/** LP_I2C_TO_REG register * Setting time out control for receiving data. */ -#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc) -/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; +#define LP_I2C_TO_REG (DR_REG_LP_I2C_BASE + 0xc) +/** LP_I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; * This register is used to configure the timeout for receiving a data bit in APBclock * cycles. */ -#define I2C_TIME_OUT_VALUE 0x0000001FU -#define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) -#define I2C_TIME_OUT_VALUE_V 0x0000001FU -#define I2C_TIME_OUT_VALUE_S 0 -/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; +#define LP_I2C_TIME_OUT_VALUE 0x0000001FU +#define LP_I2C_TIME_OUT_VALUE_M (LP_I2C_TIME_OUT_VALUE_V << LP_I2C_TIME_OUT_VALUE_S) +#define LP_I2C_TIME_OUT_VALUE_V 0x0000001FU +#define LP_I2C_TIME_OUT_VALUE_S 0 +/** LP_I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; * This is the enable bit for time out control. */ -#define I2C_TIME_OUT_EN (BIT(5)) -#define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) -#define I2C_TIME_OUT_EN_V 0x00000001U -#define I2C_TIME_OUT_EN_S 5 +#define LP_I2C_TIME_OUT_EN (BIT(5)) +#define LP_I2C_TIME_OUT_EN_M (LP_I2C_TIME_OUT_EN_V << LP_I2C_TIME_OUT_EN_S) +#define LP_I2C_TIME_OUT_EN_V 0x00000001U +#define LP_I2C_TIME_OUT_EN_S 5 -/** I2C_FIFO_ST_REG register +/** LP_I2C_FIFO_ST_REG register * FIFO status register. */ -#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14) -/** I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0; +#define LP_I2C_FIFO_ST_REG (DR_REG_LP_I2C_BASE + 0x14) +/** LP_I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0; * This is the offset address of the APB reading from rxfifo */ -#define I2C_RXFIFO_RADDR 0x0000000FU -#define I2C_RXFIFO_RADDR_M (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S) -#define I2C_RXFIFO_RADDR_V 0x0000000FU -#define I2C_RXFIFO_RADDR_S 0 -/** I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0; +#define LP_I2C_RXFIFO_RADDR 0x0000000FU +#define LP_I2C_RXFIFO_RADDR_M (LP_I2C_RXFIFO_RADDR_V << LP_I2C_RXFIFO_RADDR_S) +#define LP_I2C_RXFIFO_RADDR_V 0x0000000FU +#define LP_I2C_RXFIFO_RADDR_S 0 +/** LP_I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0; * This is the offset address of i2c module receiving data and writing to rxfifo. */ -#define I2C_RXFIFO_WADDR 0x0000000FU -#define I2C_RXFIFO_WADDR_M (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S) -#define I2C_RXFIFO_WADDR_V 0x0000000FU -#define I2C_RXFIFO_WADDR_S 5 -/** I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0; +#define LP_I2C_RXFIFO_WADDR 0x0000000FU +#define LP_I2C_RXFIFO_WADDR_M (LP_I2C_RXFIFO_WADDR_V << LP_I2C_RXFIFO_WADDR_S) +#define LP_I2C_RXFIFO_WADDR_V 0x0000000FU +#define LP_I2C_RXFIFO_WADDR_S 5 +/** LP_I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0; * This is the offset address of i2c module reading from txfifo. */ -#define I2C_TXFIFO_RADDR 0x0000000FU -#define I2C_TXFIFO_RADDR_M (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S) -#define I2C_TXFIFO_RADDR_V 0x0000000FU -#define I2C_TXFIFO_RADDR_S 10 -/** I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0; +#define LP_I2C_TXFIFO_RADDR 0x0000000FU +#define LP_I2C_TXFIFO_RADDR_M (LP_I2C_TXFIFO_RADDR_V << LP_I2C_TXFIFO_RADDR_S) +#define LP_I2C_TXFIFO_RADDR_V 0x0000000FU +#define LP_I2C_TXFIFO_RADDR_S 10 +/** LP_I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0; * This is the offset address of APB bus writing to txfifo. */ -#define I2C_TXFIFO_WADDR 0x0000000FU -#define I2C_TXFIFO_WADDR_M (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S) -#define I2C_TXFIFO_WADDR_V 0x0000000FU -#define I2C_TXFIFO_WADDR_S 15 +#define LP_I2C_TXFIFO_WADDR 0x0000000FU +#define LP_I2C_TXFIFO_WADDR_M (LP_I2C_TXFIFO_WADDR_V << LP_I2C_TXFIFO_WADDR_S) +#define LP_I2C_TXFIFO_WADDR_V 0x0000000FU +#define LP_I2C_TXFIFO_WADDR_S 15 -/** I2C_FIFO_CONF_REG register +/** LP_I2C_FIFO_CONF_REG register * FIFO configuration register. */ -#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18) -/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6; +#define LP_I2C_FIFO_CONF_REG (DR_REG_LP_I2C_BASE + 0x18) +/** LP_I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6; * The water mark threshold of rx FIFO in nonfifo access mode. When * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. */ -#define I2C_RXFIFO_WM_THRHD 0x0000000FU -#define I2C_RXFIFO_WM_THRHD_M (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S) -#define I2C_RXFIFO_WM_THRHD_V 0x0000000FU -#define I2C_RXFIFO_WM_THRHD_S 0 -/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2; +#define LP_I2C_RXFIFO_WM_THRHD 0x0000000FU +#define LP_I2C_RXFIFO_WM_THRHD_M (LP_I2C_RXFIFO_WM_THRHD_V << LP_I2C_RXFIFO_WM_THRHD_S) +#define LP_I2C_RXFIFO_WM_THRHD_V 0x0000000FU +#define LP_I2C_RXFIFO_WM_THRHD_S 0 +/** LP_I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2; * The water mark threshold of tx FIFO in nonfifo access mode. When * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. */ -#define I2C_TXFIFO_WM_THRHD 0x0000000FU -#define I2C_TXFIFO_WM_THRHD_M (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S) -#define I2C_TXFIFO_WM_THRHD_V 0x0000000FU -#define I2C_TXFIFO_WM_THRHD_S 5 -/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; +#define LP_I2C_TXFIFO_WM_THRHD 0x0000000FU +#define LP_I2C_TXFIFO_WM_THRHD_M (LP_I2C_TXFIFO_WM_THRHD_V << LP_I2C_TXFIFO_WM_THRHD_S) +#define LP_I2C_TXFIFO_WM_THRHD_V 0x0000000FU +#define LP_I2C_TXFIFO_WM_THRHD_S 5 +/** LP_I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; * Set this bit to enable APB nonfifo access. */ -#define I2C_NONFIFO_EN (BIT(10)) -#define I2C_NONFIFO_EN_M (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S) -#define I2C_NONFIFO_EN_V 0x00000001U -#define I2C_NONFIFO_EN_S 10 -/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; +#define LP_I2C_NONFIFO_EN (BIT(10)) +#define LP_I2C_NONFIFO_EN_M (LP_I2C_NONFIFO_EN_V << LP_I2C_NONFIFO_EN_S) +#define LP_I2C_NONFIFO_EN_V 0x00000001U +#define LP_I2C_NONFIFO_EN_S 10 +/** LP_I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; * Set this bit to reset rx-fifo. */ -#define I2C_RX_FIFO_RST (BIT(12)) -#define I2C_RX_FIFO_RST_M (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S) -#define I2C_RX_FIFO_RST_V 0x00000001U -#define I2C_RX_FIFO_RST_S 12 -/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; +#define LP_I2C_RX_FIFO_RST (BIT(12)) +#define LP_I2C_RX_FIFO_RST_M (LP_I2C_RX_FIFO_RST_V << LP_I2C_RX_FIFO_RST_S) +#define LP_I2C_RX_FIFO_RST_V 0x00000001U +#define LP_I2C_RX_FIFO_RST_S 12 +/** LP_I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; * Set this bit to reset tx-fifo. */ -#define I2C_TX_FIFO_RST (BIT(13)) -#define I2C_TX_FIFO_RST_M (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S) -#define I2C_TX_FIFO_RST_V 0x00000001U -#define I2C_TX_FIFO_RST_S 13 -/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; +#define LP_I2C_TX_FIFO_RST (BIT(13)) +#define LP_I2C_TX_FIFO_RST_M (LP_I2C_TX_FIFO_RST_V << LP_I2C_TX_FIFO_RST_S) +#define LP_I2C_TX_FIFO_RST_V 0x00000001U +#define LP_I2C_TX_FIFO_RST_S 13 +/** LP_I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. */ -#define I2C_FIFO_PRT_EN (BIT(14)) -#define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) -#define I2C_FIFO_PRT_EN_V 0x00000001U -#define I2C_FIFO_PRT_EN_S 14 +#define LP_I2C_FIFO_PRT_EN (BIT(14)) +#define LP_I2C_FIFO_PRT_EN_M (LP_I2C_FIFO_PRT_EN_V << LP_I2C_FIFO_PRT_EN_S) +#define LP_I2C_FIFO_PRT_EN_V 0x00000001U +#define LP_I2C_FIFO_PRT_EN_S 14 -/** I2C_DATA_REG register +/** LP_I2C_DATA_REG register * Rx FIFO read data. */ -#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c) -/** I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; +#define LP_I2C_DATA_REG (DR_REG_LP_I2C_BASE + 0x1c) +/** LP_I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; * The value of rx FIFO read data. */ -#define I2C_FIFO_RDATA 0x000000FFU -#define I2C_FIFO_RDATA_M (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S) -#define I2C_FIFO_RDATA_V 0x000000FFU -#define I2C_FIFO_RDATA_S 0 +#define LP_I2C_FIFO_RDATA 0x000000FFU +#define LP_I2C_FIFO_RDATA_M (LP_I2C_FIFO_RDATA_V << LP_I2C_FIFO_RDATA_S) +#define LP_I2C_FIFO_RDATA_V 0x000000FFU +#define LP_I2C_FIFO_RDATA_S 0 -/** I2C_INT_RAW_REG register +/** LP_I2C_INT_RAW_REG register * Raw interrupt status */ -#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20) -/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. +#define LP_I2C_INT_RAW_REG (DR_REG_LP_I2C_BASE + 0x20) +/** LP_I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_WM_INT interrupt. */ -#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) -#define I2C_RXFIFO_WM_INT_RAW_M (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S) -#define I2C_RXFIFO_WM_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_WM_INT_RAW_S 0 -/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; - * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. +#define LP_I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_RAW_M (LP_I2C_RXFIFO_WM_INT_RAW_V << LP_I2C_RXFIFO_WM_INT_RAW_S) +#define LP_I2C_RXFIFO_WM_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_RAW_S 0 +/** LP_I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt bit for LP_I2C_TXFIFO_WM_INT interrupt. */ -#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) -#define I2C_TXFIFO_WM_INT_RAW_M (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S) -#define I2C_TXFIFO_WM_INT_RAW_V 0x00000001U -#define I2C_TXFIFO_WM_INT_RAW_S 1 -/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. +#define LP_I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_RAW_M (LP_I2C_TXFIFO_WM_INT_RAW_V << LP_I2C_TXFIFO_WM_INT_RAW_S) +#define LP_I2C_TXFIFO_WM_INT_RAW_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_RAW_S 1 +/** LP_I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_OVF_INT interrupt. */ -#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_M (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S) -#define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_RAW_S 2 -/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; - * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. +#define LP_I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_RAW_M (LP_I2C_RXFIFO_OVF_INT_RAW_V << LP_I2C_RXFIFO_OVF_INT_RAW_S) +#define LP_I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_RAW_S 2 +/** LP_I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt bit for the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_END_DETECT_INT_RAW (BIT(3)) -#define I2C_END_DETECT_INT_RAW_M (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S) -#define I2C_END_DETECT_INT_RAW_V 0x00000001U -#define I2C_END_DETECT_INT_RAW_S 3 -/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; - * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. +#define LP_I2C_END_DETECT_INT_RAW (BIT(3)) +#define LP_I2C_END_DETECT_INT_RAW_M (LP_I2C_END_DETECT_INT_RAW_V << LP_I2C_END_DETECT_INT_RAW_S) +#define LP_I2C_END_DETECT_INT_RAW_V 0x00000001U +#define LP_I2C_END_DETECT_INT_RAW_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt bit for the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_RAW_M (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S) -#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 -/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; - * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_M (LP_I2C_BYTE_TRANS_DONE_INT_RAW_V << LP_I2C_BYTE_TRANS_DONE_INT_RAW_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. */ -#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_M (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S) -#define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_RAW_S 5 -/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; - * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_RAW_M (LP_I2C_ARBITRATION_LOST_INT_RAW_V << LP_I2C_ARBITRATION_LOST_INT_RAW_S) +#define LP_I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_RAW_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt bit for LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_RAW_M (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S) -#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 -/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; - * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_M (LP_I2C_MST_TXFIFO_UDF_INT_RAW_V << LP_I2C_MST_TXFIFO_UDF_INT_RAW_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_M (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S) -#define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_RAW_S 7 -/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; - * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. +#define LP_I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_RAW_M (LP_I2C_TRANS_COMPLETE_INT_RAW_V << LP_I2C_TRANS_COMPLETE_INT_RAW_S) +#define LP_I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_RAW_S 7 +/** LP_I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt bit for the LP_I2C_TIME_OUT_INT interrupt. */ -#define I2C_TIME_OUT_INT_RAW (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_M (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S) -#define I2C_TIME_OUT_INT_RAW_V 0x00000001U -#define I2C_TIME_OUT_INT_RAW_S 8 -/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; - * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. +#define LP_I2C_TIME_OUT_INT_RAW (BIT(8)) +#define LP_I2C_TIME_OUT_INT_RAW_M (LP_I2C_TIME_OUT_INT_RAW_V << LP_I2C_TIME_OUT_INT_RAW_S) +#define LP_I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_RAW_S 8 +/** LP_I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt bit for the LP_I2C_TRANS_START_INT interrupt. */ -#define I2C_TRANS_START_INT_RAW (BIT(9)) -#define I2C_TRANS_START_INT_RAW_M (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S) -#define I2C_TRANS_START_INT_RAW_V 0x00000001U -#define I2C_TRANS_START_INT_RAW_S 9 -/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; - * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. +#define LP_I2C_TRANS_START_INT_RAW (BIT(9)) +#define LP_I2C_TRANS_START_INT_RAW_M (LP_I2C_TRANS_START_INT_RAW_V << LP_I2C_TRANS_START_INT_RAW_S) +#define LP_I2C_TRANS_START_INT_RAW_V 0x00000001U +#define LP_I2C_TRANS_START_INT_RAW_S 9 +/** LP_I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt bit for LP_I2C_SLAVE_STRETCH_INT interrupt. */ -#define I2C_NACK_INT_RAW (BIT(10)) -#define I2C_NACK_INT_RAW_M (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S) -#define I2C_NACK_INT_RAW_V 0x00000001U -#define I2C_NACK_INT_RAW_S 10 -/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; - * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. +#define LP_I2C_NACK_INT_RAW (BIT(10)) +#define LP_I2C_NACK_INT_RAW_M (LP_I2C_NACK_INT_RAW_V << LP_I2C_NACK_INT_RAW_S) +#define LP_I2C_NACK_INT_RAW_V 0x00000001U +#define LP_I2C_NACK_INT_RAW_S 10 +/** LP_I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt bit for LP_I2C_TXFIFO_OVF_INT interrupt. */ -#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) -#define I2C_TXFIFO_OVF_INT_RAW_M (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S) -#define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_RAW_S 11 -/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. +#define LP_I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_RAW_M (LP_I2C_TXFIFO_OVF_INT_RAW_V << LP_I2C_TXFIFO_OVF_INT_RAW_S) +#define LP_I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_RAW_S 11 +/** LP_I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_UDF_INT interrupt. */ -#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) -#define I2C_RXFIFO_UDF_INT_RAW_M (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S) -#define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_RAW_S 12 -/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; - * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. +#define LP_I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_RAW_M (LP_I2C_RXFIFO_UDF_INT_RAW_V << LP_I2C_RXFIFO_UDF_INT_RAW_S) +#define LP_I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_RAW_S 12 +/** LP_I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt bit for LP_I2C_SCL_ST_TO_INT interrupt. */ -#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) -#define I2C_SCL_ST_TO_INT_RAW_M (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S) -#define I2C_SCL_ST_TO_INT_RAW_V 0x00000001U -#define I2C_SCL_ST_TO_INT_RAW_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; - * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. +#define LP_I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_RAW_M (LP_I2C_SCL_ST_TO_INT_RAW_V << LP_I2C_SCL_ST_TO_INT_RAW_S) +#define LP_I2C_SCL_ST_TO_INT_RAW_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_RAW_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. */ -#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 -/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; - * The raw interrupt bit for I2C_DET_START_INT interrupt. +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_M (LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V << LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/** LP_I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt bit for LP_I2C_DET_START_INT interrupt. */ -#define I2C_DET_START_INT_RAW (BIT(15)) -#define I2C_DET_START_INT_RAW_M (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S) -#define I2C_DET_START_INT_RAW_V 0x00000001U -#define I2C_DET_START_INT_RAW_S 15 +#define LP_I2C_DET_START_INT_RAW (BIT(15)) +#define LP_I2C_DET_START_INT_RAW_M (LP_I2C_DET_START_INT_RAW_V << LP_I2C_DET_START_INT_RAW_S) +#define LP_I2C_DET_START_INT_RAW_V 0x00000001U +#define LP_I2C_DET_START_INT_RAW_S 15 -/** I2C_INT_CLR_REG register +/** LP_I2C_INT_CLR_REG register * Interrupt clear bits */ -#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24) -/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. +#define LP_I2C_INT_CLR_REG (DR_REG_LP_I2C_BASE + 0x24) +/** LP_I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_WM_INT interrupt. */ -#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) -#define I2C_RXFIFO_WM_INT_CLR_M (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S) -#define I2C_RXFIFO_WM_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_WM_INT_CLR_S 0 -/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. +#define LP_I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_CLR_M (LP_I2C_RXFIFO_WM_INT_CLR_V << LP_I2C_RXFIFO_WM_INT_CLR_S) +#define LP_I2C_RXFIFO_WM_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_CLR_S 0 +/** LP_I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear LP_I2C_TXFIFO_WM_INT interrupt. */ -#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) -#define I2C_TXFIFO_WM_INT_CLR_M (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S) -#define I2C_TXFIFO_WM_INT_CLR_V 0x00000001U -#define I2C_TXFIFO_WM_INT_CLR_S 1 -/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. +#define LP_I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_CLR_M (LP_I2C_TXFIFO_WM_INT_CLR_V << LP_I2C_TXFIFO_WM_INT_CLR_S) +#define LP_I2C_TXFIFO_WM_INT_CLR_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_CLR_S 1 +/** LP_I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_OVF_INT interrupt. */ -#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_M (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S) -#define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_CLR_S 2 -/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the I2C_END_DETECT_INT interrupt. +#define LP_I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_CLR_M (LP_I2C_RXFIFO_OVF_INT_CLR_V << LP_I2C_RXFIFO_OVF_INT_CLR_S) +#define LP_I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_CLR_S 2 +/** LP_I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_END_DETECT_INT_CLR (BIT(3)) -#define I2C_END_DETECT_INT_CLR_M (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S) -#define I2C_END_DETECT_INT_CLR_V 0x00000001U -#define I2C_END_DETECT_INT_CLR_S 3 -/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the I2C_END_DETECT_INT interrupt. +#define LP_I2C_END_DETECT_INT_CLR (BIT(3)) +#define LP_I2C_END_DETECT_INT_CLR_M (LP_I2C_END_DETECT_INT_CLR_V << LP_I2C_END_DETECT_INT_CLR_S) +#define LP_I2C_END_DETECT_INT_CLR_V 0x00000001U +#define LP_I2C_END_DETECT_INT_CLR_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_CLR_M (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S) -#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 -/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_M (LP_I2C_BYTE_TRANS_DONE_INT_CLR_V << LP_I2C_BYTE_TRANS_DONE_INT_CLR_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the LP_I2C_ARBITRATION_LOST_INT interrupt. */ -#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_M (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S) -#define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_CLR_S 5 -/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_CLR_M (LP_I2C_ARBITRATION_LOST_INT_CLR_V << LP_I2C_ARBITRATION_LOST_INT_CLR_S) +#define LP_I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_CLR_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_CLR_M (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S) -#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 -/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_M (LP_I2C_MST_TXFIFO_UDF_INT_CLR_V << LP_I2C_MST_TXFIFO_UDF_INT_CLR_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_M (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S) -#define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_CLR_S 7 -/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the I2C_TIME_OUT_INT interrupt. +#define LP_I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_CLR_M (LP_I2C_TRANS_COMPLETE_INT_CLR_V << LP_I2C_TRANS_COMPLETE_INT_CLR_S) +#define LP_I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_CLR_S 7 +/** LP_I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the LP_I2C_TIME_OUT_INT interrupt. */ -#define I2C_TIME_OUT_INT_CLR (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_M (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S) -#define I2C_TIME_OUT_INT_CLR_V 0x00000001U -#define I2C_TIME_OUT_INT_CLR_S 8 -/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the I2C_TRANS_START_INT interrupt. +#define LP_I2C_TIME_OUT_INT_CLR (BIT(8)) +#define LP_I2C_TIME_OUT_INT_CLR_M (LP_I2C_TIME_OUT_INT_CLR_V << LP_I2C_TIME_OUT_INT_CLR_S) +#define LP_I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_CLR_S 8 +/** LP_I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the LP_I2C_TRANS_START_INT interrupt. */ -#define I2C_TRANS_START_INT_CLR (BIT(9)) -#define I2C_TRANS_START_INT_CLR_M (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S) -#define I2C_TRANS_START_INT_CLR_V 0x00000001U -#define I2C_TRANS_START_INT_CLR_S 9 -/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. +#define LP_I2C_TRANS_START_INT_CLR (BIT(9)) +#define LP_I2C_TRANS_START_INT_CLR_M (LP_I2C_TRANS_START_INT_CLR_V << LP_I2C_TRANS_START_INT_CLR_S) +#define LP_I2C_TRANS_START_INT_CLR_V 0x00000001U +#define LP_I2C_TRANS_START_INT_CLR_S 9 +/** LP_I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear LP_I2C_SLAVE_STRETCH_INT interrupt. */ -#define I2C_NACK_INT_CLR (BIT(10)) -#define I2C_NACK_INT_CLR_M (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S) -#define I2C_NACK_INT_CLR_V 0x00000001U -#define I2C_NACK_INT_CLR_S 10 -/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. +#define LP_I2C_NACK_INT_CLR (BIT(10)) +#define LP_I2C_NACK_INT_CLR_M (LP_I2C_NACK_INT_CLR_V << LP_I2C_NACK_INT_CLR_S) +#define LP_I2C_NACK_INT_CLR_V 0x00000001U +#define LP_I2C_NACK_INT_CLR_S 10 +/** LP_I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear LP_I2C_TXFIFO_OVF_INT interrupt. */ -#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) -#define I2C_TXFIFO_OVF_INT_CLR_M (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S) -#define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_CLR_S 11 -/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. +#define LP_I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_CLR_M (LP_I2C_TXFIFO_OVF_INT_CLR_V << LP_I2C_TXFIFO_OVF_INT_CLR_S) +#define LP_I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_CLR_S 11 +/** LP_I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_UDF_INT interrupt. */ -#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) -#define I2C_RXFIFO_UDF_INT_CLR_M (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S) -#define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_CLR_S 12 -/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. +#define LP_I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_CLR_M (LP_I2C_RXFIFO_UDF_INT_CLR_V << LP_I2C_RXFIFO_UDF_INT_CLR_S) +#define LP_I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_CLR_S 12 +/** LP_I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear LP_I2C_SCL_ST_TO_INT interrupt. */ -#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) -#define I2C_SCL_ST_TO_INT_CLR_M (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S) -#define I2C_SCL_ST_TO_INT_CLR_V 0x00000001U -#define I2C_SCL_ST_TO_INT_CLR_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; - * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. +#define LP_I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_CLR_M (LP_I2C_SCL_ST_TO_INT_CLR_V << LP_I2C_SCL_ST_TO_INT_CLR_S) +#define LP_I2C_SCL_ST_TO_INT_CLR_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_CLR_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear LP_I2C_SCL_MAIN_ST_TO_INT interrupt. */ -#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 -/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; - * Set this bit to clear I2C_DET_START_INT interrupt. +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_M (LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V << LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/** LP_I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear LP_I2C_DET_START_INT interrupt. */ -#define I2C_DET_START_INT_CLR (BIT(15)) -#define I2C_DET_START_INT_CLR_M (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S) -#define I2C_DET_START_INT_CLR_V 0x00000001U -#define I2C_DET_START_INT_CLR_S 15 +#define LP_I2C_DET_START_INT_CLR (BIT(15)) +#define LP_I2C_DET_START_INT_CLR_M (LP_I2C_DET_START_INT_CLR_V << LP_I2C_DET_START_INT_CLR_S) +#define LP_I2C_DET_START_INT_CLR_V 0x00000001U +#define LP_I2C_DET_START_INT_CLR_S 15 -/** I2C_INT_ENA_REG register +/** LP_I2C_INT_ENA_REG register * Interrupt enable bits */ -#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28) -/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. +#define LP_I2C_INT_ENA_REG (DR_REG_LP_I2C_BASE + 0x28) +/** LP_I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_WM_INT interrupt. */ -#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) -#define I2C_RXFIFO_WM_INT_ENA_M (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S) -#define I2C_RXFIFO_WM_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_WM_INT_ENA_S 0 -/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. +#define LP_I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_ENA_M (LP_I2C_RXFIFO_WM_INT_ENA_V << LP_I2C_RXFIFO_WM_INT_ENA_S) +#define LP_I2C_RXFIFO_WM_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_ENA_S 0 +/** LP_I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for LP_I2C_TXFIFO_WM_INT interrupt. */ -#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) -#define I2C_TXFIFO_WM_INT_ENA_M (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S) -#define I2C_TXFIFO_WM_INT_ENA_V 0x00000001U -#define I2C_TXFIFO_WM_INT_ENA_S 1 -/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. +#define LP_I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_ENA_M (LP_I2C_TXFIFO_WM_INT_ENA_V << LP_I2C_TXFIFO_WM_INT_ENA_S) +#define LP_I2C_TXFIFO_WM_INT_ENA_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_ENA_S 1 +/** LP_I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_OVF_INT interrupt. */ -#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_M (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S) -#define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_ENA_S 2 -/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. +#define LP_I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_ENA_M (LP_I2C_RXFIFO_OVF_INT_ENA_V << LP_I2C_RXFIFO_OVF_INT_ENA_S) +#define LP_I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_ENA_S 2 +/** LP_I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_END_DETECT_INT_ENA (BIT(3)) -#define I2C_END_DETECT_INT_ENA_M (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S) -#define I2C_END_DETECT_INT_ENA_V 0x00000001U -#define I2C_END_DETECT_INT_ENA_S 3 -/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. +#define LP_I2C_END_DETECT_INT_ENA (BIT(3)) +#define LP_I2C_END_DETECT_INT_ENA_M (LP_I2C_END_DETECT_INT_ENA_V << LP_I2C_END_DETECT_INT_ENA_S) +#define LP_I2C_END_DETECT_INT_ENA_V 0x00000001U +#define LP_I2C_END_DETECT_INT_ENA_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ENA_M (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S) -#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 -/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_M (LP_I2C_BYTE_TRANS_DONE_INT_ENA_V << LP_I2C_BYTE_TRANS_DONE_INT_ENA_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. */ -#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_M (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S) -#define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_ENA_S 5 -/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_ENA_M (LP_I2C_ARBITRATION_LOST_INT_ENA_V << LP_I2C_ARBITRATION_LOST_INT_ENA_S) +#define LP_I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_ENA_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ENA_M (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S) -#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 -/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_M (LP_I2C_MST_TXFIFO_UDF_INT_ENA_V << LP_I2C_MST_TXFIFO_UDF_INT_ENA_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_M (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S) -#define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_ENA_S 7 -/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. +#define LP_I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_ENA_M (LP_I2C_TRANS_COMPLETE_INT_ENA_V << LP_I2C_TRANS_COMPLETE_INT_ENA_S) +#define LP_I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_ENA_S 7 +/** LP_I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the LP_I2C_TIME_OUT_INT interrupt. */ -#define I2C_TIME_OUT_INT_ENA (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_M (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S) -#define I2C_TIME_OUT_INT_ENA_V 0x00000001U -#define I2C_TIME_OUT_INT_ENA_S 8 -/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. +#define LP_I2C_TIME_OUT_INT_ENA (BIT(8)) +#define LP_I2C_TIME_OUT_INT_ENA_M (LP_I2C_TIME_OUT_INT_ENA_V << LP_I2C_TIME_OUT_INT_ENA_S) +#define LP_I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_ENA_S 8 +/** LP_I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the LP_I2C_TRANS_START_INT interrupt. */ -#define I2C_TRANS_START_INT_ENA (BIT(9)) -#define I2C_TRANS_START_INT_ENA_M (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S) -#define I2C_TRANS_START_INT_ENA_V 0x00000001U -#define I2C_TRANS_START_INT_ENA_S 9 -/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. +#define LP_I2C_TRANS_START_INT_ENA (BIT(9)) +#define LP_I2C_TRANS_START_INT_ENA_M (LP_I2C_TRANS_START_INT_ENA_V << LP_I2C_TRANS_START_INT_ENA_S) +#define LP_I2C_TRANS_START_INT_ENA_V 0x00000001U +#define LP_I2C_TRANS_START_INT_ENA_S 9 +/** LP_I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for LP_I2C_SLAVE_STRETCH_INT interrupt. */ -#define I2C_NACK_INT_ENA (BIT(10)) -#define I2C_NACK_INT_ENA_M (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S) -#define I2C_NACK_INT_ENA_V 0x00000001U -#define I2C_NACK_INT_ENA_S 10 -/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. +#define LP_I2C_NACK_INT_ENA (BIT(10)) +#define LP_I2C_NACK_INT_ENA_M (LP_I2C_NACK_INT_ENA_V << LP_I2C_NACK_INT_ENA_S) +#define LP_I2C_NACK_INT_ENA_V 0x00000001U +#define LP_I2C_NACK_INT_ENA_S 10 +/** LP_I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for LP_I2C_TXFIFO_OVF_INT interrupt. */ -#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ENA_M (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S) -#define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_ENA_S 11 -/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. +#define LP_I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_ENA_M (LP_I2C_TXFIFO_OVF_INT_ENA_V << LP_I2C_TXFIFO_OVF_INT_ENA_S) +#define LP_I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_ENA_S 11 +/** LP_I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_UDF_INT interrupt. */ -#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ENA_M (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S) -#define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_ENA_S 12 -/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. +#define LP_I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_ENA_M (LP_I2C_RXFIFO_UDF_INT_ENA_V << LP_I2C_RXFIFO_UDF_INT_ENA_S) +#define LP_I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_ENA_S 12 +/** LP_I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for LP_I2C_SCL_ST_TO_INT interrupt. */ -#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) -#define I2C_SCL_ST_TO_INT_ENA_M (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S) -#define I2C_SCL_ST_TO_INT_ENA_V 0x00000001U -#define I2C_SCL_ST_TO_INT_ENA_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; - * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. +#define LP_I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_ENA_M (LP_I2C_SCL_ST_TO_INT_ENA_V << LP_I2C_SCL_ST_TO_INT_ENA_S) +#define LP_I2C_SCL_ST_TO_INT_ENA_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_ENA_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. */ -#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 -/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; - * The interrupt enable bit for I2C_DET_START_INT interrupt. +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_M (LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V << LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/** LP_I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for LP_I2C_DET_START_INT interrupt. */ -#define I2C_DET_START_INT_ENA (BIT(15)) -#define I2C_DET_START_INT_ENA_M (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S) -#define I2C_DET_START_INT_ENA_V 0x00000001U -#define I2C_DET_START_INT_ENA_S 15 +#define LP_I2C_DET_START_INT_ENA (BIT(15)) +#define LP_I2C_DET_START_INT_ENA_M (LP_I2C_DET_START_INT_ENA_V << LP_I2C_DET_START_INT_ENA_S) +#define LP_I2C_DET_START_INT_ENA_V 0x00000001U +#define LP_I2C_DET_START_INT_ENA_S 15 -/** I2C_INT_STATUS_REG register +/** LP_I2C_INT_STATUS_REG register * Status of captured I2C communication events */ -#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c) -/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. +#define LP_I2C_INT_STATUS_REG (DR_REG_LP_I2C_BASE + 0x2c) +/** LP_I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_WM_INT interrupt. */ -#define I2C_RXFIFO_WM_INT_ST (BIT(0)) -#define I2C_RXFIFO_WM_INT_ST_M (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S) -#define I2C_RXFIFO_WM_INT_ST_V 0x00000001U -#define I2C_RXFIFO_WM_INT_ST_S 0 -/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. +#define LP_I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_ST_M (LP_I2C_RXFIFO_WM_INT_ST_V << LP_I2C_RXFIFO_WM_INT_ST_S) +#define LP_I2C_RXFIFO_WM_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_ST_S 0 +/** LP_I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for LP_I2C_TXFIFO_WM_INT interrupt. */ -#define I2C_TXFIFO_WM_INT_ST (BIT(1)) -#define I2C_TXFIFO_WM_INT_ST_M (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S) -#define I2C_TXFIFO_WM_INT_ST_V 0x00000001U -#define I2C_TXFIFO_WM_INT_ST_S 1 -/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. +#define LP_I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_ST_M (LP_I2C_TXFIFO_WM_INT_ST_V << LP_I2C_TXFIFO_WM_INT_ST_S) +#define LP_I2C_TXFIFO_WM_INT_ST_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_ST_S 1 +/** LP_I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_OVF_INT interrupt. */ -#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_M (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S) -#define I2C_RXFIFO_OVF_INT_ST_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_ST_S 2 -/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. +#define LP_I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_ST_M (LP_I2C_RXFIFO_OVF_INT_ST_V << LP_I2C_RXFIFO_OVF_INT_ST_S) +#define LP_I2C_RXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_ST_S 2 +/** LP_I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_END_DETECT_INT_ST (BIT(3)) -#define I2C_END_DETECT_INT_ST_M (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S) -#define I2C_END_DETECT_INT_ST_V 0x00000001U -#define I2C_END_DETECT_INT_ST_S 3 -/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. +#define LP_I2C_END_DETECT_INT_ST (BIT(3)) +#define LP_I2C_END_DETECT_INT_ST_M (LP_I2C_END_DETECT_INT_ST_V << LP_I2C_END_DETECT_INT_ST_S) +#define LP_I2C_END_DETECT_INT_ST_V 0x00000001U +#define LP_I2C_END_DETECT_INT_ST_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ST_M (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S) -#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 -/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. +#define LP_I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_M (LP_I2C_BYTE_TRANS_DONE_INT_ST_V << LP_I2C_BYTE_TRANS_DONE_INT_ST_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. */ -#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_M (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S) -#define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_ST_S 5 -/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_ST_M (LP_I2C_ARBITRATION_LOST_INT_ST_V << LP_I2C_ARBITRATION_LOST_INT_ST_S) +#define LP_I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_ST_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ST_M (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S) -#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 -/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; - * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_M (LP_I2C_MST_TXFIFO_UDF_INT_ST_V << LP_I2C_MST_TXFIFO_UDF_INT_ST_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_M (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S) -#define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_ST_S 7 -/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; - * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. +#define LP_I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_ST_M (LP_I2C_TRANS_COMPLETE_INT_ST_V << LP_I2C_TRANS_COMPLETE_INT_ST_S) +#define LP_I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_ST_S 7 +/** LP_I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the LP_I2C_TIME_OUT_INT interrupt. */ -#define I2C_TIME_OUT_INT_ST (BIT(8)) -#define I2C_TIME_OUT_INT_ST_M (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S) -#define I2C_TIME_OUT_INT_ST_V 0x00000001U -#define I2C_TIME_OUT_INT_ST_S 8 -/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; - * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. +#define LP_I2C_TIME_OUT_INT_ST (BIT(8)) +#define LP_I2C_TIME_OUT_INT_ST_M (LP_I2C_TIME_OUT_INT_ST_V << LP_I2C_TIME_OUT_INT_ST_S) +#define LP_I2C_TIME_OUT_INT_ST_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_ST_S 8 +/** LP_I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the LP_I2C_TRANS_START_INT interrupt. */ -#define I2C_TRANS_START_INT_ST (BIT(9)) -#define I2C_TRANS_START_INT_ST_M (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S) -#define I2C_TRANS_START_INT_ST_V 0x00000001U -#define I2C_TRANS_START_INT_ST_S 9 -/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; - * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. +#define LP_I2C_TRANS_START_INT_ST (BIT(9)) +#define LP_I2C_TRANS_START_INT_ST_M (LP_I2C_TRANS_START_INT_ST_V << LP_I2C_TRANS_START_INT_ST_S) +#define LP_I2C_TRANS_START_INT_ST_V 0x00000001U +#define LP_I2C_TRANS_START_INT_ST_S 9 +/** LP_I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for LP_I2C_SLAVE_STRETCH_INT interrupt. */ -#define I2C_NACK_INT_ST (BIT(10)) -#define I2C_NACK_INT_ST_M (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S) -#define I2C_NACK_INT_ST_V 0x00000001U -#define I2C_NACK_INT_ST_S 10 -/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; - * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. +#define LP_I2C_NACK_INT_ST (BIT(10)) +#define LP_I2C_NACK_INT_ST_M (LP_I2C_NACK_INT_ST_V << LP_I2C_NACK_INT_ST_S) +#define LP_I2C_NACK_INT_ST_V 0x00000001U +#define LP_I2C_NACK_INT_ST_S 10 +/** LP_I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for LP_I2C_TXFIFO_OVF_INT interrupt. */ -#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ST_M (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S) -#define I2C_TXFIFO_OVF_INT_ST_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_ST_S 11 -/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. +#define LP_I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_ST_M (LP_I2C_TXFIFO_OVF_INT_ST_V << LP_I2C_TXFIFO_OVF_INT_ST_S) +#define LP_I2C_TXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_ST_S 11 +/** LP_I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_UDF_INT interrupt. */ -#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ST_M (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S) -#define I2C_RXFIFO_UDF_INT_ST_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_ST_S 12 -/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; - * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. +#define LP_I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_ST_M (LP_I2C_RXFIFO_UDF_INT_ST_V << LP_I2C_RXFIFO_UDF_INT_ST_S) +#define LP_I2C_RXFIFO_UDF_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_ST_S 12 +/** LP_I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for LP_I2C_SCL_ST_TO_INT interrupt. */ -#define I2C_SCL_ST_TO_INT_ST (BIT(13)) -#define I2C_SCL_ST_TO_INT_ST_M (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S) -#define I2C_SCL_ST_TO_INT_ST_V 0x00000001U -#define I2C_SCL_ST_TO_INT_ST_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; - * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. +#define LP_I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_ST_M (LP_I2C_SCL_ST_TO_INT_ST_V << LP_I2C_SCL_ST_TO_INT_ST_S) +#define LP_I2C_SCL_ST_TO_INT_ST_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_ST_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. */ -#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ST_M (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S) -#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 -/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; - * The masked interrupt status bit for I2C_DET_START_INT interrupt. +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_M (LP_I2C_SCL_MAIN_ST_TO_INT_ST_V << LP_I2C_SCL_MAIN_ST_TO_INT_ST_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/** LP_I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for LP_I2C_DET_START_INT interrupt. */ -#define I2C_DET_START_INT_ST (BIT(15)) -#define I2C_DET_START_INT_ST_M (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S) -#define I2C_DET_START_INT_ST_V 0x00000001U -#define I2C_DET_START_INT_ST_S 15 +#define LP_I2C_DET_START_INT_ST (BIT(15)) +#define LP_I2C_DET_START_INT_ST_M (LP_I2C_DET_START_INT_ST_V << LP_I2C_DET_START_INT_ST_S) +#define LP_I2C_DET_START_INT_ST_V 0x00000001U +#define LP_I2C_DET_START_INT_ST_S 15 -/** I2C_SDA_HOLD_REG register +/** LP_I2C_SDA_HOLD_REG register * Configures the hold time after a negative SCL edge. */ -#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30) -/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SDA_HOLD_REG (DR_REG_LP_I2C_BASE + 0x30) +/** LP_I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; * This register is used to configure the time to hold the data after the negativeedge * of SCL, in I2C module clock cycles. */ -#define I2C_SDA_HOLD_TIME 0x000001FFU -#define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) -#define I2C_SDA_HOLD_TIME_V 0x000001FFU -#define I2C_SDA_HOLD_TIME_S 0 +#define LP_I2C_SDA_HOLD_TIME 0x000001FFU +#define LP_I2C_SDA_HOLD_TIME_M (LP_I2C_SDA_HOLD_TIME_V << LP_I2C_SDA_HOLD_TIME_S) +#define LP_I2C_SDA_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SDA_HOLD_TIME_S 0 -/** I2C_SDA_SAMPLE_REG register +/** LP_I2C_SDA_SAMPLE_REG register * Configures the sample time after a positive SCL edge. */ -#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34) -/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SDA_SAMPLE_REG (DR_REG_LP_I2C_BASE + 0x34) +/** LP_I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; * This register is used to configure for how long SDA is sampled, in I2C module clock * cycles. */ -#define I2C_SDA_SAMPLE_TIME 0x000001FFU -#define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) -#define I2C_SDA_SAMPLE_TIME_V 0x000001FFU -#define I2C_SDA_SAMPLE_TIME_S 0 +#define LP_I2C_SDA_SAMPLE_TIME 0x000001FFU +#define LP_I2C_SDA_SAMPLE_TIME_M (LP_I2C_SDA_SAMPLE_TIME_V << LP_I2C_SDA_SAMPLE_TIME_S) +#define LP_I2C_SDA_SAMPLE_TIME_V 0x000001FFU +#define LP_I2C_SDA_SAMPLE_TIME_S 0 -/** I2C_SCL_HIGH_PERIOD_REG register +/** LP_I2C_SCL_HIGH_PERIOD_REG register * Configures the high level width of SCL */ -#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38) -/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SCL_HIGH_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x38) +/** LP_I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; * This register is used to configure for how long SCL setup to high level and remains * high in master mode, in I2C module clock cycles. */ -#define I2C_SCL_HIGH_PERIOD 0x000001FFU -#define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) -#define I2C_SCL_HIGH_PERIOD_V 0x000001FFU -#define I2C_SCL_HIGH_PERIOD_S 0 -/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; +#define LP_I2C_SCL_HIGH_PERIOD 0x000001FFU +#define LP_I2C_SCL_HIGH_PERIOD_M (LP_I2C_SCL_HIGH_PERIOD_V << LP_I2C_SCL_HIGH_PERIOD_S) +#define LP_I2C_SCL_HIGH_PERIOD_V 0x000001FFU +#define LP_I2C_SCL_HIGH_PERIOD_S 0 +/** LP_I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; * This register is used to configure for the SCL_FSM's waiting period for SCL high * level in master mode, in I2C module clock cycles. */ -#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU -#define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) -#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU -#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 +#define LP_I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_M (LP_I2C_SCL_WAIT_HIGH_PERIOD_V << LP_I2C_SCL_WAIT_HIGH_PERIOD_S) +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_S 9 -/** I2C_SCL_START_HOLD_REG register +/** LP_I2C_SCL_START_HOLD_REG register * Configures the delay between the SDA and SCL negative edge for a start condition */ -#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40) -/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_START_HOLD_REG (DR_REG_LP_I2C_BASE + 0x40) +/** LP_I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the time between the negative edgeof SDA and the * negative edge of SCL for a START condition, in I2C module clock cycles. */ -#define I2C_SCL_START_HOLD_TIME 0x000001FFU -#define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) -#define I2C_SCL_START_HOLD_TIME_V 0x000001FFU -#define I2C_SCL_START_HOLD_TIME_S 0 +#define LP_I2C_SCL_START_HOLD_TIME 0x000001FFU +#define LP_I2C_SCL_START_HOLD_TIME_M (LP_I2C_SCL_START_HOLD_TIME_V << LP_I2C_SCL_START_HOLD_TIME_S) +#define LP_I2C_SCL_START_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SCL_START_HOLD_TIME_S 0 -/** I2C_SCL_RSTART_SETUP_REG register +/** LP_I2C_SCL_RSTART_SETUP_REG register * Configures the delay between the positive * edge of SCL and the negative edge of SDA */ -#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44) -/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_RSTART_SETUP_REG (DR_REG_LP_I2C_BASE + 0x44) +/** LP_I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the time between the positiveedge of SCL and the * negative edge of SDA for a RESTART condition, in I2C module clock cycles. */ -#define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU -#define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) -#define I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU -#define I2C_SCL_RSTART_SETUP_TIME_S 0 +#define LP_I2C_SCL_RSTART_SETUP_TIME 0x000001FFU +#define LP_I2C_SCL_RSTART_SETUP_TIME_M (LP_I2C_SCL_RSTART_SETUP_TIME_V << LP_I2C_SCL_RSTART_SETUP_TIME_S) +#define LP_I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU +#define LP_I2C_SCL_RSTART_SETUP_TIME_S 0 -/** I2C_SCL_STOP_HOLD_REG register +/** LP_I2C_SCL_STOP_HOLD_REG register * Configures the delay after the SCL clock * edge for a stop condition */ -#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48) -/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_STOP_HOLD_REG (DR_REG_LP_I2C_BASE + 0x48) +/** LP_I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the delay after the STOP condition,in I2C module * clock cycles. */ -#define I2C_SCL_STOP_HOLD_TIME 0x000001FFU -#define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) -#define I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU -#define I2C_SCL_STOP_HOLD_TIME_S 0 +#define LP_I2C_SCL_STOP_HOLD_TIME 0x000001FFU +#define LP_I2C_SCL_STOP_HOLD_TIME_M (LP_I2C_SCL_STOP_HOLD_TIME_V << LP_I2C_SCL_STOP_HOLD_TIME_S) +#define LP_I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SCL_STOP_HOLD_TIME_S 0 -/** I2C_SCL_STOP_SETUP_REG register +/** LP_I2C_SCL_STOP_SETUP_REG register * Configures the delay between the SDA and * SCL positive edge for a stop condition */ -#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c) -/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_STOP_SETUP_REG (DR_REG_LP_I2C_BASE + 0x4c) +/** LP_I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the time between the positive edgeof SCL and the * positive edge of SDA, in I2C module clock cycles. */ -#define I2C_SCL_STOP_SETUP_TIME 0x000001FFU -#define I2C_SCL_STOP_SETUP_TIME_M (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S) -#define I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU -#define I2C_SCL_STOP_SETUP_TIME_S 0 +#define LP_I2C_SCL_STOP_SETUP_TIME 0x000001FFU +#define LP_I2C_SCL_STOP_SETUP_TIME_M (LP_I2C_SCL_STOP_SETUP_TIME_V << LP_I2C_SCL_STOP_SETUP_TIME_S) +#define LP_I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU +#define LP_I2C_SCL_STOP_SETUP_TIME_S 0 -/** I2C_FILTER_CFG_REG register +/** LP_I2C_FILTER_CFG_REG register * SCL and SDA filter configuration register */ -#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50) -/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; +#define LP_I2C_FILTER_CFG_REG (DR_REG_LP_I2C_BASE + 0x50) +/** LP_I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; * When a pulse on the SCL input has smaller width than this register valuein I2C * module clock cycles, the I2C controller will ignore that pulse. */ -#define I2C_SCL_FILTER_THRES 0x0000000FU -#define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) -#define I2C_SCL_FILTER_THRES_V 0x0000000FU -#define I2C_SCL_FILTER_THRES_S 0 -/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; +#define LP_I2C_SCL_FILTER_THRES 0x0000000FU +#define LP_I2C_SCL_FILTER_THRES_M (LP_I2C_SCL_FILTER_THRES_V << LP_I2C_SCL_FILTER_THRES_S) +#define LP_I2C_SCL_FILTER_THRES_V 0x0000000FU +#define LP_I2C_SCL_FILTER_THRES_S 0 +/** LP_I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; * When a pulse on the SDA input has smaller width than this register valuein I2C * module clock cycles, the I2C controller will ignore that pulse. */ -#define I2C_SDA_FILTER_THRES 0x0000000FU -#define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) -#define I2C_SDA_FILTER_THRES_V 0x0000000FU -#define I2C_SDA_FILTER_THRES_S 4 -/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; +#define LP_I2C_SDA_FILTER_THRES 0x0000000FU +#define LP_I2C_SDA_FILTER_THRES_M (LP_I2C_SDA_FILTER_THRES_V << LP_I2C_SDA_FILTER_THRES_S) +#define LP_I2C_SDA_FILTER_THRES_V 0x0000000FU +#define LP_I2C_SDA_FILTER_THRES_S 4 +/** LP_I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; * This is the filter enable bit for SCL. */ -#define I2C_SCL_FILTER_EN (BIT(8)) -#define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) -#define I2C_SCL_FILTER_EN_V 0x00000001U -#define I2C_SCL_FILTER_EN_S 8 -/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; +#define LP_I2C_SCL_FILTER_EN (BIT(8)) +#define LP_I2C_SCL_FILTER_EN_M (LP_I2C_SCL_FILTER_EN_V << LP_I2C_SCL_FILTER_EN_S) +#define LP_I2C_SCL_FILTER_EN_V 0x00000001U +#define LP_I2C_SCL_FILTER_EN_S 8 +/** LP_I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; * This is the filter enable bit for SDA. */ -#define I2C_SDA_FILTER_EN (BIT(9)) -#define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) -#define I2C_SDA_FILTER_EN_V 0x00000001U -#define I2C_SDA_FILTER_EN_S 9 +#define LP_I2C_SDA_FILTER_EN (BIT(9)) +#define LP_I2C_SDA_FILTER_EN_M (LP_I2C_SDA_FILTER_EN_V << LP_I2C_SDA_FILTER_EN_S) +#define LP_I2C_SDA_FILTER_EN_V 0x00000001U +#define LP_I2C_SDA_FILTER_EN_S 9 -/** I2C_CLK_CONF_REG register +/** LP_I2C_CLK_CONF_REG register * I2C CLK configuration register */ -#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54) -/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; +#define LP_I2C_CLK_CONF_REG (DR_REG_LP_I2C_BASE + 0x54) +/** LP_I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; * the integral part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_NUM 0x000000FFU -#define I2C_SCLK_DIV_NUM_M (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S) -#define I2C_SCLK_DIV_NUM_V 0x000000FFU -#define I2C_SCLK_DIV_NUM_S 0 -/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; +#define LP_I2C_SCLK_DIV_NUM 0x000000FFU +#define LP_I2C_SCLK_DIV_NUM_M (LP_I2C_SCLK_DIV_NUM_V << LP_I2C_SCLK_DIV_NUM_S) +#define LP_I2C_SCLK_DIV_NUM_V 0x000000FFU +#define LP_I2C_SCLK_DIV_NUM_S 0 +/** LP_I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; * the numerator of the fractional part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_A 0x0000003FU -#define I2C_SCLK_DIV_A_M (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S) -#define I2C_SCLK_DIV_A_V 0x0000003FU -#define I2C_SCLK_DIV_A_S 8 -/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; +#define LP_I2C_SCLK_DIV_A 0x0000003FU +#define LP_I2C_SCLK_DIV_A_M (LP_I2C_SCLK_DIV_A_V << LP_I2C_SCLK_DIV_A_S) +#define LP_I2C_SCLK_DIV_A_V 0x0000003FU +#define LP_I2C_SCLK_DIV_A_S 8 +/** LP_I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; * the denominator of the fractional part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_B 0x0000003FU -#define I2C_SCLK_DIV_B_M (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S) -#define I2C_SCLK_DIV_B_V 0x0000003FU -#define I2C_SCLK_DIV_B_S 14 -/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; +#define LP_I2C_SCLK_DIV_B 0x0000003FU +#define LP_I2C_SCLK_DIV_B_M (LP_I2C_SCLK_DIV_B_V << LP_I2C_SCLK_DIV_B_S) +#define LP_I2C_SCLK_DIV_B_V 0x0000003FU +#define LP_I2C_SCLK_DIV_B_S 14 +/** LP_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. */ -#define I2C_SCLK_SEL (BIT(20)) -#define I2C_SCLK_SEL_M (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S) -#define I2C_SCLK_SEL_V 0x00000001U -#define I2C_SCLK_SEL_S 20 -/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; +#define LP_I2C_SCLK_SEL (BIT(20)) +#define LP_I2C_SCLK_SEL_M (LP_I2C_SCLK_SEL_V << LP_I2C_SCLK_SEL_S) +#define LP_I2C_SCLK_SEL_V 0x00000001U +#define LP_I2C_SCLK_SEL_S 20 +/** LP_I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; * The clock switch for i2c module */ -#define I2C_SCLK_ACTIVE (BIT(21)) -#define I2C_SCLK_ACTIVE_M (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S) -#define I2C_SCLK_ACTIVE_V 0x00000001U -#define I2C_SCLK_ACTIVE_S 21 +#define LP_I2C_SCLK_ACTIVE (BIT(21)) +#define LP_I2C_SCLK_ACTIVE_M (LP_I2C_SCLK_ACTIVE_V << LP_I2C_SCLK_ACTIVE_S) +#define LP_I2C_SCLK_ACTIVE_V 0x00000001U +#define LP_I2C_SCLK_ACTIVE_S 21 -/** I2C_COMD0_REG register +/** LP_I2C_COMD0_REG register * I2C command register 0 */ -#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58) -/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD0_REG (DR_REG_LP_I2C_BASE + 0x58) +/** LP_I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 0. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND0 0x00003FFFU -#define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) -#define I2C_COMMAND0_V 0x00003FFFU -#define I2C_COMMAND0_S 0 -/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND0 0x00003FFFU +#define LP_I2C_COMMAND0_M (LP_I2C_COMMAND0_V << LP_I2C_COMMAND0_S) +#define LP_I2C_COMMAND0_V 0x00003FFFU +#define LP_I2C_COMMAND0_S 0 +/** LP_I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 0 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND0_DONE (BIT(31)) -#define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) -#define I2C_COMMAND0_DONE_V 0x00000001U -#define I2C_COMMAND0_DONE_S 31 +#define LP_I2C_COMMAND0_DONE (BIT(31)) +#define LP_I2C_COMMAND0_DONE_M (LP_I2C_COMMAND0_DONE_V << LP_I2C_COMMAND0_DONE_S) +#define LP_I2C_COMMAND0_DONE_V 0x00000001U +#define LP_I2C_COMMAND0_DONE_S 31 -/** I2C_COMD1_REG register +/** LP_I2C_COMD1_REG register * I2C command register 1 */ -#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c) -/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD1_REG (DR_REG_LP_I2C_BASE + 0x5c) +/** LP_I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 1. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND1 0x00003FFFU -#define I2C_COMMAND1_M (I2C_COMMAND1_V << I2C_COMMAND1_S) -#define I2C_COMMAND1_V 0x00003FFFU -#define I2C_COMMAND1_S 0 -/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND1 0x00003FFFU +#define LP_I2C_COMMAND1_M (LP_I2C_COMMAND1_V << LP_I2C_COMMAND1_S) +#define LP_I2C_COMMAND1_V 0x00003FFFU +#define LP_I2C_COMMAND1_S 0 +/** LP_I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 1 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND1_DONE (BIT(31)) -#define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) -#define I2C_COMMAND1_DONE_V 0x00000001U -#define I2C_COMMAND1_DONE_S 31 +#define LP_I2C_COMMAND1_DONE (BIT(31)) +#define LP_I2C_COMMAND1_DONE_M (LP_I2C_COMMAND1_DONE_V << LP_I2C_COMMAND1_DONE_S) +#define LP_I2C_COMMAND1_DONE_V 0x00000001U +#define LP_I2C_COMMAND1_DONE_S 31 -/** I2C_COMD2_REG register +/** LP_I2C_COMD2_REG register * I2C command register 2 */ -#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60) -/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD2_REG (DR_REG_LP_I2C_BASE + 0x60) +/** LP_I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 2. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND2 0x00003FFFU -#define I2C_COMMAND2_M (I2C_COMMAND2_V << I2C_COMMAND2_S) -#define I2C_COMMAND2_V 0x00003FFFU -#define I2C_COMMAND2_S 0 -/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND2 0x00003FFFU +#define LP_I2C_COMMAND2_M (LP_I2C_COMMAND2_V << LP_I2C_COMMAND2_S) +#define LP_I2C_COMMAND2_V 0x00003FFFU +#define LP_I2C_COMMAND2_S 0 +/** LP_I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 2 is done in I2C Master mode, this bit changes to highLevel. */ -#define I2C_COMMAND2_DONE (BIT(31)) -#define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) -#define I2C_COMMAND2_DONE_V 0x00000001U -#define I2C_COMMAND2_DONE_S 31 +#define LP_I2C_COMMAND2_DONE (BIT(31)) +#define LP_I2C_COMMAND2_DONE_M (LP_I2C_COMMAND2_DONE_V << LP_I2C_COMMAND2_DONE_S) +#define LP_I2C_COMMAND2_DONE_V 0x00000001U +#define LP_I2C_COMMAND2_DONE_S 31 -/** I2C_COMD3_REG register +/** LP_I2C_COMD3_REG register * I2C command register 3 */ -#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64) -/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD3_REG (DR_REG_LP_I2C_BASE + 0x64) +/** LP_I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 3. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND3 0x00003FFFU -#define I2C_COMMAND3_M (I2C_COMMAND3_V << I2C_COMMAND3_S) -#define I2C_COMMAND3_V 0x00003FFFU -#define I2C_COMMAND3_S 0 -/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND3 0x00003FFFU +#define LP_I2C_COMMAND3_M (LP_I2C_COMMAND3_V << LP_I2C_COMMAND3_S) +#define LP_I2C_COMMAND3_V 0x00003FFFU +#define LP_I2C_COMMAND3_S 0 +/** LP_I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 3 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND3_DONE (BIT(31)) -#define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) -#define I2C_COMMAND3_DONE_V 0x00000001U -#define I2C_COMMAND3_DONE_S 31 +#define LP_I2C_COMMAND3_DONE (BIT(31)) +#define LP_I2C_COMMAND3_DONE_M (LP_I2C_COMMAND3_DONE_V << LP_I2C_COMMAND3_DONE_S) +#define LP_I2C_COMMAND3_DONE_V 0x00000001U +#define LP_I2C_COMMAND3_DONE_S 31 -/** I2C_COMD4_REG register +/** LP_I2C_COMD4_REG register * I2C command register 4 */ -#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68) -/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD4_REG (DR_REG_LP_I2C_BASE + 0x68) +/** LP_I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 4. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND4 0x00003FFFU -#define I2C_COMMAND4_M (I2C_COMMAND4_V << I2C_COMMAND4_S) -#define I2C_COMMAND4_V 0x00003FFFU -#define I2C_COMMAND4_S 0 -/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND4 0x00003FFFU +#define LP_I2C_COMMAND4_M (LP_I2C_COMMAND4_V << LP_I2C_COMMAND4_S) +#define LP_I2C_COMMAND4_V 0x00003FFFU +#define LP_I2C_COMMAND4_S 0 +/** LP_I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 4 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND4_DONE (BIT(31)) -#define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) -#define I2C_COMMAND4_DONE_V 0x00000001U -#define I2C_COMMAND4_DONE_S 31 +#define LP_I2C_COMMAND4_DONE (BIT(31)) +#define LP_I2C_COMMAND4_DONE_M (LP_I2C_COMMAND4_DONE_V << LP_I2C_COMMAND4_DONE_S) +#define LP_I2C_COMMAND4_DONE_V 0x00000001U +#define LP_I2C_COMMAND4_DONE_S 31 -/** I2C_COMD5_REG register +/** LP_I2C_COMD5_REG register * I2C command register 5 */ -#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c) -/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD5_REG (DR_REG_LP_I2C_BASE + 0x6c) +/** LP_I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 5. It consists of three parts:op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND5 0x00003FFFU -#define I2C_COMMAND5_M (I2C_COMMAND5_V << I2C_COMMAND5_S) -#define I2C_COMMAND5_V 0x00003FFFU -#define I2C_COMMAND5_S 0 -/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND5 0x00003FFFU +#define LP_I2C_COMMAND5_M (LP_I2C_COMMAND5_V << LP_I2C_COMMAND5_S) +#define LP_I2C_COMMAND5_V 0x00003FFFU +#define LP_I2C_COMMAND5_S 0 +/** LP_I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 5 is done in I2C Master mode, this bit changes to high level. */ -#define I2C_COMMAND5_DONE (BIT(31)) -#define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) -#define I2C_COMMAND5_DONE_V 0x00000001U -#define I2C_COMMAND5_DONE_S 31 +#define LP_I2C_COMMAND5_DONE (BIT(31)) +#define LP_I2C_COMMAND5_DONE_M (LP_I2C_COMMAND5_DONE_V << LP_I2C_COMMAND5_DONE_S) +#define LP_I2C_COMMAND5_DONE_V 0x00000001U +#define LP_I2C_COMMAND5_DONE_S 31 -/** I2C_COMD6_REG register +/** LP_I2C_COMD6_REG register * I2C command register 6 */ -#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70) -/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD6_REG (DR_REG_LP_I2C_BASE + 0x70) +/** LP_I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 6. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND6 0x00003FFFU -#define I2C_COMMAND6_M (I2C_COMMAND6_V << I2C_COMMAND6_S) -#define I2C_COMMAND6_V 0x00003FFFU -#define I2C_COMMAND6_S 0 -/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND6 0x00003FFFU +#define LP_I2C_COMMAND6_M (LP_I2C_COMMAND6_V << LP_I2C_COMMAND6_S) +#define LP_I2C_COMMAND6_V 0x00003FFFU +#define LP_I2C_COMMAND6_S 0 +/** LP_I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 6 is done in I2C Master mode, this bit changes to high level. */ -#define I2C_COMMAND6_DONE (BIT(31)) -#define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) -#define I2C_COMMAND6_DONE_V 0x00000001U -#define I2C_COMMAND6_DONE_S 31 +#define LP_I2C_COMMAND6_DONE (BIT(31)) +#define LP_I2C_COMMAND6_DONE_M (LP_I2C_COMMAND6_DONE_V << LP_I2C_COMMAND6_DONE_S) +#define LP_I2C_COMMAND6_DONE_V 0x00000001U +#define LP_I2C_COMMAND6_DONE_S 31 -/** I2C_COMD7_REG register +/** LP_I2C_COMD7_REG register * I2C command register 7 */ -#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74) -/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD7_REG (DR_REG_LP_I2C_BASE + 0x74) +/** LP_I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 7. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND7 0x00003FFFU -#define I2C_COMMAND7_M (I2C_COMMAND7_V << I2C_COMMAND7_S) -#define I2C_COMMAND7_V 0x00003FFFU -#define I2C_COMMAND7_S 0 -/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND7 0x00003FFFU +#define LP_I2C_COMMAND7_M (LP_I2C_COMMAND7_V << LP_I2C_COMMAND7_S) +#define LP_I2C_COMMAND7_V 0x00003FFFU +#define LP_I2C_COMMAND7_S 0 +/** LP_I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 7 is done in I2C Master mode, this bit changes to high level. */ -#define I2C_COMMAND7_DONE (BIT(31)) -#define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) -#define I2C_COMMAND7_DONE_V 0x00000001U -#define I2C_COMMAND7_DONE_S 31 +#define LP_I2C_COMMAND7_DONE (BIT(31)) +#define LP_I2C_COMMAND7_DONE_M (LP_I2C_COMMAND7_DONE_V << LP_I2C_COMMAND7_DONE_S) +#define LP_I2C_COMMAND7_DONE_V 0x00000001U +#define LP_I2C_COMMAND7_DONE_S 31 -/** I2C_SCL_ST_TIME_OUT_REG register +/** LP_I2C_SCL_ST_TIME_OUT_REG register * SCL status time out register */ -#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78) -/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; +#define LP_I2C_SCL_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x78) +/** LP_I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 */ -#define I2C_SCL_ST_TO_I2C 0x0000001FU -#define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) -#define I2C_SCL_ST_TO_I2C_V 0x0000001FU -#define I2C_SCL_ST_TO_I2C_S 0 +#define LP_I2C_SCL_ST_TO_I2C 0x0000001FU +#define LP_I2C_SCL_ST_TO_LP_I2C_M (LP_I2C_SCL_ST_TO_LP_I2C_V << LP_I2C_SCL_ST_TO_LP_I2C_S) +#define LP_I2C_SCL_ST_TO_LP_I2C_V 0x0000001FU +#define LP_I2C_SCL_ST_TO_LP_I2C_S 0 -/** I2C_SCL_MAIN_ST_TIME_OUT_REG register +/** LP_I2C_SCL_MAIN_ST_TIME_OUT_REG register * SCL main status time out register */ -#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c) -/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; +#define LP_I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x7c) +/** LP_I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more * than 23 */ -#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU -#define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) -#define I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU -#define I2C_SCL_MAIN_ST_TO_I2C_S 0 +#define LP_I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_M (LP_I2C_SCL_MAIN_ST_TO_LP_I2C_V << LP_I2C_SCL_MAIN_ST_TO_LP_I2C_S) +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_V 0x0000001FU +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_S 0 -/** I2C_SCL_SP_CONF_REG register +/** LP_I2C_SCL_SP_CONF_REG register * Power configuration register */ -#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80) -/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; +#define LP_I2C_SCL_SP_CONF_REG (DR_REG_LP_I2C_BASE + 0x80) +/** LP_I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses * equals to reg_scl_rst_slv_num[4:0]. */ -#define I2C_SCL_RST_SLV_EN (BIT(0)) -#define I2C_SCL_RST_SLV_EN_M (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S) -#define I2C_SCL_RST_SLV_EN_V 0x00000001U -#define I2C_SCL_RST_SLV_EN_S 0 -/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; +#define LP_I2C_SCL_RST_SLV_EN (BIT(0)) +#define LP_I2C_SCL_RST_SLV_EN_M (LP_I2C_SCL_RST_SLV_EN_V << LP_I2C_SCL_RST_SLV_EN_S) +#define LP_I2C_SCL_RST_SLV_EN_V 0x00000001U +#define LP_I2C_SCL_RST_SLV_EN_S 0 +/** LP_I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; * Configure the pulses of SCL generated in I2C master mode. Valid when * reg_scl_rst_slv_en is 1. */ -#define I2C_SCL_RST_SLV_NUM 0x0000001FU -#define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) -#define I2C_SCL_RST_SLV_NUM_V 0x0000001FU -#define I2C_SCL_RST_SLV_NUM_S 1 -/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; +#define LP_I2C_SCL_RST_SLV_NUM 0x0000001FU +#define LP_I2C_SCL_RST_SLV_NUM_M (LP_I2C_SCL_RST_SLV_NUM_V << LP_I2C_SCL_RST_SLV_NUM_S) +#define LP_I2C_SCL_RST_SLV_NUM_V 0x0000001FU +#define LP_I2C_SCL_RST_SLV_NUM_S 1 +/** LP_I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. */ -#define I2C_SCL_PD_EN (BIT(6)) -#define I2C_SCL_PD_EN_M (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S) -#define I2C_SCL_PD_EN_V 0x00000001U -#define I2C_SCL_PD_EN_S 6 -/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; +#define LP_I2C_SCL_PD_EN (BIT(6)) +#define LP_I2C_SCL_PD_EN_M (LP_I2C_SCL_PD_EN_V << LP_I2C_SCL_PD_EN_S) +#define LP_I2C_SCL_PD_EN_V 0x00000001U +#define LP_I2C_SCL_PD_EN_S 6 +/** LP_I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. */ -#define I2C_SDA_PD_EN (BIT(7)) -#define I2C_SDA_PD_EN_M (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S) -#define I2C_SDA_PD_EN_V 0x00000001U -#define I2C_SDA_PD_EN_S 7 +#define LP_I2C_SDA_PD_EN (BIT(7)) +#define LP_I2C_SDA_PD_EN_M (LP_I2C_SDA_PD_EN_V << LP_I2C_SDA_PD_EN_S) +#define LP_I2C_SDA_PD_EN_V 0x00000001U +#define LP_I2C_SDA_PD_EN_S 7 -/** I2C_DATE_REG register +/** LP_I2C_DATE_REG register * Version register */ -#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8) -/** I2C_DATE : R/W; bitpos: [31:0]; default: 37765408; +#define LP_I2C_DATE_REG (DR_REG_LP_I2C_BASE + 0xf8) +/** LP_I2C_DATE : R/W; bitpos: [31:0]; default: 37765408; * This is the the version register. */ -#define I2C_DATE 0xFFFFFFFFU -#define I2C_DATE_M (I2C_DATE_V << I2C_DATE_S) -#define I2C_DATE_V 0xFFFFFFFFU -#define I2C_DATE_S 0 +#define LP_I2C_DATE 0xFFFFFFFFU +#define LP_I2C_DATE_M (LP_I2C_DATE_V << LP_I2C_DATE_S) +#define LP_I2C_DATE_V 0xFFFFFFFFU +#define LP_I2C_DATE_S 0 -/** I2C_TXFIFO_START_ADDR_REG register +/** LP_I2C_TXFIFO_START_ADDR_REG register * I2C TXFIFO base address register */ -#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100) -/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; +#define LP_I2C_TXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x100) +/** LP_I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; * This is the I2C txfifo first address. */ -#define I2C_TXFIFO_START_ADDR 0xFFFFFFFFU -#define I2C_TXFIFO_START_ADDR_M (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S) -#define I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU -#define I2C_TXFIFO_START_ADDR_S 0 +#define LP_I2C_TXFIFO_START_ADDR 0xFFFFFFFFU +#define LP_I2C_TXFIFO_START_ADDR_M (LP_I2C_TXFIFO_START_ADDR_V << LP_I2C_TXFIFO_START_ADDR_S) +#define LP_I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU +#define LP_I2C_TXFIFO_START_ADDR_S 0 -/** I2C_RXFIFO_START_ADDR_REG register +/** LP_I2C_RXFIFO_START_ADDR_REG register * I2C RXFIFO base address register */ -#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180) -/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; +#define LP_I2C_RXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x180) +/** LP_I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; * This is the I2C rxfifo first address. */ -#define I2C_RXFIFO_START_ADDR 0xFFFFFFFFU -#define I2C_RXFIFO_START_ADDR_M (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S) -#define I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU -#define I2C_RXFIFO_START_ADDR_S 0 +#define LP_I2C_RXFIFO_START_ADDR 0xFFFFFFFFU +#define LP_I2C_RXFIFO_START_ADDR_M (LP_I2C_RXFIFO_START_ADDR_V << LP_I2C_RXFIFO_START_ADDR_S) +#define LP_I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU +#define LP_I2C_RXFIFO_START_ADDR_S 0 #ifdef __cplusplus } diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h index 0735efd6be..db7e40838d 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h @@ -813,245 +813,19 @@ typedef union { } lp_spi_sleep_conf1_reg_t; -/** Group: LP SPI W0 REG */ -/** Type of spi_w0 register +/** Group: LP SPI Wn REG */ +/** Type of spi_wn register * SPI CPU-controlled buffer0 */ typedef union { struct { - /** reg_buf0 : R/W/SS; bitpos: [31:0]; default: 0; + /** reg_buf : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ - uint32_t reg_buf0:32; + uint32_t reg_buf:32; }; uint32_t val; -} lp_spi_w0_reg_t; - - -/** Group: LP SPI W1 REG */ -/** Type of spi_w1 register - * SPI CPU-controlled buffer1 - */ -typedef union { - struct { - /** reg_buf1 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf1:32; - }; - uint32_t val; -} lp_spi_w1_reg_t; - - -/** Group: LP SPI W2 REG */ -/** Type of spi_w2 register - * SPI CPU-controlled buffer2 - */ -typedef union { - struct { - /** reg_buf2 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf2:32; - }; - uint32_t val; -} lp_spi_w2_reg_t; - - -/** Group: LP SPI W3 REG */ -/** Type of spi_w3 register - * SPI CPU-controlled buffer3 - */ -typedef union { - struct { - /** reg_buf3 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf3:32; - }; - uint32_t val; -} lp_spi_w3_reg_t; - - -/** Group: LP SPI W4 REG */ -/** Type of spi_w4 register - * SPI CPU-controlled buffer4 - */ -typedef union { - struct { - /** reg_buf4 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf4:32; - }; - uint32_t val; -} lp_spi_w4_reg_t; - - -/** Group: LP SPI W5 REG */ -/** Type of spi_w5 register - * SPI CPU-controlled buffer5 - */ -typedef union { - struct { - /** reg_buf5 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf5:32; - }; - uint32_t val; -} lp_spi_w5_reg_t; - - -/** Group: LP SPI W6 REG */ -/** Type of spi_w6 register - * SPI CPU-controlled buffer6 - */ -typedef union { - struct { - /** reg_buf6 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf6:32; - }; - uint32_t val; -} lp_spi_w6_reg_t; - - -/** Group: LP SPI W7 REG */ -/** Type of spi_w7 register - * SPI CPU-controlled buffer7 - */ -typedef union { - struct { - /** reg_buf7 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf7:32; - }; - uint32_t val; -} lp_spi_w7_reg_t; - - -/** Group: LP SPI W8 REG */ -/** Type of spi_w8 register - * SPI CPU-controlled buffer8 - */ -typedef union { - struct { - /** reg_buf8 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf8:32; - }; - uint32_t val; -} lp_spi_w8_reg_t; - - -/** Group: LP SPI W9 REG */ -/** Type of spi_w9 register - * SPI CPU-controlled buffer9 - */ -typedef union { - struct { - /** reg_buf9 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf9:32; - }; - uint32_t val; -} lp_spi_w9_reg_t; - - -/** Group: LP SPI W10 REG */ -/** Type of spi_w10 register - * SPI CPU-controlled buffer10 - */ -typedef union { - struct { - /** reg_buf10 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf10:32; - }; - uint32_t val; -} lp_spi_w10_reg_t; - - -/** Group: LP SPI W11 REG */ -/** Type of spi_w11 register - * SPI CPU-controlled buffer11 - */ -typedef union { - struct { - /** reg_buf11 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf11:32; - }; - uint32_t val; -} lp_spi_w11_reg_t; - - -/** Group: LP SPI W12 REG */ -/** Type of spi_w12 register - * SPI CPU-controlled buffer12 - */ -typedef union { - struct { - /** reg_buf12 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf12:32; - }; - uint32_t val; -} lp_spi_w12_reg_t; - - -/** Group: LP SPI W13 REG */ -/** Type of spi_w13 register - * SPI CPU-controlled buffer13 - */ -typedef union { - struct { - /** reg_buf13 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf13:32; - }; - uint32_t val; -} lp_spi_w13_reg_t; - - -/** Group: LP SPI W14 REG */ -/** Type of spi_w14 register - * SPI CPU-controlled buffer14 - */ -typedef union { - struct { - /** reg_buf14 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf14:32; - }; - uint32_t val; -} lp_spi_w14_reg_t; - - -/** Group: LP SPI W15 REG */ -/** Type of spi_w15 register - * SPI CPU-controlled buffer15 - */ -typedef union { - struct { - /** reg_buf15 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf15:32; - }; - uint32_t val; -} lp_spi_w15_reg_t; - +} lp_spi_wn_reg_t; /** Group: LP SPI SLAVE REG */ /** Type of spi_slave register @@ -1238,22 +1012,7 @@ typedef struct { volatile lp_spi_sleep_conf1_reg_t spi_sleep_conf1; volatile lp_spi_dma_int_set_reg_t spi_dma_int_set; uint32_t reserved_050[18]; - volatile lp_spi_w0_reg_t spi_w0; - volatile lp_spi_w1_reg_t spi_w1; - volatile lp_spi_w2_reg_t spi_w2; - volatile lp_spi_w3_reg_t spi_w3; - volatile lp_spi_w4_reg_t spi_w4; - volatile lp_spi_w5_reg_t spi_w5; - volatile lp_spi_w6_reg_t spi_w6; - volatile lp_spi_w7_reg_t spi_w7; - volatile lp_spi_w8_reg_t spi_w8; - volatile lp_spi_w9_reg_t spi_w9; - volatile lp_spi_w10_reg_t spi_w10; - volatile lp_spi_w11_reg_t spi_w11; - volatile lp_spi_w12_reg_t spi_w12; - volatile lp_spi_w13_reg_t spi_w13; - volatile lp_spi_w14_reg_t spi_w14; - volatile lp_spi_w15_reg_t spi_w15; + volatile lp_spi_wn_reg_t data_buf[16]; uint32_t reserved_0d8[2]; volatile lp_spi_slave_reg_t spi_slave; volatile lp_spi_slave1_reg_t spi_slave1; @@ -1263,12 +1022,12 @@ typedef struct { volatile lp_rnd_eco_cs_reg_t rnd_eco_cs; volatile lp_rnd_eco_low_reg_t rnd_eco_low; volatile lp_rnd_eco_high_reg_t rnd_eco_high; -} lp_dev_t; +} lp_spi_dev_t; -extern lp_dev_t LP_SPI; +extern lp_spi_dev_t LP_SPI; #ifndef __cplusplus -_Static_assert(sizeof(lp_dev_t) == 0x100, "Invalid size of lp_dev_t structure"); +_Static_assert(sizeof(lp_spi_dev_t) == 0x100, "Invalid size of lp_spi_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h index 683e3596ac..68abe42e33 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h @@ -11,331 +11,331 @@ extern "C" { #endif -/** RTC_TIMER_TAR0_LOW_REG register +/** LP_TIMER_TAR0_LOW_REG register * need_des */ -#define RTC_TIMER_TAR0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x0) -/** RTC_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; +#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0) +/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_M (RTC_TIMER_MAIN_TIMER_TAR_LOW0_V << RTC_TIMER_MAIN_TIMER_TAR_LOW0_S) -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_S 0 +#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0 -/** RTC_TIMER_TAR0_HIGH_REG register +/** LP_TIMER_TAR0_HIGH_REG register * need_des */ -#define RTC_TIMER_TAR0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x4) -/** RTC_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; +#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_M (RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S) -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 -/** RTC_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_TAR_EN0_M (RTC_TIMER_MAIN_TIMER_TAR_EN0_V << RTC_TIMER_MAIN_TIMER_TAR_EN0_S) -#define RTC_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_TAR_EN0_S 31 +#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31 -/** RTC_TIMER_TAR1_LOW_REG register +/** LP_TIMER_TAR1_LOW_REG register * need_des */ -#define RTC_TIMER_TAR1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x8) -/** RTC_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; +#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8) +/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_M (RTC_TIMER_MAIN_TIMER_TAR_LOW1_V << RTC_TIMER_MAIN_TIMER_TAR_LOW1_S) -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_S 0 +#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0 -/** RTC_TIMER_TAR1_HIGH_REG register +/** LP_TIMER_TAR1_HIGH_REG register * need_des */ -#define RTC_TIMER_TAR1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0xc) -/** RTC_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; +#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_M (RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S) -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 -/** RTC_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_TAR_EN1_M (RTC_TIMER_MAIN_TIMER_TAR_EN1_V << RTC_TIMER_MAIN_TIMER_TAR_EN1_S) -#define RTC_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_TAR_EN1_S 31 +#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31 -/** RTC_TIMER_UPDATE_REG register +/** LP_TIMER_UPDATE_REG register * need_des */ -#define RTC_TIMER_UPDATE_REG (DR_REG_RTC_TIMER_BASE + 0x10) -/** RTC_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0; +#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10) +/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_UPDATE (BIT(28)) -#define RTC_TIMER_MAIN_TIMER_UPDATE_M (RTC_TIMER_MAIN_TIMER_UPDATE_V << RTC_TIMER_MAIN_TIMER_UPDATE_S) -#define RTC_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_UPDATE_S 28 -/** RTC_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; +#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(28)) +#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S) +#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_UPDATE_S 28 +/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_M (RTC_TIMER_MAIN_TIMER_XTAL_OFF_V << RTC_TIMER_MAIN_TIMER_XTAL_OFF_S) -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_S 29 -/** RTC_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; +#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29 +/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_SYS_STALL_M (RTC_TIMER_MAIN_TIMER_SYS_STALL_V << RTC_TIMER_MAIN_TIMER_SYS_STALL_S) -#define RTC_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_SYS_STALL_S 30 -/** RTC_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30 +/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_SYS_RST_M (RTC_TIMER_MAIN_TIMER_SYS_RST_V << RTC_TIMER_MAIN_TIMER_SYS_RST_S) -#define RTC_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_SYS_RST_S 31 +#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S) +#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31 -/** RTC_TIMER_MAIN_BUF0_LOW_REG register +/** LP_TIMER_MAIN_BUF0_LOW_REG register * need_des */ -#define RTC_TIMER_MAIN_BUF0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x14) -/** RTC_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; +#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14) +/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_M (RTC_TIMER_MAIN_TIMER_BUF0_LOW_V << RTC_TIMER_MAIN_TIMER_BUF0_LOW_S) -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_S 0 +#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0 -/** RTC_TIMER_MAIN_BUF0_HIGH_REG register +/** LP_TIMER_MAIN_BUF0_HIGH_REG register * need_des */ -#define RTC_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x18) -/** RTC_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; +#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18) +/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_M (RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S) -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 -/** RTC_TIMER_MAIN_BUF1_LOW_REG register +/** LP_TIMER_MAIN_BUF1_LOW_REG register * need_des */ -#define RTC_TIMER_MAIN_BUF1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x1c) -/** RTC_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; +#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c) +/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_M (RTC_TIMER_MAIN_TIMER_BUF1_LOW_V << RTC_TIMER_MAIN_TIMER_BUF1_LOW_S) -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_S 0 +#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0 -/** RTC_TIMER_MAIN_BUF1_HIGH_REG register +/** LP_TIMER_MAIN_BUF1_HIGH_REG register * need_des */ -#define RTC_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x20) -/** RTC_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; +#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20) +/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_M (RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S) -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 -/** RTC_TIMER_MAIN_OVERFLOW_REG register +/** LP_TIMER_MAIN_OVERFLOW_REG register * need_des */ -#define RTC_TIMER_MAIN_OVERFLOW_REG (DR_REG_RTC_TIMER_BASE + 0x24) -/** RTC_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24) +/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_M (RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V << RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S) -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 -/** RTC_TIMER_INT_RAW_REG register +/** LP_TIMER_INT_RAW_REG register * need_des */ -#define RTC_TIMER_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x28) -/** RTC_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; +#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28) +/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_OVERFLOW_RAW (BIT(30)) -#define RTC_TIMER_OVERFLOW_RAW_M (RTC_TIMER_OVERFLOW_RAW_V << RTC_TIMER_OVERFLOW_RAW_S) -#define RTC_TIMER_OVERFLOW_RAW_V 0x00000001U -#define RTC_TIMER_OVERFLOW_RAW_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; +#define LP_TIMER_OVERFLOW_RAW (BIT(30)) +#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S) +#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U +#define LP_TIMER_OVERFLOW_RAW_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_RAW_M (RTC_TIMER_SOC_WAKEUP_INT_RAW_V << RTC_TIMER_SOC_WAKEUP_INT_RAW_S) -#define RTC_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_RAW_S 31 +#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31 -/** RTC_TIMER_INT_ST_REG register +/** LP_TIMER_INT_ST_REG register * need_des */ -#define RTC_TIMER_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x2c) -/** RTC_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; +#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c) +/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_OVERFLOW_ST (BIT(30)) -#define RTC_TIMER_OVERFLOW_ST_M (RTC_TIMER_OVERFLOW_ST_V << RTC_TIMER_OVERFLOW_ST_S) -#define RTC_TIMER_OVERFLOW_ST_V 0x00000001U -#define RTC_TIMER_OVERFLOW_ST_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; +#define LP_TIMER_OVERFLOW_ST (BIT(30)) +#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S) +#define LP_TIMER_OVERFLOW_ST_V 0x00000001U +#define LP_TIMER_OVERFLOW_ST_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_ST_M (RTC_TIMER_SOC_WAKEUP_INT_ST_V << RTC_TIMER_SOC_WAKEUP_INT_ST_S) -#define RTC_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_ST_S 31 +#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S) +#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31 -/** RTC_TIMER_INT_ENA_REG register +/** LP_TIMER_INT_ENA_REG register * need_des */ -#define RTC_TIMER_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x30) -/** RTC_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; +#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30) +/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_OVERFLOW_ENA (BIT(30)) -#define RTC_TIMER_OVERFLOW_ENA_M (RTC_TIMER_OVERFLOW_ENA_V << RTC_TIMER_OVERFLOW_ENA_S) -#define RTC_TIMER_OVERFLOW_ENA_V 0x00000001U -#define RTC_TIMER_OVERFLOW_ENA_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; +#define LP_TIMER_OVERFLOW_ENA (BIT(30)) +#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S) +#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U +#define LP_TIMER_OVERFLOW_ENA_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_ENA_M (RTC_TIMER_SOC_WAKEUP_INT_ENA_V << RTC_TIMER_SOC_WAKEUP_INT_ENA_S) -#define RTC_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_ENA_S 31 +#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31 -/** RTC_TIMER_INT_CLR_REG register +/** LP_TIMER_INT_CLR_REG register * need_des */ -#define RTC_TIMER_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x34) -/** RTC_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; +#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34) +/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_OVERFLOW_CLR (BIT(30)) -#define RTC_TIMER_OVERFLOW_CLR_M (RTC_TIMER_OVERFLOW_CLR_V << RTC_TIMER_OVERFLOW_CLR_S) -#define RTC_TIMER_OVERFLOW_CLR_V 0x00000001U -#define RTC_TIMER_OVERFLOW_CLR_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; +#define LP_TIMER_OVERFLOW_CLR (BIT(30)) +#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S) +#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U +#define LP_TIMER_OVERFLOW_CLR_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_CLR_M (RTC_TIMER_SOC_WAKEUP_INT_CLR_V << RTC_TIMER_SOC_WAKEUP_INT_CLR_S) -#define RTC_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_CLR_S 31 +#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31 -/** RTC_TIMER_LP_INT_RAW_REG register +/** LP_TIMER_LP_INT_RAW_REG register * need_des */ -#define RTC_TIMER_LP_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x38) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; +#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_M (RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 -/** RTC_TIMER_LP_INT_ST_REG register +/** LP_TIMER_LP_INT_ST_REG register * need_des */ -#define RTC_TIMER_LP_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x3c) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; +#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_M (RTC_TIMER_MAIN_TIMER_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_LP_INT_ST_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_S 31 +#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31 -/** RTC_TIMER_LP_INT_ENA_REG register +/** LP_TIMER_LP_INT_ENA_REG register * need_des */ -#define RTC_TIMER_LP_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x40) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; +#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_M (RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 -/** RTC_TIMER_LP_INT_CLR_REG register +/** LP_TIMER_LP_INT_CLR_REG register * need_des */ -#define RTC_TIMER_LP_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x44) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; +#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_M (RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 -/** RTC_TIMER_DATE_REG register +/** LP_TIMER_DATE_REG register * need_des */ -#define RTC_TIMER_DATE_REG (DR_REG_RTC_TIMER_BASE + 0x3fc) -/** RTC_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976; +#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc) +/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976; * need_des */ -#define RTC_TIMER_DATE 0x7FFFFFFFU -#define RTC_TIMER_DATE_M (RTC_TIMER_DATE_V << RTC_TIMER_DATE_S) -#define RTC_TIMER_DATE_V 0x7FFFFFFFU -#define RTC_TIMER_DATE_S 0 -/** RTC_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; +#define LP_TIMER_DATE 0x7FFFFFFFU +#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S) +#define LP_TIMER_DATE_V 0x7FFFFFFFU +#define LP_TIMER_DATE_S 0 +/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_CLK_EN (BIT(31)) -#define RTC_TIMER_CLK_EN_M (RTC_TIMER_CLK_EN_V << RTC_TIMER_CLK_EN_S) -#define RTC_TIMER_CLK_EN_V 0x00000001U -#define RTC_TIMER_CLK_EN_S 31 +#define LP_TIMER_CLK_EN (BIT(31)) +#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S) +#define LP_TIMER_CLK_EN_V 0x00000001U +#define LP_TIMER_CLK_EN_S 31 #ifdef __cplusplus } diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h index afa99e4849..66d15d4985 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h @@ -5,6 +5,7 @@ */ #pragma once +#include #include #include "pmu_reg.h" #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h index 95ce3b2fe2..c8978c0f54 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h @@ -14,1272 +14,1272 @@ extern "C" { /** USB_DEVICE_EP1_REG register * FIFO access for the CDC-ACM data IN and OUT endpoints. */ -#define USB_DEVICE_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0) -/** USB_DEVICE_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0; +#define USB_DEVICE_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) +/** USB_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0; * Write and read byte data to/from UART Tx/Rx FIFO through this field. When * USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) * into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check * USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is * received, then read data from UART Rx FIFO. */ -#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_M (USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_V << USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_S) -#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_S 0 +#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S) +#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_S 0 /** USB_DEVICE_EP1_CONF_REG register * Configuration and control registers for the CDC-ACM FIFOs. */ -#define USB_DEVICE_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4) -/** USB_DEVICE_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; +#define USB_DEVICE_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) +/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; * Set this bit to indicate writing byte data to UART Tx FIFO is done. */ -#define USB_DEVICE_SERIAL_JTAG_WR_DONE (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_WR_DONE_M (USB_DEVICE_SERIAL_JTAG_WR_DONE_V << USB_DEVICE_SERIAL_JTAG_WR_DONE_S) -#define USB_DEVICE_SERIAL_JTAG_WR_DONE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_WR_DONE_S 0 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; +#define USB_SERIAL_JTAG_WR_DONE (BIT(0)) +#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S) +#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001U +#define USB_SERIAL_JTAG_WR_DONE_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing * USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB * Host. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; * 1'b1: Indicate there is data in UART Rx FIFO. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 /** USB_DEVICE_INT_RAW_REG register * Interrupt raw status register. */ -#define USB_DEVICE_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8) -/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; +#define USB_DEVICE_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when flush cmd is received for IN * endpoint 2 of JTAG. */ -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 -/** USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 +/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when SOF frame is received. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; +#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S) +#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; * default: 0; * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received * one packet. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 -/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; * The raw interrupt bit turns to high level when pid error is detected. */ -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 -/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; * The raw interrupt bit turns to high level when CRC5 error is detected. */ -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 -/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; * The raw interrupt bit turns to high level when CRC16 error is detected. */ -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 -/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; * The raw interrupt bit turns to high level when stuff error is detected. */ -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; * default: 0; * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is * received. */ -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; * The raw interrupt bit turns to high level when usb bus reset is detected. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; * default: 0; * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with * zero palyload. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; * default: 0; * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with * zero palyload. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 -/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; * The raw interrupt bit turns to high level when level of RTS from usb serial channel * is changed. */ -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 -/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; * The raw interrupt bit turns to high level when level of DTR from usb serial channel * is changed. */ -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 -/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; * The raw interrupt bit turns to high level when level of GET LINE CODING request is * received. */ -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 -/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; * The raw interrupt bit turns to high level when level of SET LINE CODING request is * received. */ -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 /** USB_DEVICE_INT_ST_REG register * Interrupt status register. */ -#define USB_DEVICE_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xc) -/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; +#define USB_DEVICE_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; * The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 -/** USB_DEVICE_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; * The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) +#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ST_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; * The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; * The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 -/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; * The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_S 4 -/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; * The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 -/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; * The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 -/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; * The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; * The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; * The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; * The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; * The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 -/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; * The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 -/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; * The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 -/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; * The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 -/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; * The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 /** USB_DEVICE_INT_ENA_REG register * Interrupt enable status register. */ -#define USB_DEVICE_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10) -/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 -/** USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; * The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) +#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; * The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; * The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 -/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; * The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 -/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; * The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 -/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; * The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 -/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; * The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; * The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; * The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; * The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; * The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 -/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; * The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 -/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; * The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 -/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; * The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 -/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; * The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 /** USB_DEVICE_INT_CLR_REG register * Interrupt clear status register. */ -#define USB_DEVICE_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14) -/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; +#define USB_DEVICE_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 -/** USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 +/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; * Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) +#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; * Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; * Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 -/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; * Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 -/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; * Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 -/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; * Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 -/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; * Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; * Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; * Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; * Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; * Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 -/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; * Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 -/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; * Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 -/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; * Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 -/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; * Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 /** USB_DEVICE_CONF0_REG register * PHY hardware configuration. */ -#define USB_DEVICE_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18) -/** USB_DEVICE_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) +/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; * Select internal/external PHY */ -#define USB_DEVICE_SERIAL_JTAG_PHY_SEL (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_M (USB_DEVICE_SERIAL_JTAG_PHY_SEL_V << USB_DEVICE_SERIAL_JTAG_PHY_SEL_S) -#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_S 0 -/** USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) +#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) +#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U +#define USB_SERIAL_JTAG_PHY_SEL_S 0 +/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; * Enable software control USB D+ D- exchange */ -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 -/** USB_DEVICE_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 +/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; * USB D+ D- exchange */ -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_M (USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_V << USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_S) -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_S 2 -/** USB_DEVICE_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; +#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2)) +#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_S 2 +/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; * Control single-end input high threshold,1.76V to 2V, step 80mV */ -#define USB_DEVICE_SERIAL_JTAG_VREFH 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_VREFH_M (USB_DEVICE_SERIAL_JTAG_VREFH_V << USB_DEVICE_SERIAL_JTAG_VREFH_S) -#define USB_DEVICE_SERIAL_JTAG_VREFH_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_VREFH_S 3 -/** USB_DEVICE_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; +#define USB_SERIAL_JTAG_VREFH 0x00000003U +#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S) +#define USB_SERIAL_JTAG_VREFH_V 0x00000003U +#define USB_SERIAL_JTAG_VREFH_S 3 +/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; * Control single-end input low threshold,0.8V to 1.04V, step 80mV */ -#define USB_DEVICE_SERIAL_JTAG_VREFL 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_VREFL_M (USB_DEVICE_SERIAL_JTAG_VREFL_V << USB_DEVICE_SERIAL_JTAG_VREFL_S) -#define USB_DEVICE_SERIAL_JTAG_VREFL_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_VREFL_S 5 -/** USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_VREFL 0x00000003U +#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S) +#define USB_SERIAL_JTAG_VREFL_V 0x00000003U +#define USB_SERIAL_JTAG_VREFL_S 5 +/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; * Enable software control input threshold */ -#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_M (USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_S) -#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_S 7 -/** USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7 +/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; * Enable software control USB D+ D- pullup pulldown */ -#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) -#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 -/** USB_DEVICE_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 +/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; * Control USB D+ pull up. */ -#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_M (USB_DEVICE_SERIAL_JTAG_DP_PULLUP_V << USB_DEVICE_SERIAL_JTAG_DP_PULLUP_S) -#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_S 9 -/** USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; +#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9)) +#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S) +#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLUP_S 9 +/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; * Control USB D+ pull down. */ -#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_M (USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_V << USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_S) -#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_S 10 -/** USB_DEVICE_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; +#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) +#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S) +#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10 +/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; * Control USB D- pull up. */ -#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_M (USB_DEVICE_SERIAL_JTAG_DM_PULLUP_V << USB_DEVICE_SERIAL_JTAG_DM_PULLUP_S) -#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_S 11 -/** USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11)) +#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S) +#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLUP_S 11 +/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; * Control USB D- pull down. */ -#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_M (USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_V << USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_S) -#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_S 12 -/** USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) +#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S) +#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12 +/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; * Control pull up value. */ -#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_M (USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_V << USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_S) -#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_S 13 -/** USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; +#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) +#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S) +#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U +#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13 +/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; * Enable USB pad function. */ -#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_S) -#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_S 14 -/** USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14 +/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input * through GPIO Matrix. */ -#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) -#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 /** USB_DEVICE_TEST_REG register * Registers used for debugging the PHY. */ -#define USB_DEVICE_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1c) -/** USB_DEVICE_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) +/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; * Enable test of the USB pad */ -#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_M (USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_V << USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_S 0 -/** USB_DEVICE_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0)) +#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S) +#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_ENABLE_S 0 +/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; * USB pad oen in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_M (USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_V << USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_S 1 -/** USB_DEVICE_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) +#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) +#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_USB_OE_S 1 +/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; * USB D+ tx value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_M (USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_V << USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_S 2 -/** USB_DEVICE_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2)) +#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S) +#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DP_S 2 +/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; * USB D- tx value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_M (USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_V << USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_S 3 -/** USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; +#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3)) +#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S) +#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DM_S 3 +/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; * USB RCV value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_M (USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_S 4 -/** USB_DEVICE_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; +#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) +#define USB_SERIAL_JTAG_TEST_RX_RCV_M (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S) +#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4 +/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; * USB D+ rx value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_M (USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_S 5 -/** USB_DEVICE_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5)) +#define USB_SERIAL_JTAG_TEST_RX_DP_M (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S) +#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DP_S 5 +/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; * USB D- rx value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_M (USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_S 6 +#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6)) +#define USB_SERIAL_JTAG_TEST_RX_DM_M (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S) +#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DM_S 6 /** USB_DEVICE_JFIFO_ST_REG register * JTAG FIFO status and control registers. */ -#define USB_DEVICE_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20) -/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; +#define USB_DEVICE_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) +/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; * JTAT in fifo counter. */ -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_S) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; +#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S) +#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 +/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; * 1: JTAG in fifo is empty. */ -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_S) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 +/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; * 1: JTAG in fifo is full. */ -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_S) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_S 3 -/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; +#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3 +/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; * JTAT out fifo counter. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_S 4 -/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; +#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S) +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4 +/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; * 1: JTAG out fifo is empty. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 -/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 +/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; * 1: JTAG out fifo is full. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7 +/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; * Write 1 to reset JTAG in fifo. */ -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_S) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_S 8 -/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8 +/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; * Write 1 to reset JTAG out fifo. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_S 9 +#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 /** USB_DEVICE_FRAM_NUM_REG register * Last received SOF frame index register. */ -#define USB_DEVICE_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24) -/** USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; +#define USB_DEVICE_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) +/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; * Frame index of received SOF frame. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU -#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU -#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S) +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 /** USB_DEVICE_IN_EP0_ST_REG register * Control IN endpoint status information. */ -#define USB_DEVICE_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28) -/** USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; +#define USB_DEVICE_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) +/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S) +#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of IN endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of IN endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 /** USB_DEVICE_IN_EP1_ST_REG register * CDC-ACM IN endpoint status information. */ -#define USB_DEVICE_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2c) -/** USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; +#define USB_DEVICE_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) +/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S) +#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of IN endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of IN endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 /** USB_DEVICE_IN_EP2_ST_REG register * CDC-ACM interrupt IN endpoint status information. */ -#define USB_DEVICE_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30) -/** USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; +#define USB_DEVICE_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) +/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S) +#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of IN endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of IN endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 /** USB_DEVICE_IN_EP3_ST_REG register * JTAG IN endpoint status information. */ -#define USB_DEVICE_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34) -/** USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; +#define USB_DEVICE_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) +/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 3. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S) +#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of IN endpoint 3. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of IN endpoint 3. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 /** USB_DEVICE_OUT_EP0_ST_REG register * Control OUT endpoint status information. */ -#define USB_DEVICE_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38) -/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; +#define USB_DEVICE_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) +/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_M (USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is * detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of OUT endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 /** USB_DEVICE_OUT_EP1_ST_REG register * CDC-ACM OUT endpoint status information. */ -#define USB_DEVICE_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3c) -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; +#define USB_DEVICE_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) +/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is * detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of OUT endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; * Data count in OUT endpoint 1 when one packet is received. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 /** USB_DEVICE_OUT_EP2_ST_REG register * JTAG OUT endpoint status information. */ -#define USB_DEVICE_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40) -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; +#define USB_DEVICE_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) +/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is * detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of OUT endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 /** USB_DEVICE_MISC_CONF_REG register * Clock enable control */ -#define USB_DEVICE_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44) -/** USB_DEVICE_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) +/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes * registers. */ -#define USB_DEVICE_SERIAL_JTAG_CLK_EN (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_CLK_EN_M (USB_DEVICE_SERIAL_JTAG_CLK_EN_V << USB_DEVICE_SERIAL_JTAG_CLK_EN_S) -#define USB_DEVICE_SERIAL_JTAG_CLK_EN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CLK_EN_S 0 +#define USB_SERIAL_JTAG_CLK_EN (BIT(0)) +#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S) +#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_CLK_EN_S 0 -/** USB_DEVICE_MEM_CONF_REG register +/** USB_SERIAL_JTAG_MEM_CONF_REG register * Memory power control */ -#define USB_DEVICE_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48) -/** USB_DEVICE_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) +/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; * 1: power down usb memory. */ -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_M (USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_V << USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_S) -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_S 0 -/** USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; +#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0)) +#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S) +#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_PD_S 0 +/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; * 1: Force clock on for usb memory. */ -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_S) -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 /** USB_DEVICE_CHIP_RST_REG register * CDC-ACM chip reset control. */ -#define USB_DEVICE_CHIP_RST_REG (DR_REG_USB_DEVICE_BASE + 0x4c) -/** USB_DEVICE_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; +#define USB_DEVICE_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c) +/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. */ -#define USB_DEVICE_SERIAL_JTAG_RTS (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_RTS_M (USB_DEVICE_SERIAL_JTAG_RTS_V << USB_DEVICE_SERIAL_JTAG_RTS_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_S 0 -/** USB_DEVICE_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_RTS (BIT(0)) +#define USB_SERIAL_JTAG_RTS_M (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S) +#define USB_SERIAL_JTAG_RTS_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_S 0 +/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. */ -#define USB_DEVICE_SERIAL_JTAG_DTR (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_DTR_M (USB_DEVICE_SERIAL_JTAG_DTR_V << USB_DEVICE_SERIAL_JTAG_DTR_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_S 1 -/** USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_DTR (BIT(1)) +#define USB_SERIAL_JTAG_DTR_M (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S) +#define USB_SERIAL_JTAG_DTR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_S 1 +/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; * Set this bit to disable chip reset from usb serial channel to reset chip. */ -#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) -#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 /** USB_DEVICE_SET_LINE_CODE_W0_REG register * W0 of SET_LINE_CODING command. */ -#define USB_DEVICE_SET_LINE_CODE_W0_REG (DR_REG_USB_DEVICE_BASE + 0x50) -/** USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; +#define USB_DEVICE_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50) +/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; * The value of dwDTERate set by host through SET_LINE_CODING command. */ -#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_M (USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_V << USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_S) -#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_S 0 +#define USB_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_M (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_S 0 /** USB_DEVICE_SET_LINE_CODE_W1_REG register * W1 of SET_LINE_CODING command. */ -#define USB_DEVICE_SET_LINE_CODE_W1_REG (DR_REG_USB_DEVICE_BASE + 0x54) -/** USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; +#define USB_DEVICE_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54) +/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; * The value of bCharFormat set by host through SET_LINE_CODING command. */ -#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_M (USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_V << USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_S) -#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_S 0 -/** USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; +#define USB_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_M (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_S 0 +/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; * The value of bParityTpye set by host through SET_LINE_CODING command. */ -#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_M (USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_V << USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_S) -#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_S 8 -/** USB_DEVICE_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; +#define USB_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_M (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; * The value of bDataBits set by host through SET_LINE_CODING command. */ -#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_M (USB_DEVICE_SERIAL_JTAG_BDATA_BITS_V << USB_DEVICE_SERIAL_JTAG_BDATA_BITS_S) -#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_S 16 +#define USB_SERIAL_JTAG_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_M (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S) +#define USB_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_S 16 /** USB_DEVICE_GET_LINE_CODE_W0_REG register * W0 of GET_LINE_CODING command. */ -#define USB_DEVICE_GET_LINE_CODE_W0_REG (DR_REG_USB_DEVICE_BASE + 0x58) -/** USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; +#define USB_DEVICE_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58) +/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; * The value of dwDTERate set by software which is requested by GET_LINE_CODING * command. */ -#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_S) -#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 /** USB_DEVICE_GET_LINE_CODE_W1_REG register * W1 of GET_LINE_CODING command. */ -#define USB_DEVICE_GET_LINE_CODE_W1_REG (DR_REG_USB_DEVICE_BASE + 0x5c) -/** USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; +#define USB_DEVICE_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c) +/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; * The value of bCharFormat set by software which is requested by GET_LINE_CODING * command. */ -#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_M (USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_V << USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_S) -#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_S 0 -/** USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; +#define USB_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_M (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S) +#define USB_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_S 0 +/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; * The value of bParityTpye set by software which is requested by GET_LINE_CODING * command. */ -#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_S) -#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 -/** USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; * The value of bDataBits set by software which is requested by GET_LINE_CODING * command. */ -#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_S) -#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 /** USB_DEVICE_CONFIG_UPDATE_REG register * Configuration registers' value update */ -#define USB_DEVICE_CONFIG_UPDATE_REG (DR_REG_USB_DEVICE_BASE + 0x60) -/** USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; +#define USB_DEVICE_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60) +/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; * Write 1 to this register would update the value of configure registers from APB * clock domain to 48MHz clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_M (USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_V << USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_S) -#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_S 0 +#define USB_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_M (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U +#define USB_SERIAL_JTAG_CONFIG_UPDATE_S 0 /** USB_DEVICE_SER_AFIFO_CONFIG_REG register * Serial AFIFO configure register */ -#define USB_DEVICE_SER_AFIFO_CONFIG_REG (DR_REG_USB_DEVICE_BASE + 0x64) -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64) +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; * Write 1 to reset CDC_ACM IN async FIFO write clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; * Write 1 to reset CDC_ACM IN async FIFO read clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; * CDC_ACM OUTPUT async FIFO empty signal in read clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; * CDC_ACM OUT IN async FIFO empty signal in write clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 /** USB_DEVICE_BUS_RESET_ST_REG register * USB Bus reset status register */ -#define USB_DEVICE_BUS_RESET_ST_REG (DR_REG_USB_DEVICE_BASE + 0x68) -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; +#define USB_DEVICE_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68) +/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus * reset is released. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 /** USB_DEVICE_ECO_LOW_48_REG register * Reserved. */ -#define USB_DEVICE_ECO_LOW_48_REG (DR_REG_USB_DEVICE_BASE + 0x6c) -/** USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0; +#define USB_DEVICE_ECO_LOW_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c) +/** USB_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_S) -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_S 0 +#define USB_SERIAL_JTAG_RND_ECO_LOW_48 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_48_M (USB_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_SERIAL_JTAG_RND_ECO_LOW_48_S) +#define USB_SERIAL_JTAG_RND_ECO_LOW_48_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_48_S 0 /** USB_DEVICE_ECO_HIGH_48_REG register * Reserved. */ -#define USB_DEVICE_ECO_HIGH_48_REG (DR_REG_USB_DEVICE_BASE + 0x70) -/** USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295; +#define USB_DEVICE_ECO_HIGH_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70) +/** USB_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_S) -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_S 0 +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_M (USB_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_SERIAL_JTAG_RND_ECO_HIGH_48_S) +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_S 0 /** USB_DEVICE_ECO_CELL_CTRL_48_REG register * Reserved. */ -#define USB_DEVICE_ECO_CELL_CTRL_48_REG (DR_REG_USB_DEVICE_BASE + 0x74) -/** USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0; +#define USB_DEVICE_ECO_CELL_CTRL_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x74) +/** USB_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48 (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_M (USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_V << USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_S) -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_S 0 -/** USB_DEVICE_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_RDN_RESULT_48 (BIT(0)) +#define USB_SERIAL_JTAG_RDN_RESULT_48_M (USB_SERIAL_JTAG_RDN_RESULT_48_V << USB_SERIAL_JTAG_RDN_RESULT_48_S) +#define USB_SERIAL_JTAG_RDN_RESULT_48_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_RESULT_48_S 0 +/** USB_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48 (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_M (USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_V << USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_S) -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_S 1 +#define USB_SERIAL_JTAG_RDN_ENA_48 (BIT(1)) +#define USB_SERIAL_JTAG_RDN_ENA_48_M (USB_SERIAL_JTAG_RDN_ENA_48_V << USB_SERIAL_JTAG_RDN_ENA_48_S) +#define USB_SERIAL_JTAG_RDN_ENA_48_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_ENA_48_S 1 /** USB_DEVICE_ECO_LOW_APB_REG register * Reserved. */ -#define USB_DEVICE_ECO_LOW_APB_REG (DR_REG_USB_DEVICE_BASE + 0x78) -/** USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0; +#define USB_DEVICE_ECO_LOW_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x78) +/** USB_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_S) -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_S 0 +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_M (USB_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_SERIAL_JTAG_RND_ECO_LOW_APB_S) +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_S 0 /** USB_DEVICE_ECO_HIGH_APB_REG register * Reserved. */ -#define USB_DEVICE_ECO_HIGH_APB_REG (DR_REG_USB_DEVICE_BASE + 0x7c) -/** USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295; +#define USB_DEVICE_ECO_HIGH_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x7c) +/** USB_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_S) -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_S 0 +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_M (USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S) +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S 0 /** USB_DEVICE_ECO_CELL_CTRL_APB_REG register * Reserved. */ -#define USB_DEVICE_ECO_CELL_CTRL_APB_REG (DR_REG_USB_DEVICE_BASE + 0x80) -/** USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0; +#define USB_DEVICE_ECO_CELL_CTRL_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) +/** USB_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_M (USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_V << USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_S) -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_S 0 -/** USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_RDN_RESULT_APB (BIT(0)) +#define USB_SERIAL_JTAG_RDN_RESULT_APB_M (USB_SERIAL_JTAG_RDN_RESULT_APB_V << USB_SERIAL_JTAG_RDN_RESULT_APB_S) +#define USB_SERIAL_JTAG_RDN_RESULT_APB_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_RESULT_APB_S 0 +/** USB_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_M (USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_V << USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_S) -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_S 1 +#define USB_SERIAL_JTAG_RDN_ENA_APB (BIT(1)) +#define USB_SERIAL_JTAG_RDN_ENA_APB_M (USB_SERIAL_JTAG_RDN_ENA_APB_V << USB_SERIAL_JTAG_RDN_ENA_APB_S) +#define USB_SERIAL_JTAG_RDN_ENA_APB_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_ENA_APB_S 1 /** USB_DEVICE_SRAM_CTRL_REG register * PPA SRAM Control Register */ -#define USB_DEVICE_SRAM_CTRL_REG (DR_REG_USB_DEVICE_BASE + 0x84) -/** USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; +#define USB_DEVICE_SRAM_CTRL_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x84) +/** USB_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; * Control signals */ -#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL 0x00003FFFU -#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_M (USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_S) -#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_V 0x00003FFFU -#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_S 0 +#define USB_SERIAL_JTAG_MEM_AUX_CTRL 0x00003FFFU +#define USB_SERIAL_JTAG_MEM_AUX_CTRL_M (USB_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_SERIAL_JTAG_MEM_AUX_CTRL_S) +#define USB_SERIAL_JTAG_MEM_AUX_CTRL_V 0x00003FFFU +#define USB_SERIAL_JTAG_MEM_AUX_CTRL_S 0 /** USB_DEVICE_DATE_REG register * Date register */ -#define USB_DEVICE_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x88) -/** USB_DEVICE_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752; +#define USB_DEVICE_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x88) +/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752; * register version. */ -#define USB_DEVICE_SERIAL_JTAG_DATE 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_DATE_M (USB_DEVICE_SERIAL_JTAG_DATE_V << USB_DEVICE_SERIAL_JTAG_DATE_S) -#define USB_DEVICE_SERIAL_JTAG_DATE_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_DATE_S 0 +#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S) +#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_S 0 #ifdef __cplusplus } diff --git a/components/ulp/test_apps/.build-test-rules.yml b/components/ulp/test_apps/.build-test-rules.yml index 8045f63c2e..a8eeee9bd7 100644 --- a/components/ulp/test_apps/.build-test-rules.yml +++ b/components/ulp/test_apps/.build-test-rules.yml @@ -5,10 +5,17 @@ components/ulp/test_apps/lp_core/lp_core_basic_tests: - if: SOC_LP_CORE_SUPPORTED != 1 - if: CONFIG_NAME == "xtal" and SOC_CLK_LP_FAST_SUPPORT_XTAL != 1 - if: CONFIG_NAME == "lp_vad" and SOC_LP_VAD_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14368 components/ulp/test_apps/lp_core/lp_core_hp_uart: disable: - if: SOC_LP_CORE_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14422 components/ulp/test_apps/ulp_fsm: enable: diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/README.md b/components/ulp/test_apps/lp_core/lp_core_basic_tests/README.md index 59db987a22..86c1aea12b 100644 --- a/components/ulp/test_apps/lp_core/lp_core_basic_tests/README.md +++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/README.md @@ -1,3 +1,3 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | +| ----------------- | -------- | -------- | diff --git a/components/ulp/test_apps/lp_core/lp_core_hp_uart/pytest_lp_core_hp_uart.py b/components/ulp/test_apps/lp_core/lp_core_hp_uart/pytest_lp_core_hp_uart.py index 92d70c7aff..34dc719f41 100644 --- a/components/ulp/test_apps/lp_core/lp_core_hp_uart/pytest_lp_core_hp_uart.py +++ b/components/ulp/test_apps/lp_core/lp_core_hp_uart/pytest_lp_core_hp_uart.py @@ -8,6 +8,7 @@ from pytest_embedded_idf.utils import soc_filtered_targets @pytest.mark.generic @idf_parametrize('target', soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1'), indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_hp_uart_print(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') dut.write('"lp-print can output to hp-uart"') @@ -18,6 +19,7 @@ def test_lp_core_hp_uart_print(dut: Dut) -> None: @pytest.mark.generic @idf_parametrize('target', soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1'), indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_panic(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') dut.write('"LP-Core panic"') @@ -29,6 +31,7 @@ def test_lp_core_panic(dut: Dut) -> None: @pytest.mark.generic @idf_parametrize('target', soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1'), indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_shared_mem(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') dut.write('"LP-Core Shared-mem"') @@ -47,6 +50,7 @@ def test_lp_core_shared_mem(dut: Dut) -> None: @pytest.mark.generic @idf_parametrize('target', ['esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_lp_rom(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') dut.write('"LP-Core LP-ROM"') diff --git a/examples/cxx/.build-test-rules.yml b/examples/cxx/.build-test-rules.yml new file mode 100644 index 0000000000..9d21130a1c --- /dev/null +++ b/examples/cxx/.build-test-rules.yml @@ -0,0 +1,13 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +examples/cxx/exceptions: + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14402 + +examples/cxx/rtti: + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14402 diff --git a/examples/cxx/exceptions/pytest_examples_cxx_exceptions.py b/examples/cxx/exceptions/pytest_examples_cxx_exceptions.py index f62a8ae866..b2df9354f1 100644 --- a/examples/cxx/exceptions/pytest_examples_cxx_exceptions.py +++ b/examples/cxx/exceptions/pytest_examples_cxx_exceptions.py @@ -7,6 +7,7 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.generic @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14402') def test_examples_cpp_exceptions(dut: IdfDut) -> None: lines = [ 'app_main starting', diff --git a/examples/cxx/rtti/pytest_examples_cxx_rtti.py b/examples/cxx/rtti/pytest_examples_cxx_rtti.py index e6d81bd99b..705acc6249 100644 --- a/examples/cxx/rtti/pytest_examples_cxx_rtti.py +++ b/examples/cxx/rtti/pytest_examples_cxx_rtti.py @@ -7,6 +7,7 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.generic @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14402') def test_cpp_rtti_example(dut: IdfDut) -> None: dut.expect_exact('Type name of std::cout is: std::ostream') dut.expect_exact('Type name of std::cin is: std::istream') diff --git a/examples/ethernet/.build-test-rules.yml b/examples/ethernet/.build-test-rules.yml index be7ea7711f..be1747c0ce 100644 --- a/examples/ethernet/.build-test-rules.yml +++ b/examples/ethernet/.build-test-rules.yml @@ -4,7 +4,7 @@ examples/ethernet/basic: enable: - if: INCLUDE_DEFAULT == 1 disable: - - if: IDF_TARGET not in ["esp32", "esp32p4"] + - if: IDF_TARGET not in ["esp32"] # TODO: IDF-14365 depends_components: - esp_eth - esp_netif @@ -17,8 +17,7 @@ examples/ethernet/iperf: - if: IDF_TARGET in ["esp32h21", "esp32h4"] temporary: true reason: not supported yet # TODO: [ESP32H21] IDF-11581 [ESP32H4] IDF-12360 - disable_test: - - if: IDF_TARGET not in ["esp32", "esp32p4"] + - if: IDF_TARGET not in ["esp32"] # TODO: IDF-14365 temporary: true reason: lack of runners depends_components: diff --git a/examples/ethernet/basic/README.md b/examples/ethernet/basic/README.md index a6f556be70..1c2013fa22 100644 --- a/examples/ethernet/basic/README.md +++ b/examples/ethernet/basic/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-P4 | -| ----------------- | ----- | -------- | +| Supported Targets | ESP32 | +| ----------------- | ----- | # Basic Ethernet Example (See the README.md file in the upper level 'examples' directory for more information about examples.) diff --git a/examples/ethernet/iperf/README.md b/examples/ethernet/iperf/README.md index ea5af8a6f6..0005ee58d2 100644 --- a/examples/ethernet/iperf/README.md +++ b/examples/ethernet/iperf/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | +| ----------------- | ----- | # Ethernet iperf Example diff --git a/examples/peripherals/.build-test-rules.yml b/examples/peripherals/.build-test-rules.yml index 0bf59d30a5..99ed89538b 100644 --- a/examples/peripherals/.build-test-rules.yml +++ b/examples/peripherals/.build-test-rules.yml @@ -10,11 +10,19 @@ examples/peripherals/adc/continuous_read: disable: - if: SOC_ADC_DMA_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14357 <<: *adc_dependencies examples/peripherals/adc/oneshot_read: disable: - if: SOC_ADC_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14357 <<: *adc_dependencies examples/peripherals/analog_comparator: @@ -523,24 +531,40 @@ examples/peripherals/touch_sensor/touch_sens_sleep: examples/peripherals/twai/cybergear: disable: - if: SOC_TWAI_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14393 depends_components: - esp_driver_twai examples/peripherals/twai/twai_error_recovery: disable: - if: SOC_TWAI_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14393 depends_components: - esp_driver_twai examples/peripherals/twai/twai_network: disable: - if: SOC_TWAI_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14393 depends_components: - esp_driver_twai examples/peripherals/twai/twai_utils: disable: - if: SOC_TWAI_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14393 depends_components: - esp_driver_twai @@ -560,9 +584,9 @@ examples/peripherals/usb/device: disable: - if: SOC_USB_OTG_SUPPORTED != 1 disable_test: - - if: IDF_TARGET not in ["esp32s2", "esp32p4"] + - if: IDF_TARGET not in ["esp32s2"] temporary: true - reason: lack of runners with usb_device tag + reason: lack of runners with usb_device tag # TODO: IDF-14369 depends_components: - fatfs depends_filepatterns: diff --git a/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py b/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py index c7793c69a5..dbc5321751 100644 --- a/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py +++ b/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py @@ -11,6 +11,7 @@ from pytest_embedded_idf.utils import idf_parametrize ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c5', 'esp32p4', 'esp32c61'], indirect=['target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14357') def test_adc_continuous(dut: Dut) -> None: res = dut.expect(r'TASK: ret is 0, ret_num is (\d+) bytes') num = res.group(1).decode('utf8') diff --git a/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py b/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py index 17e15ba727..5b8ecc80bc 100644 --- a/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py +++ b/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py @@ -11,6 +11,7 @@ from pytest_embedded_idf.utils import idf_parametrize ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c5', 'esp32p4', 'esp32c61'], indirect=['target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14357') def test_adc_oneshot(dut: Dut) -> None: dut.expect(r'EXAMPLE: ADC1 Channel\[(\d+)\] Raw Data: (\d+)', timeout=5) diff --git a/examples/peripherals/twai/twai_utils/pytest_twai_utils.py b/examples/peripherals/twai/twai_utils/pytest_twai_utils.py index bfa808a9da..8168a55cfa 100644 --- a/examples/peripherals/twai/twai_utils/pytest_twai_utils.py +++ b/examples/peripherals/twai/twai_utils/pytest_twai_utils.py @@ -646,6 +646,7 @@ def test_twai_range_filters(twai: TwaiTestHelper) -> None: @pytest.mark.twai_std @pytest.mark.temp_skip_ci(targets=['esp32h4'], reason='no runner') @idf_parametrize('target', soc_filtered_targets('SOC_TWAI_SUPPORTED == 1'), indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14393') def test_twai_external_communication(twai: TwaiTestHelper, can_manager: CanBusManager) -> None: """ Test bidirectional communication with external CAN interface (hardware level). diff --git a/examples/peripherals/usb/device/tusb_composite_msc_serialdevice/pytest_usb_device_composite.py b/examples/peripherals/usb/device/tusb_composite_msc_serialdevice/pytest_usb_device_composite.py index 2c42a9235a..68705ecc1f 100644 --- a/examples/peripherals/usb/device/tusb_composite_msc_serialdevice/pytest_usb_device_composite.py +++ b/examples/peripherals/usb/device/tusb_composite_msc_serialdevice/pytest_usb_device_composite.py @@ -12,6 +12,7 @@ from serial.tools.list_ports import comports @pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='lack of runners with usb_device tag') @pytest.mark.usb_device @idf_parametrize('target', ['esp32s2', 'esp32s3', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14369') def test_usb_composite_device_serial_example(dut: Dut) -> None: dut.expect_exact('Hello World!') dut.expect_exact('USB Composite initialization') @@ -23,7 +24,7 @@ def test_usb_composite_device_serial_example(dut: Dut) -> None: for port, _, hwid in ports: if '303A:4001' in hwid: with Serial(port) as s: - s.write('text\r\n'.encode()) # Write dummy text to COM port + s.write(b'text\r\n') # Write dummy text to COM port dut.expect_exact('Data from channel 0:') # Check ESP log dut.expect_exact('|text..|') res = s.readline() # Check COM echo diff --git a/examples/peripherals/usb/device/tusb_console/pytest_usb_device_console.py b/examples/peripherals/usb/device/tusb_console/pytest_usb_device_console.py index 8860dbff92..ef534d52f0 100644 --- a/examples/peripherals/usb/device/tusb_console/pytest_usb_device_console.py +++ b/examples/peripherals/usb/device/tusb_console/pytest_usb_device_console.py @@ -12,6 +12,7 @@ from serial.tools.list_ports import comports @pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='lack of runners with usb_device tag') @pytest.mark.usb_device @idf_parametrize('target', ['esp32s2', 'esp32s3', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14369') def test_usb_device_console_example(dut: Dut) -> None: dut.expect_exact('USB initialization DONE') dut.expect_exact('example: log -> UART') diff --git a/examples/peripherals/usb/device/tusb_hid/pytest_usb_device_hid.py b/examples/peripherals/usb/device/tusb_hid/pytest_usb_device_hid.py index 986b293fe8..a896e566b8 100644 --- a/examples/peripherals/usb/device/tusb_hid/pytest_usb_device_hid.py +++ b/examples/peripherals/usb/device/tusb_hid/pytest_usb_device_hid.py @@ -8,6 +8,7 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='lack of runners with usb_device tag') @pytest.mark.usb_device @idf_parametrize('target', ['esp32s2', 'esp32s3', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14369') def test_usb_device_hid_example(dut: Dut) -> None: dut.expect_exact('USB initialization DONE') dut.expect_exact('Sending Keyboard report') diff --git a/examples/peripherals/usb/device/tusb_midi/pytest_usb_device_midi.py b/examples/peripherals/usb/device/tusb_midi/pytest_usb_device_midi.py index 9c6a576246..3490e43add 100644 --- a/examples/peripherals/usb/device/tusb_midi/pytest_usb_device_midi.py +++ b/examples/peripherals/usb/device/tusb_midi/pytest_usb_device_midi.py @@ -8,6 +8,7 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='lack of runners with usb_device tag') @pytest.mark.usb_device @idf_parametrize('target', ['esp32s2', 'esp32s3', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14369') def test_usb_device_midi_example(dut: Dut) -> None: dut.expect_exact('USB initialization DONE') dut.expect_exact('MIDI write task init') diff --git a/examples/peripherals/usb/device/tusb_msc/pytest_usb_device_msc.py b/examples/peripherals/usb/device/tusb_msc/pytest_usb_device_msc.py index 3503b0e62d..c099ac0f41 100644 --- a/examples/peripherals/usb/device/tusb_msc/pytest_usb_device_msc.py +++ b/examples/peripherals/usb/device/tusb_msc/pytest_usb_device_msc.py @@ -8,6 +8,7 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='lack of runners with usb_device tag') @pytest.mark.usb_device @idf_parametrize('target', ['esp32s2', 'esp32s3', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14369') def test_usb_device_msc_example(dut: Dut) -> None: dut.expect('Mount storage') dut.expect('TinyUSB Driver installed') diff --git a/examples/peripherals/usb/device/tusb_serial_device/pytest_usb_device_serial.py b/examples/peripherals/usb/device/tusb_serial_device/pytest_usb_device_serial.py index f1dd71ef11..ed4f4bcccc 100644 --- a/examples/peripherals/usb/device/tusb_serial_device/pytest_usb_device_serial.py +++ b/examples/peripherals/usb/device/tusb_serial_device/pytest_usb_device_serial.py @@ -12,6 +12,7 @@ from serial.tools.list_ports import comports @pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='lack of runners with usb_device tag') @pytest.mark.usb_device @idf_parametrize('target', ['esp32s2', 'esp32s3', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14369') def test_usb_device_serial_example(dut: Dut) -> None: dut.expect_exact('USB initialization DONE') sleep(2) # Some time for the OS to enumerate our USB device @@ -21,7 +22,7 @@ def test_usb_device_serial_example(dut: Dut) -> None: for port, _, hwid in ports: if '303A:4001' in hwid: with Serial(port) as s: - s.write('text\r\n'.encode()) # Write dummy text to COM port + s.write(b'text\r\n') # Write dummy text to COM port dut.expect_exact('Data from channel 0:') # Check ESP log dut.expect_exact('|text..|') res = s.readline() # Check COM echo diff --git a/examples/security/.build-test-rules.yml b/examples/security/.build-test-rules.yml index 1849b89f52..ce90a603d5 100644 --- a/examples/security/.build-test-rules.yml +++ b/examples/security/.build-test-rules.yml @@ -3,6 +3,9 @@ examples/security/flash_encryption: disable: - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14367 disable_test: - if: IDF_TARGET in ["esp32s2", "esp32s3", "esp32c6", "esp32h2", "esp32c2", "esp32c5", "esp32c61"] temporary: true diff --git a/examples/security/flash_encryption/README.md b/examples/security/flash_encryption/README.md index 54d524739d..1dda7e4075 100644 --- a/examples/security/flash_encryption/README.md +++ b/examples/security/flash_encryption/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | # Flash Encryption diff --git a/examples/storage/.build-test-rules.yml b/examples/storage/.build-test-rules.yml index 77336032d6..9b2c9ca969 100644 --- a/examples/storage/.build-test-rules.yml +++ b/examples/storage/.build-test-rules.yml @@ -14,6 +14,10 @@ examples/storage/emmc: enable: - if: IDF_TARGET in ["esp32s3", "esp32p4"] reason: only support on esp32s3 and esp32p4 + disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14356 examples/storage/partition_api/partition_find: depends_components: @@ -82,6 +86,9 @@ examples/storage/sd_card/sdspi: - esp_driver_sdspi disable: - if: SOC_GPSPI_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14363 disable_test: - if: IDF_TARGET not in ["esp32", "esp32s3", "esp32c3", "esp32c5", "esp32p4"] reason: needs special runner, select few typical targets for testing diff --git a/examples/storage/emmc/README.md b/examples/storage/emmc/README.md index 64d85be82f..36404def8d 100644 --- a/examples/storage/emmc/README.md +++ b/examples/storage/emmc/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-P4 | ESP32-S3 | -| ----------------- | -------- | -------- | +| Supported Targets | ESP32-S3 | +| ----------------- | -------- | # eMMC chip example (with SDMMC Host) diff --git a/examples/storage/sd_card/sdspi/README.md b/examples/storage/sd_card/sdspi/README.md index 0386e4d1f7..33ba92d1cb 100644 --- a/examples/storage/sd_card/sdspi/README.md +++ b/examples/storage/sd_card/sdspi/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | # SD Card example (SDSPI) diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml index 8f4d552dc8..e3a6556af9 100644 --- a/examples/system/.build-test-rules.yml +++ b/examples/system/.build-test-rules.yml @@ -1,6 +1,10 @@ # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps examples/system/app_trace_basic: + disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14364 disable_test: - if: IDF_TARGET == "esp32h21" temporary: true @@ -98,6 +102,9 @@ examples/system/gcov: - if: IDF_TARGET == "esp32h4" temporary: true reason: not supported yet #TODO: OCD-1138 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14440 examples/system/heap_task_tracking: disable: @@ -256,6 +263,9 @@ examples/system/sysview_tracing: - if: IDF_TARGET in ["esp32", "esp32s2", "esp32s3", "esp32c2", "esp32c3", "esp32c5", "esp32c61", "esp32c6", "esp32h2", "esp32h21", "esp32h4", "esp32p4"] temporary: true reason: temporarily disabled until the sysview component is published in the component registry + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14364 disable_test: - if: IDF_TARGET == "esp32h21" temporary: true @@ -270,6 +280,9 @@ examples/system/sysview_tracing_heap_log: - if: IDF_TARGET in ["esp32", "esp32s2", "esp32s3", "esp32c2", "esp32c3", "esp32c5", "esp32c61", "esp32c6", "esp32h2", "esp32h21", "esp32h4", "esp32p4"] temporary: true reason: temporarily disabled until the sysview component is published in the component registry + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14364 disable_test: - if: IDF_TARGET == "esp32h21" temporary: true @@ -288,6 +301,10 @@ examples/system/task_watchdog: examples/system/ulp/lp_core/build_system: enable: - if: SOC_LP_CORE_SUPPORTED == 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14422 depends_components: - ulp @@ -308,6 +325,10 @@ examples/system/ulp/lp_core/gpio: examples/system/ulp/lp_core/gpio_intr_pulse_counter: enable: - if: (SOC_LP_CORE_SUPPORTED == 1) and (SOC_ULP_LP_UART_SUPPORTED == 1 and SOC_DEEP_SLEEP_SUPPORTED == 1) + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14422 depends_components: - ulp @@ -320,12 +341,20 @@ examples/system/ulp/lp_core/gpio_wakeup: examples/system/ulp/lp_core/inter_cpu_critical_section/: enable: - if: SOC_LP_CORE_SUPPORTED == 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14422 depends_components: - ulp examples/system/ulp/lp_core/interrupt: enable: - if: SOC_LP_CORE_SUPPORTED == 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14422 depends_components: - ulp @@ -344,6 +373,10 @@ examples/system/ulp/lp_core/lp_i2c: examples/system/ulp/lp_core/lp_mailbox: enable: - if: SOC_LP_CORE_SUPPORTED == 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14422 depends_components: - ulp diff --git a/examples/system/app_trace_basic/README.md b/examples/system/app_trace_basic/README.md index 81adb079a5..9270ccdddb 100644 --- a/examples/system/app_trace_basic/README.md +++ b/examples/system/app_trace_basic/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | # Application Level Tracing Example (Basic) diff --git a/examples/system/gcov/pytest_gcov.py b/examples/system/gcov/pytest_gcov.py index 49e4be994e..16493f4838 100644 --- a/examples/system/gcov/pytest_gcov.py +++ b/examples/system/gcov/pytest_gcov.py @@ -82,5 +82,6 @@ def test_gcov(openocd_dut: 'OpenOCD', dut: IdfDut) -> None: @idf_parametrize( 'target', ['esp32s3', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32p4'], indirect=['target'] ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14440') def test_gcov_usj(openocd_dut: 'OpenOCD', dut: IdfDut) -> None: _test_gcov(openocd_dut, dut) diff --git a/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py b/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py index 4128c2c896..81d9f50a79 100644 --- a/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py +++ b/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py @@ -7,6 +7,7 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.generic @idf_parametrize('target', ['esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14423') def test_ipc_isr_riscv(dut: Dut) -> None: dut.expect_exact('example: Start') dut.expect_exact('example: MSTATUS = 0x11880') diff --git a/examples/system/sysview_tracing/README.md b/examples/system/sysview_tracing/README.md index 22a208cab6..f675c0eaf1 100644 --- a/examples/system/sysview_tracing/README.md +++ b/examples/system/sysview_tracing/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | # Example: Application Level Tracing - SystemView Tracing (sysview_tracing) This test code shows how to perform system-wide behavioral analysis of the program using [SEGGER SystemView tool](https://www.segger.com/products/development-tools/systemview/). diff --git a/examples/system/sysview_tracing_heap_log/README.md b/examples/system/sysview_tracing_heap_log/README.md index 050a5f5fbb..22d00657d0 100644 --- a/examples/system/sysview_tracing_heap_log/README.md +++ b/examples/system/sysview_tracing_heap_log/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | # SystemView Heap and Log Tracing Example diff --git a/examples/system/ulp/lp_core/build_system/pytest_lp_core_build_sys.py b/examples/system/ulp/lp_core/build_system/pytest_lp_core_build_sys.py index b9089f97eb..498d68c6b5 100644 --- a/examples/system/ulp/lp_core/build_system/pytest_lp_core_build_sys.py +++ b/examples/system/ulp/lp_core/build_system/pytest_lp_core_build_sys.py @@ -7,5 +7,6 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.generic @idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_build_sys(dut: IdfDut) -> None: dut.expect('Sum calculated by ULP using external library func: 11') diff --git a/examples/system/ulp/lp_core/gpio_intr_pulse_counter/pytest_lp_core_pcnt.py b/examples/system/ulp/lp_core/gpio_intr_pulse_counter/pytest_lp_core_pcnt.py index 8b3e00f60f..2885f81958 100644 --- a/examples/system/ulp/lp_core/gpio_intr_pulse_counter/pytest_lp_core_pcnt.py +++ b/examples/system/ulp/lp_core/gpio_intr_pulse_counter/pytest_lp_core_pcnt.py @@ -9,6 +9,7 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.generic @idf_parametrize('target', ['esp32c6', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_pcnt(dut: Dut) -> None: res = dut.expect(r'ULP will wake up processor after every (\d+) pulses') wakeup_limit = res.group(1).decode('utf-8') diff --git a/examples/system/ulp/lp_core/inter_cpu_critical_section/pytest_lp_core_critical_section.py b/examples/system/ulp/lp_core/inter_cpu_critical_section/pytest_lp_core_critical_section.py index 8fabae0eb9..0562a97061 100644 --- a/examples/system/ulp/lp_core/inter_cpu_critical_section/pytest_lp_core_critical_section.py +++ b/examples/system/ulp/lp_core/inter_cpu_critical_section/pytest_lp_core_critical_section.py @@ -16,6 +16,7 @@ def test_lp_core_critical_section_main_1_task(dut: Dut) -> None: @pytest.mark.generic @idf_parametrize('target', ['esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_critical_section_main_2_tasks(dut: Dut) -> None: dut.expect("LP CPU's increment starts, shared counter = 0") dut.expect(r'core 0 started, cnt = \d+') diff --git a/examples/system/ulp/lp_core/interrupt/pytest_lp_core_intr.py b/examples/system/ulp/lp_core/interrupt/pytest_lp_core_intr.py index 622198c941..a3c971dffd 100644 --- a/examples/system/ulp/lp_core/interrupt/pytest_lp_core_intr.py +++ b/examples/system/ulp/lp_core/interrupt/pytest_lp_core_intr.py @@ -7,5 +7,6 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.generic @idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_intr(dut: Dut) -> None: dut.expect('Triggered 10 interrupts on the LP-Core, LP-Core received 10 interrupts') diff --git a/examples/system/ulp/lp_core/lp_mailbox/pytest_lp_mailbox.py b/examples/system/ulp/lp_core/lp_mailbox/pytest_lp_mailbox.py index dcaa74d705..ae94f96887 100644 --- a/examples/system/ulp/lp_core/lp_mailbox/pytest_lp_mailbox.py +++ b/examples/system/ulp/lp_core/lp_mailbox/pytest_lp_mailbox.py @@ -7,6 +7,7 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.generic @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_mailbox(dut: Dut) -> None: # Wait for LP core to be loaded and running dut.expect_exact('LP Mailbox initialized successfully') diff --git a/pytest.ini b/pytest.ini index 2cab870a03..3ebb50c851 100644 --- a/pytest.ini +++ b/pytest.ini @@ -129,4 +129,5 @@ env_markers = ram_app: ram_app runners esp32c3eco7: esp32c3 major version(v1.1) chips esp32c2eco4: esp32c2 major version(v2.0) chips - recovery_bootloader: Runner with recovery bootloader offset set in eFuse + recovery_bootloader: Runner with recovery bootloader offset set in + esp32p4_eco4: Runner with esp32p4 eco4 connected diff --git a/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml b/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml index 1683f128d7..05efc0b22f 100644 --- a/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml +++ b/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml @@ -24,7 +24,5 @@ no_runner_tags: - esp32c6,jtag - esp32c61,jtag - esp32h2,jtag - - esp32p4,* - esp32p4,jtag - - esp32p4_2,* - esp32s2,usb_host_flash_disk diff --git a/tools/test_apps/system/.build-test-rules.yml b/tools/test_apps/system/.build-test-rules.yml index fe4c7d8a96..a55d36ade3 100644 --- a/tools/test_apps/system/.build-test-rules.yml +++ b/tools/test_apps/system/.build-test-rules.yml @@ -39,9 +39,9 @@ tools/test_apps/system/build_tests/trax_esp32s2: tools/test_apps/system/clang_build_test: enable: - - if: IDF_TARGET in ["esp32", "esp32s2", "esp32s3", "esp32c2", "esp32c3", "esp32c5", "esp32c6", "esp32h2", "esp32p4"] + - if: IDF_TARGET in ["esp32", "esp32s2", "esp32s3", "esp32c2", "esp32c3", "esp32c5", "esp32c6", "esp32h2"] temporary: true - reason: the other targets are not supported yet + reason: the other targets are not supported yet, esp32p4 # TODO: IDF-14355 tools/test_apps/system/cxx_no_except: enable: @@ -53,6 +53,10 @@ tools/test_apps/system/eh_frame: disable: - if: IDF_TARGET in ["esp32", "esp32s2", "esp32s3", "linux"] reason: Only relevant for riscv targets + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14424 tools/test_apps/system/esp_intr_dump: @@ -90,6 +94,10 @@ tools/test_apps/system/gdb_loadable_elf: tools/test_apps/system/init_array: enable: - if: INCLUDE_DEFAULT == 1 or IDF_TARGET == "linux" + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14425 depends_components: - esp_system depends_filepatterns: @@ -129,7 +137,15 @@ tools/test_apps/system/no_embedded_paths: tools/test_apps/system/panic: enable: - - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32p4", "esp32c61", "esp32h21"] # preview targets + - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32p4"] # preview targets + disable: + - if: IDF_TARGET == "esp32p4" # TODO: IDF-14348 + +tools/test_apps/system/ram_loadable_app: + disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14370 tools/test_apps/system/rtc_mem_reserve: enable: diff --git a/tools/test_apps/system/clang_build_test/README.md b/tools/test_apps/system/clang_build_test/README.md index c410436a3a..99461edd60 100644 --- a/tools/test_apps/system/clang_build_test/README.md +++ b/tools/test_apps/system/clang_build_test/README.md @@ -1,4 +1,4 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | This project is for testing if the application can be built with Clang toolchain. diff --git a/tools/test_apps/system/eh_frame/pytest_eh_frame.py b/tools/test_apps/system/eh_frame/pytest_eh_frame.py index f70b715e35..92de8630dc 100644 --- a/tools/test_apps/system/eh_frame/pytest_eh_frame.py +++ b/tools/test_apps/system/eh_frame/pytest_eh_frame.py @@ -9,9 +9,10 @@ from pytest_embedded_idf.utils import idf_parametrize @idf_parametrize( 'target', ['esp32c2', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32p4'], indirect=['target'] ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14424') def test_eh_frame_wdt(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') - dut.confirm_write('"Test task wdt can print backtrace with eh-frame"', expect_str=f'Running') + dut.confirm_write('"Test task wdt can print backtrace with eh-frame"', expect_str='Running') # Expect a backtrace which is at least 3 PC-SP pairs deep dut.expect(r'Backtrace: (0x[a-fA-F0-9]+:0x[a-fA-F0-9]+\s*){3,}') @@ -21,9 +22,10 @@ def test_eh_frame_wdt(dut: Dut) -> None: @idf_parametrize( 'target', ['esp32c2', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32p4'], indirect=['target'] ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14424') def test_eh_frame_panic(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') - dut.confirm_write('"Test panic can print backtrace with eh-frame"', expect_str=f'Running') + dut.confirm_write('"Test panic can print backtrace with eh-frame"', expect_str='Running') # Expect a backtrace which is at least 3 PC-SP pairs deep dut.expect(r'Backtrace: (0x[a-fA-F0-9]+:0x[a-fA-F0-9]+\s*){3,}') diff --git a/tools/test_apps/system/init_array/pytest_init_array.py b/tools/test_apps/system/init_array/pytest_init_array.py index fe367c7998..df3b1ae8e8 100644 --- a/tools/test_apps/system/init_array/pytest_init_array.py +++ b/tools/test_apps/system/init_array/pytest_init_array.py @@ -7,6 +7,7 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.generic @idf_parametrize('target', ['supported_targets', 'preview_targets', 'linux'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14425') def test_init_array(dut: Dut) -> None: dut.expect_exact('preinit_func') dut.expect_exact('init_prio_101') diff --git a/tools/test_apps/system/panic/README.md b/tools/test_apps/system/panic/README.md index abc7746d75..574b9f3fc1 100644 --- a/tools/test_apps/system/panic/README.md +++ b/tools/test_apps/system/panic/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | # Introduction diff --git a/tools/test_apps/system/ram_loadable_app/README.md b/tools/test_apps/system/ram_loadable_app/README.md index f33ad5d479..5ca70b341b 100644 --- a/tools/test_apps/system/ram_loadable_app/README.md +++ b/tools/test_apps/system/ram_loadable_app/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | # RAM loadable app Example diff --git a/tools/test_apps/system/rtc_mem_reserve/pytest_rtc_mem_reserve.py b/tools/test_apps/system/rtc_mem_reserve/pytest_rtc_mem_reserve.py index a03a14f070..409d252794 100644 --- a/tools/test_apps/system/rtc_mem_reserve/pytest_rtc_mem_reserve.py +++ b/tools/test_apps/system/rtc_mem_reserve/pytest_rtc_mem_reserve.py @@ -7,5 +7,6 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.generic @idf_parametrize('target', ['esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_rtc_mem_reserve(dut: Dut) -> None: dut.run_all_single_board_cases()