diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig
index cac3182bbe..55b269df09 100644
--- a/components/esp_hw_support/Kconfig
+++ b/components/esp_hw_support/Kconfig
@@ -309,6 +309,7 @@ menu "Hardware Settings"
     config ESP_ENABLE_PVT
         bool "Auto adjust hp & lp voltage using pvt function (MUST ENABLE FOR MP)"
         depends on SOC_PMU_PVT_SUPPORTED
+        default n if IDF_TARGET_ESP32C6
         default y
         help
             If enabled, hp & lp voltage can be auto adjust by PVT characteristic.
diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf
index cf092acee2..28b51cbb3b 100644
--- a/components/esp_hw_support/linker.lf
+++ b/components/esp_hw_support/linker.lf
@@ -47,7 +47,7 @@ entries:
         elif PM_SLP_IRAM_OPT = y && IDF_TARGET_ESP32P4 != y:
             pmu_param:get_act_hp_dbias (noflash)
             pmu_param:get_act_lp_dbias (noflash)
-    if SOC_PMU_PVT_SUPPORTED = y:
+    if SOC_PMU_PVT_SUPPORTED = y && ESP_ENABLE_PVT = y:
         pmu_pvt (noflash)
     if PM_SLP_IRAM_OPT = y && SOC_USB_SERIAL_JTAG_SUPPORTED = y:
         sleep_console (noflash)
diff --git a/components/esp_hw_support/port/esp32c6/pmu_pvt.c b/components/esp_hw_support/port/esp32c6/pmu_pvt.c
index e8ecb5122c..6d07f86d4f 100644
--- a/components/esp_hw_support/port/esp32c6/pmu_pvt.c
+++ b/components/esp_hw_support/port/esp32c6/pmu_pvt.c
@@ -83,7 +83,7 @@ void pvt_auto_dbias_init(void)
         SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
         /*config for dbias func*/
         CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN);
-        esp_rom_delay_us(100);
+        esp_rom_delay_us(1);
         SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL0_SEL, PVT_CHANNEL0_SEL, PVT_DBIAS_CHANNEL0_SEL_S);
         SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL1_SEL, PVT_CHANNEL1_SEL, PVT_DBIAS_CHANNEL1_SEL_S);  // Select monitor cell ,which  used to monitor PVT situation
         SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL0_SEL_REG, PVT_DBIAS_CHANNEL0_CFG, PVT_CHANNEL0_CFG, PVT_DBIAS_CHANNEL0_CFG_S);
@@ -130,7 +130,6 @@ void IRAM_ATTR pvt_func_enable(bool enable)
             SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, pvt_hp_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
             SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, pvt_lp_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S);
             CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); //disable auto dbias
-            CLEAR_PERI_REG_MASK(PVT_CLK_CFG_REG, PVT_MONITOR_CLK_PVT_EN);
             SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL);   // hand over control of dbias to pmu
             CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
             CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c
index 47af3bd9c0..4acbd5f8dd 100644
--- a/components/esp_hw_support/port/esp32c6/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -215,6 +215,8 @@ static void rtc_clk_cpu_freq_to_rc_fast(void)
 static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
 {
 #if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
+    pvt_auto_dbias_init();
+    charge_pump_init();
     pvt_func_enable(true);
     charge_pump_enable(true);
 #endif
@@ -353,10 +355,6 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
 void rtc_clk_cpu_freq_set_xtal(void)
 {
     rtc_clk_cpu_set_to_default_config();
-#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
-    charge_pump_enable(false);
-    pvt_func_enable(false);
-#endif
     rtc_clk_bbpll_disable();
 }
 
diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index 05040de22b..7a15bf12a5 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -797,7 +797,7 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool
         regi2c_tsens_reg_read();
 #endif
     }
-#if CONFIG_ESP_ENABLE_PVT
+#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_EN_WITH_SLEEP
     pvt_func_enable(false);
 #endif
 
@@ -814,7 +814,7 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool
  */
 static SLEEP_FN_ATTR void misc_modules_wake_prepare(uint32_t sleep_flags)
 {
-#if CONFIG_ESP_ENABLE_PVT
+#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_EN_WITH_SLEEP
     pvt_func_enable(true);
 #endif
 
diff --git a/components/esp_hw_support/sleep_system_peripheral.c b/components/esp_hw_support/sleep_system_peripheral.c
index 8fdb596ef3..155bbadba3 100644
--- a/components/esp_hw_support/sleep_system_peripheral.c
+++ b/components/esp_hw_support/sleep_system_peripheral.c
@@ -168,7 +168,7 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_retention_init(void *a
     err = sleep_pau_retention_init();
     if(err) goto error;
 #endif
-#if CONFIG_ESP_ENABLE_PVT
+#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_RETENTION_BY_REGDMA
     err = sleep_pvt_retention_init();
     if(err) goto error;
 #endif
diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c
index cf8792c912..337a2b1d8c 100644
--- a/components/esp_system/port/soc/esp32c6/clk.c
+++ b/components/esp_system/port/soc/esp32c6/clk.c
@@ -241,6 +241,9 @@ __attribute__((weak)) void esp_perip_clk_init(void)
 #if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
     clk_gate_config.disable_usb_serial_jtag = true;
 #endif
+#if !CONFIG_ESP_ENABLE_PVT
+    clk_gate_config.disable_pvt_clk = true;
+#endif
 
     periph_ll_clk_gate_set_default(rst_reason, &clk_gate_config);
 }
diff --git a/components/hal/esp32c6/include/hal/clk_gate_ll.h b/components/hal/esp32c6/include/hal/clk_gate_ll.h
index 524c94fe1b..0d42637069 100644
--- a/components/hal/esp32c6/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32c6/include/hal/clk_gate_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -220,10 +220,11 @@ FORCE_INLINE_ATTR void _clk_gate_ll_rtc_fast_to_lp_periph_en(bool enable)
 typedef struct {
     bool disable_uart0_clk;          ///< Disable UART0 clock
     bool disable_uart1_clk;          ///< Disable UART1 clock
-    bool disable_mspi_flash_clk;           ///< Disable MSPI flash clock
+    bool disable_mspi_flash_clk;     ///< Disable MSPI flash clock
     bool disable_assist_clk;         ///< Disable ASSIST Debug module clock
     bool disable_crypto_periph_clk;  ///< Disable crypto peripherals clock
     bool disable_usb_serial_jtag;    ///< Disable USB-Serial-JTAG clock
+    bool disable_pvt_clk;            ///< Disable PVT clock
 } periph_ll_clk_gate_config_t;
 
 /**
@@ -302,8 +303,10 @@ static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason,
         PCR.ctrl_tick_conf.tick_enable = 0;
         PCR.trace_conf.trace_clk_en = 0;
         PCR.mem_monitor_conf.mem_monitor_clk_en = 0;
-        PCR.pvt_monitor_conf.pvt_monitor_clk_en = 0;
-        PCR.pvt_monitor_func_clk_conf.pvt_monitor_func_clk_en = 0;
+        if (config->disable_pvt_clk) {
+            PCR.pvt_monitor_conf.pvt_monitor_clk_en = 0;
+            PCR.pvt_monitor_func_clk_conf.pvt_monitor_func_clk_en = 0;
+        }
         PCR.ctrl_clk_out_en.val = 0;
 
         if (config->disable_usb_serial_jtag) {
diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
index 556f6869a4..085c3fabf5 100644
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -251,6 +251,14 @@ config SOC_PMU_PVT_SUPPORTED
     bool
     default y
 
+config SOC_PVT_EN_WITH_SLEEP
+    bool
+    default y
+
+config SOC_PVT_RETENTION_BY_REGDMA
+    bool
+    default y
+
 config SOC_DCDC_SUPPORTED
     bool
     default y
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
index 3f3836b667..2739cc1b44 100644
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -85,6 +85,8 @@
 #define SOC_APM_SUPPORTED               1
 #define SOC_PMU_SUPPORTED               1
 #define SOC_PMU_PVT_SUPPORTED           1
+#define SOC_PVT_EN_WITH_SLEEP           1
+#define SOC_PVT_RETENTION_BY_REGDMA     1
 #define SOC_DCDC_SUPPORTED              1
 #define SOC_PAU_SUPPORTED               1     //TODO: IDF-7531
 #define SOC_LP_TIMER_SUPPORTED          1