diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h index dd755ff9a6..b21dcb15f0 100644 --- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h @@ -113,12 +113,12 @@ set pvt default param #define PVT_CMD2 0x427 #define PVT_TARGET 0xffff #define PVT_CLK_DIV 1 -#define PVT_DELAY_NUM_HIGH 150 -#define PVT_DELAY_NUM_LOW 143 +#define PVT_DELAY_NUM_HIGH 154 +#define PVT_DELAY_NUM_LOW 147 #define PVT_PUMP_CHANNEL_CODE 1 #define PVT_PUMP_BITMAP 22 #define PVT_PUMP_DRV 0 -#define PVT_DELAY_NUM_PUMP 139 +#define PVT_DELAY_NUM_PUMP 143 /** * @brief Initialize PVT related parameters diff --git a/components/esp_hw_support/port/esp32c5/pmu_pvt.c b/components/esp_hw_support/port/esp32c5/pmu_pvt.c index f4fa36face..9f81f95832 100644 --- a/components/esp_hw_support/port/esp32c5/pmu_pvt.c +++ b/components/esp_hw_support/port/esp32c5/pmu_pvt.c @@ -122,6 +122,7 @@ void IRAM_ATTR pvt_func_enable(bool enable) CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pvt CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // must clear @HP_CALI_DBIAS_DEFAULT SET_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); // enable auto dbias + esp_rom_delay_us(50); } else { uint32_t pvt_hp_dbias = get_pvt_hp_dbias(); uint32_t pvt_lp_dbias = get_pvt_lp_dbias(); // update pvt_cali_dbias diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index a5e53cddb4..fde19ae70e 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -199,7 +199,7 @@ #elif CONFIG_IDF_TARGET_ESP32C5 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (318) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56) -#define PVT_REINIT_COST_US (25) +#define PVT_REINIT_COST_US (75) #elif CONFIG_IDF_TARGET_ESP32C61 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (230) #define PVT_REINIT_COST_US (90)