From 225b1d8a37a7372c8f9753e12f9fa466edc30cde Mon Sep 17 00:00:00 2001 From: hebinglin Date: Mon, 15 Sep 2025 14:50:16 +0800 Subject: [PATCH] change(esp_hw_support): change some pmu params for esp32h21 & esp32h4 --- .../test_apps/uart/main/test_hp_uart_wakeup.c | 3 +++ .../esp_hw_support/port/esp32h21/pmu_init.c | 25 ++++++++----------- .../esp_hw_support/port/esp32h21/pmu_param.c | 2 +- .../esp_hw_support/port/esp32h4/pmu_param.c | 4 +-- .../esp_hw_support/port/esp32h4/pmu_sleep.c | 6 ----- .../port/esp32h4/private_include/pmu_param.h | 10 ++++---- components/hal/esp32h21/include/hal/pmu_ll.h | 14 ++++++++++- 7 files changed, 35 insertions(+), 29 deletions(-) diff --git a/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c b/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c index 5955041037..e2b5b6b80a 100644 --- a/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c +++ b/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c @@ -39,6 +39,9 @@ #elif CONFIG_IDF_TARGET_ESP32C5 #define DEFAULT_UART1_TX_IO_NUM GPIO_NUM_2 #define DEFAULT_UART1_RX_IO_NUM GPIO_NUM_3 +#elif CONFIG_IDF_TARGET_ESP32H21 +#define DEFAULT_UART1_TX_IO_NUM GPIO_NUM_4 +#define DEFAULT_UART1_RX_IO_NUM GPIO_NUM_5 #elif CONFIG_IDF_TARGET_ESP32H4 #define DEFAULT_UART1_TX_IO_NUM GPIO_NUM_15 #define DEFAULT_UART1_RX_IO_NUM GPIO_NUM_16 diff --git a/components/esp_hw_support/port/esp32h21/pmu_init.c b/components/esp_hw_support/port/esp32h21/pmu_init.c index 5ec242300f..bf829bbc72 100644 --- a/components/esp_hw_support/port/esp32h21/pmu_init.c +++ b/components/esp_hw_support/port/esp32h21/pmu_init.c @@ -86,6 +86,7 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, const pmu_hp_sys pmu_ll_hp_set_dcm_mode (ctx->hal->dev, mode, anlg->bias.dcm_mode); pmu_ll_hp_set_bias_xpd (ctx->hal->dev, mode, anlg->bias.xpd_bias); pmu_ll_hp_set_trx_xpd (ctx->hal->dev, mode, anlg->bias.xpd_trx); + pmu_ll_hp_set_discnnt_dig_rtc (ctx->hal->dev, mode, anlg->bias.discnnt_dig_rtc); pmu_ll_hp_set_current_power_off (ctx->hal->dev, mode, anlg->bias.pd_cur); pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, mode, anlg->bias.bias_sleep); if (mode == PMU_MODE_HP_ACTIVE) { @@ -113,6 +114,9 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, const pmu_hp_sys pmu_ll_imm_update_dig_icg_switch(ctx->hal->dev, true); pmu_ll_hp_set_sleep_protect_mode(ctx->hal->dev, PMU_SLEEP_PROTECT_HP_LP_SLEEP); + + /* set dcdc ccm mode software enable */ + pmu_ll_set_dcdc_ccm_sw_en(&PMU, true); } void pmu_lp_system_init(pmu_context_t *ctx, pmu_lp_mode_t mode, const pmu_lp_system_param_t *param) @@ -135,6 +139,7 @@ void pmu_lp_system_init(pmu_context_t *ctx, pmu_lp_mode_t mode, const pmu_lp_sys pmu_ll_lp_set_dcm_vset (ctx->hal->dev, mode, anlg->bias.dcm_vset); pmu_ll_lp_set_dcm_mode (ctx->hal->dev, mode, anlg->bias.dcm_mode); pmu_ll_lp_set_bias_xpd (ctx->hal->dev, mode, anlg->bias.xpd_bias); + pmu_ll_lp_set_discnnt_dig_rtc (ctx->hal->dev, mode, anlg->bias.discnnt_dig_rtc); pmu_ll_lp_set_current_power_off (ctx->hal->dev, mode, anlg->bias.pd_cur); pmu_ll_lp_set_bias_sleep_enable (ctx->hal->dev, mode, anlg->bias.bias_sleep); } @@ -229,8 +234,12 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx) void pmu_init() { - /* No peripheral reg i2c power up required on the target */ + pmu_hp_system_init_default(PMU_instance()); + pmu_lp_system_init_default(PMU_instance()); + pmu_power_domain_force_default(PMU_instance()); + /* No peripheral reg i2c power up required on the target */ +#if !CONFIG_IDF_ENV_FPGA REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, 0); REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, 0); REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG_SLP, 0); @@ -238,19 +247,7 @@ void pmu_init() REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_RTC_REG, 0); REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_DIG_REG, 0); REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_TRX, 0); - - WRITE_PERI_REG(PMU_POWER_PD_TOP_CNTL_REG, 0); - WRITE_PERI_REG(PMU_POWER_PD_HPAON_CNTL_REG, 0); - WRITE_PERI_REG(PMU_POWER_PD_HPCPU_CNTL_REG, 0); - WRITE_PERI_REG(PMU_POWER_PD_HPPERI_RESERVE_REG, 0); - WRITE_PERI_REG(PMU_POWER_PD_HPWIFI_CNTL_REG, 0); - WRITE_PERI_REG(PMU_POWER_PD_LPPERI_CNTL_REG, 0); - - pmu_hp_system_init_default(PMU_instance()); - pmu_lp_system_init_default(PMU_instance()); - pmu_ll_dcm_ctrl_ccm_sw_en(&PMU, true); - - pmu_power_domain_force_default(PMU_instance()); +#endif #if !CONFIG_IDF_ENV_FPGA // TODO: IDF-11548 diff --git a/components/esp_hw_support/port/esp32h21/pmu_param.c b/components/esp_hw_support/port/esp32h21/pmu_param.c index fd5173b28c..ccb52da2f3 100644 --- a/components/esp_hw_support/port/esp32h21/pmu_param.c +++ b/components/esp_hw_support/port/esp32h21/pmu_param.c @@ -332,7 +332,7 @@ const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mod .dcm_vset = 0, \ .dcm_mode = 3, \ .xpd_bias = 0, \ - .discnnt_dig_rtc = 0, \ + .discnnt_dig_rtc = 1, \ .pd_cur = 1, \ .bias_sleep = 1 \ }, \ diff --git a/components/esp_hw_support/port/esp32h4/pmu_param.c b/components/esp_hw_support/port/esp32h4/pmu_param.c index ff0b2e8b1b..cd82069cc1 100644 --- a/components/esp_hw_support/port/esp32h4/pmu_param.c +++ b/components/esp_hw_support/port/esp32h4/pmu_param.c @@ -42,7 +42,7 @@ static __attribute__((unused)) const char *TAG = "pmu_param"; .xpd_bbpll = 1 \ }, \ .xtal = { \ - .xpd_xtalx2 = 1, \ + .xpd_xtalx2 = 0, \ .xpd_xtal = 1 \ } \ } @@ -434,7 +434,7 @@ const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mod .dcm_mode = 3, \ .dcm_vset = 0, \ .xpd_bias = 0, \ - .discnnt_dig_rtc = 0, \ + .discnnt_dig_rtc = 1, \ .pd_cur = 1, \ .bias_sleep = 1, \ }, \ diff --git a/components/esp_hw_support/port/esp32h4/pmu_sleep.c b/components/esp_hw_support/port/esp32h4/pmu_sleep.c index 79ed5b8776..95f9fc4be2 100644 --- a/components/esp_hw_support/port/esp32h4/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32h4/pmu_sleep.c @@ -210,14 +210,8 @@ static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_con pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbias); pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.drv_b); - pmu_ll_hp_set_discnnt_dig_rtc (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.discnnt_dig_rtc); - pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b); pmu_ll_hp_set_dcm_mode (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dcm_mode); pmu_ll_hp_set_dcm_vset (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dcm_vset); - pmu_ll_lp_set_discnnt_dig_rtc (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.discnnt_dig_rtc); - pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbias); - pmu_ll_lp_set_regulator_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.xpd); - pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.drv_b); pmu_ll_lp_set_dcm_mode (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dcm_mode); pmu_ll_lp_set_dcm_vset (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dcm_vset); } diff --git a/components/esp_hw_support/port/esp32h4/private_include/pmu_param.h b/components/esp_hw_support/port/esp32h4/private_include/pmu_param.h index 6c8d5a1e11..8e2e4197bd 100644 --- a/components/esp_hw_support/port/esp32h4/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32h4/private_include/pmu_param.h @@ -384,7 +384,7 @@ typedef struct { #define PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags) { \ .hp_sys = { \ .analog = { \ - .dcdc_ccm_enb = 0, \ + .dcdc_ccm_enb = 1, \ .dcdc_clear_rdy = 0, \ .dig_reg_dpcur_bias = 1, \ .dig_reg_dsfmos = 4, \ @@ -402,7 +402,7 @@ typedef struct { }, \ .lp_sys[PMU_MODE_LP_SLEEP] = { \ .analog = { \ - .dcdc_ccm_enb = 0, \ + .dcdc_ccm_enb = 1, \ .dcdc_clear_rdy = 0, \ .dig_reg_dpcur_bias = 1, \ .dig_reg_dsfmos = 4, \ @@ -423,7 +423,7 @@ typedef struct { #define PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags) { \ .hp_sys = { \ .analog = { \ - .dcdc_ccm_enb = 0, \ + .dcdc_ccm_enb = 1, \ .dcdc_clear_rdy = 0, \ .dig_reg_dpcur_bias = 1, \ .dig_reg_dsfmos = 4, \ @@ -439,13 +439,13 @@ typedef struct { }, \ .lp_sys[PMU_MODE_LP_SLEEP] = { \ .analog = { \ - .dcdc_ccm_enb = 0, \ + .dcdc_ccm_enb = 1, \ .dcdc_clear_rdy = 0, \ .dig_reg_dpcur_bias = 1, \ .dig_reg_dsfmos = 4, \ .dcm_vset = 0, \ .dcm_mode = 3, \ - .discnnt_dig_rtc = 0, \ + .discnnt_dig_rtc = 1, \ .drv_b = PMU_LP_DRVB_DEEPSLEEP, \ .pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \ .bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \ diff --git a/components/hal/esp32h21/include/hal/pmu_ll.h b/components/hal/esp32h21/include/hal/pmu_ll.h index 22aaf1f259..99a1c696ad 100644 --- a/components/hal/esp32h21/include/hal/pmu_ll.h +++ b/components/hal/esp32h21/include/hal/pmu_ll.h @@ -134,6 +134,12 @@ FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, hw->hp_sys[mode].xtal.xpd_xtal = xpd_xtal; } +FORCE_INLINE_ATTR void pmu_ll_hp_set_discnnt_dig_rtc(pmu_dev_t *hw, pmu_hp_mode_t mode, bool discnnt) +{ + hw->hp_sys[mode].bias.discnnt_dig_rtc = discnnt; +} + + FORCE_INLINE_ATTR void pmu_ll_hp_set_current_power_off(pmu_dev_t *hw, pmu_hp_mode_t mode, bool off) { hw->hp_sys[mode].bias.pd_cur = off; @@ -345,6 +351,12 @@ FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, hw->lp_sys[mode].bias.xpd_bias = xpd_bias; } +FORCE_INLINE_ATTR void pmu_ll_lp_set_discnnt_dig_rtc(pmu_dev_t *hw, pmu_lp_mode_t mode, bool discnnt) +{ + HAL_ASSERT(mode == PMU_MODE_LP_SLEEP); + hw->lp_sys[mode].bias.discnnt_dig_rtc = discnnt; +} + FORCE_INLINE_ATTR void pmu_ll_lp_set_current_power_off(pmu_dev_t *hw, pmu_lp_mode_t mode, bool off) { HAL_ASSERT(mode == PMU_MODE_LP_SLEEP); @@ -714,7 +726,7 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t * return hw->power.wait_timer0.powerup_timer; } -FORCE_INLINE_ATTR void pmu_ll_dcm_ctrl_ccm_sw_en(pmu_dev_t *hw, bool enable) +FORCE_INLINE_ATTR void pmu_ll_set_dcdc_ccm_sw_en(pmu_dev_t *hw, bool enable) { hw->dcm_ctrl.dcdc_ccm_sw_en = enable; }