From 22dfacc18da97b6fe4912c466ea6e6af56368ddc Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 4 Sep 2025 15:34:41 +0800 Subject: [PATCH] feat(ledc): ESP32P4 ECO5 LEDC related updates --- components/esp_driver_ledc/src/ledc.c | 2 +- components/hal/esp32p4/include/hal/ledc_ll.h | 7 +- .../soc/esp32p4/ld/esp32p4.peripherals.ld | 2 +- .../register/hw_ver1/soc/ledc_struct.h | 16 +- .../register/hw_ver3/soc/ledc_eco5_reg.h | 3116 ----------------- .../register/hw_ver3/soc/ledc_eco5_struct.h | 1359 ------- .../esp32p4/register/hw_ver3/soc/ledc_reg.h | 968 +++-- .../register/hw_ver3/soc/ledc_struct.h | 1345 +++---- docs/en/api-reference/peripherals/ledc.rst | 4 + docs/zh_CN/api-reference/peripherals/ledc.rst | 4 + .../ledc_basic/main/ledc_basic_example_main.c | 2 +- 11 files changed, 1328 insertions(+), 5497 deletions(-) delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_reg.h delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_struct.h diff --git a/components/esp_driver_ledc/src/ledc.c b/components/esp_driver_ledc/src/ledc.c index 89e578ad16..04bada46c8 100644 --- a/components/esp_driver_ledc/src/ledc.c +++ b/components/esp_driver_ledc/src/ledc.c @@ -905,7 +905,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf) /*set channel parameters*/ /* channel parameters decide how the waveform looks like in one period */ /* set channel duty and hpoint value, duty range is [0, (2**duty_res)], hpoint range is [0, (2**duty_res)-1] */ - /* Note: On ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4, due to a hardware bug, + /* Note: On ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4 (rev < 3.0), due to a hardware bug, * 100% duty cycle (i.e. 2**duty_res) is not reachable when the binded timer selects the maximum duty * resolution. For example, the max duty resolution on ESP32C3 is 14-bit width, then set duty to (2**14) * will mess up the duty calculation in hardware. diff --git a/components/hal/esp32p4/include/hal/ledc_ll.h b/components/hal/esp32p4/include/hal/ledc_ll.h index 1445e85ec3..134399b294 100644 --- a/components/hal/esp32p4/include/hal/ledc_ll.h +++ b/components/hal/esp32p4/include/hal/ledc_ll.h @@ -283,7 +283,6 @@ static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_m static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src) { // The target has no timer-specific clock source option - HAL_ASSERT(hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel == 0); *clk_src = LEDC_SCLK; } @@ -403,7 +402,7 @@ static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_m */ static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *duty_val) { - *duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_r.duty >> 4); + *duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_r.duty_r >> 4); } /** @@ -444,7 +443,7 @@ static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t spee */ static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t range_num) { - hw->chn_gamma_conf[channel_num].ch0_gamma_entry_num = range_num; + hw->chn_gamma_conf[channel_num].gamma_entry_num = range_num; } /** @@ -459,7 +458,7 @@ static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mo */ static inline void ledc_ll_get_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *range_num) { - *range_num = hw->chn_gamma_conf[channel_num].ch0_gamma_entry_num; + *range_num = hw->chn_gamma_conf[channel_num].gamma_entry_num; } /** diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld index 13302d2c1e..62aff83a15 100644 --- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld +++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld @@ -26,7 +26,7 @@ PROVIDE ( LP2HP_PERI_PMS = 0x500A5800 ); PROVIDE ( DMA_PMS = 0x500A6000 ); PROVIDE ( AXI_PERF_MON = 0x500A8000 ); PROVIDE ( LEDC = 0x500D3000 ); -PROVIDE ( LEDC_GAMMA_RAM = 0x500D3400 ); +PROVIDE ( LEDC_GAMMA_RAM = 0x500D3400 ); PROVIDE ( TIMERG0 = 0x500C2000 ); PROVIDE ( TIMERG1 = 0x500C3000 ); PROVIDE ( SYSTIMER = 0x500E2000 ); diff --git a/components/soc/esp32p4/register/hw_ver1/soc/ledc_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/ledc_struct.h index df2c5df873..2dbc716a79 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/ledc_struct.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/ledc_struct.h @@ -106,10 +106,10 @@ typedef union { */ typedef union { struct { - /** duty_ch0_r : RO; bitpos: [24:0]; default: 0; + /** duty_r : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel n. */ - uint32_t duty:25; + uint32_t duty_r:25; uint32_t reserved_25:7; }; uint32_t val; @@ -577,20 +577,20 @@ typedef union { */ typedef union { struct { - /** ch0_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; + /** gamma_entry_num : R/W; bitpos: [4:0]; default: 0; * Configures the number of duty cycle fading rages for LEDC chn. */ - uint32_t ch0_gamma_entry_num:5; - /** ch0_gamma_pause : WT; bitpos: [5]; default: 0; + uint32_t gamma_entry_num:5; + /** gamma_pause : WT; bitpos: [5]; default: 0; * Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No * effect\\1: Pause */ - uint32_t ch0_gamma_pause:1; - /** ch0_gamma_resume : WT; bitpos: [6]; default: 0; + uint32_t gamma_pause:1; + /** gamma_resume : WT; bitpos: [6]; default: 0; * Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No * effect\\1: Resume */ - uint32_t ch0_gamma_resume:1; + uint32_t gamma_resume:1; uint32_t reserved_7:25; }; uint32_t val; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_reg.h deleted file mode 100644 index b10ff9f379..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_reg.h +++ /dev/null @@ -1,3116 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** LEDC_CH0_CONF0_REG register - * Configuration register 0 for channel 0 - */ -#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) -/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 0 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH0 0x00000003U -#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) -#define LEDC_TIMER_SEL_CH0_V 0x00000003U -#define LEDC_TIMER_SEL_CH0_S 0 -/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 0. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) -#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH0_S 2 -/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 0 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH0 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH0 (BIT(3)) -#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) -#define LEDC_IDLE_LV_CH0_V 0x00000001U -#define LEDC_IDLE_LV_CH0_S 3 -/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0, - * LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0, - * LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel - * 0, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH0 (BIT(4)) -#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) -#define LEDC_PARA_UP_CH0_V 0x00000001U -#define LEDC_PARA_UP_CH0_S 4 -/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH0_INT interrupt - * will be triggered when channel 0 overflows for (LEDC_OVF_NUM_CH0 + 1) times. - */ -#define LEDC_OVF_NUM_CH0 0x000003FFU -#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) -#define LEDC_OVF_NUM_CH0_V 0x000003FFU -#define LEDC_OVF_NUM_CH0_S 5 -/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 0. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) -#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH0_S 15 -/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 0. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) -#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH0_S 16 - -/** LEDC_CH0_HPOINT_REG register - * High point register for channel 0 - */ -#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4) -/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 0. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH0 0x000FFFFFU -#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) -#define LEDC_HPOINT_CH0_V 0x000FFFFFU -#define LEDC_HPOINT_CH0_S 0 - -/** LEDC_CH0_DUTY_REG register - * Initial duty cycle register for channel 0 - */ -#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8) -/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 0. - */ -#define LEDC_DUTY_CH0 0x01FFFFFFU -#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) -#define LEDC_DUTY_CH0_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_S 0 - -/** LEDC_CH0_CONF1_REG register - * Configuration register 1 for channel 0 - */ -#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) -/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH0 (BIT(31)) -#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) -#define LEDC_DUTY_START_CH0_V 0x00000001U -#define LEDC_DUTY_START_CH0_S 31 - -/** LEDC_CH0_DUTY_R_REG register - * Current duty cycle register for channel 0 - */ -#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10) -/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 0. - */ -#define LEDC_DUTY_CH0_R 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) -#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_S 0 - -/** LEDC_CH1_CONF0_REG register - * Configuration register 0 for channel 1 - */ -#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) -/** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 1 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH1 0x00000003U -#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) -#define LEDC_TIMER_SEL_CH1_V 0x00000003U -#define LEDC_TIMER_SEL_CH1_S 0 -/** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 1. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH1 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) -#define LEDC_SIG_OUT_EN_CH1_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH1_S 2 -/** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 1 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH1 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH1 (BIT(3)) -#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) -#define LEDC_IDLE_LV_CH1_V 0x00000001U -#define LEDC_IDLE_LV_CH1_S 3 -/** LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1, - * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1, - * LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel - * 1, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH1 (BIT(4)) -#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) -#define LEDC_PARA_UP_CH1_V 0x00000001U -#define LEDC_PARA_UP_CH1_S 4 -/** LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH1_INT interrupt - * will be triggered when channel 1 overflows for (LEDC_OVF_NUM_CH1 + 1) times. - */ -#define LEDC_OVF_NUM_CH1 0x000003FFU -#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S) -#define LEDC_OVF_NUM_CH1_V 0x000003FFU -#define LEDC_OVF_NUM_CH1_S 5 -/** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 1. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH1 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) -#define LEDC_OVF_CNT_EN_CH1_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH1_S 15 -/** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 1. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) -#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH1_S 16 - -/** LEDC_CH1_HPOINT_REG register - * High point register for channel 1 - */ -#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18) -/** LEDC_HPOINT_CH1 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 1. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH1 0x000FFFFFU -#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S) -#define LEDC_HPOINT_CH1_V 0x000FFFFFU -#define LEDC_HPOINT_CH1_S 0 - -/** LEDC_CH1_DUTY_REG register - * Initial duty cycle register for channel 1 - */ -#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c) -/** LEDC_DUTY_CH1 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 1. - */ -#define LEDC_DUTY_CH1 0x01FFFFFFU -#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S) -#define LEDC_DUTY_CH1_V 0x01FFFFFFU -#define LEDC_DUTY_CH1_S 0 - -/** LEDC_CH1_CONF1_REG register - * Configuration register 1 for channel 1 - */ -#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) -/** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH1 (BIT(31)) -#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) -#define LEDC_DUTY_START_CH1_V 0x00000001U -#define LEDC_DUTY_START_CH1_S 31 - -/** LEDC_CH1_DUTY_R_REG register - * Current duty cycle register for channel 1 - */ -#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24) -/** LEDC_DUTY_CH1_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 1. - */ -#define LEDC_DUTY_CH1_R 0x01FFFFFFU -#define LEDC_DUTY_CH1_R_M (LEDC_DUTY_CH1_R_V << LEDC_DUTY_CH1_R_S) -#define LEDC_DUTY_CH1_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH1_R_S 0 - -/** LEDC_CH2_CONF0_REG register - * Configuration register 0 for channel 2 - */ -#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) -/** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 2 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH2 0x00000003U -#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) -#define LEDC_TIMER_SEL_CH2_V 0x00000003U -#define LEDC_TIMER_SEL_CH2_S 0 -/** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 2. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH2 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) -#define LEDC_SIG_OUT_EN_CH2_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH2_S 2 -/** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 2 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH2 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH2 (BIT(3)) -#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) -#define LEDC_IDLE_LV_CH2_V 0x00000001U -#define LEDC_IDLE_LV_CH2_S 3 -/** LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2, - * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2, - * LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel - * 2, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH2 (BIT(4)) -#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) -#define LEDC_PARA_UP_CH2_V 0x00000001U -#define LEDC_PARA_UP_CH2_S 4 -/** LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH2_INT interrupt - * will be triggered when channel 2 overflows for (LEDC_OVF_NUM_CH2 + 1) times. - */ -#define LEDC_OVF_NUM_CH2 0x000003FFU -#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S) -#define LEDC_OVF_NUM_CH2_V 0x000003FFU -#define LEDC_OVF_NUM_CH2_S 5 -/** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 2. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH2 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) -#define LEDC_OVF_CNT_EN_CH2_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH2_S 15 -/** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 2. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) -#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH2_S 16 - -/** LEDC_CH2_HPOINT_REG register - * High point register for channel 2 - */ -#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c) -/** LEDC_HPOINT_CH2 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 2. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH2 0x000FFFFFU -#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S) -#define LEDC_HPOINT_CH2_V 0x000FFFFFU -#define LEDC_HPOINT_CH2_S 0 - -/** LEDC_CH2_DUTY_REG register - * Initial duty cycle register for channel 2 - */ -#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30) -/** LEDC_DUTY_CH2 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 2. - */ -#define LEDC_DUTY_CH2 0x01FFFFFFU -#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S) -#define LEDC_DUTY_CH2_V 0x01FFFFFFU -#define LEDC_DUTY_CH2_S 0 - -/** LEDC_CH2_CONF1_REG register - * Configuration register 1 for channel 2 - */ -#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) -/** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH2 (BIT(31)) -#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) -#define LEDC_DUTY_START_CH2_V 0x00000001U -#define LEDC_DUTY_START_CH2_S 31 - -/** LEDC_CH2_DUTY_R_REG register - * Current duty cycle register for channel 2 - */ -#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38) -/** LEDC_DUTY_CH2_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 2. - */ -#define LEDC_DUTY_CH2_R 0x01FFFFFFU -#define LEDC_DUTY_CH2_R_M (LEDC_DUTY_CH2_R_V << LEDC_DUTY_CH2_R_S) -#define LEDC_DUTY_CH2_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH2_R_S 0 - -/** LEDC_CH3_CONF0_REG register - * Configuration register 0 for channel 3 - */ -#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) -/** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 3 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH3 0x00000003U -#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) -#define LEDC_TIMER_SEL_CH3_V 0x00000003U -#define LEDC_TIMER_SEL_CH3_S 0 -/** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 3. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH3 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) -#define LEDC_SIG_OUT_EN_CH3_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH3_S 2 -/** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 3 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH3 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH3 (BIT(3)) -#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) -#define LEDC_IDLE_LV_CH3_V 0x00000001U -#define LEDC_IDLE_LV_CH3_S 3 -/** LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3, - * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3, - * LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel - * 3, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH3 (BIT(4)) -#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) -#define LEDC_PARA_UP_CH3_V 0x00000001U -#define LEDC_PARA_UP_CH3_S 4 -/** LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH3_INT interrupt - * will be triggered when channel 3 overflows for (LEDC_OVF_NUM_CH3 + 1) times. - */ -#define LEDC_OVF_NUM_CH3 0x000003FFU -#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S) -#define LEDC_OVF_NUM_CH3_V 0x000003FFU -#define LEDC_OVF_NUM_CH3_S 5 -/** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 3. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH3 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) -#define LEDC_OVF_CNT_EN_CH3_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH3_S 15 -/** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 3. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) -#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH3_S 16 - -/** LEDC_CH3_HPOINT_REG register - * High point register for channel 3 - */ -#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40) -/** LEDC_HPOINT_CH3 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 3. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH3 0x000FFFFFU -#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S) -#define LEDC_HPOINT_CH3_V 0x000FFFFFU -#define LEDC_HPOINT_CH3_S 0 - -/** LEDC_CH3_DUTY_REG register - * Initial duty cycle register for channel 3 - */ -#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44) -/** LEDC_DUTY_CH3 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 3. - */ -#define LEDC_DUTY_CH3 0x01FFFFFFU -#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S) -#define LEDC_DUTY_CH3_V 0x01FFFFFFU -#define LEDC_DUTY_CH3_S 0 - -/** LEDC_CH3_CONF1_REG register - * Configuration register 1 for channel 3 - */ -#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) -/** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH3 (BIT(31)) -#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) -#define LEDC_DUTY_START_CH3_V 0x00000001U -#define LEDC_DUTY_START_CH3_S 31 - -/** LEDC_CH3_DUTY_R_REG register - * Current duty cycle register for channel 3 - */ -#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c) -/** LEDC_DUTY_CH3_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 3. - */ -#define LEDC_DUTY_CH3_R 0x01FFFFFFU -#define LEDC_DUTY_CH3_R_M (LEDC_DUTY_CH3_R_V << LEDC_DUTY_CH3_R_S) -#define LEDC_DUTY_CH3_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH3_R_S 0 - -/** LEDC_CH4_CONF0_REG register - * Configuration register 0 for channel 4 - */ -#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) -/** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 4 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH4 0x00000003U -#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) -#define LEDC_TIMER_SEL_CH4_V 0x00000003U -#define LEDC_TIMER_SEL_CH4_S 0 -/** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 4. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH4 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) -#define LEDC_SIG_OUT_EN_CH4_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH4_S 2 -/** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 4 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH4 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH4 (BIT(3)) -#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) -#define LEDC_IDLE_LV_CH4_V 0x00000001U -#define LEDC_IDLE_LV_CH4_S 3 -/** LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4, - * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4, - * LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel - * 4, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH4 (BIT(4)) -#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) -#define LEDC_PARA_UP_CH4_V 0x00000001U -#define LEDC_PARA_UP_CH4_S 4 -/** LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH4_INT interrupt - * will be triggered when channel 4 overflows for (LEDC_OVF_NUM_CH4 + 1) times. - */ -#define LEDC_OVF_NUM_CH4 0x000003FFU -#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S) -#define LEDC_OVF_NUM_CH4_V 0x000003FFU -#define LEDC_OVF_NUM_CH4_S 5 -/** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 4. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH4 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) -#define LEDC_OVF_CNT_EN_CH4_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH4_S 15 -/** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 4. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) -#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH4_S 16 - -/** LEDC_CH4_HPOINT_REG register - * High point register for channel 4 - */ -#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54) -/** LEDC_HPOINT_CH4 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 4. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH4 0x000FFFFFU -#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S) -#define LEDC_HPOINT_CH4_V 0x000FFFFFU -#define LEDC_HPOINT_CH4_S 0 - -/** LEDC_CH4_DUTY_REG register - * Initial duty cycle register for channel 4 - */ -#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58) -/** LEDC_DUTY_CH4 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 4. - */ -#define LEDC_DUTY_CH4 0x01FFFFFFU -#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S) -#define LEDC_DUTY_CH4_V 0x01FFFFFFU -#define LEDC_DUTY_CH4_S 0 - -/** LEDC_CH4_CONF1_REG register - * Configuration register 1 for channel 4 - */ -#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) -/** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH4 (BIT(31)) -#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) -#define LEDC_DUTY_START_CH4_V 0x00000001U -#define LEDC_DUTY_START_CH4_S 31 - -/** LEDC_CH4_DUTY_R_REG register - * Current duty cycle register for channel 4 - */ -#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60) -/** LEDC_DUTY_CH4_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 4. - */ -#define LEDC_DUTY_CH4_R 0x01FFFFFFU -#define LEDC_DUTY_CH4_R_M (LEDC_DUTY_CH4_R_V << LEDC_DUTY_CH4_R_S) -#define LEDC_DUTY_CH4_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH4_R_S 0 - -/** LEDC_CH5_CONF0_REG register - * Configuration register 0 for channel 5 - */ -#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) -/** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 5 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH5 0x00000003U -#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) -#define LEDC_TIMER_SEL_CH5_V 0x00000003U -#define LEDC_TIMER_SEL_CH5_S 0 -/** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 5. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH5 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) -#define LEDC_SIG_OUT_EN_CH5_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH5_S 2 -/** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 5 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH5 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH5 (BIT(3)) -#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) -#define LEDC_IDLE_LV_CH5_V 0x00000001U -#define LEDC_IDLE_LV_CH5_S 3 -/** LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5, - * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5, - * LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel - * 5, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH5 (BIT(4)) -#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) -#define LEDC_PARA_UP_CH5_V 0x00000001U -#define LEDC_PARA_UP_CH5_S 4 -/** LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH5_INT interrupt - * will be triggered when channel 5 overflows for (LEDC_OVF_NUM_CH5 + 1) times. - */ -#define LEDC_OVF_NUM_CH5 0x000003FFU -#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S) -#define LEDC_OVF_NUM_CH5_V 0x000003FFU -#define LEDC_OVF_NUM_CH5_S 5 -/** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 5. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH5 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) -#define LEDC_OVF_CNT_EN_CH5_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH5_S 15 -/** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 5. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) -#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH5_S 16 - -/** LEDC_CH5_HPOINT_REG register - * High point register for channel 5 - */ -#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68) -/** LEDC_HPOINT_CH5 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 5. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH5 0x000FFFFFU -#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S) -#define LEDC_HPOINT_CH5_V 0x000FFFFFU -#define LEDC_HPOINT_CH5_S 0 - -/** LEDC_CH5_DUTY_REG register - * Initial duty cycle register for channel 5 - */ -#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c) -/** LEDC_DUTY_CH5 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 5. - */ -#define LEDC_DUTY_CH5 0x01FFFFFFU -#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S) -#define LEDC_DUTY_CH5_V 0x01FFFFFFU -#define LEDC_DUTY_CH5_S 0 - -/** LEDC_CH5_CONF1_REG register - * Configuration register 1 for channel 5 - */ -#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) -/** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH5 (BIT(31)) -#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) -#define LEDC_DUTY_START_CH5_V 0x00000001U -#define LEDC_DUTY_START_CH5_S 31 - -/** LEDC_CH5_DUTY_R_REG register - * Current duty cycle register for channel 5 - */ -#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74) -/** LEDC_DUTY_CH5_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 5. - */ -#define LEDC_DUTY_CH5_R 0x01FFFFFFU -#define LEDC_DUTY_CH5_R_M (LEDC_DUTY_CH5_R_V << LEDC_DUTY_CH5_R_S) -#define LEDC_DUTY_CH5_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH5_R_S 0 - -/** LEDC_CH6_CONF0_REG register - * Configuration register 0 for channel 6 - */ -#define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78) -/** LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 6 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH6 0x00000003U -#define LEDC_TIMER_SEL_CH6_M (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S) -#define LEDC_TIMER_SEL_CH6_V 0x00000003U -#define LEDC_TIMER_SEL_CH6_S 0 -/** LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 6. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH6 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH6_M (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S) -#define LEDC_SIG_OUT_EN_CH6_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH6_S 2 -/** LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 6 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH6 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH6 (BIT(3)) -#define LEDC_IDLE_LV_CH6_M (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S) -#define LEDC_IDLE_LV_CH6_V 0x00000001U -#define LEDC_IDLE_LV_CH6_S 3 -/** LEDC_PARA_UP_CH6 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH6, LEDC_DUTY_START_CH6, - * LEDC_SIG_OUT_EN_CH6, LEDC_TIMER_SEL_CH6, LEDC_DUTY_NUM_CH6, LEDC_DUTY_CYCLE_CH6, - * LEDC_DUTY_SCALE_CH6, LEDC_DUTY_INC_CH6, and LEDC_OVF_CNT_EN_CH6 fields for channel - * 6, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH6 (BIT(4)) -#define LEDC_PARA_UP_CH6_M (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S) -#define LEDC_PARA_UP_CH6_V 0x00000001U -#define LEDC_PARA_UP_CH6_S 4 -/** LEDC_OVF_NUM_CH6 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH6_INT interrupt - * will be triggered when channel 6 overflows for (LEDC_OVF_NUM_CH6 + 1) times. - */ -#define LEDC_OVF_NUM_CH6 0x000003FFU -#define LEDC_OVF_NUM_CH6_M (LEDC_OVF_NUM_CH6_V << LEDC_OVF_NUM_CH6_S) -#define LEDC_OVF_NUM_CH6_V 0x000003FFU -#define LEDC_OVF_NUM_CH6_S 5 -/** LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 6. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH6 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH6_M (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S) -#define LEDC_OVF_CNT_EN_CH6_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH6_S 15 -/** LEDC_OVF_CNT_RESET_CH6 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 6. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH6 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH6_M (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S) -#define LEDC_OVF_CNT_RESET_CH6_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH6_S 16 - -/** LEDC_CH6_HPOINT_REG register - * High point register for channel 6 - */ -#define LEDC_CH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x7c) -/** LEDC_HPOINT_CH6 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 6. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH6 0x000FFFFFU -#define LEDC_HPOINT_CH6_M (LEDC_HPOINT_CH6_V << LEDC_HPOINT_CH6_S) -#define LEDC_HPOINT_CH6_V 0x000FFFFFU -#define LEDC_HPOINT_CH6_S 0 - -/** LEDC_CH6_DUTY_REG register - * Initial duty cycle register for channel 6 - */ -#define LEDC_CH6_DUTY_REG (DR_REG_LEDC_BASE + 0x80) -/** LEDC_DUTY_CH6 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 6. - */ -#define LEDC_DUTY_CH6 0x01FFFFFFU -#define LEDC_DUTY_CH6_M (LEDC_DUTY_CH6_V << LEDC_DUTY_CH6_S) -#define LEDC_DUTY_CH6_V 0x01FFFFFFU -#define LEDC_DUTY_CH6_S 0 - -/** LEDC_CH6_CONF1_REG register - * Configuration register 1 for channel 6 - */ -#define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84) -/** LEDC_DUTY_START_CH6 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH6 (BIT(31)) -#define LEDC_DUTY_START_CH6_M (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S) -#define LEDC_DUTY_START_CH6_V 0x00000001U -#define LEDC_DUTY_START_CH6_S 31 - -/** LEDC_CH6_DUTY_R_REG register - * Current duty cycle register for channel 6 - */ -#define LEDC_CH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x88) -/** LEDC_DUTY_CH6_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 6. - */ -#define LEDC_DUTY_CH6_R 0x01FFFFFFU -#define LEDC_DUTY_CH6_R_M (LEDC_DUTY_CH6_R_V << LEDC_DUTY_CH6_R_S) -#define LEDC_DUTY_CH6_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH6_R_S 0 - -/** LEDC_CH7_CONF0_REG register - * Configuration register 0 for channel 7 - */ -#define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c) -/** LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 7 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH7 0x00000003U -#define LEDC_TIMER_SEL_CH7_M (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S) -#define LEDC_TIMER_SEL_CH7_V 0x00000003U -#define LEDC_TIMER_SEL_CH7_S 0 -/** LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 7. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH7 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH7_M (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S) -#define LEDC_SIG_OUT_EN_CH7_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH7_S 2 -/** LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 7 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH7 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH7 (BIT(3)) -#define LEDC_IDLE_LV_CH7_M (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S) -#define LEDC_IDLE_LV_CH7_V 0x00000001U -#define LEDC_IDLE_LV_CH7_S 3 -/** LEDC_PARA_UP_CH7 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH7, LEDC_DUTY_START_CH7, - * LEDC_SIG_OUT_EN_CH7, LEDC_TIMER_SEL_CH7, LEDC_DUTY_NUM_CH7, LEDC_DUTY_CYCLE_CH7, - * LEDC_DUTY_SCALE_CH7, LEDC_DUTY_INC_CH7, and LEDC_OVF_CNT_EN_CH7 fields for channel - * 7, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH7 (BIT(4)) -#define LEDC_PARA_UP_CH7_M (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S) -#define LEDC_PARA_UP_CH7_V 0x00000001U -#define LEDC_PARA_UP_CH7_S 4 -/** LEDC_OVF_NUM_CH7 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH7_INT interrupt - * will be triggered when channel 7 overflows for (LEDC_OVF_NUM_CH7 + 1) times. - */ -#define LEDC_OVF_NUM_CH7 0x000003FFU -#define LEDC_OVF_NUM_CH7_M (LEDC_OVF_NUM_CH7_V << LEDC_OVF_NUM_CH7_S) -#define LEDC_OVF_NUM_CH7_V 0x000003FFU -#define LEDC_OVF_NUM_CH7_S 5 -/** LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 7. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH7 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH7_M (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S) -#define LEDC_OVF_CNT_EN_CH7_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH7_S 15 -/** LEDC_OVF_CNT_RESET_CH7 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 7. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH7 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH7_M (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S) -#define LEDC_OVF_CNT_RESET_CH7_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH7_S 16 - -/** LEDC_CH7_HPOINT_REG register - * High point register for channel 7 - */ -#define LEDC_CH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x90) -/** LEDC_HPOINT_CH7 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 7. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH7 0x000FFFFFU -#define LEDC_HPOINT_CH7_M (LEDC_HPOINT_CH7_V << LEDC_HPOINT_CH7_S) -#define LEDC_HPOINT_CH7_V 0x000FFFFFU -#define LEDC_HPOINT_CH7_S 0 - -/** LEDC_CH7_DUTY_REG register - * Initial duty cycle register for channel 7 - */ -#define LEDC_CH7_DUTY_REG (DR_REG_LEDC_BASE + 0x94) -/** LEDC_DUTY_CH7 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 7. - */ -#define LEDC_DUTY_CH7 0x01FFFFFFU -#define LEDC_DUTY_CH7_M (LEDC_DUTY_CH7_V << LEDC_DUTY_CH7_S) -#define LEDC_DUTY_CH7_V 0x01FFFFFFU -#define LEDC_DUTY_CH7_S 0 - -/** LEDC_CH7_CONF1_REG register - * Configuration register 1 for channel 7 - */ -#define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98) -/** LEDC_DUTY_START_CH7 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH7 (BIT(31)) -#define LEDC_DUTY_START_CH7_M (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S) -#define LEDC_DUTY_START_CH7_V 0x00000001U -#define LEDC_DUTY_START_CH7_S 31 - -/** LEDC_CH7_DUTY_R_REG register - * Current duty cycle register for channel 7 - */ -#define LEDC_CH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x9c) -/** LEDC_DUTY_CH7_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 7. - */ -#define LEDC_DUTY_CH7_R 0x01FFFFFFU -#define LEDC_DUTY_CH7_R_M (LEDC_DUTY_CH7_R_V << LEDC_DUTY_CH7_R_S) -#define LEDC_DUTY_CH7_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH7_R_S 0 - -/** LEDC_TIMER0_CONF_REG register - * Timer 0 configuration register - */ -#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0) -/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer 0. - */ -#define LEDC_TIMER0_DUTY_RES 0x0000001FU -#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) -#define LEDC_TIMER0_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER0_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer 0.The least significant eight bits - * represent the fractional part. - */ -#define LEDC_CLK_DIV_TIMER0 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) -#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER0_S 5 -/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 0. - * 0: Normal - * 1: Pause - */ -#define LEDC_TIMER0_PAUSE (BIT(23)) -#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) -#define LEDC_TIMER0_PAUSE_V 0x00000001U -#define LEDC_TIMER0_PAUSE_S 23 -/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 0. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ -#define LEDC_TIMER0_RST (BIT(24)) -#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) -#define LEDC_TIMER0_RST_V 0x00000001U -#define LEDC_TIMER0_RST_S 24 -/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER0 and LEDC_TIMER0_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_TIMER0_PARA_UP (BIT(26)) -#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) -#define LEDC_TIMER0_PARA_UP_V 0x00000001U -#define LEDC_TIMER0_PARA_UP_S 26 - -/** LEDC_TIMER0_VALUE_REG register - * Timer 0 current counter value register - */ -#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4) -/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer 0. - */ -#define LEDC_TIMER0_CNT 0x000FFFFFU -#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) -#define LEDC_TIMER0_CNT_V 0x000FFFFFU -#define LEDC_TIMER0_CNT_S 0 - -/** LEDC_TIMER1_CONF_REG register - * Timer 1 configuration register - */ -#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8) -/** LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer 1. - */ -#define LEDC_TIMER1_DUTY_RES 0x0000001FU -#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S) -#define LEDC_TIMER1_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER1_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer 1.The least significant eight bits - * represent the fractional part. - */ -#define LEDC_CLK_DIV_TIMER1 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S) -#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER1_S 5 -/** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 1. - * 0: Normal - * 1: Pause - */ -#define LEDC_TIMER1_PAUSE (BIT(23)) -#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) -#define LEDC_TIMER1_PAUSE_V 0x00000001U -#define LEDC_TIMER1_PAUSE_S 23 -/** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 1. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ -#define LEDC_TIMER1_RST (BIT(24)) -#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) -#define LEDC_TIMER1_RST_V 0x00000001U -#define LEDC_TIMER1_RST_S 24 -/** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and LEDC_TIMER1_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_TIMER1_PARA_UP (BIT(26)) -#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) -#define LEDC_TIMER1_PARA_UP_V 0x00000001U -#define LEDC_TIMER1_PARA_UP_S 26 - -/** LEDC_TIMER1_VALUE_REG register - * Timer 1 current counter value register - */ -#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac) -/** LEDC_TIMER1_CNT : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer 1. - */ -#define LEDC_TIMER1_CNT 0x000FFFFFU -#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S) -#define LEDC_TIMER1_CNT_V 0x000FFFFFU -#define LEDC_TIMER1_CNT_S 0 - -/** LEDC_TIMER2_CONF_REG register - * Timer 2 configuration register - */ -#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0) -/** LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer 2. - */ -#define LEDC_TIMER2_DUTY_RES 0x0000001FU -#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S) -#define LEDC_TIMER2_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER2_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer 2.The least significant eight bits - * represent the fractional part. - */ -#define LEDC_CLK_DIV_TIMER2 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S) -#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER2_S 5 -/** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 2. - * 0: Normal - * 1: Pause - */ -#define LEDC_TIMER2_PAUSE (BIT(23)) -#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) -#define LEDC_TIMER2_PAUSE_V 0x00000001U -#define LEDC_TIMER2_PAUSE_S 23 -/** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 2. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ -#define LEDC_TIMER2_RST (BIT(24)) -#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) -#define LEDC_TIMER2_RST_V 0x00000001U -#define LEDC_TIMER2_RST_S 24 -/** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and LEDC_TIMER2_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_TIMER2_PARA_UP (BIT(26)) -#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) -#define LEDC_TIMER2_PARA_UP_V 0x00000001U -#define LEDC_TIMER2_PARA_UP_S 26 - -/** LEDC_TIMER2_VALUE_REG register - * Timer 2 current counter value register - */ -#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4) -/** LEDC_TIMER2_CNT : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer 2. - */ -#define LEDC_TIMER2_CNT 0x000FFFFFU -#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S) -#define LEDC_TIMER2_CNT_V 0x000FFFFFU -#define LEDC_TIMER2_CNT_S 0 - -/** LEDC_TIMER3_CONF_REG register - * Timer 3 configuration register - */ -#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8) -/** LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer 3. - */ -#define LEDC_TIMER3_DUTY_RES 0x0000001FU -#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S) -#define LEDC_TIMER3_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER3_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer 3.The least significant eight bits - * represent the fractional part. - */ -#define LEDC_CLK_DIV_TIMER3 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S) -#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER3_S 5 -/** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 3. - * 0: Normal - * 1: Pause - */ -#define LEDC_TIMER3_PAUSE (BIT(23)) -#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) -#define LEDC_TIMER3_PAUSE_V 0x00000001U -#define LEDC_TIMER3_PAUSE_S 23 -/** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 3. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ -#define LEDC_TIMER3_RST (BIT(24)) -#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) -#define LEDC_TIMER3_RST_V 0x00000001U -#define LEDC_TIMER3_RST_S 24 -/** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and LEDC_TIMER3_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_TIMER3_PARA_UP (BIT(26)) -#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) -#define LEDC_TIMER3_PARA_UP_V 0x00000001U -#define LEDC_TIMER3_PARA_UP_S 26 - -/** LEDC_TIMER3_VALUE_REG register - * Timer 3 current counter value register - */ -#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc) -/** LEDC_TIMER3_CNT : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer 3. - */ -#define LEDC_TIMER3_CNT 0x000FFFFFU -#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S) -#define LEDC_TIMER3_CNT_V 0x000FFFFFU -#define LEDC_TIMER3_CNT_S 0 - -/** LEDC_INT_RAW_REG register - * Interrupt raw status register - */ -#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0) -/** LEDC_TIMER0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the - * timer0 has reached its maximum counter value. - */ -#define LEDC_TIMER0_OVF_INT_RAW (BIT(0)) -#define LEDC_TIMER0_OVF_INT_RAW_M (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S) -#define LEDC_TIMER0_OVF_INT_RAW_V 0x00000001U -#define LEDC_TIMER0_OVF_INT_RAW_S 0 -/** LEDC_TIMER1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the - * timer1 has reached its maximum counter value. - */ -#define LEDC_TIMER1_OVF_INT_RAW (BIT(1)) -#define LEDC_TIMER1_OVF_INT_RAW_M (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S) -#define LEDC_TIMER1_OVF_INT_RAW_V 0x00000001U -#define LEDC_TIMER1_OVF_INT_RAW_S 1 -/** LEDC_TIMER2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the - * timer2 has reached its maximum counter value. - */ -#define LEDC_TIMER2_OVF_INT_RAW (BIT(2)) -#define LEDC_TIMER2_OVF_INT_RAW_M (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S) -#define LEDC_TIMER2_OVF_INT_RAW_V 0x00000001U -#define LEDC_TIMER2_OVF_INT_RAW_S 2 -/** LEDC_TIMER3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the - * timer3 has reached its maximum counter value. - */ -#define LEDC_TIMER3_OVF_INT_RAW (BIT(3)) -#define LEDC_TIMER3_OVF_INT_RAW_M (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S) -#define LEDC_TIMER3_OVF_INT_RAW_V 0x00000001U -#define LEDC_TIMER3_OVF_INT_RAW_S 3 -/** LEDC_DUTY_CHNG_END_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S 4 -/** LEDC_DUTY_CHNG_END_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S 5 -/** LEDC_DUTY_CHNG_END_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S 6 -/** LEDC_DUTY_CHNG_END_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S 7 -/** LEDC_DUTY_CHNG_END_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S 8 -/** LEDC_DUTY_CHNG_END_CH5_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S 9 -/** LEDC_DUTY_CHNG_END_CH6_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_M (LEDC_DUTY_CHNG_END_CH6_INT_RAW_V << LEDC_DUTY_CHNG_END_CH6_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_S 10 -/** LEDC_DUTY_CHNG_END_CH7_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_M (LEDC_DUTY_CHNG_END_CH7_INT_RAW_V << LEDC_DUTY_CHNG_END_CH7_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_S 11 -/** LEDC_OVF_CNT_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. - */ -#define LEDC_OVF_CNT_CH0_INT_RAW (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_RAW_M (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S) -#define LEDC_OVF_CNT_CH0_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH0_INT_RAW_S 12 -/** LEDC_OVF_CNT_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. - */ -#define LEDC_OVF_CNT_CH1_INT_RAW (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_RAW_M (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S) -#define LEDC_OVF_CNT_CH1_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH1_INT_RAW_S 13 -/** LEDC_OVF_CNT_CH2_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. - */ -#define LEDC_OVF_CNT_CH2_INT_RAW (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_RAW_M (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S) -#define LEDC_OVF_CNT_CH2_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH2_INT_RAW_S 14 -/** LEDC_OVF_CNT_CH3_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. - */ -#define LEDC_OVF_CNT_CH3_INT_RAW (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_RAW_M (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S) -#define LEDC_OVF_CNT_CH3_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH3_INT_RAW_S 15 -/** LEDC_OVF_CNT_CH4_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. - */ -#define LEDC_OVF_CNT_CH4_INT_RAW (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_RAW_M (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S) -#define LEDC_OVF_CNT_CH4_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH4_INT_RAW_S 16 -/** LEDC_OVF_CNT_CH5_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. - */ -#define LEDC_OVF_CNT_CH5_INT_RAW (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_RAW_M (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S) -#define LEDC_OVF_CNT_CH5_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH5_INT_RAW_S 17 -/** LEDC_OVF_CNT_CH6_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. - */ -#define LEDC_OVF_CNT_CH6_INT_RAW (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_RAW_M (LEDC_OVF_CNT_CH6_INT_RAW_V << LEDC_OVF_CNT_CH6_INT_RAW_S) -#define LEDC_OVF_CNT_CH6_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH6_INT_RAW_S 18 -/** LEDC_OVF_CNT_CH7_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. - */ -#define LEDC_OVF_CNT_CH7_INT_RAW (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_RAW_M (LEDC_OVF_CNT_CH7_INT_RAW_V << LEDC_OVF_CNT_CH7_INT_RAW_S) -#define LEDC_OVF_CNT_CH7_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH7_INT_RAW_S 19 - -/** LEDC_INT_ST_REG register - * Interrupt masked status register - */ -#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4) -/** LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only - * when LEDC_TIMER0_OVF_INT_ENA is set to 1. - */ -#define LEDC_TIMER0_OVF_INT_ST (BIT(0)) -#define LEDC_TIMER0_OVF_INT_ST_M (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S) -#define LEDC_TIMER0_OVF_INT_ST_V 0x00000001U -#define LEDC_TIMER0_OVF_INT_ST_S 0 -/** LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only - * when LEDC_TIMER1_OVF_INT_ENA is set to 1. - */ -#define LEDC_TIMER1_OVF_INT_ST (BIT(1)) -#define LEDC_TIMER1_OVF_INT_ST_M (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S) -#define LEDC_TIMER1_OVF_INT_ST_V 0x00000001U -#define LEDC_TIMER1_OVF_INT_ST_S 1 -/** LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only - * when LEDC_TIMER2_OVF_INT_ENA is set to 1. - */ -#define LEDC_TIMER2_OVF_INT_ST (BIT(2)) -#define LEDC_TIMER2_OVF_INT_ST_M (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S) -#define LEDC_TIMER2_OVF_INT_ST_V 0x00000001U -#define LEDC_TIMER2_OVF_INT_ST_S 2 -/** LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only - * when LEDC_TIMER3_OVF_INT_ENA is set to 1. - */ -#define LEDC_TIMER3_OVF_INT_ST (BIT(3)) -#define LEDC_TIMER3_OVF_INT_ST_M (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S) -#define LEDC_TIMER3_OVF_INT_ST_V 0x00000001U -#define LEDC_TIMER3_OVF_INT_ST_S 3 -/** LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH0_INT_ST (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S 4 -/** LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH1_INT_ST (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S 5 -/** LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH2_INT_ST (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S 6 -/** LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH3_INT_ST (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S 7 -/** LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH4_INT_ST (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S 8 -/** LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH5_INT_ST (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S 9 -/** LEDC_DUTY_CHNG_END_CH6_INT_ST : RO; bitpos: [10]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH6_INT_ST (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_ST_M (LEDC_DUTY_CHNG_END_CH6_INT_ST_V << LEDC_DUTY_CHNG_END_CH6_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH6_INT_ST_S 10 -/** LEDC_DUTY_CHNG_END_CH7_INT_ST : RO; bitpos: [11]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH7_INT_ST (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_ST_M (LEDC_DUTY_CHNG_END_CH7_INT_ST_V << LEDC_DUTY_CHNG_END_CH7_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH7_INT_ST_S 11 -/** LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only - * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH0_INT_ST (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_ST_M (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S) -#define LEDC_OVF_CNT_CH0_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH0_INT_ST_S 12 -/** LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only - * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH1_INT_ST (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_ST_M (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S) -#define LEDC_OVF_CNT_CH1_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH1_INT_ST_S 13 -/** LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only - * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH2_INT_ST (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_ST_M (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S) -#define LEDC_OVF_CNT_CH2_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH2_INT_ST_S 14 -/** LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only - * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH3_INT_ST (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_ST_M (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S) -#define LEDC_OVF_CNT_CH3_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH3_INT_ST_S 15 -/** LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only - * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH4_INT_ST (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_ST_M (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S) -#define LEDC_OVF_CNT_CH4_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH4_INT_ST_S 16 -/** LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only - * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH5_INT_ST (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_ST_M (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S) -#define LEDC_OVF_CNT_CH5_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH5_INT_ST_S 17 -/** LEDC_OVF_CNT_CH6_INT_ST : RO; bitpos: [18]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only - * when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH6_INT_ST (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_ST_M (LEDC_OVF_CNT_CH6_INT_ST_V << LEDC_OVF_CNT_CH6_INT_ST_S) -#define LEDC_OVF_CNT_CH6_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH6_INT_ST_S 18 -/** LEDC_OVF_CNT_CH7_INT_ST : RO; bitpos: [19]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only - * when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH7_INT_ST (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_ST_M (LEDC_OVF_CNT_CH7_INT_ST_V << LEDC_OVF_CNT_CH7_INT_ST_S) -#define LEDC_OVF_CNT_CH7_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH7_INT_ST_S 19 - -/** LEDC_INT_ENA_REG register - * Interrupt enable register - */ -#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8) -/** LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. - */ -#define LEDC_TIMER0_OVF_INT_ENA (BIT(0)) -#define LEDC_TIMER0_OVF_INT_ENA_M (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S) -#define LEDC_TIMER0_OVF_INT_ENA_V 0x00000001U -#define LEDC_TIMER0_OVF_INT_ENA_S 0 -/** LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. - */ -#define LEDC_TIMER1_OVF_INT_ENA (BIT(1)) -#define LEDC_TIMER1_OVF_INT_ENA_M (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S) -#define LEDC_TIMER1_OVF_INT_ENA_V 0x00000001U -#define LEDC_TIMER1_OVF_INT_ENA_S 1 -/** LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. - */ -#define LEDC_TIMER2_OVF_INT_ENA (BIT(2)) -#define LEDC_TIMER2_OVF_INT_ENA_M (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S) -#define LEDC_TIMER2_OVF_INT_ENA_V 0x00000001U -#define LEDC_TIMER2_OVF_INT_ENA_S 2 -/** LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. - */ -#define LEDC_TIMER3_OVF_INT_ENA (BIT(3)) -#define LEDC_TIMER3_OVF_INT_ENA_M (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S) -#define LEDC_TIMER3_OVF_INT_ENA_V 0x00000001U -#define LEDC_TIMER3_OVF_INT_ENA_S 3 -/** LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. - */ -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S 4 -/** LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. - */ -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S 5 -/** LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. - */ -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S 6 -/** LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. - */ -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S 7 -/** LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. - */ -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S 8 -/** LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. - */ -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S 9 -/** LEDC_DUTY_CHNG_END_CH6_INT_ENA : R/W; bitpos: [10]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. - */ -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_M (LEDC_DUTY_CHNG_END_CH6_INT_ENA_V << LEDC_DUTY_CHNG_END_CH6_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_S 10 -/** LEDC_DUTY_CHNG_END_CH7_INT_ENA : R/W; bitpos: [11]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. - */ -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_M (LEDC_DUTY_CHNG_END_CH7_INT_ENA_V << LEDC_DUTY_CHNG_END_CH7_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_S 11 -/** LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. - */ -#define LEDC_OVF_CNT_CH0_INT_ENA (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_ENA_M (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S) -#define LEDC_OVF_CNT_CH0_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH0_INT_ENA_S 12 -/** LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. - */ -#define LEDC_OVF_CNT_CH1_INT_ENA (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_ENA_M (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S) -#define LEDC_OVF_CNT_CH1_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH1_INT_ENA_S 13 -/** LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. - */ -#define LEDC_OVF_CNT_CH2_INT_ENA (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_ENA_M (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S) -#define LEDC_OVF_CNT_CH2_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH2_INT_ENA_S 14 -/** LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. - */ -#define LEDC_OVF_CNT_CH3_INT_ENA (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_ENA_M (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S) -#define LEDC_OVF_CNT_CH3_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH3_INT_ENA_S 15 -/** LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. - */ -#define LEDC_OVF_CNT_CH4_INT_ENA (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_ENA_M (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S) -#define LEDC_OVF_CNT_CH4_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH4_INT_ENA_S 16 -/** LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. - */ -#define LEDC_OVF_CNT_CH5_INT_ENA (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_ENA_M (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S) -#define LEDC_OVF_CNT_CH5_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH5_INT_ENA_S 17 -/** LEDC_OVF_CNT_CH6_INT_ENA : R/W; bitpos: [18]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. - */ -#define LEDC_OVF_CNT_CH6_INT_ENA (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_ENA_M (LEDC_OVF_CNT_CH6_INT_ENA_V << LEDC_OVF_CNT_CH6_INT_ENA_S) -#define LEDC_OVF_CNT_CH6_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH6_INT_ENA_S 18 -/** LEDC_OVF_CNT_CH7_INT_ENA : R/W; bitpos: [19]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. - */ -#define LEDC_OVF_CNT_CH7_INT_ENA (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_ENA_M (LEDC_OVF_CNT_CH7_INT_ENA_V << LEDC_OVF_CNT_CH7_INT_ENA_S) -#define LEDC_OVF_CNT_CH7_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH7_INT_ENA_S 19 - -/** LEDC_INT_CLR_REG register - * Interrupt clear register - */ -#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc) -/** LEDC_TIMER0_OVF_INT_CLR : WT; bitpos: [0]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. - */ -#define LEDC_TIMER0_OVF_INT_CLR (BIT(0)) -#define LEDC_TIMER0_OVF_INT_CLR_M (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S) -#define LEDC_TIMER0_OVF_INT_CLR_V 0x00000001U -#define LEDC_TIMER0_OVF_INT_CLR_S 0 -/** LEDC_TIMER1_OVF_INT_CLR : WT; bitpos: [1]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. - */ -#define LEDC_TIMER1_OVF_INT_CLR (BIT(1)) -#define LEDC_TIMER1_OVF_INT_CLR_M (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S) -#define LEDC_TIMER1_OVF_INT_CLR_V 0x00000001U -#define LEDC_TIMER1_OVF_INT_CLR_S 1 -/** LEDC_TIMER2_OVF_INT_CLR : WT; bitpos: [2]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. - */ -#define LEDC_TIMER2_OVF_INT_CLR (BIT(2)) -#define LEDC_TIMER2_OVF_INT_CLR_M (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S) -#define LEDC_TIMER2_OVF_INT_CLR_V 0x00000001U -#define LEDC_TIMER2_OVF_INT_CLR_S 2 -/** LEDC_TIMER3_OVF_INT_CLR : WT; bitpos: [3]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. - */ -#define LEDC_TIMER3_OVF_INT_CLR (BIT(3)) -#define LEDC_TIMER3_OVF_INT_CLR_M (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S) -#define LEDC_TIMER3_OVF_INT_CLR_V 0x00000001U -#define LEDC_TIMER3_OVF_INT_CLR_S 3 -/** LEDC_DUTY_CHNG_END_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. - */ -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S 4 -/** LEDC_DUTY_CHNG_END_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. - */ -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S 5 -/** LEDC_DUTY_CHNG_END_CH2_INT_CLR : WT; bitpos: [6]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. - */ -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S 6 -/** LEDC_DUTY_CHNG_END_CH3_INT_CLR : WT; bitpos: [7]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. - */ -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S 7 -/** LEDC_DUTY_CHNG_END_CH4_INT_CLR : WT; bitpos: [8]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. - */ -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S 8 -/** LEDC_DUTY_CHNG_END_CH5_INT_CLR : WT; bitpos: [9]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. - */ -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S 9 -/** LEDC_DUTY_CHNG_END_CH6_INT_CLR : WT; bitpos: [10]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. - */ -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_M (LEDC_DUTY_CHNG_END_CH6_INT_CLR_V << LEDC_DUTY_CHNG_END_CH6_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_S 10 -/** LEDC_DUTY_CHNG_END_CH7_INT_CLR : WT; bitpos: [11]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. - */ -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_M (LEDC_DUTY_CHNG_END_CH7_INT_CLR_V << LEDC_DUTY_CHNG_END_CH7_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_S 11 -/** LEDC_OVF_CNT_CH0_INT_CLR : WT; bitpos: [12]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. - */ -#define LEDC_OVF_CNT_CH0_INT_CLR (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_CLR_M (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S) -#define LEDC_OVF_CNT_CH0_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH0_INT_CLR_S 12 -/** LEDC_OVF_CNT_CH1_INT_CLR : WT; bitpos: [13]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. - */ -#define LEDC_OVF_CNT_CH1_INT_CLR (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_CLR_M (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S) -#define LEDC_OVF_CNT_CH1_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH1_INT_CLR_S 13 -/** LEDC_OVF_CNT_CH2_INT_CLR : WT; bitpos: [14]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. - */ -#define LEDC_OVF_CNT_CH2_INT_CLR (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_CLR_M (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S) -#define LEDC_OVF_CNT_CH2_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH2_INT_CLR_S 14 -/** LEDC_OVF_CNT_CH3_INT_CLR : WT; bitpos: [15]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. - */ -#define LEDC_OVF_CNT_CH3_INT_CLR (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_CLR_M (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S) -#define LEDC_OVF_CNT_CH3_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH3_INT_CLR_S 15 -/** LEDC_OVF_CNT_CH4_INT_CLR : WT; bitpos: [16]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. - */ -#define LEDC_OVF_CNT_CH4_INT_CLR (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_CLR_M (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S) -#define LEDC_OVF_CNT_CH4_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH4_INT_CLR_S 16 -/** LEDC_OVF_CNT_CH5_INT_CLR : WT; bitpos: [17]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. - */ -#define LEDC_OVF_CNT_CH5_INT_CLR (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_CLR_M (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S) -#define LEDC_OVF_CNT_CH5_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH5_INT_CLR_S 17 -/** LEDC_OVF_CNT_CH6_INT_CLR : WT; bitpos: [18]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. - */ -#define LEDC_OVF_CNT_CH6_INT_CLR (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_CLR_M (LEDC_OVF_CNT_CH6_INT_CLR_V << LEDC_OVF_CNT_CH6_INT_CLR_S) -#define LEDC_OVF_CNT_CH6_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH6_INT_CLR_S 18 -/** LEDC_OVF_CNT_CH7_INT_CLR : WT; bitpos: [19]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. - */ -#define LEDC_OVF_CNT_CH7_INT_CLR (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_CLR_M (LEDC_OVF_CNT_CH7_INT_CLR_V << LEDC_OVF_CNT_CH7_INT_CLR_S) -#define LEDC_OVF_CNT_CH7_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH7_INT_CLR_S 19 - -/** LEDC_CH0_GAMMA_CONF_REG register - * Ledc ch0 gamma config register. - */ -#define LEDC_CH0_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x100) -/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch0. - */ -#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) -#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch0. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) -#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH0_GAMMA_PAUSE_S 5 -/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch0. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH0_GAMMA_RESUME (BIT(6)) -#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) -#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH0_GAMMA_RESUME_S 6 - -/** LEDC_CH1_GAMMA_CONF_REG register - * Ledc ch1 gamma config register. - */ -#define LEDC_CH1_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x104) -/** LEDC_CH1_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch1. - */ -#define LEDC_CH1_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH1_GAMMA_ENTRY_NUM_M (LEDC_CH1_GAMMA_ENTRY_NUM_V << LEDC_CH1_GAMMA_ENTRY_NUM_S) -#define LEDC_CH1_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH1_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch1. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH1_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH1_GAMMA_PAUSE_M (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S) -#define LEDC_CH1_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH1_GAMMA_PAUSE_S 5 -/** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch1. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH1_GAMMA_RESUME (BIT(6)) -#define LEDC_CH1_GAMMA_RESUME_M (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S) -#define LEDC_CH1_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH1_GAMMA_RESUME_S 6 - -/** LEDC_CH2_GAMMA_CONF_REG register - * Ledc ch2 gamma config register. - */ -#define LEDC_CH2_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x108) -/** LEDC_CH2_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch2. - */ -#define LEDC_CH2_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH2_GAMMA_ENTRY_NUM_M (LEDC_CH2_GAMMA_ENTRY_NUM_V << LEDC_CH2_GAMMA_ENTRY_NUM_S) -#define LEDC_CH2_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH2_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch2. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH2_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH2_GAMMA_PAUSE_M (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S) -#define LEDC_CH2_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH2_GAMMA_PAUSE_S 5 -/** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch2. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH2_GAMMA_RESUME (BIT(6)) -#define LEDC_CH2_GAMMA_RESUME_M (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S) -#define LEDC_CH2_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH2_GAMMA_RESUME_S 6 - -/** LEDC_CH3_GAMMA_CONF_REG register - * Ledc ch3 gamma config register. - */ -#define LEDC_CH3_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x10c) -/** LEDC_CH3_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch3. - */ -#define LEDC_CH3_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH3_GAMMA_ENTRY_NUM_M (LEDC_CH3_GAMMA_ENTRY_NUM_V << LEDC_CH3_GAMMA_ENTRY_NUM_S) -#define LEDC_CH3_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH3_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch3. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH3_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH3_GAMMA_PAUSE_M (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S) -#define LEDC_CH3_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH3_GAMMA_PAUSE_S 5 -/** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch3. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH3_GAMMA_RESUME (BIT(6)) -#define LEDC_CH3_GAMMA_RESUME_M (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S) -#define LEDC_CH3_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH3_GAMMA_RESUME_S 6 - -/** LEDC_CH4_GAMMA_CONF_REG register - * Ledc ch4 gamma config register. - */ -#define LEDC_CH4_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x110) -/** LEDC_CH4_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch4. - */ -#define LEDC_CH4_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH4_GAMMA_ENTRY_NUM_M (LEDC_CH4_GAMMA_ENTRY_NUM_V << LEDC_CH4_GAMMA_ENTRY_NUM_S) -#define LEDC_CH4_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH4_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch4. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH4_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH4_GAMMA_PAUSE_M (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S) -#define LEDC_CH4_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH4_GAMMA_PAUSE_S 5 -/** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch4. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH4_GAMMA_RESUME (BIT(6)) -#define LEDC_CH4_GAMMA_RESUME_M (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S) -#define LEDC_CH4_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH4_GAMMA_RESUME_S 6 - -/** LEDC_CH5_GAMMA_CONF_REG register - * Ledc ch5 gamma config register. - */ -#define LEDC_CH5_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x114) -/** LEDC_CH5_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch5. - */ -#define LEDC_CH5_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH5_GAMMA_ENTRY_NUM_M (LEDC_CH5_GAMMA_ENTRY_NUM_V << LEDC_CH5_GAMMA_ENTRY_NUM_S) -#define LEDC_CH5_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH5_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch5. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH5_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH5_GAMMA_PAUSE_M (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S) -#define LEDC_CH5_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH5_GAMMA_PAUSE_S 5 -/** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch5. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH5_GAMMA_RESUME (BIT(6)) -#define LEDC_CH5_GAMMA_RESUME_M (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S) -#define LEDC_CH5_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH5_GAMMA_RESUME_S 6 - -/** LEDC_CH6_GAMMA_CONF_REG register - * Ledc ch6 gamma config register. - */ -#define LEDC_CH6_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x118) -/** LEDC_CH6_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch6. - */ -#define LEDC_CH6_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH6_GAMMA_ENTRY_NUM_M (LEDC_CH6_GAMMA_ENTRY_NUM_V << LEDC_CH6_GAMMA_ENTRY_NUM_S) -#define LEDC_CH6_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH6_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH6_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch6. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH6_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH6_GAMMA_PAUSE_M (LEDC_CH6_GAMMA_PAUSE_V << LEDC_CH6_GAMMA_PAUSE_S) -#define LEDC_CH6_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH6_GAMMA_PAUSE_S 5 -/** LEDC_CH6_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch6. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH6_GAMMA_RESUME (BIT(6)) -#define LEDC_CH6_GAMMA_RESUME_M (LEDC_CH6_GAMMA_RESUME_V << LEDC_CH6_GAMMA_RESUME_S) -#define LEDC_CH6_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH6_GAMMA_RESUME_S 6 - -/** LEDC_CH7_GAMMA_CONF_REG register - * Ledc ch7 gamma config register. - */ -#define LEDC_CH7_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x11c) -/** LEDC_CH7_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch7. - */ -#define LEDC_CH7_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH7_GAMMA_ENTRY_NUM_M (LEDC_CH7_GAMMA_ENTRY_NUM_V << LEDC_CH7_GAMMA_ENTRY_NUM_S) -#define LEDC_CH7_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH7_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH7_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch7. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH7_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH7_GAMMA_PAUSE_M (LEDC_CH7_GAMMA_PAUSE_V << LEDC_CH7_GAMMA_PAUSE_S) -#define LEDC_CH7_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH7_GAMMA_PAUSE_S 5 -/** LEDC_CH7_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch7. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH7_GAMMA_RESUME (BIT(6)) -#define LEDC_CH7_GAMMA_RESUME_M (LEDC_CH7_GAMMA_RESUME_V << LEDC_CH7_GAMMA_RESUME_S) -#define LEDC_CH7_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH7_GAMMA_RESUME_S 6 - -/** LEDC_EVT_TASK_EN0_REG register - * Ledc event task enable bit register0. - */ -#define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x120) -/** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH0_EN (BIT(0)) -#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S 0 -/** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH1_EN (BIT(1)) -#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S 1 -/** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH2_EN (BIT(2)) -#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S 2 -/** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH3_EN (BIT(3)) -#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S 3 -/** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH4_EN (BIT(4)) -#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S 4 -/** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH5_EN (BIT(5)) -#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S 5 -/** LEDC_EVT_DUTY_CHNG_END_CH6_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH6_EN (BIT(6)) -#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_M (LEDC_EVT_DUTY_CHNG_END_CH6_EN_V << LEDC_EVT_DUTY_CHNG_END_CH6_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_S 6 -/** LEDC_EVT_DUTY_CHNG_END_CH7_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH7_EN (BIT(7)) -#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_M (LEDC_EVT_DUTY_CHNG_END_CH7_EN_V << LEDC_EVT_DUTY_CHNG_END_CH7_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_S 7 -/** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH0_EN (BIT(8)) -#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S 8 -/** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH1_EN (BIT(9)) -#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S 9 -/** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH2_EN (BIT(10)) -#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S 10 -/** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH3_EN (BIT(11)) -#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S 11 -/** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH4_EN (BIT(12)) -#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S 12 -/** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH5_EN (BIT(13)) -#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S 13 -/** LEDC_EVT_OVF_CNT_PLS_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH6_EN (BIT(14)) -#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_M (LEDC_EVT_OVF_CNT_PLS_CH6_EN_V << LEDC_EVT_OVF_CNT_PLS_CH6_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_S 14 -/** LEDC_EVT_OVF_CNT_PLS_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH7_EN (BIT(15)) -#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_M (LEDC_EVT_OVF_CNT_PLS_CH7_EN_V << LEDC_EVT_OVF_CNT_PLS_CH7_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_S 15 -/** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the ledc_timer0_ovf event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME_OVF_TIMER0_EN (BIT(16)) -#define LEDC_EVT_TIME_OVF_TIMER0_EN_M (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S) -#define LEDC_EVT_TIME_OVF_TIMER0_EN_V 0x00000001U -#define LEDC_EVT_TIME_OVF_TIMER0_EN_S 16 -/** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable the ledc_timer1_ovf event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME_OVF_TIMER1_EN (BIT(17)) -#define LEDC_EVT_TIME_OVF_TIMER1_EN_M (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S) -#define LEDC_EVT_TIME_OVF_TIMER1_EN_V 0x00000001U -#define LEDC_EVT_TIME_OVF_TIMER1_EN_S 17 -/** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable the ledc_timer2_ovf event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME_OVF_TIMER2_EN (BIT(18)) -#define LEDC_EVT_TIME_OVF_TIMER2_EN_M (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S) -#define LEDC_EVT_TIME_OVF_TIMER2_EN_V 0x00000001U -#define LEDC_EVT_TIME_OVF_TIMER2_EN_S 18 -/** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable the ledc_timer3_ovf event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME_OVF_TIMER3_EN (BIT(19)) -#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S) -#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U -#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19 -/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable the ledc_timer0_cmp event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME0_CMP_EN (BIT(20)) -#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S) -#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIME0_CMP_EN_S 20 -/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable the ledc_timer1_cmp event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME1_CMP_EN (BIT(21)) -#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S) -#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIME1_CMP_EN_S 21 -/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable the ledc_timer2_cmp event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME2_CMP_EN (BIT(22)) -#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S) -#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIME2_CMP_EN_S 22 -/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable the ledc_timer3_cmp event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME3_CMP_EN (BIT(23)) -#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S) -#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIME3_CMP_EN_S 23 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN (BIT(24)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S 24 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN (BIT(25)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S 25 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN (BIT(26)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S 26 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN (BIT(27)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S 27 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN (BIT(28)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S 28 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN (BIT(29)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S 29 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN (BIT(30)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S 30 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN (BIT(31)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S 31 - -/** LEDC_EVT_TASK_EN1_REG register - * Ledc event task enable bit register1. - */ -#define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x124) -/** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_timer0_res_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER0_RES_UPDATE_EN (BIT(0)) -#define LEDC_TASK_TIMER0_RES_UPDATE_EN_M (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S) -#define LEDC_TASK_TIMER0_RES_UPDATE_EN_V 0x00000001U -#define LEDC_TASK_TIMER0_RES_UPDATE_EN_S 0 -/** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_timer1_res_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER1_RES_UPDATE_EN (BIT(1)) -#define LEDC_TASK_TIMER1_RES_UPDATE_EN_M (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S) -#define LEDC_TASK_TIMER1_RES_UPDATE_EN_V 0x00000001U -#define LEDC_TASK_TIMER1_RES_UPDATE_EN_S 1 -/** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_timer2_res_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER2_RES_UPDATE_EN (BIT(2)) -#define LEDC_TASK_TIMER2_RES_UPDATE_EN_M (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S) -#define LEDC_TASK_TIMER2_RES_UPDATE_EN_V 0x00000001U -#define LEDC_TASK_TIMER2_RES_UPDATE_EN_S 2 -/** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_timer3_res_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER3_RES_UPDATE_EN (BIT(3)) -#define LEDC_TASK_TIMER3_RES_UPDATE_EN_M (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S) -#define LEDC_TASK_TIMER3_RES_UPDATE_EN_V 0x00000001U -#define LEDC_TASK_TIMER3_RES_UPDATE_EN_S 3 -/** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_timer0_cap task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER0_CAP_EN (BIT(4)) -#define LEDC_TASK_TIMER0_CAP_EN_M (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S) -#define LEDC_TASK_TIMER0_CAP_EN_V 0x00000001U -#define LEDC_TASK_TIMER0_CAP_EN_S 4 -/** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_timer1_cap task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER1_CAP_EN (BIT(5)) -#define LEDC_TASK_TIMER1_CAP_EN_M (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S) -#define LEDC_TASK_TIMER1_CAP_EN_V 0x00000001U -#define LEDC_TASK_TIMER1_CAP_EN_S 5 -/** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_timer2_cap task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER2_CAP_EN (BIT(6)) -#define LEDC_TASK_TIMER2_CAP_EN_M (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S) -#define LEDC_TASK_TIMER2_CAP_EN_V 0x00000001U -#define LEDC_TASK_TIMER2_CAP_EN_S 6 -/** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_timer3_cap task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER3_CAP_EN (BIT(7)) -#define LEDC_TASK_TIMER3_CAP_EN_M (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S) -#define LEDC_TASK_TIMER3_CAP_EN_V 0x00000001U -#define LEDC_TASK_TIMER3_CAP_EN_S 7 -/** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH0_EN (BIT(8)) -#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S 8 -/** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH1_EN (BIT(9)) -#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S 9 -/** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH2_EN (BIT(10)) -#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S 10 -/** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH3_EN (BIT(11)) -#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S 11 -/** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH4_EN (BIT(12)) -#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S 12 -/** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH5_EN (BIT(13)) -#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S 13 -/** LEDC_TASK_SIG_OUT_DIS_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH6_EN (BIT(14)) -#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_M (LEDC_TASK_SIG_OUT_DIS_CH6_EN_V << LEDC_TASK_SIG_OUT_DIS_CH6_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_S 14 -/** LEDC_TASK_SIG_OUT_DIS_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH7_EN (BIT(15)) -#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_M (LEDC_TASK_SIG_OUT_DIS_CH7_EN_V << LEDC_TASK_SIG_OUT_DIS_CH7_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_S 15 -/** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH0_EN (BIT(16)) -#define LEDC_TASK_OVF_CNT_RST_CH0_EN_M (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH0_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH0_EN_S 16 -/** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH1_EN (BIT(17)) -#define LEDC_TASK_OVF_CNT_RST_CH1_EN_M (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH1_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH1_EN_S 17 -/** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH2_EN (BIT(18)) -#define LEDC_TASK_OVF_CNT_RST_CH2_EN_M (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH2_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH2_EN_S 18 -/** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH3_EN (BIT(19)) -#define LEDC_TASK_OVF_CNT_RST_CH3_EN_M (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH3_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH3_EN_S 19 -/** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH4_EN (BIT(20)) -#define LEDC_TASK_OVF_CNT_RST_CH4_EN_M (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH4_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH4_EN_S 20 -/** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH5_EN (BIT(21)) -#define LEDC_TASK_OVF_CNT_RST_CH5_EN_M (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH5_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH5_EN_S 21 -/** LEDC_TASK_OVF_CNT_RST_CH6_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH6_EN (BIT(22)) -#define LEDC_TASK_OVF_CNT_RST_CH6_EN_M (LEDC_TASK_OVF_CNT_RST_CH6_EN_V << LEDC_TASK_OVF_CNT_RST_CH6_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH6_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH6_EN_S 22 -/** LEDC_TASK_OVF_CNT_RST_CH7_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH7_EN (BIT(23)) -#define LEDC_TASK_OVF_CNT_RST_CH7_EN_M (LEDC_TASK_OVF_CNT_RST_CH7_EN_V << LEDC_TASK_OVF_CNT_RST_CH7_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH7_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH7_EN_S 23 -/** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable ledc_timer0_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER0_RST_EN (BIT(24)) -#define LEDC_TASK_TIMER0_RST_EN_M (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S) -#define LEDC_TASK_TIMER0_RST_EN_V 0x00000001U -#define LEDC_TASK_TIMER0_RST_EN_S 24 -/** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable ledc_timer1_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER1_RST_EN (BIT(25)) -#define LEDC_TASK_TIMER1_RST_EN_M (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S) -#define LEDC_TASK_TIMER1_RST_EN_V 0x00000001U -#define LEDC_TASK_TIMER1_RST_EN_S 25 -/** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable ledc_timer2_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER2_RST_EN (BIT(26)) -#define LEDC_TASK_TIMER2_RST_EN_M (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S) -#define LEDC_TASK_TIMER2_RST_EN_V 0x00000001U -#define LEDC_TASK_TIMER2_RST_EN_S 26 -/** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable ledc_timer3_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER3_RST_EN (BIT(27)) -#define LEDC_TASK_TIMER3_RST_EN_M (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S) -#define LEDC_TASK_TIMER3_RST_EN_V 0x00000001U -#define LEDC_TASK_TIMER3_RST_EN_S 27 -/** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable ledc_timer0_pause_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN (BIT(28)) -#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S) -#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V 0x00000001U -#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S 28 -/** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable ledc_timer1_pause_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN (BIT(29)) -#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S) -#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V 0x00000001U -#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S 29 -/** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable ledc_timer2_pause_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN (BIT(30)) -#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S) -#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V 0x00000001U -#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S 30 -/** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable ledc_timer3_pause_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN (BIT(31)) -#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S) -#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V 0x00000001U -#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S 31 - -/** LEDC_EVT_TASK_EN2_REG register - * Ledc event task enable bit register2. - */ -#define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x128) -/** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH0_EN (BIT(0)) -#define LEDC_TASK_GAMMA_RESTART_CH0_EN_M (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH0_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH0_EN_S 0 -/** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH1_EN (BIT(1)) -#define LEDC_TASK_GAMMA_RESTART_CH1_EN_M (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH1_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH1_EN_S 1 -/** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH2_EN (BIT(2)) -#define LEDC_TASK_GAMMA_RESTART_CH2_EN_M (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH2_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH2_EN_S 2 -/** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH3_EN (BIT(3)) -#define LEDC_TASK_GAMMA_RESTART_CH3_EN_M (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH3_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH3_EN_S 3 -/** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH4_EN (BIT(4)) -#define LEDC_TASK_GAMMA_RESTART_CH4_EN_M (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH4_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH4_EN_S 4 -/** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH5_EN (BIT(5)) -#define LEDC_TASK_GAMMA_RESTART_CH5_EN_M (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH5_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH5_EN_S 5 -/** LEDC_TASK_GAMMA_RESTART_CH6_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH6_EN (BIT(6)) -#define LEDC_TASK_GAMMA_RESTART_CH6_EN_M (LEDC_TASK_GAMMA_RESTART_CH6_EN_V << LEDC_TASK_GAMMA_RESTART_CH6_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH6_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH6_EN_S 6 -/** LEDC_TASK_GAMMA_RESTART_CH7_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH7_EN (BIT(7)) -#define LEDC_TASK_GAMMA_RESTART_CH7_EN_M (LEDC_TASK_GAMMA_RESTART_CH7_EN_V << LEDC_TASK_GAMMA_RESTART_CH7_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH7_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH7_EN_S 7 -/** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH0_EN (BIT(8)) -#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S 8 -/** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH1_EN (BIT(9)) -#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S 9 -/** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH2_EN (BIT(10)) -#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S 10 -/** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH3_EN (BIT(11)) -#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S 11 -/** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH4_EN (BIT(12)) -#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S 12 -/** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH5_EN (BIT(13)) -#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S 13 -/** LEDC_TASK_GAMMA_PAUSE_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH6_EN (BIT(14)) -#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_M (LEDC_TASK_GAMMA_PAUSE_CH6_EN_V << LEDC_TASK_GAMMA_PAUSE_CH6_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_S 14 -/** LEDC_TASK_GAMMA_PAUSE_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH7_EN (BIT(15)) -#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_M (LEDC_TASK_GAMMA_PAUSE_CH7_EN_V << LEDC_TASK_GAMMA_PAUSE_CH7_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_S 15 -/** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH0_EN (BIT(16)) -#define LEDC_TASK_GAMMA_RESUME_CH0_EN_M (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH0_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH0_EN_S 16 -/** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH1_EN (BIT(17)) -#define LEDC_TASK_GAMMA_RESUME_CH1_EN_M (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH1_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH1_EN_S 17 -/** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH2_EN (BIT(18)) -#define LEDC_TASK_GAMMA_RESUME_CH2_EN_M (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH2_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH2_EN_S 18 -/** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH3_EN (BIT(19)) -#define LEDC_TASK_GAMMA_RESUME_CH3_EN_M (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH3_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH3_EN_S 19 -/** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH4_EN (BIT(20)) -#define LEDC_TASK_GAMMA_RESUME_CH4_EN_M (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH4_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH4_EN_S 20 -/** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH5_EN (BIT(21)) -#define LEDC_TASK_GAMMA_RESUME_CH5_EN_M (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH5_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH5_EN_S 21 -/** LEDC_TASK_GAMMA_RESUME_CH6_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH6_EN (BIT(22)) -#define LEDC_TASK_GAMMA_RESUME_CH6_EN_M (LEDC_TASK_GAMMA_RESUME_CH6_EN_V << LEDC_TASK_GAMMA_RESUME_CH6_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH6_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH6_EN_S 22 -/** LEDC_TASK_GAMMA_RESUME_CH7_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH7_EN (BIT(23)) -#define LEDC_TASK_GAMMA_RESUME_CH7_EN_M (LEDC_TASK_GAMMA_RESUME_CH7_EN_V << LEDC_TASK_GAMMA_RESUME_CH7_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH7_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH7_EN_S 23 - -/** LEDC_TIMER0_CMP_REG register - * Ledc timer0 compare value register. - */ -#define LEDC_TIMER0_CMP_REG (DR_REG_LEDC_BASE + 0x140) -/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timer0. - */ -#define LEDC_TIMER0_CMP 0x000FFFFFU -#define LEDC_TIMER0_CMP_M (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S) -#define LEDC_TIMER0_CMP_V 0x000FFFFFU -#define LEDC_TIMER0_CMP_S 0 - -/** LEDC_TIMER1_CMP_REG register - * Ledc timer1 compare value register. - */ -#define LEDC_TIMER1_CMP_REG (DR_REG_LEDC_BASE + 0x144) -/** LEDC_TIMER1_CMP : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timer1. - */ -#define LEDC_TIMER1_CMP 0x000FFFFFU -#define LEDC_TIMER1_CMP_M (LEDC_TIMER1_CMP_V << LEDC_TIMER1_CMP_S) -#define LEDC_TIMER1_CMP_V 0x000FFFFFU -#define LEDC_TIMER1_CMP_S 0 - -/** LEDC_TIMER2_CMP_REG register - * Ledc timer2 compare value register. - */ -#define LEDC_TIMER2_CMP_REG (DR_REG_LEDC_BASE + 0x148) -/** LEDC_TIMER2_CMP : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timer2. - */ -#define LEDC_TIMER2_CMP 0x000FFFFFU -#define LEDC_TIMER2_CMP_M (LEDC_TIMER2_CMP_V << LEDC_TIMER2_CMP_S) -#define LEDC_TIMER2_CMP_V 0x000FFFFFU -#define LEDC_TIMER2_CMP_S 0 - -/** LEDC_TIMER3_CMP_REG register - * Ledc timer3 compare value register. - */ -#define LEDC_TIMER3_CMP_REG (DR_REG_LEDC_BASE + 0x14c) -/** LEDC_TIMER3_CMP : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timer3. - */ -#define LEDC_TIMER3_CMP 0x000FFFFFU -#define LEDC_TIMER3_CMP_M (LEDC_TIMER3_CMP_V << LEDC_TIMER3_CMP_S) -#define LEDC_TIMER3_CMP_V 0x000FFFFFU -#define LEDC_TIMER3_CMP_S 0 - -/** LEDC_TIMER0_CNT_CAP_REG register - * Ledc timer0 captured count value register. - */ -#define LEDC_TIMER0_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x150) -/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timer0 count value. - */ -#define LEDC_TIMER0_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER0_CNT_CAP_M (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S) -#define LEDC_TIMER0_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER0_CNT_CAP_S 0 - -/** LEDC_TIMER1_CNT_CAP_REG register - * Ledc timer1 captured count value register. - */ -#define LEDC_TIMER1_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x154) -/** LEDC_TIMER1_CNT_CAP : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timer1 count value. - */ -#define LEDC_TIMER1_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER1_CNT_CAP_M (LEDC_TIMER1_CNT_CAP_V << LEDC_TIMER1_CNT_CAP_S) -#define LEDC_TIMER1_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER1_CNT_CAP_S 0 - -/** LEDC_TIMER2_CNT_CAP_REG register - * Ledc timer2 captured count value register. - */ -#define LEDC_TIMER2_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x158) -/** LEDC_TIMER2_CNT_CAP : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timer2 count value. - */ -#define LEDC_TIMER2_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER2_CNT_CAP_M (LEDC_TIMER2_CNT_CAP_V << LEDC_TIMER2_CNT_CAP_S) -#define LEDC_TIMER2_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER2_CNT_CAP_S 0 - -/** LEDC_TIMER3_CNT_CAP_REG register - * Ledc timer3 captured count value register. - */ -#define LEDC_TIMER3_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x15c) -/** LEDC_TIMER3_CNT_CAP : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timer3 count value. - */ -#define LEDC_TIMER3_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER3_CNT_CAP_M (LEDC_TIMER3_CNT_CAP_V << LEDC_TIMER3_CNT_CAP_S) -#define LEDC_TIMER3_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER3_CNT_CAP_S 0 - -/** LEDC_CONF_REG register - * LEDC global configuration register - */ -#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x170) -/** LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0; - * Configures the clock source for the four timers. - * 0: APB_CLK - * 1: RC_FAST_CLK - * 2: XTAL_CLK - * 3: Invalid. No clock - */ -#define LEDC_APB_CLK_SEL 0x00000003U -#define LEDC_APB_CLK_SEL_M (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S) -#define LEDC_APB_CLK_SEL_V 0x00000003U -#define LEDC_APB_CLK_SEL_S 0 -/** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to open LEDC ch0 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram - * 1: Force open the clock gate for LEDC ch0 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH0 (BIT(2)) -#define LEDC_GAMMA_RAM_CLK_EN_CH0_M (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH0_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH0_S 2 -/** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0; - * Configures whether or not to open LEDC ch1 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram - * 1: Force open the clock gate for LEDC ch1 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH1 (BIT(3)) -#define LEDC_GAMMA_RAM_CLK_EN_CH1_M (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH1_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH1_S 3 -/** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to open LEDC ch2 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram - * 1: Force open the clock gate for LEDC ch2 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH2 (BIT(4)) -#define LEDC_GAMMA_RAM_CLK_EN_CH2_M (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH2_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH2_S 4 -/** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to open LEDC ch3 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram - * 1: Force open the clock gate for LEDC ch3 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH3 (BIT(5)) -#define LEDC_GAMMA_RAM_CLK_EN_CH3_M (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH3_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH3_S 5 -/** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to open LEDC ch4 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram - * 1: Force open the clock gate for LEDC ch4 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH4 (BIT(6)) -#define LEDC_GAMMA_RAM_CLK_EN_CH4_M (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH4_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH4_S 6 -/** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0; - * Configures whether or not to open LEDC ch5 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram - * 1: Force open the clock gate for LEDC ch5 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH5 (BIT(7)) -#define LEDC_GAMMA_RAM_CLK_EN_CH5_M (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH5_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH5_S 7 -/** LEDC_GAMMA_RAM_CLK_EN_CH6 : R/W; bitpos: [8]; default: 0; - * Configures whether or not to open LEDC ch6 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram - * 1: Force open the clock gate for LEDC ch6 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH6 (BIT(8)) -#define LEDC_GAMMA_RAM_CLK_EN_CH6_M (LEDC_GAMMA_RAM_CLK_EN_CH6_V << LEDC_GAMMA_RAM_CLK_EN_CH6_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH6_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH6_S 8 -/** LEDC_GAMMA_RAM_CLK_EN_CH7 : R/W; bitpos: [9]; default: 0; - * Configures whether or not to open LEDC ch7 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram - * 1: Force open the clock gate for LEDC ch7 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH7 (BIT(9)) -#define LEDC_GAMMA_RAM_CLK_EN_CH7_M (LEDC_GAMMA_RAM_CLK_EN_CH7_V << LEDC_GAMMA_RAM_CLK_EN_CH7_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH7_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH7_S 9 -/** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to open register clock gate. - * 0: Open the clock gate only when application writes registers - * 1: Force open the clock gate for register - */ -#define LEDC_CLK_EN (BIT(31)) -#define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) -#define LEDC_CLK_EN_V 0x00000001U -#define LEDC_CLK_EN_S 31 - -/** LEDC_DATE_REG register - * Version control register - */ -#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x174) -/** LEDC_LEDC_DATE : R/W; bitpos: [27:0]; default: 37765152; - * Configures the version. - */ -#define LEDC_LEDC_DATE 0x0FFFFFFFU -#define LEDC_LEDC_DATE_M (LEDC_LEDC_DATE_V << LEDC_LEDC_DATE_S) -#define LEDC_LEDC_DATE_V 0x0FFFFFFFU -#define LEDC_LEDC_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_struct.h deleted file mode 100644 index ef59597ded..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_struct.h +++ /dev/null @@ -1,1359 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Register */ -/** Type of chn_conf0 register - * Configuration register 0 for channel n - */ -typedef union { - struct { - /** timer_sel_chn : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel n selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ - uint32_t timer_sel_chn:2; - /** sig_out_en_chn : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel n. - * 0: Signal output disable - * 1: Signal output enable - */ - uint32_t sig_out_en_chn:1; - /** idle_lv_chn : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel n is inactive. Valid only when - * LEDC_SIG_OUT_EN_CHn is 0. - * 0: Output level is low - * 1: Output level is high - */ - uint32_t idle_lv_chn:1; - /** para_up_chn : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, - * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn, - * LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel - * n, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ - uint32_t para_up_chn:1; - /** ovf_num_chn : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt - * will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times. - */ - uint32_t ovf_num_chn:10; - /** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel n. - * 0: Disable - * 1: Enable - */ - uint32_t ovf_cnt_en_chn:1; - /** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel n. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ - uint32_t ovf_cnt_reset_chn:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} ledc_chn_conf0_reg_t; - -/** Type of chn_hpoint register - * High point register for channel n - */ -typedef union { - struct { - /** hpoint_chn : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel n. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ - uint32_t hpoint_chn:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_chn_hpoint_reg_t; - -/** Type of chn_duty register - * Initial duty cycle register for channel n - */ -typedef union { - struct { - /** duty_chn : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel n. - */ - uint32_t duty_chn:25; - uint32_t reserved_25:7; - }; - uint32_t val; -} ledc_chn_duty_reg_t; - -/** Type of chn_conf1 register - * Configuration register 1 for channel n - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** duty_start_chn : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ - uint32_t duty_start_chn:1; - }; - uint32_t val; -} ledc_chn_conf1_reg_t; - -/** Type of timern_conf register - * Timer n configuration register - */ -typedef union { - struct { - /** timern_duty_res : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer n. - */ - uint32_t timern_duty_res:5; - /** clk_div_timern : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer n.The least significant eight bits - * represent the fractional part. - */ - uint32_t clk_div_timern:18; - /** timern_pause : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer n. - * 0: Normal - * 1: Pause - */ - uint32_t timern_pause:1; - /** timern_rst : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer n. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ - uint32_t timern_rst:1; - uint32_t reserved_25:1; - /** timern_para_up : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMERn and LEDC_TIMERn_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ - uint32_t timern_para_up:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} ledc_timern_conf_reg_t; - -/** Type of chn_gamma_conf register - * Ledc chn gamma config register. - */ -typedef union { - struct { - /** chn_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC chn. - */ - uint32_t chn_gamma_entry_num:5; - /** chn_gamma_pause : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC chn. - * 0: Invalid. No effect - * 1: Pause - */ - uint32_t chn_gamma_pause:1; - /** chn_gamma_resume : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC chn. - * 0: Invalid. No effect - * 1: Resume - */ - uint32_t chn_gamma_resume:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ledc_chn_gamma_conf_reg_t; - -/** Type of evt_task_en0 register - * Ledc event task enable bit register0. - */ -typedef union { - struct { - /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch0_en:1; - /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch1_en:1; - /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch2_en:1; - /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch3_en:1; - /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch4_en:1; - /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch5_en:1; - /** evt_duty_chng_end_ch6_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch6_en:1; - /** evt_duty_chng_end_ch7_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch7_en:1; - /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch0_en:1; - /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch1_en:1; - /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch2_en:1; - /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch3_en:1; - /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch4_en:1; - /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch5_en:1; - /** evt_ovf_cnt_pls_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch6_en:1; - /** evt_ovf_cnt_pls_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch7_en:1; - /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the ledc_timer0_ovf event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time_ovf_timer0_en:1; - /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable the ledc_timer1_ovf event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time_ovf_timer1_en:1; - /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable the ledc_timer2_ovf event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time_ovf_timer2_en:1; - /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable the ledc_timer3_ovf event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time_ovf_timer3_en:1; - /** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable the ledc_timer0_cmp event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time0_cmp_en:1; - /** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable the ledc_timer1_cmp event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time1_cmp_en:1; - /** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable the ledc_timer2_cmp event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time2_cmp_en:1; - /** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable the ledc_timer3_cmp event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time3_cmp_en:1; - /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch0_en:1; - /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch1_en:1; - /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch2_en:1; - /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch3_en:1; - /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch4_en:1; - /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch5_en:1; - /** task_duty_scale_update_ch6_en : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch6_en:1; - /** task_duty_scale_update_ch7_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch7_en:1; - }; - uint32_t val; -} ledc_evt_task_en0_reg_t; - -/** Type of evt_task_en1 register - * Ledc event task enable bit register1. - */ -typedef union { - struct { - /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_timer0_res_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer0_res_update_en:1; - /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_timer1_res_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer1_res_update_en:1; - /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_timer2_res_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer2_res_update_en:1; - /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_timer3_res_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer3_res_update_en:1; - /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_timer0_cap task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer0_cap_en:1; - /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_timer1_cap task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer1_cap_en:1; - /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_timer2_cap task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer2_cap_en:1; - /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_timer3_cap task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer3_cap_en:1; - /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch0_en:1; - /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch1_en:1; - /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch2_en:1; - /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch3_en:1; - /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch4_en:1; - /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch5_en:1; - /** task_sig_out_dis_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch6_en:1; - /** task_sig_out_dis_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch7_en:1; - /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch0_en:1; - /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch1_en:1; - /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch2_en:1; - /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch3_en:1; - /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch4_en:1; - /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch5_en:1; - /** task_ovf_cnt_rst_ch6_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch6_en:1; - /** task_ovf_cnt_rst_ch7_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch7_en:1; - /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable ledc_timer0_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer0_rst_en:1; - /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable ledc_timer1_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer1_rst_en:1; - /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable ledc_timer2_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer2_rst_en:1; - /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable ledc_timer3_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer3_rst_en:1; - /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable ledc_timer0_pause_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer0_pause_resume_en:1; - /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable ledc_timer1_pause_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer1_pause_resume_en:1; - /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable ledc_timer2_pause_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer2_pause_resume_en:1; - /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable ledc_timer3_pause_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer3_pause_resume_en:1; - }; - uint32_t val; -} ledc_evt_task_en1_reg_t; - -/** Type of evt_task_en2 register - * Ledc event task enable bit register2. - */ -typedef union { - struct { - /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch0_en:1; - /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch1_en:1; - /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch2_en:1; - /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch3_en:1; - /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch4_en:1; - /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch5_en:1; - /** task_gamma_restart_ch6_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch6_en:1; - /** task_gamma_restart_ch7_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch7_en:1; - /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch0_en:1; - /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch1_en:1; - /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch2_en:1; - /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch3_en:1; - /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch4_en:1; - /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch5_en:1; - /** task_gamma_pause_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch6_en:1; - /** task_gamma_pause_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch7_en:1; - /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch0_en:1; - /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch1_en:1; - /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch2_en:1; - /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch3_en:1; - /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch4_en:1; - /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch5_en:1; - /** task_gamma_resume_ch6_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch6_en:1; - /** task_gamma_resume_ch7_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch7_en:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} ledc_evt_task_en2_reg_t; - -/** Type of timern_cmp register - * Ledc timern compare value register. - */ -typedef union { - struct { - /** timern_cmp : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timern. - */ - uint32_t timern_cmp:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_timern_cmp_reg_t; - -/** Type of conf register - * LEDC global configuration register - */ -typedef union { - struct { - /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0; - * Configures the clock source for the four timers. - * 0: APB_CLK - * 1: RC_FAST_CLK - * 2: XTAL_CLK - * 3: Invalid. No clock - */ - uint32_t apb_clk_sel:2; - /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to open LEDC ch0 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram - * 1: Force open the clock gate for LEDC ch0 gamma ram - */ - uint32_t gamma_ram_clk_en_ch0:1; - /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; - * Configures whether or not to open LEDC ch1 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram - * 1: Force open the clock gate for LEDC ch1 gamma ram - */ - uint32_t gamma_ram_clk_en_ch1:1; - /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to open LEDC ch2 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram - * 1: Force open the clock gate for LEDC ch2 gamma ram - */ - uint32_t gamma_ram_clk_en_ch2:1; - /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to open LEDC ch3 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram - * 1: Force open the clock gate for LEDC ch3 gamma ram - */ - uint32_t gamma_ram_clk_en_ch3:1; - /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to open LEDC ch4 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram - * 1: Force open the clock gate for LEDC ch4 gamma ram - */ - uint32_t gamma_ram_clk_en_ch4:1; - /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; - * Configures whether or not to open LEDC ch5 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram - * 1: Force open the clock gate for LEDC ch5 gamma ram - */ - uint32_t gamma_ram_clk_en_ch5:1; - /** gamma_ram_clk_en_ch6 : R/W; bitpos: [8]; default: 0; - * Configures whether or not to open LEDC ch6 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram - * 1: Force open the clock gate for LEDC ch6 gamma ram - */ - uint32_t gamma_ram_clk_en_ch6:1; - /** gamma_ram_clk_en_ch7 : R/W; bitpos: [9]; default: 0; - * Configures whether or not to open LEDC ch7 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram - * 1: Force open the clock gate for LEDC ch7 gamma ram - */ - uint32_t gamma_ram_clk_en_ch7:1; - uint32_t reserved_10:21; - /** clk_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to open register clock gate. - * 0: Open the clock gate only when application writes registers - * 1: Force open the clock gate for register - */ - uint32_t clk_en:1; - }; - uint32_t val; -} ledc_conf_reg_t; - - -/** Group: Status Register */ -/** Type of chn_duty_r register - * Current duty cycle register for channel n - */ -typedef union { - struct { - /** duty_chn_r : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel n. - */ - uint32_t duty_chn_r:25; - uint32_t reserved_25:7; - }; - uint32_t val; -} ledc_chn_duty_r_reg_t; - -/** Type of timern_value register - * Timer n current counter value register - */ -typedef union { - struct { - /** timern_cnt : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer n. - */ - uint32_t timern_cnt:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_timern_value_reg_t; - -/** Type of timern_cnt_cap register - * Ledc timern captured count value register. - */ -typedef union { - struct { - /** timern_cnt_cap : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timern count value. - */ - uint32_t timern_cnt_cap:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_timern_cnt_cap_reg_t; - - -/** Group: Interrupt Register */ -/** Type of int_raw register - * Interrupt raw status register - */ -typedef union { - struct { - /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the - * timer0 has reached its maximum counter value. - */ - uint32_t timer0_ovf_int_raw:1; - /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the - * timer1 has reached its maximum counter value. - */ - uint32_t timer1_ovf_int_raw:1; - /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the - * timer2 has reached its maximum counter value. - */ - uint32_t timer2_ovf_int_raw:1; - /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the - * timer3 has reached its maximum counter value. - */ - uint32_t timer3_ovf_int_raw:1; - /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch0_int_raw:1; - /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch1_int_raw:1; - /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch2_int_raw:1; - /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch3_int_raw:1; - /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch4_int_raw:1; - /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch5_int_raw:1; - /** duty_chng_end_ch6_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch6_int_raw:1; - /** duty_chng_end_ch7_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch7_int_raw:1; - /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. - */ - uint32_t ovf_cnt_ch0_int_raw:1; - /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. - */ - uint32_t ovf_cnt_ch1_int_raw:1; - /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. - */ - uint32_t ovf_cnt_ch2_int_raw:1; - /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. - */ - uint32_t ovf_cnt_ch3_int_raw:1; - /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. - */ - uint32_t ovf_cnt_ch4_int_raw:1; - /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. - */ - uint32_t ovf_cnt_ch5_int_raw:1; - /** ovf_cnt_ch6_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. - */ - uint32_t ovf_cnt_ch6_int_raw:1; - /** ovf_cnt_ch7_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. - */ - uint32_t ovf_cnt_ch7_int_raw:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_int_raw_reg_t; - -/** Type of int_st register - * Interrupt masked status register - */ -typedef union { - struct { - /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only - * when LEDC_TIMER0_OVF_INT_ENA is set to 1. - */ - uint32_t timer0_ovf_int_st:1; - /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only - * when LEDC_TIMER1_OVF_INT_ENA is set to 1. - */ - uint32_t timer1_ovf_int_st:1; - /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only - * when LEDC_TIMER2_OVF_INT_ENA is set to 1. - */ - uint32_t timer2_ovf_int_st:1; - /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only - * when LEDC_TIMER3_OVF_INT_ENA is set to 1. - */ - uint32_t timer3_ovf_int_st:1; - /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch0_int_st:1; - /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch1_int_st:1; - /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch2_int_st:1; - /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch3_int_st:1; - /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch4_int_st:1; - /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch5_int_st:1; - /** duty_chng_end_ch6_int_st : RO; bitpos: [10]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch6_int_st:1; - /** duty_chng_end_ch7_int_st : RO; bitpos: [11]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch7_int_st:1; - /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only - * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch0_int_st:1; - /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only - * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch1_int_st:1; - /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only - * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch2_int_st:1; - /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only - * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch3_int_st:1; - /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only - * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch4_int_st:1; - /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only - * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch5_int_st:1; - /** ovf_cnt_ch6_int_st : RO; bitpos: [18]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only - * when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch6_int_st:1; - /** ovf_cnt_ch7_int_st : RO; bitpos: [19]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only - * when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch7_int_st:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_int_st_reg_t; - -/** Type of int_ena register - * Interrupt enable register - */ -typedef union { - struct { - /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. - */ - uint32_t timer0_ovf_int_ena:1; - /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. - */ - uint32_t timer1_ovf_int_ena:1; - /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. - */ - uint32_t timer2_ovf_int_ena:1; - /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. - */ - uint32_t timer3_ovf_int_ena:1; - /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. - */ - uint32_t duty_chng_end_ch0_int_ena:1; - /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. - */ - uint32_t duty_chng_end_ch1_int_ena:1; - /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. - */ - uint32_t duty_chng_end_ch2_int_ena:1; - /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. - */ - uint32_t duty_chng_end_ch3_int_ena:1; - /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. - */ - uint32_t duty_chng_end_ch4_int_ena:1; - /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. - */ - uint32_t duty_chng_end_ch5_int_ena:1; - /** duty_chng_end_ch6_int_ena : R/W; bitpos: [10]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. - */ - uint32_t duty_chng_end_ch6_int_ena:1; - /** duty_chng_end_ch7_int_ena : R/W; bitpos: [11]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. - */ - uint32_t duty_chng_end_ch7_int_ena:1; - /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. - */ - uint32_t ovf_cnt_ch0_int_ena:1; - /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. - */ - uint32_t ovf_cnt_ch1_int_ena:1; - /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. - */ - uint32_t ovf_cnt_ch2_int_ena:1; - /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. - */ - uint32_t ovf_cnt_ch3_int_ena:1; - /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. - */ - uint32_t ovf_cnt_ch4_int_ena:1; - /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. - */ - uint32_t ovf_cnt_ch5_int_ena:1; - /** ovf_cnt_ch6_int_ena : R/W; bitpos: [18]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. - */ - uint32_t ovf_cnt_ch6_int_ena:1; - /** ovf_cnt_ch7_int_ena : R/W; bitpos: [19]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. - */ - uint32_t ovf_cnt_ch7_int_ena:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_int_ena_reg_t; - -/** Type of int_clr register - * Interrupt clear register - */ -typedef union { - struct { - /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. - */ - uint32_t timer0_ovf_int_clr:1; - /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. - */ - uint32_t timer1_ovf_int_clr:1; - /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. - */ - uint32_t timer2_ovf_int_clr:1; - /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. - */ - uint32_t timer3_ovf_int_clr:1; - /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. - */ - uint32_t duty_chng_end_ch0_int_clr:1; - /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. - */ - uint32_t duty_chng_end_ch1_int_clr:1; - /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. - */ - uint32_t duty_chng_end_ch2_int_clr:1; - /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. - */ - uint32_t duty_chng_end_ch3_int_clr:1; - /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. - */ - uint32_t duty_chng_end_ch4_int_clr:1; - /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. - */ - uint32_t duty_chng_end_ch5_int_clr:1; - /** duty_chng_end_ch6_int_clr : WT; bitpos: [10]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. - */ - uint32_t duty_chng_end_ch6_int_clr:1; - /** duty_chng_end_ch7_int_clr : WT; bitpos: [11]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. - */ - uint32_t duty_chng_end_ch7_int_clr:1; - /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. - */ - uint32_t ovf_cnt_ch0_int_clr:1; - /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. - */ - uint32_t ovf_cnt_ch1_int_clr:1; - /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. - */ - uint32_t ovf_cnt_ch2_int_clr:1; - /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. - */ - uint32_t ovf_cnt_ch3_int_clr:1; - /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. - */ - uint32_t ovf_cnt_ch4_int_clr:1; - /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. - */ - uint32_t ovf_cnt_ch5_int_clr:1; - /** ovf_cnt_ch6_int_clr : WT; bitpos: [18]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. - */ - uint32_t ovf_cnt_ch6_int_clr:1; - /** ovf_cnt_ch7_int_clr : WT; bitpos: [19]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. - */ - uint32_t ovf_cnt_ch7_int_clr:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_int_clr_reg_t; - - -/** Group: Version Register */ -/** Type of date register - * Version control register - */ -typedef union { - struct { - /** ledc_date : R/W; bitpos: [27:0]; default: 37765152; - * Configures the version. - */ - uint32_t ledc_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} ledc_date_reg_t; - - -typedef struct { - volatile ledc_chn_conf0_reg_t ch0_conf0; - volatile ledc_chn_hpoint_reg_t ch0_hpoint; - volatile ledc_chn_duty_reg_t ch0_duty; - volatile ledc_chn_conf1_reg_t ch0_conf1; - volatile ledc_chn_duty_r_reg_t ch0_duty_r; - volatile ledc_chn_conf0_reg_t ch1_conf0; - volatile ledc_chn_hpoint_reg_t ch1_hpoint; - volatile ledc_chn_duty_reg_t ch1_duty; - volatile ledc_chn_conf1_reg_t ch1_conf1; - volatile ledc_chn_duty_r_reg_t ch1_duty_r; - volatile ledc_chn_conf0_reg_t ch2_conf0; - volatile ledc_chn_hpoint_reg_t ch2_hpoint; - volatile ledc_chn_duty_reg_t ch2_duty; - volatile ledc_chn_conf1_reg_t ch2_conf1; - volatile ledc_chn_duty_r_reg_t ch2_duty_r; - volatile ledc_chn_conf0_reg_t ch3_conf0; - volatile ledc_chn_hpoint_reg_t ch3_hpoint; - volatile ledc_chn_duty_reg_t ch3_duty; - volatile ledc_chn_conf1_reg_t ch3_conf1; - volatile ledc_chn_duty_r_reg_t ch3_duty_r; - volatile ledc_chn_conf0_reg_t ch4_conf0; - volatile ledc_chn_hpoint_reg_t ch4_hpoint; - volatile ledc_chn_duty_reg_t ch4_duty; - volatile ledc_chn_conf1_reg_t ch4_conf1; - volatile ledc_chn_duty_r_reg_t ch4_duty_r; - volatile ledc_chn_conf0_reg_t ch5_conf0; - volatile ledc_chn_hpoint_reg_t ch5_hpoint; - volatile ledc_chn_duty_reg_t ch5_duty; - volatile ledc_chn_conf1_reg_t ch5_conf1; - volatile ledc_chn_duty_r_reg_t ch5_duty_r; - volatile ledc_chn_conf0_reg_t ch6_conf0; - volatile ledc_chn_hpoint_reg_t ch6_hpoint; - volatile ledc_chn_duty_reg_t ch6_duty; - volatile ledc_chn_conf1_reg_t ch6_conf1; - volatile ledc_chn_duty_r_reg_t ch6_duty_r; - volatile ledc_chn_conf0_reg_t ch7_conf0; - volatile ledc_chn_hpoint_reg_t ch7_hpoint; - volatile ledc_chn_duty_reg_t ch7_duty; - volatile ledc_chn_conf1_reg_t ch7_conf1; - volatile ledc_chn_duty_r_reg_t ch7_duty_r; - volatile ledc_timern_conf_reg_t timer0_conf; - volatile ledc_timern_value_reg_t timer0_value; - volatile ledc_timern_conf_reg_t timer1_conf; - volatile ledc_timern_value_reg_t timer1_value; - volatile ledc_timern_conf_reg_t timer2_conf; - volatile ledc_timern_value_reg_t timer2_value; - volatile ledc_timern_conf_reg_t timer3_conf; - volatile ledc_timern_value_reg_t timer3_value; - volatile ledc_int_raw_reg_t int_raw; - volatile ledc_int_st_reg_t int_st; - volatile ledc_int_ena_reg_t int_ena; - volatile ledc_int_clr_reg_t int_clr; - uint32_t reserved_0d0[12]; - volatile ledc_chn_gamma_conf_reg_t chn_gamma_conf[8]; - volatile ledc_evt_task_en0_reg_t evt_task_en0; - volatile ledc_evt_task_en1_reg_t evt_task_en1; - volatile ledc_evt_task_en2_reg_t evt_task_en2; - uint32_t reserved_12c[5]; - volatile ledc_timern_cmp_reg_t timern_cmp[4]; - volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4]; - uint32_t reserved_160[4]; - volatile ledc_conf_reg_t conf; - volatile ledc_date_reg_t date; -} ledc_dev_t; - -extern ledc_dev_t LEDC; - -#ifndef __cplusplus -_Static_assert(sizeof(ledc_dev_t) == 0x178, "Invalid size of ledc_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h index 05d7e02bbc..6599e1dab0 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h @@ -16,16 +16,20 @@ extern "C" { */ #define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) /** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 0 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 0 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH0 0x00000003U #define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) #define LEDC_TIMER_SEL_CH0_V 0x00000003U #define LEDC_TIMER_SEL_CH0_S 0 /** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 0.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 0. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH0 (BIT(2)) #define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) @@ -33,7 +37,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH0_S 2 /** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 0 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH0 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH0 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH0 (BIT(3)) #define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) @@ -43,7 +49,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0, * LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0, * LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel - * 0, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 0, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH0 (BIT(4)) #define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) @@ -58,15 +66,18 @@ extern "C" { #define LEDC_OVF_NUM_CH0_V 0x000003FFU #define LEDC_OVF_NUM_CH0_S 5 /** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 0.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 0. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH0 (BIT(15)) #define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) #define LEDC_OVF_CNT_EN_CH0_V 0x00000001U #define LEDC_OVF_CNT_EN_CH0_S 15 /** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 0.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 0. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) @@ -103,8 +114,9 @@ extern "C" { */ #define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) /** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH0 (BIT(31)) #define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) @@ -128,16 +140,20 @@ extern "C" { */ #define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) /** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 1 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 1 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH1 0x00000003U #define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) #define LEDC_TIMER_SEL_CH1_V 0x00000003U #define LEDC_TIMER_SEL_CH1_S 0 /** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 1.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 1. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH1 (BIT(2)) #define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) @@ -145,7 +161,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH1_S 2 /** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 1 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH1 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH1 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH1 (BIT(3)) #define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) @@ -155,7 +173,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1, * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1, * LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel - * 1, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 1, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH1 (BIT(4)) #define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) @@ -170,15 +190,18 @@ extern "C" { #define LEDC_OVF_NUM_CH1_V 0x000003FFU #define LEDC_OVF_NUM_CH1_S 5 /** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 1.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 1. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH1 (BIT(15)) #define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) #define LEDC_OVF_CNT_EN_CH1_V 0x00000001U #define LEDC_OVF_CNT_EN_CH1_S 15 /** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 1.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 1. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) @@ -215,8 +238,9 @@ extern "C" { */ #define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) /** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH1 (BIT(31)) #define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) @@ -240,16 +264,20 @@ extern "C" { */ #define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) /** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 2 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 2 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH2 0x00000003U #define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) #define LEDC_TIMER_SEL_CH2_V 0x00000003U #define LEDC_TIMER_SEL_CH2_S 0 /** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 2.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 2. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH2 (BIT(2)) #define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) @@ -257,7 +285,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH2_S 2 /** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 2 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH2 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH2 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH2 (BIT(3)) #define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) @@ -267,7 +297,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2, * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2, * LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel - * 2, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 2, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH2 (BIT(4)) #define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) @@ -282,15 +314,18 @@ extern "C" { #define LEDC_OVF_NUM_CH2_V 0x000003FFU #define LEDC_OVF_NUM_CH2_S 5 /** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 2.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 2. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH2 (BIT(15)) #define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) #define LEDC_OVF_CNT_EN_CH2_V 0x00000001U #define LEDC_OVF_CNT_EN_CH2_S 15 /** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 2.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 2. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) @@ -327,8 +362,9 @@ extern "C" { */ #define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) /** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH2 (BIT(31)) #define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) @@ -352,16 +388,20 @@ extern "C" { */ #define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) /** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 3 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 3 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH3 0x00000003U #define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) #define LEDC_TIMER_SEL_CH3_V 0x00000003U #define LEDC_TIMER_SEL_CH3_S 0 /** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 3.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 3. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH3 (BIT(2)) #define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) @@ -369,7 +409,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH3_S 2 /** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 3 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH3 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH3 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH3 (BIT(3)) #define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) @@ -379,7 +421,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3, * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3, * LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel - * 3, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 3, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH3 (BIT(4)) #define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) @@ -394,15 +438,18 @@ extern "C" { #define LEDC_OVF_NUM_CH3_V 0x000003FFU #define LEDC_OVF_NUM_CH3_S 5 /** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 3.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 3. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH3 (BIT(15)) #define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) #define LEDC_OVF_CNT_EN_CH3_V 0x00000001U #define LEDC_OVF_CNT_EN_CH3_S 15 /** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 3.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 3. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) @@ -439,8 +486,9 @@ extern "C" { */ #define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) /** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH3 (BIT(31)) #define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) @@ -464,16 +512,20 @@ extern "C" { */ #define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) /** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 4 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 4 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH4 0x00000003U #define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) #define LEDC_TIMER_SEL_CH4_V 0x00000003U #define LEDC_TIMER_SEL_CH4_S 0 /** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 4.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 4. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH4 (BIT(2)) #define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) @@ -481,7 +533,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH4_S 2 /** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 4 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH4 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH4 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH4 (BIT(3)) #define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) @@ -491,7 +545,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4, * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4, * LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel - * 4, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 4, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH4 (BIT(4)) #define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) @@ -506,15 +562,18 @@ extern "C" { #define LEDC_OVF_NUM_CH4_V 0x000003FFU #define LEDC_OVF_NUM_CH4_S 5 /** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 4.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 4. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH4 (BIT(15)) #define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) #define LEDC_OVF_CNT_EN_CH4_V 0x00000001U #define LEDC_OVF_CNT_EN_CH4_S 15 /** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 4.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 4. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) @@ -551,8 +610,9 @@ extern "C" { */ #define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) /** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH4 (BIT(31)) #define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) @@ -576,16 +636,20 @@ extern "C" { */ #define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) /** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 5 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 5 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH5 0x00000003U #define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) #define LEDC_TIMER_SEL_CH5_V 0x00000003U #define LEDC_TIMER_SEL_CH5_S 0 /** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 5.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 5. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH5 (BIT(2)) #define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) @@ -593,7 +657,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH5_S 2 /** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 5 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH5 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH5 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH5 (BIT(3)) #define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) @@ -603,7 +669,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5, * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5, * LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel - * 5, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 5, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH5 (BIT(4)) #define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) @@ -618,15 +686,18 @@ extern "C" { #define LEDC_OVF_NUM_CH5_V 0x000003FFU #define LEDC_OVF_NUM_CH5_S 5 /** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 5.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 5. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH5 (BIT(15)) #define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) #define LEDC_OVF_CNT_EN_CH5_V 0x00000001U #define LEDC_OVF_CNT_EN_CH5_S 15 /** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 5.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 5. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) @@ -663,8 +734,9 @@ extern "C" { */ #define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) /** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH5 (BIT(31)) #define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) @@ -688,16 +760,20 @@ extern "C" { */ #define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78) /** LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 6 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 6 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH6 0x00000003U #define LEDC_TIMER_SEL_CH6_M (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S) #define LEDC_TIMER_SEL_CH6_V 0x00000003U #define LEDC_TIMER_SEL_CH6_S 0 /** LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 6.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 6. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH6 (BIT(2)) #define LEDC_SIG_OUT_EN_CH6_M (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S) @@ -705,7 +781,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH6_S 2 /** LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 6 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH6 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH6 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH6 (BIT(3)) #define LEDC_IDLE_LV_CH6_M (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S) @@ -715,7 +793,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH6, LEDC_DUTY_START_CH6, * LEDC_SIG_OUT_EN_CH6, LEDC_TIMER_SEL_CH6, LEDC_DUTY_NUM_CH6, LEDC_DUTY_CYCLE_CH6, * LEDC_DUTY_SCALE_CH6, LEDC_DUTY_INC_CH6, and LEDC_OVF_CNT_EN_CH6 fields for channel - * 6, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 6, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH6 (BIT(4)) #define LEDC_PARA_UP_CH6_M (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S) @@ -730,15 +810,18 @@ extern "C" { #define LEDC_OVF_NUM_CH6_V 0x000003FFU #define LEDC_OVF_NUM_CH6_S 5 /** LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 6.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 6. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH6 (BIT(15)) #define LEDC_OVF_CNT_EN_CH6_M (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S) #define LEDC_OVF_CNT_EN_CH6_V 0x00000001U #define LEDC_OVF_CNT_EN_CH6_S 15 /** LEDC_OVF_CNT_RESET_CH6 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 6.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 6. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH6 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH6_M (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S) @@ -775,8 +858,9 @@ extern "C" { */ #define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84) /** LEDC_DUTY_START_CH6 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH6 (BIT(31)) #define LEDC_DUTY_START_CH6_M (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S) @@ -800,16 +884,20 @@ extern "C" { */ #define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c) /** LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 7 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 7 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH7 0x00000003U #define LEDC_TIMER_SEL_CH7_M (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S) #define LEDC_TIMER_SEL_CH7_V 0x00000003U #define LEDC_TIMER_SEL_CH7_S 0 /** LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 7.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 7. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH7 (BIT(2)) #define LEDC_SIG_OUT_EN_CH7_M (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S) @@ -817,7 +905,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH7_S 2 /** LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 7 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH7 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH7 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH7 (BIT(3)) #define LEDC_IDLE_LV_CH7_M (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S) @@ -827,7 +917,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH7, LEDC_DUTY_START_CH7, * LEDC_SIG_OUT_EN_CH7, LEDC_TIMER_SEL_CH7, LEDC_DUTY_NUM_CH7, LEDC_DUTY_CYCLE_CH7, * LEDC_DUTY_SCALE_CH7, LEDC_DUTY_INC_CH7, and LEDC_OVF_CNT_EN_CH7 fields for channel - * 7, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 7, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH7 (BIT(4)) #define LEDC_PARA_UP_CH7_M (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S) @@ -842,15 +934,18 @@ extern "C" { #define LEDC_OVF_NUM_CH7_V 0x000003FFU #define LEDC_OVF_NUM_CH7_S 5 /** LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 7.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 7. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH7 (BIT(15)) #define LEDC_OVF_CNT_EN_CH7_M (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S) #define LEDC_OVF_CNT_EN_CH7_V 0x00000001U #define LEDC_OVF_CNT_EN_CH7_S 15 /** LEDC_OVF_CNT_RESET_CH7 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 7.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 7. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH7 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH7_M (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S) @@ -887,8 +982,9 @@ extern "C" { */ #define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98) /** LEDC_DUTY_START_CH7 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH7 (BIT(31)) #define LEDC_DUTY_START_CH7_M (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S) @@ -927,30 +1023,27 @@ extern "C" { #define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU #define LEDC_CLK_DIV_TIMER0_S 5 /** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 0.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer 0. + * 0: Normal + * 1: Pause */ #define LEDC_TIMER0_PAUSE (BIT(23)) #define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) #define LEDC_TIMER0_PAUSE_V 0x00000001U #define LEDC_TIMER0_PAUSE_S 23 /** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 0. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer 0. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ #define LEDC_TIMER0_RST (BIT(24)) #define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) #define LEDC_TIMER0_RST_V 0x00000001U #define LEDC_TIMER0_RST_S 24 -/** LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer 0 selected. Unused. - */ -#define LEDC_TICK_SEL_TIMER0 (BIT(25)) -#define LEDC_TICK_SEL_TIMER0_M (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S) -#define LEDC_TICK_SEL_TIMER0_V 0x00000001U -#define LEDC_TICK_SEL_TIMER0_S 25 /** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER0 and - * LEDC_TIMER0_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMER0 and LEDC_TIMER0_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_TIMER0_PARA_UP (BIT(26)) #define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) @@ -989,30 +1082,27 @@ extern "C" { #define LEDC_CLK_DIV_TIMER1_V 0x0003FFFFU #define LEDC_CLK_DIV_TIMER1_S 5 /** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 1.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer 1. + * 0: Normal + * 1: Pause */ #define LEDC_TIMER1_PAUSE (BIT(23)) #define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) #define LEDC_TIMER1_PAUSE_V 0x00000001U #define LEDC_TIMER1_PAUSE_S 23 /** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 1. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer 1. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ #define LEDC_TIMER1_RST (BIT(24)) #define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) #define LEDC_TIMER1_RST_V 0x00000001U #define LEDC_TIMER1_RST_S 24 -/** LEDC_TICK_SEL_TIMER1 : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer 1 selected. Unused. - */ -#define LEDC_TICK_SEL_TIMER1 (BIT(25)) -#define LEDC_TICK_SEL_TIMER1_M (LEDC_TICK_SEL_TIMER1_V << LEDC_TICK_SEL_TIMER1_S) -#define LEDC_TICK_SEL_TIMER1_V 0x00000001U -#define LEDC_TICK_SEL_TIMER1_S 25 /** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and - * LEDC_TIMER1_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and LEDC_TIMER1_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_TIMER1_PARA_UP (BIT(26)) #define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) @@ -1051,30 +1141,27 @@ extern "C" { #define LEDC_CLK_DIV_TIMER2_V 0x0003FFFFU #define LEDC_CLK_DIV_TIMER2_S 5 /** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 2.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer 2. + * 0: Normal + * 1: Pause */ #define LEDC_TIMER2_PAUSE (BIT(23)) #define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) #define LEDC_TIMER2_PAUSE_V 0x00000001U #define LEDC_TIMER2_PAUSE_S 23 /** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 2. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer 2. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ #define LEDC_TIMER2_RST (BIT(24)) #define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) #define LEDC_TIMER2_RST_V 0x00000001U #define LEDC_TIMER2_RST_S 24 -/** LEDC_TICK_SEL_TIMER2 : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer 2 selected. Unused. - */ -#define LEDC_TICK_SEL_TIMER2 (BIT(25)) -#define LEDC_TICK_SEL_TIMER2_M (LEDC_TICK_SEL_TIMER2_V << LEDC_TICK_SEL_TIMER2_S) -#define LEDC_TICK_SEL_TIMER2_V 0x00000001U -#define LEDC_TICK_SEL_TIMER2_S 25 /** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and - * LEDC_TIMER2_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and LEDC_TIMER2_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_TIMER2_PARA_UP (BIT(26)) #define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) @@ -1113,30 +1200,27 @@ extern "C" { #define LEDC_CLK_DIV_TIMER3_V 0x0003FFFFU #define LEDC_CLK_DIV_TIMER3_S 5 /** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 3.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer 3. + * 0: Normal + * 1: Pause */ #define LEDC_TIMER3_PAUSE (BIT(23)) #define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) #define LEDC_TIMER3_PAUSE_V 0x00000001U #define LEDC_TIMER3_PAUSE_S 23 /** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 3. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer 3. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ #define LEDC_TIMER3_RST (BIT(24)) #define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) #define LEDC_TIMER3_RST_V 0x00000001U #define LEDC_TIMER3_RST_S 24 -/** LEDC_TICK_SEL_TIMER3 : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer 3 selected. Unused. - */ -#define LEDC_TICK_SEL_TIMER3 (BIT(25)) -#define LEDC_TICK_SEL_TIMER3_M (LEDC_TICK_SEL_TIMER3_V << LEDC_TICK_SEL_TIMER3_S) -#define LEDC_TICK_SEL_TIMER3_V 0x00000001U -#define LEDC_TICK_SEL_TIMER3_S 25 /** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and - * LEDC_TIMER3_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and LEDC_TIMER3_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_TIMER3_PARA_UP (BIT(26)) #define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) @@ -1787,16 +1871,18 @@ extern "C" { #define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch0.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch0. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH0_GAMMA_PAUSE (BIT(5)) #define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) #define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH0_GAMMA_PAUSE_S 5 /** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch0.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch0. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH0_GAMMA_RESUME (BIT(6)) #define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) @@ -1815,16 +1901,18 @@ extern "C" { #define LEDC_CH1_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH1_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch1.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch1. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH1_GAMMA_PAUSE (BIT(5)) #define LEDC_CH1_GAMMA_PAUSE_M (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S) #define LEDC_CH1_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH1_GAMMA_PAUSE_S 5 /** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch1.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch1. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH1_GAMMA_RESUME (BIT(6)) #define LEDC_CH1_GAMMA_RESUME_M (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S) @@ -1843,16 +1931,18 @@ extern "C" { #define LEDC_CH2_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH2_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch2.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch2. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH2_GAMMA_PAUSE (BIT(5)) #define LEDC_CH2_GAMMA_PAUSE_M (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S) #define LEDC_CH2_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH2_GAMMA_PAUSE_S 5 /** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch2.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch2. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH2_GAMMA_RESUME (BIT(6)) #define LEDC_CH2_GAMMA_RESUME_M (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S) @@ -1871,16 +1961,18 @@ extern "C" { #define LEDC_CH3_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH3_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch3.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch3. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH3_GAMMA_PAUSE (BIT(5)) #define LEDC_CH3_GAMMA_PAUSE_M (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S) #define LEDC_CH3_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH3_GAMMA_PAUSE_S 5 /** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch3.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch3. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH3_GAMMA_RESUME (BIT(6)) #define LEDC_CH3_GAMMA_RESUME_M (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S) @@ -1899,16 +1991,18 @@ extern "C" { #define LEDC_CH4_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH4_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch4.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch4. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH4_GAMMA_PAUSE (BIT(5)) #define LEDC_CH4_GAMMA_PAUSE_M (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S) #define LEDC_CH4_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH4_GAMMA_PAUSE_S 5 /** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch4.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch4. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH4_GAMMA_RESUME (BIT(6)) #define LEDC_CH4_GAMMA_RESUME_M (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S) @@ -1927,16 +2021,18 @@ extern "C" { #define LEDC_CH5_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH5_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch5.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch5. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH5_GAMMA_PAUSE (BIT(5)) #define LEDC_CH5_GAMMA_PAUSE_M (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S) #define LEDC_CH5_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH5_GAMMA_PAUSE_S 5 /** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch5.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch5. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH5_GAMMA_RESUME (BIT(6)) #define LEDC_CH5_GAMMA_RESUME_M (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S) @@ -1955,16 +2051,18 @@ extern "C" { #define LEDC_CH6_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH6_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH6_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch6.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch6. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH6_GAMMA_PAUSE (BIT(5)) #define LEDC_CH6_GAMMA_PAUSE_M (LEDC_CH6_GAMMA_PAUSE_V << LEDC_CH6_GAMMA_PAUSE_S) #define LEDC_CH6_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH6_GAMMA_PAUSE_S 5 /** LEDC_CH6_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch6.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch6. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH6_GAMMA_RESUME (BIT(6)) #define LEDC_CH6_GAMMA_RESUME_M (LEDC_CH6_GAMMA_RESUME_V << LEDC_CH6_GAMMA_RESUME_S) @@ -1983,16 +2081,18 @@ extern "C" { #define LEDC_CH7_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH7_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH7_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch7.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch7. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH7_GAMMA_PAUSE (BIT(5)) #define LEDC_CH7_GAMMA_PAUSE_M (LEDC_CH7_GAMMA_PAUSE_V << LEDC_CH7_GAMMA_PAUSE_S) #define LEDC_CH7_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH7_GAMMA_PAUSE_S 5 /** LEDC_CH7_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch7.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch7. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH7_GAMMA_RESUME (BIT(6)) #define LEDC_CH7_GAMMA_RESUME_M (LEDC_CH7_GAMMA_RESUME_V << LEDC_CH7_GAMMA_RESUME_S) @@ -2004,256 +2104,288 @@ extern "C" { */ #define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x120) /** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch0_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH0_EN (BIT(0)) #define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S 0 /** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch1_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH1_EN (BIT(1)) #define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S 1 /** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch2_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH2_EN (BIT(2)) #define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S 2 /** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch3_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH3_EN (BIT(3)) #define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S 3 /** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch4_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH4_EN (BIT(4)) #define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S 4 /** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch5_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH5_EN (BIT(5)) #define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S 5 /** LEDC_EVT_DUTY_CHNG_END_CH6_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch6_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH6_EN (BIT(6)) #define LEDC_EVT_DUTY_CHNG_END_CH6_EN_M (LEDC_EVT_DUTY_CHNG_END_CH6_EN_V << LEDC_EVT_DUTY_CHNG_END_CH6_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH6_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH6_EN_S 6 /** LEDC_EVT_DUTY_CHNG_END_CH7_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch7_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH7_EN (BIT(7)) #define LEDC_EVT_DUTY_CHNG_END_CH7_EN_M (LEDC_EVT_DUTY_CHNG_END_CH7_EN_V << LEDC_EVT_DUTY_CHNG_END_CH7_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH7_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH7_EN_S 7 /** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH0_EN (BIT(8)) #define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S 8 /** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH1_EN (BIT(9)) #define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S 9 /** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH2_EN (BIT(10)) #define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S 10 /** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH3_EN (BIT(11)) #define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S 11 /** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH4_EN (BIT(12)) #define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S 12 /** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH5_EN (BIT(13)) #define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S 13 /** LEDC_EVT_OVF_CNT_PLS_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH6_EN (BIT(14)) #define LEDC_EVT_OVF_CNT_PLS_CH6_EN_M (LEDC_EVT_OVF_CNT_PLS_CH6_EN_V << LEDC_EVT_OVF_CNT_PLS_CH6_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH6_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH6_EN_S 14 /** LEDC_EVT_OVF_CNT_PLS_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH7_EN (BIT(15)) #define LEDC_EVT_OVF_CNT_PLS_CH7_EN_M (LEDC_EVT_OVF_CNT_PLS_CH7_EN_V << LEDC_EVT_OVF_CNT_PLS_CH7_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH7_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH7_EN_S 15 /** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_timer0_ovf event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_TIME_OVF_TIMER0_EN (BIT(16)) #define LEDC_EVT_TIME_OVF_TIMER0_EN_M (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S) #define LEDC_EVT_TIME_OVF_TIMER0_EN_V 0x00000001U #define LEDC_EVT_TIME_OVF_TIMER0_EN_S 16 /** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_timer1_ovf event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_TIME_OVF_TIMER1_EN (BIT(17)) #define LEDC_EVT_TIME_OVF_TIMER1_EN_M (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S) #define LEDC_EVT_TIME_OVF_TIMER1_EN_V 0x00000001U #define LEDC_EVT_TIME_OVF_TIMER1_EN_S 17 /** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_timer2_ovf event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_TIME_OVF_TIMER2_EN (BIT(18)) #define LEDC_EVT_TIME_OVF_TIMER2_EN_M (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S) #define LEDC_EVT_TIME_OVF_TIMER2_EN_V 0x00000001U #define LEDC_EVT_TIME_OVF_TIMER2_EN_S 18 /** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_timer3_ovf event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_TIME_OVF_TIMER3_EN (BIT(19)) #define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S) #define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U #define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19 -/** LEDC_EVT_TIMER0_CMP_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: - * Enable +/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the ledc_timer0_cmp event. + * 0: Disable + * 1: Enable */ -#define LEDC_EVT_TIMER0_CMP_EN (BIT(20)) -#define LEDC_EVT_TIMER0_CMP_EN_M (LEDC_EVT_TIMER0_CMP_EN_V << LEDC_EVT_TIMER0_CMP_EN_S) -#define LEDC_EVT_TIMER0_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIMER0_CMP_EN_S 20 -/** LEDC_EVT_TIMER1_CMP_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: - * Enable +#define LEDC_EVT_TIME0_CMP_EN (BIT(20)) +#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S) +#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME0_CMP_EN_S 20 +/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the ledc_timer1_cmp event. + * 0: Disable + * 1: Enable */ -#define LEDC_EVT_TIMER1_CMP_EN (BIT(21)) -#define LEDC_EVT_TIMER1_CMP_EN_M (LEDC_EVT_TIMER1_CMP_EN_V << LEDC_EVT_TIMER1_CMP_EN_S) -#define LEDC_EVT_TIMER1_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIMER1_CMP_EN_S 21 -/** LEDC_EVT_TIMER2_CMP_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: - * Enable +#define LEDC_EVT_TIME1_CMP_EN (BIT(21)) +#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S) +#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME1_CMP_EN_S 21 +/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the ledc_timer2_cmp event. + * 0: Disable + * 1: Enable */ -#define LEDC_EVT_TIMER2_CMP_EN (BIT(22)) -#define LEDC_EVT_TIMER2_CMP_EN_M (LEDC_EVT_TIMER2_CMP_EN_V << LEDC_EVT_TIMER2_CMP_EN_S) -#define LEDC_EVT_TIMER2_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIMER2_CMP_EN_S 22 -/** LEDC_EVT_TIMER3_CMP_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: - * Enable +#define LEDC_EVT_TIME2_CMP_EN (BIT(22)) +#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S) +#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME2_CMP_EN_S 22 +/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the ledc_timer3_cmp event. + * 0: Disable + * 1: Enable */ -#define LEDC_EVT_TIMER3_CMP_EN (BIT(23)) -#define LEDC_EVT_TIMER3_CMP_EN_M (LEDC_EVT_TIMER3_CMP_EN_V << LEDC_EVT_TIMER3_CMP_EN_S) -#define LEDC_EVT_TIMER3_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIMER3_CMP_EN_S 23 +#define LEDC_EVT_TIME3_CMP_EN (BIT(23)) +#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S) +#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME3_CMP_EN_S 23 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch0_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN (BIT(24)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S 24 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch1_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN (BIT(25)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S 25 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch2_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN (BIT(26)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S 26 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch3_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN (BIT(27)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S 27 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch4_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN (BIT(28)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S 28 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch5_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN (BIT(29)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S 29 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch6_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN (BIT(30)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S 30 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch7_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN (BIT(31)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S) @@ -2265,248 +2397,288 @@ extern "C" { */ #define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x124) /** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer0_res_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER0_RES_UPDATE_EN (BIT(0)) #define LEDC_TASK_TIMER0_RES_UPDATE_EN_M (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S) #define LEDC_TASK_TIMER0_RES_UPDATE_EN_V 0x00000001U #define LEDC_TASK_TIMER0_RES_UPDATE_EN_S 0 /** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer1_res_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER1_RES_UPDATE_EN (BIT(1)) #define LEDC_TASK_TIMER1_RES_UPDATE_EN_M (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S) #define LEDC_TASK_TIMER1_RES_UPDATE_EN_V 0x00000001U #define LEDC_TASK_TIMER1_RES_UPDATE_EN_S 1 /** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer2_res_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER2_RES_UPDATE_EN (BIT(2)) #define LEDC_TASK_TIMER2_RES_UPDATE_EN_M (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S) #define LEDC_TASK_TIMER2_RES_UPDATE_EN_V 0x00000001U #define LEDC_TASK_TIMER2_RES_UPDATE_EN_S 2 /** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer3_res_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER3_RES_UPDATE_EN (BIT(3)) #define LEDC_TASK_TIMER3_RES_UPDATE_EN_M (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S) #define LEDC_TASK_TIMER3_RES_UPDATE_EN_V 0x00000001U #define LEDC_TASK_TIMER3_RES_UPDATE_EN_S 3 /** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer0_cap task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER0_CAP_EN (BIT(4)) #define LEDC_TASK_TIMER0_CAP_EN_M (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S) #define LEDC_TASK_TIMER0_CAP_EN_V 0x00000001U #define LEDC_TASK_TIMER0_CAP_EN_S 4 /** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer1_cap task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER1_CAP_EN (BIT(5)) #define LEDC_TASK_TIMER1_CAP_EN_M (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S) #define LEDC_TASK_TIMER1_CAP_EN_V 0x00000001U #define LEDC_TASK_TIMER1_CAP_EN_S 5 /** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer2_cap task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER2_CAP_EN (BIT(6)) #define LEDC_TASK_TIMER2_CAP_EN_M (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S) #define LEDC_TASK_TIMER2_CAP_EN_V 0x00000001U #define LEDC_TASK_TIMER2_CAP_EN_S 6 /** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer3_cap task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER3_CAP_EN (BIT(7)) #define LEDC_TASK_TIMER3_CAP_EN_M (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S) #define LEDC_TASK_TIMER3_CAP_EN_V 0x00000001U #define LEDC_TASK_TIMER3_CAP_EN_S 7 /** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH0_EN (BIT(8)) #define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S 8 /** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH1_EN (BIT(9)) #define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S 9 /** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH2_EN (BIT(10)) #define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S 10 /** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH3_EN (BIT(11)) #define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S 11 /** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH4_EN (BIT(12)) #define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S 12 /** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH5_EN (BIT(13)) #define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S 13 /** LEDC_TASK_SIG_OUT_DIS_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH6_EN (BIT(14)) #define LEDC_TASK_SIG_OUT_DIS_CH6_EN_M (LEDC_TASK_SIG_OUT_DIS_CH6_EN_V << LEDC_TASK_SIG_OUT_DIS_CH6_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH6_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH6_EN_S 14 /** LEDC_TASK_SIG_OUT_DIS_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH7_EN (BIT(15)) #define LEDC_TASK_SIG_OUT_DIS_CH7_EN_M (LEDC_TASK_SIG_OUT_DIS_CH7_EN_V << LEDC_TASK_SIG_OUT_DIS_CH7_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH7_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH7_EN_S 15 /** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH0_EN (BIT(16)) #define LEDC_TASK_OVF_CNT_RST_CH0_EN_M (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH0_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH0_EN_S 16 /** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH1_EN (BIT(17)) #define LEDC_TASK_OVF_CNT_RST_CH1_EN_M (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH1_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH1_EN_S 17 /** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH2_EN (BIT(18)) #define LEDC_TASK_OVF_CNT_RST_CH2_EN_M (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH2_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH2_EN_S 18 /** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH3_EN (BIT(19)) #define LEDC_TASK_OVF_CNT_RST_CH3_EN_M (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH3_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH3_EN_S 19 /** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH4_EN (BIT(20)) #define LEDC_TASK_OVF_CNT_RST_CH4_EN_M (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH4_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH4_EN_S 20 /** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH5_EN (BIT(21)) #define LEDC_TASK_OVF_CNT_RST_CH5_EN_M (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH5_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH5_EN_S 21 /** LEDC_TASK_OVF_CNT_RST_CH6_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH6_EN (BIT(22)) #define LEDC_TASK_OVF_CNT_RST_CH6_EN_M (LEDC_TASK_OVF_CNT_RST_CH6_EN_V << LEDC_TASK_OVF_CNT_RST_CH6_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH6_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH6_EN_S 22 /** LEDC_TASK_OVF_CNT_RST_CH7_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH7_EN (BIT(23)) #define LEDC_TASK_OVF_CNT_RST_CH7_EN_M (LEDC_TASK_OVF_CNT_RST_CH7_EN_V << LEDC_TASK_OVF_CNT_RST_CH7_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH7_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH7_EN_S 23 /** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer0_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER0_RST_EN (BIT(24)) #define LEDC_TASK_TIMER0_RST_EN_M (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S) #define LEDC_TASK_TIMER0_RST_EN_V 0x00000001U #define LEDC_TASK_TIMER0_RST_EN_S 24 /** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer1_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER1_RST_EN (BIT(25)) #define LEDC_TASK_TIMER1_RST_EN_M (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S) #define LEDC_TASK_TIMER1_RST_EN_V 0x00000001U #define LEDC_TASK_TIMER1_RST_EN_S 25 /** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer2_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER2_RST_EN (BIT(26)) #define LEDC_TASK_TIMER2_RST_EN_M (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S) #define LEDC_TASK_TIMER2_RST_EN_V 0x00000001U #define LEDC_TASK_TIMER2_RST_EN_S 26 /** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer3_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER3_RST_EN (BIT(27)) #define LEDC_TASK_TIMER3_RST_EN_M (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S) #define LEDC_TASK_TIMER3_RST_EN_V 0x00000001U #define LEDC_TASK_TIMER3_RST_EN_S 27 /** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer0_pause_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER0_PAUSE_RESUME_EN (BIT(28)) #define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S) #define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V 0x00000001U #define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S 28 /** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer1_pause_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER1_PAUSE_RESUME_EN (BIT(29)) #define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S) #define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V 0x00000001U #define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S 29 /** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer2_pause_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER2_PAUSE_RESUME_EN (BIT(30)) #define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S) #define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V 0x00000001U #define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S 30 /** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer3_pause_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER3_PAUSE_RESUME_EN (BIT(31)) #define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S) @@ -2518,192 +2690,216 @@ extern "C" { */ #define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x128) /** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH0_EN (BIT(0)) #define LEDC_TASK_GAMMA_RESTART_CH0_EN_M (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH0_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH0_EN_S 0 /** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH1_EN (BIT(1)) #define LEDC_TASK_GAMMA_RESTART_CH1_EN_M (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH1_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH1_EN_S 1 /** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH2_EN (BIT(2)) #define LEDC_TASK_GAMMA_RESTART_CH2_EN_M (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH2_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH2_EN_S 2 /** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH3_EN (BIT(3)) #define LEDC_TASK_GAMMA_RESTART_CH3_EN_M (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH3_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH3_EN_S 3 /** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH4_EN (BIT(4)) #define LEDC_TASK_GAMMA_RESTART_CH4_EN_M (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH4_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH4_EN_S 4 /** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH5_EN (BIT(5)) #define LEDC_TASK_GAMMA_RESTART_CH5_EN_M (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH5_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH5_EN_S 5 /** LEDC_TASK_GAMMA_RESTART_CH6_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH6_EN (BIT(6)) #define LEDC_TASK_GAMMA_RESTART_CH6_EN_M (LEDC_TASK_GAMMA_RESTART_CH6_EN_V << LEDC_TASK_GAMMA_RESTART_CH6_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH6_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH6_EN_S 6 /** LEDC_TASK_GAMMA_RESTART_CH7_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH7_EN (BIT(7)) #define LEDC_TASK_GAMMA_RESTART_CH7_EN_M (LEDC_TASK_GAMMA_RESTART_CH7_EN_V << LEDC_TASK_GAMMA_RESTART_CH7_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH7_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH7_EN_S 7 /** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH0_EN (BIT(8)) #define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S 8 /** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH1_EN (BIT(9)) #define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S 9 /** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH2_EN (BIT(10)) #define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S 10 /** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH3_EN (BIT(11)) #define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S 11 /** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH4_EN (BIT(12)) #define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S 12 /** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH5_EN (BIT(13)) #define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S 13 /** LEDC_TASK_GAMMA_PAUSE_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH6_EN (BIT(14)) #define LEDC_TASK_GAMMA_PAUSE_CH6_EN_M (LEDC_TASK_GAMMA_PAUSE_CH6_EN_V << LEDC_TASK_GAMMA_PAUSE_CH6_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH6_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH6_EN_S 14 /** LEDC_TASK_GAMMA_PAUSE_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH7_EN (BIT(15)) #define LEDC_TASK_GAMMA_PAUSE_CH7_EN_M (LEDC_TASK_GAMMA_PAUSE_CH7_EN_V << LEDC_TASK_GAMMA_PAUSE_CH7_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH7_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH7_EN_S 15 /** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH0_EN (BIT(16)) #define LEDC_TASK_GAMMA_RESUME_CH0_EN_M (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH0_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH0_EN_S 16 /** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH1_EN (BIT(17)) #define LEDC_TASK_GAMMA_RESUME_CH1_EN_M (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH1_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH1_EN_S 17 /** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH2_EN (BIT(18)) #define LEDC_TASK_GAMMA_RESUME_CH2_EN_M (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH2_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH2_EN_S 18 /** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH3_EN (BIT(19)) #define LEDC_TASK_GAMMA_RESUME_CH3_EN_M (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH3_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH3_EN_S 19 /** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH4_EN (BIT(20)) #define LEDC_TASK_GAMMA_RESUME_CH4_EN_M (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH4_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH4_EN_S 20 /** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH5_EN (BIT(21)) #define LEDC_TASK_GAMMA_RESUME_CH5_EN_M (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH5_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH5_EN_S 21 /** LEDC_TASK_GAMMA_RESUME_CH6_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH6_EN (BIT(22)) #define LEDC_TASK_GAMMA_RESUME_CH6_EN_M (LEDC_TASK_GAMMA_RESUME_CH6_EN_V << LEDC_TASK_GAMMA_RESUME_CH6_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH6_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH6_EN_S 22 /** LEDC_TASK_GAMMA_RESUME_CH7_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH7_EN (BIT(23)) #define LEDC_TASK_GAMMA_RESUME_CH7_EN_M (LEDC_TASK_GAMMA_RESUME_CH7_EN_V << LEDC_TASK_GAMMA_RESUME_CH7_EN_S) @@ -2811,88 +3007,92 @@ extern "C" { */ #define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x170) /** LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0; - * Configures the clock source for the four timers.\\0: APB_CLK\\1: RC_FAST_CLK\\2: - * XTAL_CLK\\3: Invalid. No clock + * Configures the clock source for the four timers. + * 0: APB_CLK + * 1: RC_FAST_CLK + * 2: XTAL_CLK + * 3: Invalid. No clock */ #define LEDC_APB_CLK_SEL 0x00000003U #define LEDC_APB_CLK_SEL_M (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S) #define LEDC_APB_CLK_SEL_V 0x00000003U #define LEDC_APB_CLK_SEL_S 0 /** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the - * clock gate for LEDC ch0 gamma ram + * Configures whether or not to open LEDC ch0 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram + * 1: Force open the clock gate for LEDC ch0 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH0 (BIT(2)) #define LEDC_GAMMA_RAM_CLK_EN_CH0_M (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S) #define LEDC_GAMMA_RAM_CLK_EN_CH0_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH0_S 2 /** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0; - * Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the - * clock gate for LEDC ch1 gamma ram + * Configures whether or not to open LEDC ch1 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram + * 1: Force open the clock gate for LEDC ch1 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH1 (BIT(3)) #define LEDC_GAMMA_RAM_CLK_EN_CH1_M (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S) #define LEDC_GAMMA_RAM_CLK_EN_CH1_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH1_S 3 /** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the - * clock gate for LEDC ch2 gamma ram + * Configures whether or not to open LEDC ch2 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram + * 1: Force open the clock gate for LEDC ch2 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH2 (BIT(4)) #define LEDC_GAMMA_RAM_CLK_EN_CH2_M (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S) #define LEDC_GAMMA_RAM_CLK_EN_CH2_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH2_S 4 /** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the - * clock gate for LEDC ch3 gamma ram + * Configures whether or not to open LEDC ch3 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram + * 1: Force open the clock gate for LEDC ch3 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH3 (BIT(5)) #define LEDC_GAMMA_RAM_CLK_EN_CH3_M (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S) #define LEDC_GAMMA_RAM_CLK_EN_CH3_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH3_S 5 /** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the - * clock gate for LEDC ch4 gamma ram + * Configures whether or not to open LEDC ch4 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram + * 1: Force open the clock gate for LEDC ch4 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH4 (BIT(6)) #define LEDC_GAMMA_RAM_CLK_EN_CH4_M (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S) #define LEDC_GAMMA_RAM_CLK_EN_CH4_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH4_S 6 /** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0; - * Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the - * clock gate for LEDC ch5 gamma ram + * Configures whether or not to open LEDC ch5 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram + * 1: Force open the clock gate for LEDC ch5 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH5 (BIT(7)) #define LEDC_GAMMA_RAM_CLK_EN_CH5_M (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S) #define LEDC_GAMMA_RAM_CLK_EN_CH5_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH5_S 7 /** LEDC_GAMMA_RAM_CLK_EN_CH6 : R/W; bitpos: [8]; default: 0; - * Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch6 gamma ram\\1: Force open the - * clock gate for LEDC ch6 gamma ram + * Configures whether or not to open LEDC ch6 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram + * 1: Force open the clock gate for LEDC ch6 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH6 (BIT(8)) #define LEDC_GAMMA_RAM_CLK_EN_CH6_M (LEDC_GAMMA_RAM_CLK_EN_CH6_V << LEDC_GAMMA_RAM_CLK_EN_CH6_S) #define LEDC_GAMMA_RAM_CLK_EN_CH6_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH6_S 8 /** LEDC_GAMMA_RAM_CLK_EN_CH7 : R/W; bitpos: [9]; default: 0; - * Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch7 gamma ram\\1: Force open the - * clock gate for LEDC ch7 gamma ram + * Configures whether or not to open LEDC ch7 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram + * 1: Force open the clock gate for LEDC ch7 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH7 (BIT(9)) #define LEDC_GAMMA_RAM_CLK_EN_CH7_M (LEDC_GAMMA_RAM_CLK_EN_CH7_V << LEDC_GAMMA_RAM_CLK_EN_CH7_S) #define LEDC_GAMMA_RAM_CLK_EN_CH7_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH7_S 9 /** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to open register clock gate.\\0: Open the clock gate only - * when application writes registers\\1: Force open the clock gate for register + * Configures whether or not to open register clock gate. + * 0: Open the clock gate only when application writes registers + * 1: Force open the clock gate for register */ #define LEDC_CLK_EN (BIT(31)) #define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h index 23029726e8..668767aa68 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h @@ -10,32 +10,40 @@ extern "C" { #endif -/** Group: conf0 */ +/** Group: Configuration Register */ /** Type of chn_conf0 register * Configuration register 0 for channel n */ typedef union { struct { /** timer_sel : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel n selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel n selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ uint32_t timer_sel:2; /** sig_out_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel n.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel n. + * 0: Signal output disable + * 1: Signal output enable */ uint32_t sig_out_en:1; /** idle_lv : R/W; bitpos: [3]; default: 0; * Configures the output value when channel n is inactive. Valid only when - * LEDC_SIG_OUT_EN_CHn is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CHn is 0. + * 0: Output level is low + * 1: Output level is high */ uint32_t idle_lv:1; /** para_up : WT; bitpos: [4]; default: 0; * Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn, * LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel - * n, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * n, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ uint32_t para_up:1; /** ovf_num : R/W; bitpos: [14:5]; default: 0; @@ -44,12 +52,15 @@ typedef union { */ uint32_t ovf_num:10; /** ovf_cnt_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel n.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel n. + * 0: Disable + * 1: Enable */ uint32_t ovf_cnt_en:1; /** ovf_cnt_reset : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel n.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel n. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ uint32_t ovf_cnt_reset:1; uint32_t reserved_17:15; @@ -93,30 +104,30 @@ typedef union { struct { uint32_t reserved_0:31; /** duty_start : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ uint32_t duty_start:1; }; uint32_t val; } ledc_chn_conf1_reg_t; +/** Group: Status Register */ /** Type of chn_duty_r register * Current duty cycle register for channel n */ typedef union { struct { - /** duty_ch0_r : RO; bitpos: [24:0]; default: 0; + /** duty_r : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel n. */ - uint32_t duty:25; + uint32_t duty_r:25; uint32_t reserved_25:7; }; uint32_t val; } ledc_chn_duty_r_reg_t; - -/** Group: conf1 */ /** Type of timern_conf register * Timer n configuration register */ @@ -132,21 +143,22 @@ typedef union { */ uint32_t clk_div:18; /** pause : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer n.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer n. + * 0: Normal + * 1: Pause */ uint32_t pause:1; /** rst : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer n. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer n. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ uint32_t rst:1; - /** tick_sel : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer n selected. Unused. - */ - uint32_t tick_sel:1; + uint32_t reserved_25:1; /** para_up : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMERn and - * LEDC_TIMERn_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMERn and LEDC_TIMERn_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ uint32_t para_up:1; uint32_t reserved_27:5; @@ -168,6 +180,688 @@ typedef union { uint32_t val; } ledc_timern_value_reg_t; +/** Type of conf register + * LEDC global configuration register + */ +typedef union { + struct { + /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0; + * Configures the clock source for the four timers. + * 0: APB_CLK + * 1: RC_FAST_CLK + * 2: XTAL_CLK + * 3: Invalid. No clock + */ + uint32_t apb_clk_sel:2; + /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to open LEDC ch0 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram + * 1: Force open the clock gate for LEDC ch0 gamma ram + */ + uint32_t gamma_ram_clk_en_ch0:1; + /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; + * Configures whether or not to open LEDC ch1 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram + * 1: Force open the clock gate for LEDC ch1 gamma ram + */ + uint32_t gamma_ram_clk_en_ch1:1; + /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to open LEDC ch2 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram + * 1: Force open the clock gate for LEDC ch2 gamma ram + */ + uint32_t gamma_ram_clk_en_ch2:1; + /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to open LEDC ch3 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram + * 1: Force open the clock gate for LEDC ch3 gamma ram + */ + uint32_t gamma_ram_clk_en_ch3:1; + /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to open LEDC ch4 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram + * 1: Force open the clock gate for LEDC ch4 gamma ram + */ + uint32_t gamma_ram_clk_en_ch4:1; + /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; + * Configures whether or not to open LEDC ch5 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram + * 1: Force open the clock gate for LEDC ch5 gamma ram + */ + uint32_t gamma_ram_clk_en_ch5:1; + /** gamma_ram_clk_en_ch6 : R/W; bitpos: [8]; default: 0; + * Configures whether or not to open LEDC ch6 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram + * 1: Force open the clock gate for LEDC ch6 gamma ram + */ + uint32_t gamma_ram_clk_en_ch6:1; + /** gamma_ram_clk_en_ch7 : R/W; bitpos: [9]; default: 0; + * Configures whether or not to open LEDC ch7 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram + * 1: Force open the clock gate for LEDC ch7 gamma ram + */ + uint32_t gamma_ram_clk_en_ch7:1; + uint32_t reserved_10:21; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to open register clock gate. + * 0: Open the clock gate only when application writes registers + * 1: Force open the clock gate for register + */ + uint32_t clk_en:1; + }; + uint32_t val; +} ledc_conf_reg_t; + +/** Type of chn_gamma_conf register + * Ledc chn gamma config register. + */ +typedef union { + struct { + /** gamma_entry_num : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC chn. + */ + uint32_t gamma_entry_num:5; + /** gamma_pause : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC chn. + * 0: Invalid. No effect + * 1: Pause + */ + uint32_t gamma_pause:1; + /** gamma_resume : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC chn. + * 0: Invalid. No effect + * 1: Resume + */ + uint32_t gamma_resume:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ledc_chn_gamma_conf_reg_t; + +/** Type of evt_task_en0 register + * Ledc event task enable bit register0. + */ +typedef union { + struct { + /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch0_en:1; + /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch1_en:1; + /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch2_en:1; + /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch3_en:1; + /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch4_en:1; + /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch5_en:1; + /** evt_duty_chng_end_ch6_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable the ledc_ch6_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch6_en:1; + /** evt_duty_chng_end_ch7_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable the ledc_ch7_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch7_en:1; + /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch0_en:1; + /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch1_en:1; + /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch2_en:1; + /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch3_en:1; + /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch4_en:1; + /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch5_en:1; + /** evt_ovf_cnt_pls_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch6_en:1; + /** evt_ovf_cnt_pls_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch7_en:1; + /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the ledc_timer0_ovf event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time_ovf_timer0_en:1; + /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable the ledc_timer1_ovf event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time_ovf_timer1_en:1; + /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable the ledc_timer2_ovf event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time_ovf_timer2_en:1; + /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable the ledc_timer3_ovf event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time_ovf_timer3_en:1; + /** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the ledc_timer0_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time0_cmp_en:1; + /** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the ledc_timer1_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time1_cmp_en:1; + /** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the ledc_timer2_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time2_cmp_en:1; + /** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the ledc_timer3_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time3_cmp_en:1; + /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch0_en:1; + /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch1_en:1; + /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch2_en:1; + /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch3_en:1; + /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch4_en:1; + /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch5_en:1; + /** task_duty_scale_update_ch6_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable the ledc_ch6_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch6_en:1; + /** task_duty_scale_update_ch7_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable the ledc_ch7_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch7_en:1; + }; + uint32_t val; +} ledc_evt_task_en0_reg_t; + +/** Type of evt_task_en1 register + * Ledc event task enable bit register1. + */ +typedef union { + struct { + /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_timer0_res_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer0_res_update_en:1; + /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_timer1_res_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer1_res_update_en:1; + /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_timer2_res_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer2_res_update_en:1; + /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_timer3_res_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer3_res_update_en:1; + /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_timer0_cap task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer0_cap_en:1; + /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_timer1_cap task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer1_cap_en:1; + /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_timer2_cap task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer2_cap_en:1; + /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_timer3_cap task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer3_cap_en:1; + /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch0_en:1; + /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch1_en:1; + /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch2_en:1; + /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch3_en:1; + /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch4_en:1; + /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch5_en:1; + /** task_sig_out_dis_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable ledc_ch6_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch6_en:1; + /** task_sig_out_dis_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable ledc_ch7_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch7_en:1; + /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch0_en:1; + /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch1_en:1; + /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch2_en:1; + /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch3_en:1; + /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch4_en:1; + /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch5_en:1; + /** task_ovf_cnt_rst_ch6_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch6_en:1; + /** task_ovf_cnt_rst_ch7_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch7_en:1; + /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable ledc_timer0_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer0_rst_en:1; + /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable ledc_timer1_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer1_rst_en:1; + /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable ledc_timer2_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer2_rst_en:1; + /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable ledc_timer3_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer3_rst_en:1; + /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable ledc_timer0_pause_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer0_pause_resume_en:1; + /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable ledc_timer1_pause_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer1_pause_resume_en:1; + /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable ledc_timer2_pause_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer2_pause_resume_en:1; + /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable ledc_timer3_pause_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer3_pause_resume_en:1; + }; + uint32_t val; +} ledc_evt_task_en1_reg_t; + +/** Type of evt_task_en2 register + * Ledc event task enable bit register2. + */ +typedef union { + struct { + /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch0_en:1; + /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch1_en:1; + /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch2_en:1; + /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch3_en:1; + /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch4_en:1; + /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch5_en:1; + /** task_gamma_restart_ch6_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch6_en:1; + /** task_gamma_restart_ch7_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch7_en:1; + /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch0_en:1; + /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch1_en:1; + /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch2_en:1; + /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch3_en:1; + /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch4_en:1; + /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch5_en:1; + /** task_gamma_pause_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch6_en:1; + /** task_gamma_pause_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch7_en:1; + /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch0_en:1; + /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch1_en:1; + /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch2_en:1; + /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch3_en:1; + /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch4_en:1; + /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch5_en:1; + /** task_gamma_resume_ch6_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch6_en:1; + /** task_gamma_resume_ch7_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch7_en:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} ledc_evt_task_en2_reg_t; + +/** Type of timern_cmp register + * Ledc timern compare value register. + */ +typedef union { + struct { + /** timer_cmp : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timern. + */ + uint32_t timer_cmp:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cmp_reg_t; + +/** Type of timern_cnt_cap register + * Ledc timern captured count value register. + */ +typedef union { + struct { + /** timer_cnt_cap : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timern count value. + */ + uint32_t timer_cnt_cap:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cnt_cap_reg_t; + /** Group: Interrupt Register */ /** Type of int_raw register @@ -571,607 +1265,13 @@ typedef union { } ledc_int_clr_reg_t; -/** Group: gamma */ -/** Type of chn_gamma_conf register - * Ledc chn gamma config register. - */ -typedef union { - struct { - /** ch0_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC chn. - */ - uint32_t ch0_gamma_entry_num:5; - /** ch0_gamma_pause : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No - * effect\\1: Pause - */ - uint32_t ch0_gamma_pause:1; - /** ch0_gamma_resume : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No - * effect\\1: Resume - */ - uint32_t ch0_gamma_resume:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ledc_chn_gamma_conf_reg_t; - - -/** Group: en0 */ -/** Type of evt_task_en0 register - * Ledc event task enable bit register0. - */ -typedef union { - struct { - /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch0_en:1; - /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch1_en:1; - /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch2_en:1; - /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch3_en:1; - /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch4_en:1; - /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch5_en:1; - /** evt_duty_chng_end_ch6_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch6_en:1; - /** evt_duty_chng_end_ch7_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch7_en:1; - /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch0_en:1; - /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch1_en:1; - /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch2_en:1; - /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch3_en:1; - /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch4_en:1; - /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch5_en:1; - /** evt_ovf_cnt_pls_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch6_en:1; - /** evt_ovf_cnt_pls_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch7_en:1; - /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_time_ovf_timer0_en:1; - /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_time_ovf_timer1_en:1; - /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_time_ovf_timer2_en:1; - /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_time_ovf_timer3_en:1; - /** evt_timer0_cmp_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer0_cmp_en:1; - /** evt_timer1_cmp_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer1_cmp_en:1; - /** evt_timer2_cmp_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer2_cmp_en:1; - /** evt_timer3_cmp_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer3_cmp_en:1; - /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch0_en:1; - /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch1_en:1; - /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch2_en:1; - /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch3_en:1; - /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch4_en:1; - /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch5_en:1; - /** task_duty_scale_update_ch6_en : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch6_en:1; - /** task_duty_scale_update_ch7_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch7_en:1; - }; - uint32_t val; -} ledc_evt_task_en0_reg_t; - - -/** Group: en1 */ -/** Type of evt_task_en1 register - * Ledc event task enable bit register1. - */ -typedef union { - struct { - /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer0_res_update_en:1; - /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer1_res_update_en:1; - /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer2_res_update_en:1; - /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer3_res_update_en:1; - /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable - */ - uint32_t task_timer0_cap_en:1; - /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable - */ - uint32_t task_timer1_cap_en:1; - /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable - */ - uint32_t task_timer2_cap_en:1; - /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable - */ - uint32_t task_timer3_cap_en:1; - /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch0_en:1; - /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch1_en:1; - /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch2_en:1; - /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch3_en:1; - /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch4_en:1; - /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch5_en:1; - /** task_sig_out_dis_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch6_en:1; - /** task_sig_out_dis_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch7_en:1; - /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch0_en:1; - /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch1_en:1; - /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch2_en:1; - /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch3_en:1; - /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch4_en:1; - /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch5_en:1; - /** task_ovf_cnt_rst_ch6_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch6_en:1; - /** task_ovf_cnt_rst_ch7_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch7_en:1; - /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable - */ - uint32_t task_timer0_rst_en:1; - /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable - */ - uint32_t task_timer1_rst_en:1; - /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable - */ - uint32_t task_timer2_rst_en:1; - /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable - */ - uint32_t task_timer3_rst_en:1; - /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer0_pause_resume_en:1; - /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer1_pause_resume_en:1; - /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer2_pause_resume_en:1; - /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer3_pause_resume_en:1; - }; - uint32_t val; -} ledc_evt_task_en1_reg_t; - - -/** Group: en2 */ -/** Type of evt_task_en2 register - * Ledc event task enable bit register2. - */ -typedef union { - struct { - /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch0_en:1; - /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch1_en:1; - /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch2_en:1; - /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch3_en:1; - /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch4_en:1; - /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch5_en:1; - /** task_gamma_restart_ch6_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch6_en:1; - /** task_gamma_restart_ch7_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch7_en:1; - /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch0_en:1; - /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch1_en:1; - /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch2_en:1; - /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch3_en:1; - /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch4_en:1; - /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch5_en:1; - /** task_gamma_pause_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch6_en:1; - /** task_gamma_pause_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch7_en:1; - /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch0_en:1; - /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch1_en:1; - /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch2_en:1; - /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch3_en:1; - /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch4_en:1; - /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch5_en:1; - /** task_gamma_resume_ch6_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch6_en:1; - /** task_gamma_resume_ch7_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch7_en:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} ledc_evt_task_en2_reg_t; - - -/** Group: cmp */ -/** Type of timern_cmp register - * Ledc timern compare value register. - */ -typedef union { - struct { - /** timer0_cmp : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timern. - */ - uint32_t timer0_cmp:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_timern_cmp_reg_t; - - -/** Group: cap */ -/** Type of timern_cnt_cap register - * Ledc timern captured count value register. - */ -typedef union { - struct { - /** timer0_cnt_cap : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timern count value. - */ - uint32_t timer_cnt_cap:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_timern_cnt_cap_reg_t; - - -/** Group: Configuration Register */ -/** Type of conf register - * LEDC global configuration register - */ -typedef union { - struct { - /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0; - * Configures the clock source for the four timers.\\0: APB_CLK\\1: RC_FAST_CLK\\2: - * XTAL_CLK\\3: Invalid. No clock - */ - uint32_t apb_clk_sel:2; - /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the - * clock gate for LEDC ch0 gamma ram - */ - uint32_t gamma_ram_clk_en_ch0:1; - /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; - * Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the - * clock gate for LEDC ch1 gamma ram - */ - uint32_t gamma_ram_clk_en_ch1:1; - /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the - * clock gate for LEDC ch2 gamma ram - */ - uint32_t gamma_ram_clk_en_ch2:1; - /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the - * clock gate for LEDC ch3 gamma ram - */ - uint32_t gamma_ram_clk_en_ch3:1; - /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the - * clock gate for LEDC ch4 gamma ram - */ - uint32_t gamma_ram_clk_en_ch4:1; - /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; - * Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the - * clock gate for LEDC ch5 gamma ram - */ - uint32_t gamma_ram_clk_en_ch5:1; - /** gamma_ram_clk_en_ch6 : R/W; bitpos: [8]; default: 0; - * Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch6 gamma ram\\1: Force open the - * clock gate for LEDC ch6 gamma ram - */ - uint32_t gamma_ram_clk_en_ch6:1; - /** gamma_ram_clk_en_ch7 : R/W; bitpos: [9]; default: 0; - * Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch7 gamma ram\\1: Force open the - * clock gate for LEDC ch7 gamma ram - */ - uint32_t gamma_ram_clk_en_ch7:1; - uint32_t reserved_10:21; - /** clk_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to open register clock gate.\\0: Open the clock gate only - * when application writes registers\\1: Force open the clock gate for register - */ - uint32_t clk_en:1; - }; - uint32_t val; -} ledc_conf_reg_t; - - /** Group: Version Register */ /** Type of date register * Version control register */ typedef union { struct { - /** ledc_date : R/W; bitpos: [27:0]; default: 36712560; + /** ledc_date : R/W; bitpos: [27:0]; default: 37765152; * Configures the version. */ uint32_t ledc_date:28; @@ -1180,6 +1280,7 @@ typedef union { uint32_t val; } ledc_date_reg_t; + typedef struct { volatile ledc_chn_conf0_reg_t conf0; volatile ledc_chn_hpoint_reg_t hpoint; @@ -1205,7 +1306,7 @@ typedef struct { volatile ledc_ch_group_reg_t channel_group[1]; volatile ledc_timer_group_reg_t timer_group[1]; volatile ledc_int_raw_reg_t int_raw; - volatile ledc_int_st_reg_t int_st; + volatile ledc_int_st_reg_t int_st; volatile ledc_int_ena_reg_t int_ena; volatile ledc_int_clr_reg_t int_clr; uint32_t reserved_0d0[12]; @@ -1221,7 +1322,6 @@ typedef struct { volatile ledc_date_reg_t date; } ledc_dev_t; - /** * Gamma fade param group ram type */ @@ -1244,7 +1344,6 @@ typedef struct { volatile ledc_gamma_channel_t channel[8]; } ledc_gamma_ram_t; - extern ledc_dev_t LEDC; extern ledc_gamma_ram_t LEDC_GAMMA_RAM; diff --git a/docs/en/api-reference/peripherals/ledc.rst b/docs/en/api-reference/peripherals/ledc.rst index fdc2fa6dd0..d15a676fc3 100644 --- a/docs/en/api-reference/peripherals/ledc.rst +++ b/docs/en/api-reference/peripherals/ledc.rst @@ -298,6 +298,10 @@ The range of the duty cycle values passed to functions depends on selected ``dut The hardware limitation above only applies to chip revision before v1.2. + .. only:: esp32p4 + + The hardware limitation above only applies to chip revision before v3.0. + Change PWM Duty Cycle Using Hardware """""""""""""""""""""""""""""""""""" diff --git a/docs/zh_CN/api-reference/peripherals/ledc.rst b/docs/zh_CN/api-reference/peripherals/ledc.rst index 8e8bfa6e77..5a2cb1d199 100644 --- a/docs/zh_CN/api-reference/peripherals/ledc.rst +++ b/docs/zh_CN/api-reference/peripherals/ledc.rst @@ -298,6 +298,10 @@ LEDC 驱动提供了一个辅助函数 :cpp:func:`ledc_find_suitable_duty_resolu 以上硬件限制仅在芯片版本低于 v1.2 的 ESP32H2 上存在。 + .. only:: esp32p4 + + 以上硬件限制仅在芯片版本低于 v3.0 的 ESP32P4 上存在。 + 使用硬件改变 PWM 占空比 """""""""""""""""""""""""""""""""""" diff --git a/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c b/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c index df8352731d..02cdebccad 100644 --- a/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c +++ b/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c @@ -19,7 +19,7 @@ #define LEDC_FREQUENCY (4000) // Frequency in Hertz. Set frequency at 4 kHz /* Warning: - * For ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4 targets, + * For ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4 (rev < 3.0) targets, * when LEDC_DUTY_RES selects the maximum duty resolution (i.e. value equal to SOC_LEDC_TIMER_BIT_WIDTH), * 100% duty cycle is not reachable (duty cannot be set to (2 ** SOC_LEDC_TIMER_BIT_WIDTH)). */