diff --git a/components/esp_mm/esp_cache_msync.c b/components/esp_mm/esp_cache_msync.c
index a53a49aec7..411fc4eb25 100644
--- a/components/esp_mm/esp_cache_msync.c
+++ b/components/esp_mm/esp_cache_msync.c
@@ -33,6 +33,16 @@ DEFINE_CRIT_SECTION_LOCK_STATIC(s_spinlock);
 static _lock_t s_mutex;
 #endif
 
+void esp_cache_sync_ops_enter_critical_section(void)
+{
+    esp_os_enter_critical_safe(&s_spinlock);
+}
+
+void esp_cache_sync_ops_exit_critical_section(void)
+{
+    esp_os_exit_critical_safe(&s_spinlock);
+}
+
 #if SOC_CACHE_WRITEBACK_SUPPORTED
 static void s_c2m_ops(uint32_t vaddr, size_t size)
 {
diff --git a/components/esp_mm/esp_mmu_map.c b/components/esp_mm/esp_mmu_map.c
index 6bdd8420ef..791b55d59d 100644
--- a/components/esp_mm/esp_mmu_map.c
+++ b/components/esp_mm/esp_mmu_map.c
@@ -404,7 +404,9 @@ static void IRAM_ATTR NOINLINE_ATTR s_do_cache_invalidate(uint32_t vaddr_start,
      */
     cache_sync();
 #else   //Other chips
+    esp_cache_sync_ops_enter_critical_section();
     cache_hal_invalidate_addr(vaddr_start, size);
+    esp_cache_sync_ops_exit_critical_section();
 #endif // CONFIG_IDF_TARGET_ESP32
 }
 
diff --git a/components/esp_mm/include/esp_private/esp_cache_private.h b/components/esp_mm/include/esp_private/esp_cache_private.h
index 0fb3dae103..4c37b4027c 100644
--- a/components/esp_mm/include/esp_private/esp_cache_private.h
+++ b/components/esp_mm/include/esp_private/esp_cache_private.h
@@ -67,6 +67,16 @@ void esp_cache_freeze_caches_disable_interrupts(void);
 void esp_cache_unfreeze_caches_enable_interrupts(void);
 #endif
 
+/**
+ * @brief Enter critical section for cache sync operations
+ */
+void esp_cache_sync_ops_enter_critical_section(void);
+
+/**
+ * @brief Exit critical section for cache sync operations
+ */
+void esp_cache_sync_ops_exit_critical_section(void);
+
 /**
  * @brief Get Cache alignment requirement for data
  *
diff --git a/components/spi_flash/flash_mmap.c b/components/spi_flash/flash_mmap.c
index d9476cbe30..8b5ed948e6 100644
--- a/components/spi_flash/flash_mmap.c
+++ b/components/spi_flash/flash_mmap.c
@@ -22,6 +22,7 @@
 #endif
 
 #include "esp_private/esp_mmu_map_private.h"
+#include "esp_private/esp_cache_private.h"
 #include "esp_mmu_map.h"
 #include "esp_rom_spiflash.h"
 #if CONFIG_SPIRAM
@@ -315,7 +316,9 @@ IRAM_ATTR bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length)
             return true;
 #else // CONFIG_IDF_TARGET_ESP32
             if (vaddr != NULL) {
+                esp_cache_sync_ops_enter_critical_section();
                 cache_hal_invalidate_addr((uint32_t)vaddr, SPI_FLASH_MMU_PAGE_SIZE);
+                esp_cache_sync_ops_exit_critical_section();
                 ret = true;
             }
 #endif // CONFIG_IDF_TARGET_ESP32