diff --git a/components/esp_security/src/init.c b/components/esp_security/src/init.c
index 9a3a3fc147..db1fac033a 100644
--- a/components/esp_security/src/init.c
+++ b/components/esp_security/src/init.c
@@ -55,16 +55,6 @@ static void esp_key_mgr_init(void)
 
 ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
 {
-#if CONFIG_IDF_TARGET_ESP32C5
-    // Check for unsupported configuration: flash encryption with CPU frequency > 160MHz
-    // Manual encrypted flash writes are not stable at higher CPU clock.
-    // Please refer to the ESP32-C5 SoC Errata document for more details.
-    if (efuse_hal_flash_encryption_enabled() && CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ > 160) {
-        ESP_EARLY_LOGE(TAG, "Flash encryption with CPU frequency > 160MHz is not supported. Please reconfigure the CPU frequency.");
-        return ESP_ERR_NOT_SUPPORTED;
-    }
-#endif
-
     esp_crypto_clk_init();
 
 #if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
diff --git a/components/esp_system/port/soc/esp32c5/Kconfig.cpu b/components/esp_system/port/soc/esp32c5/Kconfig.cpu
index 95c3b92cbc..a9fd58e28f 100644
--- a/components/esp_system/port/soc/esp32c5/Kconfig.cpu
+++ b/components/esp_system/port/soc/esp32c5/Kconfig.cpu
@@ -1,12 +1,9 @@
 choice ESP_DEFAULT_CPU_FREQ_MHZ
     prompt "CPU frequency"
     default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA
-    default ESP_DEFAULT_CPU_FREQ_MHZ_160 if SECURE_FLASH_ENC_ENABLED
     default ESP_DEFAULT_CPU_FREQ_MHZ_240
     help
-        CPU frequency to be set on application startup. For flash encryption enabled case,
-        the default CPU frequency is 160MHz as the encrypted flash writes are not stable at
-        higher CPU clock. Please see SoC Errata document for details.
+        CPU frequency to be set on application startup.
 
     config ESP_DEFAULT_CPU_FREQ_MHZ_40
         bool "40 MHz"
@@ -16,9 +13,6 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
     config ESP_DEFAULT_CPU_FREQ_MHZ_160
         bool "160 MHz"
     config ESP_DEFAULT_CPU_FREQ_MHZ_240
-        # Encrypted flash writes aren't supported at 240 MHz.
-        # Please see SoC Errata document for details.
-        depends on !SECURE_FLASH_ENC_ENABLED
         bool "240 MHz"
         help
             When 240MHz is selected, esp_flash_write_encrypted() will automatically limit CPU frequency during