From 3a739eba9bfbeb0786fb76ef3aa63dd146bd696e Mon Sep 17 00:00:00 2001
From: Guilherme Ferreira <guilherme.ferreira@espressif.com>
Date: Thu, 19 Mar 2026 20:51:09 -0300
Subject: [PATCH] fix(esp_eth): correct PHYCFGR sanity check mask and bit
 validation

Closes https://github.com/espressif/esp-idf/issues/17530
---
 components/esp_eth/src/spi/w5500/esp_eth_mac_w5500.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/components/esp_eth/src/spi/w5500/esp_eth_mac_w5500.c b/components/esp_eth/src/spi/w5500/esp_eth_mac_w5500.c
index 48856d285b..393da0a077 100644
--- a/components/esp_eth/src/spi/w5500/esp_eth_mac_w5500.c
+++ b/components/esp_eth/src/spi/w5500/esp_eth_mac_w5500.c
@@ -613,7 +613,7 @@ static inline bool is_w5500_sane_for_rxtx(emac_w5500_t *emac)
 {
     uint8_t phycfg;
     /* phy is ok for rx and tx operations if bits RST and LNK are set (no link down, no reset) */
-    if (w5500_read(emac, W5500_REG_PHYCFGR, &phycfg, 1) == ESP_OK && (phycfg & 0x8001)) {
+    if (w5500_read(emac, W5500_REG_PHYCFGR, &phycfg, 1) == ESP_OK && (phycfg & 0x81) == 0x81) {
         return true;
     }
    return false;