From 3cf86e260ca867b5ad71876cea80bc228a35aee4 Mon Sep 17 00:00:00 2001 From: Chen Chen Date: Tue, 25 Nov 2025 18:00:28 +0800 Subject: [PATCH] refactor(esp_system): clear dependency on hal components --- components/esp_hw_support/CMakeLists.txt | 5 + components/esp_system/CMakeLists.txt | 16 +- components/esp_system/port/soc/esp32c5/clk.c | 129 +-------- components/esp_system/port/soc/esp32c6/clk.c | 119 +-------- components/esp_system/port/soc/esp32h2/clk.c | 106 +------- components/esp_system/port/soc/esp32p4/clk.c | 210 ++------------- .../hal/esp32c5/include/hal/clk_gate_ll.h | 93 +++++++ .../hal/esp32c6/include/hal/clk_gate_ll.h | 127 ++++++++- .../hal/esp32h2/include/hal/clk_gate_ll.h | 104 ++++++++ components/hal/esp32p4/include/hal/apm_ll.h | 2 +- .../hal/esp32p4/include/hal/clk_gate_ll.h | 234 ++++++++++++++++ components/hal/esp32p4/include/hal/uart_ll.h | 10 +- .../soc/esp32c5/register/soc/lp_apm0_struct.h | 1 + .../soc/esp32h4/register/soc/trace_reg.h | 40 +-- components/soc/esp32p4/include/soc/soc.h | 1 - .../soc/esp32p4/ld/esp32p4.peripherals.ld | 1 + .../hw_ver1/soc/assist_debug_struct.h | 1 + .../register/hw_ver1/soc/hp_peri_pms_reg.h | 40 +-- .../register/hw_ver1/soc/lp2hp_peri_pms_reg.h | 10 +- .../esp32p4/register/hw_ver1/soc/trace_reg.h | 2 + .../hw_ver1/soc/usb_serial_jtag_reg.h | 116 ++++---- .../hw_ver3/soc/hp_peri_pms_eco5_reg.h | 40 +-- .../register/hw_ver3/soc/hp_peri_pms_reg.h | 40 +-- .../register/hw_ver3/soc/hp_sys_clkrst_reg.h | 90 +++---- .../hw_ver3/soc/lp2hp_peri_pms_eco5_reg.h | 10 +- .../register/hw_ver3/soc/lp2hp_peri_pms_reg.h | 10 +- .../esp32p4/register/hw_ver3/soc/trace_reg.h | 40 +-- .../hw_ver3/soc/usb_serial_jtag_reg.h | 252 +++++++++--------- .../esp32s31/register/soc/hp_peri0_pms_reg.h | 94 +++---- .../esp32s31/register/soc/hp_sys_clkrst_reg.h | 94 +++---- .../system/g1_components/CMakeLists.txt | 11 +- .../system/g1_components/main/CMakeLists.txt | 2 +- 32 files changed, 1065 insertions(+), 985 deletions(-) diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index b5a495ac5e..bff4639928 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -211,6 +211,11 @@ if(NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3 AND CONFIG_IDF_TARGET_ESP32P4) endif() endif() +if(${target} STREQUAL "esp32p4") + # for mipi_csi_share_hw_ctrl.c + list(APPEND priv_requires esp_hal_cam) +endif() + idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${public_include_dirs} PRIV_INCLUDE_DIRS port/include include/esp_private diff --git a/components/esp_system/CMakeLists.txt b/components/esp_system/CMakeLists.txt index 5ffa44d759..b213ce4eb0 100644 --- a/components/esp_system/CMakeLists.txt +++ b/components/esp_system/CMakeLists.txt @@ -75,25 +75,11 @@ else() idf_component_register(SRCS "${srcs}" INCLUDE_DIRS include - PRIV_REQUIRES spi_flash esp_timer esp_mm esp_hal_mspi + PRIV_REQUIRES spi_flash esp_timer esp_mm esp_hal_mspi esp_hal_wdt # [refactor-todo] requirements due to init code, # should be removable once using component init functions # link-time registration is used. bootloader_support esp_pm esp_usb_cdc_rom_console - # [REFACTOR-TODO] Provide system hook to release dependency reversion. - # IDF-13980 - esp_hal_i2c - esp_hal_i2s - esp_hal_wdt - esp_hal_lcd - esp_hal_mcpwm - esp_hal_jpeg - esp_hal_emac - esp_hal_pcnt - esp_hal_rmt - esp_hal_parlio - esp_hal_cam - esp_hal_twai LDFRAGMENTS "linker.lf" "app.lf") add_subdirectory(port) diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c index cffc44fd66..549ebd941a 100644 --- a/components/esp_system/port/soc/esp32c5/clk.c +++ b/components/esp_system/port/soc/esp32c5/clk.c @@ -27,38 +27,9 @@ #if SOC_MODEM_CLOCK_SUPPORTED #include "hal/modem_lpcon_ll.h" #endif -#include "hal/adc_ll.h" -#include "hal/aes_ll.h" -#include "hal/assist_debug_ll.h" #include "hal/apm_ll.h" #include "hal/clk_gate_ll.h" #include "hal/clk_tree_ll.h" -#include "hal/ds_ll.h" -#include "hal/ecc_ll.h" -#include "hal/etm_ll.h" -#include "hal/gdma_ll.h" -#include "hal/hmac_ll.h" -#include "hal/i2c_ll.h" -#include "hal/i2s_ll.h" -#include "hal/ledc_ll.h" -#include "hal/lp_core_ll.h" -#include "hal/lp_clkrst_ll.h" -#include "hal/mcpwm_ll.h" -#include "hal/mpi_ll.h" -#include "hal/mspi_ll.h" -#include "hal/parlio_ll.h" -#include "hal/pau_ll.h" -#include "hal/pcnt_ll.h" -#include "hal/rmt_ll.h" -#include "hal/rtc_io_ll.h" -#include "hal/sha_ll.h" -#include "hal/spi_ll.h" -#include "hal/temperature_sensor_ll.h" -#include "hal/timer_ll.h" -#include "hal/twai_ll.h" -#include "hal/uart_ll.h" -#include "hal/uhci_ll.h" -#include "hal/usb_serial_jtag_ll.h" #include "esp_private/esp_sleep_internal.h" #include "esp_private/esp_modem_clock.h" #include "esp_private/periph_ctrl.h" @@ -269,103 +240,23 @@ __attribute__((weak)) void esp_perip_clk_init(void) clk_ll_soc_root_clk_auto_gating_bypass(true); soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); - if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) \ - && (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT) \ - && (rst_reason != RESET_REASON_CPU0_JTAG) && (rst_reason != RESET_REASON_CPU0_LOCKUP)) { + periph_ll_clk_gate_config_t clk_gate_config = {0}; + #if CONFIG_ESP_CONSOLE_UART_NUM != 0 - uart_ll_enable_bus_clock(UART_NUM_0, false); - uart_ll_sclk_disable(&UART0); -#elif CONFIG_ESP_CONSOLE_UART_NUM != 1 - uart_ll_sclk_disable(&UART1); - uart_ll_enable_bus_clock(UART_NUM_1, false); + clk_gate_config.disable_uart0_clk = true; +#endif +#if CONFIG_ESP_CONSOLE_UART_NUM != 1 + clk_gate_config.disable_uart1_clk = true; #endif - i2c_ll_enable_bus_clock(0, false); - i2c_ll_enable_controller_clock(&I2C0, false); - rmt_ll_enable_bus_clock(0, false); - rmt_ll_enable_group_clock(0, false); - ledc_ll_enable_clock(&LEDC, false); - ledc_ll_enable_bus_clock(false); - clk_ll_enable_timergroup_rtc_calibration_clock(false); - timer_ll_enable_clock(0, 0, false); - timer_ll_enable_clock(1, 0, false); - _timg_ll_enable_bus_clock(0, false); - _timg_ll_enable_bus_clock(1, false); - twai_ll_enable_clock(0, false); - twai_ll_enable_bus_clock(0, false); - twai_ll_enable_clock(1, false); - twai_ll_enable_bus_clock(1, false); - i2s_ll_enable_bus_clock(0, false); - i2s_ll_tx_disable_clock(&I2S0); - i2s_ll_rx_disable_clock(&I2S0); - adc_ll_enable_bus_clock(false); - pcnt_ll_enable_bus_clock(0, false); - etm_ll_enable_bus_clock(0, false); - mcpwm_ll_enable_bus_clock(0, false); - mcpwm_ll_group_enable_clock(0, false); - parlio_ll_rx_enable_clock(&PARL_IO, false); - parlio_ll_tx_enable_clock(&PARL_IO, false); - parlio_ll_enable_bus_clock(0, false); - ahb_dma_ll_force_enable_reg_clock(&AHB_DMA, false); - _gdma_ll_enable_bus_clock(0, false); #if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP - mspi_timing_ll_enable_core_clock(0, false); + clk_gate_config.disable_mspi_flash_clk = true; #endif - spi_ll_enable_bus_clock(SPI2_HOST, false); - temperature_sensor_ll_bus_clk_enable(false); - pau_ll_enable_bus_clock(false); -#if !CONFIG_ESP_SYSTEM_HW_PC_RECORD - /* Disable ASSIST Debug module clock if PC recoreding function is not used, - * if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */ - assist_debug_ll_enable_bus_clock(false); -#endif - mpi_ll_enable_bus_clock(false); #if !CONFIG_SECURE_ENABLE_TEE - aes_ll_enable_bus_clock(false); - sha_ll_enable_bus_clock(false); - ecc_ll_enable_bus_clock(false); - hmac_ll_enable_bus_clock(false); - ds_ll_enable_bus_clock(false); - apm_ll_hp_tee_enable_clk_gating(true); - apm_ll_lp_tee_enable_clk_gating(true); - apm_ll_hp_apm_enable_ctrl_clk_gating(true); - apm_ll_cpu_apm_enable_ctrl_clk_gating(true); + clk_gate_config.disable_crypto_periph_clk = true; #endif - uhci_ll_enable_bus_clock(0, false); - - // TODO: Replace with hal implementation - REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN); - REG_CLR_BIT(PCR_TCM_MEM_MONITOR_CONF_REG, PCR_TCM_MEM_MONITOR_CLK_EN); - REG_CLR_BIT(PCR_PSRAM_MEM_MONITOR_CONF_REG, PCR_PSRAM_MEM_MONITOR_CLK_EN); - REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN); - REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN); - WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0); - #if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED - // Disable USB-Serial-JTAG clock and it's pad if not used - usb_serial_jtag_ll_phy_enable_pad(false); - usb_serial_jtag_ll_enable_bus_clock(false); - usb_serial_jtag_ll_enable_mem_clock(false); - usb_serial_jtag_ll_set_mem_pd(true); + clk_gate_config.disable_usb_serial_jtag = true; #endif - } - if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \ - || (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) \ - || (rst_reason == RESET_REASON_CORE_PWR_GLITCH)) { - _lp_i2c_ll_enable_bus_clock(0, false); - lp_uart_ll_sclk_disable(0); - _lp_uart_ll_enable_bus_clock(0, false); - _lp_core_ll_enable_bus_clock(false); - _rtcio_ll_enable_io_clock(false); - _lp_clkrst_ll_enable_rng_clock(false); - _lp_clkrst_ll_enable_otp_dbg_clock(false); - _lp_clkrst_ll_enable_lp_ana_i2c_clock(false); - _lp_clkrst_ll_enable_lp_ext_i2c_clock(false); - -#if !CONFIG_SECURE_ENABLE_TEE - apm_ll_lp_apm_enable_ctrl_clk_gating(true); - apm_ll_lp_apm0_enable_ctrl_clk_gating(true); -#endif - WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0); - } + periph_ll_clk_gate_set_default(rst_reason, &clk_gate_config); } diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c index 50a2ccd572..cf8792c912 100644 --- a/components/esp_system/port/soc/esp32c6/clk.c +++ b/components/esp_system/port/soc/esp32c6/clk.c @@ -9,44 +9,17 @@ #include #include #include "sdkconfig.h" -#include "esp_attr.h" #include "esp_log.h" -#include "esp_clk_internal.h" -#include "esp32c6/rom/ets_sys.h" -#include "esp32c6/rom/uart.h" #include "soc/soc.h" #include "soc/rtc.h" -#include "soc/rtc_periph.h" -#include "soc/i2s_reg.h" -#include "soc/lpperi_reg.h" -#include "soc/lp_clkrst_reg.h" #include "esp_cpu.h" #include "hal/wdt_hal.h" -#include "hal/uart_ll.h" -#include "hal/i2c_ll.h" -#include "hal/rmt_ll.h" -#include "hal/ledc_ll.h" -#include "hal/lp_clkrst_ll.h" -#include "hal/timer_ll.h" -#include "hal/twai_ll.h" -#include "hal/i2s_ll.h" -#include "hal/pcnt_ll.h" -#include "hal/etm_ll.h" -#include "hal/mcpwm_ll.h" -#include "hal/parlio_ll.h" -#include "hal/gdma_ll.h" -#include "hal/pau_ll.h" -#include "hal/spi_ll.h" #include "hal/clk_gate_ll.h" -#include "hal/lp_core_ll.h" -#include "hal/temperature_sensor_ll.h" -#include "hal/usb_serial_jtag_ll.h" +#include "hal/pmu_ll.h" #include "esp_private/esp_modem_clock.h" -#include "esp_private/periph_ctrl.h" #include "esp_private/esp_clk.h" #include "esp_private/esp_pmu.h" #include "esp_rom_serial_output.h" -#include "esp_rom_sys.h" /* Number of cycles to wait from the 32k XTAL oscillator to consider it running. * Larger values increase startup delay. Smaller values may cause false positive @@ -248,96 +221,28 @@ __attribute__((weak)) void esp_perip_clk_init(void) #endif soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); - if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) \ - && (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT) \ - && (rst_reason != RESET_REASON_CPU0_JTAG)) { + periph_ll_clk_gate_config_t clk_gate_config = {0}; + #if CONFIG_ESP_CONSOLE_UART_NUM != 0 - uart_ll_enable_bus_clock(UART_NUM_0, false); - uart_ll_sclk_disable(&UART0); -#elif CONFIG_ESP_CONSOLE_UART_NUM != 1 - uart_ll_sclk_disable(&UART1); - uart_ll_enable_bus_clock(UART_NUM_1, false); + clk_gate_config.disable_uart0_clk = true; +#endif +#if CONFIG_ESP_CONSOLE_UART_NUM != 1 + clk_gate_config.disable_uart1_clk = true; #endif - i2c_ll_enable_bus_clock(0, false); - i2c_ll_enable_controller_clock(&I2C0, false); - rmt_ll_enable_bus_clock(0, false); - rmt_ll_enable_group_clock(0, false); - ledc_ll_enable_clock(&LEDC, false); - ledc_ll_enable_bus_clock(false); - timer_ll_enable_clock(0, 0, false); - timer_ll_enable_clock(1, 0, false); - _timg_ll_enable_bus_clock(0, false); - _timg_ll_enable_bus_clock(1, false); - twai_ll_enable_clock(0, false); - twai_ll_enable_bus_clock(0, false); - twai_ll_enable_clock(1, false); - twai_ll_enable_bus_clock(1, false); - i2s_ll_enable_bus_clock(0, false); - i2s_ll_tx_disable_clock(&I2S0); - i2s_ll_rx_disable_clock(&I2S0); - pcnt_ll_enable_bus_clock(0, false); - etm_ll_enable_bus_clock(0, false); - mcpwm_ll_enable_bus_clock(0, false); - mcpwm_ll_group_enable_clock(0, false); - parlio_ll_rx_enable_clock(&PARL_IO, false); - parlio_ll_tx_enable_clock(&PARL_IO, false); - parlio_ll_enable_bus_clock(0, false); - gdma_ll_force_enable_reg_clock(&GDMA, false); - _gdma_ll_enable_bus_clock(0, false); #if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP - spi_ll_enable_bus_clock(SPI1_HOST, false); + clk_gate_config.disable_mspi_flash_clk = true; #endif - spi_ll_enable_bus_clock(SPI2_HOST, false); - temperature_sensor_ll_bus_clk_enable(false); - pau_ll_enable_bus_clock(false); - - periph_ll_disable_clk_set_rst(PERIPH_UHCI0_MODULE); - periph_ll_disable_clk_set_rst(PERIPH_SARADC_MODULE); - periph_ll_disable_clk_set_rst(PERIPH_SDIO_SLAVE_MODULE); #if !CONFIG_ESP_SYSTEM_HW_PC_RECORD - /* Disable ASSIST Debug module clock if PC recoreding function is not used, - * if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */ - periph_ll_disable_clk_set_rst(PERIPH_ASSIST_DEBUG_MODULE); + clk_gate_config.disable_assist_clk = true; #endif - periph_ll_disable_clk_set_rst(PERIPH_RSA_MODULE); #if !CONFIG_SECURE_ENABLE_TEE - // NOTE: [ESP-TEE] The TEE is responsible for the AES and SHA peripherals - periph_ll_disable_clk_set_rst(PERIPH_AES_MODULE); - periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE); - periph_ll_disable_clk_set_rst(PERIPH_HMAC_MODULE); - periph_ll_disable_clk_set_rst(PERIPH_DS_MODULE); - periph_ll_disable_clk_set_rst(PERIPH_ECC_MODULE); + clk_gate_config.disable_crypto_periph_clk = true; #endif - - // TODO: Replace with hal implementation - REG_CLR_BIT(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE); - REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN); - REG_CLR_BIT(PCR_RETENTION_CONF_REG, PCR_RETENTION_CLK_EN); - REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN); - REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN); - REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN); - WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0); - #if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED - // Disable USB-Serial-JTAG clock and it's pad if not used - usb_serial_jtag_ll_phy_enable_pad(false); - usb_serial_jtag_ll_enable_bus_clock(false); + clk_gate_config.disable_usb_serial_jtag = true; #endif - } - if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \ - || (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)) { - _lp_i2c_ll_enable_bus_clock(0, false); - lp_uart_ll_sclk_disable(0); - _lp_uart_ll_enable_bus_clock(0, false); - lp_core_ll_enable_bus_clock(false); - _lp_clkrst_ll_enable_rng_clock(false); - - CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN); - CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_ANA_I2C_CK_EN); - CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_IO_CK_EN); - WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0); - } + periph_ll_clk_gate_set_default(rst_reason, &clk_gate_config); } // Workaround for bootloader not calibrated well issue. diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c index cd61d1e23e..c60dd0dcda 100644 --- a/components/esp_system/port/soc/esp32h2/clk.c +++ b/components/esp_system/port/soc/esp32h2/clk.c @@ -17,34 +17,12 @@ #include "esp32h2/rom/ets_sys.h" #include "esp32h2/rom/uart.h" #include "soc/soc.h" -#include "soc/pcr_reg.h" #include "soc/rtc.h" #include "soc/rtc_periph.h" -#include "soc/i2s_reg.h" -#include "soc/lpperi_reg.h" -#include "soc/lp_clkrst_reg.h" -#include "soc/pcr_reg.h" #include "hal/wdt_hal.h" -#include "hal/uart_ll.h" -#include "hal/i2c_ll.h" -#include "hal/rmt_ll.h" -#include "hal/ledc_ll.h" -#include "hal/lp_clkrst_ll.h" -#include "hal/timer_ll.h" -#include "hal/twai_ll.h" -#include "hal/i2s_ll.h" -#include "hal/pcnt_ll.h" -#include "hal/etm_ll.h" -#include "hal/mcpwm_ll.h" -#include "hal/parlio_ll.h" -#include "hal/gdma_ll.h" -#include "hal/pau_ll.h" -#include "hal/spi_ll.h" #include "hal/clk_gate_ll.h" -#include "hal/temperature_sensor_ll.h" -#include "hal/usb_serial_jtag_ll.h" +#include "hal/pmu_ll.h" #include "esp_private/esp_modem_clock.h" -#include "esp_private/periph_ctrl.h" #include "esp_private/esp_clk.h" #include "esp_private/esp_pmu.h" #include "esp_rom_serial_output.h" @@ -234,88 +212,28 @@ void rtc_clk_select_rtc_slow_clk(void) __attribute__((weak)) void esp_perip_clk_init(void) { soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); - if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) \ - && (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT) \ - && (rst_reason != RESET_REASON_CPU0_JTAG)) { + periph_ll_clk_gate_config_t clk_gate_config = {0}; + #if CONFIG_ESP_CONSOLE_UART_NUM != 0 - uart_ll_enable_bus_clock(UART_NUM_0, false); -#elif CONFIG_ESP_CONSOLE_UART_NUM != 1 - uart_ll_enable_bus_clock(UART_NUM_1, false); + clk_gate_config.disable_uart0_clk = true; +#endif +#if CONFIG_ESP_CONSOLE_UART_NUM != 1 + clk_gate_config.disable_uart1_clk = true; #endif - i2c_ll_enable_bus_clock(0, false); - i2c_ll_enable_bus_clock(1, false); - i2c_ll_enable_controller_clock(&I2C0, false); - i2c_ll_enable_controller_clock(&I2C1, false); - rmt_ll_enable_bus_clock(0, false); - rmt_ll_enable_group_clock(0, false); - ledc_ll_enable_clock(&LEDC, false); - ledc_ll_enable_bus_clock(false); - timer_ll_enable_clock(0, 0, false); - timer_ll_enable_clock(1, 0, false); - _timg_ll_enable_bus_clock(0, false); - _timg_ll_enable_bus_clock(1, false); - twai_ll_enable_clock(0, false); - twai_ll_enable_bus_clock(0, false); - i2s_ll_enable_bus_clock(0, false); - i2s_ll_tx_disable_clock(&I2S0); - i2s_ll_rx_disable_clock(&I2S0); - pcnt_ll_enable_bus_clock(0, false); - etm_ll_enable_bus_clock(0, false); - mcpwm_ll_enable_bus_clock(0, false); - mcpwm_ll_group_enable_clock(0, false); - parlio_ll_rx_enable_clock(&PARL_IO, false); - parlio_ll_tx_enable_clock(&PARL_IO, false); - parlio_ll_enable_bus_clock(0, false); - gdma_ll_force_enable_reg_clock(&GDMA, false); - _gdma_ll_enable_bus_clock(0, false); #if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP - spi_ll_enable_bus_clock(SPI1_HOST, false); + clk_gate_config.disable_mspi_flash_clk = true; #endif - spi_ll_enable_bus_clock(SPI2_HOST, false); - temperature_sensor_ll_bus_clk_enable(false); - pau_ll_enable_bus_clock(false); - - periph_ll_disable_clk_set_rst(PERIPH_UHCI0_MODULE); - periph_ll_disable_clk_set_rst(PERIPH_SARADC_MODULE); #if !CONFIG_ESP_SYSTEM_HW_PC_RECORD - /* Disable ASSIST Debug module clock if PC recoreding function is not used, - * if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */ - periph_ll_disable_clk_set_rst(PERIPH_ASSIST_DEBUG_MODULE); + clk_gate_config.disable_assist_clk = true; #endif - periph_ll_disable_clk_set_rst(PERIPH_RSA_MODULE); #if !CONFIG_SECURE_ENABLE_TEE - // NOTE: [ESP-TEE] The TEE is responsible for the AES and SHA peripherals - periph_ll_disable_clk_set_rst(PERIPH_AES_MODULE); - periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE); - periph_ll_disable_clk_set_rst(PERIPH_ECC_MODULE); - periph_ll_disable_clk_set_rst(PERIPH_HMAC_MODULE); - periph_ll_disable_clk_set_rst(PERIPH_DS_MODULE); + clk_gate_config.disable_crypto_periph_clk = true; #endif - periph_ll_disable_clk_set_rst(PERIPH_ECDSA_MODULE); - - // TODO: Replace with hal implementation - REG_CLR_BIT(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE); - REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN); - REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN); - REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN); - REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN); - WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0); - #if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED - // Disable USB-Serial-JTAG clock and it's pad if not used - usb_serial_jtag_ll_phy_enable_pad(false); - usb_serial_jtag_ll_enable_bus_clock(false); + clk_gate_config.disable_usb_serial_jtag = true; #endif - } - if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \ - || (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)) { - _lp_clkrst_ll_enable_rng_clock(false); - CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN); - CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_ANA_I2C_CK_EN); - CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_IO_CK_EN); - WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0); - } + periph_ll_clk_gate_set_default(rst_reason, &clk_gate_config); } // Workaround for bootloader not calibrated well issue. diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c index 79e296bae0..3262708c5b 100644 --- a/components/esp_system/port/soc/esp32p4/clk.c +++ b/components/esp_system/port/soc/esp32p4/clk.c @@ -18,49 +18,12 @@ #include "soc/soc.h" #include "soc/rtc.h" #include "soc/rtc_periph.h" -#include "soc/i2s_reg.h" -#include "soc/hp_sys_clkrst_reg.h" #include "esp_cpu.h" #include "mspi_timing_tuning_configs.h" - -#include "soc/hp_sys_clkrst_reg.h" -#include "soc/lp_clkrst_reg.h" -#include "soc/lp_system_reg.h" -#include "soc/sdmmc_reg.h" -#include "soc/spi_mem_c_reg.h" -#include "soc/spi_mem_s_reg.h" -#include "soc/usb_serial_jtag_reg.h" -#include "soc/trace_struct.h" - -#include "hal/adc_ll.h" -#include "hal/aes_ll.h" -#include "hal/assist_debug_ll.h" -#include "hal/ds_ll.h" -#include "hal/ecc_ll.h" -#include "hal/emac_ll.h" -#include "hal/etm_ll.h" -#include "hal/gdma_ll.h" -#include "hal/hmac_ll.h" -#include "hal/mipi_csi_ll.h" -#include "hal/mipi_dsi_brg_ll.h" -#include "hal/mpi_ll.h" -#include "hal/pau_ll.h" -#include "hal/parlio_ll.h" -#include "hal/psram_ctrlr_ll.h" -#include "hal/rtc_io_ll.h" -#include "hal/sha_ll.h" -#include "hal/spi_ll.h" -#include "hal/spimem_flash_ll.h" -#include "hal/timer_ll.h" -#include "hal/uart_ll.h" -#include "hal/usb_serial_jtag_ll.h" -#include "hal/usb_utmi_ll.h" +#include "hal/clk_gate_ll.h" #include "hal/wdt_hal.h" -#include "hal/bitscrambler_ll.h" - #include "esp_private/esp_modem_clock.h" #include "esp_private/esp_sleep_internal.h" -#include "esp_private/periph_ctrl.h" #include "esp_private/esp_clk.h" #include "esp_private/esp_pmu.h" #include "esp_rom_serial_output.h" @@ -242,172 +205,39 @@ void rtc_clk_select_rtc_slow_clk(void) __attribute__((weak)) void esp_perip_clk_init(void) { soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); - // HP modules related clock control - if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CORE_PMU_PWR_DOWN) - || (rst_reason == RESET_REASON_SYS_BROWN_OUT) || (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) - || (rst_reason == RESET_REASON_CORE_SW) || (rst_reason == RESET_REASON_CORE_MWDT) || (rst_reason == RESET_REASON_CORE_RWDT) || (rst_reason == RESET_REASON_CORE_PWR_GLITCH) || (rst_reason == RESET_REASON_CORE_EFUSE_CRC) || (rst_reason == RESET_REASON_CORE_USB_JTAG) || (rst_reason == RESET_REASON_CORE_USB_UART) - ) { - // Not gate HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON since the hardware will not automatically ungate when DMA accesses L2 MEM. - REG_CLR_BIT(HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG, HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON - | HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON - | HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON - | HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON - | HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON); - _adc_ll_sar1_clock_force_en(false); - _adc_ll_sar2_clock_force_en(false); - _emac_ll_clock_force_en(false); - // hp_sys_clkrst register gets reset only if chip reset or pmu powers down hp - // but at core reset and above, we will also disable HP modules' clock gating to save power consumption - _gdma_ll_enable_bus_clock(0, false); - _gdma_ll_enable_bus_clock(1, false); - _pau_ll_enable_bus_clock(false); - _parlio_ll_enable_bus_clock(0, false); - _etm_ll_enable_bus_clock(0, false); - _bitscrambler_ll_set_bus_clock_sys_enable(false); - _bitscrambler_ll_set_bus_clock_rx_enable(false); - _bitscrambler_ll_set_bus_clock_tx_enable(false); + periph_ll_clk_gate_config_t clk_gate_config = {0}; -// Non-Console UART #if CONFIG_ESP_CONSOLE_UART_NUM != 0 - _uart_ll_enable_bus_clock(UART_NUM_0, false); - _uart_ll_sclk_disable(&UART0); -#elif CONFIG_ESP_CONSOLE_UART_NUM != 1 - _uart_ll_enable_bus_clock(UART_NUM_1, false); - _uart_ll_sclk_disable(&UART1); + clk_gate_config.disable_uart0_clk = true; +#endif +#if CONFIG_ESP_CONSOLE_UART_NUM != 1 + clk_gate_config.disable_uart1_clk = true; #endif - _uart_ll_enable_bus_clock(UART_NUM_2, false); - _uart_ll_sclk_disable(&UART2); - _uart_ll_enable_bus_clock(UART_NUM_3, false); - _uart_ll_sclk_disable(&UART3); - _uart_ll_enable_bus_clock(UART_NUM_4, false); - _uart_ll_sclk_disable(&UART4); - - _timg_ll_enable_bus_clock(0, false); - _timer_ll_enable_clock(0, 0, false); - _timer_ll_enable_clock(0, 1, false); - - _timg_ll_enable_bus_clock(1, false); - _timer_ll_enable_clock(1, 0, false); - _timer_ll_enable_clock(1, 1, false); - - mipi_dsi_brg_ll_enable_ref_clock(&MIPI_DSI_BRIDGE, false); - _mipi_csi_ll_enable_host_bus_clock(0, false); - - REG_CLR_BIT(SDHOST_CLK_EDGE_SEL_REG, SDHOST_CCLK_EN); - #if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP - _spimem_ctrlr_ll_unset_clock(0); + clk_gate_config.disable_mspi_flash_clk = true; #endif - #if !MSPI_TIMING_FLASH_NEEDS_TUNING - REG_CLR_BIT(SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CLK_ENA); - REG_CLR_BIT(SPI_MEM_C_SMEM_TIMING_CALI_REG, SPI_MEM_C_SMEM_TIMING_CLK_ENA); + clk_gate_config.disable_mspi_flash_timing_clk = true; #endif - #if !MSPI_TIMING_PSRAM_NEEDS_TUNING - REG_CLR_BIT(SPI_MEM_S_TIMING_CALI_REG, SPI_MEM_S_TIMING_CLK_ENA); - REG_CLR_BIT(SPI_MEM_S_SMEM_TIMING_CALI_REG, SPI_MEM_S_SMEM_TIMING_CLK_ENA); + clk_gate_config.disable_mspi_psram_timing_clk = true; #endif - #if !CONFIG_SPIRAM - _psram_ctrlr_ll_enable_core_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false); - _psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false); + clk_gate_config.disable_mspi_psram_clk = true; #endif - - _spi_ll_enable_bus_clock(SPI2_HOST, false); - _spi_ll_enable_bus_clock(SPI3_HOST, false); - _spi_ll_enable_clock(SPI2_HOST, false); - _spi_ll_enable_clock(SPI3_HOST, false); - -#if !CONFIG_ESP_SYSTEM_HW_PC_RECORD - /* Disable ASSIST Debug module clock if PC recoreding function is not used, - * if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */ - _assist_debug_ll_enable_bus_clock(false); -#endif - // Trace & Bus Monitor (0) - TRACE0.clock_gate.clk_en = 0; - TRACE1.clock_gate.clk_en = 0; - REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN); - REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN); - REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN); - - // Crypto Modules - _aes_ll_enable_bus_clock(false); - _ds_ll_enable_bus_clock(false); - _ecc_ll_enable_bus_clock(false); - _hmac_ll_enable_bus_clock(false); - _mpi_ll_enable_bus_clock(false); - _sha_ll_enable_bus_clock(false); - - // USB1.1 - REG_CLR_BIT(LP_CLKRST_HP_USB_CLKRST_CTRL0_REG, LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN); - REG_CLR_BIT(LP_CLKRST_HP_USB_CLKRST_CTRL0_REG, LP_CLKRST_USB_OTG11_48M_CLK_EN); - REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN); - // USB2.0 - _usb_utmi_ll_enable_bus_clock(false); - REG_CLR_BIT(LP_CLKRST_HP_USB_CLKRST_CTRL0_REG, LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN); - REG_CLR_BIT(LP_CLKRST_HP_USB_CLKRST_CTRL1_REG, LP_CLKRST_USB_OTG20_ULPI_CLK_EN); - // UHCI - REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN); - REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN); - -#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED - // Disable USB-Serial-JTAG clock and it's pad if not used - usb_serial_jtag_ll_phy_enable_pad(false); - _usb_serial_jtag_ll_enable_bus_clock(false); - REG_SET_BIT(USB_SERIAL_JTAG_MEM_CONF_REG, USB_SERIAL_JTAG_USB_MEM_PD); - REG_CLR_BIT(USB_SERIAL_JTAG_MEM_CONF_REG, USB_SERIAL_JTAG_USB_MEM_CLK_EN); -#endif - } - - // HP modules' clock source gating control - if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CORE_PMU_PWR_DOWN)) { - // Only safe to disable these clock source gatings if all HP modules clock configurations has been reset - REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_REF_50M_CLK_EN); - REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_REF_25M_CLK_EN); - // 240M CLK is for Key Management use, should not be gated #if !CONFIG_ESP_ENABLE_PVT - REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN); + clk_gate_config.disable_pvt_clk = true; #endif - // 160M CLK is for PVT use, should not be gated - REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_120M_CLK_EN); - REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_80M_CLK_EN); - REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_20M_CLK_EN); - } - - // LP related clock control - if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) \ - || (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_BROWN_OUT)) { - // lpperi,lp peripheral registers get reset for reset level equal or higher than system reset - lp_uart_ll_sclk_disable(0); - _lp_uart_ll_enable_bus_clock(0, false); - _rtcio_ll_enable_io_clock(false); - - if (rst_reason == RESET_REASON_CHIP_POWER_ON) { - // lp_aon_clkrst, lp_system registers get reset only if chip reset - _uart_ll_enable_pad_sleep_clock(&UART0, false); - _uart_ll_enable_pad_sleep_clock(&UART1, false); - _uart_ll_enable_pad_sleep_clock(&UART2, false); - _uart_ll_enable_pad_sleep_clock(&UART3, false); - _uart_ll_enable_pad_sleep_clock(&UART4, false); - REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN); - REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN); - REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_I2S2_MCLK_EN); - REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_I2S1_MCLK_EN); - REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_I2S0_MCLK_EN); - REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN); - REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN); - REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN); - REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PLL_8M_CLK_EN); - REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_AUDIO_PLL_CLK_EN); - REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_SDIO_PLL2_CLK_EN); - REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_SDIO_PLL1_CLK_EN); - REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_SDIO_PLL0_CLK_EN); #if !CONFIG_SPIRAM_BOOT_HW_INIT - REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_MPLL_500M_CLK_EN); + clk_gate_config.disable_spiram_boot_clk = true; #endif - REG_CLR_BIT(LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG, LP_SYSTEM_REG_CPU_CLK_EN); - } - } +#if !CONFIG_ESP_SYSTEM_HW_PC_RECORD + clk_gate_config.disable_assist_clk = true; +#endif +#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED + clk_gate_config.disable_usb_serial_jtag = true; +#endif + + periph_ll_clk_gate_set_default(rst_reason, &clk_gate_config); } diff --git a/components/hal/esp32c5/include/hal/clk_gate_ll.h b/components/hal/esp32c5/include/hal/clk_gate_ll.h index 059c0b2e4b..118d3cb8e1 100644 --- a/components/hal/esp32c5/include/hal/clk_gate_ll.h +++ b/components/hal/esp32c5/include/hal/clk_gate_ll.h @@ -13,7 +13,19 @@ extern "C" { #include #include #include "esp_attr.h" +#include "soc/reset_reasons.h" #include "soc/pcr_struct.h" +#include "soc/ahb_dma_struct.h" +#include "soc/lpperi_struct.h" +#include "soc/uart_struct.h" +#include "soc/tee_struct.h" +#include "soc/lp_gpio_struct.h" +#include "soc/lp_tee_struct.h" +#include "soc/lp_apm_struct.h" +#include "soc/lp_apm0_struct.h" +#include "soc/hp_apm_struct.h" +#include "soc/cpu_apm_struct.h" +#include "soc/usb_serial_jtag_struct.h" #include "soc/lp_clkrst_struct.h" /** @@ -136,6 +148,87 @@ FORCE_INLINE_ATTR void _clk_gate_ll_rtc_fast_to_lp_periph_en(bool enable) /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance #define clk_gate_ll_rtc_fast_to_lp_periph_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_rtc_fast_to_lp_periph_en(__VA_ARGS__) +/** + * @brief Configuration structure for peripheral clock gate settings + */ +typedef struct { + bool disable_uart0_clk; ///< Disable UART0 clock (when UART0 is not console) + bool disable_uart1_clk; ///< Disable UART1 clock (when UART1 is not console) + bool disable_mspi_flash_clk; ///< Disable MSPI flash clock (for PURE_RAM_APP) + bool disable_crypto_periph_clk; ///< Disable crypto peripherals clock when TEE is not enabled + bool disable_usb_serial_jtag; ///< Disable USB-Serial-JTAG clock and pad (when not enabled) +} periph_ll_clk_gate_config_t; + +/** + * @brief Set the default clock gate configuration + * @param config The configuration structure + */ +static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason, const periph_ll_clk_gate_config_t *config) +{ + if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) \ + && (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT) \ + && (rst_reason != RESET_REASON_CPU0_JTAG) && (rst_reason != RESET_REASON_CPU0_LOCKUP)) { + if (config->disable_uart0_clk) { + PCR.uart0_conf.uart0_clk_en = 0; + PCR.uart0_sclk_conf.uart0_sclk_en = 0; + } + + else if (config->disable_uart1_clk) { + PCR.uart1_sclk_conf.uart1_sclk_en = 0; + PCR.uart1_conf.uart1_clk_en = 0; + } + + PCR.timergroup_xtal_conf.tg0_xtal_clk_en = 0; + PCR.timergroup0_timer_clk_conf.tg0_timer_clk_en = 0; + PCR.timergroup1_timer_clk_conf.tg1_timer_clk_en = 0; + PCR.timergroup0_conf.tg0_clk_en = 0; + PCR.timergroup1_conf.tg1_clk_en = 0; + PCR.gdma_conf.gdma_clk_en = 0; + + if (config->disable_mspi_flash_clk) { + PCR.mspi_conf.mspi_clk_en = 0; + } + + PCR.spi2_conf.spi2_clk_en = 0; + + if (config->disable_crypto_periph_clk) { + TEE.clock_gate.clk_en = 0; + LP_TEE.clock_gate.clk_en = 0; + HP_APM.clock_gate.clk_en = 0; + CPU_APM.clock_gate.clk_en = 0; + } + + PCR.uhci_conf.uhci_clk_en = 0; + PCR.tcm_mem_monitor_conf.tcm_mem_monitor_clk_en = 0; + PCR.psram_mem_monitor_conf.psram_mem_monitor_clk_en = 0; + PCR.ctrl_clk_out_en.val = 0; + + if (config->disable_usb_serial_jtag) { + // Disable USB-Serial-JTAG clock and it's pad if not used + USB_SERIAL_JTAG.conf0.usb_pad_enable = 0; + PCR.usb_device_conf.usb_device_clk_en = 0; + USB_SERIAL_JTAG.mem_conf.usb_mem_clk_en = 0; + USB_SERIAL_JTAG.mem_conf.usb_mem_pd = 1; + } + } + + if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \ + || (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) \ + || (rst_reason == RESET_REASON_CORE_PWR_GLITCH)) { + LP_GPIO.clock_gate.clk_en = 0; + LP_UART.clk_conf.val = 0; + LPPERI.clk_en.val = 0; + LPPERI.clk_en.efuse_ck_en = 1; // keep efuse clock enabled + + if (config->disable_crypto_periph_clk) { + LP_APM.clock_gate.clk_en = 0; + LP_APM0.clock_gate.clk_en = 0; + } + + LP_CLKRST.lp_clk_po_en.val = 0; + } +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c6/include/hal/clk_gate_ll.h b/components/hal/esp32c6/include/hal/clk_gate_ll.h index 93cf20c6aa..524c94fe1b 100644 --- a/components/hal/esp32c6/include/hal/clk_gate_ll.h +++ b/components/hal/esp32c6/include/hal/clk_gate_ll.h @@ -9,10 +9,17 @@ #include #include #include "hal/assert.h" -#include "soc/periph_defs.h" -#include "soc/pcr_reg.h" #include "soc/soc.h" #include "soc/soc_caps.h" +#include "soc/reset_reasons.h" +#include "soc/periph_defs.h" +#include "soc/pcr_reg.h" +#include "soc/pcr_struct.h" +#include "soc/gdma_struct.h" +#include "soc/lpperi_struct.h" +#include "soc/lp_uart_struct.h" +#include "soc/uart_struct.h" +#include "soc/usb_serial_jtag_struct.h" #include "esp_attr.h" #include "soc/lp_clkrst_struct.h" @@ -74,20 +81,20 @@ static inline uint32_t periph_ll_get_rst_en_mask(shared_periph_module_t periph, case PERIPH_AES_MODULE: if (enable == true) { // Clear reset on digital signature, otherwise AES unit is held in reset - CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); + PCR.ds_conf.ds_rst_en = 0; } return PCR_AES_RST_EN; case PERIPH_SHA_MODULE: if (enable == true) { // Clear reset on digital signature and HMAC, otherwise SHA is held in reset - CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); - CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); + PCR.ds_conf.ds_rst_en = 0; + PCR.hmac_conf.hmac_rst_en = 0; } return PCR_SHA_RST_EN; case PERIPH_RSA_MODULE: if (enable == true) { // Clear reset on digital signature, otherwise RSA is held in reset - CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); + PCR.ds_conf.ds_rst_en = 0; } return PCR_RSA_RST_EN; case PERIPH_HMAC_MODULE: @@ -207,6 +214,114 @@ FORCE_INLINE_ATTR void _clk_gate_ll_rtc_fast_to_lp_periph_en(bool enable) /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance #define clk_gate_ll_rtc_fast_to_lp_periph_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_rtc_fast_to_lp_periph_en(__VA_ARGS__) +/** + * @brief Configuration structure for peripheral clock gate settings + */ +typedef struct { + bool disable_uart0_clk; ///< Disable UART0 clock + bool disable_uart1_clk; ///< Disable UART1 clock + bool disable_mspi_flash_clk; ///< Disable MSPI flash clock + bool disable_assist_clk; ///< Disable ASSIST Debug module clock + bool disable_crypto_periph_clk; ///< Disable crypto peripherals clock + bool disable_usb_serial_jtag; ///< Disable USB-Serial-JTAG clock +} periph_ll_clk_gate_config_t; + +/** + * @brief Set the default clock gate configuration + * @param config The configuration structure + */ +static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason, const periph_ll_clk_gate_config_t *config) +{ + if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) \ + && (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT) \ + && (rst_reason != RESET_REASON_CPU0_JTAG)) { + + if (config->disable_uart0_clk) { + PCR.uart0_conf.uart0_clk_en = 0; + PCR.uart0_sclk_conf.uart0_sclk_en = 0; + } + + else if (config->disable_uart1_clk) { + PCR.uart1_sclk_conf.uart1_sclk_en = 0; + PCR.uart1_conf.uart1_clk_en = 0; + } + + PCR.i2c_conf.i2c_clk_en = 0; + PCR.i2c_sclk_conf.i2c_sclk_en = 0; + PCR.rmt_conf.rmt_clk_en = 0; + PCR.rmt_sclk_conf.rmt_sclk_en = 0; + PCR.ledc_sclk_conf.ledc_sclk_en = 0; + PCR.ledc_conf.ledc_clk_en = 0; + PCR.timergroup0_timer_clk_conf.tg0_timer_clk_en = 0; + PCR.timergroup1_timer_clk_conf.tg1_timer_clk_en = 0; + PCR.timergroup0_conf.tg0_clk_en = 0; + PCR.timergroup1_conf.tg1_clk_en = 0; + PCR.twai0_func_clk_conf.twai0_func_clk_en = 0; + PCR.twai0_conf.twai0_clk_en = 0; + PCR.twai1_func_clk_conf.twai1_func_clk_en = 0; + PCR.twai1_conf.twai1_clk_en = 0; + PCR.i2s_conf.i2s_clk_en = 0; + PCR.i2s_tx_clkm_conf.i2s_tx_clkm_en = 0; + PCR.i2s_rx_clkm_conf.i2s_rx_clkm_en = 0; + PCR.pcnt_conf.pcnt_clk_en = 0; + PCR.etm_conf.etm_clk_en = 0; + PCR.pwm_conf.pwm_clk_en = 0; + PCR.pwm_clk_conf.pwm_clkm_en = 0; + PCR.parl_clk_rx_conf.parl_clk_rx_en = 0; + PCR.parl_clk_tx_conf.parl_clk_tx_en = 0; + PCR.parl_io_conf.parl_clk_en = 0; + PCR.gdma_conf.gdma_clk_en = 0; + + if (config->disable_mspi_flash_clk) { + PCR.mspi_conf.mspi_clk_en = 0; + } + + PCR.spi2_conf.spi2_clk_en = 0; + PCR.tsens_clk_conf.tsens_clk_en = 0; + + PCR.uhci_conf.uhci_clk_en = 0; + PCR.saradc_conf.saradc_clk_en = 0; + PCR.sdio_slave_conf.sdio_slave_clk_en = 0; + + if (config->disable_assist_clk) { + /* Disable ASSIST Debug module clock if PC recoreding function is not used, + * if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */ + PCR.assist_conf.assist_clk_en = 0; + } + + if (config->disable_crypto_periph_clk) { + // NOTE: [ESP-TEE] The TEE is responsible for the AES and SHA peripherals + PCR.aes_conf.aes_clk_en = 0; + PCR.sha_conf.sha_clk_en = 0; + PCR.hmac_conf.hmac_clk_en = 0; + PCR.ds_conf.ds_clk_en = 0; + PCR.ecc_conf.ecc_clk_en = 0; + PCR.rsa_conf.rsa_clk_en = 0; + } + + PCR.ctrl_tick_conf.tick_enable = 0; + PCR.trace_conf.trace_clk_en = 0; + PCR.mem_monitor_conf.mem_monitor_clk_en = 0; + PCR.pvt_monitor_conf.pvt_monitor_clk_en = 0; + PCR.pvt_monitor_func_clk_conf.pvt_monitor_func_clk_en = 0; + PCR.ctrl_clk_out_en.val = 0; + + if (config->disable_usb_serial_jtag) { + // Disable USB-Serial-JTAG clock and it's pad if not used + USB_SERIAL_JTAG.conf0.usb_pad_enable = 0; + PCR.usb_device_conf.usb_device_clk_en = 0; + } + } + + if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \ + || (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)) { + LP_CLKRST.lp_clk_po_en.val = 0; + LPPERI.clk_en.val = 0; + LPPERI.clk_en.efuse_ck_en = 1; // keep efuse clock enabled + LP_UART.clk_conf.val = 0; + } +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/clk_gate_ll.h b/components/hal/esp32h2/include/hal/clk_gate_ll.h index 608c0a5803..ee999faed3 100644 --- a/components/hal/esp32h2/include/hal/clk_gate_ll.h +++ b/components/hal/esp32h2/include/hal/clk_gate_ll.h @@ -14,6 +14,13 @@ #include "soc/pcr_reg.h" #include "soc/soc.h" #include "soc/soc_caps.h" +#include "soc/reset_reasons.h" +#include "soc/pcr_struct.h" +#include "soc/gdma_struct.h" +#include "soc/parl_io_struct.h" +#include "soc/lpperi_struct.h" +#include "soc/usb_serial_jtag_struct.h" +#include "soc/lp_clkrst_struct.h" #ifdef __cplusplus extern "C" { @@ -224,6 +231,103 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void) // DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); } +/** + * @brief Configuration structure for peripheral clock gate settings + */ +typedef struct { + bool disable_uart0_clk; ///< Disable UART0 clock + bool disable_uart1_clk; ///< Disable UART1 clock + bool disable_mspi_flash_clk; ///< Disable MSPI flash clock + bool disable_assist_clk; ///< Disable ASSIST Debug module clock + bool disable_crypto_periph_clk; ///< Disable crypto peripherals clock + bool disable_usb_serial_jtag; ///< Disable USB-Serial-JTAG clock +} periph_ll_clk_gate_config_t; + +static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason, const periph_ll_clk_gate_config_t *config) +{ + if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) \ + && (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT) \ + && (rst_reason != RESET_REASON_CPU0_JTAG)) { + if (config->disable_uart0_clk) { + PCR.uart0_conf.uart0_clk_en = 0; + } + else if (config->disable_uart1_clk) { + PCR.uart1_conf.uart1_clk_en = 0; + } + + PCR.i2c[0].i2c_conf.i2c_clk_en = 0; + PCR.i2c[1].i2c_conf.i2c_clk_en = 0; + PCR.i2c[0].i2c_sclk_conf.i2c_sclk_en = 0; + PCR.i2c[1].i2c_sclk_conf.i2c_sclk_en = 0; + PCR.rmt_conf.rmt_clk_en = 0; + PCR.rmt_sclk_conf.rmt_sclk_en = 0; + PCR.ledc_sclk_conf.ledc_sclk_en = 0; + PCR.ledc_conf.ledc_clk_en = 0; + PCR.timergroup0_timer_clk_conf.tg0_timer_clk_en = 0; + PCR.timergroup1_timer_clk_conf.tg1_timer_clk_en = 0; + PCR.timergroup0_conf.tg0_clk_en = 0; + PCR.timergroup1_conf.tg1_clk_en = 0; + PCR.twai0_func_clk_conf.twai0_func_clk_en = 0; + PCR.twai0_conf.twai0_clk_en = 0; + PCR.i2s_conf.i2s_clk_en = 0; + PCR.i2s_tx_clkm_conf.i2s_tx_clkm_en = 0; + PCR.i2s_rx_clkm_conf.i2s_rx_clkm_en = 0; + PCR.pcnt_conf.pcnt_clk_en = 0; + PCR.etm_conf.etm_clk_en = 0; + PCR.pwm_conf.pwm_clk_en = 0; + PCR.pwm_clk_conf.pwm_clkm_en = 0; + PCR.parl_io_conf.parl_clk_en = 0; + PCR.gdma_conf.gdma_clk_en = 0; + + if (config->disable_mspi_flash_clk) { + PCR.mspi_conf.mspi_clk_en = 0; + } + + PCR.spi2_conf.spi2_clk_en = 0; + PCR.tsens_clk_conf.tsens_clk_en = 0; + + PCR.uhci_conf.uhci_clk_en = 0; + PCR.saradc_conf.saradc_clk_en = 0; + + if (config->disable_assist_clk) { + /* Disable ASSIST Debug module clock if PC recoreding function is not used, + * if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */ + PCR.assist_conf.assist_clk_en = 0; + } + + if (config->disable_crypto_periph_clk) { + // NOTE: [ESP-TEE] The TEE is responsible for the AES and SHA peripherals + PCR.aes_conf.aes_clk_en = 0; + PCR.sha_conf.sha_clk_en = 0; + PCR.ecc_conf.ecc_clk_en = 0; + PCR.hmac_conf.hmac_clk_en = 0; + PCR.ds_conf.ds_clk_en = 0; + PCR.rsa_conf.rsa_clk_en = 0; + PCR.ecdsa_conf.ecdsa_clk_en = 0; + } + + PCR.ctrl_tick_conf.tick_enable = 0; + PCR.trace_conf.trace_clk_en = 0; + PCR.mem_monitor_conf.mem_monitor_clk_en = 0; + PCR.pvt_monitor_conf.pvt_monitor_clk_en = 0; + PCR.pvt_monitor_func_clk_conf.pvt_monitor_func_clk_en = 0; + PCR.ctrl_clk_out_en.val = 0; + + if (config->disable_usb_serial_jtag) { + // Disable USB-Serial-JTAG clock and it's pad if not used + USB_SERIAL_JTAG.conf0.usb_pad_enable = 0; + PCR.usb_device_conf.usb_device_clk_en = 0; + } + } + + if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \ + || (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)) { + LPPERI_REG_SET(clk_en.val, 0); + LPPERI_REG_SET(clk_en.efuse_ck_en, 1); // keep efuse clock enabled + LP_CLKRST.lp_clk_po_en.val = 0; + } +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32p4/include/hal/apm_ll.h b/components/hal/esp32p4/include/hal/apm_ll.h index 9757e44b7c..a97776f87b 100644 --- a/components/hal/esp32p4/include/hal/apm_ll.h +++ b/components/hal/esp32p4/include/hal/apm_ll.h @@ -86,7 +86,7 @@ typedef enum { PMS_COREn_XM_HP_ISP_ALLOW, PMS_COREn_XM_HP_H264_CORE_ALLOW, PMS_COREn_XM_HP_RMT_ALLOW, - PMS_COREn_XM_HP_BITSRAMBLER_ALLOW, + PMS_COREn_XM_HP_BITSCRAMBLER_ALLOW, PMS_COREn_XM_HP_AXI_ICM_ALLOW, PMS_COREn_XM_HP_PERI_PMS_ALLOW, PMS_COREn_XM_LP2HP_PERI_PMS_ALLOW, diff --git a/components/hal/esp32p4/include/hal/clk_gate_ll.h b/components/hal/esp32p4/include/hal/clk_gate_ll.h index b55a76bf32..feb8948d3b 100644 --- a/components/hal/esp32p4/include/hal/clk_gate_ll.h +++ b/components/hal/esp32p4/include/hal/clk_gate_ll.h @@ -13,8 +13,24 @@ extern "C" { #include #include #include "esp_attr.h" +#include "soc/soc.h" +#include "soc/reset_reasons.h" #include "soc/hp_sys_clkrst_struct.h" +#include "soc/hp_sys_clkrst_reg.h" #include "soc/lp_clkrst_struct.h" +#include "soc/lp_clkrst_reg.h" +#include "soc/lp_system_reg.h" +#include "soc/mipi_dsi_bridge_reg.h" +#include "soc/sdmmc_reg.h" +#include "soc/spi_mem_c_reg.h" +#include "soc/spi_mem_s_reg.h" +#include "soc/assist_debug_reg.h" +#include "soc/trace_reg.h" +#include "soc/usb_serial_jtag_reg.h" +#include "soc/lp_uart_reg.h" +#include "soc/lp_gpio_reg.h" +#include "soc/lpperi_reg.h" +#include "soc/uart_reg.h" /** * Enable or disable the clock gate for ref_20m. @@ -152,6 +168,224 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_50m_clk_en(bool enable) } while(0) +/** + * @brief Configuration structure for peripheral clock gate settings + */ +typedef struct { + bool disable_uart0_clk; ///< Disable UART0 clock + bool disable_uart1_clk; ///< Disable UART1 clock + bool disable_mspi_flash_clk; ///< Disable MSPI flash clock + bool disable_mspi_flash_timing_clk; ///< Disable MSPI flash timing calibration clock + bool disable_mspi_psram_timing_clk; ///< Disable MSPI PSRAM timing calibration clock + bool disable_mspi_psram_clk; ///< Disable MSPI PSRAM clock + bool disable_pvt_clk; ///< Disable PVT monitor clock + bool disable_spiram_boot_clk; ///< Disable SPI RAM boot clock + bool disable_assist_clk; ///< Disable ASSIST Debug module clock + bool disable_usb_serial_jtag; ///< Disable USB-Serial-JTAG clock +} periph_ll_clk_gate_config_t; + +/** + * @brief Set the default clock gate configuration + * @param config The configuration structure + */ +static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason, const periph_ll_clk_gate_config_t *config) +{ + if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CORE_PMU_PWR_DOWN) || + (rst_reason == RESET_REASON_SYS_BROWN_OUT) || (rst_reason == RESET_REASON_SYS_RWDT) || + (rst_reason == RESET_REASON_SYS_SUPER_WDT) || (rst_reason == RESET_REASON_CORE_SW) || + (rst_reason == RESET_REASON_CORE_MWDT) || (rst_reason == RESET_REASON_CORE_RWDT) || + (rst_reason == RESET_REASON_CORE_PWR_GLITCH) || (rst_reason == RESET_REASON_CORE_EFUSE_CRC) || + (rst_reason == RESET_REASON_CORE_USB_JTAG) || (rst_reason == RESET_REASON_CORE_USB_UART) + ) { + // Not gate HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON since the hardware will not automatically ungate when DMA accesses L2 MEM. + REG_CLR_BIT(HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG, + HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON); + REG_CLR_BIT(HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG, + HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON); + + // hp_sys_clkrst register gets reset only if chip reset or pmu powers down hp + // but at core reset and above, we will also disable HP modules' clock gating to save power consumption + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, + HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN | + HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN | + HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN | + HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN | + HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN | + HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN); + // HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN, HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN default to 0, removed + // HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN, HP_SYS_CLKRST_REG_ETM_APB_CLK_EN default to 0, removed + + // Non-Console UART + if (config->disable_uart0_clk) { + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_UART0_APB_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL110_REG, HP_SYS_CLKRST_REG_UART0_CLK_EN); + } else if (config->disable_uart1_clk) { + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_UART1_APB_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL111_REG, HP_SYS_CLKRST_REG_UART1_CLK_EN); + } + + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_UART2_APB_CLK_EN | + HP_SYS_CLKRST_REG_UART3_APB_CLK_EN | + HP_SYS_CLKRST_REG_UART4_APB_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN | + HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN | + HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL112_REG, HP_SYS_CLKRST_REG_UART2_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL113_REG, HP_SYS_CLKRST_REG_UART3_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL114_REG, HP_SYS_CLKRST_REG_UART4_CLK_EN); + + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN | + HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL20_REG, HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN | + HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL21_REG, HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN | + HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN); + + REG_CLR_BIT(DSI_BRG_HOST_CTRL_REG, DSI_BRG_DSI_CFG_REF_CLK_EN); + REG_CLR_BIT(SDHOST_CLK_EDGE_SEL_REG, SDHOST_CCLK_EN); + + // Disable MSPI flash clock + if (config->disable_mspi_flash_clk) { + REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL00_REG, HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN | + HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN); + } + + // Disable flash timing calibration clock + if (config->disable_mspi_flash_timing_clk) { + REG_CLR_BIT(SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CLK_ENA); + REG_CLR_BIT(SPI_MEM_C_SMEM_TIMING_CALI_REG, SPI_MEM_C_SMEM_TIMING_CLK_ENA); + } + + // Disable PSRAM timing calibration clock + if (config->disable_mspi_psram_timing_clk) { + REG_CLR_BIT(SPI_MEM_S_TIMING_CALI_REG, SPI_MEM_S_TIMING_CLK_ENA); + REG_CLR_BIT(SPI_MEM_S_SMEM_TIMING_CALI_REG, SPI_MEM_S_SMEM_TIMING_CLK_ENA); + } + + // Disable PSRAM clock + if (config->disable_mspi_psram_clk) { + REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL00_REG, HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN | + HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN); + } + + // Disable GP SPI2 and SPI3 clock + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN | + HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN); + // HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN defaults to 0, removed + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN | + HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL116_REG, HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN | + HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN | + HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL117_REG, HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN); + + if (config->disable_assist_clk) { + /* Disable ASSIST Debug module clock if PC recoreding function is not used, + * if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */ + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN); + REG_CLR_BIT(ASSIST_DEBUG_CLOCK_GATE_REG, ASSIST_DEBUG_CLK_EN); + } + + // Trace & Bus Monitor (0) + REG_CLR_BIT(TRACE_CLOCK_GATE_REG(0), TRACE_CLK_EN); + REG_CLR_BIT(TRACE_CLOCK_GATE_REG(1), TRACE_CLK_EN); + + // Crypto Modules + REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL25_REG, HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN | + HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN | + HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN | + HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN | + HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN | + HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN); + + // USB1.1 + REG_CLR_BIT(LP_CLKRST_HP_USB_CLKRST_CTRL0_REG, LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN | + LP_CLKRST_USB_OTG11_48M_CLK_EN | + LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN | + HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN | + HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN); + // USB2.0 + REG_CLR_BIT(LP_CLKRST_HP_USB_CLKRST_CTRL1_REG, LP_CLKRST_USB_OTG20_PHYREF_CLK_EN | + LP_CLKRST_USB_OTG20_ULPI_CLK_EN); + // UHCI + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN); + + if (config->disable_usb_serial_jtag) { + // Disable USB-Serial-JTAG clock and it's pad if not used + REG_CLR_BIT(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_USB_CLKRST_CTRL0_REG, LP_CLKRST_USB_DEVICE_48M_CLK_EN); + REG_SET_BIT(USB_SERIAL_JTAG_MEM_CONF_REG, USB_SERIAL_JTAG_USB_MEM_PD); + REG_CLR_BIT(USB_SERIAL_JTAG_MEM_CONF_REG, USB_SERIAL_JTAG_USB_MEM_CLK_EN); + } + } + + // HP modules' clock source gating control + if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CORE_PMU_PWR_DOWN)) { + // Only safe to disable these clock source gatings if all HP modules clock configurations has been reset + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_REF_50M_CLK_EN | + HP_SYS_CLKRST_REG_REF_25M_CLK_EN); + // 240M CLK is for Key Management use, should not be gated + if (config->disable_pvt_clk) { + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN); + } + // 160M CLK is for PVT use, should not be gated + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_120M_CLK_EN | + HP_SYS_CLKRST_REG_REF_80M_CLK_EN | + HP_SYS_CLKRST_REG_REF_20M_CLK_EN); + } + + // LP related clock control + if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) \ + || (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_BROWN_OUT)) { + // lpperi,lp peripheral registers get reset for reset level equal or higher than system reset + REG_CLR_BIT(LP_UART_CLK_CONF_REG, LP_UART_TX_SCLK_EN | LP_UART_RX_SCLK_EN); + REG_CLR_BIT(LPPERI_CLK_EN_REG, LPPERI_CK_EN_LP_UART); + REG_CLR_BIT(LP_GPIO_CLK_EN_REG, LP_GPIO_REG_CLK_EN); + while (REG_GET_BIT(LP_GPIO_CLK_EN_REG, LP_GPIO_REG_CLK_EN) != 0) { + ; + } + + if (rst_reason == RESET_REASON_CHIP_POWER_ON) { + // lp_aon_clkrst, lp_system registers get reset only if chip reset + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN | + LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN | + LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN | + LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN | + LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN | + LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN | + LP_CLKRST_HP_PAD_I2S2_MCLK_EN | + LP_CLKRST_HP_PAD_I2S1_MCLK_EN | + LP_CLKRST_HP_PAD_I2S0_MCLK_EN | + LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN | + LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN | + LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN | + LP_CLKRST_HP_PLL_8M_CLK_EN | + LP_CLKRST_HP_AUDIO_PLL_CLK_EN | + LP_CLKRST_HP_SDIO_PLL2_CLK_EN | + LP_CLKRST_HP_SDIO_PLL1_CLK_EN | + LP_CLKRST_HP_SDIO_PLL0_CLK_EN); + if (config->disable_spiram_boot_clk) { + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_MPLL_500M_CLK_EN); + } + REG_CLR_BIT(LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG, LP_SYSTEM_REG_CPU_CLK_EN); + } + } + +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32p4/include/hal/uart_ll.h b/components/hal/esp32p4/include/hal/uart_ll.h index 8fbad650a5..08b0155e57 100644 --- a/components/hal/esp32p4/include/hal/uart_ll.h +++ b/components/hal/esp32p4/include/hal/uart_ll.h @@ -1179,15 +1179,15 @@ FORCE_INLINE_ATTR void uart_ll_set_char_seq_wk_char(uart_dev_t *hw, uint32_t cha FORCE_INLINE_ATTR void _uart_ll_enable_pad_sleep_clock(uart_dev_t *hw, bool enable) { if (hw == &UART0) { - LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart0_slp_clk_en = 1; + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart0_slp_clk_en = enable; } else if (hw == &UART1) { - LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart1_slp_clk_en = 1; + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart1_slp_clk_en = enable; } else if (hw == &UART2) { - LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart2_slp_clk_en = 1; + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart2_slp_clk_en = enable; } else if (hw == &UART3) { - LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart3_slp_clk_en = 1; + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart3_slp_clk_en = enable; } else if (hw == &UART4) { - LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart4_slp_clk_en = 1; + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart4_slp_clk_en = enable; } } diff --git a/components/soc/esp32c5/register/soc/lp_apm0_struct.h b/components/soc/esp32c5/register/soc/lp_apm0_struct.h index 9985d10bed..b3a595aaec 100644 --- a/components/soc/esp32c5/register/soc/lp_apm0_struct.h +++ b/components/soc/esp32c5/register/soc/lp_apm0_struct.h @@ -282,6 +282,7 @@ typedef struct { volatile lp_apm0_date_reg_t date; } lp_apm0_dev_t; +extern lp_apm0_dev_t LP_APM0; #ifndef __cplusplus _Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure"); diff --git a/components/soc/esp32h4/register/soc/trace_reg.h b/components/soc/esp32h4/register/soc/trace_reg.h index aa2cd3d783..41828a46da 100644 --- a/components/soc/esp32h4/register/soc/trace_reg.h +++ b/components/soc/esp32h4/register/soc/trace_reg.h @@ -11,10 +11,12 @@ extern "C" { #endif +#define REG_TRACE_BASE(i) (DR_REG_TRACE0_BASE + (i) * 0x1000) + /** TRACE_MEM_START_ADDR_REG register * Memory start address */ -#define TRACE_MEM_START_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x0) +#define TRACE_MEM_START_ADDR_REG(i) (REG_TRACE_BASE(i) + 0x0) /** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; * Configures the start address of the trace memory */ @@ -26,7 +28,7 @@ extern "C" { /** TRACE_MEM_END_ADDR_REG register * Memory end address */ -#define TRACE_MEM_END_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x4) +#define TRACE_MEM_END_ADDR_REG(i) (REG_TRACE_BASE(i) + 0x4) /** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; * Configures the end address of the trace memory. */ @@ -38,7 +40,7 @@ extern "C" { /** TRACE_MEM_CURRENT_ADDR_REG register * Memory current addr */ -#define TRACE_MEM_CURRENT_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x8) +#define TRACE_MEM_CURRENT_ADDR_REG(i) (REG_TRACE_BASE(i) + 0x8) /** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; * Represents the current memory address for writing. */ @@ -50,7 +52,7 @@ extern "C" { /** TRACE_MEM_ADDR_UPDATE_REG register * Memory address update */ -#define TRACE_MEM_ADDR_UPDATE_REG(i) (DR_REG_TRACE_BASE(i) + 0xc) +#define TRACE_MEM_ADDR_UPDATE_REG(i) (REG_TRACE_BASE(i) + 0xc) /** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0; * Configures whether to update the value of * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} to @@ -66,7 +68,7 @@ extern "C" { /** TRACE_FIFO_STATUS_REG register * FIFO status register */ -#define TRACE_FIFO_STATUS_REG(i) (DR_REG_TRACE_BASE(i) + 0x10) +#define TRACE_FIFO_STATUS_REG(i) (REG_TRACE_BASE(i) + 0x10) /** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1; * Represent whether the FIFO is empty. * 1: Empty @@ -91,7 +93,7 @@ extern "C" { /** TRACE_INTR_ENA_REG register * Interrupt enable register */ -#define TRACE_INTR_ENA_REG(i) (DR_REG_TRACE_BASE(i) + 0x14) +#define TRACE_INTR_ENA_REG(i) (REG_TRACE_BASE(i) + 0x14) /** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0; * Write 1 to enable TRACE_FIFO_OVERFLOW_INTR */ @@ -110,7 +112,7 @@ extern "C" { /** TRACE_INTR_RAW_REG register * Interrupt raw status register */ -#define TRACE_INTR_RAW_REG(i) (DR_REG_TRACE_BASE(i) + 0x18) +#define TRACE_INTR_RAW_REG(i) (REG_TRACE_BASE(i) + 0x18) /** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0; * The raw interrupt status of TRACE_FIFO_OVERFLOW_INTR. */ @@ -129,7 +131,7 @@ extern "C" { /** TRACE_INTR_CLR_REG register * Interrupt clear register */ -#define TRACE_INTR_CLR_REG(i) (DR_REG_TRACE_BASE(i) + 0x1c) +#define TRACE_INTR_CLR_REG(i) (REG_TRACE_BASE(i) + 0x1c) /** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0; * Write 1 to clear TRACE_FIFO_OVERFLOW_INTR */ @@ -148,7 +150,7 @@ extern "C" { /** TRACE_TRIGGER_REG register * Trace enable register */ -#define TRACE_TRIGGER_REG(i) (DR_REG_TRACE_BASE(i) + 0x20) +#define TRACE_TRIGGER_REG(i) (REG_TRACE_BASE(i) + 0x20) /** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0; * Configure whether to enable the encoder. * 0: Invalid @@ -189,7 +191,7 @@ extern "C" { /** TRACE_CONFIG_REG register * trace configuration register */ -#define TRACE_CONFIG_REG(i) (DR_REG_TRACE_BASE(i) + 0x24) +#define TRACE_CONFIG_REG(i) (REG_TRACE_BASE(i) + 0x24) /** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0; * Configure whether to enable the trigger signal. * 0: Disable @@ -251,7 +253,7 @@ extern "C" { /** TRACE_FILTER_CONTROL_REG register * filter control register */ -#define TRACE_FILTER_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x28) +#define TRACE_FILTER_CONTROL_REG(i) (REG_TRACE_BASE(i) + 0x28) /** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0; * Configure whether to enable filtering. * 0: Disable, always match. @@ -306,7 +308,7 @@ extern "C" { /** TRACE_FILTER_MATCH_CONTROL_REG register * filter match control register */ -#define TRACE_FILTER_MATCH_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x2c) +#define TRACE_FILTER_MATCH_CONTROL_REG(i) (REG_TRACE_BASE(i) + 0x2c) /** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0; * Configures the privilege level for matching. Valid only when * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. @@ -338,7 +340,7 @@ extern "C" { /** TRACE_FILTER_COMPARATOR_CONTROL_REG register * filter comparator match control register */ -#define TRACE_FILTER_COMPARATOR_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x30) +#define TRACE_FILTER_COMPARATOR_CONTROL_REG(i) (REG_TRACE_BASE(i) + 0x30) /** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0; * Configures the input of the primary comparator for matching: * 0: iaddr @@ -419,7 +421,7 @@ extern "C" { /** TRACE_FILTER_P_COMPARATOR_MATCH_REG register * primary comparator match value */ -#define TRACE_FILTER_P_COMPARATOR_MATCH_REG(i) (DR_REG_TRACE_BASE(i) + 0x34) +#define TRACE_FILTER_P_COMPARATOR_MATCH_REG(i) (REG_TRACE_BASE(i) + 0x34) /** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0; * Configures the match value for the primary comparator */ @@ -431,7 +433,7 @@ extern "C" { /** TRACE_FILTER_S_COMPARATOR_MATCH_REG register * secondary comparator match value */ -#define TRACE_FILTER_S_COMPARATOR_MATCH_REG(i) (DR_REG_TRACE_BASE(i) + 0x38) +#define TRACE_FILTER_S_COMPARATOR_MATCH_REG(i) (REG_TRACE_BASE(i) + 0x38) /** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0; * Configures the match value for the secondary comparator */ @@ -443,7 +445,7 @@ extern "C" { /** TRACE_RESYNC_PROLONGED_REG register * Resync configuration register */ -#define TRACE_RESYNC_PROLONGED_REG(i) (DR_REG_TRACE_BASE(i) + 0x3c) +#define TRACE_RESYNC_PROLONGED_REG(i) (REG_TRACE_BASE(i) + 0x3c) /** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128; * Configures the threshold for synchronization counter */ @@ -466,7 +468,7 @@ extern "C" { /** TRACE_AHB_CONFIG_REG register * AHB config register */ -#define TRACE_AHB_CONFIG_REG(i) (DR_REG_TRACE_BASE(i) + 0x40) +#define TRACE_AHB_CONFIG_REG(i) (REG_TRACE_BASE(i) + 0x40) /** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0; * Configures the AHB burst mode. * 0: SINGLE @@ -490,7 +492,7 @@ extern "C" { /** TRACE_CLOCK_GATE_REG register * Clock gate control register */ -#define TRACE_CLOCK_GATE_REG(i) (DR_REG_TRACE_BASE(i) + 0x44) +#define TRACE_CLOCK_GATE_REG(i) (REG_TRACE_BASE(i) + 0x44) /** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures register clock gating. * 0: Support clock only when the application writes registers to save power. @@ -505,7 +507,7 @@ extern "C" { /** TRACE_DATE_REG register * Version control register */ -#define TRACE_DATE_REG(i) (DR_REG_TRACE_BASE(i) + 0x3fc) +#define TRACE_DATE_REG(i) (REG_TRACE_BASE(i) + 0x3fc) /** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984; * Version control register. */ diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h index 920b9bfa1c..0a47f86f2a 100644 --- a/components/soc/esp32p4/include/soc/soc.h +++ b/components/soc/esp32p4/include/soc/soc.h @@ -24,7 +24,6 @@ #define REG_I2C_BASE(i) (DR_REG_I2C0_BASE + (i) * 0x1000) #define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE + (i) * 0x1000) #define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x1000) // TWAI0 and TWAI1 -#define REG_TRACE_BASE(i) (DR_REG_TRACE_BASE + (i) * 0x1000) //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld index 693f41688a..be4afeba32 100644 --- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld +++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld @@ -126,3 +126,4 @@ PROVIDE ( EMAC_DMA = 0x50099000 ); PROVIDE ( CACHE = 0x3FF10000); PROVIDE ( TRACE0 = 0x3FF04000); PROVIDE ( TRACE1 = 0x3FF05000); +PROVIDE ( ASSIST_DEBUG = 0x3FF06000); diff --git a/components/soc/esp32p4/register/hw_ver1/soc/assist_debug_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/assist_debug_struct.h index 429bc986ca..225efd75f5 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/assist_debug_struct.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/assist_debug_struct.h @@ -1306,6 +1306,7 @@ typedef struct { volatile assist_debug_date_reg_t date; } assist_debug_dev_t; +extern assist_debug_dev_t ASSIST_DEBUG; #ifndef __cplusplus _Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure"); diff --git a/components/soc/esp32p4/register/hw_ver1/soc/hp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/hp_peri_pms_reg.h index 53109b176c..63fb1009b7 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/hp_peri_pms_reg.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/hp_peri_pms_reg.h @@ -350,16 +350,16 @@ extern "C" { #define PMS_CORE0_MM_HP_RMT_ALLOW_M (PMS_CORE0_MM_HP_RMT_ALLOW_V << PMS_CORE0_MM_HP_RMT_ALLOW_S) #define PMS_CORE0_MM_HP_RMT_ALLOW_V 0x00000001U #define PMS_CORE0_MM_HP_RMT_ALLOW_S 22 -/** PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** PMS_CORE0_MM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * Configures whether HP CPU0 in machine mode has permission to access HP bit * scrambler. * 0: Not allowed * 1: Allowed */ -#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_M (PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_S) -#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_S 23 +#define PMS_CORE0_MM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define PMS_CORE0_MM_HP_BITSCRAMBLER_ALLOW_M (PMS_CORE0_MM_HP_BITSCRAMBLER_ALLOW_V << PMS_CORE0_MM_HP_BITSCRAMBLER_ALLOW_S) +#define PMS_CORE0_MM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define PMS_CORE0_MM_HP_BITSCRAMBLER_ALLOW_S 23 /** PMS_CORE0_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * Configures whether HP CPU0 in machine mode has permission to access HP AXI ICM. * 0: Not allowed @@ -1050,15 +1050,15 @@ extern "C" { #define PMS_CORE0_UM_HP_RMT_ALLOW_M (PMS_CORE0_UM_HP_RMT_ALLOW_V << PMS_CORE0_UM_HP_RMT_ALLOW_S) #define PMS_CORE0_UM_HP_RMT_ALLOW_V 0x00000001U #define PMS_CORE0_UM_HP_RMT_ALLOW_S 22 -/** PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** PMS_CORE0_UM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * Configures whether HP CPU0 in user mode has permission to access HP bit scrambler. * 0: Not allowed * 1: Allowed */ -#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_M (PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_S) -#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_S 23 +#define PMS_CORE0_UM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define PMS_CORE0_UM_HP_BITSCRAMBLER_ALLOW_M (PMS_CORE0_UM_HP_BITSCRAMBLER_ALLOW_V << PMS_CORE0_UM_HP_BITSCRAMBLER_ALLOW_S) +#define PMS_CORE0_UM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define PMS_CORE0_UM_HP_BITSCRAMBLER_ALLOW_S 23 /** PMS_CORE0_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * Configures whether HP CPU0 in user mode has permission to access HP AXI ICM. * 0: Not allowed @@ -1749,16 +1749,16 @@ extern "C" { #define PMS_CORE1_MM_HP_RMT_ALLOW_M (PMS_CORE1_MM_HP_RMT_ALLOW_V << PMS_CORE1_MM_HP_RMT_ALLOW_S) #define PMS_CORE1_MM_HP_RMT_ALLOW_V 0x00000001U #define PMS_CORE1_MM_HP_RMT_ALLOW_S 22 -/** PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** PMS_CORE1_MM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * Configures whether HP CPU1 in machine mode has permission to access HP bit * scrambler. * 0: Not allowed * 1: Allowed */ -#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_M (PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_S) -#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_S 23 +#define PMS_CORE1_MM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define PMS_CORE1_MM_HP_BITSCRAMBLER_ALLOW_M (PMS_CORE1_MM_HP_BITSCRAMBLER_ALLOW_V << PMS_CORE1_MM_HP_BITSCRAMBLER_ALLOW_S) +#define PMS_CORE1_MM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define PMS_CORE1_MM_HP_BITSCRAMBLER_ALLOW_S 23 /** PMS_CORE1_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * Configures whether HP CPU1 in machine mode has permission to access HP AXI ICM. * 0: Not allowed @@ -2449,15 +2449,15 @@ extern "C" { #define PMS_CORE1_UM_HP_RMT_ALLOW_M (PMS_CORE1_UM_HP_RMT_ALLOW_V << PMS_CORE1_UM_HP_RMT_ALLOW_S) #define PMS_CORE1_UM_HP_RMT_ALLOW_V 0x00000001U #define PMS_CORE1_UM_HP_RMT_ALLOW_S 22 -/** PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** PMS_CORE1_UM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * Configures whether HP CPU1 in user mode has permission to access HP bit scrambler. * 0: Not allowed * 1: Allowed */ -#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_M (PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_S) -#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_S 23 +#define PMS_CORE1_UM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define PMS_CORE1_UM_HP_BITSCRAMBLER_ALLOW_M (PMS_CORE1_UM_HP_BITSCRAMBLER_ALLOW_V << PMS_CORE1_UM_HP_BITSCRAMBLER_ALLOW_S) +#define PMS_CORE1_UM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define PMS_CORE1_UM_HP_BITSCRAMBLER_ALLOW_S 23 /** PMS_CORE1_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * Configures whether HP CPU1 in user mode has permission to access HP AXI ICM. * 0: Not allowed diff --git a/components/soc/esp32p4/register/hw_ver1/soc/lp2hp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/lp2hp_peri_pms_reg.h index 91ce65974d..c219a7080b 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/lp2hp_peri_pms_reg.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/lp2hp_peri_pms_reg.h @@ -350,16 +350,16 @@ extern "C" { #define PMS_LP_MM_HP_RMT_ALLOW_M (PMS_LP_MM_HP_RMT_ALLOW_V << PMS_LP_MM_HP_RMT_ALLOW_S) #define PMS_LP_MM_HP_RMT_ALLOW_V 0x00000001U #define PMS_LP_MM_HP_RMT_ALLOW_S 22 -/** PMS_LP_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** PMS_LP_MM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * Configures whether the LP CPU in machine mode has permission to access HP bit * scrambler. * 0: Not allowed * 1: Allowed */ -#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_M (PMS_LP_MM_HP_BITSRAMBLER_ALLOW_V << PMS_LP_MM_HP_BITSRAMBLER_ALLOW_S) -#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_S 23 +#define PMS_LP_MM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define PMS_LP_MM_HP_BITSCRAMBLER_ALLOW_M (PMS_LP_MM_HP_BITSCRAMBLER_ALLOW_V << PMS_LP_MM_HP_BITSCRAMBLER_ALLOW_S) +#define PMS_LP_MM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_BITSCRAMBLER_ALLOW_S 23 /** PMS_LP_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * Configures whether the LP CPU in machine mode has permission to access HP AXI ICM. * 0: Not allowed diff --git a/components/soc/esp32p4/register/hw_ver1/soc/trace_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/trace_reg.h index 09bbb43bac..7623601bd8 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/trace_reg.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/trace_reg.h @@ -11,6 +11,8 @@ extern "C" { #endif +#define REG_TRACE_BASE(i) (DR_REG_TRACE_BASE + (i) * 0x1000) + /** TRACE_MEM_START_ADDR_REG register * mem start addr */ diff --git a/components/soc/esp32p4/register/hw_ver1/soc/usb_serial_jtag_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/usb_serial_jtag_reg.h index 40dc5d9a16..96cc0d97c8 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/usb_serial_jtag_reg.h @@ -17,9 +17,9 @@ extern "C" { #define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) /** USB_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0; * Write and read byte data to/from UART Tx/Rx FIFO through this field. When - * USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) - * into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check - * USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) + * into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check + * USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is * received, then read data from UART Rx FIFO. */ #define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU @@ -40,7 +40,7 @@ extern "C" { #define USB_SERIAL_JTAG_WR_DONE_S 0 /** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing - * USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB + * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB * Host. */ #define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) @@ -186,112 +186,112 @@ extern "C" { */ #define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. */ #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 /** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. */ #define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) #define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) #define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_SOF_INT_ST_S 1 /** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. */ #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 /** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. */ #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 /** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) #define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) #define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 /** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) #define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) #define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 /** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) #define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) #define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 /** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) #define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) #define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 /** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. */ #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 /** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. */ #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 /** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 /** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 /** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. */ #define USB_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) #define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S) #define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 /** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. */ #define USB_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) #define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S) #define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 /** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. */ #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 /** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. */ #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) @@ -303,112 +303,112 @@ extern "C" { */ #define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. */ #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 /** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. */ #define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) #define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) #define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 /** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. */ #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 /** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. */ #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 /** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) #define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) #define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 /** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) #define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) #define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 /** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) #define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) #define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 /** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) #define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) #define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 /** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. */ #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 /** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. */ #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 /** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 /** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 /** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. */ #define USB_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) #define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S) #define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 /** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. */ #define USB_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) #define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S) #define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 /** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; - * The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. */ #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 /** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. */ #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) @@ -420,112 +420,112 @@ extern "C" { */ #define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. */ #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 /** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. */ #define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) #define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) #define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 /** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. */ #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 /** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. */ #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 /** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) #define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) #define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 /** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) #define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) #define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 /** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) #define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) #define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 /** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) #define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) #define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 /** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. */ #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 /** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. */ #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 /** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 /** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 /** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. */ #define USB_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) #define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S) #define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 /** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. */ #define USB_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) #define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S) #define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 /** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; - * Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. */ #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 /** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; - * Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. */ #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) @@ -880,8 +880,8 @@ extern "C" { #define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U #define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 /** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - * detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. */ #define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU #define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) @@ -907,8 +907,8 @@ extern "C" { #define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U #define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 /** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - * detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. */ #define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU #define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) @@ -941,8 +941,8 @@ extern "C" { #define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U #define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 /** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - * detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. */ #define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU #define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_eco5_reg.h index 0ddcf24494..ade1215e6e 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_eco5_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_eco5_reg.h @@ -275,13 +275,13 @@ extern "C" { #define TEE_REG_CORE0_MM_HP_RMT_ALLOW_M (TEE_REG_CORE0_MM_HP_RMT_ALLOW_V << TEE_REG_CORE0_MM_HP_RMT_ALLOW_S) #define TEE_REG_CORE0_MM_HP_RMT_ALLOW_V 0x00000001U #define TEE_REG_CORE0_MM_HP_RMT_ALLOW_S 22 -/** TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** TEE_REG_CORE0_MM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * NA */ -#define TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_M (TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_S) -#define TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_S 23 +#define TEE_REG_CORE0_MM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define TEE_REG_CORE0_MM_HP_BITSCRAMBLER_ALLOW_M (TEE_REG_CORE0_MM_HP_BITSCRAMBLER_ALLOW_V << TEE_REG_CORE0_MM_HP_BITSCRAMBLER_ALLOW_S) +#define TEE_REG_CORE0_MM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define TEE_REG_CORE0_MM_HP_BITSCRAMBLER_ALLOW_S 23 /** TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * NA */ @@ -820,13 +820,13 @@ extern "C" { #define TEE_REG_CORE0_UM_HP_RMT_ALLOW_M (TEE_REG_CORE0_UM_HP_RMT_ALLOW_V << TEE_REG_CORE0_UM_HP_RMT_ALLOW_S) #define TEE_REG_CORE0_UM_HP_RMT_ALLOW_V 0x00000001U #define TEE_REG_CORE0_UM_HP_RMT_ALLOW_S 22 -/** TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** TEE_REG_CORE0_UM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * NA */ -#define TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_M (TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_S) -#define TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_S 23 +#define TEE_REG_CORE0_UM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define TEE_REG_CORE0_UM_HP_BITSCRAMBLER_ALLOW_M (TEE_REG_CORE0_UM_HP_BITSCRAMBLER_ALLOW_V << TEE_REG_CORE0_UM_HP_BITSCRAMBLER_ALLOW_S) +#define TEE_REG_CORE0_UM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define TEE_REG_CORE0_UM_HP_BITSCRAMBLER_ALLOW_S 23 /** TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * NA */ @@ -1365,13 +1365,13 @@ extern "C" { #define TEE_REG_CORE1_MM_HP_RMT_ALLOW_M (TEE_REG_CORE1_MM_HP_RMT_ALLOW_V << TEE_REG_CORE1_MM_HP_RMT_ALLOW_S) #define TEE_REG_CORE1_MM_HP_RMT_ALLOW_V 0x00000001U #define TEE_REG_CORE1_MM_HP_RMT_ALLOW_S 22 -/** TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** TEE_REG_CORE1_MM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * NA */ -#define TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_M (TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_S) -#define TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_S 23 +#define TEE_REG_CORE1_MM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define TEE_REG_CORE1_MM_HP_BITSCRAMBLER_ALLOW_M (TEE_REG_CORE1_MM_HP_BITSCRAMBLER_ALLOW_V << TEE_REG_CORE1_MM_HP_BITSCRAMBLER_ALLOW_S) +#define TEE_REG_CORE1_MM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define TEE_REG_CORE1_MM_HP_BITSCRAMBLER_ALLOW_S 23 /** TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * NA */ @@ -1910,13 +1910,13 @@ extern "C" { #define TEE_REG_CORE1_UM_HP_RMT_ALLOW_M (TEE_REG_CORE1_UM_HP_RMT_ALLOW_V << TEE_REG_CORE1_UM_HP_RMT_ALLOW_S) #define TEE_REG_CORE1_UM_HP_RMT_ALLOW_V 0x00000001U #define TEE_REG_CORE1_UM_HP_RMT_ALLOW_S 22 -/** TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** TEE_REG_CORE1_UM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * NA */ -#define TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_M (TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_S) -#define TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_S 23 +#define TEE_REG_CORE1_UM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define TEE_REG_CORE1_UM_HP_BITSCRAMBLER_ALLOW_M (TEE_REG_CORE1_UM_HP_BITSCRAMBLER_ALLOW_V << TEE_REG_CORE1_UM_HP_BITSCRAMBLER_ALLOW_S) +#define TEE_REG_CORE1_UM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define TEE_REG_CORE1_UM_HP_BITSCRAMBLER_ALLOW_S 23 /** TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * NA */ diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_reg.h index 53109b176c..63fb1009b7 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_reg.h @@ -350,16 +350,16 @@ extern "C" { #define PMS_CORE0_MM_HP_RMT_ALLOW_M (PMS_CORE0_MM_HP_RMT_ALLOW_V << PMS_CORE0_MM_HP_RMT_ALLOW_S) #define PMS_CORE0_MM_HP_RMT_ALLOW_V 0x00000001U #define PMS_CORE0_MM_HP_RMT_ALLOW_S 22 -/** PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** PMS_CORE0_MM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * Configures whether HP CPU0 in machine mode has permission to access HP bit * scrambler. * 0: Not allowed * 1: Allowed */ -#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_M (PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_S) -#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_S 23 +#define PMS_CORE0_MM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define PMS_CORE0_MM_HP_BITSCRAMBLER_ALLOW_M (PMS_CORE0_MM_HP_BITSCRAMBLER_ALLOW_V << PMS_CORE0_MM_HP_BITSCRAMBLER_ALLOW_S) +#define PMS_CORE0_MM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define PMS_CORE0_MM_HP_BITSCRAMBLER_ALLOW_S 23 /** PMS_CORE0_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * Configures whether HP CPU0 in machine mode has permission to access HP AXI ICM. * 0: Not allowed @@ -1050,15 +1050,15 @@ extern "C" { #define PMS_CORE0_UM_HP_RMT_ALLOW_M (PMS_CORE0_UM_HP_RMT_ALLOW_V << PMS_CORE0_UM_HP_RMT_ALLOW_S) #define PMS_CORE0_UM_HP_RMT_ALLOW_V 0x00000001U #define PMS_CORE0_UM_HP_RMT_ALLOW_S 22 -/** PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** PMS_CORE0_UM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * Configures whether HP CPU0 in user mode has permission to access HP bit scrambler. * 0: Not allowed * 1: Allowed */ -#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_M (PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_S) -#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_S 23 +#define PMS_CORE0_UM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define PMS_CORE0_UM_HP_BITSCRAMBLER_ALLOW_M (PMS_CORE0_UM_HP_BITSCRAMBLER_ALLOW_V << PMS_CORE0_UM_HP_BITSCRAMBLER_ALLOW_S) +#define PMS_CORE0_UM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define PMS_CORE0_UM_HP_BITSCRAMBLER_ALLOW_S 23 /** PMS_CORE0_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * Configures whether HP CPU0 in user mode has permission to access HP AXI ICM. * 0: Not allowed @@ -1749,16 +1749,16 @@ extern "C" { #define PMS_CORE1_MM_HP_RMT_ALLOW_M (PMS_CORE1_MM_HP_RMT_ALLOW_V << PMS_CORE1_MM_HP_RMT_ALLOW_S) #define PMS_CORE1_MM_HP_RMT_ALLOW_V 0x00000001U #define PMS_CORE1_MM_HP_RMT_ALLOW_S 22 -/** PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** PMS_CORE1_MM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * Configures whether HP CPU1 in machine mode has permission to access HP bit * scrambler. * 0: Not allowed * 1: Allowed */ -#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_M (PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_S) -#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_S 23 +#define PMS_CORE1_MM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define PMS_CORE1_MM_HP_BITSCRAMBLER_ALLOW_M (PMS_CORE1_MM_HP_BITSCRAMBLER_ALLOW_V << PMS_CORE1_MM_HP_BITSCRAMBLER_ALLOW_S) +#define PMS_CORE1_MM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define PMS_CORE1_MM_HP_BITSCRAMBLER_ALLOW_S 23 /** PMS_CORE1_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * Configures whether HP CPU1 in machine mode has permission to access HP AXI ICM. * 0: Not allowed @@ -2449,15 +2449,15 @@ extern "C" { #define PMS_CORE1_UM_HP_RMT_ALLOW_M (PMS_CORE1_UM_HP_RMT_ALLOW_V << PMS_CORE1_UM_HP_RMT_ALLOW_S) #define PMS_CORE1_UM_HP_RMT_ALLOW_V 0x00000001U #define PMS_CORE1_UM_HP_RMT_ALLOW_S 22 -/** PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** PMS_CORE1_UM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * Configures whether HP CPU1 in user mode has permission to access HP bit scrambler. * 0: Not allowed * 1: Allowed */ -#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_M (PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_S) -#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_S 23 +#define PMS_CORE1_UM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define PMS_CORE1_UM_HP_BITSCRAMBLER_ALLOW_M (PMS_CORE1_UM_HP_BITSCRAMBLER_ALLOW_V << PMS_CORE1_UM_HP_BITSCRAMBLER_ALLOW_S) +#define PMS_CORE1_UM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define PMS_CORE1_UM_HP_BITSCRAMBLER_ALLOW_S 23 /** PMS_CORE1_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * Configures whether HP CPU1 in user mode has permission to access HP AXI ICM. * 0: Not allowed diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_sys_clkrst_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_sys_clkrst_reg.h index 0c42d1e8ca..ec107f6126 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/hp_sys_clkrst_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_sys_clkrst_reg.h @@ -570,27 +570,27 @@ extern "C" { #define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_S) #define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_V 0x00000001U #define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_S 27 -/** HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN : R/W; bitpos: [28]; default: 1; +/** HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN : R/W; bitpos: [28]; default: 1; * Reserved */ -#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN (BIT(28)) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_S) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_V 0x00000001U -#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_S 28 -/** HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN : R/W; bitpos: [29]; default: 1; +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN (BIT(28)) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_S) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_V 0x00000001U +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_S 28 +/** HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN : R/W; bitpos: [29]; default: 1; * Reserved */ -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN (BIT(29)) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_S) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_V 0x00000001U -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_S 29 -/** HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN : R/W; bitpos: [30]; default: 1; +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN (BIT(29)) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_S) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_V 0x00000001U +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_S 29 +/** HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN : R/W; bitpos: [30]; default: 1; * Reserved */ -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN (BIT(30)) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_S) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_V 0x00000001U -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_S 30 +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN (BIT(30)) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_S) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_V 0x00000001U +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_S 30 /** HP_SYS_CLKRST_REG_H264_SYS_CLK_EN : R/W; bitpos: [31]; default: 0; * Reserved */ @@ -3627,27 +3627,27 @@ extern "C" { #define HP_SYS_CLKRST_REG_RST_EN_ADC_M (HP_SYS_CLKRST_REG_RST_EN_ADC_V << HP_SYS_CLKRST_REG_RST_EN_ADC_S) #define HP_SYS_CLKRST_REG_RST_EN_ADC_V 0x00000001U #define HP_SYS_CLKRST_REG_RST_EN_ADC_S 10 -/** HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER : R/W; bitpos: [11]; default: 0; +/** HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER : R/W; bitpos: [11]; default: 0; * Reserved */ -#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER (BIT(11)) -#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_M (HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_V << HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_S) -#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_V 0x00000001U -#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_S 11 -/** HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX : R/W; bitpos: [12]; default: 0; +#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER (BIT(11)) +#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_M (HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_V << HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_S) +#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_V 0x00000001U +#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_S 11 +/** HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_RX : R/W; bitpos: [12]; default: 0; * Reserved */ -#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX (BIT(12)) -#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_M (HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_V << HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_S) -#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_V 0x00000001U -#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_S 12 -/** HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX : R/W; bitpos: [13]; default: 0; +#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_RX (BIT(12)) +#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_RX_M (HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_RX_V << HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_RX_S) +#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_RX_V 0x00000001U +#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_RX_S 12 +/** HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_TX : R/W; bitpos: [13]; default: 0; * Reserved */ -#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX (BIT(13)) -#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_M (HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_V << HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_S) -#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_V 0x00000001U -#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_S 13 +#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_TX (BIT(13)) +#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_TX_M (HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_TX_V << HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_TX_S) +#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_TX_V 0x00000001U +#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_TX_S 13 /** HP_SYS_CLKRST_REG_RST_EN_CRYPTO : R/W; bitpos: [14]; default: 0; * Reserved */ @@ -4120,27 +4120,27 @@ extern "C" { #define HP_SYS_CLKRST_REG_FORCE_NORST_ADC_M (HP_SYS_CLKRST_REG_FORCE_NORST_ADC_V << HP_SYS_CLKRST_REG_FORCE_NORST_ADC_S) #define HP_SYS_CLKRST_REG_FORCE_NORST_ADC_V 0x00000001U #define HP_SYS_CLKRST_REG_FORCE_NORST_ADC_S 22 -/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER : R/W; bitpos: [23]; default: 0; +/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER : R/W; bitpos: [23]; default: 0; * Reserved */ -#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER (BIT(23)) -#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_M (HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_S) -#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_V 0x00000001U -#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_S 23 -/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX : R/W; bitpos: [24]; default: 0; +#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER (BIT(23)) +#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_M (HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_S) +#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_V 0x00000001U +#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_S 23 +/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_RX : R/W; bitpos: [24]; default: 0; * Reserved */ -#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX (BIT(24)) -#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_M (HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_S) -#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_V 0x00000001U -#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_S 24 -/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX : R/W; bitpos: [25]; default: 0; +#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_RX (BIT(24)) +#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_RX_M (HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_RX_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_RX_S) +#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_RX_V 0x00000001U +#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_RX_S 24 +/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_TX : R/W; bitpos: [25]; default: 0; * Reserved */ -#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX (BIT(25)) -#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_M (HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_S) -#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_V 0x00000001U -#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_S 25 +#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_TX (BIT(25)) +#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_TX_M (HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_TX_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_TX_S) +#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_TX_V 0x00000001U +#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_TX_S 25 /** HP_SYS_CLKRST_REG_FORCE_NORST_H264 : R/W; bitpos: [26]; default: 0; * Reserved */ diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_eco5_reg.h index 48bf757266..e837297c6b 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_eco5_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_eco5_reg.h @@ -275,13 +275,13 @@ extern "C" { #define TEE_REG_LP_MM_HP_RMT_ALLOW_M (TEE_REG_LP_MM_HP_RMT_ALLOW_V << TEE_REG_LP_MM_HP_RMT_ALLOW_S) #define TEE_REG_LP_MM_HP_RMT_ALLOW_V 0x00000001U #define TEE_REG_LP_MM_HP_RMT_ALLOW_S 22 -/** TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * NA */ -#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_M (TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_S) -#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_S 23 +#define TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_M (TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_V << TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_S) +#define TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_S 23 /** TEE_REG_LP_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * NA */ diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_reg.h index 91ce65974d..c219a7080b 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_reg.h @@ -350,16 +350,16 @@ extern "C" { #define PMS_LP_MM_HP_RMT_ALLOW_M (PMS_LP_MM_HP_RMT_ALLOW_V << PMS_LP_MM_HP_RMT_ALLOW_S) #define PMS_LP_MM_HP_RMT_ALLOW_V 0x00000001U #define PMS_LP_MM_HP_RMT_ALLOW_S 22 -/** PMS_LP_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; +/** PMS_LP_MM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; * Configures whether the LP CPU in machine mode has permission to access HP bit * scrambler. * 0: Not allowed * 1: Allowed */ -#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW (BIT(23)) -#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_M (PMS_LP_MM_HP_BITSRAMBLER_ALLOW_V << PMS_LP_MM_HP_BITSRAMBLER_ALLOW_S) -#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_V 0x00000001U -#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_S 23 +#define PMS_LP_MM_HP_BITSCRAMBLER_ALLOW (BIT(23)) +#define PMS_LP_MM_HP_BITSCRAMBLER_ALLOW_M (PMS_LP_MM_HP_BITSCRAMBLER_ALLOW_V << PMS_LP_MM_HP_BITSCRAMBLER_ALLOW_S) +#define PMS_LP_MM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_BITSCRAMBLER_ALLOW_S 23 /** PMS_LP_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; * Configures whether the LP CPU in machine mode has permission to access HP AXI ICM. * 0: Not allowed diff --git a/components/soc/esp32p4/register/hw_ver3/soc/trace_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/trace_reg.h index cb2b638bc6..9825cecd0d 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/trace_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/trace_reg.h @@ -11,10 +11,12 @@ extern "C" { #endif +#define REG_TRACE_BASE(i) (DR_REG_TRACE_BASE + (i) * 0x1000) + /** TRACE_MEM_START_ADDR_REG register * mem start addr */ -#define TRACE_MEM_START_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x0) +#define TRACE_MEM_START_ADDR_REG(i) (REG_TRACE_BASE(i) + 0x0) /** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; * The start address of trace memory */ @@ -26,7 +28,7 @@ extern "C" { /** TRACE_MEM_END_ADDR_REG register * mem end addr */ -#define TRACE_MEM_END_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x4) +#define TRACE_MEM_END_ADDR_REG(i) (REG_TRACE_BASE(i) + 0x4) /** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; * The end address of trace memory */ @@ -38,7 +40,7 @@ extern "C" { /** TRACE_MEM_CURRENT_ADDR_REG register * mem current addr */ -#define TRACE_MEM_CURRENT_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x8) +#define TRACE_MEM_CURRENT_ADDR_REG(i) (REG_TRACE_BASE(i) + 0x8) /** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; * current_mem_addr,indicate that next writing addr */ @@ -50,7 +52,7 @@ extern "C" { /** TRACE_MEM_ADDR_UPDATE_REG register * mem addr update */ -#define TRACE_MEM_ADDR_UPDATE_REG(i) (DR_REG_TRACE_BASE(i) + 0xc) +#define TRACE_MEM_ADDR_UPDATE_REG(i) (REG_TRACE_BASE(i) + 0xc) /** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0; * when set, the will * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to @@ -64,7 +66,7 @@ extern "C" { /** TRACE_FIFO_STATUS_REG register * fifo status register */ -#define TRACE_FIFO_STATUS_REG(i) (DR_REG_TRACE_BASE(i) + 0x10) +#define TRACE_FIFO_STATUS_REG(i) (REG_TRACE_BASE(i) + 0x10) /** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1; * Represent whether the fifo is empty. * 1: empty @@ -89,7 +91,7 @@ extern "C" { /** TRACE_INTR_ENA_REG register * interrupt enable register */ -#define TRACE_INTR_ENA_REG(i) (DR_REG_TRACE_BASE(i) + 0x14) +#define TRACE_INTR_ENA_REG(i) (REG_TRACE_BASE(i) + 0x14) /** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0; * Set 1 enable fifo_overflow interrupt */ @@ -108,7 +110,7 @@ extern "C" { /** TRACE_INTR_RAW_REG register * interrupt status register */ -#define TRACE_INTR_RAW_REG(i) (DR_REG_TRACE_BASE(i) + 0x18) +#define TRACE_INTR_RAW_REG(i) (REG_TRACE_BASE(i) + 0x18) /** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0; * fifo_overflow interrupt status */ @@ -127,7 +129,7 @@ extern "C" { /** TRACE_INTR_CLR_REG register * interrupt clear register */ -#define TRACE_INTR_CLR_REG(i) (DR_REG_TRACE_BASE(i) + 0x1c) +#define TRACE_INTR_CLR_REG(i) (REG_TRACE_BASE(i) + 0x1c) /** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0; * Set 1 clear fifo overflow interrupt */ @@ -146,7 +148,7 @@ extern "C" { /** TRACE_TRIGGER_REG register * trigger register */ -#define TRACE_TRIGGER_REG(i) (DR_REG_TRACE_BASE(i) + 0x20) +#define TRACE_TRIGGER_REG(i) (REG_TRACE_BASE(i) + 0x20) /** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0; * Configure whether or not start trace. * 1: start trace @@ -187,7 +189,7 @@ extern "C" { /** TRACE_CONFIG_REG register * trace configuration register */ -#define TRACE_CONFIG_REG(i) (DR_REG_TRACE_BASE(i) + 0x24) +#define TRACE_CONFIG_REG(i) (REG_TRACE_BASE(i) + 0x24) /** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0; * Configure whether or not enable cpu trigger action. * 1: enable @@ -254,7 +256,7 @@ extern "C" { /** TRACE_FILTER_CONTROL_REG register * filter control register */ -#define TRACE_FILTER_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x28) +#define TRACE_FILTER_CONTROL_REG(i) (REG_TRACE_BASE(i) + 0x28) /** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0; * Configure whether or not enable filter unit. * 1: enable filter. @@ -301,7 +303,7 @@ extern "C" { /** TRACE_FILTER_MATCH_CONTROL_REG register * filter match control register */ -#define TRACE_FILTER_MATCH_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x2c) +#define TRACE_FILTER_MATCH_CONTROL_REG(i) (REG_TRACE_BASE(i) + 0x2c) /** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0; * Select match which privilege level when * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. @@ -333,7 +335,7 @@ extern "C" { /** TRACE_FILTER_COMPARATOR_CONTROL_REG register * filter comparator match control register */ -#define TRACE_FILTER_COMPARATOR_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x30) +#define TRACE_FILTER_COMPARATOR_CONTROL_REG(i) (REG_TRACE_BASE(i) + 0x30) /** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0; * Determines which input to compare against the primary comparator, * 0: iaddr, @@ -411,7 +413,7 @@ extern "C" { /** TRACE_FILTER_P_COMPARATOR_MATCH_REG register * primary comparator match value */ -#define TRACE_FILTER_P_COMPARATOR_MATCH_REG(i) (DR_REG_TRACE_BASE(i) + 0x34) +#define TRACE_FILTER_P_COMPARATOR_MATCH_REG(i) (REG_TRACE_BASE(i) + 0x34) /** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0; * primary comparator match value */ @@ -423,7 +425,7 @@ extern "C" { /** TRACE_FILTER_S_COMPARATOR_MATCH_REG register * secondary comparator match value */ -#define TRACE_FILTER_S_COMPARATOR_MATCH_REG(i) (DR_REG_TRACE_BASE(i) + 0x38) +#define TRACE_FILTER_S_COMPARATOR_MATCH_REG(i) (REG_TRACE_BASE(i) + 0x38) /** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0; * secondary comparator match value */ @@ -435,7 +437,7 @@ extern "C" { /** TRACE_RESYNC_PROLONGED_REG register * resync configuration register */ -#define TRACE_RESYNC_PROLONGED_REG(i) (DR_REG_TRACE_BASE(i) + 0x3c) +#define TRACE_RESYNC_PROLONGED_REG(i) (REG_TRACE_BASE(i) + 0x3c) /** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128; * count number, when count to this value, send a sync package */ @@ -457,7 +459,7 @@ extern "C" { /** TRACE_AHB_CONFIG_REG register * AHB config register */ -#define TRACE_AHB_CONFIG_REG(i) (DR_REG_TRACE_BASE(i) + 0x40) +#define TRACE_AHB_CONFIG_REG(i) (REG_TRACE_BASE(i) + 0x40) /** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0; * set hburst */ @@ -476,7 +478,7 @@ extern "C" { /** TRACE_CLOCK_GATE_REG register * Clock gate control register */ -#define TRACE_CLOCK_GATE_REG(i) (DR_REG_TRACE_BASE(i) + 0x44) +#define TRACE_CLOCK_GATE_REG(i) (REG_TRACE_BASE(i) + 0x44) /** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; * The bit is used to enable clock gate when access all registers in this module. */ @@ -488,7 +490,7 @@ extern "C" { /** TRACE_DATE_REG register * Version control register */ -#define TRACE_DATE_REG(i) (DR_REG_TRACE_BASE(i) + 0x3fc) +#define TRACE_DATE_REG(i) (REG_TRACE_BASE(i) + 0x3fc) /** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984; * version control register. Note that this default value stored is the latest date * when the hardware logic was updated. diff --git a/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h index b0095d17c7..125ebade43 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h @@ -11,15 +11,15 @@ extern "C" { #endif -/** USB_DEVICE_EP1_REG register +/** USB_SERIAL_JTAG_EP1_REG register * FIFO access for the CDC-ACM data IN and OUT endpoints. */ -#define USB_DEVICE_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) +#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) /** USB_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0; * Write and read byte data to/from UART Tx/Rx FIFO through this field. When - * USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) - * into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check - * USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) + * into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check + * USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is * received, then read data from UART Rx FIFO. */ #define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU @@ -27,10 +27,10 @@ extern "C" { #define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU #define USB_SERIAL_JTAG_RDWR_BYTE_S 0 -/** USB_DEVICE_EP1_CONF_REG register +/** USB_SERIAL_JTAG_EP1_CONF_REG register * Configuration and control registers for the CDC-ACM FIFOs. */ -#define USB_DEVICE_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) +#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) /** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; * Set this bit to indicate writing byte data to UART Tx FIFO is done. */ @@ -40,7 +40,7 @@ extern "C" { #define USB_SERIAL_JTAG_WR_DONE_S 0 /** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing - * USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB + * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB * Host. */ #define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) @@ -55,10 +55,10 @@ extern "C" { #define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 -/** USB_DEVICE_INT_RAW_REG register +/** USB_SERIAL_JTAG_INT_RAW_REG register * Interrupt raw status register. */ -#define USB_DEVICE_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) +#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when flush cmd is received for IN * endpoint 2 of JTAG. @@ -185,361 +185,361 @@ extern "C" { #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 -/** USB_DEVICE_INT_ST_REG register +/** USB_SERIAL_JTAG_INT_ST_REG register * Interrupt status register. */ -#define USB_DEVICE_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) +#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. */ #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 /** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. */ #define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) #define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) #define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_SOF_INT_ST_S 1 /** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. */ #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 /** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. */ #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 /** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) #define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) #define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 /** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) #define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) #define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 /** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) #define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) #define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 /** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) #define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) #define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 /** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. */ #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 /** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. */ #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 /** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 /** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 /** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. */ #define USB_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) #define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S) #define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 /** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. */ #define USB_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) #define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S) #define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 /** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. */ #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 /** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + * The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. */ #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 -/** USB_DEVICE_INT_ENA_REG register +/** USB_SERIAL_JTAG_INT_ENA_REG register * Interrupt enable status register. */ -#define USB_DEVICE_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) +#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. */ #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 /** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. */ #define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) #define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) #define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 /** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. */ #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 /** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. */ #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 /** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) #define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) #define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 /** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) #define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) #define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 /** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) #define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) #define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 /** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) #define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) #define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 /** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. */ #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 /** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. */ #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 /** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 /** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 /** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. */ #define USB_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) #define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S) #define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 /** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. */ #define USB_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) #define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S) #define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 /** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; - * The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. */ #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 /** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + * The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. */ #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 -/** USB_DEVICE_INT_CLR_REG register +/** USB_SERIAL_JTAG_INT_CLR_REG register * Interrupt clear status register. */ -#define USB_DEVICE_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) +#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. */ #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 /** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. */ #define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) #define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) #define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 /** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. */ #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 /** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. */ #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 /** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) #define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) #define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 /** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) #define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) #define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 /** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) #define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) #define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 /** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. */ #define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) #define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) #define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 /** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. */ #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 /** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. */ #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 /** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 /** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 /** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. */ #define USB_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) #define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S) #define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 /** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. */ #define USB_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) #define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S) #define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 /** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; - * Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. */ #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 /** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; - * Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. + * Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. */ #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U #define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 -/** USB_DEVICE_CONF0_REG register +/** USB_SERIAL_JTAG_CONF0_REG register * PHY hardware configuration. */ -#define USB_DEVICE_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) +#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) /** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; * Select internal/external PHY */ @@ -641,10 +641,10 @@ extern "C" { #define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U #define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 -/** USB_DEVICE_TEST_REG register +/** USB_SERIAL_JTAG_TEST_REG register * Registers used for debugging the PHY. */ -#define USB_DEVICE_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) +#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) /** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; * Enable test of the USB pad */ @@ -695,10 +695,10 @@ extern "C" { #define USB_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U #define USB_SERIAL_JTAG_TEST_RX_DM_S 6 -/** USB_DEVICE_JFIFO_ST_REG register +/** USB_SERIAL_JTAG_JFIFO_ST_REG register * JTAG FIFO status and control registers. */ -#define USB_DEVICE_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) +#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) /** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; * JTAT in fifo counter. */ @@ -756,10 +756,10 @@ extern "C" { #define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U #define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 -/** USB_DEVICE_FRAM_NUM_REG register +/** USB_SERIAL_JTAG_FRAM_NUM_REG register * Last received SOF frame index register. */ -#define USB_DEVICE_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) +#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) /** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; * Frame index of received SOF frame. */ @@ -768,10 +768,10 @@ extern "C" { #define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU #define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 -/** USB_DEVICE_IN_EP0_ST_REG register +/** USB_SERIAL_JTAG_IN_EP0_ST_REG register * Control IN endpoint status information. */ -#define USB_DEVICE_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) +#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) /** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 0. */ @@ -794,10 +794,10 @@ extern "C" { #define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU #define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 -/** USB_DEVICE_IN_EP1_ST_REG register +/** USB_SERIAL_JTAG_IN_EP1_ST_REG register * CDC-ACM IN endpoint status information. */ -#define USB_DEVICE_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) +#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) /** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 1. */ @@ -820,10 +820,10 @@ extern "C" { #define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU #define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 -/** USB_DEVICE_IN_EP2_ST_REG register +/** USB_SERIAL_JTAG_IN_EP2_ST_REG register * CDC-ACM interrupt IN endpoint status information. */ -#define USB_DEVICE_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) +#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) /** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 2. */ @@ -846,10 +846,10 @@ extern "C" { #define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU #define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 -/** USB_DEVICE_IN_EP3_ST_REG register +/** USB_SERIAL_JTAG_IN_EP3_ST_REG register * JTAG IN endpoint status information. */ -#define USB_DEVICE_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) +#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) /** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 3. */ @@ -872,10 +872,10 @@ extern "C" { #define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU #define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 -/** USB_DEVICE_OUT_EP0_ST_REG register +/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register * Control OUT endpoint status information. */ -#define USB_DEVICE_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) +#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) /** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 0. */ @@ -884,8 +884,8 @@ extern "C" { #define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U #define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 /** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - * detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. */ #define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU #define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) @@ -899,10 +899,10 @@ extern "C" { #define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU #define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 -/** USB_DEVICE_OUT_EP1_ST_REG register +/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register * CDC-ACM OUT endpoint status information. */ -#define USB_DEVICE_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) +#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) /** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 1. */ @@ -911,8 +911,8 @@ extern "C" { #define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U #define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 /** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - * detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. */ #define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU #define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) @@ -933,10 +933,10 @@ extern "C" { #define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU #define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 -/** USB_DEVICE_OUT_EP2_ST_REG register +/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register * JTAG OUT endpoint status information. */ -#define USB_DEVICE_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) +#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) /** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 2. */ @@ -945,8 +945,8 @@ extern "C" { #define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U #define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 /** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - * detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. */ #define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU #define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) @@ -960,10 +960,10 @@ extern "C" { #define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU #define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 -/** USB_DEVICE_MISC_CONF_REG register +/** USB_SERIAL_JTAG_MISC_CONF_REG register * Clock enable control */ -#define USB_DEVICE_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) +#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) /** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes * registers. @@ -992,10 +992,10 @@ extern "C" { #define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U #define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 -/** USB_DEVICE_CHIP_RST_REG register +/** USB_SERIAL_JTAG_CHIP_RST_REG register * CDC-ACM chip reset control. */ -#define USB_DEVICE_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c) +#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c) /** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. */ @@ -1018,10 +1018,10 @@ extern "C" { #define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U #define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 -/** USB_DEVICE_SET_LINE_CODE_W0_REG register +/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register * W0 of SET_LINE_CODING command. */ -#define USB_DEVICE_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50) +#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50) /** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; * The value of dwDTERate set by host through SET_LINE_CODING command. */ @@ -1030,10 +1030,10 @@ extern "C" { #define USB_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU #define USB_SERIAL_JTAG_DW_DTE_RATE_S 0 -/** USB_DEVICE_SET_LINE_CODE_W1_REG register +/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register * W1 of SET_LINE_CODING command. */ -#define USB_DEVICE_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54) +#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54) /** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; * The value of bCharFormat set by host through SET_LINE_CODING command. */ @@ -1056,10 +1056,10 @@ extern "C" { #define USB_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU #define USB_SERIAL_JTAG_BDATA_BITS_S 16 -/** USB_DEVICE_GET_LINE_CODE_W0_REG register +/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register * W0 of GET_LINE_CODING command. */ -#define USB_DEVICE_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58) +#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58) /** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; * The value of dwDTERate set by software which is requested by GET_LINE_CODING * command. @@ -1069,10 +1069,10 @@ extern "C" { #define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU #define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 -/** USB_DEVICE_GET_LINE_CODE_W1_REG register +/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register * W1 of GET_LINE_CODING command. */ -#define USB_DEVICE_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c) +#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c) /** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; * The value of bCharFormat set by software which is requested by GET_LINE_CODING * command. @@ -1098,10 +1098,10 @@ extern "C" { #define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU #define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 -/** USB_DEVICE_CONFIG_UPDATE_REG register +/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register * Configuration registers' value update */ -#define USB_DEVICE_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60) /** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; * Write 1 to this register would update the value of configure registers from APB * clock domain to 48MHz clock domain. @@ -1111,10 +1111,10 @@ extern "C" { #define USB_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U #define USB_SERIAL_JTAG_CONFIG_UPDATE_S 0 -/** USB_DEVICE_SER_AFIFO_CONFIG_REG register +/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register * Serial AFIFO configure register */ -#define USB_DEVICE_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64) +#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64) /** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; * Write 1 to reset CDC_ACM IN async FIFO write clock domain. */ @@ -1158,10 +1158,10 @@ extern "C" { #define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U #define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 -/** USB_DEVICE_BUS_RESET_ST_REG register +/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register * USB Bus reset status register */ -#define USB_DEVICE_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68) +#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68) /** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus * reset is released. @@ -1171,10 +1171,10 @@ extern "C" { #define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U #define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 -/** USB_DEVICE_ECO_LOW_48_REG register +/** USB_SERIAL_JTAG_ECO_LOW_48_REG register * Reserved. */ -#define USB_DEVICE_ECO_LOW_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c) +#define USB_SERIAL_JTAG_ECO_LOW_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c) /** USB_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0; * Reserved. */ @@ -1183,10 +1183,10 @@ extern "C" { #define USB_SERIAL_JTAG_RND_ECO_LOW_48_V 0xFFFFFFFFU #define USB_SERIAL_JTAG_RND_ECO_LOW_48_S 0 -/** USB_DEVICE_ECO_HIGH_48_REG register +/** USB_SERIAL_JTAG_ECO_HIGH_48_REG register * Reserved. */ -#define USB_DEVICE_ECO_HIGH_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70) +#define USB_SERIAL_JTAG_ECO_HIGH_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70) /** USB_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295; * Reserved. */ @@ -1195,10 +1195,10 @@ extern "C" { #define USB_SERIAL_JTAG_RND_ECO_HIGH_48_V 0xFFFFFFFFU #define USB_SERIAL_JTAG_RND_ECO_HIGH_48_S 0 -/** USB_DEVICE_ECO_CELL_CTRL_48_REG register +/** USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG register * Reserved. */ -#define USB_DEVICE_ECO_CELL_CTRL_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x74) +#define USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x74) /** USB_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0; * Reserved. */ @@ -1214,10 +1214,10 @@ extern "C" { #define USB_SERIAL_JTAG_RDN_ENA_48_V 0x00000001U #define USB_SERIAL_JTAG_RDN_ENA_48_S 1 -/** USB_DEVICE_ECO_LOW_APB_REG register +/** USB_SERIAL_JTAG_ECO_LOW_APB_REG register * Reserved. */ -#define USB_DEVICE_ECO_LOW_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x78) +#define USB_SERIAL_JTAG_ECO_LOW_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x78) /** USB_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0; * Reserved. */ @@ -1226,10 +1226,10 @@ extern "C" { #define USB_SERIAL_JTAG_RND_ECO_LOW_APB_V 0xFFFFFFFFU #define USB_SERIAL_JTAG_RND_ECO_LOW_APB_S 0 -/** USB_DEVICE_ECO_HIGH_APB_REG register +/** USB_SERIAL_JTAG_ECO_HIGH_APB_REG register * Reserved. */ -#define USB_DEVICE_ECO_HIGH_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x7c) +#define USB_SERIAL_JTAG_ECO_HIGH_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x7c) /** USB_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295; * Reserved. */ @@ -1238,10 +1238,10 @@ extern "C" { #define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V 0xFFFFFFFFU #define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S 0 -/** USB_DEVICE_ECO_CELL_CTRL_APB_REG register +/** USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG register * Reserved. */ -#define USB_DEVICE_ECO_CELL_CTRL_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) +#define USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) /** USB_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0; * Reserved. */ @@ -1257,10 +1257,10 @@ extern "C" { #define USB_SERIAL_JTAG_RDN_ENA_APB_V 0x00000001U #define USB_SERIAL_JTAG_RDN_ENA_APB_S 1 -/** USB_DEVICE_SRAM_CTRL_REG register +/** USB_SERIAL_JTAG_SRAM_CTRL_REG register * PPA SRAM Control Register */ -#define USB_DEVICE_SRAM_CTRL_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x84) +#define USB_SERIAL_JTAG_SRAM_CTRL_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x84) /** USB_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; * Control signals */ @@ -1269,10 +1269,10 @@ extern "C" { #define USB_SERIAL_JTAG_MEM_AUX_CTRL_V 0x00003FFFU #define USB_SERIAL_JTAG_MEM_AUX_CTRL_S 0 -/** USB_DEVICE_DATE_REG register +/** USB_SERIAL_JTAG_DATE_REG register * Date register */ -#define USB_DEVICE_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x88) +#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x88) /** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752; * register version. */ diff --git a/components/soc/esp32s31/register/soc/hp_peri0_pms_reg.h b/components/soc/esp32s31/register/soc/hp_peri0_pms_reg.h index 0b9d152689..de55e4e527 100644 --- a/components/soc/esp32s31/register/soc/hp_peri0_pms_reg.h +++ b/components/soc/esp32s31/register/soc/hp_peri0_pms_reg.h @@ -1439,89 +1439,89 @@ extern "C" { #define HP_PERI0_PMS_HP_RMT_LOCK_V 0x00000001U #define HP_PERI0_PMS_HP_RMT_LOCK_S 8 -/** HP_PERI0_PMS_HP_BITSRAMBLER_CTRL_REG register +/** HP_PERI0_PMS_HP_BITSCRAMBLER_CTRL_REG register * hp_bitsrambler read/write control register */ -#define HP_PERI0_PMS_HP_BITSRAMBLER_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x44) -/** HP_PERI0_PMS_READ_TEE_HP_BITSRAMBLER : R/W; bitpos: [0]; default: 1; +#define HP_PERI0_PMS_HP_BITSCRAMBLER_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x44) +/** HP_PERI0_PMS_READ_TEE_HP_BITSCRAMBLER : R/W; bitpos: [0]; default: 1; * Configures hp_bitsrambler registers read permission in tee mode. * 0: can not be read * 1: can be read */ -#define HP_PERI0_PMS_READ_TEE_HP_BITSRAMBLER (BIT(0)) -#define HP_PERI0_PMS_READ_TEE_HP_BITSRAMBLER_M (HP_PERI0_PMS_READ_TEE_HP_BITSRAMBLER_V << HP_PERI0_PMS_READ_TEE_HP_BITSRAMBLER_S) -#define HP_PERI0_PMS_READ_TEE_HP_BITSRAMBLER_V 0x00000001U -#define HP_PERI0_PMS_READ_TEE_HP_BITSRAMBLER_S 0 -/** HP_PERI0_PMS_READ_REE0_HP_BITSRAMBLER : R/W; bitpos: [1]; default: 0; +#define HP_PERI0_PMS_READ_TEE_HP_BITSCRAMBLER (BIT(0)) +#define HP_PERI0_PMS_READ_TEE_HP_BITSCRAMBLER_M (HP_PERI0_PMS_READ_TEE_HP_BITSCRAMBLER_V << HP_PERI0_PMS_READ_TEE_HP_BITSCRAMBLER_S) +#define HP_PERI0_PMS_READ_TEE_HP_BITSCRAMBLER_V 0x00000001U +#define HP_PERI0_PMS_READ_TEE_HP_BITSCRAMBLER_S 0 +/** HP_PERI0_PMS_READ_REE0_HP_BITSCRAMBLER : R/W; bitpos: [1]; default: 0; * Configures hp_bitsrambler registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ -#define HP_PERI0_PMS_READ_REE0_HP_BITSRAMBLER (BIT(1)) -#define HP_PERI0_PMS_READ_REE0_HP_BITSRAMBLER_M (HP_PERI0_PMS_READ_REE0_HP_BITSRAMBLER_V << HP_PERI0_PMS_READ_REE0_HP_BITSRAMBLER_S) -#define HP_PERI0_PMS_READ_REE0_HP_BITSRAMBLER_V 0x00000001U -#define HP_PERI0_PMS_READ_REE0_HP_BITSRAMBLER_S 1 -/** HP_PERI0_PMS_READ_REE1_HP_BITSRAMBLER : R/W; bitpos: [2]; default: 0; +#define HP_PERI0_PMS_READ_REE0_HP_BITSCRAMBLER (BIT(1)) +#define HP_PERI0_PMS_READ_REE0_HP_BITSCRAMBLER_M (HP_PERI0_PMS_READ_REE0_HP_BITSCRAMBLER_V << HP_PERI0_PMS_READ_REE0_HP_BITSCRAMBLER_S) +#define HP_PERI0_PMS_READ_REE0_HP_BITSCRAMBLER_V 0x00000001U +#define HP_PERI0_PMS_READ_REE0_HP_BITSCRAMBLER_S 1 +/** HP_PERI0_PMS_READ_REE1_HP_BITSCRAMBLER : R/W; bitpos: [2]; default: 0; * Configures hp_bitsrambler registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ -#define HP_PERI0_PMS_READ_REE1_HP_BITSRAMBLER (BIT(2)) -#define HP_PERI0_PMS_READ_REE1_HP_BITSRAMBLER_M (HP_PERI0_PMS_READ_REE1_HP_BITSRAMBLER_V << HP_PERI0_PMS_READ_REE1_HP_BITSRAMBLER_S) -#define HP_PERI0_PMS_READ_REE1_HP_BITSRAMBLER_V 0x00000001U -#define HP_PERI0_PMS_READ_REE1_HP_BITSRAMBLER_S 2 -/** HP_PERI0_PMS_READ_REE2_HP_BITSRAMBLER : R/W; bitpos: [3]; default: 0; +#define HP_PERI0_PMS_READ_REE1_HP_BITSCRAMBLER (BIT(2)) +#define HP_PERI0_PMS_READ_REE1_HP_BITSCRAMBLER_M (HP_PERI0_PMS_READ_REE1_HP_BITSCRAMBLER_V << HP_PERI0_PMS_READ_REE1_HP_BITSCRAMBLER_S) +#define HP_PERI0_PMS_READ_REE1_HP_BITSCRAMBLER_V 0x00000001U +#define HP_PERI0_PMS_READ_REE1_HP_BITSCRAMBLER_S 2 +/** HP_PERI0_PMS_READ_REE2_HP_BITSCRAMBLER : R/W; bitpos: [3]; default: 0; * Configures hp_bitsrambler registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ -#define HP_PERI0_PMS_READ_REE2_HP_BITSRAMBLER (BIT(3)) -#define HP_PERI0_PMS_READ_REE2_HP_BITSRAMBLER_M (HP_PERI0_PMS_READ_REE2_HP_BITSRAMBLER_V << HP_PERI0_PMS_READ_REE2_HP_BITSRAMBLER_S) -#define HP_PERI0_PMS_READ_REE2_HP_BITSRAMBLER_V 0x00000001U -#define HP_PERI0_PMS_READ_REE2_HP_BITSRAMBLER_S 3 -/** HP_PERI0_PMS_WRITE_TEE_HP_BITSRAMBLER : R/W; bitpos: [4]; default: 1; +#define HP_PERI0_PMS_READ_REE2_HP_BITSCRAMBLER (BIT(3)) +#define HP_PERI0_PMS_READ_REE2_HP_BITSCRAMBLER_M (HP_PERI0_PMS_READ_REE2_HP_BITSCRAMBLER_V << HP_PERI0_PMS_READ_REE2_HP_BITSCRAMBLER_S) +#define HP_PERI0_PMS_READ_REE2_HP_BITSCRAMBLER_V 0x00000001U +#define HP_PERI0_PMS_READ_REE2_HP_BITSCRAMBLER_S 3 +/** HP_PERI0_PMS_WRITE_TEE_HP_BITSCRAMBLER : R/W; bitpos: [4]; default: 1; * Configures hp_bitsrambler registers write permission in tee mode. * 0: can not be write * 1: can be write */ -#define HP_PERI0_PMS_WRITE_TEE_HP_BITSRAMBLER (BIT(4)) -#define HP_PERI0_PMS_WRITE_TEE_HP_BITSRAMBLER_M (HP_PERI0_PMS_WRITE_TEE_HP_BITSRAMBLER_V << HP_PERI0_PMS_WRITE_TEE_HP_BITSRAMBLER_S) -#define HP_PERI0_PMS_WRITE_TEE_HP_BITSRAMBLER_V 0x00000001U -#define HP_PERI0_PMS_WRITE_TEE_HP_BITSRAMBLER_S 4 -/** HP_PERI0_PMS_WRITE_REE0_HP_BITSRAMBLER : R/W; bitpos: [5]; default: 0; +#define HP_PERI0_PMS_WRITE_TEE_HP_BITSCRAMBLER (BIT(4)) +#define HP_PERI0_PMS_WRITE_TEE_HP_BITSCRAMBLER_M (HP_PERI0_PMS_WRITE_TEE_HP_BITSCRAMBLER_V << HP_PERI0_PMS_WRITE_TEE_HP_BITSCRAMBLER_S) +#define HP_PERI0_PMS_WRITE_TEE_HP_BITSCRAMBLER_V 0x00000001U +#define HP_PERI0_PMS_WRITE_TEE_HP_BITSCRAMBLER_S 4 +/** HP_PERI0_PMS_WRITE_REE0_HP_BITSCRAMBLER : R/W; bitpos: [5]; default: 0; * Configures hp_bitsrambler registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ -#define HP_PERI0_PMS_WRITE_REE0_HP_BITSRAMBLER (BIT(5)) -#define HP_PERI0_PMS_WRITE_REE0_HP_BITSRAMBLER_M (HP_PERI0_PMS_WRITE_REE0_HP_BITSRAMBLER_V << HP_PERI0_PMS_WRITE_REE0_HP_BITSRAMBLER_S) -#define HP_PERI0_PMS_WRITE_REE0_HP_BITSRAMBLER_V 0x00000001U -#define HP_PERI0_PMS_WRITE_REE0_HP_BITSRAMBLER_S 5 -/** HP_PERI0_PMS_WRITE_REE1_HP_BITSRAMBLER : R/W; bitpos: [6]; default: 0; +#define HP_PERI0_PMS_WRITE_REE0_HP_BITSCRAMBLER (BIT(5)) +#define HP_PERI0_PMS_WRITE_REE0_HP_BITSCRAMBLER_M (HP_PERI0_PMS_WRITE_REE0_HP_BITSCRAMBLER_V << HP_PERI0_PMS_WRITE_REE0_HP_BITSCRAMBLER_S) +#define HP_PERI0_PMS_WRITE_REE0_HP_BITSCRAMBLER_V 0x00000001U +#define HP_PERI0_PMS_WRITE_REE0_HP_BITSCRAMBLER_S 5 +/** HP_PERI0_PMS_WRITE_REE1_HP_BITSCRAMBLER : R/W; bitpos: [6]; default: 0; * Configures hp_bitsrambler registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ -#define HP_PERI0_PMS_WRITE_REE1_HP_BITSRAMBLER (BIT(6)) -#define HP_PERI0_PMS_WRITE_REE1_HP_BITSRAMBLER_M (HP_PERI0_PMS_WRITE_REE1_HP_BITSRAMBLER_V << HP_PERI0_PMS_WRITE_REE1_HP_BITSRAMBLER_S) -#define HP_PERI0_PMS_WRITE_REE1_HP_BITSRAMBLER_V 0x00000001U -#define HP_PERI0_PMS_WRITE_REE1_HP_BITSRAMBLER_S 6 -/** HP_PERI0_PMS_WRITE_REE2_HP_BITSRAMBLER : R/W; bitpos: [7]; default: 0; +#define HP_PERI0_PMS_WRITE_REE1_HP_BITSCRAMBLER (BIT(6)) +#define HP_PERI0_PMS_WRITE_REE1_HP_BITSCRAMBLER_M (HP_PERI0_PMS_WRITE_REE1_HP_BITSCRAMBLER_V << HP_PERI0_PMS_WRITE_REE1_HP_BITSCRAMBLER_S) +#define HP_PERI0_PMS_WRITE_REE1_HP_BITSCRAMBLER_V 0x00000001U +#define HP_PERI0_PMS_WRITE_REE1_HP_BITSCRAMBLER_S 6 +/** HP_PERI0_PMS_WRITE_REE2_HP_BITSCRAMBLER : R/W; bitpos: [7]; default: 0; * Configures hp_bitsrambler registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ -#define HP_PERI0_PMS_WRITE_REE2_HP_BITSRAMBLER (BIT(7)) -#define HP_PERI0_PMS_WRITE_REE2_HP_BITSRAMBLER_M (HP_PERI0_PMS_WRITE_REE2_HP_BITSRAMBLER_V << HP_PERI0_PMS_WRITE_REE2_HP_BITSRAMBLER_S) -#define HP_PERI0_PMS_WRITE_REE2_HP_BITSRAMBLER_V 0x00000001U -#define HP_PERI0_PMS_WRITE_REE2_HP_BITSRAMBLER_S 7 -/** HP_PERI0_PMS_HP_BITSRAMBLER_LOCK : R/W; bitpos: [8]; default: 0; +#define HP_PERI0_PMS_WRITE_REE2_HP_BITSCRAMBLER (BIT(7)) +#define HP_PERI0_PMS_WRITE_REE2_HP_BITSCRAMBLER_M (HP_PERI0_PMS_WRITE_REE2_HP_BITSCRAMBLER_V << HP_PERI0_PMS_WRITE_REE2_HP_BITSCRAMBLER_S) +#define HP_PERI0_PMS_WRITE_REE2_HP_BITSCRAMBLER_V 0x00000001U +#define HP_PERI0_PMS_WRITE_REE2_HP_BITSCRAMBLER_S 7 +/** HP_PERI0_PMS_HP_BITSCRAMBLER_LOCK : R/W; bitpos: [8]; default: 0; * Set 1 to lock hp_bitsrambler peri_apm configuration */ -#define HP_PERI0_PMS_HP_BITSRAMBLER_LOCK (BIT(8)) -#define HP_PERI0_PMS_HP_BITSRAMBLER_LOCK_M (HP_PERI0_PMS_HP_BITSRAMBLER_LOCK_V << HP_PERI0_PMS_HP_BITSRAMBLER_LOCK_S) -#define HP_PERI0_PMS_HP_BITSRAMBLER_LOCK_V 0x00000001U -#define HP_PERI0_PMS_HP_BITSRAMBLER_LOCK_S 8 +#define HP_PERI0_PMS_HP_BITSCRAMBLER_LOCK (BIT(8)) +#define HP_PERI0_PMS_HP_BITSCRAMBLER_LOCK_M (HP_PERI0_PMS_HP_BITSCRAMBLER_LOCK_V << HP_PERI0_PMS_HP_BITSCRAMBLER_LOCK_S) +#define HP_PERI0_PMS_HP_BITSCRAMBLER_LOCK_V 0x00000001U +#define HP_PERI0_PMS_HP_BITSCRAMBLER_LOCK_S 8 /** HP_PERI0_PMS_HP_ASRC_CTRL_REG register * hp_asrc read/write control register diff --git a/components/soc/esp32s31/register/soc/hp_sys_clkrst_reg.h b/components/soc/esp32s31/register/soc/hp_sys_clkrst_reg.h index 09476aeef9..10e1c90054 100644 --- a/components/soc/esp32s31/register/soc/hp_sys_clkrst_reg.h +++ b/components/soc/esp32s31/register/soc/hp_sys_clkrst_reg.h @@ -1808,73 +1808,73 @@ extern "C" { #define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_V 0x000000FFU #define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_S 21 -/** HP_SYS_CLKRST_BITSRAMBLER_CTRL0_REG register +/** HP_SYS_CLKRST_BITSCRAMBLER_CTRL0_REG register * need_des */ -#define HP_SYS_CLKRST_BITSRAMBLER_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xa4) -/** HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN : R/W; bitpos: [0]; default: 0; +#define HP_SYS_CLKRST_BITSCRAMBLER_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xa4) +/** HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN : R/W; bitpos: [0]; default: 0; * need_des */ -#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN (BIT(0)) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_S) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_V 0x00000001U -#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_S 0 -/** HP_SYS_CLKRST_REG_BITSRAMBLER_RST_EN : R/W; bitpos: [1]; default: 0; +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN (BIT(0)) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_S) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_V 0x00000001U +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_S 0 +/** HP_SYS_CLKRST_REG_BITSCRAMBLER_RST_EN : R/W; bitpos: [1]; default: 0; * need_des */ -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RST_EN (BIT(1)) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RST_EN_M (HP_SYS_CLKRST_REG_BITSRAMBLER_RST_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_RST_EN_S) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RST_EN_V 0x00000001U -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RST_EN_S 1 -/** HP_SYS_CLKRST_REG_BITSRAMBLER_FORCE_NORST : R/W; bitpos: [2]; default: 0; +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RST_EN (BIT(1)) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RST_EN_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_RST_EN_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_RST_EN_S) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RST_EN_V 0x00000001U +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RST_EN_S 1 +/** HP_SYS_CLKRST_REG_BITSCRAMBLER_FORCE_NORST : R/W; bitpos: [2]; default: 0; * need_des */ -#define HP_SYS_CLKRST_REG_BITSRAMBLER_FORCE_NORST (BIT(2)) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_FORCE_NORST_M (HP_SYS_CLKRST_REG_BITSRAMBLER_FORCE_NORST_V << HP_SYS_CLKRST_REG_BITSRAMBLER_FORCE_NORST_S) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_FORCE_NORST_V 0x00000001U -#define HP_SYS_CLKRST_REG_BITSRAMBLER_FORCE_NORST_S 2 -/** HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN : R/W; bitpos: [3]; default: 0; +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_FORCE_NORST (BIT(2)) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_FORCE_NORST_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_FORCE_NORST_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_FORCE_NORST_S) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_FORCE_NORST_V 0x00000001U +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_FORCE_NORST_S 2 +/** HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN : R/W; bitpos: [3]; default: 0; * need_des */ -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN (BIT(3)) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_S) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_V 0x00000001U -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_S 3 -/** HP_SYS_CLKRST_REG_BITSRAMBLER_RX_RST_EN : R/W; bitpos: [4]; default: 0; +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN (BIT(3)) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_S) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_V 0x00000001U +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_S 3 +/** HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_RST_EN : R/W; bitpos: [4]; default: 0; * need_des */ -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_RST_EN (BIT(4)) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_RST_EN_M (HP_SYS_CLKRST_REG_BITSRAMBLER_RX_RST_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_RX_RST_EN_S) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_RST_EN_V 0x00000001U -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_RST_EN_S 4 -/** HP_SYS_CLKRST_REG_BITSRAMBLER_RX_FORCE_NORST : R/W; bitpos: [5]; default: 0; +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_RST_EN (BIT(4)) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_RST_EN_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_RST_EN_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_RST_EN_S) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_RST_EN_V 0x00000001U +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_RST_EN_S 4 +/** HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_FORCE_NORST : R/W; bitpos: [5]; default: 0; * need_des */ -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_FORCE_NORST (BIT(5)) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_FORCE_NORST_M (HP_SYS_CLKRST_REG_BITSRAMBLER_RX_FORCE_NORST_V << HP_SYS_CLKRST_REG_BITSRAMBLER_RX_FORCE_NORST_S) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_FORCE_NORST_V 0x00000001U -#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_FORCE_NORST_S 5 -/** HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN : R/W; bitpos: [6]; default: 0; +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_FORCE_NORST (BIT(5)) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_FORCE_NORST_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_FORCE_NORST_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_FORCE_NORST_S) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_FORCE_NORST_V 0x00000001U +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_FORCE_NORST_S 5 +/** HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN : R/W; bitpos: [6]; default: 0; * need_des */ -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN (BIT(6)) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_S) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_V 0x00000001U -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_S 6 -/** HP_SYS_CLKRST_REG_BITSRAMBLER_TX_RST_EN : R/W; bitpos: [7]; default: 0; +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN (BIT(6)) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_S) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_V 0x00000001U +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_S 6 +/** HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_RST_EN : R/W; bitpos: [7]; default: 0; * need_des */ -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_RST_EN (BIT(7)) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_RST_EN_M (HP_SYS_CLKRST_REG_BITSRAMBLER_TX_RST_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_TX_RST_EN_S) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_RST_EN_V 0x00000001U -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_RST_EN_S 7 -/** HP_SYS_CLKRST_REG_BITSRAMBLER_TX_FORCE_NORST : R/W; bitpos: [8]; default: 0; +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_RST_EN (BIT(7)) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_RST_EN_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_RST_EN_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_RST_EN_S) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_RST_EN_V 0x00000001U +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_RST_EN_S 7 +/** HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_FORCE_NORST : R/W; bitpos: [8]; default: 0; * need_des */ -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_FORCE_NORST (BIT(8)) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_FORCE_NORST_M (HP_SYS_CLKRST_REG_BITSRAMBLER_TX_FORCE_NORST_V << HP_SYS_CLKRST_REG_BITSRAMBLER_TX_FORCE_NORST_S) -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_FORCE_NORST_V 0x00000001U -#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_FORCE_NORST_S 8 +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_FORCE_NORST (BIT(8)) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_FORCE_NORST_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_FORCE_NORST_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_FORCE_NORST_S) +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_FORCE_NORST_V 0x00000001U +#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_FORCE_NORST_S 8 /** HP_SYS_CLKRST_ETM_CTRL0_REG register * need_des diff --git a/tools/test_apps/system/g1_components/CMakeLists.txt b/tools/test_apps/system/g1_components/CMakeLists.txt index c07ada24d9..457b569619 100644 --- a/tools/test_apps/system/g1_components/CMakeLists.txt +++ b/tools/test_apps/system/g1_components/CMakeLists.txt @@ -12,23 +12,14 @@ set(esp_hal_components esp_hal_ana_conv esp_hal_cam esp_hal_dma - esp_hal_emac esp_hal_gpio - esp_hal_i2c esp_hal_i2s - esp_hal_jpeg - esp_hal_lcd - esp_hal_mcpwm esp_hal_mspi - esp_hal_parlio - esp_hal_pcnt - esp_hal_rmt + esp_hal_gpspi esp_hal_timg esp_hal_touch_sens esp_hal_usb esp_hal_wdt - esp_hal_twai - esp_hal_gpspi ) set(COMPONENTS ${g0_components} ${g1_components} ${esp_hal_components} main) diff --git a/tools/test_apps/system/g1_components/main/CMakeLists.txt b/tools/test_apps/system/g1_components/main/CMakeLists.txt index 7f64ebdc92..c1c4323a9d 100644 --- a/tools/test_apps/system/g1_components/main/CMakeLists.txt +++ b/tools/test_apps/system/g1_components/main/CMakeLists.txt @@ -1,2 +1,2 @@ idf_component_register(SRCS "g1_components.c" - INCLUDE_DIRS ".") + INCLUDE_DIRS ".")