From 43bc8c2fe5c81a4034219beb095b38a87ac7c0ab Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 3 Apr 2026 19:16:28 +0800 Subject: [PATCH] feat(etm): add ETM LL and GPIO ETM support on esp32s31 Enable ETM caps and add S31 ETM/GPIO LL and retention support for GPTimer ETM builds. --- .../test_apps/dma/main/test_gdma_etm.c | 1 + .../esp32s31/include/hal/gpio_caps.h | 3 + .../esp32s31/include/hal/gpio_etm_ll.h | 133 ++ .../esp_hal_systimer/esp32c5/rom.systimer.ld | 5 +- .../esp_hal_systimer/esp32c6/rom.systimer.ld | 5 +- .../esp_hal_systimer/esp32c61/rom.systimer.ld | 5 +- .../esp_hal_systimer/esp32h2/rom.systimer.ld | 5 +- .../esp_hal_systimer/esp32h21/rom.systimer.ld | 5 +- .../esp_hal_systimer/esp32h4/rom.systimer.ld | 5 +- .../esp_hal_systimer/esp32p4/rom.systimer.ld | 5 +- .../esp_hal_systimer/esp32s31/rom.systimer.ld | 4 +- components/esp_hal_systimer/rom_patch.c | 21 +- components/esp_hw_support/etm/esp_etm.c | 10 + .../esp_hw_support/etm/include/esp_etm.h | 2 + .../esp_rom/esp32c5/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32c5/esp_rom_caps.h | 1 - .../esp_rom/esp32c6/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32c6/esp_rom_caps.h | 1 - .../esp_rom/esp32c61/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32c61/esp_rom_caps.h | 1 - .../esp_rom/esp32h2/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32h2/esp_rom_caps.h | 1 - .../esp_rom/esp32h21/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32h21/esp_rom_caps.h | 1 - .../esp_rom/esp32h4/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32h4/esp_rom_caps.h | 1 - .../esp_rom/esp32p4/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32p4/esp_rom_caps.h | 1 - .../main/test_systick_etm.c | 1 + components/hal/esp32c5/include/hal/etm_ll.h | 25 + components/hal/esp32c6/include/hal/etm_ll.h | 25 + components/hal/esp32c61/include/hal/etm_ll.h | 25 + components/hal/esp32h2/include/hal/etm_ll.h | 25 + components/hal/esp32h21/include/hal/etm_ll.h | 25 + components/hal/esp32h4/include/hal/etm_ll.h | 25 + components/hal/esp32p4/include/hal/etm_ll.h | 25 + components/hal/esp32s31/etm_periph.c | 44 + components/hal/esp32s31/include/hal/etm_ll.h | 169 +++ components/hal/include/hal/etm_types.h | 31 + .../soc/esp32c5/include/soc/clk_tree_defs.h | 7 + .../soc/esp32c6/include/soc/clk_tree_defs.h | 7 + .../soc/esp32c61/include/soc/clk_tree_defs.h | 7 + .../soc/esp32h2/include/soc/clk_tree_defs.h | 7 + .../soc/esp32h21/include/soc/clk_tree_defs.h | 7 + .../esp32h4/include/soc/Kconfig.soc_caps.in | 16 - .../soc/esp32h4/include/soc/clk_tree_defs.h | 7 + components/soc/esp32h4/include/soc/soc_caps.h | 6 - .../soc/esp32p4/include/soc/clk_tree_defs.h | 7 + .../esp32s31/include/soc/Kconfig.soc_caps.in | 16 + .../soc/esp32s31/include/soc/clk_tree_defs.h | 40 +- .../soc/esp32s31/include/soc/soc_caps.h | 11 +- .../soc/esp32s31/ld/esp32s31.peripherals.ld | 2 + .../esp32s31/register/soc/gpio_ext_struct.h | 1105 +---------------- .../esp32s31/register/soc/soc_etm_struct.h | 107 +- .../gptimer_capture_hc_sr04/README.md | 4 +- .../pytest_gptimer_capture_example.py | 2 +- 56 files changed, 754 insertions(+), 1268 deletions(-) create mode 100644 components/esp_hal_gpio/esp32s31/include/hal/gpio_etm_ll.h create mode 100644 components/hal/esp32s31/etm_periph.c create mode 100644 components/hal/esp32s31/include/hal/etm_ll.h create mode 100644 components/hal/include/hal/etm_types.h diff --git a/components/esp_driver_dma/test_apps/dma/main/test_gdma_etm.c b/components/esp_driver_dma/test_apps/dma/main/test_gdma_etm.c index 51e8a7d540..68d8fb4ac1 100644 --- a/components/esp_driver_dma/test_apps/dma/main/test_gdma_etm.c +++ b/components/esp_driver_dma/test_apps/dma/main/test_gdma_etm.c @@ -84,6 +84,7 @@ TEST_CASE("async_memcpy_eof_event", "[GDMA][ETM]") TEST_ESP_OK(esp_etm_del_event(mcp_event)); TEST_ESP_OK(esp_etm_del_channel(etm_channel_a)); TEST_ESP_OK(esp_async_memcpy_uninstall(mcp_ctx)); + TEST_ESP_OK(gpio_reset_pin(output_gpio)); free(src_buf); free(dst_buf); } diff --git a/components/esp_hal_gpio/esp32s31/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32s31/include/hal/gpio_caps.h index f475559875..a8b9168c75 100644 --- a/components/esp_hal_gpio/esp32s31/include/hal/gpio_caps.h +++ b/components/esp_hal_gpio/esp32s31/include/hal/gpio_caps.h @@ -7,3 +7,6 @@ #pragma once #define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32s31/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32s31/include/hal/gpio_etm_ll.h new file mode 100644 index 0000000000..d753142d09 --- /dev/null +++ b/components/esp_hal_gpio/esp32s31/include/hal/gpio_etm_ll.h @@ -0,0 +1,133 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/gpio_ext_struct.h" +#include "soc/soc_etm_source.h" + +#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch)) +#define GPIO_LL_ETM_EVENT_ID_NEG_EDGE(ch) (GPIO_EVT_CH0_FALL_EDGE + (ch)) +#define GPIO_LL_ETM_EVENT_ID_ANY_EDGE(ch) (GPIO_EVT_CH0_ANY_EDGE + (ch)) + +#define GPIO_LL_ETM_TASK_ID_SET(ch) (GPIO_TASK_CH0_SET + (ch)) +#define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) +#define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set which GPIO to be bound to the event channel + * + * @note Different channels can be bound to one GPIO + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @param gpio_num GPIO number + */ +static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num) +{ + dev->etm_event_chn_cfg[chan].etm_chn_event_sel = gpio_num; +} + +/** + * @brief Whether to enable the event channel + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable) +{ + dev->etm_event_chn_cfg[chan].etm_chn_event_en = enable; +} + +/** + * @brief Get which GPIO is bound to the event channel + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @return GPIO number + */ +static inline uint32_t gpio_ll_etm_event_channel_get_gpio(gpio_etm_dev_t *dev, uint32_t chan) +{ + return dev->etm_event_chn_cfg[chan].etm_chn_event_sel; +} + +/** + * @brief Set which GPIO to be bound to the task channel + * + * @note One channel can be bound to multiple different GPIOs + * + * @param dev Register base address + * @param chan GPIO ETM Task channel number + * @param gpio_num GPIO number + */ +static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; + reg_val &= ~(0x07 << (g_idx * 6)); + reg_val |= ((chan & 0x07) << (g_idx * 6)); + dev->etm_task_pn_cfg[g_p].val = reg_val; +} + +/** + * @brief Whether to enable the GPIO to be managed by the task channel + * + * @param dev Register base address + * @param gpio_num GPIO number + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_etm_enable_task_gpio(gpio_etm_dev_t *dev, uint32_t gpio_num, bool enable) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; + reg_val &= ~(0x01 << (g_idx * 6 + 5)); + reg_val |= ((enable & 0x01) << (g_idx * 6 + 5)); + dev->etm_task_pn_cfg[g_p].val = reg_val; +} + +/** + * @brief Check whether a GPIO has been enabled and managed by a task channel + * + * @param dev Register base address + * @param gpio_num GPIO number + * @return True if enabled, false otherwise + */ +static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_t gpio_num) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + return dev->etm_task_pn_cfg[g_p].val & (0x01 << (g_idx * 6 + 5)); +} + +/** + * @brief Get the channel number that the GPIO is bound to + * + * @param dev Register base address + * @param gpio_num GPIO number + * @return GPIO ETM Task channel number + */ +static inline uint32_t gpio_ll_etm_gpio_get_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + return (dev->etm_task_pn_cfg[g_p].val >> (g_idx * 6)) & 0x07; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_systimer/esp32c5/rom.systimer.ld b/components/esp_hal_systimer/esp32c5/rom.systimer.ld index a6b1a56f84..56efd88543 100644 --- a/components/esp_hal_systimer/esp32c5/rom.systimer.ld +++ b/components/esp_hal_systimer/esp32c5/rom.systimer.ld @@ -9,9 +9,8 @@ ***************************************/ /* Functions */ -/* The following ROM functions are commented out because they're patched in the rom_patch.c */ -/* systimer_hal_init = 0x400003d0; */ -/* systimer_hal_deinit = 0x400003d4; */ +rom_systimer_hal_init = 0x400003d0; +rom_systimer_hal_deinit = 0x400003d4; systimer_hal_set_tick_rate_ops = 0x400003d8; systimer_hal_get_counter_value = 0x400003dc; systimer_hal_get_time = 0x400003e0; diff --git a/components/esp_hal_systimer/esp32c6/rom.systimer.ld b/components/esp_hal_systimer/esp32c6/rom.systimer.ld index b0c32ea556..2f7448e24e 100644 --- a/components/esp_hal_systimer/esp32c6/rom.systimer.ld +++ b/components/esp_hal_systimer/esp32c6/rom.systimer.ld @@ -9,9 +9,8 @@ ***************************************/ /* Functions */ -/* The following ROM functions are commented out because they're patched in the rom_patch.c */ -/* systimer_hal_init = 0x400003c0; */ -/* systimer_hal_deinit = 0x400003c4; */ +rom_systimer_hal_init = 0x400003c0; +rom_systimer_hal_deinit = 0x400003c4; systimer_hal_set_tick_rate_ops = 0x400003c8; systimer_hal_get_counter_value = 0x400003cc; diff --git a/components/esp_hal_systimer/esp32c61/rom.systimer.ld b/components/esp_hal_systimer/esp32c61/rom.systimer.ld index ae669a6a3d..0417f1e58d 100644 --- a/components/esp_hal_systimer/esp32c61/rom.systimer.ld +++ b/components/esp_hal_systimer/esp32c61/rom.systimer.ld @@ -10,9 +10,8 @@ /* Functions */ -/* The following ROM functions are commented out because they're patched in the rom_patch.c */ -/* systimer_hal_init = 0x400003d0; */ -/* systimer_hal_deinit = 0x400003d4; */ +rom_systimer_hal_init = 0x400003d0; +rom_systimer_hal_deinit = 0x400003d4; systimer_hal_set_tick_rate_ops = 0x400003d8; systimer_hal_get_counter_value = 0x400003dc; diff --git a/components/esp_hal_systimer/esp32h2/rom.systimer.ld b/components/esp_hal_systimer/esp32h2/rom.systimer.ld index b4a675c8e2..6bb7431017 100644 --- a/components/esp_hal_systimer/esp32h2/rom.systimer.ld +++ b/components/esp_hal_systimer/esp32h2/rom.systimer.ld @@ -9,9 +9,8 @@ ***************************************/ /* Functions */ -/* The following ROM functions are commented out because they're patched in the rom_patch.c */ -/* systimer_hal_init = 0x400003b8; */ -/* systimer_hal_deinit = 0x400003bc; */ +rom_systimer_hal_init = 0x400003b8; +rom_systimer_hal_deinit = 0x400003bc; systimer_hal_set_tick_rate_ops = 0x400003c0; systimer_hal_get_counter_value = 0x400003c4; diff --git a/components/esp_hal_systimer/esp32h21/rom.systimer.ld b/components/esp_hal_systimer/esp32h21/rom.systimer.ld index 2a0e52bfe8..e415cbd7d9 100644 --- a/components/esp_hal_systimer/esp32h21/rom.systimer.ld +++ b/components/esp_hal_systimer/esp32h21/rom.systimer.ld @@ -9,9 +9,8 @@ ***************************************/ /* Functions */ -/* The following ROM functions are commented out because they're patched in the rom_patch.c */ -/* systimer_hal_init = 0x400003b8; */ -/* systimer_hal_deinit = 0x400003bc; */ +rom_systimer_hal_init = 0x400003b8; +rom_systimer_hal_deinit = 0x400003bc; systimer_hal_set_tick_rate_ops = 0x400003c0; systimer_hal_get_counter_value = 0x400003c4; systimer_hal_get_time = 0x400003c8; diff --git a/components/esp_hal_systimer/esp32h4/rom.systimer.ld b/components/esp_hal_systimer/esp32h4/rom.systimer.ld index 77a459c48d..275ebdaf26 100644 --- a/components/esp_hal_systimer/esp32h4/rom.systimer.ld +++ b/components/esp_hal_systimer/esp32h4/rom.systimer.ld @@ -18,9 +18,8 @@ ***************************************/ /* Functions */ -/* The following ROM functions are commented out because they're patched in the rom_patch.c */ -/* systimer_hal_init = 0x4000036c; */ -/* systimer_hal_deinit = 0x40000370; */ +rom_systimer_hal_init = 0x4000036c; +rom_systimer_hal_deinit = 0x40000370; systimer_hal_set_tick_rate_ops = 0x40000374; systimer_hal_get_counter_value = 0x40000378; diff --git a/components/esp_hal_systimer/esp32p4/rom.systimer.ld b/components/esp_hal_systimer/esp32p4/rom.systimer.ld index bf25d4a515..d5fcb61e6c 100644 --- a/components/esp_hal_systimer/esp32p4/rom.systimer.ld +++ b/components/esp_hal_systimer/esp32p4/rom.systimer.ld @@ -10,9 +10,8 @@ ***************************************/ /* Functions */ -/* The following ROM functions are commented out because they're patched in the rom_patch.c */ -/* systimer_hal_init = 0x4fc00228; */ -/* systimer_hal_deinit = 0x4fc0022c; */ +rom_systimer_hal_init = 0x4fc00228; +rom_systimer_hal_deinit = 0x4fc0022c; systimer_hal_set_tick_rate_ops = 0x4fc00230; systimer_hal_get_counter_value = 0x4fc00234; systimer_hal_get_time = 0x4fc00238; diff --git a/components/esp_hal_systimer/esp32s31/rom.systimer.ld b/components/esp_hal_systimer/esp32s31/rom.systimer.ld index 6e1c74ce74..b2854f6118 100644 --- a/components/esp_hal_systimer/esp32s31/rom.systimer.ld +++ b/components/esp_hal_systimer/esp32s31/rom.systimer.ld @@ -18,8 +18,8 @@ ***************************************/ /* Functions */ -systimer_hal_init = 0x2f800394; -systimer_hal_deinit = 0x2f800398; +rom_systimer_hal_init = 0x2f800394; +rom_systimer_hal_deinit = 0x2f800398; systimer_hal_set_tick_rate_ops = 0x2f80039c; systimer_hal_get_counter_value = 0x2f8003a0; systimer_hal_get_time = 0x2f8003a4; diff --git a/components/esp_hal_systimer/rom_patch.c b/components/esp_hal_systimer/rom_patch.c index 7ecec4a305..a92afc428f 100644 --- a/components/esp_hal_systimer/rom_patch.c +++ b/components/esp_hal_systimer/rom_patch.c @@ -9,10 +9,6 @@ * * Some chips have systimer HAL implementations in ROM that require patches. * This file provides the necessary patches when ROM implementation is used. - * - * For chips with ESP_ROM_SYSTIMER_INIT_PATCH defined (e.g., ESP32-C5, ESP32-C6, - * ESP32-H2, ESP32-P4), the ROM systimer_hal_init/deinit functions do not - * enable ETM, so we need to patch them here. */ #include @@ -20,18 +16,23 @@ #include "hal/systimer_hal.h" #include "hal/systimer_ll.h" -#if ESP_ROM_SYSTIMER_INIT_PATCH +#if !CONFIG_IDF_TARGET_ESP32C2 // esp32c2 has dedicated ROM patch + +extern void rom_systimer_hal_init(systimer_hal_context_t *hal); +extern void rom_systimer_hal_deinit(systimer_hal_context_t *hal); + void systimer_hal_init(systimer_hal_context_t *hal) { - hal->dev = &SYSTIMER; - systimer_ll_enable_clock(hal->dev, true); + // For chips with ROM systimer that does not enable ETM, the ROM functions are + // exposed with "rom_" prefix in rom.systimer.ld. We wrap them here to add + // the missing systimer_ll_enable_etm() call. + rom_systimer_hal_init(hal); systimer_ll_enable_etm(&SYSTIMER, true); } void systimer_hal_deinit(systimer_hal_context_t *hal) { systimer_ll_enable_etm(&SYSTIMER, false); - systimer_ll_enable_clock(hal->dev, false); - hal->dev = NULL; + rom_systimer_hal_deinit(hal); } -#endif // ESP_ROM_SYSTIMER_INIT_PATCH +#endif // !CONFIG_IDF_TARGET_ESP32C2 diff --git a/components/esp_hw_support/etm/esp_etm.c b/components/esp_hw_support/etm/esp_etm.c index a9195698af..dc2a8c7c57 100644 --- a/components/esp_hw_support/etm/esp_etm.c +++ b/components/esp_hw_support/etm/esp_etm.c @@ -113,6 +113,7 @@ static etm_group_t *etm_acquire_group_handle(int group_id) PERIPH_RCC_ATOMIC() { etm_ll_enable_bus_clock(group_id, true); etm_ll_reset_register(group_id); + etm_ll_enable_function_clock(group_id, true); } #if ETM_USE_RETENTION_LINK @@ -257,6 +258,15 @@ esp_err_t esp_etm_new_channel(const esp_etm_channel_config_t *config, esp_etm_ch int group_id = group->group_id; int chan_id = chan->chan_id; +#if ETM_LL_SUPPORT(CLOCK_SRC) + // set the clock source for the ETM group + etm_clock_source_t clk_src = config->clk_src; + if (clk_src == 0) { + clk_src = ETM_CLK_SRC_DEFAULT; + } + etm_ll_set_clock_source(group_id, clk_src); +#endif + // set the initial state to INIT atomic_init(&chan->fsm, ETM_CHAN_FSM_INIT); diff --git a/components/esp_hw_support/etm/include/esp_etm.h b/components/esp_hw_support/etm/include/esp_etm.h index daa97d76c3..9ee32b3aff 100644 --- a/components/esp_hw_support/etm/include/esp_etm.h +++ b/components/esp_hw_support/etm/include/esp_etm.h @@ -8,6 +8,7 @@ #include #include #include "esp_err.h" +#include "hal/etm_types.h" #ifdef __cplusplus extern "C" { @@ -32,6 +33,7 @@ typedef struct esp_etm_task_t *esp_etm_task_handle_t; * @brief ETM channel configuration */ typedef struct { + etm_clock_source_t clk_src; /*!< Clock source for the ETM channel */ /// Extra configuration flags for ETM channel struct etm_chan_flags { uint32_t allow_pd : 1; /*!< If set, driver allows the power domain to be powered off when system enters sleep mode. diff --git a/components/esp_rom/esp32c5/Kconfig.soc_caps.in b/components/esp_rom/esp32c5/Kconfig.soc_caps.in index e627affde0..6f6a881710 100644 --- a/components/esp_rom/esp32c5/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c5/Kconfig.soc_caps.in @@ -43,10 +43,6 @@ config ESP_ROM_HAS_HAL_SYSTIMER bool default y -config ESP_ROM_SYSTIMER_INIT_PATCH - bool - default y - config ESP_ROM_HAS_HEAP_TLSF bool default y diff --git a/components/esp_rom/esp32c5/esp_rom_caps.h b/components/esp_rom/esp32c5/esp_rom_caps.h index bead727fee..38985556de 100644 --- a/components/esp_rom/esp32c5/esp_rom_caps.h +++ b/components/esp_rom/esp32c5/esp_rom_caps.h @@ -16,7 +16,6 @@ #define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib #define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver #define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver -#define ESP_ROM_SYSTIMER_INIT_PATCH (1) // ROM version initializes SYSTIMER without ETM #define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library #define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check_pool() #define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk() diff --git a/components/esp_rom/esp32c6/Kconfig.soc_caps.in b/components/esp_rom/esp32c6/Kconfig.soc_caps.in index 2c703be2ba..faca1f8a51 100644 --- a/components/esp_rom/esp32c6/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c6/Kconfig.soc_caps.in @@ -43,10 +43,6 @@ config ESP_ROM_HAS_HAL_SYSTIMER bool default y -config ESP_ROM_SYSTIMER_INIT_PATCH - bool - default y - config ESP_ROM_HAS_HEAP_TLSF bool default y diff --git a/components/esp_rom/esp32c6/esp_rom_caps.h b/components/esp_rom/esp32c6/esp_rom_caps.h index 6b6d42ece3..8f87425c25 100644 --- a/components/esp_rom/esp32c6/esp_rom_caps.h +++ b/components/esp_rom/esp32c6/esp_rom_caps.h @@ -16,7 +16,6 @@ #define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib #define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver #define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver -#define ESP_ROM_SYSTIMER_INIT_PATCH (1) // ROM version initializes SYSTIMER without ETM #define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library #define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check_pool() #define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk() diff --git a/components/esp_rom/esp32c61/Kconfig.soc_caps.in b/components/esp_rom/esp32c61/Kconfig.soc_caps.in index 03e1199ac2..c4cc83ee95 100644 --- a/components/esp_rom/esp32c61/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c61/Kconfig.soc_caps.in @@ -43,10 +43,6 @@ config ESP_ROM_HAS_HAL_SYSTIMER bool default y -config ESP_ROM_SYSTIMER_INIT_PATCH - bool - default y - config ESP_ROM_HAS_HEAP_TLSF bool default y diff --git a/components/esp_rom/esp32c61/esp_rom_caps.h b/components/esp_rom/esp32c61/esp_rom_caps.h index ef17c1bdbf..0a956899b9 100644 --- a/components/esp_rom/esp32c61/esp_rom_caps.h +++ b/components/esp_rom/esp32c61/esp_rom_caps.h @@ -16,7 +16,6 @@ #define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib #define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver #define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver -#define ESP_ROM_SYSTIMER_INIT_PATCH (1) // ROM version initializes SYSTIMER without ETM #define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library #define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check_pool() #define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk() diff --git a/components/esp_rom/esp32h2/Kconfig.soc_caps.in b/components/esp_rom/esp32h2/Kconfig.soc_caps.in index 7fcb98e28d..fc338d9e1c 100644 --- a/components/esp_rom/esp32h2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h2/Kconfig.soc_caps.in @@ -35,10 +35,6 @@ config ESP_ROM_HAS_HAL_SYSTIMER bool default y -config ESP_ROM_SYSTIMER_INIT_PATCH - bool - default y - config ESP_ROM_HAS_HEAP_TLSF bool default y diff --git a/components/esp_rom/esp32h2/esp_rom_caps.h b/components/esp_rom/esp32h2/esp_rom_caps.h index 7166b5eac6..de2a08258e 100644 --- a/components/esp_rom/esp32h2/esp_rom_caps.h +++ b/components/esp_rom/esp32h2/esp_rom_caps.h @@ -14,7 +14,6 @@ #define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` #define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver #define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver -#define ESP_ROM_SYSTIMER_INIT_PATCH (1) // ROM version initializes SYSTIMER without ETM #define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library #define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check_pool() #define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk() diff --git a/components/esp_rom/esp32h21/Kconfig.soc_caps.in b/components/esp_rom/esp32h21/Kconfig.soc_caps.in index f4c78e645e..58457ed731 100644 --- a/components/esp_rom/esp32h21/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h21/Kconfig.soc_caps.in @@ -35,10 +35,6 @@ config ESP_ROM_HAS_HAL_SYSTIMER bool default y -config ESP_ROM_SYSTIMER_INIT_PATCH - bool - default y - config ESP_ROM_HAS_HEAP_TLSF bool default y diff --git a/components/esp_rom/esp32h21/esp_rom_caps.h b/components/esp_rom/esp32h21/esp_rom_caps.h index 4dcbac4149..74795293b8 100644 --- a/components/esp_rom/esp32h21/esp_rom_caps.h +++ b/components/esp_rom/esp32h21/esp_rom_caps.h @@ -14,7 +14,6 @@ #define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` #define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver #define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver -#define ESP_ROM_SYSTIMER_INIT_PATCH (1) // ROM version initializes SYSTIMER without ETM #define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library #define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk() #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table diff --git a/components/esp_rom/esp32h4/Kconfig.soc_caps.in b/components/esp_rom/esp32h4/Kconfig.soc_caps.in index 84dca246b2..b850566d83 100644 --- a/components/esp_rom/esp32h4/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h4/Kconfig.soc_caps.in @@ -35,10 +35,6 @@ config ESP_ROM_HAS_HAL_SYSTIMER bool default y -config ESP_ROM_SYSTIMER_INIT_PATCH - bool - default y - config ESP_ROM_HAS_HEAP_TLSF bool default y diff --git a/components/esp_rom/esp32h4/esp_rom_caps.h b/components/esp_rom/esp32h4/esp_rom_caps.h index 58db76b786..cbb6d9920d 100644 --- a/components/esp_rom/esp32h4/esp_rom_caps.h +++ b/components/esp_rom/esp32h4/esp_rom_caps.h @@ -14,7 +14,6 @@ #define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` #define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver #define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver -#define ESP_ROM_SYSTIMER_INIT_PATCH (1) // ROM version initializes SYSTIMER without ETM #define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library #define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk() #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table diff --git a/components/esp_rom/esp32p4/Kconfig.soc_caps.in b/components/esp_rom/esp32p4/Kconfig.soc_caps.in index 15a26f127a..c6c24fd471 100644 --- a/components/esp_rom/esp32p4/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32p4/Kconfig.soc_caps.in @@ -43,10 +43,6 @@ config ESP_ROM_HAS_HAL_SYSTIMER bool default y -config ESP_ROM_SYSTIMER_INIT_PATCH - bool - default y - config ESP_ROM_HAS_LAYOUT_TABLE bool default y diff --git a/components/esp_rom/esp32p4/esp_rom_caps.h b/components/esp_rom/esp32p4/esp_rom_caps.h index e42df199fd..d58a865a04 100644 --- a/components/esp_rom/esp32p4/esp_rom_caps.h +++ b/components/esp_rom/esp32p4/esp_rom_caps.h @@ -16,7 +16,6 @@ #define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib #define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver #define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver -#define ESP_ROM_SYSTIMER_INIT_PATCH (1) // ROM version initializes SYSTIMER without ETM #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock #define ESP_ROM_HAS_LP_ROM (1) // ROM also has a LP ROM placed in LP memory diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c index 58793d1824..8cc8ed18d4 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c @@ -60,4 +60,5 @@ TEST_CASE("rtos_systick_etm_event", "[etm]") TEST_ESP_OK(esp_etm_del_event(systick_event)); TEST_ESP_OK(esp_etm_channel_disable(etm_channel_a)); TEST_ESP_OK(esp_etm_del_channel(etm_channel_a)); + TEST_ESP_OK(gpio_reset_pin(output_gpio)); } diff --git a/components/hal/esp32c5/include/hal/etm_ll.h b/components/hal/esp32c5/include/hal/etm_ll.h index 7b03876980..7ea64391e3 100644 --- a/components/hal/esp32c5/include/hal/etm_ll.h +++ b/components/hal/esp32c5/include/hal/etm_ll.h @@ -11,6 +11,7 @@ #include #include "hal/assert.h" #include "hal/misc.h" +#include "hal/etm_types.h" #include "soc/soc_etm_struct.h" #include "soc/pcr_struct.h" @@ -42,6 +43,30 @@ static inline void etm_ll_enable_bus_clock(int group_id, bool enable) PCR.etm_conf.etm_clk_en = enable; } +/** + * @brief Enable the clock for ETM function + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void etm_ll_enable_function_clock(int group_id, bool enable) +{ + (void)group_id; + (void)enable; +} + +/** + * @brief Set the clock source for ETM + * + * @param group_id Group ID + * @param clk_src Clock source + */ +static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src) +{ + (void)group_id; + (void)clk_src; +} + /** * @brief Reset the ETM register * diff --git a/components/hal/esp32c6/include/hal/etm_ll.h b/components/hal/esp32c6/include/hal/etm_ll.h index 5338ccbebd..b27910deeb 100644 --- a/components/hal/esp32c6/include/hal/etm_ll.h +++ b/components/hal/esp32c6/include/hal/etm_ll.h @@ -11,6 +11,7 @@ #include #include "hal/assert.h" #include "hal/misc.h" +#include "hal/etm_types.h" #include "soc/soc_etm_struct.h" #include "soc/pcr_struct.h" @@ -39,6 +40,30 @@ static inline void etm_ll_enable_bus_clock(int group_id, bool enable) PCR.etm_conf.etm_clk_en = enable; } +/** + * @brief Enable the clock for ETM function + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void etm_ll_enable_function_clock(int group_id, bool enable) +{ + (void)group_id; + (void)enable; +} + +/** + * @brief Set the clock source for ETM + * + * @param group_id Group ID + * @param clk_src Clock source + */ +static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src) +{ + (void)group_id; + (void)clk_src; +} + /** * @brief Reset the ETM register * diff --git a/components/hal/esp32c61/include/hal/etm_ll.h b/components/hal/esp32c61/include/hal/etm_ll.h index 7b03876980..7ea64391e3 100644 --- a/components/hal/esp32c61/include/hal/etm_ll.h +++ b/components/hal/esp32c61/include/hal/etm_ll.h @@ -11,6 +11,7 @@ #include #include "hal/assert.h" #include "hal/misc.h" +#include "hal/etm_types.h" #include "soc/soc_etm_struct.h" #include "soc/pcr_struct.h" @@ -42,6 +43,30 @@ static inline void etm_ll_enable_bus_clock(int group_id, bool enable) PCR.etm_conf.etm_clk_en = enable; } +/** + * @brief Enable the clock for ETM function + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void etm_ll_enable_function_clock(int group_id, bool enable) +{ + (void)group_id; + (void)enable; +} + +/** + * @brief Set the clock source for ETM + * + * @param group_id Group ID + * @param clk_src Clock source + */ +static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src) +{ + (void)group_id; + (void)clk_src; +} + /** * @brief Reset the ETM register * diff --git a/components/hal/esp32h2/include/hal/etm_ll.h b/components/hal/esp32h2/include/hal/etm_ll.h index b4745a782f..6a0ad18c69 100644 --- a/components/hal/esp32h2/include/hal/etm_ll.h +++ b/components/hal/esp32h2/include/hal/etm_ll.h @@ -11,6 +11,7 @@ #include #include "hal/assert.h" #include "hal/misc.h" +#include "hal/etm_types.h" #include "soc/soc_etm_struct.h" #include "soc/pcr_struct.h" @@ -39,6 +40,30 @@ static inline void etm_ll_enable_bus_clock(int group_id, bool enable) PCR.etm_conf.etm_clk_en = enable; } +/** + * @brief Enable the clock for ETM function + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void etm_ll_enable_function_clock(int group_id, bool enable) +{ + (void)group_id; + (void)enable; +} + +/** + * @brief Set the clock source for ETM + * + * @param group_id Group ID + * @param clk_src Clock source + */ +static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src) +{ + (void)group_id; + (void)clk_src; +} + /** * @brief Reset the ETM register * diff --git a/components/hal/esp32h21/include/hal/etm_ll.h b/components/hal/esp32h21/include/hal/etm_ll.h index 149c3f30ed..5ce54945ce 100644 --- a/components/hal/esp32h21/include/hal/etm_ll.h +++ b/components/hal/esp32h21/include/hal/etm_ll.h @@ -11,6 +11,7 @@ #include #include "hal/assert.h" #include "hal/misc.h" +#include "hal/etm_types.h" #include "soc/soc_etm_struct.h" #include "soc/pcr_struct.h" @@ -39,6 +40,30 @@ static inline void etm_ll_enable_bus_clock(int group_id, bool enable) PCR.etm_conf.etm_clk_en = enable; } +/** + * @brief Enable the clock for ETM function + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void etm_ll_enable_function_clock(int group_id, bool enable) +{ + (void)group_id; + (void)enable; +} + +/** + * @brief Set the clock source for ETM + * + * @param group_id Group ID + * @param clk_src Clock source + */ +static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src) +{ + (void)group_id; + (void)clk_src; +} + /** * @brief Reset the ETM register * diff --git a/components/hal/esp32h4/include/hal/etm_ll.h b/components/hal/esp32h4/include/hal/etm_ll.h index 2d5293c791..f43899f3cb 100644 --- a/components/hal/esp32h4/include/hal/etm_ll.h +++ b/components/hal/esp32h4/include/hal/etm_ll.h @@ -11,6 +11,7 @@ #include #include "hal/assert.h" #include "hal/misc.h" +#include "hal/etm_types.h" #include "soc/soc_etm_struct.h" #include "soc/pcr_struct.h" @@ -42,6 +43,30 @@ static inline void etm_ll_enable_bus_clock(int group_id, bool enable) PCR.etm_conf.etm_clk_en = enable; } +/** + * @brief Enable the clock for ETM function + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void etm_ll_enable_function_clock(int group_id, bool enable) +{ + (void)group_id; + (void)enable; +} + +/** + * @brief Set the clock source for ETM + * + * @param group_id Group ID + * @param clk_src Clock source + */ +static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src) +{ + (void)group_id; + (void)clk_src; +} + /** * @brief Reset the ETM register * diff --git a/components/hal/esp32p4/include/hal/etm_ll.h b/components/hal/esp32p4/include/hal/etm_ll.h index 47ef4e2c39..15e451d0ea 100644 --- a/components/hal/esp32p4/include/hal/etm_ll.h +++ b/components/hal/esp32p4/include/hal/etm_ll.h @@ -11,6 +11,7 @@ #include #include "hal/assert.h" #include "hal/misc.h" +#include "hal/etm_types.h" #include "soc/soc_etm_struct.h" #include "soc/hp_sys_clkrst_struct.h" @@ -50,6 +51,30 @@ static inline void _etm_ll_enable_bus_clock(int group_id, bool enable) _etm_ll_enable_bus_clock(__VA_ARGS__); \ } while(0) +/** + * @brief Enable the clock for ETM function + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void etm_ll_enable_function_clock(int group_id, bool enable) +{ + (void)group_id; + (void)enable; +} + +/** + * @brief Set the clock source for ETM + * + * @param group_id Group ID + * @param clk_src Clock source + */ +static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src) +{ + (void)group_id; + (void)clk_src; +} + /** * @brief Reset the ETM module * diff --git a/components/hal/esp32s31/etm_periph.c b/components/hal/esp32s31/etm_periph.c new file mode 100644 index 0000000000..e0c6988c30 --- /dev/null +++ b/components/hal/esp32s31/etm_periph.c @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "hal/etm_periph.h" +#include "soc/soc_etm_reg.h" + +/** + * ETM Registers to be saved during sleep retention + * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG + */ +#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1) + +static const regdma_entries_config_t etm_regdma_entries[] = { + // backup stage: save the status of enabled channels + // restore stage: store the enabled channels + [0] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00), + SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01), + SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02), + SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, +}; + +const soc_etm_retention_desc_t soc_etm_retention_info[1] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_ETM0, + .regdma_entry_array = etm_regdma_entries, + .array_size = ARRAY_SIZE(etm_regdma_entries) + }, +}; diff --git a/components/hal/esp32s31/include/hal/etm_ll.h b/components/hal/esp32s31/include/hal/etm_ll.h new file mode 100644 index 0000000000..a793e5bafb --- /dev/null +++ b/components/hal/esp32s31/include/hal/etm_ll.h @@ -0,0 +1,169 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "hal/etm_types.h" +#include "soc/soc_etm_struct.h" +#include "soc/hp_sys_clkrst_struct.h" + +#define ETM_LL_GET(_attr) ETM_LL_ ## _attr +#define ETM_LL_SUPPORT(_feat) ETM_LL_SUPPORT_ ## _feat + +// Number of ETM instances +#define ETM_LL_INST_NUM 1 + +// Number of channels in each ETM instance +#define ETM_LL_CHANS_PER_INST 50 + +// Support to get and clear the status of the ETM event and task +#define ETM_LL_SUPPORT_STATUS_REG 1 + +// Support to set the clock source for ETM +#define ETM_LL_SUPPORT_CLOCK_SRC 1 + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the clock for ETM register + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void etm_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + HP_SYS_CLKRST.etm_ctrl0.reg_etm_apb_clk_en = enable; +} + +/** + * @brief Enable the clock for ETM function + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void etm_ll_enable_function_clock(int group_id, bool enable) +{ + (void)group_id; + HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_en = enable; +} + +/** + * @brief Set the clock source for ETM + * + * @param group_id Group ID + * @param clk_src Clock source + */ +static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src) +{ + (void)group_id; + switch (clk_src) { + case ETM_CLK_SRC_XTAL: + HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_sel = 0; + break; + case ETM_CLK_SRC_RC_FAST: + HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_sel = 1; + break; + case ETM_CLK_SRC_PLL_F80M: + HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_sel = 2; + break; + default: + HAL_ASSERT(false); + } +} + +/** + * @brief Reset the ETM register + * + * @param group_id Group ID + */ +static inline void etm_ll_reset_register(int group_id) +{ + (void)group_id; + HP_SYS_CLKRST.etm_ctrl0.reg_etm_rst_en = 1; + HP_SYS_CLKRST.etm_ctrl0.reg_etm_rst_en = 0; +} + +/** + * @brief Enable ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + */ +static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + hw->ch_ena_ad0_set.val = 1 << chan; + } else { + hw->ch_ena_ad1_set.val = 1 << (chan - 32); + } +} + +/** + * @brief Disable ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + */ +static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + hw->ch_ena_ad0_clr.val = 1 << chan; + } else { + hw->ch_ena_ad1_clr.val = 1 << (chan - 32); + } +} + +/** + * @brief Check whether the ETM channel is enabled or not + * + * @param hw ETM register base address + * @param chan Channel ID + * @return true if the channel is enabled, false otherwise + */ +static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + return hw->ch_ena_ad0.val & (1 << chan); + } else { + return hw->ch_ena_ad1.val & (1 << (chan - 32)); + } +} + +/** + * @brief Set the input event for the ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + * @param event Event ID + */ +static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event) +{ + hw->channel[chan].eid.chn_evt_id = event; +} + +/** + * @brief Set the output task for the ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + * @param task Task ID + */ +static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task) +{ + hw->channel[chan].tid.chn_task_id = task; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/etm_types.h b/components/hal/include/hal/etm_types.h new file mode 100644 index 0000000000..6b722be93a --- /dev/null +++ b/components/hal/include/hal/etm_types.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/soc_caps.h" +#include "soc/clk_tree_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if SOC_ETM_SUPPORTED +/** + * @brief ETM clock source + * @note User should select the clock source based on the power and resolution requirement + */ +typedef soc_periph_etm_clk_src_t etm_clock_source_t; +#else +/** + * @brief Default type + */ +typedef int etm_clock_source_t; +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index 8498b001de..461f3934c2 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -193,6 +193,13 @@ typedef enum { GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ } soc_periph_gptimer_clk_src_t; +//////////////////////////////////////////////////ETM/////////////////////////////////////////////////////////////////// + +/** + * @brief Type of ETM clock source + */ +typedef int soc_periph_etm_clk_src_t; + //////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32c6/include/soc/clk_tree_defs.h b/components/soc/esp32c6/include/soc/clk_tree_defs.h index 298699f4c7..5562f89fc9 100644 --- a/components/soc/esp32c6/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c6/include/soc/clk_tree_defs.h @@ -190,6 +190,13 @@ typedef enum { GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ } soc_periph_gptimer_clk_src_t; +//////////////////////////////////////////////////ETM/////////////////////////////////////////////////////////////////// + +/** + * @brief Type of ETM clock source + */ +typedef int soc_periph_etm_clk_src_t; + //////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32c61/include/soc/clk_tree_defs.h b/components/soc/esp32c61/include/soc/clk_tree_defs.h index a34a8cb5f0..283bc8637f 100644 --- a/components/soc/esp32c61/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c61/include/soc/clk_tree_defs.h @@ -180,6 +180,13 @@ typedef enum { GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ } soc_periph_gptimer_clk_src_t; +//////////////////////////////////////////////////ETM/////////////////////////////////////////////////////////////////// + +/** + * @brief Type of ETM clock source + */ +typedef int soc_periph_etm_clk_src_t; + //////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32h2/include/soc/clk_tree_defs.h b/components/soc/esp32h2/include/soc/clk_tree_defs.h index a251dd2676..cf5cf9f032 100644 --- a/components/soc/esp32h2/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h2/include/soc/clk_tree_defs.h @@ -199,6 +199,13 @@ typedef enum { GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default choice */ } soc_periph_gptimer_clk_src_t; +//////////////////////////////////////////////////ETM/////////////////////////////////////////////////////////////////// + +/** + * @brief Type of ETM clock source + */ +typedef int soc_periph_etm_clk_src_t; + //////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32h21/include/soc/clk_tree_defs.h b/components/soc/esp32h21/include/soc/clk_tree_defs.h index 53eef1d9af..b0932637e9 100644 --- a/components/soc/esp32h21/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h21/include/soc/clk_tree_defs.h @@ -188,6 +188,13 @@ typedef enum { #endif } soc_periph_gptimer_clk_src_t; +//////////////////////////////////////////////////ETM/////////////////////////////////////////////////////////////////// + +/** + * @brief Type of ETM clock source + */ +typedef int soc_periph_etm_clk_src_t; + //////////////////////////////////////////////////SDM/////////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index c3bc266397..10f1cf84e6 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -363,14 +363,6 @@ config SOC_GDMA_SUPPORT_SLEEP_RETENTION bool default y -config SOC_ETM_GROUPS - int - default 1 - -config SOC_ETM_CHANNELS_PER_GROUP - int - default 50 - config SOC_MODEM_SUPPORT_ETM bool default y @@ -403,14 +395,6 @@ config SOC_GPIO_SUPPORT_ETM bool default y -config SOC_GPIO_ETM_EVENTS_PER_GROUP - int - default 8 - -config SOC_GPIO_ETM_TASKS_PER_GROUP - int - default 8 - config SOC_LP_IO_CLOCK_IS_INDEPENDENT bool default y diff --git a/components/soc/esp32h4/include/soc/clk_tree_defs.h b/components/soc/esp32h4/include/soc/clk_tree_defs.h index 62c55acf43..2298555289 100644 --- a/components/soc/esp32h4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h4/include/soc/clk_tree_defs.h @@ -190,6 +190,13 @@ typedef enum { #endif } soc_periph_gptimer_clk_src_t; +//////////////////////////////////////////////////ETM/////////////////////////////////////////////////////////////////// + +/** + * @brief Type of ETM clock source + */ +typedef int soc_periph_etm_clk_src_t; + //////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index e0232b54aa..f6de827b8b 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -196,10 +196,6 @@ #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 -/*-------------------------- ETM CAPS --------------------------------------*/ -#define SOC_ETM_GROUPS 1U // Number of ETM groups -#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group - /*-------------------------- MODEM CAPS --------------------------------------*/ #define SOC_MODEM_SUPPORT_ETM 1 @@ -217,8 +213,6 @@ // GPIO peripheral has the ETM extension #define SOC_GPIO_SUPPORT_ETM 1 -#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8 -#define SOC_GPIO_ETM_TASKS_PER_GROUP 8 // Target has the full LP IO subsystem diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h index 8bbbc97a6b..25c529d1ad 100644 --- a/components/soc/esp32p4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h @@ -232,6 +232,13 @@ typedef enum { #endif // SOC_CLK_TREE_SUPPORTED } soc_periph_gptimer_clk_src_t; +//////////////////////////////////////////////////ETM/////////////////////////////////////////////////////////////////// + +/** + * @brief Type of ETM clock source + */ +typedef int soc_periph_etm_clk_src_t; + //////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in index 079ebb4901..30ca98505b 100644 --- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in @@ -35,6 +35,10 @@ config SOC_MCPWM_SUPPORTED bool default y +config SOC_ETM_SUPPORTED + bool + default y + config SOC_ASYNC_MEMCPY_SUPPORTED bool default y @@ -259,6 +263,10 @@ config SOC_GPIO_SUPPORT_PIN_HYS_FILTER bool default y +config SOC_GPIO_SUPPORT_ETM + bool + default y + config SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE bool default y @@ -311,6 +319,10 @@ config SOC_SDM_SUPPORT_SLEEP_RETENTION bool default y +config SOC_ETM_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_LEDC_CHANNEL_NUM int default 6 @@ -367,6 +379,10 @@ config SOC_MEMSPI_ENCRYPTION_ALIGNMENT int default 16 +config SOC_SYSTIMER_SUPPORT_ETM + bool + default y + config SOC_TIMER_SUPPORT_ETM bool default y diff --git a/components/soc/esp32s31/include/soc/clk_tree_defs.h b/components/soc/esp32s31/include/soc/clk_tree_defs.h index bd695b943f..fd187b18ca 100644 --- a/components/soc/esp32s31/include/soc/clk_tree_defs.h +++ b/components/soc/esp32s31/include/soc/clk_tree_defs.h @@ -186,11 +186,7 @@ typedef enum { * } * @endcode */ -#if SOC_CLK_TREE_SUPPORTED #define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} -#else -#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_XTAL} -#endif /** * @brief Type of GPTimer clock source @@ -199,25 +195,17 @@ typedef enum { GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ -#if SOC_CLK_TREE_SUPPORTED GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ -#else - GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ -#endif // SOC_CLK_TREE_SUPPORTED } soc_periph_gptimer_clk_src_t; -/** - * @brief Type of Timer Group clock source, reserved for the legacy timer group driver - */ +//////////////////////////////////////////////////ETM/////////////////////////////////////////////////////////////////// + typedef enum { - TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */ - TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ -#if SOC_CLK_TREE_SUPPORTED - TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */ -#else - TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Timer group clock source default choice is XTAL */ -#endif // SOC_CLK_TREE_SUPPORTED -} soc_periph_tg_clk_src_legacy_t; + ETM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + ETM_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + ETM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + ETM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ +} soc_periph_etm_clk_src_t; //////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// @@ -306,6 +294,8 @@ typedef enum { MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL 40 MHz as the default clock choice */ } soc_periph_mwdt_clk_src_t; +//////////////////////////////////////////////////SDM///////////////////////////////////////////////////////////////// + /** * @brief Sigma Delta Modulator clock source */ @@ -315,6 +305,18 @@ typedef enum { SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ } soc_periph_sdm_clk_src_t; +//////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// + +/** + * @brief Glitch filter clock source + */ + +typedef enum { + GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ + GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ +} soc_periph_glitch_filter_clk_src_t; + //////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h index 607d4fc5b3..a7cc293796 100644 --- a/components/soc/esp32s31/include/soc/soc_caps.h +++ b/components/soc/esp32s31/include/soc/soc_caps.h @@ -41,7 +41,7 @@ // #define SOC_LCDCAM_RGB_LCD_SUPPORTED 1 // TODO: [ESP32S31] IDF-14722 #define SOC_MCPWM_SUPPORTED 1 // #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32S31] IDF-14719 -// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14724 +#define SOC_ETM_SUPPORTED 1 // #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32S31] IDF-14711 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 // #define SOC_USB_OTG_SUPPORTED 1 // TODO: [ESP32S31] IDF-14701 @@ -166,9 +166,7 @@ #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 // GPIO peripheral has the ETM extension -// #define SOC_GPIO_SUPPORT_ETM 1 // TODO: [ESP32S31] IDF-14786 -// #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8 // TODO: [ESP32S31] IDF-14786 -// #define SOC_GPIO_ETM_TASKS_PER_GROUP 8 // TODO: [ESP32S31] IDF-14786 +#define SOC_GPIO_SUPPORT_ETM 1 // GPIO0~7 on ESP32S31 can support chip deep sleep wakeup // #define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1) // TODO: [ESP32S31] IDF-14643 @@ -206,6 +204,9 @@ /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 +/*-------------------------- ETM CAPS -----------------------------------*/ +#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 + /*-------------------------- LEDC CAPS ---------------------------------------*/ // TODO: [ESP32S31] IDF-14709 #define SOC_LEDC_CHANNEL_NUM (6) @@ -237,7 +238,7 @@ #define SOC_MEMSPI_ENCRYPTION_ALIGNMENT 16 /*!< 16-byte alignment restriction to mem addr and size if encryption is enabled */ /*-------------------------- SYSTIMER CAPS ----------------------------------*/ -// TODO: [ESP32S31] IDF-14693 +#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ #define SOC_TIMER_SUPPORT_ETM (1) diff --git a/components/soc/esp32s31/ld/esp32s31.peripherals.ld b/components/soc/esp32s31/ld/esp32s31.peripherals.ld index 0c5bb04371..c97ee08b38 100644 --- a/components/soc/esp32s31/ld/esp32s31.peripherals.ld +++ b/components/soc/esp32s31/ld/esp32s31.peripherals.ld @@ -73,6 +73,8 @@ PROVIDE ( IO_MUX = 0x20582000 ); PROVIDE ( GPIO = 0x20583000 ); PROVIDE ( GPIO_EXT = 0x20583E00 ); PROVIDE ( SDM = 0x20583E04 ); +PROVIDE ( GLITCH_FILTER = 0x20583E08 ); +PROVIDE ( GPIO_ETM = 0x20583F18 ); PROVIDE ( MSPI_IOMUX = 0x20584000 ); PROVIDE ( HP_SYSTEM = 0x20586000 ); PROVIDE ( HP_SYS_CLKRST = 0x20587000 ); diff --git a/components/soc/esp32s31/register/soc/gpio_ext_struct.h b/components/soc/esp32s31/register/soc/gpio_ext_struct.h index 319deb37b3..a9ac8bc271 100644 --- a/components/soc/esp32s31/register/soc/gpio_ext_struct.h +++ b/components/soc/esp32s31/register/soc/gpio_ext_struct.h @@ -22,8 +22,8 @@ typedef union { * 1: Enable * %\label{fielddesc:GPIOSDSPISWAP}- [GPIOSD_SPI_SWAP] Reserved. */ - uint32_t sigmadelta_clk_en:1; - uint32_t reserved_1:31; + uint32_t sigmadelta_clk_en: 1; + uint32_t reserved_1: 31; }; uint32_t val; } gpio_ext_sigmadelta_misc_reg_t; @@ -36,12 +36,12 @@ typedef union { /** sdn_in : R/W; bitpos: [7:0]; default: 0; * Configures the duty cycle of sigma delta modulation output. */ - uint32_t sdn_in:8; + uint32_t sdn_in: 8; /** sdn_prescale : R/W; bitpos: [15:8]; default: 255; * Configures the divider value to divide IO MUX operating clock. */ - uint32_t sdn_prescale:8; - uint32_t reserved_16:16; + uint32_t sdn_prescale: 8; + uint32_t reserved_16: 16; }; uint32_t val; } gpio_ext_sigmadeltan_reg_t; @@ -53,13 +53,13 @@ typedef union { */ typedef union { struct { - /** filter_ch0_en : R/W; bitpos: [0]; default: 0; + /** filter_chn_en : R/W; bitpos: [0]; default: 0; * Configures whether or not to enable channel n of Glitch Filter. * 0: Not enable * 1: Enable */ - uint32_t filter_ch0_en:1; - /** filter_ch0_input_io_num : R/W; bitpos: [7:1]; default: 0; + uint32_t filter_chn_en: 1; + /** filter_chn_input_io_num : R/W; bitpos: [7:1]; default: 0; * Configures to select the input GPIO for Glitch Filter. * 0: Select GPIO0 * 1: Select GPIO1 @@ -68,21 +68,21 @@ typedef union { * 62: Select GPIO62 * 63 ~ 127: Reserved */ - uint32_t filter_ch0_input_io_num:7; - /** filter_ch0_window_thres : R/W; bitpos: [13:8]; default: 0; + uint32_t filter_chn_input_io_num: 7; + /** filter_chn_window_thres : R/W; bitpos: [13:8]; default: 0; * Configures the window threshold for Glitch Filter. The window threshold should be * less than or equal to GPIOSD_FILTER_CHn_WINDOW_WIDTH. * %see DOC-4768 * Measurement unit: IO MUX operating clock cycle */ - uint32_t filter_ch0_window_thres:6; - /** filter_ch0_window_width : R/W; bitpos: [19:14]; default: 0; + uint32_t filter_chn_window_thres: 6; + /** filter_chn_window_width : R/W; bitpos: [19:14]; default: 0; * Configures the window width for Glitch Filter. The effective value of window width * is 0 ~ 63. * Measurement unit: IO MUX operating clock cycle */ - uint32_t filter_ch0_window_width:6; - uint32_t reserved_20:12; + uint32_t filter_chn_window_width: 6; + uint32_t reserved_20: 12; }; uint32_t val; } gpio_ext_glitch_filter_chn_reg_t; @@ -103,20 +103,20 @@ typedef union { * 62: Select GPIO62 * 63 ~ 127: Reserved */ - uint32_t etm_chn_event_sel:7; + uint32_t etm_chn_event_sel: 7; /** etm_chn_event_en : R/W; bitpos: [7]; default: 0; * Configures whether or not to enable ETM event send. * 0: Not enable * 1: Enable */ - uint32_t etm_chn_event_en:1; - uint32_t reserved_8:24; + uint32_t etm_chn_event_en: 1; + uint32_t reserved_8: 24; }; uint32_t val; } gpio_ext_etm_event_chn_cfg_reg_t; -/** Type of etm_task_p0_cfg register - * GPIO selection register 0 for ETM +/** Type of etm_task_pn_cfg register + * GPIO selection register n for ETM */ typedef union { struct { @@ -127,14 +127,14 @@ typedef union { * ...... * 7: Select channel 7 */ - uint32_t etm_task_gpio0_sel:3; - uint32_t reserved_3:2; + uint32_t etm_task_gpio0_sel: 3; + uint32_t reserved_3: 2; /** etm_task_gpio0_en : R/W; bitpos: [5]; default: 0; * Configures whether or not to enable GPIO0 to response ETM task. * 0: Not enable * 1: Enable */ - uint32_t etm_task_gpio0_en:1; + uint32_t etm_task_gpio0_en: 1; /** etm_task_gpio1_sel : R/W; bitpos: [8:6]; default: 0; * Configures to select an ETM task channel for GPIO1. * 0: Select channel 0 @@ -142,14 +142,14 @@ typedef union { * ...... * 7: Select channel 7 */ - uint32_t etm_task_gpio1_sel:3; - uint32_t reserved_9:2; + uint32_t etm_task_gpio1_sel: 3; + uint32_t reserved_9: 2; /** etm_task_gpio1_en : R/W; bitpos: [11]; default: 0; * Configures whether or not to enable GPIO1 to response ETM task. * 0: Not enable * 1: Enable */ - uint32_t etm_task_gpio1_en:1; + uint32_t etm_task_gpio1_en: 1; /** etm_task_gpio2_sel : R/W; bitpos: [14:12]; default: 0; * Configures to select an ETM task channel for GPIO2. * 0: Select channel 0 @@ -157,14 +157,14 @@ typedef union { * ...... * 7: Select channel 7 */ - uint32_t etm_task_gpio2_sel:3; - uint32_t reserved_15:2; + uint32_t etm_task_gpio2_sel: 3; + uint32_t reserved_15: 2; /** etm_task_gpio2_en : R/W; bitpos: [17]; default: 0; * Configures whether or not to enable GPIO2 to response ETM task. * 0: Not enable * 1: Enable */ - uint32_t etm_task_gpio2_en:1; + uint32_t etm_task_gpio2_en: 1; /** etm_task_gpio3_sel : R/W; bitpos: [20:18]; default: 0; * Configures to select an ETM task channel for GPIO3. * 0: Select channel 0 @@ -172,14 +172,14 @@ typedef union { * ...... * 7: Select channel 7 */ - uint32_t etm_task_gpio3_sel:3; - uint32_t reserved_21:2; + uint32_t etm_task_gpio3_sel: 3; + uint32_t reserved_21: 2; /** etm_task_gpio3_en : R/W; bitpos: [23]; default: 0; * Configures whether or not to enable GPIO3 to response ETM task. * 0: Not enable * 1: Enable */ - uint32_t etm_task_gpio3_en:1; + uint32_t etm_task_gpio3_en: 1; /** etm_task_gpio4_sel : R/W; bitpos: [26:24]; default: 0; * Configures to select an ETM task channel for GPIO4. * 0: Select channel 0 @@ -187,1009 +187,18 @@ typedef union { * ...... * 7: Select channel 7 */ - uint32_t etm_task_gpio4_sel:3; - uint32_t reserved_27:2; + uint32_t etm_task_gpio4_sel: 3; + uint32_t reserved_27: 2; /** etm_task_gpio4_en : R/W; bitpos: [29]; default: 0; * Configures whether or not to enable GPIO4 to response ETM task. * 0: Not enable * 1: Enable */ - uint32_t etm_task_gpio4_en:1; - uint32_t reserved_30:2; + uint32_t etm_task_gpio4_en: 1; + uint32_t reserved_30: 2; }; uint32_t val; -} gpio_ext_etm_task_p0_cfg_reg_t; - -/** Type of etm_task_p1_cfg register - * GPIO selection register 1 for ETM - */ -typedef union { - struct { - /** etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO5. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio5_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO5 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio5_en:1; - /** etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO6. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio6_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio6_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO6 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio6_en:1; - /** etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO7. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio7_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio7_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO7 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio7_en:1; - /** etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO8. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio8_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio8_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO8 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio8_en:1; - /** etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO9. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio9_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio9_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO9 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio9_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p1_cfg_reg_t; - -/** Type of etm_task_p2_cfg register - * GPIO selection register 2 for ETM - */ -typedef union { - struct { - /** etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO10. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio10_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio10_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO10 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio10_en:1; - /** etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO11. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio11_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio11_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO11 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio11_en:1; - /** etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO12. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio12_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio12_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO12 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio12_en:1; - /** etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO13. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio13_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio13_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO13 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio13_en:1; - /** etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO14. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio14_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio14_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO14 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio14_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p2_cfg_reg_t; - -/** Type of etm_task_p3_cfg register - * GPIO selection register 3 for ETM - */ -typedef union { - struct { - /** etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO15. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio15_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio15_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO15 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio15_en:1; - /** etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO16. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio16_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio16_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO16 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio16_en:1; - /** etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO17. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio17_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio17_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO17 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio17_en:1; - /** etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO18. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio18_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio18_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO18 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio18_en:1; - /** etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO19. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio19_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio19_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO19 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio19_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p3_cfg_reg_t; - -/** Type of etm_task_p4_cfg register - * GPIO selection register 4 for ETM - */ -typedef union { - struct { - /** etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO20. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio20_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio20_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO20 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio20_en:1; - /** etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO21. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio21_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio21_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO21 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio21_en:1; - /** etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO22. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio22_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio22_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO22 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio22_en:1; - /** etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO23. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio23_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio23_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO23 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio23_en:1; - /** etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO24. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio24_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio24_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO24 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio24_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p4_cfg_reg_t; - -/** Type of etm_task_p5_cfg register - * GPIO selection register 5 for ETM - */ -typedef union { - struct { - /** etm_task_gpio25_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO25. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio25_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio25_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO25 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio25_en:1; - /** etm_task_gpio26_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO26. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio26_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio26_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO26 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio26_en:1; - /** etm_task_gpio27_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO27. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio27_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio27_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO27 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio27_en:1; - /** etm_task_gpio28_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO28. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio28_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio28_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO28 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio28_en:1; - /** etm_task_gpio29_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO29. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio29_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio29_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO29 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio29_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p5_cfg_reg_t; - -/** Type of etm_task_p6_cfg register - * GPIO selection register 6 for ETM - */ -typedef union { - struct { - /** etm_task_gpio30_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO30. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio30_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio30_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO30 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio30_en:1; - /** etm_task_gpio31_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO31. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio31_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio31_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO31 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio31_en:1; - /** etm_task_gpio32_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO32. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio32_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio32_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO32 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio32_en:1; - /** etm_task_gpio33_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO33. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio33_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio33_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO33 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio33_en:1; - /** etm_task_gpio34_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO34. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio34_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio34_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO34 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio34_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p6_cfg_reg_t; - -/** Type of etm_task_p7_cfg register - * GPIO selection register 7 for ETM - */ -typedef union { - struct { - /** etm_task_gpio35_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO35. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio35_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio35_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO35 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio35_en:1; - /** etm_task_gpio36_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO36. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio36_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio36_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO36 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio36_en:1; - /** etm_task_gpio37_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO37. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio37_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio37_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO37 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio37_en:1; - /** etm_task_gpio38_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO38. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio38_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio38_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO38 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio38_en:1; - /** etm_task_gpio39_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO39. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio39_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio39_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO39 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio39_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p7_cfg_reg_t; - -/** Type of etm_task_p8_cfg register - * GPIO selection register 8 for ETM - */ -typedef union { - struct { - /** etm_task_gpio40_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO40. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio40_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio40_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO40 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio40_en:1; - /** etm_task_gpio41_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO41. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio41_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio41_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO41 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio41_en:1; - /** etm_task_gpio42_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO42. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio42_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio42_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO42 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio42_en:1; - /** etm_task_gpio43_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO43. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio43_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio43_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO43 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio43_en:1; - /** etm_task_gpio44_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO44. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio44_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio44_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO44 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio44_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p8_cfg_reg_t; - -/** Type of etm_task_p9_cfg register - * GPIO selection register 9 for ETM - */ -typedef union { - struct { - /** etm_task_gpio45_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO45. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio45_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio45_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO45 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio45_en:1; - /** etm_task_gpio46_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO46. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio46_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio46_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO46 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio46_en:1; - /** etm_task_gpio47_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO47. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio47_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio47_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO47 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio47_en:1; - /** etm_task_gpio48_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO48. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio48_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio48_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO48 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio48_en:1; - /** etm_task_gpio49_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO49. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio49_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio49_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO49 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio49_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p9_cfg_reg_t; - -/** Type of etm_task_p10_cfg register - * GPIO selection register 10 for ETM - */ -typedef union { - struct { - /** etm_task_gpio50_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO50. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio50_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio50_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO50 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio50_en:1; - /** etm_task_gpio51_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO51. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio51_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio51_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO51 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio51_en:1; - /** etm_task_gpio52_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO52. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio52_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio52_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO52 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio52_en:1; - /** etm_task_gpio53_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO53. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio53_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio53_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO53 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio53_en:1; - /** etm_task_gpio54_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO54. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio54_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio54_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO54 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio54_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p10_cfg_reg_t; - -/** Type of etm_task_p11_cfg register - * GPIO selection register 11 for ETM - */ -typedef union { - struct { - /** etm_task_gpio55_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO55. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio55_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio55_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO55 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio55_en:1; - /** etm_task_gpio56_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO56. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio56_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio56_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO56 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio56_en:1; - /** etm_task_gpio57_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO57. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio57_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio57_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO57 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio57_en:1; - /** etm_task_gpio58_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO58. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio58_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio58_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO58 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio58_en:1; - /** etm_task_gpio59_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO59. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio59_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio59_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO59 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio59_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p11_cfg_reg_t; - -/** Type of etm_task_p12_cfg register - * GPIO selection register 12 for ETM - */ -typedef union { - struct { - /** etm_task_gpio60_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO60. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio60_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio60_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO60 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio60_en:1; - /** etm_task_gpio61_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO61. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio61_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio61_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO61 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio61_en:1; - /** etm_task_gpio62_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO62. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t etm_task_gpio62_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio62_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO62 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t etm_task_gpio62_en:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} gpio_ext_etm_task_p12_cfg_reg_t; - +} gpio_ext_etm_task_pn_cfg_reg_t; /** Group: Version Register */ /** Type of version register @@ -1200,51 +209,47 @@ typedef union { /** date : R/W; bitpos: [27:0]; default: 38830416; * Version control register. */ - uint32_t date:28; - uint32_t reserved_28:4; + uint32_t date: 28; + uint32_t reserved_28: 4; }; uint32_t val; } gpio_ext_version_reg_t; - typedef struct gpio_sd_dev_t { + volatile uint32_t reserved; volatile gpio_ext_sigmadelta_misc_reg_t misc; volatile gpio_ext_sigmadeltan_reg_t channel[8]; } gpio_sd_dev_t; +typedef struct gpio_etm_dev_t { + volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; + uint32_t reserved_080[8]; + volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[13]; +} gpio_etm_dev_t; + +typedef struct { + volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8]; +} gpio_glitch_filter_dev_t; + typedef struct { - uint32_t reserved_000; volatile gpio_sd_dev_t sigma_delta; uint32_t reserved_028[44]; - volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8]; + volatile gpio_glitch_filter_dev_t glitch_filter; uint32_t reserved_0f8[8]; - volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; - uint32_t reserved_138[8]; - volatile gpio_ext_etm_task_p0_cfg_reg_t etm_task_p0_cfg; - volatile gpio_ext_etm_task_p1_cfg_reg_t etm_task_p1_cfg; - volatile gpio_ext_etm_task_p2_cfg_reg_t etm_task_p2_cfg; - volatile gpio_ext_etm_task_p3_cfg_reg_t etm_task_p3_cfg; - volatile gpio_ext_etm_task_p4_cfg_reg_t etm_task_p4_cfg; - volatile gpio_ext_etm_task_p5_cfg_reg_t etm_task_p5_cfg; - volatile gpio_ext_etm_task_p6_cfg_reg_t etm_task_p6_cfg; - volatile gpio_ext_etm_task_p7_cfg_reg_t etm_task_p7_cfg; - volatile gpio_ext_etm_task_p8_cfg_reg_t etm_task_p8_cfg; - volatile gpio_ext_etm_task_p9_cfg_reg_t etm_task_p9_cfg; - volatile gpio_ext_etm_task_p10_cfg_reg_t etm_task_p10_cfg; - volatile gpio_ext_etm_task_p11_cfg_reg_t etm_task_p11_cfg; - volatile gpio_ext_etm_task_p12_cfg_reg_t etm_task_p12_cfg; + volatile gpio_etm_dev_t etm; uint32_t reserved_18c[28]; volatile gpio_ext_version_reg_t version; } gpio_ext_dev_t; +extern gpio_sd_dev_t SDM; +extern gpio_glitch_filter_dev_t GLITCH_FILTER; +extern gpio_etm_dev_t GPIO_ETM; +extern gpio_ext_dev_t GPIO_EXT; #ifndef __cplusplus _Static_assert(sizeof(gpio_ext_dev_t) == 0x200, "Invalid size of gpio_ext_dev_t structure"); #endif -extern gpio_sd_dev_t SDM; -extern gpio_ext_dev_t GPIO_EXT; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s31/register/soc/soc_etm_struct.h b/components/soc/esp32s31/register/soc/soc_etm_struct.h index 1133364cdc..f3af33536b 100644 --- a/components/soc/esp32s31/register/soc/soc_etm_struct.h +++ b/components/soc/esp32s31/register/soc/soc_etm_struct.h @@ -10547,113 +10547,17 @@ typedef union { } soc_etm_date_reg_t; -typedef struct { +typedef struct soc_etm_dev_t { volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0; volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set; volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr; volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1; volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set; volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr; - volatile soc_etm_chn_evt_id_reg_t ch0_evt_id; - volatile soc_etm_chn_task_id_reg_t ch0_task_id; - volatile soc_etm_chn_evt_id_reg_t ch1_evt_id; - volatile soc_etm_chn_task_id_reg_t ch1_task_id; - volatile soc_etm_chn_evt_id_reg_t ch2_evt_id; - volatile soc_etm_chn_task_id_reg_t ch2_task_id; - volatile soc_etm_chn_evt_id_reg_t ch3_evt_id; - volatile soc_etm_chn_task_id_reg_t ch3_task_id; - volatile soc_etm_chn_evt_id_reg_t ch4_evt_id; - volatile soc_etm_chn_task_id_reg_t ch4_task_id; - volatile soc_etm_chn_evt_id_reg_t ch5_evt_id; - volatile soc_etm_chn_task_id_reg_t ch5_task_id; - volatile soc_etm_chn_evt_id_reg_t ch6_evt_id; - volatile soc_etm_chn_task_id_reg_t ch6_task_id; - volatile soc_etm_chn_evt_id_reg_t ch7_evt_id; - volatile soc_etm_chn_task_id_reg_t ch7_task_id; - volatile soc_etm_chn_evt_id_reg_t ch8_evt_id; - volatile soc_etm_chn_task_id_reg_t ch8_task_id; - volatile soc_etm_chn_evt_id_reg_t ch9_evt_id; - volatile soc_etm_chn_task_id_reg_t ch9_task_id; - volatile soc_etm_chn_evt_id_reg_t ch10_evt_id; - volatile soc_etm_chn_task_id_reg_t ch10_task_id; - volatile soc_etm_chn_evt_id_reg_t ch11_evt_id; - volatile soc_etm_chn_task_id_reg_t ch11_task_id; - volatile soc_etm_chn_evt_id_reg_t ch12_evt_id; - volatile soc_etm_chn_task_id_reg_t ch12_task_id; - volatile soc_etm_chn_evt_id_reg_t ch13_evt_id; - volatile soc_etm_chn_task_id_reg_t ch13_task_id; - volatile soc_etm_chn_evt_id_reg_t ch14_evt_id; - volatile soc_etm_chn_task_id_reg_t ch14_task_id; - volatile soc_etm_chn_evt_id_reg_t ch15_evt_id; - volatile soc_etm_chn_task_id_reg_t ch15_task_id; - volatile soc_etm_chn_evt_id_reg_t ch16_evt_id; - volatile soc_etm_chn_task_id_reg_t ch16_task_id; - volatile soc_etm_chn_evt_id_reg_t ch17_evt_id; - volatile soc_etm_chn_task_id_reg_t ch17_task_id; - volatile soc_etm_chn_evt_id_reg_t ch18_evt_id; - volatile soc_etm_chn_task_id_reg_t ch18_task_id; - volatile soc_etm_chn_evt_id_reg_t ch19_evt_id; - volatile soc_etm_chn_task_id_reg_t ch19_task_id; - volatile soc_etm_chn_evt_id_reg_t ch20_evt_id; - volatile soc_etm_chn_task_id_reg_t ch20_task_id; - volatile soc_etm_chn_evt_id_reg_t ch21_evt_id; - volatile soc_etm_chn_task_id_reg_t ch21_task_id; - volatile soc_etm_chn_evt_id_reg_t ch22_evt_id; - volatile soc_etm_chn_task_id_reg_t ch22_task_id; - volatile soc_etm_chn_evt_id_reg_t ch23_evt_id; - volatile soc_etm_chn_task_id_reg_t ch23_task_id; - volatile soc_etm_chn_evt_id_reg_t ch24_evt_id; - volatile soc_etm_chn_task_id_reg_t ch24_task_id; - volatile soc_etm_chn_evt_id_reg_t ch25_evt_id; - volatile soc_etm_chn_task_id_reg_t ch25_task_id; - volatile soc_etm_chn_evt_id_reg_t ch26_evt_id; - volatile soc_etm_chn_task_id_reg_t ch26_task_id; - volatile soc_etm_chn_evt_id_reg_t ch27_evt_id; - volatile soc_etm_chn_task_id_reg_t ch27_task_id; - volatile soc_etm_chn_evt_id_reg_t ch28_evt_id; - volatile soc_etm_chn_task_id_reg_t ch28_task_id; - volatile soc_etm_chn_evt_id_reg_t ch29_evt_id; - volatile soc_etm_chn_task_id_reg_t ch29_task_id; - volatile soc_etm_chn_evt_id_reg_t ch30_evt_id; - volatile soc_etm_chn_task_id_reg_t ch30_task_id; - volatile soc_etm_chn_evt_id_reg_t ch31_evt_id; - volatile soc_etm_chn_task_id_reg_t ch31_task_id; - volatile soc_etm_chn_evt_id_reg_t ch32_evt_id; - volatile soc_etm_chn_task_id_reg_t ch32_task_id; - volatile soc_etm_chn_evt_id_reg_t ch33_evt_id; - volatile soc_etm_chn_task_id_reg_t ch33_task_id; - volatile soc_etm_chn_evt_id_reg_t ch34_evt_id; - volatile soc_etm_chn_task_id_reg_t ch34_task_id; - volatile soc_etm_chn_evt_id_reg_t ch35_evt_id; - volatile soc_etm_chn_task_id_reg_t ch35_task_id; - volatile soc_etm_chn_evt_id_reg_t ch36_evt_id; - volatile soc_etm_chn_task_id_reg_t ch36_task_id; - volatile soc_etm_chn_evt_id_reg_t ch37_evt_id; - volatile soc_etm_chn_task_id_reg_t ch37_task_id; - volatile soc_etm_chn_evt_id_reg_t ch38_evt_id; - volatile soc_etm_chn_task_id_reg_t ch38_task_id; - volatile soc_etm_chn_evt_id_reg_t ch39_evt_id; - volatile soc_etm_chn_task_id_reg_t ch39_task_id; - volatile soc_etm_chn_evt_id_reg_t ch40_evt_id; - volatile soc_etm_chn_task_id_reg_t ch40_task_id; - volatile soc_etm_chn_evt_id_reg_t ch41_evt_id; - volatile soc_etm_chn_task_id_reg_t ch41_task_id; - volatile soc_etm_chn_evt_id_reg_t ch42_evt_id; - volatile soc_etm_chn_task_id_reg_t ch42_task_id; - volatile soc_etm_chn_evt_id_reg_t ch43_evt_id; - volatile soc_etm_chn_task_id_reg_t ch43_task_id; - volatile soc_etm_chn_evt_id_reg_t ch44_evt_id; - volatile soc_etm_chn_task_id_reg_t ch44_task_id; - volatile soc_etm_chn_evt_id_reg_t ch45_evt_id; - volatile soc_etm_chn_task_id_reg_t ch45_task_id; - volatile soc_etm_chn_evt_id_reg_t ch46_evt_id; - volatile soc_etm_chn_task_id_reg_t ch46_task_id; - volatile soc_etm_chn_evt_id_reg_t ch47_evt_id; - volatile soc_etm_chn_task_id_reg_t ch47_task_id; - volatile soc_etm_chn_evt_id_reg_t ch48_evt_id; - volatile soc_etm_chn_task_id_reg_t ch48_task_id; - volatile soc_etm_chn_evt_id_reg_t ch49_evt_id; - volatile soc_etm_chn_task_id_reg_t ch49_task_id; + volatile struct { + soc_etm_chn_evt_id_reg_t eid; + soc_etm_chn_task_id_reg_t tid; + } channel[50]; volatile soc_etm_evt_st0_reg_t evt_st0; volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr; volatile soc_etm_evt_st1_reg_t evt_st1; @@ -10708,6 +10612,7 @@ typedef struct { volatile soc_etm_date_reg_t date; } soc_etm_dev_t; +extern soc_etm_dev_t SOC_ETM; #ifndef __cplusplus _Static_assert(sizeof(soc_etm_dev_t) == 0x278, "Invalid size of soc_etm_dev_t structure"); diff --git a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md index 50398ef216..287d10e0c0 100644 --- a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md +++ b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | -| ----------------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S31 | +| ----------------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | --------- | # HC-SR04 Example based on GPTimer Capture and ETM diff --git a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py index 559955d047..ce0ad1a38b 100644 --- a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py +++ b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py @@ -6,7 +6,7 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.generic -@idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32p4'], indirect=['target']) +@idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32p4', 'esp32s31'], indirect=['target']) def test_gptimer_capture(dut: Dut) -> None: dut.expect_exact('Configure trig gpio') dut.expect_exact('Configure echo gpio')