diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
index 1be2362fd1..42dc2dab4d 100644
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
@@ -237,6 +237,12 @@ esp_err_t bootloader_init_spi_flash(void)
     bootloader_init_mspi_clock();
 
     bootloader_init_flash_configure();
+
+#if CONFIG_BOOTLOADER_FLASH_DC_AWARE
+    // Reset flash, clear volatile bits DC[0:1]. Make it work under default mode to boot.
+    bootloader_spi_flash_reset();
+#endif
+
     bootloader_spi_flash_resume();
     if ((void*)bootloader_flash_unlock != (void*)bootloader_flash_unlock_default) {
         ESP_EARLY_LOGD(TAG, "Using overridden bootloader_flash_unlock");
diff --git a/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h b/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h
index a4a623e598..c213631d96 100644
--- a/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h
+++ b/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h
@@ -40,6 +40,8 @@
 #define MSPI_TIMING_PSRAM_MODULE_CLOCK               40
 #elif CONFIG_SPIRAM_SPEED_80M
 #define MSPI_TIMING_PSRAM_MODULE_CLOCK               80
+#else //CONFIG_SPIRAM_SPEED_120M
+#define MSPI_TIMING_PSRAM_MODULE_CLOCK               120
 #endif
 #else   //Disable PSRAM
 #define MSPI_TIMING_PSRAM_MODULE_CLOCK               10      //Define this to 10MHz
@@ -49,17 +51,30 @@
 #define MSPI_TIMING_PSRAM_NEEDS_TUNING               (MSPI_TIMING_PSRAM_MODULE_CLOCK > 40)
 #endif
 
-///////////////////////////////////// FLASH/PSRAM CORE CLOCK /////////////////////////////////////
-#if ((CONFIG_ESPTOOLPY_FLASHFREQ_80M && !CONFIG_SPIRAM) || (CONFIG_ESPTOOLPY_FLASHFREQ_80M && CONFIG_SPIRAM_SPEED_80M))
+///////////////////////////////////// FLASH CORE CLOCK /////////////////////////////////////
+//FLASH 80M
+#if CONFIG_ESPTOOLPY_FLASHFREQ_80M
 #define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ      80
-#define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ      80
 #define MSPI_TIMING_FLASH_CONSECUTIVE_LEN_MAX        6
-#else
-#define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ      240
-#define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ      240
+#endif
+
+//FLASH 120M
+#if CONFIG_ESPTOOLPY_FLASHFREQ_120M
+#define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ      120
 #define MSPI_TIMING_FLASH_CONSECUTIVE_LEN_MAX        4
 #endif
 
+///////////////////////////////////// PSRAM CORE CLOCK /////////////////////////////////////
+//PSRAM 80M
+#if CONFIG_SPIRAM_SPEED_80M
+#define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ      80
+#endif
+
+//PSRAM 120M
+#if CONFIG_SPIRAM_SPEED_120M
+#define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ      120
+#endif  //PSRAM 120M DTR
+
 //------------------------------------------Determine the Core Clock-----------------------------------------------//
 /**
  * @note
@@ -101,10 +116,10 @@ ESP_STATIC_ASSERT(MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_FLASH_MO
 /**
  * Timing Tuning Parameters
  */
-//FLASH: core clock 240M, module clock 120M, STR mode
-#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE         {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {2, 1, 3}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {2, 1, 4}}
-#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE           12
-#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE    4
+//FLASH: core clock 120M, module clock 120M, STR mode
+#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE         {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {2, 1, 3}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {2, 1, 4}}
+#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE           12
+#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE    4
 
 //FLASH: core clock 240M, module clock 80M, STR mode
 #define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_80M_STR_MODE          {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}}
@@ -116,10 +131,10 @@ ESP_STATIC_ASSERT(MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_FLASH_MO
 #define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE             14
 #define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE      4
 
-//PSRAM: core clock 240M, module clock 120M, STR mode
-#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE         {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {2, 1, 3}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {2, 1, 4}}
-#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE           12
-#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE    4
+//PSRAM: core clock 120M, module clock 120M, STR mode
+#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE         {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {2, 1, 3}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {2, 1, 4}}
+#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE           12
+#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE    4
 
 //PSRAM: core clock 240M, module clock 80M, STR mode
 #define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_80M_STR_MODE          {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}}
diff --git a/components/esp_hw_support/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_flash_delay.c b/components/esp_hw_support/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_flash_delay.c
index 3d158a1afc..d1e9938c63 100644
--- a/components/esp_hw_support/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_flash_delay.c
+++ b/components/esp_hw_support/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_flash_delay.c
@@ -73,7 +73,7 @@ void mspi_timing_config_flash_set_tuning_regs(const void *configs, uint8_t id)
 //-------------------------------------------FLASH Read/Write------------------------------------------//
 void mspi_timing_config_flash_read_data(uint8_t *buf, uint32_t addr, uint32_t len)
 {
-#if CONFIG_ESPTOOLPY_FLASHMODE_QIO
+#if CONFIG_ESPTOOLPY_FLASHMODE_QIO && CONFIG_SPI_FLASH_HPM_ON
     g_rom_spiflash_dummy_len_plus[1] = 4;
 #endif
     esp_rom_spiflash_read(addr, (uint32_t *)buf, len);
@@ -164,7 +164,7 @@ void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi)
         //Won't touch SPI1 registers
     }
 
-#if MSPI_TIMING_FLASH_NEEDS_TUNING && CONFIG_ESPTOOLPY_FLASHMODE_QIO
+#if MSPI_TIMING_FLASH_NEEDS_TUNING && CONFIG_ESPTOOLPY_FLASHMODE_QIO && CONFIG_SPI_FLASH_HPM_ON
     mspi_timing_ll_set_flash_user_dummy(MSPI_TIMING_LL_MSPI_ID_0, 7);
 #endif
 
diff --git a/components/esp_hw_support/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_mspi_delay.c b/components/esp_hw_support/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_mspi_delay.c
index ca3efb5b49..9404717201 100644
--- a/components/esp_hw_support/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_mspi_delay.c
+++ b/components/esp_hw_support/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_mspi_delay.c
@@ -87,6 +87,9 @@ void mspi_timing_config_flash_set_tuning_regs(const void *configs, uint8_t id)
 //-------------------------------------------FLASH Read/Write------------------------------------------//
 void mspi_timing_config_flash_read_data(uint8_t *buf, uint32_t addr, uint32_t len)
 {
+#if CONFIG_ESPTOOLPY_FLASHMODE_QIO && CONFIG_SPI_FLASH_HPM_ON
+    g_rom_spiflash_dummy_len_plus[1] = 4;
+#endif
     if (bootloader_flash_is_octal_mode_enabled()) {
         // note that in spi_flash_read API, there is a wait-idle stage, since flash can only be read in idle state.
         // but after we change the timing settings, we might not read correct idle status via RDSR.
@@ -353,6 +356,10 @@ void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi)
         //Won't touch SPI1 registers
     }
 
+#if MSPI_TIMING_FLASH_NEEDS_TUNING && CONFIG_ESPTOOLPY_FLASHMODE_QIO && CONFIG_SPI_FLASH_HPM_ON
+    mspi_timing_ll_set_flash_user_dummy(MSPI_TIMING_LL_MSPI_ID_0, 7);
+#endif
+
     int spi1_usr_dummy = 0;
     int spi1_extra_dummy = 0;
     int spi0_usr_dummy = 0;
@@ -382,7 +389,7 @@ void mspi_timing_psram_config_set_tuning_regs(bool control_both_mspi)
 }
 
 /*-------------------------------------------------------------------------------------------------
- * To let upper lay (spi_flash_timing_tuning.c) to know the necessary timing registers
+ * To let upper layer (spi_flash_timing_tuning.c) to know the necessary timing registers
  *-------------------------------------------------------------------------------------------------*/
 /**
  * Get the SPI1 Flash CS timing setting. The setup time and hold time are both realistic cycles.
diff --git a/components/esp_psram/esp32c5/Kconfig.spiram b/components/esp_psram/esp32c5/Kconfig.spiram
index a27b718f9c..3b5b8ef65b 100644
--- a/components/esp_psram/esp32c5/Kconfig.spiram
+++ b/components/esp_psram/esp32c5/Kconfig.spiram
@@ -23,6 +23,8 @@ menu "SPI RAM config"
         help
             Select the speed for the SPI RAM chip.
 
+        config SPIRAM_SPEED_120M
+            bool "120MHz clock speed"
         config SPIRAM_SPEED_80M
             bool "80MHz clock speed"
         config SPIRAM_SPEED_40M
@@ -31,6 +33,7 @@ menu "SPI RAM config"
 
     config SPIRAM_SPEED
         int
+        default 120 if SPIRAM_SPEED_120M
         default 80 if SPIRAM_SPEED_80M
         default 40 if SPIRAM_SPEED_40M
 
diff --git a/components/hal/esp32c5/include/hal/mspi_ll.h b/components/hal/esp32c5/include/hal/mspi_ll.h
index f99937641f..8bfa16f90f 100644
--- a/components/hal/esp32c5/include/hal/mspi_ll.h
+++ b/components/hal/esp32c5/include/hal/mspi_ll.h
@@ -230,6 +230,18 @@ static inline void mspi_timing_ll_set_flash_extra_dummy(uint8_t mspi_id, uint8_t
     REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
 }
 
+/**
+ * Set MSPI Flash user dummy
+ *
+ * @param mspi_id      SPI0 / SPI1
+ * @param user_dummy   user dummy
+ */
+__attribute__((always_inline))
+static inline void mspi_timing_ll_set_flash_user_dummy(uint8_t mspi_id, uint8_t user_dummy)
+{
+    REG_SET_FIELD(SPI_MEM_USER1_REG(mspi_id), SPI_MEM_USR_DUMMY_CYCLELEN, user_dummy);
+}
+
 /**
  * Get MSPI flash dummy info
  *
diff --git a/components/spi_flash/Kconfig b/components/spi_flash/Kconfig
index 79dc5c50d7..9f61909ba1 100644
--- a/components/spi_flash/Kconfig
+++ b/components/spi_flash/Kconfig
@@ -36,7 +36,7 @@ menu "Main Flash configuration"
         choice SPI_FLASH_HPM
             prompt "High Performance Mode (READ DOCS FIRST, > 80MHz)"
             # Currently, only esp32s3 allows high performance mode.
-            depends on (IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32P4) && !ESPTOOLPY_OCT_FLASH
+            depends on (IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32P4 || IDF_TARGET_ESP32C5) && !ESPTOOLPY_OCT_FLASH
             default SPI_FLASH_HPM_AUTO
             help
                 Whether the High Performance Mode of Flash is enabled. As an optional feature, user needs to manually
diff --git a/components/spi_flash/esp32c5/Kconfig.flash_freq b/components/spi_flash/esp32c5/Kconfig.flash_freq
index 2eac2e2f95..ac9875af5a 100644
--- a/components/spi_flash/esp32c5/Kconfig.flash_freq
+++ b/components/spi_flash/esp32c5/Kconfig.flash_freq
@@ -1,6 +1,8 @@
 choice ESPTOOLPY_FLASHFREQ
     prompt "Flash SPI speed"
     default ESPTOOLPY_FLASHFREQ_80M
+    config ESPTOOLPY_FLASHFREQ_120M
+        bool "120 MHz"
     config ESPTOOLPY_FLASHFREQ_80M
         bool "80 MHz"
     config ESPTOOLPY_FLASHFREQ_40M