From 6e0878131e4c984bb8439d89aaa47d8cc01757ee Mon Sep 17 00:00:00 2001 From: Tomas Rezucha Date: Fri, 17 Apr 2026 13:47:12 +0200 Subject: [PATCH 1/2] Revert "fix(esp_hw_support): Fix deepsleep leakage after initializing USB HS phy" This reverts commit 7107177e2dd499feff61cfdd37d8010d49a27627. --- .../include/esp_private/sleep_usb.h | 15 ++------------- components/esp_hw_support/sleep_usb.c | 18 ++---------------- components/esp_hw_support/usb_phy/usb_phy.c | 11 ----------- .../esp32p4/include/soc/Kconfig.soc_caps.in | 4 ---- components/soc/esp32p4/include/soc/soc_caps.h | 1 - 5 files changed, 4 insertions(+), 45 deletions(-) diff --git a/components/esp_hw_support/include/esp_private/sleep_usb.h b/components/esp_hw_support/include/esp_private/sleep_usb.h index 40a12d59c5..5e49a0d4a1 100644 --- a/components/esp_hw_support/include/esp_private/sleep_usb.h +++ b/components/esp_hw_support/include/esp_private/sleep_usb.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,8 +13,7 @@ extern "C" { #endif -#if SOC_USB_OTG_SUPPORTED -#if SOC_PM_SUPPORT_CNNT_PD +#if SOC_USB_OTG_SUPPORTED && SOC_PM_SUPPORT_CNNT_PD /** * @brief Backup usb OTG phy bus_clock / stoppclk configuration and * before light sleep to avoid current leakage @@ -27,16 +26,6 @@ void sleep_usb_otg_phy_backup_and_disable(void); void sleep_usb_otg_phy_restore(void); #endif -#if SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO -/** - * @brief The DP/DM part of the UTMI PHY circuit of esp32p4 that converts logic level to digital - * has no power off isolation, which will cause leakage when entering deepsleep. - * This problem can be workarounded by enabling USB-OTG's HNP (Host negotiation protocol) - * to enable DM pull-down to suppress leakage. - */ -void sleep_usb_suppress_deepsleep_leakage(void); -#endif -#endif #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/sleep_usb.c b/components/esp_hw_support/sleep_usb.c index a1de41e013..d672fa2343 100644 --- a/components/esp_hw_support/sleep_usb.c +++ b/components/esp_hw_support/sleep_usb.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,15 +7,11 @@ #include #include "soc/soc_caps.h" #include "esp_private/sleep_usb.h" -#include "esp_attr.h" -#if SOC_USB_OTG_SUPPORTED && (SOC_PM_SUPPORT_CNNT_PD || SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO) +#if SOC_USB_OTG_SUPPORTED && SOC_PM_SUPPORT_CNNT_PD #include "hal/usb_utmi_ll.h" #include "hal/usb_dwc_ll.h" -#endif -#if SOC_USB_OTG_SUPPORTED -#if SOC_PM_SUPPORT_CNNT_PD static bool s_usb_utmi_bus_clock_state, s_usb_utmi_stoppclk_state, s_usb_dwc_bvalid_override; void sleep_usb_otg_phy_backup_and_disable(void) @@ -41,13 +37,3 @@ void sleep_usb_otg_phy_restore(void) } } #endif - -#if SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO -void sleep_usb_suppress_deepsleep_leakage(void) -{ - if (_usb_utmi_ll_bus_clock_is_enabled()) { - usb_dwc_ll_gusbcfg_en_hnp_cap(&USB_DWC_HS); - } -} -#endif -#endif diff --git a/components/esp_hw_support/usb_phy/usb_phy.c b/components/esp_hw_support/usb_phy/usb_phy.c index c95e764d04..c7e40a6805 100644 --- a/components/esp_hw_support/usb_phy/usb_phy.c +++ b/components/esp_hw_support/usb_phy/usb_phy.c @@ -20,11 +20,6 @@ #include "hal/gpio_ll.h" #include "soc/soc_caps.h" -#if SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO -#include "esp_private/sleep_usb.h" -#include "esp_sleep.h" -#endif - #if (SOC_USB_FSLS_PHY_NUM > 0) #define USB_PHY_FSLS_EXT_PHY_SUPPORTED USB_WRAP_LL_EXT_PHY_SUPPORTED #else @@ -246,12 +241,6 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r } #endif -#if SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO - if (phy_target == USB_PHY_TARGET_UTMI) { - esp_deep_sleep_register_hook(&sleep_usb_suppress_deepsleep_leakage); - } -#endif - ESP_RETURN_ON_FALSE(config, ESP_ERR_INVALID_ARG, USBPHY_TAG, "config argument is invalid"); ESP_RETURN_ON_FALSE(phy_target < USB_PHY_TARGET_MAX, ESP_ERR_INVALID_ARG, USBPHY_TAG, "specified PHY argument is invalid"); ESP_RETURN_ON_FALSE(config->controller < USB_PHY_CTRL_MAX, ESP_ERR_INVALID_ARG, USBPHY_TAG, "specified source argument is invalid"); diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 346fb42b51..d128ae121e 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -1171,10 +1171,6 @@ config SOC_USB_UTMI_PHY_NUM int default 1 -config SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO - bool - default y - config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH int default 16 diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index d2eb31aad4..be6ff60a34 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -434,7 +434,6 @@ // USB PHY Caps #define SOC_USB_UTMI_PHY_NUM (1U) -#define SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO 1 /*-------------------------- PARLIO CAPS --------------------------------------*/ #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */ From d02062f91442aaf2637b95c8c2fbe1f93c815f4a Mon Sep 17 00:00:00 2001 From: Tomas Rezucha Date: Fri, 17 Apr 2026 14:21:00 +0200 Subject: [PATCH 2/2] refactor(esp_hal_usb): Enable HNP on HNP-capable controllers --- .../esp32h4/include/hal/usb_dwc_ll.h | 37 ++++++++++++++-- .../esp32p4/include/hal/usb_dwc_ll.h | 42 +++++++++++++++---- .../esp32s2/include/hal/usb_dwc_ll.h | 37 ++++++++++++++-- .../esp32s3/include/hal/usb_dwc_ll.h | 37 ++++++++++++++-- .../esp32s31/include/hal/usb_dwc_ll.h | 42 +++++++++++++++---- components/esp_hal_usb/usb_dwc_hal.c | 10 ++++- 6 files changed, 173 insertions(+), 32 deletions(-) diff --git a/components/esp_hal_usb/esp32h4/include/hal/usb_dwc_ll.h b/components/esp_hal_usb/esp32h4/include/hal/usb_dwc_ll.h index 3a29756850..a3b0ceca9a 100644 --- a/components/esp_hal_usb/esp32h4/include/hal/usb_dwc_ll.h +++ b/components/esp_hal_usb/esp32h4/include/hal/usb_dwc_ll.h @@ -107,6 +107,17 @@ extern "C" { #define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1) #define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0) +/* + * OTG mode configuration values for the GHWCFG2 register + */ +#define USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG 0 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG 1 +#define USB_DWC_LL_GHWCFG_OTG_MODE_OTG 2 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE 3 +#define USB_DWC_LL_GHWCFG_OTG_MODE_DEVICE 4 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST 5 +#define USB_DWC_LL_GHWCFG_OTG_MODE_HOST 6 + /* * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode. * Each QTD describes one transfer. Scatter gather mode will automatically split @@ -202,14 +213,14 @@ static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw) hw->gusbcfg_reg.forcehstmode = 1; } -static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw) +static inline void usb_dwc_ll_gusbcfg_set_hnp_cap(usb_dwc_dev_t *hw, bool hnp_cap) { - hw->gusbcfg_reg.hnpcap = 0; + hw->gusbcfg_reg.hnpcap = hnp_cap; } -static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw) +static inline void usb_dwc_ll_gusbcfg_set_srp_cap(usb_dwc_dev_t *hw, bool srp_cap) { - hw->gusbcfg_reg.srpcap = 0; + hw->gusbcfg_reg.srpcap = srp_cap; } static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal) @@ -348,6 +359,24 @@ static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw) // --------------------------- GHWCFGx Register -------------------------------- +static inline void usb_dwc_ll_ghwcfg_get_hnp_srp_cap(usb_dwc_dev_t *hw, bool *hnp_cap, bool *srp_cap) +{ + const uint32_t otg_mode = hw->ghwcfg2_reg.otgmode; + + if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG) { + *hnp_cap = true; + *srp_cap = true; + } else if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG || + otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE || + otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST) { + *hnp_cap = false; + *srp_cap = true; + } else { + *hnp_cap = false; + *srp_cap = false; + } +} + static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw) { return hw->ghwcfg3_reg.dfifodepth; diff --git a/components/esp_hal_usb/esp32p4/include/hal/usb_dwc_ll.h b/components/esp_hal_usb/esp32p4/include/hal/usb_dwc_ll.h index d79133ca5d..6b34cdc72f 100644 --- a/components/esp_hal_usb/esp32p4/include/hal/usb_dwc_ll.h +++ b/components/esp_hal_usb/esp32p4/include/hal/usb_dwc_ll.h @@ -109,6 +109,17 @@ extern "C" { #define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1) #define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0) +/* + * OTG mode configuration values for the GHWCFG2 register + */ +#define USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG 0 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG 1 +#define USB_DWC_LL_GHWCFG_OTG_MODE_OTG 2 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE 3 +#define USB_DWC_LL_GHWCFG_OTG_MODE_DEVICE 4 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST 5 +#define USB_DWC_LL_GHWCFG_OTG_MODE_HOST 6 + /* * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode. * Each QTD describes one transfer. Scatter gather mode will automatically split @@ -204,19 +215,14 @@ static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw) hw->gusbcfg_reg.forcehstmode = 1; } -static inline void usb_dwc_ll_gusbcfg_en_hnp_cap(usb_dwc_dev_t *hw) +static inline void usb_dwc_ll_gusbcfg_set_hnp_cap(usb_dwc_dev_t *hw, bool hnp_cap) { - hw->gusbcfg_reg.hnpcap = 1; + hw->gusbcfg_reg.hnpcap = hnp_cap; } -static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw) +static inline void usb_dwc_ll_gusbcfg_set_srp_cap(usb_dwc_dev_t *hw, bool srp_cap) { - hw->gusbcfg_reg.hnpcap = 0; -} - -static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw) -{ - hw->gusbcfg_reg.srpcap = 0; + hw->gusbcfg_reg.srpcap = srp_cap; } static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal) @@ -371,6 +377,24 @@ static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw) // --------------------------- GHWCFGx Register -------------------------------- +static inline void usb_dwc_ll_ghwcfg_get_hnp_srp_cap(usb_dwc_dev_t *hw, bool *hnp_cap, bool *srp_cap) +{ + const uint32_t otg_mode = hw->ghwcfg2_reg.otgmode; + + if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG) { + *hnp_cap = true; + *srp_cap = true; + } else if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG || + otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE || + otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST) { + *hnp_cap = false; + *srp_cap = true; + } else { + *hnp_cap = false; + *srp_cap = false; + } +} + static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw) { return hw->ghwcfg3_reg.dfifodepth; diff --git a/components/esp_hal_usb/esp32s2/include/hal/usb_dwc_ll.h b/components/esp_hal_usb/esp32s2/include/hal/usb_dwc_ll.h index 5ba840c13e..f09b5b3913 100644 --- a/components/esp_hal_usb/esp32s2/include/hal/usb_dwc_ll.h +++ b/components/esp_hal_usb/esp32s2/include/hal/usb_dwc_ll.h @@ -107,6 +107,17 @@ extern "C" { #define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1) #define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0) +/* + * OTG mode configuration values for the GHWCFG2 register + */ +#define USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG 0 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG 1 +#define USB_DWC_LL_GHWCFG_OTG_MODE_OTG 2 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE 3 +#define USB_DWC_LL_GHWCFG_OTG_MODE_DEVICE 4 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST 5 +#define USB_DWC_LL_GHWCFG_OTG_MODE_HOST 6 + /* * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode. * Each QTD describes one transfer. Scatter gather mode will automatically split @@ -202,14 +213,14 @@ static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw) hw->gusbcfg_reg.forcehstmode = 1; } -static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw) +static inline void usb_dwc_ll_gusbcfg_set_hnp_cap(usb_dwc_dev_t *hw, bool hnp_cap) { - hw->gusbcfg_reg.hnpcap = 0; + hw->gusbcfg_reg.hnpcap = hnp_cap; } -static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw) +static inline void usb_dwc_ll_gusbcfg_set_srp_cap(usb_dwc_dev_t *hw, bool srp_cap) { - hw->gusbcfg_reg.srpcap = 0; + hw->gusbcfg_reg.srpcap = srp_cap; } static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal) @@ -346,6 +357,24 @@ static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw) // --------------------------- GHWCFGx Register -------------------------------- +static inline void usb_dwc_ll_ghwcfg_get_hnp_srp_cap(usb_dwc_dev_t *hw, bool *hnp_cap, bool *srp_cap) +{ + const uint32_t otg_mode = hw->ghwcfg2_reg.otgmode; + + if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG) { + *hnp_cap = true; + *srp_cap = true; + } else if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG || + otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE || + otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST) { + *hnp_cap = false; + *srp_cap = true; + } else { + *hnp_cap = false; + *srp_cap = false; + } +} + static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw) { return hw->ghwcfg3_reg.dfifodepth; diff --git a/components/esp_hal_usb/esp32s3/include/hal/usb_dwc_ll.h b/components/esp_hal_usb/esp32s3/include/hal/usb_dwc_ll.h index 93ea797ec2..fee252cab8 100644 --- a/components/esp_hal_usb/esp32s3/include/hal/usb_dwc_ll.h +++ b/components/esp_hal_usb/esp32s3/include/hal/usb_dwc_ll.h @@ -107,6 +107,17 @@ extern "C" { #define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1) #define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0) +/* + * OTG mode configuration values for the GHWCFG2 register + */ +#define USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG 0 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG 1 +#define USB_DWC_LL_GHWCFG_OTG_MODE_OTG 2 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE 3 +#define USB_DWC_LL_GHWCFG_OTG_MODE_DEVICE 4 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST 5 +#define USB_DWC_LL_GHWCFG_OTG_MODE_HOST 6 + /* * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode. * Each QTD describes one transfer. Scatter gather mode will automatically split @@ -202,14 +213,14 @@ static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw) hw->gusbcfg_reg.forcehstmode = 1; } -static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw) +static inline void usb_dwc_ll_gusbcfg_set_hnp_cap(usb_dwc_dev_t *hw, bool hnp_cap) { - hw->gusbcfg_reg.hnpcap = 0; + hw->gusbcfg_reg.hnpcap = hnp_cap; } -static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw) +static inline void usb_dwc_ll_gusbcfg_set_srp_cap(usb_dwc_dev_t *hw, bool srp_cap) { - hw->gusbcfg_reg.srpcap = 0; + hw->gusbcfg_reg.srpcap = srp_cap; } static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal) @@ -346,6 +357,24 @@ static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw) // --------------------------- GHWCFGx Register -------------------------------- +static inline void usb_dwc_ll_ghwcfg_get_hnp_srp_cap(usb_dwc_dev_t *hw, bool *hnp_cap, bool *srp_cap) +{ + const uint32_t otg_mode = hw->ghwcfg2_reg.otgmode; + + if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG) { + *hnp_cap = true; + *srp_cap = true; + } else if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG || + otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE || + otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST) { + *hnp_cap = false; + *srp_cap = true; + } else { + *hnp_cap = false; + *srp_cap = false; + } +} + static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw) { return hw->ghwcfg3_reg.dfifodepth; diff --git a/components/esp_hal_usb/esp32s31/include/hal/usb_dwc_ll.h b/components/esp_hal_usb/esp32s31/include/hal/usb_dwc_ll.h index 96be68454e..ad043ebb3a 100644 --- a/components/esp_hal_usb/esp32s31/include/hal/usb_dwc_ll.h +++ b/components/esp_hal_usb/esp32s31/include/hal/usb_dwc_ll.h @@ -107,6 +107,17 @@ extern "C" { #define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1) #define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0) +/* + * OTG mode configuration values for the GHWCFG2 register + */ +#define USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG 0 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG 1 +#define USB_DWC_LL_GHWCFG_OTG_MODE_OTG 2 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE 3 +#define USB_DWC_LL_GHWCFG_OTG_MODE_DEVICE 4 +#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST 5 +#define USB_DWC_LL_GHWCFG_OTG_MODE_HOST 6 + /* * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode. * Each QTD describes one transfer. Scatter gather mode will automatically split @@ -202,19 +213,14 @@ static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw) hw->gusbcfg_reg.forcehstmode = 1; } -static inline void usb_dwc_ll_gusbcfg_en_hnp_cap(usb_dwc_dev_t *hw) +static inline void usb_dwc_ll_gusbcfg_set_hnp_cap(usb_dwc_dev_t *hw, bool hnp_cap) { - hw->gusbcfg_reg.hnpcap = 1; + hw->gusbcfg_reg.hnpcap = hnp_cap; } -static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw) +static inline void usb_dwc_ll_gusbcfg_set_srp_cap(usb_dwc_dev_t *hw, bool srp_cap) { - hw->gusbcfg_reg.hnpcap = 0; -} - -static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw) -{ - hw->gusbcfg_reg.srpcap = 0; + hw->gusbcfg_reg.srpcap = srp_cap; } static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal) @@ -360,6 +366,24 @@ static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw) // --------------------------- GHWCFGx Register -------------------------------- +static inline void usb_dwc_ll_ghwcfg_get_hnp_srp_cap(usb_dwc_dev_t *hw, bool *hnp_cap, bool *srp_cap) +{ + const uint32_t otg_mode = hw->ghwcfg2_reg.otgmode; + + if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG) { + *hnp_cap = true; + *srp_cap = true; + } else if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG || + otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE || + otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST) { + *hnp_cap = false; + *srp_cap = true; + } else { + *hnp_cap = false; + *srp_cap = false; + } +} + static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw) { return hw->ghwcfg3_reg.dfifodepth; diff --git a/components/esp_hal_usb/usb_dwc_hal.c b/components/esp_hal_usb/usb_dwc_hal.c index d6a5d6bedc..d90b8612f3 100644 --- a/components/esp_hal_usb/usb_dwc_hal.c +++ b/components/esp_hal_usb/usb_dwc_hal.c @@ -125,9 +125,15 @@ static void set_defaults(usb_dwc_hal_context_t *hal) usb_dwc_ll_set_stoppclk(hal->dev, false); #endif // SOC_IS(ESP32P4) || SOC_IS(ESP32S31) usb_dwc_ll_gahbcfg_set_hbstlen(hal->dev, hbstlen); //Set AHB burst mode + //GUSBCFG register - usb_dwc_ll_gusbcfg_dis_hnp_cap(hal->dev); //Disable HNP - usb_dwc_ll_gusbcfg_dis_srp_cap(hal->dev); //Disable SRP + bool hnp_cap, srp_cap; + usb_dwc_ll_ghwcfg_get_hnp_srp_cap(hal->dev, &hnp_cap, &srp_cap); + + // On targets where the USB controller is HNP capable, the data lines pull-downs are controlled by the USB controller. + // Enabling HNP capability will also enable the data line pull-downs in deep-sleep mode eliminating leakage current. + usb_dwc_ll_gusbcfg_set_hnp_cap(hal->dev, hnp_cap); + usb_dwc_ll_gusbcfg_set_srp_cap(hal->dev, false); //Disable SRP // If this USB-DWC supports HS PHY, use it if (hal->constant_config.hsphy_type != 0) {