From 444c14dca29123209a02aa58095d50f52ed85693 Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Mon, 16 Mar 2026 11:32:32 +0800 Subject: [PATCH] change(parlio_tx): use shift edge instead sample edge Made-with: Cursor --- .../include/driver/parlio_tx.h | 7 +++++-- components/esp_driver_parlio/src/parlio_tx.c | 6 +++--- .../parlio/main/test_parlio_bitscrambler.c | 2 +- .../test_apps/parlio/main/test_parlio_sleep.c | 2 +- .../test_apps/parlio/main/test_parlio_tx.c | 20 +++++++++---------- .../parlio/main/test_parlio_tx_cache_safe.c | 2 +- .../esp32c5/include/hal/parlio_ll.h | 13 ++++++------ .../esp32c6/include/hal/parlio_ll.h | 8 ++++---- .../esp32h2/include/hal/parlio_ll.h | 13 ++++++------ .../esp32h4/include/hal/parlio_ll.h | 8 ++++---- .../esp32p4/include/hal/parlio_ll.h | 13 ++++++------ .../esp_hal_parlio/include/hal/parlio_types.h | 12 +++++++++-- .../esp_lcd/parl/esp_lcd_panel_io_parl.c | 2 +- .../peripherals/parlio/parlio_tx.rst | 8 ++++---- .../peripherals/parlio/parlio_tx.rst | 8 ++++---- .../advanced_rgb_led_matrix_example_main.c | 2 +- .../main/rgb_led_matrix_example_main.c | 2 +- 17 files changed, 68 insertions(+), 60 deletions(-) diff --git a/components/esp_driver_parlio/include/driver/parlio_tx.h b/components/esp_driver_parlio/include/driver/parlio_tx.h index ee8fd5c91e..f329832155 100644 --- a/components/esp_driver_parlio/include/driver/parlio_tx.h +++ b/components/esp_driver_parlio/include/driver/parlio_tx.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -35,7 +35,10 @@ typedef struct { size_t trans_queue_depth; /*!< Depth of internal transaction queue */ size_t max_transfer_size; /*!< Maximum transfer size in one transaction, in bytes. This decides the number of DMA nodes will be used for each transaction */ size_t dma_burst_size; /*!< DMA burst size, in bytes */ - parlio_sample_edge_t sample_edge; /*!< Parallel IO sample edge */ + union { + parlio_sample_edge_t sample_edge __attribute__((deprecated("Please use `shift_edge` instead"))); /*!< Parallel IO sample edge */ + parlio_shift_edge_t shift_edge; /*!< Parallel IO Tx shift edge */ + }; parlio_bit_pack_order_t bit_pack_order; /*!< Set the order of packing the bits into bytes (only works when `data_width` < 8) */ struct { uint32_t clk_gate_en: 1; /*!< Enable TX clock gating, diff --git a/components/esp_driver_parlio/src/parlio_tx.c b/components/esp_driver_parlio/src/parlio_tx.c index a544c520c6..e94453ff65 100644 --- a/components/esp_driver_parlio/src/parlio_tx.c +++ b/components/esp_driver_parlio/src/parlio_tx.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -340,8 +340,8 @@ esp_err_t parlio_new_tx_unit(const parlio_tx_unit_config_t *config, parlio_tx_un if (data_width < 8) { parlio_ll_tx_set_bit_pack_order(hal->regs, config->bit_pack_order); } - // set sample clock edge - parlio_ll_tx_set_sample_clock_edge(hal->regs, config->sample_edge); + + parlio_ll_tx_set_shift_clock_edge(hal->regs, config->shift_edge); // clear any pending interrupt parlio_ll_clear_interrupt_status(hal->regs, PARLIO_LL_EVENT_TX_MASK); diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_bitscrambler.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_bitscrambler.c index da99d586e1..ada07e3ac9 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_bitscrambler.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_bitscrambler.c @@ -59,7 +59,7 @@ static void test_parlio_bitscrambler(void) .trans_queue_depth = 8, .max_transfer_size = 128, .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_NEG, }; parlio_rx_unit_handle_t rx_unit = NULL; diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_sleep.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_sleep.c index 0a852f4e5e..67058c58a8 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_sleep.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_sleep.c @@ -50,7 +50,7 @@ static void test_parlio_sleep_retention(bool allow_pd) .trans_queue_depth = 8, .max_transfer_size = 128, .bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB, - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_POS, .flags.allow_pd = allow_pd, }; TEST_ESP_OK(parlio_new_tx_unit(&tx_config, &tx_unit)); diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c index 3936818d11..f482cb19e5 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -97,7 +97,7 @@ TEST_CASE("parallel_tx_unit_trans_done_event", "[parlio_tx]") .trans_queue_depth = 8, .max_transfer_size = 128, .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_POS, }; TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); @@ -149,7 +149,7 @@ TEST_CASE("parallel_tx_unit_enable_disable", "[parlio_tx]") .trans_queue_depth = 4, .max_transfer_size = 256, .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_POS, }; TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); @@ -210,7 +210,7 @@ TEST_CASE("parallel_tx_unit_idle_value", "[parlio_tx]") .trans_queue_depth = 4, .max_transfer_size = 64, .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_POS, }; TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); @@ -262,7 +262,7 @@ TEST_CASE("parallel_tx_clock_gating", "[paralio_tx]") .trans_queue_depth = 4, .max_transfer_size = 64, .bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB, - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_POS, .flags.clk_gate_en = true, // enable clock gating, controlled by the level of TEST_DATA7_GPIO }; TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); @@ -325,7 +325,7 @@ TEST_CASE("parallel_tx_clock_gating_and_msb_coexist", "[paralio_tx]") .trans_queue_depth = 4, .max_transfer_size = 256, .bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB, - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_POS, .valid_start_delay = 5, .valid_stop_delay = 5, .flags.clk_gate_en = true, // enable clock gating, controlled by the CS signal @@ -390,7 +390,7 @@ TEST_CASE("parlio_tx_can_transmit_PSRAM_buffer", "[parlio_tx]") .trans_queue_depth = 4, .max_transfer_size = 65535, .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_POS, .flags.clk_gate_en = true, }; @@ -512,7 +512,7 @@ TEST_CASE("parallel tx unit use external non-free running clock", "[parlio_tx]") .trans_queue_depth = 8, .max_transfer_size = 256, .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_POS, }; uint8_t test_round = 50; @@ -571,7 +571,7 @@ TEST_CASE("parlio_tx_loop_transmission", "[parlio_tx]") .trans_queue_depth = 3, .max_transfer_size = 256, .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_POS, }; TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); @@ -670,7 +670,7 @@ TEST_CASE("parlio_tx can transmit buffer larger than max_size decided by datalen .trans_queue_depth = 1, .max_transfer_size = 100 * 1024, .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_POS, .flags.clk_gate_en = true, }; diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx_cache_safe.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx_cache_safe.c index 1255fd9c72..c50d790426 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx_cache_safe.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx_cache_safe.c @@ -39,7 +39,7 @@ static void test_parlio_tx_cache_safe(void) .trans_queue_depth = 4, .max_transfer_size = 65535, .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_POS, }; TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); diff --git a/components/esp_hal_parlio/esp32c5/include/hal/parlio_ll.h b/components/esp_hal_parlio/esp32c5/include/hal/parlio_ll.h index 7a48056285..67d15be085 100644 --- a/components/esp_hal_parlio/esp32c5/include/hal/parlio_ll.h +++ b/components/esp_hal_parlio/esp32c5/include/hal/parlio_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -562,16 +562,15 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta } /** - * @brief Set the sample clock edge + * @brief Set the shift clock edge * * @param dev Parallel IO register base address - * @param edge Sample clock edge + * @param edge Shift clock edge */ -static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) +static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge) { - bool invert = edge == PARLIO_SAMPLE_EDGE_NEG; - dev->tx_clk_cfg.tx_clk_i_inv = invert; - dev->tx_clk_cfg.tx_clk_o_inv = invert; + dev->tx_clk_cfg.tx_clk_i_inv = edge; + dev->tx_clk_cfg.tx_clk_o_inv = edge; } /** diff --git a/components/esp_hal_parlio/esp32c6/include/hal/parlio_ll.h b/components/esp_hal_parlio/esp32c6/include/hal/parlio_ll.h index 59b3b4fe95..3d80520b39 100644 --- a/components/esp_hal_parlio/esp32c6/include/hal/parlio_ll.h +++ b/components/esp_hal_parlio/esp32c6/include/hal/parlio_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -533,12 +533,12 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta } /** - * @brief Set the sample clock edge + * @brief Set the shift clock edge * * @param dev Parallel IO register base address - * @param edge Sample clock edge + * @param edge Shift clock edge */ -static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) +static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge) { dev->tx_cfg0.tx_smp_edge_sel = edge; } diff --git a/components/esp_hal_parlio/esp32h2/include/hal/parlio_ll.h b/components/esp_hal_parlio/esp32h2/include/hal/parlio_ll.h index b9dfbdb566..29f6efd1a1 100644 --- a/components/esp_hal_parlio/esp32h2/include/hal/parlio_ll.h +++ b/components/esp_hal_parlio/esp32h2/include/hal/parlio_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -569,16 +569,15 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta } /** - * @brief Set the sample clock edge + * @brief Set the shift clock edge * * @param dev Parallel IO register base address - * @param edge Sample clock edge + * @param edge Shift clock edge */ -static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) +static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge) { - bool invert = edge == PARLIO_SAMPLE_EDGE_NEG; - dev->tx_clk_cfg.tx_clk_i_inv = invert; - dev->tx_clk_cfg.tx_clk_o_inv = invert; + dev->tx_clk_cfg.tx_clk_i_inv = edge; + dev->tx_clk_cfg.tx_clk_o_inv = edge; } /** diff --git a/components/esp_hal_parlio/esp32h4/include/hal/parlio_ll.h b/components/esp_hal_parlio/esp32h4/include/hal/parlio_ll.h index d8d08a9a4b..e48340ad3c 100644 --- a/components/esp_hal_parlio/esp32h4/include/hal/parlio_ll.h +++ b/components/esp_hal_parlio/esp32h4/include/hal/parlio_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -561,12 +561,12 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta } /** - * @brief Set the sample clock edge + * @brief Set the shift clock edge * * @param dev Parallel IO register base address - * @param edge Sample clock edge + * @param edge Shift clock edge */ -static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) +static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge) { dev->tx_clk_cfg.tx_clk_i_inv = edge; dev->tx_clk_cfg.tx_clk_o_inv = edge; diff --git a/components/esp_hal_parlio/esp32p4/include/hal/parlio_ll.h b/components/esp_hal_parlio/esp32p4/include/hal/parlio_ll.h index 37183fe8d6..4017ea6623 100644 --- a/components/esp_hal_parlio/esp32p4/include/hal/parlio_ll.h +++ b/components/esp_hal_parlio/esp32p4/include/hal/parlio_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -623,16 +623,15 @@ static inline void parlio_ll_tx_start(parl_io_dev_t *dev, bool en) } /** - * @brief Set the sample clock edge + * @brief Set the shift clock edge * * @param dev Parallel IO register base address - * @param edge Sample clock edge + * @param edge Shift clock edge */ -static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) +static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge) { - bool invert = edge == PARLIO_SAMPLE_EDGE_NEG; - dev->tx_clk_cfg.tx_clk_i_inv = invert; - dev->tx_clk_cfg.tx_clk_o_inv = invert; + dev->tx_clk_cfg.tx_clk_i_inv = edge; + dev->tx_clk_cfg.tx_clk_o_inv = edge; } /** diff --git a/components/esp_hal_parlio/include/hal/parlio_types.h b/components/esp_hal_parlio/include/hal/parlio_types.h index baaeeb4d9d..478c31f4ad 100644 --- a/components/esp_hal_parlio/include/hal/parlio_types.h +++ b/components/esp_hal_parlio/include/hal/parlio_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,13 +16,21 @@ extern "C" { #endif /** - * @brief Parallel IO sample edge + * @brief Parallel IO Rx sample edge */ typedef enum { PARLIO_SAMPLE_EDGE_NEG, /*!< Sample data on falling edge of clock */ PARLIO_SAMPLE_EDGE_POS, /*!< Sample data on rising edge of clock */ } parlio_sample_edge_t; +/** + * @brief Parallel IO Tx shift edge + */ +typedef enum { + PARLIO_SHIFT_EDGE_POS, /*!< Shift data on rising edge of clock */ + PARLIO_SHIFT_EDGE_NEG, /*!< Shift data on falling edge of clock */ +} parlio_shift_edge_t; + /** * @brief Parallel IO bit packing order * diff --git a/components/esp_lcd/parl/esp_lcd_panel_io_parl.c b/components/esp_lcd/parl/esp_lcd_panel_io_parl.c index 9fb4e63842..243934ca67 100644 --- a/components/esp_lcd/parl/esp_lcd_panel_io_parl.c +++ b/components/esp_lcd/parl/esp_lcd_panel_io_parl.c @@ -115,7 +115,7 @@ esp_err_t esp_lcd_new_panel_io_parl(const esp_lcd_panel_io_parl_config_t *io_con .output_clk_freq_hz = io_config->pclk_hz, .trans_queue_depth = io_config->trans_queue_depth ? io_config->trans_queue_depth : 4, .max_transfer_size = io_config->max_transfer_bytes, - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_NEG, .bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB, .dma_burst_size = io_config->dma_burst_size, .flags.invert_valid_out = !io_config->flags.cs_active_high, diff --git a/docs/en/api-reference/peripherals/parlio/parlio_tx.rst b/docs/en/api-reference/peripherals/parlio/parlio_tx.rst index 8ab52acc92..c482d9d9e2 100644 --- a/docs/en/api-reference/peripherals/parlio/parlio_tx.rst +++ b/docs/en/api-reference/peripherals/parlio/parlio_tx.rst @@ -46,7 +46,7 @@ First, we need to create a TX unit instance. The following code shows how to cre .output_clk_freq_hz = 10 * 1000 * 1000, // Output clock frequency is 10 MHz .trans_queue_depth = 32, // Transaction queue depth is 32 .max_transfer_size = 256, // Maximum transfer size is 256 bytes - .sample_edge = PARLIO_SAMPLE_EDGE_NEG, // Sample data on the falling edge of the clock + .shift_edge = PARLIO_SHIFT_EDGE_NEG, // Shift data on the falling edge of the clock .flags = { .invert_valid_out = true, // The valid signal is high by default, inverted to simulate the chip select signal CS in QPI timing } @@ -74,7 +74,7 @@ The following are the configuration parameters of the :cpp:type:`parlio_tx_unit_ - :cpp:member:`parlio_tx_unit_config_t::trans_queue_depth` The depth of the internal transaction queue. The deeper the queue, the more transactions can be prepared in the pending queue. - :cpp:member:`parlio_tx_unit_config_t::max_transfer_size` The maximum transfer size per transaction (in bytes). - :cpp:member:`parlio_tx_unit_config_t::dma_burst_size` The DMA burst transfer size (in bytes), must be a power of 2. - - :cpp:member:`parlio_tx_unit_config_t::sample_edge` The data sampling edge of the TX unit. + - :cpp:member:`parlio_tx_unit_config_t::shift_edge` The data shift edge of the TX unit. - :cpp:member:`parlio_tx_unit_config_t::bit_pack_order` Sets the order of data bits within a byte (valid only when data width < 8). - :cpp:member:`parlio_tx_unit_config_t::flags` Usually used to fine-tune some behaviors of the driver, including the following options - :cpp:member:`parlio_tx_unit_config_t::flags::invert_valid_out` Determines whether to invert the valid signal before sending it to the GPIO pin. @@ -216,7 +216,7 @@ The TX unit can choose various clock sources, among which the external clock sou .output_clk_freq_hz = 5 * 1000 * 1000, // Output clock frequency is 5 MHz. Note that it cannot exceed the input clock frequency .trans_queue_depth = 32, .max_transfer_size = 256, - .sample_edge = PARLIO_SAMPLE_EDGE_NEG, // Sample data on the falling edge of the clock + .shift_edge = PARLIO_SHIFT_EDGE_NEG, // Shift data on the falling edge of the clock }; // Create TX unit instance ESP_ERROR_CHECK(parlio_new_tx_unit(&config, &tx_unit)); @@ -273,7 +273,7 @@ The waveform of the external clock input is shown below: .output_clk_freq_hz = 10 * 1000 * 1000, // Output clock frequency is 10 MHz .trans_queue_depth = 32, .max_transfer_size = 256, - .sample_edge = PARLIO_SAMPLE_EDGE_NEG, // Sample data on the falling edge of the clock + .shift_edge = PARLIO_SHIFT_EDGE_NEG, // Shift data on the falling edge of the clock .flags = { .invert_valid_out = true, // The valid signal is high by default, inverted to simulate the chip select signal CS in QPI timing } diff --git a/docs/zh_CN/api-reference/peripherals/parlio/parlio_tx.rst b/docs/zh_CN/api-reference/peripherals/parlio/parlio_tx.rst index 82e280e59e..e6d1529118 100644 --- a/docs/zh_CN/api-reference/peripherals/parlio/parlio_tx.rst +++ b/docs/zh_CN/api-reference/peripherals/parlio/parlio_tx.rst @@ -46,7 +46,7 @@ .output_clk_freq_hz = 10 * 1000 * 1000, // 输出时钟频率为 10 MHz .trans_queue_depth = 32, // 待处理事务队列深度为 32 .max_transfer_size = 256, // 一次传输的最大传输大小为 256 字节 - .sample_edge = PARLIO_SAMPLE_EDGE_NEG, // 在时钟下降沿采样数据 + .shift_edge = PARLIO_SHIFT_EDGE_NEG, // 在时钟下降沿移位数据 .flags = { .invert_valid_out = true, // 有效信号默认高电平有效，通过反转，我们用来模拟 QPI 的时序中的片选信号 CS } @@ -74,7 +74,7 @@ - :cpp:member:`parlio_tx_unit_config_t::trans_queue_depth` 内部事务队列深度。队列越深，在待处理队列中可以准备的事务越多。 - :cpp:member:`parlio_tx_unit_config_t::max_transfer_size` 一次传输的最大传输大小（以字节为单位）。 - :cpp:member:`parlio_tx_unit_config_t::dma_burst_size` DMA 突发传输大小（以字节为单位），必须为 2 的幂次方。 - - :cpp:member:`parlio_tx_unit_config_t::sample_edge` TX 单元的数据采样边缘。 + - :cpp:member:`parlio_tx_unit_config_t::shift_edge` TX 单元的数据移位边缘。 - :cpp:member:`parlio_tx_unit_config_t::bit_pack_order` 设置字节内数据位出现的顺序（仅当数据宽度 < 8 时有效）。 - :cpp:member:`parlio_tx_unit_config_t::flags` 通常用来微调驱动的一些行为，包括以下选项 - :cpp:member:`parlio_tx_unit_config_t::flags::invert_valid_out` 决定是否在将 TX 单元有效信号发送到 GPIO 管脚前反转信号。 @@ -216,7 +216,7 @@ TX 单元可以选择各种不同的时钟源，其中外部时钟源较为特 .output_clk_freq_hz = 5 * 1000 * 1000, // 输出时钟频率为 5 MHz。注意，不能超过输入时钟频率 .trans_queue_depth = 32, .max_transfer_size = 256, - .sample_edge = PARLIO_SAMPLE_EDGE_NEG, // 在时钟下降沿采样数据 + .shift_edge = PARLIO_SHIFT_EDGE_NEG, // 在时钟下降沿移位数据 }; // 创建 TX 单元实例 ESP_ERROR_CHECK(parlio_new_tx_unit(&config, &tx_unit)); @@ -273,7 +273,7 @@ TX 单元可以选择各种不同的时钟源，其中外部时钟源较为特 .output_clk_freq_hz = 10 * 1000 * 1000, // 输出时钟频率为 10 MHz .trans_queue_depth = 32, .max_transfer_size = 256, - .sample_edge = PARLIO_SAMPLE_EDGE_NEG, // 在时钟下降沿采样数据 + .shift_edge = PARLIO_SHIFT_EDGE_NEG, // 在时钟下降沿移位数据 .flags = { .invert_valid_out = true, // 有效信号默认高电平有效，通过反转，我们用来模拟 QPI 的时序中的片选信号 CS } diff --git a/examples/peripherals/parlio/parlio_tx/advanced_rgb_led_matrix/main/advanced_rgb_led_matrix_example_main.c b/examples/peripherals/parlio/parlio_tx/advanced_rgb_led_matrix/main/advanced_rgb_led_matrix_example_main.c index c4dca2bab5..40b1391585 100644 --- a/examples/peripherals/parlio/parlio_tx/advanced_rgb_led_matrix/main/advanced_rgb_led_matrix_example_main.c +++ b/examples/peripherals/parlio/parlio_tx/advanced_rgb_led_matrix/main/advanced_rgb_led_matrix_example_main.c @@ -160,7 +160,7 @@ void app_main(void) .output_clk_freq_hz = EXAMPLE_LED_MATRIX_PIXEL_CLOCK_HZ, .trans_queue_depth = 4, .max_transfer_size = (EXAMPLE_LED_MATRIX_H_RES + EXAMPLE_GAP_CYCLE_PER_LINE) * EXAMPLE_LED_MATRIX_V_RES / 2 * sizeof(uint16_t), // full frame as the maximum transfer size - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_NEG, }; parlio_transmit_config_t transmit_config = { .idle_value = 0x00, // the idle value will take no effect since we are using the loop mode diff --git a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/rgb_led_matrix_example_main.c b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/rgb_led_matrix_example_main.c index f10309d0cd..756f1f9229 100644 --- a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/rgb_led_matrix_example_main.c +++ b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/rgb_led_matrix_example_main.c @@ -138,7 +138,7 @@ void app_main(void) .output_clk_freq_hz = EXAMPLE_LED_MATRIX_PIXEL_CLOCK_HZ, .trans_queue_depth = 32, .max_transfer_size = EXAMPLE_LED_MATRIX_H_RES * sizeof(uint8_t) * 2, // 2 lines as the maximum transfer size - .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .shift_edge = PARLIO_SHIFT_EDGE_NEG, }; ESP_ERROR_CHECK(parlio_new_tx_unit(&config, &tx_unit)); ESP_ERROR_CHECK(parlio_tx_unit_enable(tx_unit));