From 5698be672be02d01029458ff16e4a1284cb3f51d Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Mon, 12 Jan 2026 17:22:04 +0800 Subject: [PATCH] feat(mspi): support 120MHz flash and psram for esp32c61 --- .../src/bootloader_flash_config_esp32c61.c | 8 ++- .../port/esp32c5/mspi_timing_tuning_configs.h | 12 +---- .../esp32c61/mspi_timing_tuning_configs.h | 54 ++++++++++++------- .../test_apps/.build-test-rules.yml | 1 + .../test_apps/mspi/pytest_flash_psram.py | 36 +++++++++++-- ...ng_log_safe => sdkconfig.ci.120sdr_120sdr} | 6 +-- ...fig.ci.esp32s3_f4r4_timing_tuning_log_safe | 15 ------ components/esp_psram/esp32c61/Kconfig.spiram | 3 ++ .../psram/sdkconfig.ci.esp32c5_advanced | 5 +- .../psram/sdkconfig.ci.esp32c61_advanced | 5 +- components/esp_system/port/cpu_start.c | 2 - components/hal/esp32c5/include/hal/mspi_ll.h | 3 -- components/hal/esp32c61/include/hal/mspi_ll.h | 14 ++++- .../soc/esp32/include/soc/Kconfig.soc_caps.in | 16 ------ components/soc/esp32/include/soc/soc_caps.h | 6 --- .../esp32c2/include/soc/Kconfig.soc_caps.in | 16 ------ components/soc/esp32c2/include/soc/soc_caps.h | 5 -- .../esp32c3/include/soc/Kconfig.soc_caps.in | 16 ------ components/soc/esp32c3/include/soc/soc_caps.h | 5 -- .../esp32c5/include/soc/Kconfig.soc_caps.in | 20 ++----- components/soc/esp32c5/include/soc/soc_caps.h | 6 +-- .../esp32c6/include/soc/Kconfig.soc_caps.in | 12 ----- components/soc/esp32c6/include/soc/soc_caps.h | 4 -- .../esp32c61/include/soc/Kconfig.soc_caps.in | 16 ++---- .../soc/esp32c61/include/soc/soc_caps.h | 5 +- .../esp32h2/include/soc/Kconfig.soc_caps.in | 12 ----- components/soc/esp32h2/include/soc/soc_caps.h | 4 -- .../esp32p4/include/soc/Kconfig.soc_caps.in | 14 +---- components/soc/esp32p4/include/soc/soc_caps.h | 5 +- .../esp32s2/include/soc/Kconfig.soc_caps.in | 16 ------ components/soc/esp32s2/include/soc/soc_caps.h | 4 -- .../esp32s3/include/soc/Kconfig.soc_caps.in | 20 ++----- components/soc/esp32s3/include/soc/soc_caps.h | 7 +-- components/spi_flash/Kconfig | 3 +- .../spi_flash/esp32c61/Kconfig.flash_freq | 2 + .../spi_flash/spi_flash_override_driver.rst | 12 ++--- .../spi_flash/spi_flash_override_driver.rst | 12 ++--- 37 files changed, 133 insertions(+), 269 deletions(-) rename components/esp_hw_support/test_apps/mspi/{sdkconfig.ci.esp32p4_timing_tuning_log_safe => sdkconfig.ci.120sdr_120sdr} (56%) delete mode 100644 components/esp_hw_support/test_apps/mspi/sdkconfig.ci.esp32s3_f4r4_timing_tuning_log_safe diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c index 496a0c779a..ca8999a1ec 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -230,6 +230,12 @@ esp_err_t bootloader_init_spi_flash(void) { bootloader_init_mspi_clock(); bootloader_init_flash_configure(); + +#if CONFIG_BOOTLOADER_FLASH_DC_AWARE + // Reset flash, clear volatile bits DC[0:1]. Make it work under default mode to boot. + bootloader_spi_flash_reset(); +#endif + bootloader_spi_flash_resume(); if ((void*)bootloader_flash_unlock != (void*)bootloader_flash_unlock_default) { ESP_EARLY_LOGD(TAG, "Using overridden bootloader_flash_unlock"); diff --git a/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h b/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h index c213631d96..6918b85997 100644 --- a/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h +++ b/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -121,11 +121,6 @@ ESP_STATIC_ASSERT(MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_FLASH_MO #define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 12 #define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 4 -//FLASH: core clock 240M, module clock 80M, STR mode -#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_80M_STR_MODE {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}} -#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_80M_STR_MODE 14 -#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_80M_STR_MODE 4 - //FLASH: core clock 80M, module clock 80M, STR mode #define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}} #define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE 14 @@ -136,11 +131,6 @@ ESP_STATIC_ASSERT(MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_FLASH_MO #define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 12 #define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 4 -//PSRAM: core clock 240M, module clock 80M, STR mode -#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_80M_STR_MODE {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}} -#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_80M_STR_MODE 14 -#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_80M_STR_MODE 4 - //PSRAM: core clock 80M, module clock 80M, STR mode #define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}} #define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE 14 diff --git a/components/esp_hw_support/mspi_timing_tuning/port/esp32c61/mspi_timing_tuning_configs.h b/components/esp_hw_support/mspi_timing_tuning/port/esp32c61/mspi_timing_tuning_configs.h index 42755b434f..94a2d0cc3f 100644 --- a/components/esp_hw_support/mspi_timing_tuning/port/esp32c61/mspi_timing_tuning_configs.h +++ b/components/esp_hw_support/mspi_timing_tuning/port/esp32c61/mspi_timing_tuning_configs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,6 +13,7 @@ #define MSPI_TIMING_CONFIG_NUM_MAX 32 //This should be larger than the max available timing config num #define MSPI_TIMING_TEST_DATA_LEN 128 #define MSPI_TIMING_PSRAM_TEST_DATA_ADDR 0x100000 +#define MSPI_TIMING_FLASH_TEST_DATA_ADDR ESP_BOOTLOADER_OFFSET //--------------------------------------FLASH Sampling Mode --------------------------------------// #define MSPI_TIMING_FLASH_STR_MODE 1 @@ -27,7 +28,7 @@ #define MSPI_TIMING_FLASH_MODULE_CLOCK 120 #endif //------------------------------------FLASH Needs Tuning or not-------------------------------------// -#define MSPI_TIMING_FLASH_NEEDS_TUNING 0 +#define MSPI_TIMING_FLASH_NEEDS_TUNING (MSPI_TIMING_FLASH_MODULE_CLOCK > 80) //--------------------------------------PSRAM Sampling Mode --------------------------------------// #define MSPI_TIMING_PSRAM_STR_MODE 1 @@ -37,6 +38,8 @@ #define MSPI_TIMING_PSRAM_MODULE_CLOCK 40 #elif CONFIG_SPIRAM_SPEED_80M #define MSPI_TIMING_PSRAM_MODULE_CLOCK 80 +#elif CONFIG_SPIRAM_SPEED_120M +#define MSPI_TIMING_PSRAM_MODULE_CLOCK 120 #endif #else //Disable PSRAM #define MSPI_TIMING_PSRAM_MODULE_CLOCK 10 //Define this to 10MHz @@ -46,17 +49,30 @@ #define MSPI_TIMING_PSRAM_NEEDS_TUNING (MSPI_TIMING_PSRAM_MODULE_CLOCK > 40) #endif -///////////////////////////////////// FLASH/PSRAM CORE CLOCK ///////////////////////////////////// -#if ((CONFIG_ESPTOOLPY_FLASHFREQ_80M && !CONFIG_SPIRAM) || (CONFIG_ESPTOOLPY_FLASHFREQ_80M && CONFIG_SPIRAM_SPEED_80M)) +///////////////////////////////////// FLASH CORE CLOCK ///////////////////////////////////// +//FLASH 80M +#if CONFIG_ESPTOOLPY_FLASHFREQ_80M #define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 80 -#define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 80 #define MSPI_TIMING_FLASH_CONSECUTIVE_LEN_MAX 6 -#else -#define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240 -#define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 240 +#endif + +//FLASH 120M +#if CONFIG_ESPTOOLPY_FLASHFREQ_120M +#define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 120 #define MSPI_TIMING_FLASH_CONSECUTIVE_LEN_MAX 4 #endif +///////////////////////////////////// PSRAM CORE CLOCK ///////////////////////////////////// +//PSRAM 80M +#if CONFIG_SPIRAM_SPEED_80M +#define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 80 +#endif + +//PSRAM 120M +#if CONFIG_SPIRAM_SPEED_120M +#define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 120 +#endif //PSRAM 120M DTR + //------------------------------------------Determine the Core Clock-----------------------------------------------// /** * @note @@ -98,22 +114,22 @@ ESP_STATIC_ASSERT(MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_FLASH_MO /** * Timing Tuning Parameters */ +//FLASH: core clock 120M, module clock 120M, STR mode +#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {2, 1, 3}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {2, 1, 4}} +#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 12 +#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 2 + //FLASH: core clock 80M, module clock 80M, STR mode -#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}} +#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 1}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}} #define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE 14 #define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE 4 -//PSRAM: core clock 240M, module clock 120M, STR mode -#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {2, 1, 3}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {2, 1, 4}} -#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 12 -#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 4 - -//PSRAM: core clock 240M, module clock 80M, STR mode -#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_80M_STR_MODE {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}} -#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_80M_STR_MODE 14 -#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_80M_STR_MODE 4 +//PSRAM: core clock 120M, module clock 120M, STR mode +#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {2, 1, 3}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {2, 1, 4}} +#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 12 +#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 4 //PSRAM: core clock 80M, module clock 80M, STR mode -#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}} +#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 1}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}} #define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE 14 #define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE 4 diff --git a/components/esp_hw_support/test_apps/.build-test-rules.yml b/components/esp_hw_support/test_apps/.build-test-rules.yml index 112e747363..384c11b35b 100644 --- a/components/esp_hw_support/test_apps/.build-test-rules.yml +++ b/components/esp_hw_support/test_apps/.build-test-rules.yml @@ -25,6 +25,7 @@ components/esp_hw_support/test_apps/host_test_linux: components/esp_hw_support/test_apps/mspi: disable: - if: IDF_TARGET not in ["esp32c5", "esp32c61", "esp32s3", "esp32p4"] + - if: CONFIG_NAME == "120sdr_120sdr" and IDF_TARGET in ["esp32s3", "esp32p4"] - if: IDF_TARGET == "esp32p4" temporary: true reason: p4 rev3 migration # TODO: IDF-14366 diff --git a/components/esp_hw_support/test_apps/mspi/pytest_flash_psram.py b/components/esp_hw_support/test_apps/mspi/pytest_flash_psram.py index 142c0e50e8..8c65988972 100644 --- a/components/esp_hw_support/test_apps/mspi/pytest_flash_psram.py +++ b/components/esp_hw_support/test_apps/mspi/pytest_flash_psram.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 import os import pathlib @@ -54,7 +54,6 @@ def test_flash4_psram4(dut: IdfDut) -> None: 'config', [ 'esp32p4_120sdr_200ddr', - 'esp32p4_timing_tuning_log_safe', ], indirect=True, ) @@ -64,6 +63,18 @@ def test_flash_psram_esp32p4(dut: IdfDut) -> None: @pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + '120sdr_120sdr', + ], + indirect=True, +) +@idf_parametrize('target', ['esp32c5', 'esp32c61'], indirect=['target']) +def test_flash_psram_120sdr_120sdr(dut: IdfDut) -> None: + dut.run_all_single_board_cases() + + @pytest.mark.parametrize( 'config', [ @@ -72,6 +83,25 @@ def test_flash_psram_esp32p4(dut: IdfDut) -> None: ], indirect=True, ) -@idf_parametrize('target', ['esp32c5', 'esp32c61'], indirect=['target']) +@idf_parametrize( + 'target,markers', + [ + # S3 has no flash support auto suspend, this test is not applicable + ( + 'esp32p4', + (pytest.mark.generic,), + ), + ( + 'esp32c5', + (pytest.mark.generic,), + ), + ( + 'esp32c61', + (pytest.mark.generic,), + ), + ], + indirect=['target'], +) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-15339') def test_flash_psram_generic(dut: IdfDut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_hw_support/test_apps/mspi/sdkconfig.ci.esp32p4_timing_tuning_log_safe b/components/esp_hw_support/test_apps/mspi/sdkconfig.ci.120sdr_120sdr similarity index 56% rename from components/esp_hw_support/test_apps/mspi/sdkconfig.ci.esp32p4_timing_tuning_log_safe rename to components/esp_hw_support/test_apps/mspi/sdkconfig.ci.120sdr_120sdr index b8e3d1c163..6c8f0dba43 100644 --- a/components/esp_hw_support/test_apps/mspi/sdkconfig.ci.esp32p4_timing_tuning_log_safe +++ b/components/esp_hw_support/test_apps/mspi/sdkconfig.ci.120sdr_120sdr @@ -1,10 +1,6 @@ -CONFIG_IDF_TARGET="esp32p4" - -CONFIG_IDF_EXPERIMENTAL_FEATURES=y CONFIG_SPIRAM=y -CONFIG_SPIRAM_SPEED_200M=y +CONFIG_SPIRAM_SPEED_120M=y CONFIG_ESPTOOLPY_FLASHFREQ_120M=y CONFIG_SPI_FLASH_HPM_ENA=y CONFIG_BOOTLOADER_FLASH_DC_AWARE=y CONFIG_SPI_FLASH_AUTO_SUSPEND=y -CONFIG_LOG_IN_IRAM=n diff --git a/components/esp_hw_support/test_apps/mspi/sdkconfig.ci.esp32s3_f4r4_timing_tuning_log_safe b/components/esp_hw_support/test_apps/mspi/sdkconfig.ci.esp32s3_f4r4_timing_tuning_log_safe deleted file mode 100644 index ba6a6506ae..0000000000 --- a/components/esp_hw_support/test_apps/mspi/sdkconfig.ci.esp32s3_f4r4_timing_tuning_log_safe +++ /dev/null @@ -1,15 +0,0 @@ -# Legacy, F4R4, Flash 120M SDR, PSRAM 120M SDR - -CONFIG_IDF_TARGET="esp32s3" - -CONFIG_PARTITION_TABLE_CUSTOM=y -CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" -CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" -CONFIG_SPI_FLASH_HPM_ENA=y -CONFIG_ESPTOOLPY_FLASHFREQ_120M=y -CONFIG_BOOTLOADER_FLASH_DC_AWARE=y -CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y -CONFIG_SPIRAM=y -CONFIG_SPIRAM_SPEED_120M=y -CONFIG_SPI_FLASH_AUTO_SUSPEND=y -CONFIG_LOG_IN_IRAM=n diff --git a/components/esp_psram/esp32c61/Kconfig.spiram b/components/esp_psram/esp32c61/Kconfig.spiram index a5e97acfc6..03c8dbfde1 100644 --- a/components/esp_psram/esp32c61/Kconfig.spiram +++ b/components/esp_psram/esp32c61/Kconfig.spiram @@ -23,6 +23,8 @@ menu "SPI RAM config" help Select the speed for the SPI RAM chip. + config SPIRAM_SPEED_120M + bool "120MHz clock speed" config SPIRAM_SPEED_80M bool "80MHz clock speed" config SPIRAM_SPEED_40M @@ -31,6 +33,7 @@ menu "SPI RAM config" config SPIRAM_SPEED int + default 120 if SPIRAM_SPEED_120M default 80 if SPIRAM_SPEED_80M default 40 if SPIRAM_SPEED_40M diff --git a/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32c5_advanced b/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32c5_advanced index cab65486e0..c679eec187 100644 --- a/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32c5_advanced +++ b/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32c5_advanced @@ -4,8 +4,11 @@ CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y +# Flash frequency has to be 120M if SPIRAM speed is set to 120MHz +CONFIG_ESPTOOLPY_FLASHFREQ_120M=y + CONFIG_SPIRAM=y -CONFIG_SPIRAM_SPEED_80M=y +CONFIG_SPIRAM_SPEED_120M=y CONFIG_SPIRAM_XIP_FROM_PSRAM=y CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY=y diff --git a/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32c61_advanced b/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32c61_advanced index aa1bcea9c7..7d386150c1 100644 --- a/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32c61_advanced +++ b/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32c61_advanced @@ -4,8 +4,11 @@ CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y +# Flash frequency has to be 120M if SPIRAM speed is set to 120MHz +CONFIG_ESPTOOLPY_FLASHFREQ_120M=y + CONFIG_SPIRAM=y -CONFIG_SPIRAM_SPEED_80M=y +CONFIG_SPIRAM_SPEED_120M=y CONFIG_SPIRAM_XIP_FROM_PSRAM=y CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY=y diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 63f0c8659e..3655a3aa44 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -577,11 +577,9 @@ static NOINLINE_ATTR IRAM_ATTR void flash_init_state(void) * In this stage, we re-configure the Flash (and MSPI) to required configuration */ spi_flash_init_chip_state(); -#if SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED // This function needs to be called when PLL is enabled. Needs to be called after spi_flash_init_chip_state in case // some state of flash is modified. mspi_timing_flash_tuning(); -#endif } MSPI_INIT_ATTR void mspi_init(void) diff --git a/components/hal/esp32c5/include/hal/mspi_ll.h b/components/hal/esp32c5/include/hal/mspi_ll.h index 8bfa16f90f..fad19a7f5c 100644 --- a/components/hal/esp32c5/include/hal/mspi_ll.h +++ b/components/hal/esp32c5/include/hal/mspi_ll.h @@ -58,9 +58,6 @@ static inline __attribute__((always_inline)) void mspi_timing_ll_set_core_clock( case 120: divider = 4; break; - case 240: - divider = 2; - break; default: HAL_ASSERT(false); } diff --git a/components/hal/esp32c61/include/hal/mspi_ll.h b/components/hal/esp32c61/include/hal/mspi_ll.h index 0e048874d4..ec615ceaba 100644 --- a/components/hal/esp32c61/include/hal/mspi_ll.h +++ b/components/hal/esp32c61/include/hal/mspi_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -227,6 +227,18 @@ static inline void mspi_timing_ll_set_flash_extra_dummy(uint8_t mspi_id, uint8_t REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE); } +/** + * Set MSPI Flash user dummy + * + * @param mspi_id SPI0 / SPI1 + * @param user_dummy user dummy + */ +__attribute__((always_inline)) +static inline void mspi_timing_ll_set_flash_user_dummy(uint8_t mspi_id, uint8_t user_dummy) +{ + REG_SET_FIELD(SPI_MEM_USER1_REG(mspi_id), SPI_MEM_USR_DUMMY_CYCLELEN, user_dummy); +} + /** * Get MSPI flash dummy info * diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index 90f2450813..cbc5d52fb3 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -675,22 +675,6 @@ config SOC_SPI_MAX_PRE_DIVIDER int default 8192 -config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED - bool - default y - config SOC_TIMER_GROUPS int default 2 diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 58165267c7..039303747f 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -314,12 +314,6 @@ #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 #define SOC_SPI_MAX_PRE_DIVIDER 8192 -// Although ESP32 doesn't has memspi, but keep consistent with following chips.(This means SPI0/1) -#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 - // Peripheral supports DIO, DOUT, QIO, or QOUT #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host) ({(void)spi_host; 1;}) diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index b60e7537b4..3c14de47fb 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -559,22 +559,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y -config SOC_MEMSPI_SRC_FREQ_60M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_30M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_15M_SUPPORTED - bool - default y - config SOC_SYSTIMER_COUNTER_NUM int default 2 diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index 6026615496..81bc6fae65 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -255,11 +255,6 @@ #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1) -#define SOC_MEMSPI_SRC_FREQ_60M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_30M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_15M_SUPPORTED 1 - /*-------------------------- SYSTIMER CAPS ----------------------------------*/ #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units #define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index 6da46191c8..4892954671 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -819,22 +819,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y -config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED - bool - default y - config SOC_SYSTIMER_COUNTER_NUM int default 2 diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index cbb2f02d79..aef54ff245 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -350,11 +350,6 @@ #define SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1) -#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 - /*-------------------------- SYSTIMER CAPS ----------------------------------*/ #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units #define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index d88b95fdaa..1f98c027ff 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1263,26 +1263,14 @@ config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED bool default y +config SOC_SPI_MEM_FLASH_SUPPORT_HPM + bool + default y + config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY bool default y -config SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED - bool - default y - config SOC_SYSTIMER_COUNTER_NUM int default 2 diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 7e2568f85b..afee80f650 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -485,13 +485,9 @@ #define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1) #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) #define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1) +#define SOC_SPI_MEM_FLASH_SUPPORT_HPM (1) /*!< Support High Performance Mode */ #define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1) -#define SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 - /*-------------------------- SYSTIMER CAPS ----------------------------------*/ // TODO: [ESP32C5] IDF-8707 #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 826853ed80..0134da89cb 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -1107,18 +1107,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y -config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED - bool - default y - config SOC_SYSTIMER_COUNTER_NUM int default 2 diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 9a67eb9c8c..1f6b558c5a 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -433,10 +433,6 @@ #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1) -#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 - /*-------------------------- SYSTIMER CAPS ----------------------------------*/ #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units #define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 0e52d80037..d74e57b7c2 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -867,22 +867,14 @@ config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED bool default y +config SOC_SPI_MEM_FLASH_SUPPORT_HPM + bool + default y + config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY bool default y -config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED - bool - default y - config SOC_SYSTIMER_COUNTER_NUM int default 2 diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index a75d3b9c89..4a3790ccb2 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -350,12 +350,9 @@ #define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1) #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) #define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1) +#define SOC_SPI_MEM_FLASH_SUPPORT_HPM (1) /*!< Support High Performance Mode */ #define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1) -#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 - /*-------------------------- SYSTIMER CAPS ----------------------------------*/ #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units #define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 8708fc6268..159e408b27 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -1119,18 +1119,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y -config SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED - bool - default y - config SOC_SYSTIMER_COUNTER_NUM int default 2 diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 5bb56cdb64..334a354377 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -450,10 +450,6 @@ #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1) -#define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED 1 - /*-------------------------- SYSTIMER CAPS ----------------------------------*/ #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units #define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 03f4ea92e4..221d19dfc6 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -1699,19 +1699,7 @@ config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT bool default y -config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED +config SOC_SPI_MEM_FLASH_SUPPORT_HPM bool default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 24316d58ed..ac51750c00 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -622,10 +622,7 @@ #define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT (1) -#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED 1 +#define SOC_SPI_MEM_FLASH_SUPPORT_HPM (1) /*!< Support High Performance Mode */ #define SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT 1 diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index 1b1f95688a..cddc3dfc13 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -759,22 +759,6 @@ config SOC_MEMSPI_IS_INDEPENDENT bool default y -config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED - bool - default y - config SOC_SYSTIMER_COUNTER_NUM int default 1 diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index 33d3e2a48c..282f49bce6 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -324,10 +324,6 @@ #define SOC_SPI_SCT_CONF_BITLEN_MAX 0x7FFFFD //23 bit wide reg #define SOC_MEMSPI_IS_INDEPENDENT 1 -#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 /*-------------------------- SYSTIMER CAPS ----------------------------------*/ #define SOC_SYSTIMER_COUNTER_NUM (1U) // Number of counter units diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index 8d0760237b..5fba20ba13 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -943,22 +943,6 @@ config SOC_SPI_SCT_CONF_BITLEN_MAX hex default 0x3FFFA -config SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED - bool - default y - config SOC_SPIRAM_SUPPORTED bool default y @@ -1447,6 +1431,10 @@ config SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP bool default y +config SOC_SPI_MEM_FLASH_SUPPORT_HPM + bool + default y + config SOC_COEX_HW_PTI bool default y diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index ce83cd680b..e5ce39f10a 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -369,11 +369,6 @@ #define SOC_SPI_SCT_BUFFER_NUM_MAX (1 + SOC_SPI_SCT_REG_NUM) //1-word-bitmap + 14-word-regs #define SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA //18 bits wide reg -#define SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 - /*-------------------------- SPIRAM CAPS ----------------------------------------*/ #define SOC_SPIRAM_SUPPORTED 1 #define SOC_SPIRAM_XIP_SUPPORTED 1 @@ -562,6 +557,8 @@ #define SOC_MEMSPI_CORE_CLK_SHARED_WITH_PSRAM (1) #define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1) +#define SOC_SPI_MEM_FLASH_SUPPORT_HPM (1) /*!< Support High Performance Mode */ + /*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ #define SOC_COEX_HW_PTI (1) diff --git a/components/spi_flash/Kconfig b/components/spi_flash/Kconfig index 9f61909ba1..c5d4df7fd6 100644 --- a/components/spi_flash/Kconfig +++ b/components/spi_flash/Kconfig @@ -35,8 +35,7 @@ menu "Main Flash configuration" choice SPI_FLASH_HPM prompt "High Performance Mode (READ DOCS FIRST, > 80MHz)" - # Currently, only esp32s3 allows high performance mode. - depends on (IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32P4 || IDF_TARGET_ESP32C5) && !ESPTOOLPY_OCT_FLASH + depends on SOC_SPI_MEM_FLASH_SUPPORT_HPM && !ESPTOOLPY_OCT_FLASH default SPI_FLASH_HPM_AUTO help Whether the High Performance Mode of Flash is enabled. As an optional feature, user needs to manually diff --git a/components/spi_flash/esp32c61/Kconfig.flash_freq b/components/spi_flash/esp32c61/Kconfig.flash_freq index 2eac2e2f95..ac9875af5a 100644 --- a/components/spi_flash/esp32c61/Kconfig.flash_freq +++ b/components/spi_flash/esp32c61/Kconfig.flash_freq @@ -1,6 +1,8 @@ choice ESPTOOLPY_FLASHFREQ prompt "Flash SPI speed" default ESPTOOLPY_FLASHFREQ_80M + config ESPTOOLPY_FLASHFREQ_120M + bool "120 MHz" config ESPTOOLPY_FLASHFREQ_80M bool "80 MHz" config ESPTOOLPY_FLASHFREQ_40M diff --git a/docs/en/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst b/docs/en/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst index cf8e2d6dfd..fdd4f68791 100644 --- a/docs/en/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst +++ b/docs/en/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst @@ -231,16 +231,14 @@ The flash driver in the application is used to read, write, erase, and save data - Step 7: Build your project, and you will see the new flash driver in use. -.. only:: SOC_MEMSPI_SRC_FREQ_120M +High Performance Flash Implementation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - High Performance Flash Implementation - ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The high performance mode operates at frequencies higher than 80 MHz. Please check the datasheet for your flash and to determine which approach can reach to frequencies higher than 80 MHz, as listed in *DC Characteristics* section. Some behavior is already defined in the `high performance file `_ . If your flash meets the specified behavior, extend the list as introduced in the ``bootloader_flash_unlock`` section. If your flash has different behavior, please add the new behavior and override the behavior table ``spi_flash_hpm_enable_list``. - The high performance mode operates at frequencies higher than 80 MHz. Please check the datasheet for your flash and to determine which approach can reach to frequencies higher than 80 MHz, as listed in *DC Characteristics* section. Some behavior is already defined in the `high performance file `_ . If your flash meets the specified behavior, extend the list as introduced in the ``bootloader_flash_unlock`` section. If your flash has different behavior, please add the new behavior and override the behavior table ``spi_flash_hpm_enable_list``. +.. important:: - .. important:: - - Flash with a frequency set above 80 MHz should be tested carefully due to its strict timing requirements. If you want to use the high performance mode feature for mass production, please contact `Espressif's business team `_. + Flash with a frequency set above 80 MHz should be tested carefully due to its strict timing requirements. If you want to use the high performance mode feature for mass production, please contact `Espressif's business team `_. Example ------- diff --git a/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst b/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst index 073d039746..52549d04be 100644 --- a/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst +++ b/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst @@ -231,16 +231,14 @@ - 步骤 7：构建项目，你将看到新的 flash 驱动程序。 -.. only:: SOC_MEMSPI_SRC_FREQ_120M +高性能 flash 实现 +~~~~~~~~~~~~~~~~~ - 高性能 flash 实现 - ~~~~~~~~~~~~~~~~~ +高性能模式在高于 80 MHz 的频率下运行。请查阅 *直流电气特性* 章节，判断芯片是否支持在高于 80 MHz 的频率下工作。`高性能文件 `_ 中已经预定义了部分高性能模式下的行为，如果你的 flash 芯片符合指定行为，请按照 ``bootloader_flash_unlock`` 部分介绍的方法扩展列表。如果你的 flash 芯片有不同的行为，请添加新行为并覆盖 ``spi_flash_hpm_enable_list`` 行为表。 - 高性能模式在高于 80 MHz 的频率下运行。请查阅 *直流电气特性* 章节，判断芯片是否支持在高于 80 MHz 的频率下工作。`高性能文件 `_ 中已经预定义了部分高性能模式下的行为，如果你的 flash 芯片符合指定行为，请按照 ``bootloader_flash_unlock`` 部分介绍的方法扩展列表。如果你的 flash 芯片有不同的行为，请添加新行为并覆盖 ``spi_flash_hpm_enable_list`` 行为表。 +.. important:: - .. important:: - - 频率设置为 80 MHz 以上的 flash 芯片应进行仔细的测试，因为此时系统对于时序的要求非常严格。如果想在量产过程中使用高性能模式的功能，请联系 `乐鑫商务部 `_。 + 频率设置为 80 MHz 以上的 flash 芯片应进行仔细的测试，因为此时系统对于时序的要求非常严格。如果想在量产过程中使用高性能模式的功能，请联系 `乐鑫商务部 `_。 示例 ----