diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/README.md b/components/esp_driver_gpio/test_apps/gpio_extensions/README.md index b91fc54735..c5f27873ef 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/README.md +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | diff --git a/components/esp_hal_gpio/esp32s31/dedic_gpio_periph.c b/components/esp_hal_gpio/esp32s31/dedic_gpio_periph.c new file mode 100644 index 0000000000..aa8e596edc --- /dev/null +++ b/components/esp_hal_gpio/esp32s31/dedic_gpio_periph.c @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gpio_sig_map.h" +#include "hal/dedic_gpio_periph.h" + +const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { + .irq = -1, + .cores = { + [0] = { + .in_sig_per_channel = { + [0] = CORE_GPIO_IN_PAD_IN0_IDX, + [1] = CORE_GPIO_IN_PAD_IN1_IDX, + [2] = CORE_GPIO_IN_PAD_IN2_IDX, + [3] = CORE_GPIO_IN_PAD_IN3_IDX, + [4] = CORE_GPIO_IN_PAD_IN4_IDX, + [5] = CORE_GPIO_IN_PAD_IN5_IDX, + [6] = CORE_GPIO_IN_PAD_IN6_IDX, + [7] = CORE_GPIO_IN_PAD_IN7_IDX, + }, + .out_sig_per_channel = { + [0] = CORE_GPIO_OUT_PAD_OUT0_IDX, + [1] = CORE_GPIO_OUT_PAD_OUT1_IDX, + [2] = CORE_GPIO_OUT_PAD_OUT2_IDX, + [3] = CORE_GPIO_OUT_PAD_OUT3_IDX, + [4] = CORE_GPIO_OUT_PAD_OUT4_IDX, + [5] = CORE_GPIO_OUT_PAD_OUT5_IDX, + [6] = CORE_GPIO_OUT_PAD_OUT6_IDX, + [7] = CORE_GPIO_OUT_PAD_OUT7_IDX, + } + }, + [1] = { + .in_sig_per_channel = { + [0] = CORE_GPIO_IN_PAD_IN8_IDX, + [1] = CORE_GPIO_IN_PAD_IN9_IDX, + [2] = CORE_GPIO_IN_PAD_IN10_IDX, + [3] = CORE_GPIO_IN_PAD_IN11_IDX, + [4] = CORE_GPIO_IN_PAD_IN12_IDX, + [5] = CORE_GPIO_IN_PAD_IN13_IDX, + [6] = CORE_GPIO_IN_PAD_IN14_IDX, + [7] = CORE_GPIO_IN_PAD_IN15_IDX, + }, + .out_sig_per_channel = { + [0] = CORE_GPIO_OUT_PAD_OUT8_IDX, + [1] = CORE_GPIO_OUT_PAD_OUT9_IDX, + [2] = CORE_GPIO_OUT_PAD_OUT10_IDX, + [3] = CORE_GPIO_OUT_PAD_OUT11_IDX, + [4] = CORE_GPIO_OUT_PAD_OUT12_IDX, + [5] = CORE_GPIO_OUT_PAD_OUT13_IDX, + [6] = CORE_GPIO_OUT_PAD_OUT14_IDX, + [7] = CORE_GPIO_OUT_PAD_OUT15_IDX, + } + }, + }, +}; diff --git a/components/esp_hal_gpio/esp32s31/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32s31/include/hal/dedic_gpio_caps.h new file mode 100644 index 0000000000..f9ed4dc77f --- /dev/null +++ b/components/esp_hal_gpio/esp32s31/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32s31/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32s31/include/hal/dedic_gpio_cpu_ll.h new file mode 100644 index 0000000000..2b9858e4be --- /dev/null +++ b/components/esp_hal_gpio/esp32s31/include/hal/dedic_gpio_cpu_ll.h @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "riscv/csr.h" + +/*fast gpio*/ +#define CSR_GPIO_OEN_USER 0x803 +#define CSR_GPIO_IN_USER 0x804 +#define CSR_GPIO_OUT_USER 0x805 + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((always_inline)) +static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) +{ + // the OEN register is active low + RV_CLEAR_CSR(CSR_GPIO_OEN_USER, mask); +} + +__attribute__((always_inline)) +static inline void dedic_gpio_cpu_ll_write_all(uint32_t value) +{ + RV_WRITE_CSR(CSR_GPIO_OUT_USER, value); +} + +__attribute__((always_inline)) +static inline uint32_t dedic_gpio_cpu_ll_read_in(void) +{ + uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER); + return value; +} + +__attribute__((always_inline)) +static inline uint32_t dedic_gpio_cpu_ll_read_out(void) +{ + uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER); + return value; +} + +__attribute__((always_inline)) +static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) +{ + RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); + RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in index 099f8053e5..b51335f57a 100644 --- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in @@ -3,6 +3,10 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### +config SOC_DEDICATED_GPIO_SUPPORTED + bool + default y + config SOC_UART_SUPPORTED bool default y diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h index e91f0ac5d0..eabd9c2b76 100644 --- a/components/soc/esp32s31/include/soc/soc_caps.h +++ b/components/soc/esp32s31/include/soc/soc_caps.h @@ -25,7 +25,7 @@ /*-------------------------- COMMON CAPS ---------------------------------------*/ // #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32S31] IDF-14741 // #define SOC_ANA_CMPR_SUPPORTED 1 // TODO: [ESP32S31] IDF-14787 -// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32S31] IDF-14782 +#define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_UART_SUPPORTED 1 // TODO: [ESP32S31] IDF-14789 #define SOC_GDMA_SUPPORTED 1 // #define SOC_UHCI_SUPPORTED 1 // TODO: [ESP32S31] IDF-14791 diff --git a/examples/peripherals/dedicated_gpio/soft_i2c/README.md b/examples/peripherals/dedicated_gpio/soft_i2c/README.md index bffd05c23d..766a64d5b4 100644 --- a/examples/peripherals/dedicated_gpio/soft_i2c/README.md +++ b/examples/peripherals/dedicated_gpio/soft_i2c/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | # Example: Software I2C Master via Dedicated/Fast GPIOs diff --git a/examples/peripherals/dedicated_gpio/soft_spi/README.md b/examples/peripherals/dedicated_gpio/soft_spi/README.md index e0551c4c1b..5da7969e84 100644 --- a/examples/peripherals/dedicated_gpio/soft_spi/README.md +++ b/examples/peripherals/dedicated_gpio/soft_spi/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | --------- | # Example: SPI software emulation using dedicated/fast GPIOs diff --git a/examples/peripherals/dedicated_gpio/soft_uart/README.md b/examples/peripherals/dedicated_gpio/soft_uart/README.md index 27879b14dd..f276d0a755 100644 --- a/examples/peripherals/dedicated_gpio/soft_uart/README.md +++ b/examples/peripherals/dedicated_gpio/soft_uart/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | # Example: UART software emulation using dedicated/fast GPIOs