From 600bf5b6d7b730dc4d28225ac17c73107b4f3bd1 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 5 Feb 2026 21:07:45 +0800 Subject: [PATCH] refactor(esp_hal_regi2c): move regi2c implementation from esp_rom to esp_hal_regi2c --- .../main/ld/esp32c5/bootloader.ld.in | 1 + .../main/ld/esp32c6/bootloader.ld.in | 1 + .../main/ld/esp32c61/bootloader.ld.in | 1 + .../main/ld/esp32h2/bootloader.ld.in | 1 + .../main/ld/esp32h21/bootloader.ld.in | 1 + .../main/ld/esp32h4/bootloader.ld.in | 1 + .../main/ld/esp32p4/bootloader.ld.in | 1 + .../main/ld/esp32s2/bootloader.ld.in | 1 + .../main/ld/esp32s31/bootloader.ld.in | 1 + .../src/bootloader_random_esp32c2.c | 1 + .../src/bootloader_random_esp32c3.c | 1 + .../src/bootloader_random_esp32s2.c | 1 + .../src/bootloader_random_esp32s3.c | 1 + components/esp_hal_ana_conv/adc_hal.c | 2 +- components/esp_hal_ana_conv/adc_hal_common.c | 35 +- .../esp32c2/include/hal/adc_ll.h | 6 + .../include/hal/temperature_sensor_ll.h | 2 + .../esp32c3/include/hal/adc_ll.h | 6 + .../include/hal/temperature_sensor_ll.h | 2 + .../include/hal/temperature_sensor_ll.h | 2 + .../include/hal/temperature_sensor_ll.h | 2 + .../include/hal/temperature_sensor_ll.h | 2 + .../esp32h2/include/hal/adc_ll.h | 6 + .../include/hal/temperature_sensor_ll.h | 2 + .../include/hal/temperature_sensor_ll.h | 2 + .../esp32s2/include/hal/adc_ll.h | 6 + .../include/hal/temperature_sensor_ll.h | 2 + .../esp32s3/include/hal/adc_ll.h | 6 + .../include/hal/temperature_sensor_ll.h | 2 + .../esp_hal_ana_conv/include/hal/adc_hal.h | 2 +- .../include/hal/adc_hal_common.h | 21 +- .../include/hal/temperature_sensor_hal.h | 5 + .../esp_hal_ana_conv/temperature_sensor_hal.c | 17 +- components/esp_hal_clock/CMakeLists.txt | 3 + .../esp32c2/include/hal/clk_tree_ll.h | 29 ++ .../esp32c3/include/hal/clk_tree_ll.h | 10 + .../esp32c5/include/hal/clk_tree_ll.h | 29 ++ .../esp32c6/include/hal/clk_tree_ll.h | 29 ++ .../esp32c61/include/hal/clk_tree_ll.h | 29 ++ .../esp32h2/include/hal/clk_tree_ll.h | 29 ++ .../esp32h21/include/hal/clk_tree_ll.h | 31 +- .../esp32h4/include/hal/clk_tree_ll.h | 29 ++ .../esp32p4/include/hal/clk_tree_ll.h | 70 +++- .../esp32s3/include/hal/clk_tree_ll.h | 29 ++ .../esp32s31/include/hal/clk_tree_ll.h | 52 +++ components/esp_hal_regi2c/CMakeLists.txt | 29 ++ components/esp_hal_regi2c/README.md | 31 ++ .../esp32/include/hal/regi2c_ctrl_ll.h | 0 components/esp_hal_regi2c/esp32/rom.regi2c.ld | 9 + .../esp32c2}/include/hal/regi2c_ctrl_ll.h | 19 +- .../esp_hal_regi2c/esp32c2/rom.regi2c.ld | 9 + .../esp32c3}/include/hal/regi2c_ctrl_ll.h | 38 +-- .../esp_hal_regi2c/esp32c3/rom.regi2c.ld | 9 + .../esp32c5}/include/hal/regi2c_ctrl_ll.h | 33 +- .../esp32c5/regi2c_impl.c} | 37 +-- .../esp32c6/include/hal/regi2c_ctrl_ll.h | 31 +- .../esp32c6/regi2c_impl.c} | 37 +-- .../esp32c61}/include/hal/regi2c_ctrl_ll.h | 33 +- .../esp32c61/regi2c_impl.c} | 37 +-- .../esp32h2/include/hal/regi2c_ctrl_ll.h | 38 +-- .../esp32h2/regi2c_impl.c} | 37 +-- .../esp32h21/include/hal/regi2c_ctrl_ll.h | 31 +- .../esp32h21/regi2c_impl.c} | 103 +++--- .../esp32h4/include/hal/regi2c_ctrl_ll.h | 31 +- .../esp32h4/regi2c_impl.c} | 95 +++--- .../esp32p4/include/hal/regi2c_ctrl_ll.h | 59 +--- .../esp32p4/regi2c_impl.c} | 57 ++-- .../esp32s2/include/hal/regi2c_ctrl_ll.h | 7 - .../esp32s2/regi2c_impl.c} | 28 +- .../esp32s3/include/hal/regi2c_ctrl_ll.h | 38 +-- .../esp_hal_regi2c/esp32s3/rom.regi2c.ld | 9 + .../esp32s31/include/hal/regi2c_ctrl_ll.h | 55 +--- .../esp_hal_regi2c/esp32s31/regi2c_impl.c | 29 ++ .../esp_hal_regi2c/include/hal/regi2c_ctrl.h | 46 +++ .../esp_hal_regi2c/include/hal/regi2c_impl.h | 92 ++++++ components/esp_hal_regi2c/linker.lf | 5 + components/esp_hw_support/CMakeLists.txt | 16 +- .../include/esp_private/regi2c_ctrl.h | 52 +-- .../include/esp_private/sar_periph_ctrl.h | 13 + components/esp_hw_support/linker.lf | 11 +- .../lowpower/port/esp32c5/sleep_clock.c | 2 +- .../lowpower/port/esp32c5/sleep_modem_state.c | 2 +- .../lowpower/port/esp32c6/sleep_clock.c | 2 +- .../lowpower/port/esp32c6/sleep_modem_state.c | 2 +- .../lowpower/port/esp32c61/sleep_clock.c | 2 +- .../port/esp32c61/sleep_modem_state.c | 2 +- .../lowpower/port/esp32h2/sleep_clock.c | 2 +- .../lowpower/port/esp32h21/sleep_clock.c | 2 +- .../lowpower/port/esp32h4/sleep_clock.c | 2 +- .../port/esp32s3/mspi_timing_by_mspi_delay.c | 15 +- .../esp_hw_support/port/esp32c2/rtc_clk.c | 7 +- .../esp_hw_support/port/esp32c3/rtc_clk.c | 3 +- .../esp_hw_support/port/esp32c5/rtc_clk.c | 8 +- .../esp_hw_support/port/esp32c6/rtc_clk.c | 8 +- .../esp_hw_support/port/esp32c61/rtc_clk.c | 8 +- .../esp_hw_support/port/esp32h2/rtc_clk.c | 8 +- .../esp_hw_support/port/esp32h21/rtc_clk.c | 8 +- .../esp_hw_support/port/esp32h4/rtc_clk.c | 7 +- .../esp_hw_support/port/esp32p4/pmu_pvt.c | 1 + .../esp_hw_support/port/esp32p4/rtc_clk.c | 13 +- .../esp_hw_support/port/esp32s3/rtc_clk.c | 7 +- components/esp_hw_support/regi2c_ctrl.c | 91 +----- .../esp_hw_support/sar_periph_ctrl_common.c | 43 +++ components/esp_hw_support/sleep_modes.c | 18 +- components/esp_pm/linker.lf | 4 +- components/esp_rom/CMakeLists.txt | 10 - components/esp_rom/esp32/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32/esp_rom_caps.h | 1 + components/esp_rom/esp32/ld/esp32.rom.api.ld | 5 - components/esp_rom/esp32/ld/esp32.rom.ld | 4 - .../esp_rom/esp32c2/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32c2/esp_rom_caps.h | 1 + .../esp_rom/esp32c2/ld/esp32c2.rom.api.ld | 7 +- components/esp_rom/esp32c2/ld/esp32c2.rom.ld | 4 - .../esp_rom/esp32c3/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32c3/esp_rom_caps.h | 1 + .../esp_rom/esp32c3/ld/esp32c3.rom.api.ld | 5 - components/esp_rom/esp32c3/ld/esp32c3.rom.ld | 4 - .../esp_rom/esp32c5/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32c5/esp_rom_caps.h | 1 - .../esp_rom/esp32c6/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32c6/esp_rom_caps.h | 1 - .../esp_rom/esp32c61/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32c61/esp_rom_caps.h | 1 - .../esp_rom/esp32h2/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32h2/esp_rom_caps.h | 1 - .../esp_rom/esp32h21/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32h21/esp_rom_caps.h | 1 - .../esp_rom/esp32h4/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32h4/esp_rom_caps.h | 1 - .../esp_rom/esp32p4/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32p4/esp_rom_caps.h | 1 - .../esp_rom/esp32s2/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32s2/esp_rom_caps.h | 2 +- components/esp_rom/esp32s2/ld/esp32s2.rom.ld | 8 +- .../esp_rom/esp32s3/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32s3/esp_rom_caps.h | 1 + .../esp_rom/esp32s3/ld/esp32s3.rom.api.ld | 5 - components/esp_rom/esp32s3/ld/esp32s3.rom.ld | 4 - .../esp_rom/esp32s31/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32s31/esp_rom_caps.h | 1 - .../esp_rom/patches/esp_rom_regi2c_esp32s31.c | 29 -- components/hal/esp32/efuse_hal.c | 4 +- .../hal/platform_port/include/hal/config.h | 4 +- .../platform_port/include/hal/regi2c_ctrl.h | 35 -- .../soc/esp32/register/soc/sens_struct.h | 70 ++-- .../soc => include/modem}/i2c_ana_mst_reg.h | 2 +- .../soc/esp32c5/include/modem/reg_base.h | 1 + .../soc/esp32c5/register/soc/reg_base.h | 1 - .../soc => include/modem}/i2c_ana_mst_reg.h | 2 +- .../soc/esp32c6/include/modem/reg_base.h | 1 + .../soc/esp32c6/register/soc/reg_base.h | 2 - .../soc => include/modem}/i2c_ana_mst_reg.h | 2 +- .../soc/esp32c61/include/modem/reg_base.h | 1 + .../soc/esp32c61/register/soc/reg_base.h | 1 - .../soc => include/modem}/i2c_ana_mst_reg.h | 2 +- .../soc/esp32h2/include/modem/reg_base.h | 1 + .../soc/esp32h2/register/soc/reg_base.h | 2 - .../soc => include/modem}/i2c_ana_mst_reg.h | 2 +- .../soc/esp32h21/include/modem/reg_base.h | 1 + .../soc/esp32h21/register/soc/reg_base.h | 1 - .../include/{soc => modem}/i2c_ana_mst_reg.h | 2 +- .../soc/esp32h4/include/modem/reg_base.h | 1 + components/soc/esp32h4/include/soc/reg_base.h | 1 - .../soc/esp32p4/ld/esp32p4.peripherals.ld | 2 +- .../register/hw_ver1/soc/i2c_ana_mst_reg.h | 301 ------------------ .../register/hw_ver1/soc/lp_i2c_ana_mst_reg.h | 301 ++++++++++++++++++ ...a_mst_struct.h => lp_i2c_ana_mst_struct.h} | 68 ++-- .../esp32p4/register/hw_ver1/soc/reg_base.h | 2 +- .../register/hw_ver3/soc/i2c_ana_mst_reg.h | 301 ------------------ .../register/hw_ver3/soc/lp_i2c_ana_mst_reg.h | 301 ++++++++++++++++++ ...a_mst_struct.h => lp_i2c_ana_mst_struct.h} | 66 ++-- .../esp32p4/register/hw_ver3/soc/reg_base.h | 2 +- .../soc/esp32s2/register/soc/sens_struct.h | 88 ++--- .../soc/esp32s3/register/soc/sens_struct.h | 94 +++--- .../system/g1_components/CMakeLists.txt | 1 + 176 files changed, 1975 insertions(+), 1825 deletions(-) create mode 100644 components/esp_hal_regi2c/CMakeLists.txt create mode 100644 components/esp_hal_regi2c/README.md rename components/{hal => esp_hal_regi2c}/esp32/include/hal/regi2c_ctrl_ll.h (100%) create mode 100644 components/esp_hal_regi2c/esp32/rom.regi2c.ld rename components/{hal/esp32c3 => esp_hal_regi2c/esp32c2}/include/hal/regi2c_ctrl_ll.h (67%) create mode 100644 components/esp_hal_regi2c/esp32c2/rom.regi2c.ld rename components/{hal/esp32c2 => esp_hal_regi2c/esp32c3}/include/hal/regi2c_ctrl_ll.h (51%) create mode 100644 components/esp_hal_regi2c/esp32c3/rom.regi2c.ld rename components/{hal/esp32c61 => esp_hal_regi2c/esp32c5}/include/hal/regi2c_ctrl_ll.h (74%) rename components/{esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c => esp_hal_regi2c/esp32c5/regi2c_impl.c} (79%) rename components/{hal => esp_hal_regi2c}/esp32c6/include/hal/regi2c_ctrl_ll.h (74%) rename components/{esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c => esp_hal_regi2c/esp32c6/regi2c_impl.c} (79%) rename components/{hal/esp32c5 => esp_hal_regi2c/esp32c61}/include/hal/regi2c_ctrl_ll.h (74%) rename components/{esp_rom/patches/esp_rom_regi2c_esp32c61.c => esp_hal_regi2c/esp32c61/regi2c_impl.c} (79%) rename components/{hal => esp_hal_regi2c}/esp32h2/include/hal/regi2c_ctrl_ll.h (68%) rename components/{esp_rom/patches/esp_rom_regi2c_esp32h2.c => esp_hal_regi2c/esp32h2/regi2c_impl.c} (79%) rename components/{hal => esp_hal_regi2c}/esp32h21/include/hal/regi2c_ctrl_ll.h (71%) rename components/{esp_rom/patches/esp_rom_regi2c_esp32h21.c => esp_hal_regi2c/esp32h21/regi2c_impl.c} (50%) rename components/{hal => esp_hal_regi2c}/esp32h4/include/hal/regi2c_ctrl_ll.h (77%) rename components/{esp_rom/patches/esp_rom_regi2c_esp32h4.c => esp_hal_regi2c/esp32h4/regi2c_impl.c} (50%) rename components/{hal => esp_hal_regi2c}/esp32p4/include/hal/regi2c_ctrl_ll.h (57%) rename components/{esp_rom/patches/esp_rom_regi2c_esp32p4.c => esp_hal_regi2c/esp32p4/regi2c_impl.c} (69%) rename components/{hal => esp_hal_regi2c}/esp32s2/include/hal/regi2c_ctrl_ll.h (85%) rename components/{esp_rom/patches/esp_rom_regi2c_esp32s2.c => esp_hal_regi2c/esp32s2/regi2c_impl.c} (84%) rename components/{hal => esp_hal_regi2c}/esp32s3/include/hal/regi2c_ctrl_ll.h (50%) create mode 100644 components/esp_hal_regi2c/esp32s3/rom.regi2c.ld rename components/{hal => esp_hal_regi2c}/esp32s31/include/hal/regi2c_ctrl_ll.h (52%) create mode 100644 components/esp_hal_regi2c/esp32s31/regi2c_impl.c create mode 100644 components/esp_hal_regi2c/include/hal/regi2c_ctrl.h create mode 100644 components/esp_hal_regi2c/include/hal/regi2c_impl.h create mode 100644 components/esp_hal_regi2c/linker.lf create mode 100644 components/esp_hw_support/sar_periph_ctrl_common.c delete mode 100644 components/esp_rom/patches/esp_rom_regi2c_esp32s31.c delete mode 100644 components/hal/platform_port/include/hal/regi2c_ctrl.h rename components/soc/esp32c5/{register/soc => include/modem}/i2c_ana_mst_reg.h (99%) rename components/soc/esp32c6/{register/soc => include/modem}/i2c_ana_mst_reg.h (99%) rename components/soc/esp32c61/{register/soc => include/modem}/i2c_ana_mst_reg.h (99%) rename components/soc/esp32h2/{register/soc => include/modem}/i2c_ana_mst_reg.h (99%) rename components/soc/esp32h21/{register/soc => include/modem}/i2c_ana_mst_reg.h (99%) rename components/soc/esp32h4/include/{soc => modem}/i2c_ana_mst_reg.h (99%) delete mode 100644 components/soc/esp32p4/register/hw_ver1/soc/i2c_ana_mst_reg.h create mode 100644 components/soc/esp32p4/register/hw_ver1/soc/lp_i2c_ana_mst_reg.h rename components/soc/esp32p4/register/hw_ver1/soc/{i2c_ana_mst_struct.h => lp_i2c_ana_mst_struct.h} (79%) delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/i2c_ana_mst_reg.h create mode 100644 components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_ana_mst_reg.h rename components/soc/esp32p4/register/hw_ver3/soc/{i2c_ana_mst_struct.h => lp_i2c_ana_mst_struct.h} (79%) diff --git a/components/bootloader/subproject/main/ld/esp32c5/bootloader.ld.in b/components/bootloader/subproject/main/ld/esp32c5/bootloader.ld.in index 51f81f094a..a5c932295a 100644 --- a/components/bootloader/subproject/main/ld/esp32c5/bootloader.ld.in +++ b/components/bootloader/subproject/main/ld/esp32c5/bootloader.ld.in @@ -99,6 +99,7 @@ SECTIONS *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) + *libesp_hal_regi2c.a:regi2c_impl.*(.literal .text .literal.* .text.*) *libefuse.a:*.*(.literal .text .literal.* .text.*) *libriscv.a:rv_utils.*(.literal .text .literal.* .text.*) *(.fini.literal) diff --git a/components/bootloader/subproject/main/ld/esp32c6/bootloader.ld.in b/components/bootloader/subproject/main/ld/esp32c6/bootloader.ld.in index e0ffe6b210..a0a799bed3 100644 --- a/components/bootloader/subproject/main/ld/esp32c6/bootloader.ld.in +++ b/components/bootloader/subproject/main/ld/esp32c6/bootloader.ld.in @@ -95,6 +95,7 @@ SECTIONS *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) + *libesp_hal_regi2c.a:regi2c_impl.*(.literal .text .literal.* .text.*) *libefuse.a:*.*(.literal .text .literal.* .text.*) *libriscv.a:rv_utils.*(.literal .text .literal.* .text.*) *(.fini.literal) diff --git a/components/bootloader/subproject/main/ld/esp32c61/bootloader.ld.in b/components/bootloader/subproject/main/ld/esp32c61/bootloader.ld.in index 8daabd3d1b..3d0bcd91d8 100644 --- a/components/bootloader/subproject/main/ld/esp32c61/bootloader.ld.in +++ b/components/bootloader/subproject/main/ld/esp32c61/bootloader.ld.in @@ -94,6 +94,7 @@ SECTIONS *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) + *libesp_hal_regi2c.a:regi2c_impl.*(.literal .text .literal.* .text.*) *libefuse.a:*.*(.literal .text .literal.* .text.*) *libriscv.a:rv_utils.*(.literal .text .literal.* .text.*) *(.fini.literal) diff --git a/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld.in b/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld.in index 82d6ef3e8f..bd26b238f9 100644 --- a/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld.in +++ b/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld.in @@ -94,6 +94,7 @@ SECTIONS *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) + *libesp_hal_regi2c.a:regi2c_impl.*(.literal .text .literal.* .text.*) *libefuse.a:*.*(.literal .text .literal.* .text.*) *libriscv.a:rv_utils.*(.literal .text .literal.* .text.*) *(.fini.literal) diff --git a/components/bootloader/subproject/main/ld/esp32h21/bootloader.ld.in b/components/bootloader/subproject/main/ld/esp32h21/bootloader.ld.in index c8619fab6e..6f94636ed6 100644 --- a/components/bootloader/subproject/main/ld/esp32h21/bootloader.ld.in +++ b/components/bootloader/subproject/main/ld/esp32h21/bootloader.ld.in @@ -94,6 +94,7 @@ SECTIONS *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) + *libesp_hal_regi2c.a:regi2c_impl.*(.literal .text .literal.* .text.*) *libefuse.a:*.*(.literal .text .literal.* .text.*) *libriscv.a:rv_utils.*(.literal .text .literal.* .text.*) *(.fini.literal) diff --git a/components/bootloader/subproject/main/ld/esp32h4/bootloader.ld.in b/components/bootloader/subproject/main/ld/esp32h4/bootloader.ld.in index 3890ba2fdf..1f8441c6a5 100644 --- a/components/bootloader/subproject/main/ld/esp32h4/bootloader.ld.in +++ b/components/bootloader/subproject/main/ld/esp32h4/bootloader.ld.in @@ -94,6 +94,7 @@ SECTIONS *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) + *libesp_hal_regi2c.a:regi2c_impl.*(.literal .text .literal.* .text.*) *libefuse.a:*.*(.literal .text .literal.* .text.*) *libriscv.a:rv_utils.*(.literal .text .literal.* .text.*) *(.fini.literal) diff --git a/components/bootloader/subproject/main/ld/esp32p4/bootloader.ld.in b/components/bootloader/subproject/main/ld/esp32p4/bootloader.ld.in index 8bf17b9974..ce6ae14079 100644 --- a/components/bootloader/subproject/main/ld/esp32p4/bootloader.ld.in +++ b/components/bootloader/subproject/main/ld/esp32p4/bootloader.ld.in @@ -98,6 +98,7 @@ SECTIONS *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) + *libesp_hal_regi2c.a:regi2c_impl.*(.literal .text .literal.* .text.*) *libefuse.a:*.*(.literal .text .literal.* .text.*) *libriscv.a:rv_utils.*(.literal .text .literal.* .text.*) *(.fini.literal) diff --git a/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld.in b/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld.in index 7737c29a47..ee61741d6e 100644 --- a/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld.in +++ b/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld.in @@ -63,6 +63,7 @@ SECTIONS *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) + *libesp_hal_regi2c.a:regi2c_impl.*(.literal .text .literal.* .text.*) *libefuse.a:*.*(.literal .text .literal.* .text.*) *libesp_rom.a:esp_rom_regi2c.*(.literal .text .literal.* .text.*) *(.fini.literal) diff --git a/components/bootloader/subproject/main/ld/esp32s31/bootloader.ld.in b/components/bootloader/subproject/main/ld/esp32s31/bootloader.ld.in index c221ac304f..4abb21dce7 100644 --- a/components/bootloader/subproject/main/ld/esp32s31/bootloader.ld.in +++ b/components/bootloader/subproject/main/ld/esp32s31/bootloader.ld.in @@ -98,6 +98,7 @@ SECTIONS *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) + *libesp_hal_regi2c.a:regi2c_impl.*(.literal .text .literal.* .text.*) *libefuse.a:*.*(.literal .text .literal.* .text.*) *libriscv.a:rv_utils.*(.literal .text .literal.* .text.*) *(.fini.literal) diff --git a/components/bootloader_support/src/bootloader_random_esp32c2.c b/components/bootloader_support/src/bootloader_random_esp32c2.c index 0ad0c4bd33..dfa462be47 100644 --- a/components/bootloader_support/src/bootloader_random_esp32c2.c +++ b/components/bootloader_support/src/bootloader_random_esp32c2.c @@ -11,6 +11,7 @@ #include "soc/apb_saradc_reg.h" #include "soc/system_reg.h" #include "esp_private/regi2c_ctrl.h" +#include "esp_private/sar_periph_ctrl.h" #include "soc/regi2c_saradc.h" #include "hal/adc_ll.h" #include "hal/sar_ctrl_ll.h" diff --git a/components/bootloader_support/src/bootloader_random_esp32c3.c b/components/bootloader_support/src/bootloader_random_esp32c3.c index 2a70671e33..cf1b9aab28 100644 --- a/components/bootloader_support/src/bootloader_random_esp32c3.c +++ b/components/bootloader_support/src/bootloader_random_esp32c3.c @@ -7,6 +7,7 @@ #include "bootloader_random.h" #include "soc/rtc_cntl_reg.h" #include "esp_private/regi2c_ctrl.h" +#include "esp_private/sar_periph_ctrl.h" #include "hal/adc_ll.h" #include "hal/temperature_sensor_ll.h" #include "esp_private/sar_periph_ctrl.h" diff --git a/components/bootloader_support/src/bootloader_random_esp32s2.c b/components/bootloader_support/src/bootloader_random_esp32s2.c index b946897188..3bab07fc7a 100644 --- a/components/bootloader_support/src/bootloader_random_esp32s2.c +++ b/components/bootloader_support/src/bootloader_random_esp32s2.c @@ -12,6 +12,7 @@ #include "esp_log.h" #include "soc/apb_saradc_reg.h" #include "esp_private/regi2c_ctrl.h" +#include "esp_private/sar_periph_ctrl.h" #include "hal/adc_ll.h" #include "esp_rom_sys.h" diff --git a/components/bootloader_support/src/bootloader_random_esp32s3.c b/components/bootloader_support/src/bootloader_random_esp32s3.c index b948c4f3bc..deeb51985c 100644 --- a/components/bootloader_support/src/bootloader_random_esp32s3.c +++ b/components/bootloader_support/src/bootloader_random_esp32s3.c @@ -7,6 +7,7 @@ #include "bootloader_random.h" #include "soc/syscon_reg.h" #include "esp_private/regi2c_ctrl.h" +#include "esp_private/sar_periph_ctrl.h" #include "hal/adc_ll.h" #include "hal/adc_types.h" #include "hal/regi2c_ctrl_ll.h" diff --git a/components/esp_hal_ana_conv/adc_hal.c b/components/esp_hal_ana_conv/adc_hal.c index 717eceb088..6fcafc0627 100644 --- a/components/esp_hal_ana_conv/adc_hal.c +++ b/components/esp_hal_ana_conv/adc_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_hal_ana_conv/adc_hal_common.c b/components/esp_hal_ana_conv/adc_hal_common.c index 146f19e23c..1685cdf230 100644 --- a/components/esp_hal_ana_conv/adc_hal_common.c +++ b/components/esp_hal_ana_conv/adc_hal_common.c @@ -1,14 +1,14 @@ /* - * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include -#include "soc/soc_caps.h" #include "hal/adc_hal_common.h" -#include "hal/adc_ll.h" #include "hal/assert.h" +#include "hal/regi2c_ctrl.h" +#include "esp_attr.h" /*--------------------------------------------------------------- Controller Setting @@ -197,3 +197,32 @@ uint32_t adc_hal_self_calibration(adc_unit_t adc_n, adc_atten_t atten, bool inte } #endif //#if SOC_ADC_SELF_HW_CALI_SUPPORTED #endif //SOC_ADC_CALIBRATION_V1_SUPPORTED + +/*--------------------------------------------------------------- + I2C SAR ADC register backup/restore +---------------------------------------------------------------*/ +#if ADC_LL_ANA_CALI_REG_PD_WORKAROUND +static DRAM_ATTR uint8_t s_adc_i2c_reg_val[ADC_LL_ANA_CALI_REG_BYTE_NUM]; + +void IRAM_ATTR adc_hal_i2c_saradc_reg_backup(void) +{ + REGI2C_CLOCK_ENABLE(); + REGI2C_ENTER_CRITICAL(); + for (int i = 0; i < ADC_LL_ANA_CALI_REG_BYTE_NUM; i++) { + s_adc_i2c_reg_val[i] = regi2c_impl_read(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i); + } + REGI2C_EXIT_CRITICAL(); + REGI2C_CLOCK_DISABLE(); +} + +void IRAM_ATTR adc_hal_i2c_saradc_reg_restore(void) +{ + REGI2C_CLOCK_ENABLE(); + REGI2C_ENTER_CRITICAL(); + for (int i = 0; i < ADC_LL_ANA_CALI_REG_BYTE_NUM; i++) { + regi2c_impl_write(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i, s_adc_i2c_reg_val[i]); + } + REGI2C_EXIT_CRITICAL(); + REGI2C_CLOCK_DISABLE(); +} +#endif // ADC_LL_ANA_CALI_REG_PD_WORKAROUND diff --git a/components/esp_hal_ana_conv/esp32c2/include/hal/adc_ll.h b/components/esp_hal_ana_conv/esp32c2/include/hal/adc_ll.h index be90be3593..78255f9a0d 100644 --- a/components/esp_hal_ana_conv/esp32c2/include/hal/adc_ll.h +++ b/components/esp_hal_ana_conv/esp32c2/include/hal/adc_ll.h @@ -57,6 +57,12 @@ extern "C" { ---------------------------------------------------------------*/ #define ADC_LL_PWDET_CCT_DEFAULT (4) +/*--------------------------------------------------------------- + I2C SAR ADC REG PD workaround +---------------------------------------------------------------*/ +#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1 +#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8 + typedef enum { ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ ADC_LL_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ diff --git a/components/esp_hal_ana_conv/esp32c2/include/hal/temperature_sensor_ll.h b/components/esp_hal_ana_conv/esp32c2/include/hal/temperature_sensor_ll.h index 6e75c62456..e691583f32 100644 --- a/components/esp_hal_ana_conv/esp32c2/include/hal/temperature_sensor_ll.h +++ b/components/esp_hal_ana_conv/esp32c2/include/hal/temperature_sensor_ll.h @@ -104,6 +104,7 @@ static inline void temperature_sensor_ll_clk_sel(temperature_sensor_clk_src_t cl * * @param tsens_dac ``reg_val`` in table ``temperature_sensor_attributes`` */ +__attribute__((always_inline)) static inline void temperature_sensor_ll_set_range(uint32_t range) { REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, range); @@ -126,6 +127,7 @@ static inline uint32_t temperature_sensor_ll_get_raw_value(void) * * @return uint32_t offset value */ +__attribute__((always_inline)) static inline uint32_t temperature_sensor_ll_get_offset(void) { return REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC); diff --git a/components/esp_hal_ana_conv/esp32c3/include/hal/adc_ll.h b/components/esp_hal_ana_conv/esp32c3/include/hal/adc_ll.h index c3d11c1e73..00c2d89d66 100644 --- a/components/esp_hal_ana_conv/esp32c3/include/hal/adc_ll.h +++ b/components/esp_hal_ana_conv/esp32c3/include/hal/adc_ll.h @@ -76,6 +76,12 @@ extern "C" { ---------------------------------------------------------------*/ #define ADC_LL_PWDET_CCT_DEFAULT (4) +/*--------------------------------------------------------------- + I2C SAR ADC REG PD workaround +---------------------------------------------------------------*/ +#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1 +#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8 + typedef enum { ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ ADC_LL_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ diff --git a/components/esp_hal_ana_conv/esp32c3/include/hal/temperature_sensor_ll.h b/components/esp_hal_ana_conv/esp32c3/include/hal/temperature_sensor_ll.h index e498dded92..c773a26c4c 100644 --- a/components/esp_hal_ana_conv/esp32c3/include/hal/temperature_sensor_ll.h +++ b/components/esp_hal_ana_conv/esp32c3/include/hal/temperature_sensor_ll.h @@ -104,6 +104,7 @@ static inline void temperature_sensor_ll_clk_sel(temperature_sensor_clk_src_t cl * * @param tsens_dac ``reg_val`` in table ``temperature_sensor_attributes`` */ +__attribute__((always_inline)) static inline void temperature_sensor_ll_set_range(uint32_t range) { REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, range); @@ -126,6 +127,7 @@ static inline uint32_t temperature_sensor_ll_get_raw_value(void) * * @return uint32_t offset value */ +__attribute__((always_inline)) static inline uint32_t temperature_sensor_ll_get_offset(void) { return REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC); diff --git a/components/esp_hal_ana_conv/esp32c5/include/hal/temperature_sensor_ll.h b/components/esp_hal_ana_conv/esp32c5/include/hal/temperature_sensor_ll.h index 6e4945ddb9..b695801788 100644 --- a/components/esp_hal_ana_conv/esp32c5/include/hal/temperature_sensor_ll.h +++ b/components/esp_hal_ana_conv/esp32c5/include/hal/temperature_sensor_ll.h @@ -118,6 +118,7 @@ static inline void temperature_sensor_ll_clk_sel(temperature_sensor_clk_src_t cl * * @param tsens_dac ``reg_val`` in table ``temperature_sensor_attributes`` */ +__attribute__((always_inline)) static inline void temperature_sensor_ll_set_range(uint32_t range) { REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, range); @@ -141,6 +142,7 @@ static inline uint32_t temperature_sensor_ll_get_raw_value(void) * * @return uint32_t offset value */ +__attribute__((always_inline)) static inline uint32_t temperature_sensor_ll_get_offset(void) { return REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC); diff --git a/components/esp_hal_ana_conv/esp32c6/include/hal/temperature_sensor_ll.h b/components/esp_hal_ana_conv/esp32c6/include/hal/temperature_sensor_ll.h index a074ae08b1..87e75e5e28 100644 --- a/components/esp_hal_ana_conv/esp32c6/include/hal/temperature_sensor_ll.h +++ b/components/esp_hal_ana_conv/esp32c6/include/hal/temperature_sensor_ll.h @@ -118,6 +118,7 @@ static inline void temperature_sensor_ll_clk_sel(temperature_sensor_clk_src_t cl * * @param tsens_dac ``reg_val`` in table ``temperature_sensor_attributes`` */ +__attribute__((always_inline)) static inline void temperature_sensor_ll_set_range(uint32_t range) { REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, range); @@ -141,6 +142,7 @@ static inline uint32_t temperature_sensor_ll_get_raw_value(void) * * @return uint32_t offset value */ +__attribute__((always_inline)) static inline uint32_t temperature_sensor_ll_get_offset(void) { return REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC); diff --git a/components/esp_hal_ana_conv/esp32c61/include/hal/temperature_sensor_ll.h b/components/esp_hal_ana_conv/esp32c61/include/hal/temperature_sensor_ll.h index e0ec747fef..3dcfed41fb 100644 --- a/components/esp_hal_ana_conv/esp32c61/include/hal/temperature_sensor_ll.h +++ b/components/esp_hal_ana_conv/esp32c61/include/hal/temperature_sensor_ll.h @@ -118,6 +118,7 @@ static inline void temperature_sensor_ll_clk_sel(temperature_sensor_clk_src_t cl * * @param tsens_dac ``reg_val`` in table ``temperature_sensor_attributes`` */ +__attribute__((always_inline)) static inline void temperature_sensor_ll_set_range(uint32_t range) { REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, range); @@ -141,6 +142,7 @@ static inline uint32_t temperature_sensor_ll_get_raw_value(void) * * @return uint32_t offset value */ +__attribute__((always_inline)) static inline uint32_t temperature_sensor_ll_get_offset(void) { return REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC); diff --git a/components/esp_hal_ana_conv/esp32h2/include/hal/adc_ll.h b/components/esp_hal_ana_conv/esp32h2/include/hal/adc_ll.h index 29c8db0d1c..b89241539e 100644 --- a/components/esp_hal_ana_conv/esp32h2/include/hal/adc_ll.h +++ b/components/esp_hal_ana_conv/esp32h2/include/hal/adc_ll.h @@ -70,6 +70,12 @@ extern "C" { ---------------------------------------------------------------*/ #define ADC_LL_PWDET_CCT_DEFAULT (4) +/*--------------------------------------------------------------- + I2C SAR ADC REG PD workaround +---------------------------------------------------------------*/ +#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1 +#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8 + typedef enum { ADC_LL_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ ADC_LL_POWER_SW_ON = SAR_CTRL_LL_POWER_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ diff --git a/components/esp_hal_ana_conv/esp32h2/include/hal/temperature_sensor_ll.h b/components/esp_hal_ana_conv/esp32h2/include/hal/temperature_sensor_ll.h index 30f2fabb82..3d8a4caac4 100644 --- a/components/esp_hal_ana_conv/esp32h2/include/hal/temperature_sensor_ll.h +++ b/components/esp_hal_ana_conv/esp32h2/include/hal/temperature_sensor_ll.h @@ -117,6 +117,7 @@ static inline void temperature_sensor_ll_clk_sel(temperature_sensor_clk_src_t cl * * @param tsens_dac ``reg_val`` in table ``temperature_sensor_attributes`` */ +__attribute__((always_inline)) static inline void temperature_sensor_ll_set_range(uint32_t range) { REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, range); @@ -140,6 +141,7 @@ static inline uint32_t temperature_sensor_ll_get_raw_value(void) * * @return uint32_t offset value */ +__attribute__((always_inline)) static inline uint32_t temperature_sensor_ll_get_offset(void) { return REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC); diff --git a/components/esp_hal_ana_conv/esp32p4/include/hal/temperature_sensor_ll.h b/components/esp_hal_ana_conv/esp32p4/include/hal/temperature_sensor_ll.h index 1a72bb2897..c277079bb4 100644 --- a/components/esp_hal_ana_conv/esp32p4/include/hal/temperature_sensor_ll.h +++ b/components/esp_hal_ana_conv/esp32p4/include/hal/temperature_sensor_ll.h @@ -112,6 +112,7 @@ static inline void temperature_sensor_ll_clk_sel(temperature_sensor_clk_src_t cl * * @param tsens_dac ``reg_val`` in table ``temperature_sensor_attributes`` */ +__attribute__((always_inline)) static inline void temperature_sensor_ll_set_range(uint32_t range) { REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, range); @@ -135,6 +136,7 @@ static inline uint32_t temperature_sensor_ll_get_raw_value(void) * * @return uint32_t offset value */ +__attribute__((always_inline)) static inline uint32_t temperature_sensor_ll_get_offset(void) { return REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC); diff --git a/components/esp_hal_ana_conv/esp32s2/include/hal/adc_ll.h b/components/esp_hal_ana_conv/esp32s2/include/hal/adc_ll.h index 02f943b058..4e73306a20 100644 --- a/components/esp_hal_ana_conv/esp32s2/include/hal/adc_ll.h +++ b/components/esp_hal_ana_conv/esp32s2/include/hal/adc_ll.h @@ -68,6 +68,12 @@ extern "C" { ---------------------------------------------------------------*/ #define ADC_LL_PWDET_CCT_DEFAULT (4) +/*--------------------------------------------------------------- + I2C SAR ADC REG PD workaround +---------------------------------------------------------------*/ +#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1 +#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8 + typedef enum { ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ ADC_LL_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ diff --git a/components/esp_hal_ana_conv/esp32s2/include/hal/temperature_sensor_ll.h b/components/esp_hal_ana_conv/esp32s2/include/hal/temperature_sensor_ll.h index 76beef5144..5edc42fb0f 100644 --- a/components/esp_hal_ana_conv/esp32s2/include/hal/temperature_sensor_ll.h +++ b/components/esp_hal_ana_conv/esp32s2/include/hal/temperature_sensor_ll.h @@ -89,6 +89,7 @@ static inline void temperature_sensor_ll_clk_sel(temperature_sensor_clk_src_t cl * * @param tsens_dac ``reg_val`` in table ``temperature_sensor_attributes`` */ +__attribute__((always_inline)) static inline void temperature_sensor_ll_set_range(uint32_t tsens_dac) { REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, tsens_dac); @@ -115,6 +116,7 @@ static inline uint32_t temperature_sensor_ll_get_raw_value(void) * * @return uint32_t offset value */ +__attribute__((always_inline)) static inline uint32_t temperature_sensor_ll_get_offset(void) { return REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC); diff --git a/components/esp_hal_ana_conv/esp32s3/include/hal/adc_ll.h b/components/esp_hal_ana_conv/esp32s3/include/hal/adc_ll.h index b936ef2dd9..28e5b849f9 100644 --- a/components/esp_hal_ana_conv/esp32s3/include/hal/adc_ll.h +++ b/components/esp_hal_ana_conv/esp32s3/include/hal/adc_ll.h @@ -70,6 +70,12 @@ extern "C" { ---------------------------------------------------------------*/ #define ADC_LL_PWDET_CCT_DEFAULT (4) +/*--------------------------------------------------------------- + I2C SAR ADC REG PD workaround +---------------------------------------------------------------*/ +#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1 +#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8 + typedef enum { ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ ADC_LL_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ diff --git a/components/esp_hal_ana_conv/esp32s3/include/hal/temperature_sensor_ll.h b/components/esp_hal_ana_conv/esp32s3/include/hal/temperature_sensor_ll.h index 23a0e116b1..aa3a873dd3 100644 --- a/components/esp_hal_ana_conv/esp32s3/include/hal/temperature_sensor_ll.h +++ b/components/esp_hal_ana_conv/esp32s3/include/hal/temperature_sensor_ll.h @@ -89,6 +89,7 @@ static inline void temperature_sensor_ll_clk_sel(temperature_sensor_clk_src_t cl * * @param tsens_dac ``reg_val`` in table ``temperature_sensor_attributes`` */ +__attribute__((always_inline)) static inline void temperature_sensor_ll_set_range(uint32_t tsens_dac) { REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, tsens_dac); @@ -115,6 +116,7 @@ static inline uint32_t temperature_sensor_ll_get_raw_value(void) * * @return uint32_t offset value */ +__attribute__((always_inline)) static inline uint32_t temperature_sensor_ll_get_offset(void) { return REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC); diff --git a/components/esp_hal_ana_conv/include/hal/adc_hal.h b/components/esp_hal_ana_conv/include/hal/adc_hal.h index 521914698a..5a0ddc89ed 100644 --- a/components/esp_hal_ana_conv/include/hal/adc_hal.h +++ b/components/esp_hal_ana_conv/include/hal/adc_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_hal_ana_conv/include/hal/adc_hal_common.h b/components/esp_hal_ana_conv/include/hal/adc_hal_common.h index 734e098de0..886f015a8a 100644 --- a/components/esp_hal_ana_conv/include/hal/adc_hal_common.h +++ b/components/esp_hal_ana_conv/include/hal/adc_hal_common.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,6 +8,10 @@ #include "hal/adc_types.h" #include "hal/adc_types_private.h" +#include "soc/soc_caps.h" +#if SOC_ADC_SUPPORTED +#include "hal/adc_ll.h" +#endif #ifdef __cplusplus extern "C" { @@ -91,6 +95,21 @@ uint32_t adc_hal_self_calibration(adc_unit_t adc_n, adc_atten_t atten, bool inte #endif //SOC_ADC_CALIBRATION_V1_SUPPORTED +/*--------------------------------------------------------------- + I2C SAR ADC register backup/restore +---------------------------------------------------------------*/ +#if ADC_LL_ANA_CALI_REG_PD_WORKAROUND +/** + * @brief Backup I2C SAR ADC analog calibration related register values + */ +void adc_hal_i2c_saradc_reg_backup(void); + +/** + * @brief Restore I2C SAR ADC analog calibration related register values + */ +void adc_hal_i2c_saradc_reg_restore(void); +#endif // ADC_LL_ANA_CALI_REG_PD_WORKAROUND + #ifdef __cplusplus } #endif diff --git a/components/esp_hal_ana_conv/include/hal/temperature_sensor_hal.h b/components/esp_hal_ana_conv/include/hal/temperature_sensor_hal.h index bd76d46004..25d1ddfc5a 100644 --- a/components/esp_hal_ana_conv/include/hal/temperature_sensor_hal.h +++ b/components/esp_hal_ana_conv/include/hal/temperature_sensor_hal.h @@ -37,6 +37,11 @@ void temperature_sensor_hal_init(void); */ void temperature_sensor_hal_sync_tsens_idx(uint8_t tsens_idx); +#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION +void temperature_sensor_hal_i2c_saradc_reg_backup(void); +void temperature_sensor_hal_i2c_saradc_reg_restore(void); +#endif + #endif // SOC_TEMP_SENSOR_SUPPORTED #ifdef __cplusplus diff --git a/components/esp_hal_ana_conv/temperature_sensor_hal.c b/components/esp_hal_ana_conv/temperature_sensor_hal.c index 8855e82d73..f69b8e7f5e 100644 --- a/components/esp_hal_ana_conv/temperature_sensor_hal.c +++ b/components/esp_hal_ana_conv/temperature_sensor_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,7 @@ #include "hal/temperature_sensor_periph.h" #include "hal/log.h" #include "esp_rom_sys.h" +#include "esp_attr.h" __attribute__((unused)) static const char *TAG_TSENS = "temperature_sensor_hal"; @@ -19,6 +20,20 @@ static int s_hal_record_min = INT_NOT_USED; static int s_hal_record_max = INT_NOT_USED; static uint8_t s_hal_tsens_idx = 2; // Index for temperature attribute, set 2(middle) as default value +#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION +static uint8_t dac_offset_regi2c; + +void temperature_sensor_hal_i2c_saradc_reg_backup(void) +{ + dac_offset_regi2c = temperature_sensor_ll_get_offset(); +} + +void temperature_sensor_hal_i2c_saradc_reg_restore(void) +{ + temperature_sensor_ll_set_range(dac_offset_regi2c); +} +#endif + int temperature_sensor_hal_get_raw_value(void) { int raw_value = temperature_sensor_ll_get_raw_value(); diff --git a/components/esp_hal_clock/CMakeLists.txt b/components/esp_hal_clock/CMakeLists.txt index 8a978bae8c..8066ee34ff 100644 --- a/components/esp_hal_clock/CMakeLists.txt +++ b/components/esp_hal_clock/CMakeLists.txt @@ -1,4 +1,7 @@ idf_build_get_property(target IDF_TARGET) +if(${target} STREQUAL "linux") + return() # This component is not supported by the POSIX/Linux simulator +endif() set(srcs) set(includes "include") diff --git a/components/esp_hal_clock/esp32c2/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32c2/include/hal/clk_tree_ll.h index aa0ca72273..bf8feb3f4c 100644 --- a/components/esp_hal_clock/esp32c2/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32c2/include/hal/clk_tree_ll.h @@ -13,6 +13,7 @@ #include "soc/rtc_cntl_reg.h" #include "hal/regi2c_ctrl.h" #include "soc/regi2c_bbpll.h" +#include "soc/regi2c_defs.h" #include "soc/timer_group_struct.h" #include "soc/io_mux_reg.h" #include "hal/clkout_channel.h" @@ -284,6 +285,34 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); } +/** + * @brief Start BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_start(void) +{ + REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); +} + +/** + * @brief Stop BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_stop(void) +{ + REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); +} + +/** + * @brief Check whether BBPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool clk_ll_bbpll_calibration_is_done(void) +{ + return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); +} + /** * @brief Select the clock source for CPU_CLK * diff --git a/components/esp_hal_clock/esp32c3/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32c3/include/hal/clk_tree_ll.h index 92be119173..a1f4228ab0 100644 --- a/components/esp_hal_clock/esp32c3/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32c3/include/hal/clk_tree_ll.h @@ -13,6 +13,7 @@ #include "soc/rtc_cntl_reg.h" #include "hal/regi2c_ctrl.h" #include "soc/regi2c_bbpll.h" +#include "soc/regi2c_defs.h" #include "soc/timer_group_struct.h" #include "soc/io_mux_reg.h" #include "hal/clkout_channel.h" @@ -393,6 +394,15 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1); } +/** + * @brief Start BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_start(void) +{ + REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); +} + /** * @brief Select the clock source for CPU_CLK * diff --git a/components/esp_hal_clock/esp32c5/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32c5/include/hal/clk_tree_ll.h index b723f3f11b..7e2c3f8d18 100644 --- a/components/esp_hal_clock/esp32c5/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32c5/include/hal/clk_tree_ll.h @@ -19,6 +19,7 @@ #include "hal/clkout_channel.h" #include "hal/regi2c_ctrl.h" #include "soc/regi2c_bbpll.h" +#include "modem/i2c_ana_mst_reg.h" #include "hal/assert.h" #include "hal/log.h" #include "esp32c5/rom/rtc.h" @@ -299,6 +300,34 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); } +/** + * @brief Start BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_start(void) +{ + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); +} + +/** + * @brief Stop BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_stop(void) +{ + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); +} + +/** + * @brief Check whether BBPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool clk_ll_bbpll_calibration_is_done(void) +{ + return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); +} + /** * @brief To enable the change of soc_clk_sel, cpu_div_num, and ahb_div_num */ diff --git a/components/esp_hal_clock/esp32c6/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32c6/include/hal/clk_tree_ll.h index 96c47b2be0..cfc119fc3c 100644 --- a/components/esp_hal_clock/esp32c6/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32c6/include/hal/clk_tree_ll.h @@ -14,6 +14,7 @@ #include "soc/pmu_reg.h" #include "hal/regi2c_ctrl.h" #include "soc/regi2c_bbpll.h" +#include "modem/i2c_ana_mst_reg.h" #include "soc/timer_group_struct.h" #include "soc/io_mux_reg.h" #include "hal/clkout_channel.h" @@ -332,6 +333,34 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); } +/** + * @brief Start BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_start(void) +{ + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); +} + +/** + * @brief Stop BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_stop(void) +{ + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); +} + +/** + * @brief Check whether BBPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool clk_ll_bbpll_calibration_is_done(void) +{ + return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); +} + /** * @brief Select the clock source for CPU_CLK (SOC Clock Root) * diff --git a/components/esp_hal_clock/esp32c61/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32c61/include/hal/clk_tree_ll.h index a16481eced..4d355cafee 100644 --- a/components/esp_hal_clock/esp32c61/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32c61/include/hal/clk_tree_ll.h @@ -16,6 +16,7 @@ #include "hal/clkout_channel.h" #include "hal/regi2c_ctrl.h" #include "soc/regi2c_bbpll.h" +#include "modem/i2c_ana_mst_reg.h" #include "hal/assert.h" #include "hal/log.h" #include "esp32c61/rom/rtc.h" @@ -275,6 +276,34 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); } +/** + * @brief Start BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_start(void) +{ + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); +} + +/** + * @brief Stop BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_stop(void) +{ + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); +} + +/** + * @brief Check whether BBPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool clk_ll_bbpll_calibration_is_done(void) +{ + return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); +} + /** * @brief To enable the change of soc_clk_sel, cpu_div_num, and ahb_div_num */ diff --git a/components/esp_hal_clock/esp32h2/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32h2/include/hal/clk_tree_ll.h index 36ac154879..766869cc6f 100644 --- a/components/esp_hal_clock/esp32h2/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32h2/include/hal/clk_tree_ll.h @@ -14,6 +14,7 @@ #include "soc/pmu_reg.h" #include "hal/regi2c_ctrl.h" #include "soc/regi2c_bbpll.h" +#include "modem/i2c_ana_mst_reg.h" #include "soc/regi2c_pmu.h" #include "soc/timer_group_struct.h" #include "soc/io_mux_reg.h" @@ -326,6 +327,34 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, oc_dlref_sel); } +/** + * @brief Start BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_start(void) +{ + REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); +} + +/** + * @brief Stop BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_stop(void) +{ + REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); +} + +/** + * @brief Check whether BBPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool clk_ll_bbpll_calibration_is_done(void) +{ + return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); +} + /** * @brief Get FLASH_PLL_CLK frequency * diff --git a/components/esp_hal_clock/esp32h21/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32h21/include/hal/clk_tree_ll.h index 9090ce2cc8..8b3d0185bd 100644 --- a/components/esp_hal_clock/esp32h21/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32h21/include/hal/clk_tree_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,6 +14,7 @@ #include "soc/pmu_reg.h" #include "hal/regi2c_ctrl.h" #include "soc/regi2c_bbpll.h" +#include "modem/i2c_ana_mst_reg.h" #include "hal/assert.h" #include "hal/log.h" #include "esp32h21/rom/rtc.h" @@ -277,6 +278,34 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, oc_dlref_sel); } +/** + * @brief Start BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_start(void) +{ + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); +} + +/** + * @brief Stop BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_stop(void) +{ + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); +} + +/** + * @brief Check whether BBPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool clk_ll_bbpll_calibration_is_done(void) +{ + return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); +} + // /** // * @brief Get XTAL_X2_CLK frequency // * diff --git a/components/esp_hal_clock/esp32h4/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32h4/include/hal/clk_tree_ll.h index 39c8658529..1a8e16f053 100644 --- a/components/esp_hal_clock/esp32h4/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32h4/include/hal/clk_tree_ll.h @@ -16,6 +16,7 @@ #include "hal/clkout_channel.h" #include "hal/regi2c_ctrl.h" #include "soc/regi2c_bbpll.h" +#include "modem/i2c_ana_mst_reg.h" #include "esp32h4/rom/rtc.h" #include "hal/assert.h" #include "hal/log.h" @@ -282,6 +283,34 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, oc_dlref_sel); } +/** + * @brief Start BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_start(void) +{ + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); +} + +/** + * @brief Stop BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_stop(void) +{ + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); +} + +/** + * @brief Check whether BBPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool clk_ll_bbpll_calibration_is_done(void) +{ + return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); +} + /** * @brief Get XTAL_X2_CLK frequency * diff --git a/components/esp_hal_clock/esp32p4/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32p4/include/hal/clk_tree_ll.h index 8e7577fc78..b33e7d4da4 100644 --- a/components/esp_hal_clock/esp32p4/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32p4/include/hal/clk_tree_ll.h @@ -420,12 +420,38 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_set_config(uint32_ uint8_t i2c_cpll_dcur = (1 << I2C_CPLL_OC_DLREF_SEL_LSB) | (3 << I2C_CPLL_OC_DHREF_SEL_LSB) | dcur; // There are sequential regi2c operations in `clk_ll_cpll_set_config`, use the raw regi2c API with one lock wrapper to save time. REGI2C_ENTER_CRITICAL(); - esp_rom_regi2c_write(I2C_CPLL, I2C_CPLL_HOSTID, I2C_CPLL_OC_REF_DIV, i2c_cpll_lref); - esp_rom_regi2c_write(I2C_CPLL, I2C_CPLL_HOSTID, I2C_CPLL_OC_DIV_7_0, i2c_cpll_div_7_0); - esp_rom_regi2c_write(I2C_CPLL, I2C_CPLL_HOSTID, I2C_CPLL_OC_DCUR, i2c_cpll_dcur); + regi2c_impl_write(I2C_CPLL, I2C_CPLL_HOSTID, I2C_CPLL_OC_REF_DIV, i2c_cpll_lref); + regi2c_impl_write(I2C_CPLL, I2C_CPLL_HOSTID, I2C_CPLL_OC_DIV_7_0, i2c_cpll_div_7_0); + regi2c_impl_write(I2C_CPLL, I2C_CPLL_HOSTID, I2C_CPLL_OC_DCUR, i2c_cpll_dcur); REGI2C_EXIT_CRITICAL(); } +/** + * @brief Start CPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_cpll_calibration_start(void) +{ + HP_SYS_CLKRST.ana_pll_ctrl0.reg_cpu_pll_cal_stop = 0; +} + +/** + * @brief Stop CPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_cpll_calibration_stop(void) +{ + HP_SYS_CLKRST.ana_pll_ctrl0.reg_cpu_pll_cal_stop = 1; +} + +/** + * @brief Check whether CPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool clk_ll_cpll_calibration_is_done(void) +{ + return HP_SYS_CLKRST.ana_pll_ctrl0.reg_cpu_pll_cal_end; +} + /** * @brief Get MPLL_CLK frequency (only reliable when MPLL power is on) * @@ -452,20 +478,46 @@ static inline __attribute__((always_inline)) void clk_ll_mpll_set_config(uint32_ // There are sequential regi2c operations in `clk_ll_mpll_set_config`, use the raw regi2c API with one lock wrapper to save time. REGI2C_ENTER_CRITICAL(); - uint8_t mpll_dhref_val = esp_rom_regi2c_read(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_DHREF); - esp_rom_regi2c_write(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_DHREF, mpll_dhref_val | (3 << I2C_MPLL_DHREF_LSB)); - uint8_t mpll_rstb_val = esp_rom_regi2c_read(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_IR_CAL_RSTB); - esp_rom_regi2c_write(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_IR_CAL_RSTB, mpll_rstb_val & 0xdf); - esp_rom_regi2c_write(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_IR_CAL_RSTB, mpll_rstb_val | (1 << I2C_MPLL_IR_CAL_RSTB_lSB)); + uint8_t mpll_dhref_val = regi2c_impl_read(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_DHREF); + regi2c_impl_write(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_DHREF, mpll_dhref_val | (3 << I2C_MPLL_DHREF_LSB)); + uint8_t mpll_rstb_val = regi2c_impl_read(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_IR_CAL_RSTB); + regi2c_impl_write(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_IR_CAL_RSTB, mpll_rstb_val & 0xdf); + regi2c_impl_write(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_IR_CAL_RSTB, mpll_rstb_val | (1 << I2C_MPLL_IR_CAL_RSTB_lSB)); // MPLL_Freq = XTAL_Freq * (div + 1) / (ref_div + 1) uint8_t ref_div = 1; uint8_t div = mpll_freq_mhz / 20 - 1; uint8_t val = ((div << 3) | ref_div); - esp_rom_regi2c_write(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_DIV_REG_ADDR, val); + regi2c_impl_write(I2C_MPLL, I2C_MPLL_HOSTID, I2C_MPLL_DIV_REG_ADDR, val); REGI2C_EXIT_CRITICAL(); } +/** + * @brief Start MPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_mpll_calibration_start(void) +{ + HP_SYS_CLKRST.ana_pll_ctrl0.reg_mspi_cal_stop = 0; +} + +/** + * @brief Stop MPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_mpll_calibration_stop(void) +{ + HP_SYS_CLKRST.ana_pll_ctrl0.reg_mspi_cal_stop = 1; +} + +/** + * @brief Check whether MPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool clk_ll_mpll_calibration_is_done(void) +{ + return HP_SYS_CLKRST.ana_pll_ctrl0.reg_mspi_cal_end; +} + /** * @brief Get APLL configuration which can be used to calculate APLL frequency * diff --git a/components/esp_hal_clock/esp32s3/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32s3/include/hal/clk_tree_ll.h index 7e0b79aed1..d55680c3ab 100644 --- a/components/esp_hal_clock/esp32s3/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32s3/include/hal/clk_tree_ll.h @@ -13,6 +13,7 @@ #include "soc/rtc_cntl_reg.h" #include "hal/regi2c_ctrl.h" #include "soc/regi2c_bbpll.h" +#include "soc/regi2c_defs.h" #include "soc/timer_group_struct.h" #include "soc/io_mux_reg.h" #include "hal/clkout_channel.h" @@ -386,6 +387,34 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); } +/** + * @brief Start BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_start(void) +{ + REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); +} + +/** + * @brief Stop BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_calibration_stop(void) +{ + REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); +} + +/** + * @brief Check whether BBPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool clk_ll_bbpll_calibration_is_done(void) +{ + return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); +} + /** * @brief Select the clock source for CPU_CLK * diff --git a/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h index 58c7de91e0..f5c0c4faa4 100644 --- a/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h @@ -351,6 +351,32 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_set_config(uint32_ // TODO: [ESP32S31] IDF-14733 } +/** + * @brief Start CPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_cpll_calibration_start(void) +{ + CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP); +} + +/** + * @brief Stop CPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_cpll_calibration_stop(void) +{ + SET_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP); +} + +/** + * @brief Check whether CPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool clk_ll_cpll_calibration_is_done(void) +{ + return REG_GET_BIT(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_END); +} + /** * @brief Get MPLL_CLK frequency (only reliable when MPLL power is on) * @@ -376,6 +402,32 @@ static inline __attribute__((always_inline)) void clk_ll_mpll_set_config(uint32_ // TODO: [ESP32S31] IDF-14733 } +/** + * @brief Start MPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_mpll_calibration_start(void) +{ + CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_STOP); +} + +/** + * @brief Stop MPLL self-calibration + */ +static inline __attribute__((always_inline)) void clk_ll_mpll_calibration_stop(void) +{ + SET_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_STOP); +} + +/** + * @brief Check whether MPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool clk_ll_mpll_calibration_is_done(void) +{ + return REG_GET_BIT(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_END); +} + /** * @brief Get APLL configuration which can be used to calculate APLL frequency * diff --git a/components/esp_hal_regi2c/CMakeLists.txt b/components/esp_hal_regi2c/CMakeLists.txt new file mode 100644 index 0000000000..cf2529d8e2 --- /dev/null +++ b/components/esp_hal_regi2c/CMakeLists.txt @@ -0,0 +1,29 @@ +idf_build_get_property(target IDF_TARGET) +if(${target} STREQUAL "linux") + return() # This component is not supported by the POSIX/Linux simulator +endif() + +set(srcs "") +set(includes "include") + +# Add target-specific include directory if it exists +if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/include") + list(APPEND includes "${target}/include") +endif() + +# Per-target regi2c implementation sources (replaces ROM implementation when needed) +if(NOT CONFIG_ESP_ROM_HAS_REGI2C_IMPL) + list(APPEND srcs "${target}/regi2c_impl.c") +endif() + +idf_component_register( + SRCS ${srcs} + INCLUDE_DIRS ${includes} + REQUIRES soc hal + LDFRAGMENTS linker.lf +) + +# Link the ROM REGI2C HAL implementation linker script on specific targets +if(CONFIG_ESP_ROM_HAS_REGI2C_IMPL) + target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/rom.regi2c.ld") +endif() diff --git a/components/esp_hal_regi2c/README.md b/components/esp_hal_regi2c/README.md new file mode 100644 index 0000000000..a70ebdf88d --- /dev/null +++ b/components/esp_hal_regi2c/README.md @@ -0,0 +1,31 @@ +# ESP Hardware Abstraction Layer for Analog I2C Master (REGI2C) + +> [!NOTE] +> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems. + +## Overview + +The `esp_hal_regi2c` component provides the **Hardware Abstraction Layer** for the analog I2C master peripheral (commonly referred to as REGI2C) across ESP-IDF supported targets. This peripheral is used to access internal analog registers for calibration, PLL configuration, and other low-level analog operations. + +## Architecture + +The REGI2C HAL is organized in two layers: + +1. **Implementation Layer (Upper)**: Per-target implementation sources (`regi2c_impl.c`) provides the interface to read and write to the analog i2c **device** registers. +2. **Low-Level Layer (Bottom)**: Per-target `regi2c_ctrl_ll.h` contains functions that configure analog I2C power, clock gating, reset, bus access. + +## Usage + +This HAL is consumed by ESP-IDF internal components to perform analog register access for calibration and configuration. + +Developers may interact with the HAL directly: `regi2c_impl_write`, `regi2c_impl_write_mask`, `regi2c_impl_read`, and `regi2c_impl_read_mask` are supposed to be the only interfaces to do analog i2c register read and write operations. Atomicity and analog i2c clock needs to be taken care separately. + +Or `esp_hw_support/regi2c_ctrl.h` provides fully wrapped macros `REGI2C_WRITE`, `REGI2C_WRITE_MASK`, `REGI2C_READ`, and `REGI2C_READ_MASK` that can be used directly. + +API stability is not guaranteed during beta. + +## Dependencies + +- `soc`: SoC register definitions and analog I2C master constants +- `hal`: Common HAL utilities and macros + diff --git a/components/hal/esp32/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32/include/hal/regi2c_ctrl_ll.h similarity index 100% rename from components/hal/esp32/include/hal/regi2c_ctrl_ll.h rename to components/esp_hal_regi2c/esp32/include/hal/regi2c_ctrl_ll.h diff --git a/components/esp_hal_regi2c/esp32/rom.regi2c.ld b/components/esp_hal_regi2c/esp32/rom.regi2c.ld new file mode 100644 index 0000000000..d421b24a9a --- /dev/null +++ b/components/esp_hal_regi2c/esp32/rom.regi2c.ld @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +PROVIDE ( _regi2c_impl_read = 0x40004148 ); +PROVIDE ( _regi2c_impl_read_mask = 0x400041c0 ); +PROVIDE ( _regi2c_impl_write = 0x400041a4 ); +PROVIDE ( _regi2c_impl_write_mask = 0x400041fc ); diff --git a/components/hal/esp32c3/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32c2/include/hal/regi2c_ctrl_ll.h similarity index 67% rename from components/hal/esp32c3/include/hal/regi2c_ctrl_ll.h rename to components/esp_hal_regi2c/esp32c2/include/hal/regi2c_ctrl_ll.h index fb86a52fb2..74ea7e25c7 100644 --- a/components/hal/esp32c3/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32c2/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #pragma once #include +#include #include "soc/soc.h" #include "soc/regi2c_defs.h" @@ -14,13 +15,6 @@ extern "C" { #endif -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround for calibration error when waking up from light sleep - */ -#define REGI2C_LL_ANA_CALI_PD_WORKAROUND 1 -#define REGI2C_LL_ANA_CALI_BYTE_NUM 8 - /** * @brief Reset (Disable) the I2C internal bus for all regi2c registers */ @@ -37,15 +31,6 @@ static inline void regi2c_ctrl_ll_i2c_bbpll_enable(void) CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_BBPLL_M); } -/** - * @brief Start BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) -{ - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); -} - /** * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ diff --git a/components/esp_hal_regi2c/esp32c2/rom.regi2c.ld b/components/esp_hal_regi2c/esp32c2/rom.regi2c.ld new file mode 100644 index 0000000000..38599278fe --- /dev/null +++ b/components/esp_hal_regi2c/esp32c2/rom.regi2c.ld @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +PROVIDE ( _regi2c_impl_read = 0x400022ec ); +PROVIDE ( _regi2c_impl_read_mask = 0x400022f8 ); +PROVIDE ( _regi2c_impl_write = 0x400022f4 ); +PROVIDE ( _regi2c_impl_write_mask = 0x400022fc ); diff --git a/components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32c3/include/hal/regi2c_ctrl_ll.h similarity index 51% rename from components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h rename to components/esp_hal_regi2c/esp32c3/include/hal/regi2c_ctrl_ll.h index b31be65e4b..1a7d55ee95 100644 --- a/components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32c3/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,7 +7,6 @@ #pragma once #include -#include #include "soc/soc.h" #include "soc/regi2c_defs.h" @@ -15,13 +14,6 @@ extern "C" { #endif -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround for calibration error when waking up from light sleep - */ -#define REGI2C_LL_ANA_CALI_PD_WORKAROUND 1 -#define REGI2C_LL_ANA_CALI_BYTE_NUM 8 - /** * @brief Reset (Disable) the I2C internal bus for all regi2c registers */ @@ -38,34 +30,6 @@ static inline void regi2c_ctrl_ll_i2c_bbpll_enable(void) CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_BBPLL_M); } -/** - * @brief Start BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) -{ - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); -} - -/** - * @brief Stop BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) -{ - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); -} - -/** - * @brief Check whether BBPLL calibration is done - * - * @return True if calibration is done; otherwise false - */ -static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) -{ - return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); -} - /** * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ diff --git a/components/esp_hal_regi2c/esp32c3/rom.regi2c.ld b/components/esp_hal_regi2c/esp32c3/rom.regi2c.ld new file mode 100644 index 0000000000..96e59671d9 --- /dev/null +++ b/components/esp_hal_regi2c/esp32c3/rom.regi2c.ld @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +PROVIDE ( _regi2c_impl_read = 0x40001954 ); +PROVIDE ( _regi2c_impl_read_mask = 0x40001958 ); +PROVIDE ( _regi2c_impl_write = 0x4000195c ); +PROVIDE ( _regi2c_impl_write_mask = 0x40001960 ); diff --git a/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32c5/include/hal/regi2c_ctrl_ll.h similarity index 74% rename from components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h rename to components/esp_hal_regi2c/esp32c5/include/hal/regi2c_ctrl_ll.h index c0d2c516eb..6b103b0bbb 100644 --- a/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32c5/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,10 +9,9 @@ #include #include #include "soc/soc.h" -#include "soc/pmu_reg.h" #include "modem/modem_lpcon_struct.h" #include "modem/modem_syscon_struct.h" -#include "soc/i2c_ana_mst_reg.h" +#include "soc/pmu_reg.h" #ifdef __cplusplus extern "C" { @@ -75,34 +74,6 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configur MODEM_SYSCON.clk_conf.clk_i2c_mst_sel_160m = 1; } -/** - * @brief Start BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) -{ - REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); - REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); -} - -/** - * @brief Stop BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) -{ - REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); - REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); -} - -/** - * @brief Check whether BBPLL calibration is done - * - * @return True if calibration is done; otherwise false - */ -static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) -{ - return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); -} - /** * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ diff --git a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c b/components/esp_hal_regi2c/esp32c5/regi2c_impl.c similarity index 79% rename from components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c rename to components/esp_hal_regi2c/esp32c5/regi2c_impl.c index 868caeb197..7c9e4a0aec 100644 --- a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c +++ b/components/esp_hal_regi2c/esp32c5/regi2c_impl.c @@ -1,11 +1,11 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "esp_rom_sys.h" -#include "esp_attr.h" -#include "soc/i2c_ana_mst_reg.h" +#include "hal/regi2c_impl.h" +#include "hal/assert.h" +#include "modem/i2c_ana_mst_reg.h" #include "hal/regi2c_ctrl_ll.h" #define REGI2C_BIAS_MST_SEL (BIT(8)) @@ -66,15 +66,10 @@ /* SLAVE END */ -uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl"))); -uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl"))); -void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); -void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); - -static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) +static uint8_t regi2c_enable_block(uint8_t block) { uint32_t i2c_sel = 0; - assert(regi2c_ctrl_ll_master_is_clock_enabled()); + HAL_ASSERT(regi2c_ctrl_ll_master_is_clock_enabled()); /* Before config I2C register, enable corresponding slave. */ switch (block) { @@ -100,10 +95,10 @@ static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) break; } - return (uint8_t)(i2c_sel ? 0: 1); + return (uint8_t)(i2c_sel ? 0 : 1); } -uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) +uint8_t _regi2c_impl_read(uint8_t block, uint8_t host_id, uint8_t reg_add) { (void)host_id; uint8_t i2c_sel = regi2c_enable_block(block); @@ -118,9 +113,9 @@ uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_a return ret; } -uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +uint8_t _regi2c_impl_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) { - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); uint8_t i2c_sel = regi2c_enable_block(block); (void)host_id; @@ -135,7 +130,7 @@ uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t return ret; } -void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +void _regi2c_impl_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) { (void)host_id; uint8_t i2c_sel = regi2c_enable_block(block); @@ -149,10 +144,10 @@ void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); } -void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +void _regi2c_impl_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) { (void)host_id; - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); uint8_t i2c_sel = regi2c_enable_block(block); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); @@ -166,9 +161,9 @@ void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t re temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) - | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) - | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); } diff --git a/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32c6/include/hal/regi2c_ctrl_ll.h similarity index 74% rename from components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h rename to components/esp_hal_regi2c/esp32c6/include/hal/regi2c_ctrl_ll.h index ff8f88433b..14a5010868 100644 --- a/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32c6/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,6 @@ #include #include #include "soc/soc.h" -#include "soc/i2c_ana_mst_reg.h" #include "soc/pmu_reg.h" #include "modem/modem_lpcon_struct.h" @@ -74,34 +73,6 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configur MODEM_LPCON.i2c_mst_clk_conf.clk_i2c_mst_sel_160m = 1; } -/** - * @brief Start BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) -{ - REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); - REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); -} - -/** - * @brief Stop BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) -{ - REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); - REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); -} - -/** - * @brief Check whether BBPLL calibration is done - * - * @return True if calibration is done; otherwise false - */ -static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) -{ - return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); -} - /** * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ diff --git a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c b/components/esp_hal_regi2c/esp32c6/regi2c_impl.c similarity index 79% rename from components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c rename to components/esp_hal_regi2c/esp32c6/regi2c_impl.c index cf8479d8bc..e1339eb285 100644 --- a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c +++ b/components/esp_hal_regi2c/esp32c6/regi2c_impl.c @@ -1,11 +1,11 @@ /* - * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "esp_rom_sys.h" -#include "esp_attr.h" -#include "soc/i2c_ana_mst_reg.h" +#include "hal/regi2c_impl.h" +#include "hal/assert.h" +#include "modem/i2c_ana_mst_reg.h" #include "hal/regi2c_ctrl_ll.h" /** * BB - 0x67 - BIT0 @@ -77,15 +77,10 @@ /* SLAVE END */ -uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl"))); -uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl"))); -void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); -void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); - -static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) +static uint8_t regi2c_enable_block(uint8_t block) { uint32_t i2c_sel = 0; - assert(regi2c_ctrl_ll_master_is_clock_enabled()); + HAL_ASSERT(regi2c_ctrl_ll_master_is_clock_enabled()); /* Before config I2C register, enable corresponding slave. */ switch (block) { @@ -111,10 +106,10 @@ static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) break; } - return (uint8_t)(i2c_sel ? 0: 1); + return (uint8_t)(i2c_sel ? 0 : 1); } -uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) +uint8_t _regi2c_impl_read(uint8_t block, uint8_t host_id, uint8_t reg_add) { (void)host_id; uint8_t i2c_sel = regi2c_enable_block(block); @@ -129,9 +124,9 @@ uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_a return ret; } -uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +uint8_t _regi2c_impl_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) { - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); uint8_t i2c_sel = regi2c_enable_block(block); (void)host_id; @@ -146,7 +141,7 @@ uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t return ret; } -void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +void _regi2c_impl_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) { (void)host_id; uint8_t i2c_sel = regi2c_enable_block(block); @@ -161,10 +156,10 @@ void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add } -void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +void _regi2c_impl_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) { (void)host_id; - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); uint8_t i2c_sel = regi2c_enable_block(block); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); @@ -178,9 +173,9 @@ void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t re temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) - | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) - | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); } diff --git a/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32c61/include/hal/regi2c_ctrl_ll.h similarity index 74% rename from components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h rename to components/esp_hal_regi2c/esp32c61/include/hal/regi2c_ctrl_ll.h index 96ba5aa199..90914c5fe2 100644 --- a/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32c61/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,10 +9,9 @@ #include #include #include "soc/soc.h" +#include "soc/pmu_reg.h" #include "modem/modem_lpcon_struct.h" #include "modem/modem_syscon_struct.h" -#include "soc/i2c_ana_mst_reg.h" -#include "soc/pmu_reg.h" #ifdef __cplusplus extern "C" { @@ -75,34 +74,6 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configur MODEM_SYSCON.clk_conf.clk_i2c_mst_sel_160m = 1; } -/** - * @brief Start BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) -{ - REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); - REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); -} - -/** - * @brief Stop BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) -{ - REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); - REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); -} - -/** - * @brief Check whether BBPLL calibration is done - * - * @return True if calibration is done; otherwise false - */ -static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) -{ - return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); -} - /** * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c b/components/esp_hal_regi2c/esp32c61/regi2c_impl.c similarity index 79% rename from components/esp_rom/patches/esp_rom_regi2c_esp32c61.c rename to components/esp_hal_regi2c/esp32c61/regi2c_impl.c index 868caeb197..7c9e4a0aec 100644 --- a/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c +++ b/components/esp_hal_regi2c/esp32c61/regi2c_impl.c @@ -1,11 +1,11 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "esp_rom_sys.h" -#include "esp_attr.h" -#include "soc/i2c_ana_mst_reg.h" +#include "hal/regi2c_impl.h" +#include "hal/assert.h" +#include "modem/i2c_ana_mst_reg.h" #include "hal/regi2c_ctrl_ll.h" #define REGI2C_BIAS_MST_SEL (BIT(8)) @@ -66,15 +66,10 @@ /* SLAVE END */ -uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl"))); -uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl"))); -void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); -void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); - -static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) +static uint8_t regi2c_enable_block(uint8_t block) { uint32_t i2c_sel = 0; - assert(regi2c_ctrl_ll_master_is_clock_enabled()); + HAL_ASSERT(regi2c_ctrl_ll_master_is_clock_enabled()); /* Before config I2C register, enable corresponding slave. */ switch (block) { @@ -100,10 +95,10 @@ static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) break; } - return (uint8_t)(i2c_sel ? 0: 1); + return (uint8_t)(i2c_sel ? 0 : 1); } -uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) +uint8_t _regi2c_impl_read(uint8_t block, uint8_t host_id, uint8_t reg_add) { (void)host_id; uint8_t i2c_sel = regi2c_enable_block(block); @@ -118,9 +113,9 @@ uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_a return ret; } -uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +uint8_t _regi2c_impl_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) { - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); uint8_t i2c_sel = regi2c_enable_block(block); (void)host_id; @@ -135,7 +130,7 @@ uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t return ret; } -void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +void _regi2c_impl_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) { (void)host_id; uint8_t i2c_sel = regi2c_enable_block(block); @@ -149,10 +144,10 @@ void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); } -void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +void _regi2c_impl_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) { (void)host_id; - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); uint8_t i2c_sel = regi2c_enable_block(block); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); @@ -166,9 +161,9 @@ void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t re temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) - | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) - | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); } diff --git a/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32h2/include/hal/regi2c_ctrl_ll.h similarity index 68% rename from components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h rename to components/esp_hal_regi2c/esp32h2/include/hal/regi2c_ctrl_ll.h index 342cad0811..477f7bff1f 100644 --- a/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32h2/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,6 @@ #include #include #include "soc/soc.h" -#include "soc/i2c_ana_mst_reg.h" #include "soc/pmu_reg.h" #include "modem/modem_lpcon_struct.h" @@ -19,13 +18,6 @@ extern "C" { #define ANA_I2C_MST_CLK_HAS_ROOT_GATING 1 /*!< Any regi2c operation needs enable the analog i2c master clock first */ -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround for calibration error when waking up from light sleep - */ -#define REGI2C_LL_ANA_CALI_PD_WORKAROUND 1 -#define REGI2C_LL_ANA_CALI_BYTE_NUM 8 - /** * @brief Enable analog I2C master clock */ @@ -81,34 +73,6 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configur // Nothing to configure } -/** - * @brief Start BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) -{ - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); -} - -/** - * @brief Stop BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) -{ - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); -} - -/** - * @brief Check whether BBPLL calibration is done - * - * @return True if calibration is done; otherwise false - */ -static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) -{ - return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); -} - /** * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32h2.c b/components/esp_hal_regi2c/esp32h2/regi2c_impl.c similarity index 79% rename from components/esp_rom/patches/esp_rom_regi2c_esp32h2.c rename to components/esp_hal_regi2c/esp32h2/regi2c_impl.c index e42c3493a6..884a9b75cb 100644 --- a/components/esp_rom/patches/esp_rom_regi2c_esp32h2.c +++ b/components/esp_hal_regi2c/esp32h2/regi2c_impl.c @@ -1,11 +1,11 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "esp_rom_sys.h" -#include "esp_attr.h" -#include "soc/i2c_ana_mst_reg.h" +#include "hal/regi2c_impl.h" +#include "hal/assert.h" +#include "modem/i2c_ana_mst_reg.h" #include "hal/regi2c_ctrl_ll.h" /** @@ -78,15 +78,10 @@ /* SLAVE END */ -uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl"))); -uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl"))); -void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); -void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); - -static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) +static uint8_t regi2c_enable_block(uint8_t block) { uint32_t i2c_sel = 0; - assert(regi2c_ctrl_ll_master_is_clock_enabled()); + HAL_ASSERT(regi2c_ctrl_ll_master_is_clock_enabled()); /* Before config I2C register, enable corresponding slave. */ switch (block) { @@ -112,10 +107,10 @@ static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) break; } - return (uint8_t)(i2c_sel ? 0: 1); + return (uint8_t)(i2c_sel ? 0 : 1); } -uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) +uint8_t _regi2c_impl_read(uint8_t block, uint8_t host_id, uint8_t reg_add) { (void)host_id; uint8_t i2c_sel = regi2c_enable_block(block); @@ -130,9 +125,9 @@ uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_a return ret; } -uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +uint8_t _regi2c_impl_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) { - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); uint8_t i2c_sel = regi2c_enable_block(block); (void)host_id; @@ -147,7 +142,7 @@ uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t return ret; } -void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +void _regi2c_impl_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) { (void)host_id; uint8_t i2c_sel = regi2c_enable_block(block); @@ -162,10 +157,10 @@ void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add } -void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +void _regi2c_impl_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) { (void)host_id; - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); uint8_t i2c_sel = regi2c_enable_block(block); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); @@ -179,9 +174,9 @@ void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t re temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) - | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) - | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); } diff --git a/components/hal/esp32h21/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32h21/include/hal/regi2c_ctrl_ll.h similarity index 71% rename from components/hal/esp32h21/include/hal/regi2c_ctrl_ll.h rename to components/esp_hal_regi2c/esp32h21/include/hal/regi2c_ctrl_ll.h index 68a0b93384..422f2e5215 100644 --- a/components/hal/esp32h21/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32h21/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,6 @@ #include #include #include "soc/soc.h" -#include "soc/i2c_ana_mst_reg.h" #include "soc/pmu_reg.h" #include "modem/modem_lpcon_struct.h" @@ -69,34 +68,6 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configur // Nothing to configure } -/** - * @brief Start BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) -{ - REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); - REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); -} - -/** - * @brief Stop BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) -{ - REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); - REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); -} - -/** - * @brief Check whether BBPLL calibration is done - * - * @return True if calibration is done; otherwise false - */ -static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) -{ - return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); -} - /** * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32h21.c b/components/esp_hal_regi2c/esp32h21/regi2c_impl.c similarity index 50% rename from components/esp_rom/patches/esp_rom_regi2c_esp32h21.c rename to components/esp_hal_regi2c/esp32h21/regi2c_impl.c index 008385b959..6fdb361392 100644 --- a/components/esp_rom/patches/esp_rom_regi2c_esp32h21.c +++ b/components/esp_hal_regi2c/esp32h21/regi2c_impl.c @@ -1,13 +1,13 @@ /** - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "esp_rom_sys.h" -#include "esp_attr.h" -#include "soc/i2c_ana_mst_reg.h" +#include "hal/regi2c_impl.h" +#include "hal/assert.h" +#include "modem/i2c_ana_mst_reg.h" #include "hal/regi2c_ctrl_ll.h" -#include "sdkconfig.h" +#include "hal/config.h" /* SLAVE */ #define REGI2C_BBPLL 0x66 // regi2c_bbpll.h @@ -22,57 +22,52 @@ /* SLAVE END */ -uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl"))); -uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl"))); -void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); -void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); - -static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) +static uint8_t regi2c_enable_block(uint8_t block) { uint32_t i2c_sel = 0; -#if !CONFIG_IDF_ENV_FPGA // on FPGA, unable to manipulate modem registers, skip the check - assert(regi2c_ctrl_ll_master_is_clock_enabled()); +#if !HAL_CONFIG(ENV_FPGA) // on FPGA, unable to manipulate modem registers, skip the check + HAL_ASSERT(regi2c_ctrl_ll_master_is_clock_enabled()); #endif /* Before config I2C register, enable corresponding slave. */ switch (block) { - case REGI2C_BBPLL: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBPLL_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBPLL_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; - case REGI2C_BBTOP: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBTOP_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBTOP_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; - case REGI2C_DCDC: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PMU_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PMU_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; - case REGI2C_PERIF: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PERIF_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PERIF_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; - case REGI2C_RFPLL: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PLL_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PLL_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; - case REGI2C_SDM: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_SDM_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_SDM_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; - case REGI2C_TXTOP: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_TXTOP_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_TXTOP_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; - case REGI2C_ULP: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_ULP_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_ULP_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; + case REGI2C_BBPLL: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBPLL_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBPLL_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_BBTOP: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBTOP_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBTOP_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_DCDC: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PMU_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PMU_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_PERIF: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PERIF_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PERIF_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_RFPLL: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PLL_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PLL_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_SDM: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_SDM_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_SDM_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_TXTOP: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_TXTOP_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_TXTOP_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_ULP: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_ULP_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_ULP_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; } return (uint8_t)(i2c_sel ? 0 : 1); } -uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) +uint8_t _regi2c_impl_read(uint8_t block, uint8_t host_id, uint8_t reg_add) { (void)host_id; uint8_t i2c_sel = regi2c_enable_block(block); @@ -87,9 +82,9 @@ uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_a return ret; } -uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +uint8_t _regi2c_impl_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) { - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); uint8_t i2c_sel = regi2c_enable_block(block); (void)host_id; @@ -104,7 +99,7 @@ uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t return ret; } -void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +void _regi2c_impl_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) { (void)host_id; uint8_t i2c_sel = regi2c_enable_block(block); @@ -119,10 +114,10 @@ void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add } -void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +void _regi2c_impl_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) { (void)host_id; - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); uint8_t i2c_sel = regi2c_enable_block(block); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); @@ -136,9 +131,9 @@ void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t re temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) - | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) - | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); } diff --git a/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32h4/include/hal/regi2c_ctrl_ll.h similarity index 77% rename from components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h rename to components/esp_hal_regi2c/esp32h4/include/hal/regi2c_ctrl_ll.h index c241530213..ff476dabb4 100644 --- a/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32h4/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,6 @@ #include #include #include "soc/soc.h" -#include "soc/i2c_ana_mst_reg.h" #include "soc/pmu_reg.h" #include "modem/modem_lpcon_struct.h" #include "modem/modem_syscon_struct.h" @@ -69,34 +68,6 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configur MODEM_SYSCON.clk_conf.clk_i2c_mst_sel_160m = 1; } -/** - * @brief Start BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) -{ - REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); - REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); -} - -/** - * @brief Stop BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) -{ - REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); - REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); -} - -/** - * @brief Check whether BBPLL calibration is done - * - * @return True if calibration is done; otherwise false - */ -static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) -{ - return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); -} - /** * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32h4.c b/components/esp_hal_regi2c/esp32h4/regi2c_impl.c similarity index 50% rename from components/esp_rom/patches/esp_rom_regi2c_esp32h4.c rename to components/esp_hal_regi2c/esp32h4/regi2c_impl.c index 288080994c..f95401556f 100644 --- a/components/esp_rom/patches/esp_rom_regi2c_esp32h4.c +++ b/components/esp_hal_regi2c/esp32h4/regi2c_impl.c @@ -1,13 +1,13 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "esp_rom_sys.h" -#include "esp_attr.h" -#include "soc/i2c_ana_mst_reg.h" +#include "hal/regi2c_impl.h" +#include "hal/assert.h" +#include "modem/i2c_ana_mst_reg.h" #include "hal/regi2c_ctrl_ll.h" -#include "sdkconfig.h" +#include "hal/config.h" /* SLAVE */ #define REGI2C_BBPLL (0x66) @@ -19,53 +19,48 @@ #define REGI2C_ULP (0x61) /* SLAVE END */ -uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl"))); -uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl"))); -void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); -void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); - -static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) +static uint8_t regi2c_enable_block(uint8_t block) { uint32_t i2c_sel = 0; -#if !CONFIG_IDF_ENV_FPGA // on FPGA, unable to manipulate modem registers, skip the check - assert(regi2c_ctrl_ll_master_is_clock_enabled()); +#if !HAL_CONFIG(ENV_FPGA) // on FPGA, unable to manipulate modem registers, skip the check + HAL_ASSERT(regi2c_ctrl_ll_master_is_clock_enabled()); #endif /* Before config I2C register, enable corresponding slave. */ switch (block) { - case REGI2C_BBPLL: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBPLL_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBPLL_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; - case REGI2C_BBTOP: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBTOP_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBTOP_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; - case REGI2C_DCDC: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_DCDC_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_DCDC_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; - case REGI2C_PERIF: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PERIF_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PERIF_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; - case REGI2C_PLL: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PLL_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PLL_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; - case REGI2C_SDM: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_SDM_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_SDM_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; - case REGI2C_ULP: - i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_ULP_SEL); - REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_ULP_SEL & I2C_ANA_MST_ANA_CONF1_M); - break; + case REGI2C_BBPLL: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBPLL_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBPLL_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_BBTOP: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBTOP_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBTOP_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_DCDC: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_DCDC_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_DCDC_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_PERIF: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PERIF_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PERIF_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_PLL: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PLL_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PLL_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_SDM: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_SDM_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_SDM_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; + case REGI2C_ULP: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_ULP_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_ULP_SEL & I2C_ANA_MST_ANA_CONF1_M); + break; } return (uint8_t)(i2c_sel ? 0 : 1); } -uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) +uint8_t _regi2c_impl_read(uint8_t block, uint8_t host_id, uint8_t reg_add) { (void)host_id; uint8_t i2c_sel = regi2c_enable_block(block); @@ -78,9 +73,9 @@ uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_a return ret; } -uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +uint8_t _regi2c_impl_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) { - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); uint8_t i2c_sel = regi2c_enable_block(block); (void)host_id; while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle @@ -93,7 +88,7 @@ uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t return ret; } -void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +void _regi2c_impl_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) { (void)host_id; uint8_t i2c_sel = regi2c_enable_block(block); @@ -106,10 +101,10 @@ void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); } -void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +void _regi2c_impl_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) { (void)host_id; - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); uint8_t i2c_sel = regi2c_enable_block(block); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); /*Read the i2c bus register*/ @@ -122,9 +117,9 @@ void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t re temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) - | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) - | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); } diff --git a/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32p4/include/hal/regi2c_ctrl_ll.h similarity index 57% rename from components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h rename to components/esp_hal_regi2c/esp32p4/include/hal/regi2c_ctrl_ll.h index 6d4f97b96a..d54d85165f 100644 --- a/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32p4/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,9 +9,8 @@ #include #include #include "soc/soc.h" -#include "soc/hp_sys_clkrst_reg.h" #include "soc/lpperi_struct.h" -#include "soc/i2c_ana_mst_struct.h" +#include "soc/lp_i2c_ana_mst_struct.h" #include "soc/pmu_reg.h" #ifdef __cplusplus @@ -62,59 +61,7 @@ static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(v */ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configure_clock(void) { - I2C_ANA_MST.clk160m.clk_i2c_mst_sel_160m = 1; -} - -/** - * @brief Start CPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_cpll_calibration_start(void) -{ - CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP); -} - -/** - * @brief Stop CPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_cpll_calibration_stop(void) -{ - SET_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP); -} - -/** - * @brief Check whether CPLL calibration is done - * - * @return True if calibration is done; otherwise false - */ -static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_cpll_calibration_is_done(void) -{ - return REG_GET_BIT(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_END); -} - -/** - * @brief Start MPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_mpll_calibration_start(void) -{ - CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_STOP); -} - -/** - * @brief Stop MPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_mpll_calibration_stop(void) -{ - SET_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_STOP); -} - -/** - * @brief Check whether MPLL calibration is done - * - * @return True if calibration is done; otherwise false - */ -static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_mpll_calibration_is_done(void) -{ - return REG_GET_BIT(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_END); + LP_I2C_ANA_MST.clk160m.clk_i2c_mst_sel_160m = 1; } /** diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c b/components/esp_hal_regi2c/esp32p4/regi2c_impl.c similarity index 69% rename from components/esp_rom/patches/esp_rom_regi2c_esp32p4.c rename to components/esp_hal_regi2c/esp32p4/regi2c_impl.c index 6175540bbb..85d2f57fa2 100644 --- a/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c +++ b/components/esp_hal_regi2c/esp32p4/regi2c_impl.c @@ -1,11 +1,11 @@ /* - * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "esp_rom_sys.h" -#include "esp_attr.h" -#include "soc/i2c_ana_mst_reg.h" +#include "hal/regi2c_impl.h" +#include "hal/assert.h" +#include "soc/lp_i2c_ana_mst_reg.h" #include "hal/regi2c_ctrl_ll.h" /** * DIG_REG - 0x6D - BIT10 @@ -27,7 +27,7 @@ #define REGI2C_PLLA_MST_SEL (BIT(8)) #define REGI2C_SAR_I2C_MST_SEL (BIT(7)) -#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG +#define I2C_ANA_MST_I2C_CTRL_REG(n) (LP_I2C_ANA_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG #define REGI2C_RTC_BUSY (BIT(25)) #define REGI2C_RTC_BUSY_M (BIT(25)) @@ -80,48 +80,43 @@ #define REGI2C_SAR_I2C_HOSTID 0 /* SLAVE END */ -uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl"))); -uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl"))); -void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); -void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); - -static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) +static uint8_t regi2c_enable_block(uint8_t block) { - assert(regi2c_ctrl_ll_master_is_clock_enabled()); - REG_SET_FIELD(I2C_ANA_MST_ANA_CONF2_REG, I2C_ANA_MST_ANA_CONF2, 0); - REG_SET_FIELD(I2C_ANA_MST_ANA_CONF1_REG, I2C_ANA_MST_ANA_CONF1, 0); + HAL_ASSERT(regi2c_ctrl_ll_master_is_clock_enabled()); + REG_SET_FIELD(LP_I2C_ANA_MST_ANA_CONF2_REG, LP_I2C_ANA_MST_ANA_CONF2, 0); + REG_SET_FIELD(LP_I2C_ANA_MST_ANA_CONF1_REG, LP_I2C_ANA_MST_ANA_CONF1, 0); switch (block) { case REGI2C_DIG_REG: - REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); + REG_SET_BIT(LP_I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); break; case REGI2C_CPU_PLL: - REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_CPU_MST_SEL); + REG_SET_BIT(LP_I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_CPU_MST_SEL); break; case REGI2C_SDIO_PLL: - REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_SDIO_MST_SEL); + REG_SET_BIT(LP_I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_SDIO_MST_SEL); break; case REGI2C_BIAS: - REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); + REG_SET_BIT(LP_I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); break; case REGI2C_MSPI: - REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_MSPI_XTAL_MST_SEL); + REG_SET_BIT(LP_I2C_ANA_MST_ANA_CONF2_REG, REGI2C_MSPI_XTAL_MST_SEL); break; case REGI2C_SYS_PLL: - REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_SYS_MST_SEL); + REG_SET_BIT(LP_I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_SYS_MST_SEL); break; case REGI2C_PLLA: - REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLLA_MST_SEL); + REG_SET_BIT(LP_I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLLA_MST_SEL); break; case REGI2C_SAR_I2C: - REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); + REG_SET_BIT(LP_I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); break; } return 0; } -uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) +uint8_t _regi2c_impl_read(uint8_t block, uint8_t host_id, uint8_t reg_add) { (void)host_id; uint8_t i2c_sel = regi2c_enable_block(block); @@ -136,9 +131,9 @@ uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_a return ret; } -uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +uint8_t _regi2c_impl_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) { - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); uint8_t i2c_sel = regi2c_enable_block(block); (void)host_id; @@ -153,7 +148,7 @@ uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t return ret; } -void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +void _regi2c_impl_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) { (void)host_id; uint8_t i2c_sel = regi2c_enable_block(block); @@ -168,10 +163,10 @@ void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add } -void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +void _regi2c_impl_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) { (void)host_id; - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); uint8_t i2c_sel = regi2c_enable_block(block); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); @@ -185,9 +180,9 @@ void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t re temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) - | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) - | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); } diff --git a/components/hal/esp32s2/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32s2/include/hal/regi2c_ctrl_ll.h similarity index 85% rename from components/hal/esp32s2/include/hal/regi2c_ctrl_ll.h rename to components/esp_hal_regi2c/esp32s2/include/hal/regi2c_ctrl_ll.h index 98404fdb4d..7a1df7cd88 100644 --- a/components/hal/esp32s2/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32s2/include/hal/regi2c_ctrl_ll.h @@ -14,13 +14,6 @@ extern "C" { #endif -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround for calibration error when waking up from light sleep - */ -#define REGI2C_LL_ANA_CALI_PD_WORKAROUND 1 -#define REGI2C_LL_ANA_CALI_BYTE_NUM 8 - /** * @brief Reset (Disable) the I2C internal bus for all regi2c registers */ diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32s2.c b/components/esp_hal_regi2c/esp32s2/regi2c_impl.c similarity index 84% rename from components/esp_rom/patches/esp_rom_regi2c_esp32s2.c rename to components/esp_hal_regi2c/esp32s2/regi2c_impl.c index 045c96dc09..4161a542e4 100644 --- a/components/esp_rom/patches/esp_rom_regi2c_esp32s2.c +++ b/components/esp_hal_regi2c/esp32s2/regi2c_impl.c @@ -1,15 +1,13 @@ /* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include +#include "hal/regi2c_impl.h" +#include "hal/assert.h" #include "esp_bit_defs.h" -#include "esp_rom_caps.h" -#include "esp_attr.h" -#include "sdkconfig.h" - #include "soc/syscon_reg.h" #define I2C_RTC_WIFI_CLK_EN (SYSCON_WIFI_CLK_EN_REG) @@ -87,7 +85,7 @@ #define I2C_SAR_ADC 0X69 #define I2C_APLL 0X6D -static IRAM_ATTR void i2c_rtc_enable_block(uint8_t block) +static void i2c_rtc_enable_block(uint8_t block) { REG_SET_FIELD(I2C_RTC_CONFIG0, I2C_RTC_MAGIC_CTRL, I2C_RTC_MAGIC_DEFAULT); REG_SET_FIELD(I2C_RTC_CONFIG1, I2C_RTC_ALL_MASK, I2C_RTC_ALL_MASK_V); @@ -108,7 +106,7 @@ static IRAM_ATTR void i2c_rtc_enable_block(uint8_t block) } } -uint8_t IRAM_ATTR esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) +uint8_t _regi2c_impl_read(uint8_t block, uint8_t host_id, uint8_t reg_add) { i2c_rtc_enable_block(block); @@ -119,9 +117,9 @@ uint8_t IRAM_ATTR esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t re return REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA); } -uint8_t IRAM_ATTR esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +uint8_t _regi2c_impl_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) { - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); i2c_rtc_enable_block(block); uint32_t temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S) @@ -132,7 +130,7 @@ uint8_t IRAM_ATTR esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8 return (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); } -void IRAM_ATTR esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +void _regi2c_impl_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) { i2c_rtc_enable_block(block); @@ -144,9 +142,9 @@ void IRAM_ATTR esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_ while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY)); } -void IRAM_ATTR esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +void _regi2c_impl_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) { - assert(msb - lsb < 8); + HAL_ASSERT(msb - lsb < 8); i2c_rtc_enable_block(block); /*Read the i2c bus register*/ @@ -159,9 +157,9 @@ void IRAM_ATTR esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S) - | ((reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S) - | ((0x1 & I2C_RTC_WR_CNTL_V) << I2C_RTC_WR_CNTL_S) - | ((temp & I2C_RTC_DATA_V) << I2C_RTC_DATA_S); + | ((reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S) + | ((0x1 & I2C_RTC_WR_CNTL_V) << I2C_RTC_WR_CNTL_S) + | ((temp & I2C_RTC_DATA_V) << I2C_RTC_DATA_S); REG_WRITE(I2C_RTC_CONFIG2, temp); while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY)); } diff --git a/components/hal/esp32s3/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32s3/include/hal/regi2c_ctrl_ll.h similarity index 50% rename from components/hal/esp32s3/include/hal/regi2c_ctrl_ll.h rename to components/esp_hal_regi2c/esp32s3/include/hal/regi2c_ctrl_ll.h index b5869c875f..6ba96a0f57 100644 --- a/components/hal/esp32s3/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32s3/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,13 +15,6 @@ extern "C" { #endif -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround for calibration error when waking up from light sleep - */ -#define REGI2C_LL_ANA_CALI_PD_WORKAROUND 1 -#define REGI2C_LL_ANA_CALI_BYTE_NUM 8 - /** * @brief Reset (Disable) the I2C internal bus for all regi2c registers */ @@ -55,35 +48,6 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) CLEAR_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M); } - -/** - * @brief Start BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) -{ - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); -} - -/** - * @brief Stop BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) -{ - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); -} - -/** - * @brief Check whether BBPLL calibration is done - * - * @return True if calibration is done; otherwise false - */ -static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) -{ - return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); -} - #ifdef __cplusplus } #endif diff --git a/components/esp_hal_regi2c/esp32s3/rom.regi2c.ld b/components/esp_hal_regi2c/esp32s3/rom.regi2c.ld new file mode 100644 index 0000000000..6a1ea9aea8 --- /dev/null +++ b/components/esp_hal_regi2c/esp32s3/rom.regi2c.ld @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +PROVIDE ( _regi2c_impl_read = 0x40005d48 ); +PROVIDE ( _regi2c_impl_read_mask = 0x40005d54 ); +PROVIDE ( _regi2c_impl_write = 0x40005d60 ); +PROVIDE ( _regi2c_impl_write_mask = 0x40005d6c ); diff --git a/components/hal/esp32s31/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32s31/include/hal/regi2c_ctrl_ll.h similarity index 52% rename from components/hal/esp32s31/include/hal/regi2c_ctrl_ll.h rename to components/esp_hal_regi2c/esp32s31/include/hal/regi2c_ctrl_ll.h index 283f8b504f..fcf709b17d 100644 --- a/components/hal/esp32s31/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32s31/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,6 @@ #include #include #include "soc/soc.h" -#include "soc/hp_sys_clkrst_reg.h" #include "soc/pmu_reg.h" #ifdef __cplusplus @@ -54,58 +53,6 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configur // TODO: [ESP32S31] IDF-14680 } -/** - * @brief Start CPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_cpll_calibration_start(void) -{ - CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP); -} - -/** - * @brief Stop CPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_cpll_calibration_stop(void) -{ - SET_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP); -} - -/** - * @brief Check whether CPLL calibration is done - * - * @return True if calibration is done; otherwise false - */ -static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_cpll_calibration_is_done(void) -{ - return REG_GET_BIT(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_END); -} - -/** - * @brief Start MPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_mpll_calibration_start(void) -{ - CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_STOP); -} - -/** - * @brief Stop MPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_mpll_calibration_stop(void) -{ - SET_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_STOP); -} - -/** - * @brief Check whether MPLL calibration is done - * - * @return True if calibration is done; otherwise false - */ -static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_mpll_calibration_is_done(void) -{ - return REG_GET_BIT(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_END); -} - /** * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ diff --git a/components/esp_hal_regi2c/esp32s31/regi2c_impl.c b/components/esp_hal_regi2c/esp32s31/regi2c_impl.c new file mode 100644 index 0000000000..96083b92a6 --- /dev/null +++ b/components/esp_hal_regi2c/esp32s31/regi2c_impl.c @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "hal/regi2c_impl.h" +#include "hal/assert.h" + +uint8_t _regi2c_impl_read(uint8_t block, uint8_t host_id, uint8_t reg_add) +{ + // TODO: [ESP32S31] IDF-14680 + return 0; +} + +uint8_t _regi2c_impl_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +{ + // TODO: [ESP32S31] IDF-14680 + return 0; +} + +void _regi2c_impl_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +{ + // TODO: [ESP32S31] IDF-14680 +} + +void _regi2c_impl_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +{ + // TODO: [ESP32S31] IDF-14680 +} diff --git a/components/esp_hal_regi2c/include/hal/regi2c_ctrl.h b/components/esp_hal_regi2c/include/hal/regi2c_ctrl.h new file mode 100644 index 0000000000..d7849e715e --- /dev/null +++ b/components/esp_hal_regi2c/include/hal/regi2c_ctrl.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +/** + * When compiling G0-layer only, we can't depend on `esp_hw_support` component. + * However, `esp_private/regi2c_ctrl.h` is part of that component. + * Thus, if we don't have this header file in our compilation unit, we should use + * ROM functions. + * The main difference is that `regi2c_ctrl.h` implementation protects the functions + * with mutex. ROM functions must be protected explicitly by the user. + */ +#if __has_include("esp_private/regi2c_ctrl.h") +#include "esp_private/regi2c_ctrl.h" +#else +#include "hal/regi2c_impl.h" + +#define REGI2C_WRITE_MASK(block, reg_add, indata) do { \ + int __DECLARE_REGI2C_ATOMIC_ENV __attribute__((unused)); \ + regi2c_impl_write_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata); \ + } while(0) + +#define REGI2C_WRITE(block, reg_add, indata) do { \ + int __DECLARE_REGI2C_ATOMIC_ENV __attribute__((unused)); \ + regi2c_impl_write(block, block##_HOSTID, reg_add, indata); \ + } while(0) + +#define REGI2C_READ_MASK(block, reg_add) ({ \ + int __DECLARE_REGI2C_ATOMIC_ENV __attribute__((unused)); \ + regi2c_impl_read_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB); \ + }) + +#define REGI2C_READ(block, reg_add) ({ \ + int __DECLARE_REGI2C_ATOMIC_ENV __attribute__((unused)); \ + regi2c_impl_read(block, block##_HOSTID, reg_add); \ + }) + +#define REGI2C_ENTER_CRITICAL() int __DECLARE_REGI2C_ATOMIC_ENV __attribute__((unused)); +#define REGI2C_EXIT_CRITICAL() + +#define REGI2C_CLOCK_ENABLE() +#define REGI2C_CLOCK_DISABLE() +#endif diff --git a/components/esp_hal_regi2c/include/hal/regi2c_impl.h b/components/esp_hal_regi2c/include/hal/regi2c_impl.h new file mode 100644 index 0000000000..9d080ad146 --- /dev/null +++ b/components/esp_hal_regi2c/include/hal/regi2c_impl.h @@ -0,0 +1,92 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_rom_caps.h" +#include "esp_rom_regi2c.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief REGI2C implementation layer + * + * If CONFIG_ESP_ROM_HAS_REGI2C_IMPL is not set, + * the IDF provides its own implementation of the regi2c functions. + * Otherwise, the ROM implementation is used directly. + * + * @note The APIs provided by this layer does not consider either clock gating to analog i2c master clock or atomicity of the operations. + * Upper layer (esp_private/regi2c_ctrl.h) provides APIs that considered both, and is recommended to use. + * If you are using the interfaces in this layer directly (when you want to group multiple regi2c operations together), please make sure to enable the clock gating and atomicity by yourself. + */ + +/** + * @brief Read internal register + */ +uint8_t _regi2c_impl_read(uint8_t block, uint8_t host_id, uint8_t reg_add); + +/** + * @brief Read internal register with mask + */ +uint8_t _regi2c_impl_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb); + +/** + * @brief Write internal register + */ +void _regi2c_impl_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data); + +/** + * @brief Write internal register with mask + */ +void _regi2c_impl_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data); + +#if NON_OS_BUILD + +/* If compiling for the non-FreeRTOS builds (e.g. bootloader), REGI2C read/write operations are always atomic */ +#define regi2c_impl_read(...) _regi2c_impl_read(__VA_ARGS__) +#define regi2c_impl_read_mask(...) _regi2c_impl_read_mask(__VA_ARGS__) +#define regi2c_impl_write(...) _regi2c_impl_write(__VA_ARGS__) +#define regi2c_impl_write_mask(...) _regi2c_impl_write_mask(__VA_ARGS__) + +#else // !NON_OS_BUILD + +/* REGI2C read/write needs to be atomic, so any regi2c operation needs to be wrapped within a lock, this is implemented in esp_private/regi2c_ctrl.h */ +#define regi2c_impl_read(...) ({ \ + (void)__DECLARE_REGI2C_ATOMIC_ENV; \ + int _temp; \ + do { \ + _temp = _regi2c_impl_read(__VA_ARGS__); \ + } while(0); \ + _temp; \ +}) + +#define regi2c_impl_read_mask(...) ({ \ + (void)__DECLARE_REGI2C_ATOMIC_ENV; \ + int _temp; \ + do { \ + _temp = _regi2c_impl_read_mask(__VA_ARGS__); \ + } while(0); \ + _temp; \ +}) + +#define regi2c_impl_write(...) do { \ + (void)__DECLARE_REGI2C_ATOMIC_ENV; \ + _regi2c_impl_write(__VA_ARGS__); \ + } while(0) + +#define regi2c_impl_write_mask(...) do { \ + (void)__DECLARE_REGI2C_ATOMIC_ENV; \ + _regi2c_impl_write_mask(__VA_ARGS__); \ + } while(0) + +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_regi2c/linker.lf b/components/esp_hal_regi2c/linker.lf new file mode 100644 index 0000000000..7e59e96b31 --- /dev/null +++ b/components/esp_hal_regi2c/linker.lf @@ -0,0 +1,5 @@ +[mapping:esp_hal_regi2c] +archive: libesp_hal_regi2c.a +entries: + if ESP_REGI2C_CTRL_FUNC_IN_IRAM = y: + * (noflash) diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 7a012e520f..281cfedbd5 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -9,10 +9,17 @@ if(${target} STREQUAL "linux") return() endif() -set(requires esp_hal_gpio esp_hal_usb esp_hal_pmu) -# only esp_hw_support/adc_share_hw_ctrl.c requires efuse component -set(priv_requires efuse spi_flash bootloader_support esp_hal_wdt esp_hal_rtc_timer - esp_hal_clock esp_hal_security esp_hal_systimer) +set(requires esp_hal_gpio esp_hal_usb esp_hal_pmu esp_hal_regi2c) +set(priv_requires efuse # only esp_hw_support/adc_share_hw_ctrl.c requires efuse component + spi_flash + bootloader_support + esp_hal_wdt + esp_hal_rtc_timer + esp_hal_clock + esp_hal_security + esp_hal_systimer + esp_hal_ana_conv # sleep process requires backup/restore some ADC, TSENS registers + ) set(srcs "cpu.c" "port/${IDF_TARGET}/esp_cpu_intr.c" "esp_memory_utils.c" "port/${IDF_TARGET}/cpu_region_protect.c") if(NOT non_os_build) @@ -27,6 +34,7 @@ if(NOT non_os_build) "regi2c_ctrl.c" "esp_gpio_reserve.c" "sar_tsens_ctrl.c" + "sar_periph_ctrl_common.c" "port/${target}/io_mux.c" "port/${target}/esp_clk_tree.c" "spi_bus_lock.c" diff --git a/components/esp_hw_support/include/esp_private/regi2c_ctrl.h b/components/esp_hw_support/include/esp_private/regi2c_ctrl.h index ad7458501b..2275364594 100644 --- a/components/esp_hw_support/include/esp_private/regi2c_ctrl.h +++ b/components/esp_hw_support/include/esp_private/regi2c_ctrl.h @@ -9,7 +9,7 @@ #include #include #include "sdkconfig.h" -#include "esp_rom_regi2c.h" +#include "hal/regi2c_impl.h" #include "soc/soc_caps.h" #include "esp_private/periph_ctrl.h" #include "hal/regi2c_ctrl_ll.h" @@ -72,36 +72,35 @@ static inline __attribute__((always_inline)) void ANA_I2C_SRC_CLOCK_ENABLE(bool #define REGI2C_CLOCK_DISABLE() ANALOG_CLOCK_DISABLE() -#define regi2c_read_reg_raw esp_rom_regi2c_read -#define regi2c_read_reg_mask_raw esp_rom_regi2c_read_mask -#define regi2c_write_reg_raw esp_rom_regi2c_write -#define regi2c_write_reg_mask_raw esp_rom_regi2c_write_mask - - #if NON_OS_BUILD /** - * If compiling for the non-FreeRTOS builds (e.g. bootloader), ROM functions can be called directly, + * If compiling for the non-FreeRTOS builds (e.g. bootloader), regi2c_impl functions can be called directly, * without the need of a lock. */ -#define regi2c_ctrl_read_reg regi2c_read_reg_raw -#define regi2c_ctrl_read_reg_mask regi2c_read_reg_mask_raw -#define regi2c_ctrl_write_reg regi2c_write_reg_raw -#define regi2c_ctrl_write_reg_mask regi2c_write_reg_mask_raw +#define regi2c_ctrl_read_reg regi2c_impl_read +#define regi2c_ctrl_read_reg_mask regi2c_impl_read_mask +#define regi2c_ctrl_write_reg regi2c_impl_write +#define regi2c_ctrl_write_reg_mask regi2c_impl_write_mask #define REGI2C_ENTER_CRITICAL() #define REGI2C_EXIT_CRITICAL() #else -/* Access internal registers, don't use in application */ +/* Access regi2c registers, don't use in application + * The following four functions have considered the atomicity of the operations and the clock gating enable/disable for + * the analog i2c master clock. + */ uint8_t regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add); uint8_t regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb); void regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data); void regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data); -/* enter the critical section that protects internal registers. Don't use it in SDK. Use the functions above. */ +/* Enter the critical section that protects regi2c operations. + * Use it if multiple regi2c operations are called in a row, a lock wrapped outside saves lock acquire/release time. + */ void regi2c_enter_critical(void); void regi2c_exit_critical(void); -#define REGI2C_ENTER_CRITICAL() regi2c_enter_critical() +#define REGI2C_ENTER_CRITICAL() int __DECLARE_REGI2C_ATOMIC_ENV __attribute__((unused)); regi2c_enter_critical() #define REGI2C_EXIT_CRITICAL() regi2c_exit_critical() #endif // NON_OS_BUILD @@ -120,29 +119,6 @@ void regi2c_exit_critical(void); #define REGI2C_READ(block, reg_add) \ regi2c_ctrl_read_reg(block, block##_HOSTID, reg_add) -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround, and is fixed on later chips - */ -#if REGI2C_LL_ANA_CALI_PD_WORKAROUND -void regi2c_analog_cali_reg_read(void); -void regi2c_analog_cali_reg_write(void); -#endif //#if ADC_CALI_PD_WORKAROUND - -#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION -// regi2c would be powered down in light sleep, but measure range is recorded -// in regi2c, so this function is used for record. -void regi2c_tsens_reg_read(void); -void regi2c_tsens_reg_write(void); -#endif - -/* Enable/Disable regi2c_saradc with calling these two functions. - With reference count protection inside. - Internal use only. -*/ -void regi2c_saradc_enable(void); -void regi2c_saradc_disable(void); - #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/include/esp_private/sar_periph_ctrl.h b/components/esp_hw_support/include/esp_private/sar_periph_ctrl.h index f4a7b7bb22..97342fb49d 100644 --- a/components/esp_hw_support/include/esp_private/sar_periph_ctrl.h +++ b/components/esp_hw_support/include/esp_private/sar_periph_ctrl.h @@ -123,6 +123,19 @@ void adc_reset_lock_release(void); */ void sar_periph_ctrl_adc_reset(void); +/*------------------------------------------------------------------------------ +* I2C SAR ADC +*----------------------------------------------------------------------------*/ + +/** + * @brief Enable I2C SAR ADC + */ +void regi2c_saradc_enable(void); + +/** + * @brief Disable I2C SAR ADC + */ +void regi2c_saradc_disable(void); #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index bc36135cc9..528205e275 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -71,12 +71,7 @@ entries: periph_ctrl: wifi_module_enable (noflash) periph_ctrl: wifi_module_disable (noflash) if ESP_REGI2C_CTRL_FUNC_IN_IRAM = y: - regi2c_ctrl:regi2c_ctrl_read_reg (noflash) - regi2c_ctrl:regi2c_ctrl_read_reg_mask (noflash) - regi2c_ctrl:regi2c_ctrl_write_reg (noflash) - regi2c_ctrl:regi2c_ctrl_write_reg_mask (noflash) - regi2c_ctrl:regi2c_enter_critical (noflash) - regi2c_ctrl:regi2c_exit_critical (noflash) + regi2c_ctrl (noflash) if SOC_SYSTIMER_SUPPORTED = y: systimer (noflash) if SOC_ADC_SHARED_POWER = y: @@ -106,3 +101,7 @@ archive: libesp_hal_ana_conv.a entries: if PM_SLP_IRAM_OPT = y && SOC_TEMP_SENSOR_SUPPORTED = y: temperature_sensor_periph:temperature_sensor_attributes (noflash) + if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION = y: + temperature_sensor_hal: dac_offset_regi2c (noflash) + temperature_sensor_hal: temperature_sensor_hal_i2c_saradc_reg_backup (noflash) + temperature_sensor_hal: temperature_sensor_hal_i2c_saradc_reg_restore (noflash) diff --git a/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c index 0b1a1fba57..57385b849d 100644 --- a/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c @@ -11,7 +11,7 @@ #include "soc/rtc.h" #include "modem/modem_syscon_reg.h" #include "modem/modem_lpcon_reg.h" -#include "soc/i2c_ana_mst_reg.h" +#include "modem/i2c_ana_mst_reg.h" #include "soc/chip_revision.h" #include "hal/efuse_hal.h" diff --git a/components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c b/components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c index b161ed38fa..81d607ab9a 100644 --- a/components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c +++ b/components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c @@ -8,9 +8,9 @@ #include "esp_attr.h" #include "soc/soc_caps.h" -#include "soc/i2c_ana_mst_reg.h" #include "soc/pmu_reg.h" +#include "modem/i2c_ana_mst_reg.h" #include "modem/modem_syscon_reg.h" #include "modem/modem_lpcon_reg.h" diff --git a/components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c index 809092647d..f6b72e5bff 100644 --- a/components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c @@ -7,7 +7,7 @@ #include "esp_private/sleep_clock.h" #include "soc/pcr_reg.h" #include "soc/pmu_reg.h" -#include "soc/i2c_ana_mst_reg.h" +#include "modem/i2c_ana_mst_reg.h" #include "modem/modem_lpcon_reg.h" #include "modem/modem_syscon_reg.h" diff --git a/components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c b/components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c index 3d12d1f080..d217cc6457 100644 --- a/components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c +++ b/components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c @@ -6,9 +6,9 @@ #include "esp_attr.h" #include "soc/soc_caps.h" -#include "soc/i2c_ana_mst_reg.h" #include "soc/pmu_reg.h" +#include "modem/i2c_ana_mst_reg.h" #include "modem/modem_syscon_reg.h" #include "modem/modem_lpcon_reg.h" diff --git a/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c index aa99bf8b89..aede05755e 100644 --- a/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c @@ -8,7 +8,7 @@ #include "soc/lp_analog_peri_reg.h" #include "soc/pcr_reg.h" #include "soc/pmu_reg.h" -#include "soc/i2c_ana_mst_reg.h" +#include "modem/i2c_ana_mst_reg.h" #include "modem/modem_lpcon_reg.h" #include "modem/modem_syscon_reg.h" diff --git a/components/esp_hw_support/lowpower/port/esp32c61/sleep_modem_state.c b/components/esp_hw_support/lowpower/port/esp32c61/sleep_modem_state.c index 55dfa60f14..46107d416c 100644 --- a/components/esp_hw_support/lowpower/port/esp32c61/sleep_modem_state.c +++ b/components/esp_hw_support/lowpower/port/esp32c61/sleep_modem_state.c @@ -6,9 +6,9 @@ #include "esp_attr.h" #include "soc/soc_caps.h" -#include "soc/i2c_ana_mst_reg.h" #include "soc/pmu_reg.h" +#include "modem/i2c_ana_mst_reg.h" #include "modem/modem_syscon_reg.h" #include "modem/modem_lpcon_reg.h" diff --git a/components/esp_hw_support/lowpower/port/esp32h2/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32h2/sleep_clock.c index 9d57f16ba7..c9a0f8dfb8 100644 --- a/components/esp_hw_support/lowpower/port/esp32h2/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32h2/sleep_clock.c @@ -5,8 +5,8 @@ */ #include "esp_private/sleep_clock.h" -#include "soc/i2c_ana_mst_reg.h" #include "soc/pcr_reg.h" +#include "modem/i2c_ana_mst_reg.h" #include "modem/modem_syscon_reg.h" #include "modem/modem_lpcon_reg.h" diff --git a/components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c index c1971a9728..71af05bc32 100644 --- a/components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c @@ -5,8 +5,8 @@ */ #include "esp_private/sleep_clock.h" -#include "soc/i2c_ana_mst_reg.h" #include "soc/pcr_reg.h" +#include "modem/i2c_ana_mst_reg.h" #include "modem/modem_syscon_reg.h" #include "modem/modem_lpcon_reg.h" diff --git a/components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c index 2ec104f269..c21c2cb332 100644 --- a/components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c @@ -8,7 +8,7 @@ #include "soc/pcr_reg.h" #include "modem/modem_syscon_reg.h" #include "modem/modem_lpcon_reg.h" -#include "soc/i2c_ana_mst_reg.h" +#include "modem/i2c_ana_mst_reg.h" #include "soc/pmu_reg.h" #include "soc/lp_analog_peri_reg.h" diff --git a/components/esp_hw_support/mspi/mspi_timing_tuning/port/esp32s3/mspi_timing_by_mspi_delay.c b/components/esp_hw_support/mspi/mspi_timing_tuning/port/esp32s3/mspi_timing_by_mspi_delay.c index 5429bef029..08a32b6cfe 100644 --- a/components/esp_hw_support/mspi/mspi_timing_tuning/port/esp32s3/mspi_timing_by_mspi_delay.c +++ b/components/esp_hw_support/mspi/mspi_timing_tuning/port/esp32s3/mspi_timing_by_mspi_delay.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,7 +21,6 @@ #include "soc/rtc.h" #include "hal/mspi_ll.h" #include "hal/clk_tree_ll.h" -#include "hal/regi2c_ctrl_ll.h" #include "esp_private/mspi_timing_config.h" #include "esp_private/mspi_timing_by_mspi_delay.h" #include "bootloader_flash.h" @@ -364,7 +363,7 @@ static bool get_working_pll_freq(const uint8_t *reference_data, bool is_flash, u for (int pll_mhz_tuning = MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MIN; pll_mhz_tuning <= MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MAX; pll_mhz_tuning += 8) { //bbpll calibration start - regi2c_ctrl_ll_bbpll_calibration_start(); + clk_ll_bbpll_calibration_start(); /** * pll_mhz = xtal_mhz * (oc_div + 4) / (oc_ref_div + 1) @@ -372,10 +371,10 @@ static bool get_working_pll_freq(const uint8_t *reference_data, bool is_flash, u clk_ll_bbpll_set_frequency_for_mspi_tuning(xtal_freq, pll_mhz_tuning, ((pll_mhz_tuning / 4) - 4), 9); //wait calibration done - while(!regi2c_ctrl_ll_bbpll_calibration_is_done()); + while(!clk_ll_bbpll_calibration_is_done()); //bbpll calibration stop - regi2c_ctrl_ll_bbpll_calibration_stop(); + clk_ll_bbpll_calibration_stop(); memset(read_data, 0, MSPI_TIMING_TEST_DATA_LEN); if (is_flash) { @@ -403,13 +402,13 @@ static bool get_working_pll_freq(const uint8_t *reference_data, bool is_flash, u //restore PLL config clk_ll_bbpll_set_freq_mhz(previous_config.source_freq_mhz); //bbpll calibration start - regi2c_ctrl_ll_bbpll_calibration_start(); + clk_ll_bbpll_calibration_start(); //set pll clk_ll_bbpll_set_config(previous_config.source_freq_mhz, xtal_freq); //wait calibration done - while(!regi2c_ctrl_ll_bbpll_calibration_is_done()); + while(!clk_ll_bbpll_calibration_is_done()); //bbpll calibration stop - regi2c_ctrl_ll_bbpll_calibration_stop(); + clk_ll_bbpll_calibration_stop(); *out_max_freq = max_freq; *out_min_freq = min_freq; diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk.c b/components/esp_hw_support/port/esp32c2/rtc_clk.c index eb2f85f788..976cd22634 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c2/rtc_clk.c @@ -20,7 +20,6 @@ #include "esp_hw_log.h" #include "esp_rom_sys.h" #include "hal/clk_tree_ll.h" -#include "hal/regi2c_ctrl_ll.h" #include "esp_attr.h" ESP_HW_LOG_ATTR_TAG(TAG, "rtc_clk"); @@ -138,13 +137,13 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) /* Digital part */ clk_ll_bbpll_set_freq_mhz(pll_freq); /* Analog part */ - regi2c_ctrl_ll_bbpll_calibration_start(); + clk_ll_bbpll_calibration_start(); clk_ll_bbpll_set_config(pll_freq, xtal_freq); /* WAIT CALIBRATION DONE */ - while(!regi2c_ctrl_ll_bbpll_calibration_is_done()); + while(!clk_ll_bbpll_calibration_is_done()); esp_rom_delay_us(10); /* BBPLL CALIBRATION STOP */ - regi2c_ctrl_ll_bbpll_calibration_stop(); + clk_ll_bbpll_calibration_stop(); s_cur_pll_freq = pll_freq; } diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk.c b/components/esp_hw_support/port/esp32c3/rtc_clk.c index 775971eb76..86cb39f29d 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c3/rtc_clk.c @@ -18,7 +18,6 @@ #include "esp_hw_log.h" #include "esp_rom_sys.h" #include "hal/clk_tree_ll.h" -#include "hal/regi2c_ctrl_ll.h" #include "esp_attr.h" ESP_HW_LOG_ATTR_TAG(TAG, "rtc_clk"); @@ -172,7 +171,7 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) /* Digital part */ clk_ll_bbpll_set_freq_mhz(pll_freq); /* Analog part */ - regi2c_ctrl_ll_bbpll_calibration_start(); + clk_ll_bbpll_calibration_start(); clk_ll_bbpll_set_config(pll_freq, xtal_freq); s_cur_pll_freq = pll_freq; diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c index efa96d66f2..59780b67d2 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk.c @@ -17,13 +17,11 @@ #include "esp_rom_sys.h" #include "esp_sleep.h" #include "hal/clk_tree_ll.h" -#include "hal/regi2c_ctrl_ll.h" #include "hal/gpio_ll.h" #include "soc/lp_aon_reg.h" #include "esp_private/sleep_event.h" #include "hal/efuse_hal.h" #include "soc/chip_revision.h" -#include "esp_private/regi2c_ctrl.h" #include "esp_attr.h" #include "esp_private/esp_pmu.h" @@ -154,13 +152,13 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) /* Analog part */ ANALOG_CLOCK_ENABLE(); /* BBPLL CALIBRATION START */ - regi2c_ctrl_ll_bbpll_calibration_start(); + clk_ll_bbpll_calibration_start(); clk_ll_bbpll_set_config(pll_freq, xtal_freq); /* WAIT CALIBRATION DONE */ - while(!regi2c_ctrl_ll_bbpll_calibration_is_done()); + while(!clk_ll_bbpll_calibration_is_done()); esp_rom_delay_us(10); // wait for true stop /* BBPLL CALIBRATION STOP */ - regi2c_ctrl_ll_bbpll_calibration_stop(); + clk_ll_bbpll_calibration_stop(); ANALOG_CLOCK_DISABLE(); s_cur_pll_freq = pll_freq; diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c index 889b041c9d..d16500c562 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c @@ -17,11 +17,9 @@ #include "esp_rom_sys.h" #include "esp_sleep.h" #include "hal/clk_tree_ll.h" -#include "hal/regi2c_ctrl_ll.h" #include "hal/gpio_ll.h" #include "soc/lp_aon_reg.h" #include "esp_private/sleep_event.h" -#include "esp_private/regi2c_ctrl.h" #include "esp_attr.h" ESP_HW_LOG_ATTR_TAG(TAG, "rtc_clk"); @@ -167,13 +165,13 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) /* Analog part */ ANALOG_CLOCK_ENABLE(); /* BBPLL CALIBRATION START */ - regi2c_ctrl_ll_bbpll_calibration_start(); + clk_ll_bbpll_calibration_start(); clk_ll_bbpll_set_config(pll_freq, xtal_freq); /* WAIT CALIBRATION DONE */ - while(!regi2c_ctrl_ll_bbpll_calibration_is_done()); + while(!clk_ll_bbpll_calibration_is_done()); esp_rom_delay_us(10); /* BBPLL CALIBRATION STOP */ - regi2c_ctrl_ll_bbpll_calibration_stop(); + clk_ll_bbpll_calibration_stop(); ANALOG_CLOCK_DISABLE(); s_cur_pll_freq = pll_freq; diff --git a/components/esp_hw_support/port/esp32c61/rtc_clk.c b/components/esp_hw_support/port/esp32c61/rtc_clk.c index be2389c638..1af70a96f2 100644 --- a/components/esp_hw_support/port/esp32c61/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c61/rtc_clk.c @@ -17,11 +17,9 @@ #include "esp_rom_sys.h" #include "esp_sleep.h" #include "hal/clk_tree_ll.h" -#include "hal/regi2c_ctrl_ll.h" #include "hal/gpio_ll.h" #include "soc/lp_aon_reg.h" #include "esp_private/sleep_event.h" -#include "esp_private/regi2c_ctrl.h" #include "esp_attr.h" #include "esp_private/esp_pmu.h" @@ -152,13 +150,13 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) /* Analog part */ ANALOG_CLOCK_ENABLE(); /* BBPLL CALIBRATION START */ - regi2c_ctrl_ll_bbpll_calibration_start(); + clk_ll_bbpll_calibration_start(); clk_ll_bbpll_set_config(pll_freq, xtal_freq); /* WAIT CALIBRATION DONE */ - while(!regi2c_ctrl_ll_bbpll_calibration_is_done()); + while(!clk_ll_bbpll_calibration_is_done()); esp_rom_delay_us(10); // wait for true stop /* BBPLL CALIBRATION STOP */ - regi2c_ctrl_ll_bbpll_calibration_stop(); + clk_ll_bbpll_calibration_stop(); ANALOG_CLOCK_DISABLE(); s_cur_pll_freq = pll_freq; diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk.c b/components/esp_hw_support/port/esp32h2/rtc_clk.c index e0614801e4..c9498fce35 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32h2/rtc_clk.c @@ -17,11 +17,9 @@ #include "esp_rom_sys.h" #include "esp_sleep.h" #include "hal/clk_tree_ll.h" -#include "hal/regi2c_ctrl_ll.h" #include "hal/gpio_ll.h" #include "soc/lp_aon_reg.h" #include "esp_private/sleep_event.h" -#include "esp_private/regi2c_ctrl.h" #include "esp_attr.h" ESP_HW_LOG_ATTR_TAG(TAG, "rtc_clk"); @@ -178,13 +176,13 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) /* Analog part */ ANALOG_CLOCK_ENABLE(); /* BBPLL CALIBRATION START */ - regi2c_ctrl_ll_bbpll_calibration_start(); + clk_ll_bbpll_calibration_start(); clk_ll_bbpll_set_config(pll_freq, xtal_freq); /* WAIT CALIBRATION DONE */ - while(!regi2c_ctrl_ll_bbpll_calibration_is_done()); + while(!clk_ll_bbpll_calibration_is_done()); esp_rom_delay_us(10); /* BBPLL CALIBRATION STOP */ - regi2c_ctrl_ll_bbpll_calibration_stop(); + clk_ll_bbpll_calibration_stop(); ANALOG_CLOCK_DISABLE(); s_cur_pll_freq = pll_freq; diff --git a/components/esp_hw_support/port/esp32h21/rtc_clk.c b/components/esp_hw_support/port/esp32h21/rtc_clk.c index 97e690dddd..d9c7d9ea0a 100644 --- a/components/esp_hw_support/port/esp32h21/rtc_clk.c +++ b/components/esp_hw_support/port/esp32h21/rtc_clk.c @@ -17,11 +17,9 @@ #include "esp_rom_sys.h" #include "esp_sleep.h" #include "hal/clk_tree_ll.h" -#include "hal/regi2c_ctrl_ll.h" #include "hal/gpio_ll.h" #include "soc/lp_aon_reg.h" #include "esp_private/sleep_event.h" -#include "esp_private/regi2c_ctrl.h" #include "esp_private/esp_clk_tree_common.h" #include "esp_attr.h" @@ -152,13 +150,13 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) /* Analog part */ ANALOG_CLOCK_ENABLE(); /* BBPLL CALIBRATION START */ - regi2c_ctrl_ll_bbpll_calibration_start(); + clk_ll_bbpll_calibration_start(); clk_ll_bbpll_set_config(pll_freq, xtal_freq); /* WAIT CALIBRATION DONE */ - while(!regi2c_ctrl_ll_bbpll_calibration_is_done()); + while(!clk_ll_bbpll_calibration_is_done()); esp_rom_delay_us(10); // wait for true stop /* BBPLL CALIBRATION STOP */ - regi2c_ctrl_ll_bbpll_calibration_stop(); + clk_ll_bbpll_calibration_stop(); ANALOG_CLOCK_DISABLE(); s_cur_pll_freq = pll_freq; diff --git a/components/esp_hw_support/port/esp32h4/rtc_clk.c b/components/esp_hw_support/port/esp32h4/rtc_clk.c index b410dbd5d7..cac9fe1cfd 100644 --- a/components/esp_hw_support/port/esp32h4/rtc_clk.c +++ b/components/esp_hw_support/port/esp32h4/rtc_clk.c @@ -18,7 +18,6 @@ #include "esp_sleep.h" #include "hal/clk_tree_ll.h" #include "hal/gpio_ll.h" -#include "hal/regi2c_ctrl_ll.h" #include "soc/lp_aon_reg.h" #include "esp_private/sleep_event.h" #include "esp_private/esp_clk_tree_common.h" @@ -153,13 +152,13 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) /* Analog part */ ANALOG_CLOCK_ENABLE(); /* BBPLL CALIBRATION START */ - regi2c_ctrl_ll_bbpll_calibration_start(); + clk_ll_bbpll_calibration_start(); clk_ll_bbpll_set_config(pll_freq, xtal_freq); /* WAIT CALIBRATION DONE */ - while (!regi2c_ctrl_ll_bbpll_calibration_is_done()); + while (!clk_ll_bbpll_calibration_is_done()); esp_rom_delay_us(10); // wait for true stop /* BBPLL CALIBRATION STOP */ - regi2c_ctrl_ll_bbpll_calibration_stop(); + clk_ll_bbpll_calibration_stop(); ANALOG_CLOCK_DISABLE(); s_cur_pll_freq = pll_freq; diff --git a/components/esp_hw_support/port/esp32p4/pmu_pvt.c b/components/esp_hw_support/port/esp32p4/pmu_pvt.c index ccc5d2de2b..60301abc30 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_pvt.c +++ b/components/esp_hw_support/port/esp32p4/pmu_pvt.c @@ -13,6 +13,7 @@ #include "soc/pmu_struct.h" #include "soc/pvt_reg.h" #include "soc/pmu_reg.h" +#include "soc/hp_sys_clkrst_reg.h" #include "hal/pmu_hal.h" #include "pmu_param.h" #include "esp_rom_sys.h" diff --git a/components/esp_hw_support/port/esp32p4/rtc_clk.c b/components/esp_hw_support/port/esp32p4/rtc_clk.c index 1f7dd0ca60..38ca18646c 100644 --- a/components/esp_hw_support/port/esp32p4/rtc_clk.c +++ b/components/esp_hw_support/port/esp32p4/rtc_clk.c @@ -22,7 +22,6 @@ #include "hal/gpio_ll.h" #include "soc/io_mux_reg.h" #include "esp_private/sleep_event.h" -#include "esp_private/regi2c_ctrl.h" #include "esp_attr.h" ESP_HW_LOG_ATTR_TAG(TAG, "rtc_clk"); @@ -160,13 +159,13 @@ static void rtc_clk_cpll_configure(soc_xtal_freq_t xtal_freq, int cpll_freq) /* Analog part */ ANALOG_CLOCK_ENABLE(); /* CPLL CALIBRATION START */ - regi2c_ctrl_ll_cpll_calibration_start(); + clk_ll_cpll_calibration_start(); clk_ll_cpll_set_config(cpll_freq, xtal_freq); /* WAIT CALIBRATION DONE */ - while(!regi2c_ctrl_ll_cpll_calibration_is_done()); + while(!clk_ll_cpll_calibration_is_done()); esp_rom_delay_us(10); // wait for true stop /* CPLL CALIBRATION STOP */ - regi2c_ctrl_ll_cpll_calibration_stop(); + clk_ll_cpll_calibration_stop(); ANALOG_CLOCK_DISABLE(); s_cur_cpll_freq = cpll_freq; @@ -663,12 +662,12 @@ void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq, bool thread_ ANALOG_CLOCK_ENABLE(); } /* MPLL calibration start */ - regi2c_ctrl_ll_mpll_calibration_start(); + clk_ll_mpll_calibration_start(); clk_ll_mpll_set_config(mpll_freq, xtal_freq); /* wait calibration done */ - while(!regi2c_ctrl_ll_mpll_calibration_is_done()); + while(!clk_ll_mpll_calibration_is_done()); /* MPLL calibration stop */ - regi2c_ctrl_ll_mpll_calibration_stop(); + clk_ll_mpll_calibration_stop(); if (thread_safe) { _regi2c_ctrl_ll_master_enable_clock(false); diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c index 462084da08..13169a76e8 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c @@ -19,7 +19,6 @@ #include "esp_rom_sys.h" #include "esp_hw_log.h" #include "hal/clk_tree_ll.h" -#include "hal/regi2c_ctrl_ll.h" #include "hal/rtc_io_ll.h" #include "esp_private/regi2c_ctrl.h" #include "soc/regi2c_dig_reg.h" @@ -189,13 +188,13 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) clk_ll_bbpll_set_freq_mhz(pll_freq); /* Analog part */ /* BBPLL CALIBRATION START */ - regi2c_ctrl_ll_bbpll_calibration_start(); + clk_ll_bbpll_calibration_start(); clk_ll_bbpll_set_config(pll_freq, xtal_freq); /* WAIT CALIBRATION DONE */ - while(!regi2c_ctrl_ll_bbpll_calibration_is_done()); + while(!clk_ll_bbpll_calibration_is_done()); esp_rom_delay_us(10); /* BBPLL CALIBRATION STOP */ - regi2c_ctrl_ll_bbpll_calibration_stop(); + clk_ll_bbpll_calibration_stop(); s_cur_pll_freq = pll_freq; } diff --git a/components/esp_hw_support/regi2c_ctrl.c b/components/esp_hw_support/regi2c_ctrl.c index 5ae13e21e2..e3fe6b9217 100644 --- a/components/esp_hw_support/regi2c_ctrl.c +++ b/components/esp_hw_support/regi2c_ctrl.c @@ -10,20 +10,17 @@ #include "freertos/FreeRTOS.h" #include "freertos/semphr.h" #include "hal/regi2c_ctrl.h" -#include "hal/regi2c_ctrl_ll.h" -#include "esp_hw_log.h" -#include "soc/soc_caps.h" #include "esp_private/critical_section.h" -static portMUX_TYPE __attribute__((unused)) mux = portMUX_INITIALIZER_UNLOCKED; - -ESP_HW_LOG_ATTR_TAG_DRAM(TAG, "REGI2C"); +// This lock is used to protect the analog i2c bus from being used concurrently +DEFINE_CRIT_SECTION_LOCK_STATIC(mux); uint8_t regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add) { REGI2C_CLOCK_ENABLE(); + int __DECLARE_REGI2C_ATOMIC_ENV __attribute__((unused)); esp_os_enter_critical_safe(&mux); - uint8_t value = regi2c_read_reg_raw(block, host_id, reg_add); + uint8_t value = regi2c_impl_read(block, host_id, reg_add); esp_os_exit_critical_safe(&mux); REGI2C_CLOCK_DISABLE(); return value; @@ -32,8 +29,9 @@ uint8_t regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add) uint8_t regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) { REGI2C_CLOCK_ENABLE(); + int __DECLARE_REGI2C_ATOMIC_ENV __attribute__((unused)); esp_os_enter_critical_safe(&mux); - uint8_t value = regi2c_read_reg_mask_raw(block, host_id, reg_add, msb, lsb); + uint8_t value = regi2c_impl_read_mask(block, host_id, reg_add, msb, lsb); esp_os_exit_critical_safe(&mux); REGI2C_CLOCK_DISABLE(); return value; @@ -42,8 +40,9 @@ uint8_t regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_ad void regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) { REGI2C_CLOCK_ENABLE(); + int __DECLARE_REGI2C_ATOMIC_ENV __attribute__((unused)); esp_os_enter_critical_safe(&mux); - regi2c_write_reg_raw(block, host_id, reg_add, data); + regi2c_impl_write(block, host_id, reg_add, data); esp_os_exit_critical_safe(&mux); REGI2C_CLOCK_DISABLE(); } @@ -51,8 +50,9 @@ void regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint void regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) { REGI2C_CLOCK_ENABLE(); + int __DECLARE_REGI2C_ATOMIC_ENV __attribute__((unused)); esp_os_enter_critical_safe(&mux); - regi2c_write_reg_mask_raw(block, host_id, reg_add, msb, lsb, data); + regi2c_impl_write_mask(block, host_id, reg_add, msb, lsb, data); esp_os_exit_critical_safe(&mux); REGI2C_CLOCK_DISABLE(); } @@ -66,74 +66,3 @@ void regi2c_exit_critical(void) { esp_os_exit_critical_safe(&mux); } - -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround, and is fixed on later chips - */ -#if REGI2C_LL_ANA_CALI_PD_WORKAROUND -#include "soc/regi2c_saradc.h" - -static DRAM_ATTR uint8_t reg_val[REGI2C_LL_ANA_CALI_BYTE_NUM]; - -void IRAM_ATTR regi2c_analog_cali_reg_read(void) -{ - for (int i = 0; i < REGI2C_LL_ANA_CALI_BYTE_NUM; i++) { - reg_val[i] = regi2c_ctrl_read_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i); - } -} - -void IRAM_ATTR regi2c_analog_cali_reg_write(void) -{ - for (int i = 0; i < REGI2C_LL_ANA_CALI_BYTE_NUM; i++) { - regi2c_ctrl_write_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i, reg_val[i]); - } -} -#endif //#if ADC_CALI_PD_WORKAROUND - -/** - * REGI2C_SARADC reference count - */ -static int s_i2c_saradc_enable_cnt; - -void regi2c_saradc_enable(void) -{ - regi2c_enter_critical(); - s_i2c_saradc_enable_cnt++; - if (s_i2c_saradc_enable_cnt == 1) { - regi2c_ctrl_ll_i2c_sar_periph_enable(); - } - regi2c_exit_critical(); -} - -void regi2c_saradc_disable(void) -{ - regi2c_enter_critical(); - s_i2c_saradc_enable_cnt--; - if (s_i2c_saradc_enable_cnt < 0){ - regi2c_exit_critical(); - ESP_HW_LOGE(TAG, "REGI2C_SARADC is already disabled"); - } else if (s_i2c_saradc_enable_cnt == 0) { - regi2c_ctrl_ll_i2c_sar_periph_disable(); - } - regi2c_exit_critical(); - -} - -#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION - -#include "soc/regi2c_saradc.h" - -static DRAM_ATTR uint8_t dac_offset_regi2c; - -void IRAM_ATTR regi2c_tsens_reg_read(void) -{ - dac_offset_regi2c = REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC); -} - -void IRAM_ATTR regi2c_tsens_reg_write(void) -{ - REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, dac_offset_regi2c); -} - -#endif diff --git a/components/esp_hw_support/sar_periph_ctrl_common.c b/components/esp_hw_support/sar_periph_ctrl_common.c new file mode 100644 index 0000000000..be744819f1 --- /dev/null +++ b/components/esp_hw_support/sar_periph_ctrl_common.c @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" +#include "esp_private/critical_section.h" +#include "hal/regi2c_ctrl_ll.h" +#include "esp_hw_log.h" +#include "esp_private/sar_periph_ctrl.h" + +ESP_HW_LOG_ATTR_TAG(TAG, "sar_ctrl_common"); + +DEFINE_CRIT_SECTION_LOCK_STATIC(mux); + +static int s_i2c_saradc_enable_cnt; + +void regi2c_saradc_enable(void) +{ + esp_os_enter_critical_safe(&mux); + s_i2c_saradc_enable_cnt++; + if (s_i2c_saradc_enable_cnt == 1) { + regi2c_ctrl_ll_i2c_sar_periph_enable(); + } + esp_os_exit_critical_safe(&mux); +} + +void regi2c_saradc_disable(void) +{ + esp_os_enter_critical_safe(&mux); + s_i2c_saradc_enable_cnt--; + if (s_i2c_saradc_enable_cnt < 0){ + esp_os_exit_critical_safe(&mux); + ESP_HW_LOGE(TAG, "REGI2C_SARADC is already disabled"); + return; + } else if (s_i2c_saradc_enable_cnt == 0) { + regi2c_ctrl_ll_i2c_sar_periph_disable(); + } + esp_os_exit_critical_safe(&mux); +} diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index ad9e148d2b..62cf582d8d 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -65,7 +65,6 @@ #include "hal/rtc_hal.h" #include "soc/rtc.h" -#include "regi2c_ctrl.h" //For `REGI2C_LL_ANA_CALI_PD_WORKAROUND`, temp #include "hal/cache_ll.h" #include "hal/clk_tree_ll.h" @@ -74,6 +73,11 @@ #if SOC_TOUCH_SENSOR_SUPPORTED #include "hal/touch_sens_hal.h" #endif +#if SOC_ADC_SUPPORTED +#include "hal/adc_ll.h" // For `ADC_LL_ANA_CALI_REG_PD_WORKAROUND`, temp +#include "hal/adc_hal_common.h" +#endif +#include "hal/temperature_sensor_hal.h" #include "hal/mspi_ll.h" #include "sdkconfig.h" @@ -701,11 +705,11 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool Cache_WriteBack_All(); } #endif -#if REGI2C_LL_ANA_CALI_PD_WORKAROUND - regi2c_analog_cali_reg_read(); +#if ADC_LL_ANA_CALI_REG_PD_WORKAROUND + adc_hal_i2c_saradc_reg_backup(); #endif #if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION - regi2c_tsens_reg_read(); + temperature_sensor_hal_i2c_saradc_reg_backup(); #endif } #if CONFIG_ESP_ENABLE_PVT && SOC_PVT_EN_WITH_SLEEP @@ -765,11 +769,11 @@ static SLEEP_FN_ATTR void misc_modules_wake_prepare(uint32_t sleep_flags) clk_ll_soc_root_clk_auto_gating_bypass(true); # endif #endif -#if REGI2C_LL_ANA_CALI_PD_WORKAROUND - regi2c_analog_cali_reg_write(); +#if ADC_LL_ANA_CALI_REG_PD_WORKAROUND + adc_hal_i2c_saradc_reg_restore(); #endif #if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION - regi2c_tsens_reg_write(); + temperature_sensor_hal_i2c_saradc_reg_restore(); #endif #if RNG_LL_DEPENDS_ON_LP_PERIPH if (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) { diff --git a/components/esp_pm/linker.lf b/components/esp_pm/linker.lf index cd783b7ae9..484a5aa1f8 100644 --- a/components/esp_pm/linker.lf +++ b/components/esp_pm/linker.lf @@ -46,8 +46,8 @@ entries: sar_tsens_ctrl:temperature_sensor_power_acquire (noflash) sar_tsens_ctrl:temperature_sensor_power_release (noflash) sar_tsens_ctrl:temp_sensor_get_raw_value (noflash) - regi2c_ctrl:regi2c_saradc_enable (noflash) - regi2c_ctrl:regi2c_saradc_disable (noflash) + sar_periph_ctrl_common:regi2c_saradc_enable (noflash) + sar_periph_ctrl_common:regi2c_saradc_disable (noflash) if SOC_ADC_SUPPORTED = y: adc_share_hw_ctrl:adc_apb_periph_claim (noflash) adc_share_hw_ctrl:adc_apb_periph_free (noflash) diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 0b264900a8..09b671b936 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -24,16 +24,6 @@ else() "patches/esp_rom_efuse.c" "patches/esp_rom_gpio.c") - - # Override regi2c implementation in ROM - if(CONFIG_ESP_ROM_HAS_REGI2C_BUG OR CONFIG_ESP_ROM_WITHOUT_REGI2C) - if(target STREQUAL "esp32c6" OR target STREQUAL "esp32c5") - list(APPEND sources "patches/esp_rom_hp_regi2c_${target}.c") - else() - list(APPEND sources "patches/esp_rom_regi2c_${target}.c") - endif() - endif() - if(CONFIG_HEAP_TLSF_USE_ROM_IMPL AND CONFIG_ESP_ROM_TLSF_CHECK_PATCH) # This file shall be included in the build if TLSF in ROM is activated list(APPEND sources "patches/esp_rom_tlsf.c") diff --git a/components/esp_rom/esp32/Kconfig.soc_caps.in b/components/esp_rom/esp32/Kconfig.soc_caps.in index 37e4cb4ab5..54a5c404ba 100644 --- a/components/esp_rom/esp32/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32/Kconfig.soc_caps.in @@ -58,3 +58,7 @@ config ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB config ESP_ROM_HAS_OUTPUT_PUTC_FUNC bool default y + +config ESP_ROM_HAS_REGI2C_IMPL + bool + default y diff --git a/components/esp_rom/esp32/esp_rom_caps.h b/components/esp_rom/esp32/esp_rom_caps.h index 27675717e4..5a387b51c8 100644 --- a/components/esp_rom/esp32/esp_rom_caps.h +++ b/components/esp_rom/esp32/esp_rom_caps.h @@ -20,3 +20,4 @@ #define ESP_ROM_USB_SERIAL_DEVICE_NUM (-1) // No USB_SERIAL_JTAG in the ROM, set -1 for Kconfig usage. #define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep. #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) +#define ESP_ROM_HAS_REGI2C_IMPL (1) // ROM has the implementation of REGI2C read/write functions diff --git a/components/esp_rom/esp32/ld/esp32.rom.api.ld b/components/esp_rom/esp32/ld/esp32.rom.api.ld index 1321113c17..91f3e90208 100644 --- a/components/esp_rom/esp32/ld/esp32.rom.api.ld +++ b/components/esp_rom/esp32/ld/esp32.rom.api.ld @@ -55,8 +55,3 @@ PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); PROVIDE ( esp_rom_spiflash_set_bp = esp_rom_spiflash_lock ); PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable); - -PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg ); -PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask ); -PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg ); -PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask ); diff --git a/components/esp_rom/esp32/ld/esp32.rom.ld b/components/esp_rom/esp32/ld/esp32.rom.ld index 9c27c7746b..6a451b4321 100644 --- a/components/esp_rom/esp32/ld/esp32.rom.ld +++ b/components/esp_rom/esp32/ld/esp32.rom.ld @@ -1173,10 +1173,6 @@ PROVIDE ( rom_get_pwctrl_correct = 0x400065d4 ); PROVIDE ( rom_get_rfcal_rxiq_data = 0x40005bbc ); PROVIDE ( rom_get_rf_gain_qdb = 0x40006290 ); PROVIDE ( rom_get_sar_dout = 0x40006564 ); -PROVIDE ( rom_i2c_readReg = 0x40004148 ); -PROVIDE ( rom_i2c_readReg_Mask = 0x400041c0 ); -PROVIDE ( rom_i2c_writeReg = 0x400041a4 ); -PROVIDE ( rom_i2c_writeReg_Mask = 0x400041fc ); PROVIDE ( rom_index_to_txbbgain = 0x40004df8 ); PROVIDE ( rom_iq_est_disable = 0x40005590 ); PROVIDE ( rom_iq_est_enable = 0x40005514 ); diff --git a/components/esp_rom/esp32c2/Kconfig.soc_caps.in b/components/esp_rom/esp32c2/Kconfig.soc_caps.in index 50fbfeab1a..8b5fcfe9b2 100644 --- a/components/esp_rom/esp32c2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c2/Kconfig.soc_caps.in @@ -110,3 +110,7 @@ config ESP_ROM_CONSOLE_OUTPUT_SECONDARY config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY bool default y + +config ESP_ROM_HAS_REGI2C_IMPL + bool + default y diff --git a/components/esp_rom/esp32c2/esp_rom_caps.h b/components/esp_rom/esp32c2/esp_rom_caps.h index 881e52ba64..7307a8ddcc 100644 --- a/components/esp_rom/esp32c2/esp_rom_caps.h +++ b/components/esp_rom/esp32c2/esp_rom_caps.h @@ -33,3 +33,4 @@ #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) #define ESP_ROM_CONSOLE_OUTPUT_SECONDARY (1) // The console output functions will also output to the USB-serial secondary console #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access. +#define ESP_ROM_HAS_REGI2C_IMPL (1) // ROM has the implementation of REGI2C read/write functions diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld index e9c6eb95e9..a85c065d1b 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -62,8 +62,3 @@ PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix ); PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs); PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction ); PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command ); - -PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg ); -PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask ); -PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg ); -PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask ); diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld index b257d14296..7ae3b32271 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld @@ -1098,11 +1098,7 @@ rom_i2c_paral_read = 0x400022dc; rom_i2c_paral_write = 0x400022e0; rom_i2c_paral_write_num = 0x400022e4; rom_i2c_paral_write_mask = 0x400022e8; -rom_i2c_readReg = 0x400022ec; rom_chip_i2c_writeReg = 0x400022f0; -rom_i2c_writeReg = 0x400022f4; -rom_i2c_readReg_Mask = 0x400022f8; -rom_i2c_writeReg_Mask = 0x400022fc; rom_set_txcap_reg = 0x40002300; i2c_sar2_init_code = 0x40002304; phy_i2c_init1 = 0x40002308; diff --git a/components/esp_rom/esp32c3/Kconfig.soc_caps.in b/components/esp_rom/esp32c3/Kconfig.soc_caps.in index 5498ffab5b..061379e2cc 100644 --- a/components/esp_rom/esp32c3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c3/Kconfig.soc_caps.in @@ -106,3 +106,7 @@ config ESP_ROM_CONSOLE_OUTPUT_SECONDARY config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY bool default y + +config ESP_ROM_HAS_REGI2C_IMPL + bool + default y diff --git a/components/esp_rom/esp32c3/esp_rom_caps.h b/components/esp_rom/esp32c3/esp_rom_caps.h index ccb7762199..ce9b8a8f4f 100644 --- a/components/esp_rom/esp32c3/esp_rom_caps.h +++ b/components/esp_rom/esp32c3/esp_rom_caps.h @@ -32,3 +32,4 @@ #define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep. #define ESP_ROM_CONSOLE_OUTPUT_SECONDARY (1) // The console output functions will also output to the USB-serial secondary console #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access. +#define ESP_ROM_HAS_REGI2C_IMPL (1) // ROM has the implementation of REGI2C read/write functions diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld index a1b8713c2f..3c6079d4e6 100644 --- a/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld +++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld @@ -54,8 +54,3 @@ PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix ); PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs); PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction ); PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command ); - -PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg ); -PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask ); -PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg ); -PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask ); diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.ld index 6ad741688b..214e634a81 100644 --- a/components/esp_rom/esp32c3/ld/esp32c3.rom.ld +++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.ld @@ -983,10 +983,6 @@ rom_get_data_sat = 0x40001944; rom_get_i2c_read_mask = 0x40001948; rom_get_pwctrl_correct = 0x4000194c; rom_get_rf_gain_qdb = 0x40001950; -rom_i2c_readReg = 0x40001954; -rom_i2c_readReg_Mask = 0x40001958; -rom_i2c_writeReg = 0x4000195c; -rom_i2c_writeReg_Mask = 0x40001960; /* rom_index_to_txbbgain = 0x40001964; */ rom_iq_est_disable = 0x40001968; rom_iq_est_enable = 0x4000196c; diff --git a/components/esp_rom/esp32c5/Kconfig.soc_caps.in b/components/esp_rom/esp32c5/Kconfig.soc_caps.in index f475909a2a..e627affde0 100644 --- a/components/esp_rom/esp32c5/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c5/Kconfig.soc_caps.in @@ -71,10 +71,6 @@ config ESP_ROM_HAS_SPI_FLASH_MMAP bool default y -config ESP_ROM_WITHOUT_REGI2C - bool - default y - config ESP_ROM_HAS_NEWLIB bool default y diff --git a/components/esp_rom/esp32c5/esp_rom_caps.h b/components/esp_rom/esp32c5/esp_rom_caps.h index 1812656eb2..bead727fee 100644 --- a/components/esp_rom/esp32c5/esp_rom_caps.h +++ b/components/esp_rom/esp32c5/esp_rom_caps.h @@ -23,7 +23,6 @@ #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver #define ESP_ROM_HAS_SPI_FLASH_MMAP (1) // ROM has the implementation of SPI Flash mmap driver -#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs TODO: IDF-10110 need refactor #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock diff --git a/components/esp_rom/esp32c6/Kconfig.soc_caps.in b/components/esp_rom/esp32c6/Kconfig.soc_caps.in index 2f6dba3eca..2c703be2ba 100644 --- a/components/esp_rom/esp32c6/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c6/Kconfig.soc_caps.in @@ -71,10 +71,6 @@ config ESP_ROM_HAS_SPI_FLASH_MMAP bool default y -config ESP_ROM_HAS_REGI2C_BUG - bool - default y - config ESP_ROM_HAS_NEWLIB bool default y diff --git a/components/esp_rom/esp32c6/esp_rom_caps.h b/components/esp_rom/esp32c6/esp_rom_caps.h index 1bd42f0899..6b6d42ece3 100644 --- a/components/esp_rom/esp32c6/esp_rom_caps.h +++ b/components/esp_rom/esp32c6/esp_rom_caps.h @@ -23,7 +23,6 @@ #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver #define ESP_ROM_HAS_SPI_FLASH_MMAP (1) // ROM has the implementation of SPI Flash mmap driver -#define ESP_ROM_HAS_REGI2C_BUG (1) // ROM has the regi2c bug #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions) #define ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE (1) // ECO 0 does not have ets_ecdsa_verify symbol, future revision will have it diff --git a/components/esp_rom/esp32c61/Kconfig.soc_caps.in b/components/esp_rom/esp32c61/Kconfig.soc_caps.in index de114450fa..03e1199ac2 100644 --- a/components/esp_rom/esp32c61/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c61/Kconfig.soc_caps.in @@ -71,10 +71,6 @@ config ESP_ROM_HAS_SPI_FLASH_MMAP bool default y -config ESP_ROM_WITHOUT_REGI2C - bool - default y - config ESP_ROM_HAS_NEWLIB bool default y diff --git a/components/esp_rom/esp32c61/esp_rom_caps.h b/components/esp_rom/esp32c61/esp_rom_caps.h index 88c28b664d..ef17c1bdbf 100644 --- a/components/esp_rom/esp32c61/esp_rom_caps.h +++ b/components/esp_rom/esp32c61/esp_rom_caps.h @@ -23,7 +23,6 @@ #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver #define ESP_ROM_HAS_SPI_FLASH_MMAP (1) // ROM has the implementation of SPI Flash mmap driver -#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs TODO: IDF-10110 need refactor #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG (1) // ROM has the printf float bug with newlib nano version diff --git a/components/esp_rom/esp32h2/Kconfig.soc_caps.in b/components/esp_rom/esp32h2/Kconfig.soc_caps.in index 57dae80a53..7fcb98e28d 100644 --- a/components/esp_rom/esp32h2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h2/Kconfig.soc_caps.in @@ -63,10 +63,6 @@ config ESP_ROM_HAS_SPI_FLASH_MMAP bool default y -config ESP_ROM_WITHOUT_REGI2C - bool - default y - config ESP_ROM_HAS_NEWLIB bool default y diff --git a/components/esp_rom/esp32h2/esp_rom_caps.h b/components/esp_rom/esp32h2/esp_rom_caps.h index cb9475c9ea..7166b5eac6 100644 --- a/components/esp_rom/esp32h2/esp_rom_caps.h +++ b/components/esp_rom/esp32h2/esp_rom_caps.h @@ -21,7 +21,6 @@ #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver #define ESP_ROM_HAS_SPI_FLASH_MMAP (1) // ROM has the implementation of SPI Flash mmap driver -#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano versions of formatting functions #define ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG (1) // ROM has the printf float bug with newlib nano version diff --git a/components/esp_rom/esp32h21/Kconfig.soc_caps.in b/components/esp_rom/esp32h21/Kconfig.soc_caps.in index 836a3e3874..f4c78e645e 100644 --- a/components/esp_rom/esp32h21/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h21/Kconfig.soc_caps.in @@ -59,10 +59,6 @@ config ESP_ROM_HAS_SPI_FLASH_MMAP bool default y -config ESP_ROM_WITHOUT_REGI2C - bool - default y - config ESP_ROM_HAS_NEWLIB bool default y diff --git a/components/esp_rom/esp32h21/esp_rom_caps.h b/components/esp_rom/esp32h21/esp_rom_caps.h index d08c8ecf72..4dcbac4149 100644 --- a/components/esp_rom/esp32h21/esp_rom_caps.h +++ b/components/esp_rom/esp32h21/esp_rom_caps.h @@ -20,7 +20,6 @@ #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver #define ESP_ROM_HAS_SPI_FLASH_MMAP (1) // ROM has the implementation of SPI Flash mmap driver -#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano versions of formatting functions #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock diff --git a/components/esp_rom/esp32h4/Kconfig.soc_caps.in b/components/esp_rom/esp32h4/Kconfig.soc_caps.in index d40437c43e..84dca246b2 100644 --- a/components/esp_rom/esp32h4/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h4/Kconfig.soc_caps.in @@ -51,10 +51,6 @@ config ESP_ROM_HAS_LAYOUT_TABLE bool default y -config ESP_ROM_WITHOUT_REGI2C - bool - default y - config ESP_ROM_HAS_NEWLIB bool default y diff --git a/components/esp_rom/esp32h4/esp_rom_caps.h b/components/esp_rom/esp32h4/esp_rom_caps.h index 5276df390b..58db76b786 100644 --- a/components/esp_rom/esp32h4/esp_rom_caps.h +++ b/components/esp_rom/esp32h4/esp_rom_caps.h @@ -18,7 +18,6 @@ #define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library #define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk() #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table -#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has the regi2c bug or rom does not support regi2c function #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano versions of formatting functions #define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage. diff --git a/components/esp_rom/esp32p4/Kconfig.soc_caps.in b/components/esp_rom/esp32p4/Kconfig.soc_caps.in index 42ccc7ed5f..15a26f127a 100644 --- a/components/esp_rom/esp32p4/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32p4/Kconfig.soc_caps.in @@ -59,10 +59,6 @@ config ESP_ROM_HAS_LP_ROM bool default y -config ESP_ROM_WITHOUT_REGI2C - bool - default y - config ESP_ROM_HAS_NEWLIB bool default y diff --git a/components/esp_rom/esp32p4/esp_rom_caps.h b/components/esp_rom/esp32p4/esp_rom_caps.h index 437fa7bdd7..e42df199fd 100644 --- a/components/esp_rom/esp32p4/esp_rom_caps.h +++ b/components/esp_rom/esp32p4/esp_rom_caps.h @@ -20,7 +20,6 @@ #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock #define ESP_ROM_HAS_LP_ROM (1) // ROM also has a LP ROM placed in LP memory -#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG (1) // ROM has the printf float bug with newlib nano version diff --git a/components/esp_rom/esp32s2/Kconfig.soc_caps.in b/components/esp_rom/esp32s2/Kconfig.soc_caps.in index a4dc4de268..09c55fd7bb 100644 --- a/components/esp_rom/esp32s2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s2/Kconfig.soc_caps.in @@ -19,10 +19,6 @@ config ESP_ROM_NEEDS_SWSETUP_WORKAROUND bool default y -config ESP_ROM_HAS_REGI2C_BUG - bool - default y - config ESP_ROM_HAS_NEWLIB bool default y diff --git a/components/esp_rom/esp32s2/esp_rom_caps.h b/components/esp_rom/esp32s2/esp_rom_caps.h index c89f9c128c..06ddf3dc4a 100644 --- a/components/esp_rom/esp32s2/esp_rom_caps.h +++ b/components/esp_rom/esp32s2/esp_rom_caps.h @@ -10,7 +10,7 @@ #define ESP_ROM_HAS_MZ_CRC32 (1) // ROM has mz_crc32 function #define ESP_ROM_HAS_UART_BUF_SWITCH (1) // ROM has exported the uart buffer switch function #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing -#define ESP_ROM_HAS_REGI2C_BUG (1) // ROM has the regi2c bug +// #define ESP_ROM_HAS_REGI2C_IMPL (1) // ROM has the implementation of REGI2C read/write functions (but has bugs, we don't use it) #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_HAS_NEWLIB_32BIT_TIME (1) // ROM was compiled with 32 bit time_t diff --git a/components/esp_rom/esp32s2/ld/esp32s2.rom.ld b/components/esp_rom/esp32s2/ld/esp32s2.rom.ld index fba68198a7..4edc70f0fd 100644 --- a/components/esp_rom/esp32s2/ld/esp32s2.rom.ld +++ b/components/esp_rom/esp32s2/ld/esp32s2.rom.ld @@ -480,10 +480,10 @@ PROVIDE ( rom_get_rfcal_rxiq_data = 0x4000cab0 ); PROVIDE ( rom_get_rf_gain_qdb = 0x4000d29c ); PROVIDE ( rom_get_sar_dout = 0x4000d400 ); PROVIDE ( rom_i2c_clk_sel = 0x4000a788 ); -PROVIDE ( rom_i2c_readReg = 0x4000a940 ); -PROVIDE ( rom_i2c_readReg_Mask = 0x4000a9c4 ); -PROVIDE ( rom_i2c_writeReg = 0x4000a9a8 ); -PROVIDE ( rom_i2c_writeReg_Mask = 0x4000aa00 ); +/* PROVIDE ( rom_i2c_readReg = 0x4000a940 ); ROM version has bug, we don't use */ +/* PROVIDE ( rom_i2c_readReg_Mask = 0x4000a9c4 ); ROM version has bug, we don't use */ +/* PROVIDE ( rom_i2c_writeReg = 0x4000a9a8 ); ROM version has bug, we don't use */ +/* PROVIDE ( rom_i2c_writeReg_Mask = 0x4000aa00 ); ROM version has bug, we don't use */ PROVIDE ( rom_index_to_txbbgain = 0x4000bd10 ); PROVIDE ( rom_iq_est_disable = 0x4000c3d8 ); PROVIDE ( rom_iq_est_enable = 0x4000c358 ); diff --git a/components/esp_rom/esp32s3/Kconfig.soc_caps.in b/components/esp_rom/esp32s3/Kconfig.soc_caps.in index 7723ea47d7..8d36b54e35 100644 --- a/components/esp_rom/esp32s3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s3/Kconfig.soc_caps.in @@ -122,3 +122,7 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC config ESP_ROM_CONSOLE_OUTPUT_SECONDARY bool default y + +config ESP_ROM_HAS_REGI2C_IMPL + bool + default y diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h index 566c593b5a..f2a0302466 100644 --- a/components/esp_rom/esp32s3/esp_rom_caps.h +++ b/components/esp_rom/esp32s3/esp_rom_caps.h @@ -36,3 +36,4 @@ #define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep. #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) #define ESP_ROM_CONSOLE_OUTPUT_SECONDARY (1) // The console output functions will also output to the USB-serial secondary console +#define ESP_ROM_HAS_REGI2C_IMPL (1) // ROM has the implementation of REGI2C read/write functions diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld index 5afa9926eb..38f4900917 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld @@ -62,8 +62,3 @@ PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix ); PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs); PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction ); PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command ); - -PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg ); -PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask ); -PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg ); -PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask ); diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld index 7f7fdf550b..d8143aa3fb 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld @@ -1242,10 +1242,6 @@ rom_get_bbgain_db = 0x40005d18; rom_get_data_sat = 0x40005d24; rom_get_i2c_read_mask = 0x40005d30; rom_get_pwctrl_correct = 0x40005d3c; -rom_i2c_readReg = 0x40005d48; -rom_i2c_readReg_Mask = 0x40005d54; -rom_i2c_writeReg = 0x40005d60; -rom_i2c_writeReg_Mask = 0x40005d6c; rom_index_to_txbbgain = 0x40005d78; rom_iq_est_disable = 0x40005d84; rom_iq_est_enable = 0x40005d90; diff --git a/components/esp_rom/esp32s31/Kconfig.soc_caps.in b/components/esp_rom/esp32s31/Kconfig.soc_caps.in index 8d8dec58f5..9d4d933fb3 100644 --- a/components/esp_rom/esp32s31/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s31/Kconfig.soc_caps.in @@ -55,10 +55,6 @@ config ESP_ROM_WDT_INIT_PATCH bool default y -config ESP_ROM_WITHOUT_REGI2C - bool - default y - config ESP_ROM_HAS_HEAP_TLSF bool default y diff --git a/components/esp_rom/esp32s31/esp_rom_caps.h b/components/esp_rom/esp32s31/esp_rom_caps.h index 391b689171..c165e4e3a2 100644 --- a/components/esp_rom/esp32s31/esp_rom_caps.h +++ b/components/esp_rom/esp32s31/esp_rom_caps.h @@ -19,7 +19,6 @@ #define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock -#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs #define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32s31.c b/components/esp_rom/patches/esp_rom_regi2c_esp32s31.c deleted file mode 100644 index c538f617a9..0000000000 --- a/components/esp_rom/patches/esp_rom_regi2c_esp32s31.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "esp_rom_sys.h" -#include "esp_attr.h" - -uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) -{ - // TODO: [ESP32S31] IDF-14680 - return 0; -} - -uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) -{ - // TODO: [ESP32S31] IDF-14680 - return 0; -} - -void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) -{ - // TODO: [ESP32S31] IDF-14680 -} - -void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) -{ - // TODO: [ESP32S31] IDF-14680 -} diff --git a/components/hal/esp32/efuse_hal.c b/components/hal/esp32/efuse_hal.c index 7a8148e5ad..a1a67ebdf0 100644 --- a/components/hal/esp32/efuse_hal.c +++ b/components/hal/esp32/efuse_hal.c @@ -29,11 +29,11 @@ IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void) case 3: chip_ver = 2; break; -#if HAL_CONFIG(EFUSE_ENV_FPGA) +#if HAL_CONFIG(ENV_FPGA) case 4: /* Empty efuses, but SYSCON_DATE_REG bit is set */ chip_ver = 3; break; -#endif // HAL_CONFIG_EFUSE_ENV_FPGA +#endif // HAL_CONFIG_ENV_FPGA case 7: chip_ver = 3; break; diff --git a/components/hal/platform_port/include/hal/config.h b/components/hal/platform_port/include/hal/config.h index fd4709c622..5dd14329bb 100644 --- a/components/hal/platform_port/include/hal/config.h +++ b/components/hal/platform_port/include/hal/config.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,7 +30,7 @@ extern "C" { /** * @brief Enable this to indicate the target is an FPGA. */ -#define HAL_CONFIG_EFUSE_ENV_FPGA CONFIG_IDF_ENV_FPGA +#define HAL_CONFIG_ENV_FPGA CONFIG_IDF_ENV_FPGA /** * @brief When the hardware fails in measuring the XTAL frequency, use this value as a hint. diff --git a/components/hal/platform_port/include/hal/regi2c_ctrl.h b/components/hal/platform_port/include/hal/regi2c_ctrl.h deleted file mode 100644 index dea715874d..0000000000 --- a/components/hal/platform_port/include/hal/regi2c_ctrl.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -/** - * When compiling G0-layer only, we can't depend on `esp_hw_support` component. - * However, `esp_private/regi2c_ctrl.h` is part of that component. - * Thus, if we don't have this header file in our compilation unit, we should use - * ROM functions. - * The main difference is that `regi2c_ctrl.h` implementation protects the functions - * with mutex. ROM functions must be protected explicitly by the user. - */ -#if __has_include("esp_private/regi2c_ctrl.h") - #include "esp_private/regi2c_ctrl.h" -#else - #include "esp_rom_regi2c.h" - - #define REGI2C_WRITE_MASK(block, reg_add, indata) \ - esp_rom_regi2c_write_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata) - - #define REGI2C_WRITE(block, reg_add, indata) \ - esp_rom_regi2c_write(block, block##_HOSTID, reg_add, indata) - - #define REGI2C_READ_MASK(block, reg_add) \ - esp_rom_regi2c_read_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB) - - #define REGI2C_READ(block, reg_add) \ - esp_rom_regi2c_read(block, block##_HOSTID, reg_add) - - #define REGI2C_ENTER_CRITICAL() - #define REGI2C_EXIT_CRITICAL() -#endif diff --git a/components/soc/esp32/register/soc/sens_struct.h b/components/soc/esp32/register/soc/sens_struct.h index 5294aee02c..0baa33a49f 100644 --- a/components/soc/esp32/register/soc/sens_struct.h +++ b/components/soc/esp32/register/soc/sens_struct.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -12,8 +12,8 @@ extern "C" { #endif -typedef volatile struct sens_dev_s { - union { +typedef struct sens_dev_t { + volatile union { struct { uint32_t sar1_clk_div: 8; uint32_t sar1_sample_cycle: 8; @@ -26,15 +26,15 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_read_ctrl; - uint32_t sar_read_status1; /**/ - union { + volatile uint32_t sar_read_status1; /**/ + volatile union { struct { uint32_t sar_amp_wait1:16; uint32_t sar_amp_wait2:16; }; uint32_t val; } sar_meas_wait1; - union { + volatile union { struct { uint32_t sar_amp_wait3: 16; uint32_t force_xpd_amp: 2; @@ -44,7 +44,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_meas_wait2; - union { + volatile union { struct { uint32_t xpd_sar_amp_fsm: 4; uint32_t amp_rst_fb_fsm: 4; @@ -56,13 +56,13 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_meas_ctrl; - uint32_t sar_read_status2; /**/ - uint32_t ulp_cp_sleep_cyc0; /**/ - uint32_t ulp_cp_sleep_cyc1; /**/ - uint32_t ulp_cp_sleep_cyc2; /**/ - uint32_t ulp_cp_sleep_cyc3; /**/ - uint32_t ulp_cp_sleep_cyc4; /**/ - union { + volatile uint32_t sar_read_status2; /**/ + volatile uint32_t ulp_cp_sleep_cyc0; /**/ + volatile uint32_t ulp_cp_sleep_cyc1; /**/ + volatile uint32_t ulp_cp_sleep_cyc2; /**/ + volatile uint32_t ulp_cp_sleep_cyc3; /**/ + volatile uint32_t ulp_cp_sleep_cyc4; /**/ + volatile union { struct { uint32_t sar1_bit_width: 2; uint32_t sar2_bit_width: 2; @@ -79,7 +79,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_start_force; - union { + volatile union { struct { uint32_t mem_wr_addr_init: 11; uint32_t mem_wr_addr_size: 11; @@ -88,9 +88,9 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_mem_wr_ctrl; - uint32_t sar_atten1; /**/ - uint32_t sar_atten2; /**/ - union { + volatile uint32_t sar_atten1; /**/ + volatile uint32_t sar_atten2; /**/ + volatile union { struct { uint32_t i2c_slave_addr1: 11; uint32_t i2c_slave_addr0: 11; @@ -107,7 +107,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_slave_addr2; - union { + volatile union { struct { uint32_t i2c_slave_addr5:11; uint32_t i2c_slave_addr4:11; @@ -117,7 +117,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_slave_addr3; - union { + volatile union { struct { uint32_t i2c_slave_addr7:11; uint32_t i2c_slave_addr6:11; @@ -127,7 +127,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_slave_addr4; - union { + volatile union { struct { uint32_t tsens_xpd_wait: 12; uint32_t tsens_xpd_force: 1; @@ -142,7 +142,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_tctrl; - union { + volatile union { struct { uint32_t sar_i2c_ctrl: 28; uint32_t sar_i2c_start: 1; @@ -151,7 +151,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_i2c_ctrl; - union { + volatile union { struct { uint32_t meas1_data_sar: 16; uint32_t meas1_done_sar: 1; @@ -162,7 +162,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_meas_start1; - union { + volatile union { struct { uint32_t touch_meas_delay:16; uint32_t touch_xpd_wait: 8; @@ -174,21 +174,21 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_touch_ctrl1; - union { + volatile union { struct { uint32_t l_thresh: 16; uint32_t h_thresh: 16; }; uint32_t val; } touch_thresh[5]; - union { + volatile union { struct { uint32_t l_val: 16; uint32_t h_val: 16; }; uint32_t val; } touch_meas[5]; - union { + volatile union { struct { uint32_t touch_meas_en: 10; uint32_t touch_meas_done: 1; @@ -202,7 +202,7 @@ typedef volatile struct sens_dev_s { uint32_t val; } sar_touch_ctrl2; uint32_t reserved_88; - union { + volatile union { struct { uint32_t touch_pad_worken:10; uint32_t touch_pad_outen2:10; @@ -211,7 +211,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_touch_enable; - union { + volatile union { struct { uint32_t sar2_clk_div: 8; uint32_t sar2_sample_cycle: 8; @@ -225,7 +225,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_read_ctrl2; - union { + volatile union { struct { uint32_t meas2_data_sar: 16; uint32_t meas2_done_sar: 1; @@ -236,7 +236,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_meas_start2; - union { + volatile union { struct { uint32_t sw_fstep: 16; uint32_t sw_tone_en: 1; @@ -249,7 +249,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_dac_ctrl1; - union { + volatile union { struct { uint32_t dac_dc1: 8; uint32_t dac_dc2: 8; @@ -263,7 +263,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_dac_ctrl2; - union { + volatile union { struct { uint32_t sar1_dac_xpd_fsm: 4; uint32_t sar1_dac_xpd_fsm_idle: 1; @@ -302,8 +302,8 @@ typedef volatile struct sens_dev_s { uint32_t reserved_ec; uint32_t reserved_f0; uint32_t reserved_f4; - uint32_t sar_nouse; /**/ - union { + volatile uint32_t sar_nouse; /**/ + volatile union { struct { uint32_t sar_date: 28; uint32_t reserved28: 4; diff --git a/components/soc/esp32c5/register/soc/i2c_ana_mst_reg.h b/components/soc/esp32c5/include/modem/i2c_ana_mst_reg.h similarity index 99% rename from components/soc/esp32c5/register/soc/i2c_ana_mst_reg.h rename to components/soc/esp32c5/include/modem/i2c_ana_mst_reg.h index 91a49bf0e7..57e8187e07 100644 --- a/components/soc/esp32c5/register/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32c5/include/modem/i2c_ana_mst_reg.h @@ -7,7 +7,7 @@ #pragma once #include -#include "soc/soc.h" +#include "modem/reg_base.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32c5/include/modem/reg_base.h b/components/soc/esp32c5/include/modem/reg_base.h index e0b391e7e2..d7a700756d 100644 --- a/components/soc/esp32c5/include/modem/reg_base.h +++ b/components/soc/esp32c5/include/modem/reg_base.h @@ -7,3 +7,4 @@ #pragma once #define DR_REG_MODEM_SYSCON_BASE 0x600A9C00 #define DR_REG_MODEM_LPCON_BASE 0x600AF000 +#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 diff --git a/components/soc/esp32c5/register/soc/reg_base.h b/components/soc/esp32c5/register/soc/reg_base.h index c4725baa90..66601d1d0d 100644 --- a/components/soc/esp32c5/register/soc/reg_base.h +++ b/components/soc/esp32c5/register/soc/reg_base.h @@ -82,7 +82,6 @@ #define DR_REG_MODEM_PWR1_BASE 0x600AF000 #define PWDET_CONF_REG 0x600A0810 -#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 #define IEEE802154_REG_BASE 0x600A3000 /** diff --git a/components/soc/esp32c6/register/soc/i2c_ana_mst_reg.h b/components/soc/esp32c6/include/modem/i2c_ana_mst_reg.h similarity index 99% rename from components/soc/esp32c6/register/soc/i2c_ana_mst_reg.h rename to components/soc/esp32c6/include/modem/i2c_ana_mst_reg.h index f1d4ef210e..4b1c7fa0d0 100644 --- a/components/soc/esp32c6/register/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32c6/include/modem/i2c_ana_mst_reg.h @@ -7,7 +7,7 @@ #pragma once #include -#include "soc/soc.h" +#include "modem/reg_base.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32c6/include/modem/reg_base.h b/components/soc/esp32c6/include/modem/reg_base.h index 3a3bcd165e..405f400b3c 100644 --- a/components/soc/esp32c6/include/modem/reg_base.h +++ b/components/soc/esp32c6/include/modem/reg_base.h @@ -7,3 +7,4 @@ #pragma once #define DR_REG_MODEM_SYSCON_BASE 0x600A9800 #define DR_REG_MODEM_LPCON_BASE 0x600AF000 +#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 diff --git a/components/soc/esp32c6/register/soc/reg_base.h b/components/soc/esp32c6/register/soc/reg_base.h index a58c4fca84..f84e18c5c3 100644 --- a/components/soc/esp32c6/register/soc/reg_base.h +++ b/components/soc/esp32c6/register/soc/reg_base.h @@ -56,8 +56,6 @@ #define DR_REG_LP_APM0_BASE 0x60099800 #define DR_REG_MISC_BASE 0x6009F000 -#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 - #define DR_REG_PMU_BASE 0x600B0000 #define DR_REG_LP_CLKRST_BASE 0x600B0400 #define DR_REG_EFUSE_BASE 0x600B0800 diff --git a/components/soc/esp32c61/register/soc/i2c_ana_mst_reg.h b/components/soc/esp32c61/include/modem/i2c_ana_mst_reg.h similarity index 99% rename from components/soc/esp32c61/register/soc/i2c_ana_mst_reg.h rename to components/soc/esp32c61/include/modem/i2c_ana_mst_reg.h index 83321bb213..134ab8478d 100644 --- a/components/soc/esp32c61/register/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32c61/include/modem/i2c_ana_mst_reg.h @@ -7,7 +7,7 @@ #pragma once #include -#include "soc/soc.h" +#include "modem/reg_base.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32c61/include/modem/reg_base.h b/components/soc/esp32c61/include/modem/reg_base.h index e0b391e7e2..d7a700756d 100644 --- a/components/soc/esp32c61/include/modem/reg_base.h +++ b/components/soc/esp32c61/include/modem/reg_base.h @@ -7,3 +7,4 @@ #pragma once #define DR_REG_MODEM_SYSCON_BASE 0x600A9C00 #define DR_REG_MODEM_LPCON_BASE 0x600AF000 +#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 diff --git a/components/soc/esp32c61/register/soc/reg_base.h b/components/soc/esp32c61/register/soc/reg_base.h index d5d506ac6d..0e03d91d1a 100644 --- a/components/soc/esp32c61/register/soc/reg_base.h +++ b/components/soc/esp32c61/register/soc/reg_base.h @@ -62,4 +62,3 @@ // below are not generated but pick from old file #define DR_REG_CLINT_M_BASE 0x20000000 #define PWDET_CONF_REG 0x600A0808 -#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 diff --git a/components/soc/esp32h2/register/soc/i2c_ana_mst_reg.h b/components/soc/esp32h2/include/modem/i2c_ana_mst_reg.h similarity index 99% rename from components/soc/esp32h2/register/soc/i2c_ana_mst_reg.h rename to components/soc/esp32h2/include/modem/i2c_ana_mst_reg.h index e933dc2a36..fd8b2733e3 100644 --- a/components/soc/esp32h2/register/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32h2/include/modem/i2c_ana_mst_reg.h @@ -6,7 +6,7 @@ #pragma once #include -#include "soc/soc.h" +#include "modem/reg_base.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32h2/include/modem/reg_base.h b/components/soc/esp32h2/include/modem/reg_base.h index 4a33ea404f..801b274edd 100644 --- a/components/soc/esp32h2/include/modem/reg_base.h +++ b/components/soc/esp32h2/include/modem/reg_base.h @@ -7,3 +7,4 @@ #pragma once #define DR_REG_MODEM_SYSCON_BASE 0x600A5400 #define DR_REG_MODEM_LPCON_BASE 0x600AD000 +#define DR_REG_I2C_ANA_MST_BASE 0x600AD800 diff --git a/components/soc/esp32h2/register/soc/reg_base.h b/components/soc/esp32h2/register/soc/reg_base.h index 13e2ce6496..e4f13fa31d 100644 --- a/components/soc/esp32h2/register/soc/reg_base.h +++ b/components/soc/esp32h2/register/soc/reg_base.h @@ -50,8 +50,6 @@ #define DR_REG_LP_APM0_BASE 0x60099800 #define DR_REG_MISC_BASE 0x6009F000 -#define DR_REG_I2C_ANA_MST_BASE 0x600AD800 - #define DR_REG_PMU_BASE 0x600B0000 #define DR_REG_LP_CLKRST_BASE 0x600B0400 #define DR_REG_EFUSE_BASE 0x600B0800 diff --git a/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h b/components/soc/esp32h21/include/modem/i2c_ana_mst_reg.h similarity index 99% rename from components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h rename to components/soc/esp32h21/include/modem/i2c_ana_mst_reg.h index ecedf883b4..a1d0c418f2 100644 --- a/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32h21/include/modem/i2c_ana_mst_reg.h @@ -6,7 +6,7 @@ #pragma once #include -#include "soc/soc.h" +#include "modem/reg_base.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32h21/include/modem/reg_base.h b/components/soc/esp32h21/include/modem/reg_base.h index 4a33ea404f..801b274edd 100644 --- a/components/soc/esp32h21/include/modem/reg_base.h +++ b/components/soc/esp32h21/include/modem/reg_base.h @@ -7,3 +7,4 @@ #pragma once #define DR_REG_MODEM_SYSCON_BASE 0x600A5400 #define DR_REG_MODEM_LPCON_BASE 0x600AD000 +#define DR_REG_I2C_ANA_MST_BASE 0x600AD800 diff --git a/components/soc/esp32h21/register/soc/reg_base.h b/components/soc/esp32h21/register/soc/reg_base.h index 53d78b2799..4e2b14d446 100644 --- a/components/soc/esp32h21/register/soc/reg_base.h +++ b/components/soc/esp32h21/register/soc/reg_base.h @@ -47,7 +47,6 @@ #define DR_REG_TEE_BASE 0x60098000 #define DR_REG_HP_APM_BASE 0x60099000 #define DR_REG_LP_APM0_BASE 0x60099800 -#define DR_REG_I2C_ANA_MST_BASE 0x600AD800 #define DR_REG_PMU_BASE 0x600B0000 #define DR_REG_LP_CLKRST_BASE 0x600B0400 #define DR_REG_LP_TIMER_BASE 0x600B0C00 diff --git a/components/soc/esp32h4/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32h4/include/modem/i2c_ana_mst_reg.h similarity index 99% rename from components/soc/esp32h4/include/soc/i2c_ana_mst_reg.h rename to components/soc/esp32h4/include/modem/i2c_ana_mst_reg.h index a510728422..59048a2df3 100644 --- a/components/soc/esp32h4/include/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32h4/include/modem/i2c_ana_mst_reg.h @@ -7,7 +7,7 @@ #pragma once #include -#include "soc/soc.h" +#include "modem/reg_base.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32h4/include/modem/reg_base.h b/components/soc/esp32h4/include/modem/reg_base.h index b25c048312..f1ece46964 100644 --- a/components/soc/esp32h4/include/modem/reg_base.h +++ b/components/soc/esp32h4/include/modem/reg_base.h @@ -10,3 +10,4 @@ #define DR_REG_MODEM_SYSCON_BASE 0x600C9C00 #define DR_REG_MODEM_LPCON_BASE 0x600CF000 // (DR_REG_MODEM_PWR_BASE + 0x2000) +#define DR_REG_I2C_ANA_MST_BASE 0x600CF800 // (DR_REG_MODEM_PWR_BASE + 0x2800) diff --git a/components/soc/esp32h4/include/soc/reg_base.h b/components/soc/esp32h4/include/soc/reg_base.h index ddc6012af7..657aaf410f 100644 --- a/components/soc/esp32h4/include/soc/reg_base.h +++ b/components/soc/esp32h4/include/soc/reg_base.h @@ -75,7 +75,6 @@ #define DR_REG_LP_WDT_BASE 0x600B5400 #define DR_REG_TOUCH_SENS_BASE 0x600B5800 #define DR_REG_TOUCH_AON_BASE 0x600B5C00 -#define DR_REG_I2C_ANA_MST_BASE 0x600CF800 // (DR_REG_MODEM_PWR_BASE + 0x2800) #define DR_REG_CLINT_M_BASE 0x20000000 // TODO: [ESP32H4] IDF-12303 inherit from verify code, need check diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld index be4afeba32..180e506225 100644 --- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld +++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld @@ -89,7 +89,7 @@ PROVIDE ( LP_TOUCH = 0x50128000 ); PROVIDE ( LP_GPIO = 0x5012A000 ); PROVIDE ( LP_PERI_PMS = 0x5012E000 ); PROVIDE ( HP2LP_PERI_PMS = 0x5012E800 ); -PROVIDE ( I2C_ANA_MST = 0x50124000 ); +PROVIDE ( LP_I2C_ANA_MST = 0x50124000 ); PROVIDE ( LP_ANA_PERI = 0x50113000 ); PROVIDE ( AHB_DMA = 0x50085000 ); PROVIDE ( AXI_DMA = 0x5008a000 ); diff --git a/components/soc/esp32p4/register/hw_ver1/soc/i2c_ana_mst_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/i2c_ana_mst_reg.h deleted file mode 100644 index 06fc137dbb..0000000000 --- a/components/soc/esp32p4/register/hw_ver1/soc/i2c_ana_mst_reg.h +++ /dev/null @@ -1,301 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 OR MIT - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** I2C_ANA_MST_I2C0_CTRL_REG register - * need des - */ -#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) -/** I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU -#define I2C_ANA_MST_I2C0_CTRL_M (I2C_ANA_MST_I2C0_CTRL_V << I2C_ANA_MST_I2C0_CTRL_S) -#define I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU -#define I2C_ANA_MST_I2C0_CTRL_S 0 -/** I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C0_BUSY (BIT(25)) -#define I2C_ANA_MST_I2C0_BUSY_M (I2C_ANA_MST_I2C0_BUSY_V << I2C_ANA_MST_I2C0_BUSY_S) -#define I2C_ANA_MST_I2C0_BUSY_V 0x00000001U -#define I2C_ANA_MST_I2C0_BUSY_S 25 - -/** I2C_ANA_MST_I2C1_CTRL_REG register - * need des - */ -#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) -/** I2C_ANA_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFFU -#define I2C_ANA_MST_I2C1_CTRL_M (I2C_ANA_MST_I2C1_CTRL_V << I2C_ANA_MST_I2C1_CTRL_S) -#define I2C_ANA_MST_I2C1_CTRL_V 0x01FFFFFFU -#define I2C_ANA_MST_I2C1_CTRL_S 0 -/** I2C_ANA_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C1_BUSY (BIT(25)) -#define I2C_ANA_MST_I2C1_BUSY_M (I2C_ANA_MST_I2C1_BUSY_V << I2C_ANA_MST_I2C1_BUSY_S) -#define I2C_ANA_MST_I2C1_BUSY_V 0x00000001U -#define I2C_ANA_MST_I2C1_BUSY_S 25 - -/** I2C_ANA_MST_I2C0_CONF_REG register - * need des - */ -#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) -/** I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU -#define I2C_ANA_MST_I2C0_CONF_M (I2C_ANA_MST_I2C0_CONF_V << I2C_ANA_MST_I2C0_CONF_S) -#define I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU -#define I2C_ANA_MST_I2C0_CONF_S 0 -/** I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C0_STATUS 0x000000FFU -#define I2C_ANA_MST_I2C0_STATUS_M (I2C_ANA_MST_I2C0_STATUS_V << I2C_ANA_MST_I2C0_STATUS_S) -#define I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU -#define I2C_ANA_MST_I2C0_STATUS_S 24 - -/** I2C_ANA_MST_I2C1_CONF_REG register - * need des - */ -#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xc) -/** I2C_ANA_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFFU -#define I2C_ANA_MST_I2C1_CONF_M (I2C_ANA_MST_I2C1_CONF_V << I2C_ANA_MST_I2C1_CONF_S) -#define I2C_ANA_MST_I2C1_CONF_V 0x00FFFFFFU -#define I2C_ANA_MST_I2C1_CONF_S 0 -/** I2C_ANA_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C1_STATUS 0x000000FFU -#define I2C_ANA_MST_I2C1_STATUS_M (I2C_ANA_MST_I2C1_STATUS_V << I2C_ANA_MST_I2C1_STATUS_S) -#define I2C_ANA_MST_I2C1_STATUS_V 0x000000FFU -#define I2C_ANA_MST_I2C1_STATUS_S 24 - -/** I2C_ANA_MST_I2C_BURST_CONF_REG register - * need des - */ -#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) -/** I2C_ANA_MST_I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C_MST_BURST_CTRL 0xFFFFFFFFU -#define I2C_ANA_MST_I2C_MST_BURST_CTRL_M (I2C_ANA_MST_I2C_MST_BURST_CTRL_V << I2C_ANA_MST_I2C_MST_BURST_CTRL_S) -#define I2C_ANA_MST_I2C_MST_BURST_CTRL_V 0xFFFFFFFFU -#define I2C_ANA_MST_I2C_MST_BURST_CTRL_S 0 - -/** I2C_ANA_MST_I2C_BURST_STATUS_REG register - * need des - */ -#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) -/** I2C_ANA_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C_MST_BURST_DONE (BIT(0)) -#define I2C_ANA_MST_I2C_MST_BURST_DONE_M (I2C_ANA_MST_I2C_MST_BURST_DONE_V << I2C_ANA_MST_I2C_MST_BURST_DONE_S) -#define I2C_ANA_MST_I2C_MST_BURST_DONE_V 0x00000001U -#define I2C_ANA_MST_I2C_MST_BURST_DONE_S 0 -/** I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1)) -#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_M (I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S) -#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U -#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S 1 -/** I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2)) -#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_M (I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V << I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S) -#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U -#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S 2 -/** I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W; bitpos: [31:20]; default: 1024; - * need des - */ -#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT 0x00000FFFU -#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_M (I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V << I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S) -#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V 0x00000FFFU -#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S 20 - -/** I2C_ANA_MST_ANA_CONF0_REG register - * need des - */ -#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18) -/** I2C_ANA_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFFU -#define I2C_ANA_MST_ANA_CONF0_M (I2C_ANA_MST_ANA_CONF0_V << I2C_ANA_MST_ANA_CONF0_S) -#define I2C_ANA_MST_ANA_CONF0_V 0x00FFFFFFU -#define I2C_ANA_MST_ANA_CONF0_S 0 -/** I2C_ANA_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define I2C_ANA_MST_ANA_STATUS0 0x000000FFU -#define I2C_ANA_MST_ANA_STATUS0_M (I2C_ANA_MST_ANA_STATUS0_V << I2C_ANA_MST_ANA_STATUS0_S) -#define I2C_ANA_MST_ANA_STATUS0_V 0x000000FFU -#define I2C_ANA_MST_ANA_STATUS0_S 24 - -/** I2C_ANA_MST_ANA_CONF1_REG register - * need des - */ -#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c) -/** I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU -#define I2C_ANA_MST_ANA_CONF1_M (I2C_ANA_MST_ANA_CONF1_V << I2C_ANA_MST_ANA_CONF1_S) -#define I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU -#define I2C_ANA_MST_ANA_CONF1_S 0 -/** I2C_ANA_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define I2C_ANA_MST_ANA_STATUS1 0x000000FFU -#define I2C_ANA_MST_ANA_STATUS1_M (I2C_ANA_MST_ANA_STATUS1_V << I2C_ANA_MST_ANA_STATUS1_S) -#define I2C_ANA_MST_ANA_STATUS1_V 0x000000FFU -#define I2C_ANA_MST_ANA_STATUS1_S 24 - -/** I2C_ANA_MST_ANA_CONF2_REG register - * need des - */ -#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20) -/** I2C_ANA_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFFU -#define I2C_ANA_MST_ANA_CONF2_M (I2C_ANA_MST_ANA_CONF2_V << I2C_ANA_MST_ANA_CONF2_S) -#define I2C_ANA_MST_ANA_CONF2_V 0x00FFFFFFU -#define I2C_ANA_MST_ANA_CONF2_S 0 -/** I2C_ANA_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define I2C_ANA_MST_ANA_STATUS2 0x000000FFU -#define I2C_ANA_MST_ANA_STATUS2_M (I2C_ANA_MST_ANA_STATUS2_V << I2C_ANA_MST_ANA_STATUS2_S) -#define I2C_ANA_MST_ANA_STATUS2_V 0x000000FFU -#define I2C_ANA_MST_ANA_STATUS2_S 24 - -/** I2C_ANA_MST_I2C0_CTRL1_REG register - * need des - */ -#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) -/** I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; - * need des - */ -#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003FU -#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M (I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V << I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S) -#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU -#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 -/** I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; - * need des - */ -#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU -#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M (I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V << I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S) -#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU -#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 - -/** I2C_ANA_MST_I2C1_CTRL1_REG register - * need des - */ -#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) -/** I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; - * need des - */ -#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003FU -#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M (I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V << I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S) -#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU -#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 -/** I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; - * need des - */ -#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU -#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M (I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V << I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S) -#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU -#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 - -/** I2C_ANA_MST_HW_I2C_CTRL_REG register - * need des - */ -#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2c) -/** I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; - * need des - */ -#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU -#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M (I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V << I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S) -#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU -#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 -/** I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; - * need des - */ -#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU -#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M (I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S) -#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU -#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 -/** I2C_ANA_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0; - * need des - */ -#define I2C_ANA_MST_ARBITER_DIS (BIT(11)) -#define I2C_ANA_MST_ARBITER_DIS_M (I2C_ANA_MST_ARBITER_DIS_V << I2C_ANA_MST_ARBITER_DIS_S) -#define I2C_ANA_MST_ARBITER_DIS_V 0x00000001U -#define I2C_ANA_MST_ARBITER_DIS_S 11 - -/** I2C_ANA_MST_NOUSE_REG register - * need des - */ -#define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) -/** I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU -#define I2C_ANA_MST_I2C_MST_NOUSE_M (I2C_ANA_MST_I2C_MST_NOUSE_V << I2C_ANA_MST_I2C_MST_NOUSE_S) -#define I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU -#define I2C_ANA_MST_I2C_MST_NOUSE_S 0 - -/** I2C_ANA_MST_CLK160M_REG register - * need des - */ -#define I2C_ANA_MST_CLK160M_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) -/** I2C_ANA_MST_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0; - * need des - */ -#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M (BIT(0)) -#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_M (I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V << I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S) -#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V 0x00000001U -#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S 0 - -/** I2C_ANA_MST_DATE_REG register - * need des - */ -#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x38) -/** I2C_ANA_MST_DATE : R/W; bitpos: [27:0]; default: 35656448; - * need des - */ -#define I2C_ANA_MST_DATE 0x0FFFFFFFU -#define I2C_ANA_MST_DATE_M (I2C_ANA_MST_DATE_V << I2C_ANA_MST_DATE_S) -#define I2C_ANA_MST_DATE_V 0x0FFFFFFFU -#define I2C_ANA_MST_DATE_S 0 -/** I2C_ANA_MST_I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C_MST_CLK_EN (BIT(28)) -#define I2C_ANA_MST_I2C_MST_CLK_EN_M (I2C_ANA_MST_I2C_MST_CLK_EN_V << I2C_ANA_MST_I2C_MST_CLK_EN_S) -#define I2C_ANA_MST_I2C_MST_CLK_EN_V 0x00000001U -#define I2C_ANA_MST_I2C_MST_CLK_EN_S 28 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver1/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/lp_i2c_ana_mst_reg.h new file mode 100644 index 0000000000..6e90a1c1f4 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver1/soc/lp_i2c_ana_mst_reg.h @@ -0,0 +1,301 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_I2C_ANA_MST_I2C0_CTRL_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0) +/** LP_I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CTRL_M (LP_I2C_ANA_MST_I2C0_CTRL_V << LP_I2C_ANA_MST_I2C0_CTRL_S) +#define LP_I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CTRL_S 0 +/** LP_I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C0_BUSY (BIT(25)) +#define LP_I2C_ANA_MST_I2C0_BUSY_M (LP_I2C_ANA_MST_I2C0_BUSY_V << LP_I2C_ANA_MST_I2C0_BUSY_S) +#define LP_I2C_ANA_MST_I2C0_BUSY_V 0x00000001U +#define LP_I2C_ANA_MST_I2C0_BUSY_S 25 + +/** LP_I2C_ANA_MST_I2C1_CTRL_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x4) +/** LP_I2C_ANA_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C1_CTRL 0x01FFFFFFU +#define LP_I2C_ANA_MST_I2C1_CTRL_M (LP_I2C_ANA_MST_I2C1_CTRL_V << LP_I2C_ANA_MST_I2C1_CTRL_S) +#define LP_I2C_ANA_MST_I2C1_CTRL_V 0x01FFFFFFU +#define LP_I2C_ANA_MST_I2C1_CTRL_S 0 +/** LP_I2C_ANA_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C1_BUSY (BIT(25)) +#define LP_I2C_ANA_MST_I2C1_BUSY_M (LP_I2C_ANA_MST_I2C1_BUSY_V << LP_I2C_ANA_MST_I2C1_BUSY_S) +#define LP_I2C_ANA_MST_I2C1_BUSY_V 0x00000001U +#define LP_I2C_ANA_MST_I2C1_BUSY_S 25 + +/** LP_I2C_ANA_MST_I2C0_CONF_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C0_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x8) +/** LP_I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CONF_M (LP_I2C_ANA_MST_I2C0_CONF_V << LP_I2C_ANA_MST_I2C0_CONF_S) +#define LP_I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CONF_S 0 +/** LP_I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C0_STATUS 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_STATUS_M (LP_I2C_ANA_MST_I2C0_STATUS_V << LP_I2C_ANA_MST_I2C0_STATUS_S) +#define LP_I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_STATUS_S 24 + +/** LP_I2C_ANA_MST_I2C1_CONF_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C1_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0xc) +/** LP_I2C_ANA_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C1_CONF 0x00FFFFFFU +#define LP_I2C_ANA_MST_I2C1_CONF_M (LP_I2C_ANA_MST_I2C1_CONF_V << LP_I2C_ANA_MST_I2C1_CONF_S) +#define LP_I2C_ANA_MST_I2C1_CONF_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_I2C1_CONF_S 0 +/** LP_I2C_ANA_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C1_STATUS 0x000000FFU +#define LP_I2C_ANA_MST_I2C1_STATUS_M (LP_I2C_ANA_MST_I2C1_STATUS_V << LP_I2C_ANA_MST_I2C1_STATUS_S) +#define LP_I2C_ANA_MST_I2C1_STATUS_V 0x000000FFU +#define LP_I2C_ANA_MST_I2C1_STATUS_S 24 + +/** LP_I2C_ANA_MST_I2C_BURST_CONF_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x10) +/** LP_I2C_ANA_MST_I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST_BURST_CTRL 0xFFFFFFFFU +#define LP_I2C_ANA_MST_I2C_MST_BURST_CTRL_M (LP_I2C_ANA_MST_I2C_MST_BURST_CTRL_V << LP_I2C_ANA_MST_I2C_MST_BURST_CTRL_S) +#define LP_I2C_ANA_MST_I2C_MST_BURST_CTRL_V 0xFFFFFFFFU +#define LP_I2C_ANA_MST_I2C_MST_BURST_CTRL_S 0 + +/** LP_I2C_ANA_MST_I2C_BURST_STATUS_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x14) +/** LP_I2C_ANA_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST_BURST_DONE (BIT(0)) +#define LP_I2C_ANA_MST_I2C_MST_BURST_DONE_M (LP_I2C_ANA_MST_I2C_MST_BURST_DONE_V << LP_I2C_ANA_MST_I2C_MST_BURST_DONE_S) +#define LP_I2C_ANA_MST_I2C_MST_BURST_DONE_V 0x00000001U +#define LP_I2C_ANA_MST_I2C_MST_BURST_DONE_S 0 +/** LP_I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1)) +#define LP_I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_M (LP_I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V << LP_I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S) +#define LP_I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U +#define LP_I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S 1 +/** LP_I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2)) +#define LP_I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_M (LP_I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V << LP_I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S) +#define LP_I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U +#define LP_I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S 2 +/** LP_I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W; bitpos: [31:20]; default: 1024; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT 0x00000FFFU +#define LP_I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_M (LP_I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V << LP_I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S) +#define LP_I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V 0x00000FFFU +#define LP_I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S 20 + +/** LP_I2C_ANA_MST_ANA_CONF0_REG register + * need des + */ +#define LP_I2C_ANA_MST_ANA_CONF0_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x18) +/** LP_I2C_ANA_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_ANA_CONF0 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF0_M (LP_I2C_ANA_MST_ANA_CONF0_V << LP_I2C_ANA_MST_ANA_CONF0_S) +#define LP_I2C_ANA_MST_ANA_CONF0_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF0_S 0 +/** LP_I2C_ANA_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_ANA_STATUS0 0x000000FFU +#define LP_I2C_ANA_MST_ANA_STATUS0_M (LP_I2C_ANA_MST_ANA_STATUS0_V << LP_I2C_ANA_MST_ANA_STATUS0_S) +#define LP_I2C_ANA_MST_ANA_STATUS0_V 0x000000FFU +#define LP_I2C_ANA_MST_ANA_STATUS0_S 24 + +/** LP_I2C_ANA_MST_ANA_CONF1_REG register + * need des + */ +#define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x1c) +/** LP_I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF1_M (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S) +#define LP_I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF1_S 0 +/** LP_I2C_ANA_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_ANA_STATUS1 0x000000FFU +#define LP_I2C_ANA_MST_ANA_STATUS1_M (LP_I2C_ANA_MST_ANA_STATUS1_V << LP_I2C_ANA_MST_ANA_STATUS1_S) +#define LP_I2C_ANA_MST_ANA_STATUS1_V 0x000000FFU +#define LP_I2C_ANA_MST_ANA_STATUS1_S 24 + +/** LP_I2C_ANA_MST_ANA_CONF2_REG register + * need des + */ +#define LP_I2C_ANA_MST_ANA_CONF2_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x20) +/** LP_I2C_ANA_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_ANA_CONF2 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF2_M (LP_I2C_ANA_MST_ANA_CONF2_V << LP_I2C_ANA_MST_ANA_CONF2_S) +#define LP_I2C_ANA_MST_ANA_CONF2_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF2_S 0 +/** LP_I2C_ANA_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_ANA_STATUS2 0x000000FFU +#define LP_I2C_ANA_MST_ANA_STATUS2_M (LP_I2C_ANA_MST_ANA_STATUS2_V << LP_I2C_ANA_MST_ANA_STATUS2_S) +#define LP_I2C_ANA_MST_ANA_STATUS2_V 0x000000FFU +#define LP_I2C_ANA_MST_ANA_STATUS2_S 24 + +/** LP_I2C_ANA_MST_I2C0_CTRL1_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x24) +/** LP_I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; + * need des + */ +#define LP_I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003FU +#define LP_I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M (LP_I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V << LP_I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S) +#define LP_I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU +#define LP_I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 +/** LP_I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; + * need des + */ +#define LP_I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU +#define LP_I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M (LP_I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V << LP_I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S) +#define LP_I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU +#define LP_I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 + +/** LP_I2C_ANA_MST_I2C1_CTRL1_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x28) +/** LP_I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; + * need des + */ +#define LP_I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003FU +#define LP_I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M (LP_I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V << LP_I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S) +#define LP_I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU +#define LP_I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 +/** LP_I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; + * need des + */ +#define LP_I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU +#define LP_I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M (LP_I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V << LP_I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S) +#define LP_I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU +#define LP_I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 + +/** LP_I2C_ANA_MST_HW_I2C_CTRL_REG register + * need des + */ +#define LP_I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x2c) +/** LP_I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; + * need des + */ +#define LP_I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU +#define LP_I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M (LP_I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V << LP_I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S) +#define LP_I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU +#define LP_I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 +/** LP_I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; + * need des + */ +#define LP_I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU +#define LP_I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M (LP_I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V << LP_I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S) +#define LP_I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU +#define LP_I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 +/** LP_I2C_ANA_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_ARBITER_DIS (BIT(11)) +#define LP_I2C_ANA_MST_ARBITER_DIS_M (LP_I2C_ANA_MST_ARBITER_DIS_V << LP_I2C_ANA_MST_ARBITER_DIS_S) +#define LP_I2C_ANA_MST_ARBITER_DIS_V 0x00000001U +#define LP_I2C_ANA_MST_ARBITER_DIS_S 11 + +/** LP_I2C_ANA_MST_NOUSE_REG register + * need des + */ +#define LP_I2C_ANA_MST_NOUSE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x30) +/** LP_I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_M (LP_I2C_ANA_MST_I2C_MST_NOUSE_V << LP_I2C_ANA_MST_I2C_MST_NOUSE_S) +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_S 0 + +/** LP_I2C_ANA_MST_CLK160M_REG register + * need des + */ +#define LP_I2C_ANA_MST_CLK160M_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x34) +/** LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M (BIT(0)) +#define LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_M (LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V << LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S) +#define LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V 0x00000001U +#define LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S 0 + +/** LP_I2C_ANA_MST_DATE_REG register + * need des + */ +#define LP_I2C_ANA_MST_DATE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x38) +/** LP_I2C_ANA_MST_DATE : R/W; bitpos: [27:0]; default: 35656448; + * need des + */ +#define LP_I2C_ANA_MST_DATE 0x0FFFFFFFU +#define LP_I2C_ANA_MST_DATE_M (LP_I2C_ANA_MST_DATE_V << LP_I2C_ANA_MST_DATE_S) +#define LP_I2C_ANA_MST_DATE_V 0x0FFFFFFFU +#define LP_I2C_ANA_MST_DATE_S 0 +/** LP_I2C_ANA_MST_I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST_CLK_EN (BIT(28)) +#define LP_I2C_ANA_MST_I2C_MST_CLK_EN_M (LP_I2C_ANA_MST_I2C_MST_CLK_EN_V << LP_I2C_ANA_MST_I2C_MST_CLK_EN_S) +#define LP_I2C_ANA_MST_I2C_MST_CLK_EN_V 0x00000001U +#define LP_I2C_ANA_MST_I2C_MST_CLK_EN_S 28 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver1/soc/i2c_ana_mst_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/lp_i2c_ana_mst_struct.h similarity index 79% rename from components/soc/esp32p4/register/hw_ver1/soc/i2c_ana_mst_struct.h rename to components/soc/esp32p4/register/hw_ver1/soc/lp_i2c_ana_mst_struct.h index e1d2d126ab..aff4f23b53 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/i2c_ana_mst_struct.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/lp_i2c_ana_mst_struct.h @@ -27,7 +27,7 @@ typedef union { uint32_t reserved_26:6; }; uint32_t val; -} i2c_ana_mst_i2c0_ctrl_reg_t; +} lp_i2c_ana_mst_i2c0_ctrl_reg_t; /** Type of i2c1_ctrl register * need des @@ -45,7 +45,7 @@ typedef union { uint32_t reserved_26:6; }; uint32_t val; -} i2c_ana_mst_i2c1_ctrl_reg_t; +} lp_i2c_ana_mst_i2c1_ctrl_reg_t; /** Type of i2c0_conf register * need des @@ -62,7 +62,7 @@ typedef union { uint32_t i2c0_status:8; }; uint32_t val; -} i2c_ana_mst_i2c0_conf_reg_t; +} lp_i2c_ana_mst_i2c0_conf_reg_t; /** Type of i2c1_conf register * need des @@ -79,7 +79,7 @@ typedef union { uint32_t i2c1_status:8; }; uint32_t val; -} i2c_ana_mst_i2c1_conf_reg_t; +} lp_i2c_ana_mst_i2c1_conf_reg_t; /** Type of i2c_burst_conf register * need des @@ -92,7 +92,7 @@ typedef union { uint32_t i2c_mst_burst_ctrl:32; }; uint32_t val; -} i2c_ana_mst_i2c_burst_conf_reg_t; +} lp_i2c_ana_mst_i2c_burst_conf_reg_t; /** Type of i2c_burst_status register * need des @@ -118,7 +118,7 @@ typedef union { uint32_t i2c_mst_burst_timeout_cnt:12; }; uint32_t val; -} i2c_ana_mst_i2c_burst_status_reg_t; +} lp_i2c_ana_mst_i2c_burst_status_reg_t; /** Type of ana_conf0 register * need des @@ -135,7 +135,7 @@ typedef union { uint32_t ana_status0:8; }; uint32_t val; -} i2c_ana_mst_ana_conf0_reg_t; +} lp_i2c_ana_mst_ana_conf0_reg_t; /** Type of ana_conf1 register * need des @@ -152,7 +152,7 @@ typedef union { uint32_t ana_status1:8; }; uint32_t val; -} i2c_ana_mst_ana_conf1_reg_t; +} lp_i2c_ana_mst_ana_conf1_reg_t; /** Type of ana_conf2 register * need des @@ -169,7 +169,7 @@ typedef union { uint32_t ana_status2:8; }; uint32_t val; -} i2c_ana_mst_ana_conf2_reg_t; +} lp_i2c_ana_mst_ana_conf2_reg_t; /** Type of i2c0_ctrl1 register * need des @@ -187,7 +187,7 @@ typedef union { uint32_t reserved_11:21; }; uint32_t val; -} i2c_ana_mst_i2c0_ctrl1_reg_t; +} lp_i2c_ana_mst_i2c0_ctrl1_reg_t; /** Type of i2c1_ctrl1 register * need des @@ -205,7 +205,7 @@ typedef union { uint32_t reserved_11:21; }; uint32_t val; -} i2c_ana_mst_i2c1_ctrl1_reg_t; +} lp_i2c_ana_mst_i2c1_ctrl1_reg_t; /** Type of hw_i2c_ctrl register * need des @@ -227,7 +227,7 @@ typedef union { uint32_t reserved_12:20; }; uint32_t val; -} i2c_ana_mst_hw_i2c_ctrl_reg_t; +} lp_i2c_ana_mst_hw_i2c_ctrl_reg_t; /** Type of nouse register * need des @@ -240,7 +240,7 @@ typedef union { uint32_t i2c_mst_nouse:32; }; uint32_t val; -} i2c_ana_mst_nouse_reg_t; +} lp_i2c_ana_mst_nouse_reg_t; /** Type of clk160m register * need des @@ -254,7 +254,7 @@ typedef union { uint32_t reserved_1:31; }; uint32_t val; -} i2c_ana_mst_clk160m_reg_t; +} lp_i2c_ana_mst_clk160m_reg_t; /** Type of date register * need des @@ -272,31 +272,31 @@ typedef union { uint32_t reserved_29:3; }; uint32_t val; -} i2c_ana_mst_date_reg_t; +} lp_i2c_ana_mst_date_reg_t; -typedef struct i2c_ana_mst_dev_t { - volatile i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl; - volatile i2c_ana_mst_i2c1_ctrl_reg_t i2c1_ctrl; - volatile i2c_ana_mst_i2c0_conf_reg_t i2c0_conf; - volatile i2c_ana_mst_i2c1_conf_reg_t i2c1_conf; - volatile i2c_ana_mst_i2c_burst_conf_reg_t i2c_burst_conf; - volatile i2c_ana_mst_i2c_burst_status_reg_t i2c_burst_status; - volatile i2c_ana_mst_ana_conf0_reg_t ana_conf0; - volatile i2c_ana_mst_ana_conf1_reg_t ana_conf1; - volatile i2c_ana_mst_ana_conf2_reg_t ana_conf2; - volatile i2c_ana_mst_i2c0_ctrl1_reg_t i2c0_ctrl1; - volatile i2c_ana_mst_i2c1_ctrl1_reg_t i2c1_ctrl1; - volatile i2c_ana_mst_hw_i2c_ctrl_reg_t hw_i2c_ctrl; - volatile i2c_ana_mst_nouse_reg_t nouse; - volatile i2c_ana_mst_clk160m_reg_t clk160m; - volatile i2c_ana_mst_date_reg_t date; -} i2c_ana_mst_dev_t; +typedef struct lp_i2c_ana_mst_dev_t { + volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl; + volatile lp_i2c_ana_mst_i2c1_ctrl_reg_t i2c1_ctrl; + volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf; + volatile lp_i2c_ana_mst_i2c1_conf_reg_t i2c1_conf; + volatile lp_i2c_ana_mst_i2c_burst_conf_reg_t i2c_burst_conf; + volatile lp_i2c_ana_mst_i2c_burst_status_reg_t i2c_burst_status; + volatile lp_i2c_ana_mst_ana_conf0_reg_t ana_conf0; + volatile lp_i2c_ana_mst_ana_conf1_reg_t ana_conf1; + volatile lp_i2c_ana_mst_ana_conf2_reg_t ana_conf2; + volatile lp_i2c_ana_mst_i2c0_ctrl1_reg_t i2c0_ctrl1; + volatile lp_i2c_ana_mst_i2c1_ctrl1_reg_t i2c1_ctrl1; + volatile lp_i2c_ana_mst_hw_i2c_ctrl_reg_t hw_i2c_ctrl; + volatile lp_i2c_ana_mst_nouse_reg_t nouse; + volatile lp_i2c_ana_mst_clk160m_reg_t clk160m; + volatile lp_i2c_ana_mst_date_reg_t date; +} lp_i2c_ana_mst_dev_t; -extern i2c_ana_mst_dev_t I2C_ANA_MST; +extern lp_i2c_ana_mst_dev_t LP_I2C_ANA_MST; #ifndef __cplusplus -_Static_assert(sizeof(i2c_ana_mst_dev_t) == 0x3c, "Invalid size of i2c_ana_mst_dev_t structure"); +_Static_assert(sizeof(lp_i2c_ana_mst_dev_t) == 0x3c, "Invalid size of lp_i2c_ana_mst_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver1/soc/reg_base.h b/components/soc/esp32p4/register/hw_ver1/soc/reg_base.h index 38d6649b7e..062019b55f 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/reg_base.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/reg_base.h @@ -149,7 +149,7 @@ #define DR_REG_LP_UART_BASE (DR_REG_LPPERIPH_BASE + 0x1000) #define DR_REG_LP_I2C_BASE (DR_REG_LPPERIPH_BASE + 0x2000) #define DR_REG_LP_SPI_BASE (DR_REG_LPPERIPH_BASE + 0x3000) -#define DR_REG_I2C_ANA_MST_BASE (DR_REG_LPPERIPH_BASE + 0x4000) +#define DR_REG_LP_I2C_ANA_MST_BASE (DR_REG_LPPERIPH_BASE + 0x4000) #define DR_REG_LP_I2S_BASE (DR_REG_LPPERIPH_BASE + 0x5000) #define DR_REG_LP_ADC_BASE (DR_REG_LPPERIPH_BASE + 0x7000) #define DR_REG_LP_TOUCH_BASE (DR_REG_LPPERIPH_BASE + 0x8000) diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i2c_ana_mst_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/i2c_ana_mst_reg.h deleted file mode 100644 index 2a76fabcfb..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/i2c_ana_mst_reg.h +++ /dev/null @@ -1,301 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 OR MIT - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** I2C_ANA_MST_I2C0_CTRL_REG register - * need des - */ -#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) -/** I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU -#define I2C_ANA_MST_I2C0_CTRL_M (I2C_ANA_MST_I2C0_CTRL_V << I2C_ANA_MST_I2C0_CTRL_S) -#define I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU -#define I2C_ANA_MST_I2C0_CTRL_S 0 -/** I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C0_BUSY (BIT(25)) -#define I2C_ANA_MST_I2C0_BUSY_M (I2C_ANA_MST_I2C0_BUSY_V << I2C_ANA_MST_I2C0_BUSY_S) -#define I2C_ANA_MST_I2C0_BUSY_V 0x00000001U -#define I2C_ANA_MST_I2C0_BUSY_S 25 - -/** I2C_ANA_MST_I2C1_CTRL_REG register - * need des - */ -#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) -/** I2C_ANA_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFFU -#define I2C_ANA_MST_I2C1_CTRL_M (I2C_ANA_MST_I2C1_CTRL_V << I2C_ANA_MST_I2C1_CTRL_S) -#define I2C_ANA_MST_I2C1_CTRL_V 0x01FFFFFFU -#define I2C_ANA_MST_I2C1_CTRL_S 0 -/** I2C_ANA_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C1_BUSY (BIT(25)) -#define I2C_ANA_MST_I2C1_BUSY_M (I2C_ANA_MST_I2C1_BUSY_V << I2C_ANA_MST_I2C1_BUSY_S) -#define I2C_ANA_MST_I2C1_BUSY_V 0x00000001U -#define I2C_ANA_MST_I2C1_BUSY_S 25 - -/** I2C_ANA_MST_I2C0_CONF_REG register - * need des - */ -#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) -/** I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU -#define I2C_ANA_MST_I2C0_CONF_M (I2C_ANA_MST_I2C0_CONF_V << I2C_ANA_MST_I2C0_CONF_S) -#define I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU -#define I2C_ANA_MST_I2C0_CONF_S 0 -/** I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C0_STATUS 0x000000FFU -#define I2C_ANA_MST_I2C0_STATUS_M (I2C_ANA_MST_I2C0_STATUS_V << I2C_ANA_MST_I2C0_STATUS_S) -#define I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU -#define I2C_ANA_MST_I2C0_STATUS_S 24 - -/** I2C_ANA_MST_I2C1_CONF_REG register - * need des - */ -#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xc) -/** I2C_ANA_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFFU -#define I2C_ANA_MST_I2C1_CONF_M (I2C_ANA_MST_I2C1_CONF_V << I2C_ANA_MST_I2C1_CONF_S) -#define I2C_ANA_MST_I2C1_CONF_V 0x00FFFFFFU -#define I2C_ANA_MST_I2C1_CONF_S 0 -/** I2C_ANA_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C1_STATUS 0x000000FFU -#define I2C_ANA_MST_I2C1_STATUS_M (I2C_ANA_MST_I2C1_STATUS_V << I2C_ANA_MST_I2C1_STATUS_S) -#define I2C_ANA_MST_I2C1_STATUS_V 0x000000FFU -#define I2C_ANA_MST_I2C1_STATUS_S 24 - -/** I2C_ANA_MST_I2C_BURST_CONF_REG register - * need des - */ -#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) -/** I2C_ANA_MST_I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C_MST_BURST_CTRL 0xFFFFFFFFU -#define I2C_ANA_MST_I2C_MST_BURST_CTRL_M (I2C_ANA_MST_I2C_MST_BURST_CTRL_V << I2C_ANA_MST_I2C_MST_BURST_CTRL_S) -#define I2C_ANA_MST_I2C_MST_BURST_CTRL_V 0xFFFFFFFFU -#define I2C_ANA_MST_I2C_MST_BURST_CTRL_S 0 - -/** I2C_ANA_MST_I2C_BURST_STATUS_REG register - * need des - */ -#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) -/** I2C_ANA_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C_MST_BURST_DONE (BIT(0)) -#define I2C_ANA_MST_I2C_MST_BURST_DONE_M (I2C_ANA_MST_I2C_MST_BURST_DONE_V << I2C_ANA_MST_I2C_MST_BURST_DONE_S) -#define I2C_ANA_MST_I2C_MST_BURST_DONE_V 0x00000001U -#define I2C_ANA_MST_I2C_MST_BURST_DONE_S 0 -/** I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1)) -#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_M (I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S) -#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U -#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S 1 -/** I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2)) -#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_M (I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V << I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S) -#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U -#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S 2 -/** I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W; bitpos: [31:20]; default: 1024; - * need des - */ -#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT 0x00000FFFU -#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_M (I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V << I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S) -#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V 0x00000FFFU -#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S 20 - -/** I2C_ANA_MST_ANA_CONF0_REG register - * need des - */ -#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18) -/** I2C_ANA_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFFU -#define I2C_ANA_MST_ANA_CONF0_M (I2C_ANA_MST_ANA_CONF0_V << I2C_ANA_MST_ANA_CONF0_S) -#define I2C_ANA_MST_ANA_CONF0_V 0x00FFFFFFU -#define I2C_ANA_MST_ANA_CONF0_S 0 -/** I2C_ANA_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define I2C_ANA_MST_ANA_STATUS0 0x000000FFU -#define I2C_ANA_MST_ANA_STATUS0_M (I2C_ANA_MST_ANA_STATUS0_V << I2C_ANA_MST_ANA_STATUS0_S) -#define I2C_ANA_MST_ANA_STATUS0_V 0x000000FFU -#define I2C_ANA_MST_ANA_STATUS0_S 24 - -/** I2C_ANA_MST_ANA_CONF1_REG register - * need des - */ -#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c) -/** I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU -#define I2C_ANA_MST_ANA_CONF1_M (I2C_ANA_MST_ANA_CONF1_V << I2C_ANA_MST_ANA_CONF1_S) -#define I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU -#define I2C_ANA_MST_ANA_CONF1_S 0 -/** I2C_ANA_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define I2C_ANA_MST_ANA_STATUS1 0x000000FFU -#define I2C_ANA_MST_ANA_STATUS1_M (I2C_ANA_MST_ANA_STATUS1_V << I2C_ANA_MST_ANA_STATUS1_S) -#define I2C_ANA_MST_ANA_STATUS1_V 0x000000FFU -#define I2C_ANA_MST_ANA_STATUS1_S 24 - -/** I2C_ANA_MST_ANA_CONF2_REG register - * need des - */ -#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20) -/** I2C_ANA_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFFU -#define I2C_ANA_MST_ANA_CONF2_M (I2C_ANA_MST_ANA_CONF2_V << I2C_ANA_MST_ANA_CONF2_S) -#define I2C_ANA_MST_ANA_CONF2_V 0x00FFFFFFU -#define I2C_ANA_MST_ANA_CONF2_S 0 -/** I2C_ANA_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define I2C_ANA_MST_ANA_STATUS2 0x000000FFU -#define I2C_ANA_MST_ANA_STATUS2_M (I2C_ANA_MST_ANA_STATUS2_V << I2C_ANA_MST_ANA_STATUS2_S) -#define I2C_ANA_MST_ANA_STATUS2_V 0x000000FFU -#define I2C_ANA_MST_ANA_STATUS2_S 24 - -/** I2C_ANA_MST_I2C0_CTRL1_REG register - * need des - */ -#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) -/** I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; - * need des - */ -#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003FU -#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M (I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V << I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S) -#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU -#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 -/** I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; - * need des - */ -#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU -#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M (I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V << I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S) -#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU -#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 - -/** I2C_ANA_MST_I2C1_CTRL1_REG register - * need des - */ -#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) -/** I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; - * need des - */ -#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003FU -#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M (I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V << I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S) -#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU -#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 -/** I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; - * need des - */ -#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU -#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M (I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V << I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S) -#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU -#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 - -/** I2C_ANA_MST_HW_I2C_CTRL_REG register - * need des - */ -#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2c) -/** I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; - * need des - */ -#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU -#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M (I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V << I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S) -#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU -#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 -/** I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; - * need des - */ -#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU -#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M (I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S) -#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU -#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 -/** I2C_ANA_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0; - * need des - */ -#define I2C_ANA_MST_ARBITER_DIS (BIT(11)) -#define I2C_ANA_MST_ARBITER_DIS_M (I2C_ANA_MST_ARBITER_DIS_V << I2C_ANA_MST_ARBITER_DIS_S) -#define I2C_ANA_MST_ARBITER_DIS_V 0x00000001U -#define I2C_ANA_MST_ARBITER_DIS_S 11 - -/** I2C_ANA_MST_NOUSE_REG register - * need des - */ -#define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) -/** I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU -#define I2C_ANA_MST_I2C_MST_NOUSE_M (I2C_ANA_MST_I2C_MST_NOUSE_V << I2C_ANA_MST_I2C_MST_NOUSE_S) -#define I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU -#define I2C_ANA_MST_I2C_MST_NOUSE_S 0 - -/** I2C_ANA_MST_CLK160M_REG register - * need des - */ -#define I2C_ANA_MST_CLK160M_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) -/** I2C_ANA_MST_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0; - * need des - */ -#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M (BIT(0)) -#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_M (I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V << I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S) -#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V 0x00000001U -#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S 0 - -/** I2C_ANA_MST_DATE_REG register - * need des - */ -#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x38) -/** I2C_ANA_MST_DATE : R/W; bitpos: [27:0]; default: 36717104; - * need des - */ -#define I2C_ANA_MST_DATE 0x0FFFFFFFU -#define I2C_ANA_MST_DATE_M (I2C_ANA_MST_DATE_V << I2C_ANA_MST_DATE_S) -#define I2C_ANA_MST_DATE_V 0x0FFFFFFFU -#define I2C_ANA_MST_DATE_S 0 -/** I2C_ANA_MST_I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0; - * need des - */ -#define I2C_ANA_MST_I2C_MST_CLK_EN (BIT(28)) -#define I2C_ANA_MST_I2C_MST_CLK_EN_M (I2C_ANA_MST_I2C_MST_CLK_EN_V << I2C_ANA_MST_I2C_MST_CLK_EN_S) -#define I2C_ANA_MST_I2C_MST_CLK_EN_V 0x00000001U -#define I2C_ANA_MST_I2C_MST_CLK_EN_S 28 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_ana_mst_reg.h new file mode 100644 index 0000000000..ec981e4375 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_ana_mst_reg.h @@ -0,0 +1,301 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_I2C_ANA_MST_I2C0_CTRL_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0) +/** LP_I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CTRL_M (LP_I2C_ANA_MST_I2C0_CTRL_V << LP_I2C_ANA_MST_I2C0_CTRL_S) +#define LP_I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CTRL_S 0 +/** LP_I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C0_BUSY (BIT(25)) +#define LP_I2C_ANA_MST_I2C0_BUSY_M (LP_I2C_ANA_MST_I2C0_BUSY_V << LP_I2C_ANA_MST_I2C0_BUSY_S) +#define LP_I2C_ANA_MST_I2C0_BUSY_V 0x00000001U +#define LP_I2C_ANA_MST_I2C0_BUSY_S 25 + +/** LP_I2C_ANA_MST_I2C1_CTRL_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x4) +/** LP_I2C_ANA_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C1_CTRL 0x01FFFFFFU +#define LP_I2C_ANA_MST_I2C1_CTRL_M (LP_I2C_ANA_MST_I2C1_CTRL_V << LP_I2C_ANA_MST_I2C1_CTRL_S) +#define LP_I2C_ANA_MST_I2C1_CTRL_V 0x01FFFFFFU +#define LP_I2C_ANA_MST_I2C1_CTRL_S 0 +/** LP_I2C_ANA_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C1_BUSY (BIT(25)) +#define LP_I2C_ANA_MST_I2C1_BUSY_M (LP_I2C_ANA_MST_I2C1_BUSY_V << LP_I2C_ANA_MST_I2C1_BUSY_S) +#define LP_I2C_ANA_MST_I2C1_BUSY_V 0x00000001U +#define LP_I2C_ANA_MST_I2C1_BUSY_S 25 + +/** LP_I2C_ANA_MST_I2C0_CONF_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C0_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x8) +/** LP_I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CONF_M (LP_I2C_ANA_MST_I2C0_CONF_V << LP_I2C_ANA_MST_I2C0_CONF_S) +#define LP_I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CONF_S 0 +/** LP_I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C0_STATUS 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_STATUS_M (LP_I2C_ANA_MST_I2C0_STATUS_V << LP_I2C_ANA_MST_I2C0_STATUS_S) +#define LP_I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_STATUS_S 24 + +/** LP_I2C_ANA_MST_I2C1_CONF_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C1_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0xc) +/** LP_I2C_ANA_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C1_CONF 0x00FFFFFFU +#define LP_I2C_ANA_MST_I2C1_CONF_M (LP_I2C_ANA_MST_I2C1_CONF_V << LP_I2C_ANA_MST_I2C1_CONF_S) +#define LP_I2C_ANA_MST_I2C1_CONF_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_I2C1_CONF_S 0 +/** LP_I2C_ANA_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C1_STATUS 0x000000FFU +#define LP_I2C_ANA_MST_I2C1_STATUS_M (LP_I2C_ANA_MST_I2C1_STATUS_V << LP_I2C_ANA_MST_I2C1_STATUS_S) +#define LP_I2C_ANA_MST_I2C1_STATUS_V 0x000000FFU +#define LP_I2C_ANA_MST_I2C1_STATUS_S 24 + +/** LP_I2C_ANA_MST_I2C_BURST_CONF_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x10) +/** LP_I2C_ANA_MST_I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST_BURST_CTRL 0xFFFFFFFFU +#define LP_I2C_ANA_MST_I2C_MST_BURST_CTRL_M (LP_I2C_ANA_MST_I2C_MST_BURST_CTRL_V << LP_I2C_ANA_MST_I2C_MST_BURST_CTRL_S) +#define LP_I2C_ANA_MST_I2C_MST_BURST_CTRL_V 0xFFFFFFFFU +#define LP_I2C_ANA_MST_I2C_MST_BURST_CTRL_S 0 + +/** LP_I2C_ANA_MST_I2C_BURST_STATUS_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x14) +/** LP_I2C_ANA_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST_BURST_DONE (BIT(0)) +#define LP_I2C_ANA_MST_I2C_MST_BURST_DONE_M (LP_I2C_ANA_MST_I2C_MST_BURST_DONE_V << LP_I2C_ANA_MST_I2C_MST_BURST_DONE_S) +#define LP_I2C_ANA_MST_I2C_MST_BURST_DONE_V 0x00000001U +#define LP_I2C_ANA_MST_I2C_MST_BURST_DONE_S 0 +/** LP_I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1)) +#define LP_I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_M (LP_I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V << LP_I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S) +#define LP_I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U +#define LP_I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S 1 +/** LP_I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2)) +#define LP_I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_M (LP_I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V << LP_I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S) +#define LP_I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U +#define LP_I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S 2 +/** LP_I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W; bitpos: [31:20]; default: 1024; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT 0x00000FFFU +#define LP_I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_M (LP_I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V << LP_I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S) +#define LP_I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V 0x00000FFFU +#define LP_I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S 20 + +/** LP_I2C_ANA_MST_ANA_CONF0_REG register + * need des + */ +#define LP_I2C_ANA_MST_ANA_CONF0_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x18) +/** LP_I2C_ANA_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_ANA_CONF0 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF0_M (LP_I2C_ANA_MST_ANA_CONF0_V << LP_I2C_ANA_MST_ANA_CONF0_S) +#define LP_I2C_ANA_MST_ANA_CONF0_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF0_S 0 +/** LP_I2C_ANA_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_ANA_STATUS0 0x000000FFU +#define LP_I2C_ANA_MST_ANA_STATUS0_M (LP_I2C_ANA_MST_ANA_STATUS0_V << LP_I2C_ANA_MST_ANA_STATUS0_S) +#define LP_I2C_ANA_MST_ANA_STATUS0_V 0x000000FFU +#define LP_I2C_ANA_MST_ANA_STATUS0_S 24 + +/** LP_I2C_ANA_MST_ANA_CONF1_REG register + * need des + */ +#define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x1c) +/** LP_I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF1_M (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S) +#define LP_I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF1_S 0 +/** LP_I2C_ANA_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_ANA_STATUS1 0x000000FFU +#define LP_I2C_ANA_MST_ANA_STATUS1_M (LP_I2C_ANA_MST_ANA_STATUS1_V << LP_I2C_ANA_MST_ANA_STATUS1_S) +#define LP_I2C_ANA_MST_ANA_STATUS1_V 0x000000FFU +#define LP_I2C_ANA_MST_ANA_STATUS1_S 24 + +/** LP_I2C_ANA_MST_ANA_CONF2_REG register + * need des + */ +#define LP_I2C_ANA_MST_ANA_CONF2_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x20) +/** LP_I2C_ANA_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_ANA_CONF2 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF2_M (LP_I2C_ANA_MST_ANA_CONF2_V << LP_I2C_ANA_MST_ANA_CONF2_S) +#define LP_I2C_ANA_MST_ANA_CONF2_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF2_S 0 +/** LP_I2C_ANA_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_ANA_STATUS2 0x000000FFU +#define LP_I2C_ANA_MST_ANA_STATUS2_M (LP_I2C_ANA_MST_ANA_STATUS2_V << LP_I2C_ANA_MST_ANA_STATUS2_S) +#define LP_I2C_ANA_MST_ANA_STATUS2_V 0x000000FFU +#define LP_I2C_ANA_MST_ANA_STATUS2_S 24 + +/** LP_I2C_ANA_MST_I2C0_CTRL1_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x24) +/** LP_I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; + * need des + */ +#define LP_I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003FU +#define LP_I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M (LP_I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V << LP_I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S) +#define LP_I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU +#define LP_I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 +/** LP_I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; + * need des + */ +#define LP_I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU +#define LP_I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M (LP_I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V << LP_I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S) +#define LP_I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU +#define LP_I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 + +/** LP_I2C_ANA_MST_I2C1_CTRL1_REG register + * need des + */ +#define LP_I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x28) +/** LP_I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; + * need des + */ +#define LP_I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003FU +#define LP_I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M (LP_I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V << LP_I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S) +#define LP_I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU +#define LP_I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 +/** LP_I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; + * need des + */ +#define LP_I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU +#define LP_I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M (LP_I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V << LP_I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S) +#define LP_I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU +#define LP_I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 + +/** LP_I2C_ANA_MST_HW_I2C_CTRL_REG register + * need des + */ +#define LP_I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x2c) +/** LP_I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; + * need des + */ +#define LP_I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU +#define LP_I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M (LP_I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V << LP_I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S) +#define LP_I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU +#define LP_I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 +/** LP_I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; + * need des + */ +#define LP_I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU +#define LP_I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M (LP_I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V << LP_I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S) +#define LP_I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU +#define LP_I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 +/** LP_I2C_ANA_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_ARBITER_DIS (BIT(11)) +#define LP_I2C_ANA_MST_ARBITER_DIS_M (LP_I2C_ANA_MST_ARBITER_DIS_V << LP_I2C_ANA_MST_ARBITER_DIS_S) +#define LP_I2C_ANA_MST_ARBITER_DIS_V 0x00000001U +#define LP_I2C_ANA_MST_ARBITER_DIS_S 11 + +/** LP_I2C_ANA_MST_NOUSE_REG register + * need des + */ +#define LP_I2C_ANA_MST_NOUSE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x30) +/** LP_I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_M (LP_I2C_ANA_MST_I2C_MST_NOUSE_V << LP_I2C_ANA_MST_I2C_MST_NOUSE_S) +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_S 0 + +/** LP_I2C_ANA_MST_CLK160M_REG register + * need des + */ +#define LP_I2C_ANA_MST_CLK160M_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x34) +/** LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M (BIT(0)) +#define LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_M (LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V << LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S) +#define LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V 0x00000001U +#define LP_I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S 0 + +/** LP_I2C_ANA_MST_DATE_REG register + * need des + */ +#define LP_I2C_ANA_MST_DATE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x38) +/** LP_I2C_ANA_MST_DATE : R/W; bitpos: [27:0]; default: 36717104; + * need des + */ +#define LP_I2C_ANA_MST_DATE 0x0FFFFFFFU +#define LP_I2C_ANA_MST_DATE_M (LP_I2C_ANA_MST_DATE_V << LP_I2C_ANA_MST_DATE_S) +#define LP_I2C_ANA_MST_DATE_V 0x0FFFFFFFU +#define LP_I2C_ANA_MST_DATE_S 0 +/** LP_I2C_ANA_MST_I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST_CLK_EN (BIT(28)) +#define LP_I2C_ANA_MST_I2C_MST_CLK_EN_M (LP_I2C_ANA_MST_I2C_MST_CLK_EN_V << LP_I2C_ANA_MST_I2C_MST_CLK_EN_S) +#define LP_I2C_ANA_MST_I2C_MST_CLK_EN_V 0x00000001U +#define LP_I2C_ANA_MST_I2C_MST_CLK_EN_S 28 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i2c_ana_mst_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_ana_mst_struct.h similarity index 79% rename from components/soc/esp32p4/register/hw_ver3/soc/i2c_ana_mst_struct.h rename to components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_ana_mst_struct.h index 31a3db4c67..fb9625fd37 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/i2c_ana_mst_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_ana_mst_struct.h @@ -27,7 +27,7 @@ typedef union { uint32_t reserved_26:6; }; uint32_t val; -} i2c_ana_mst_i2c0_ctrl_reg_t; +} lp_i2c_ana_mst_i2c0_ctrl_reg_t; /** Type of i2c1_ctrl register * need des @@ -45,7 +45,7 @@ typedef union { uint32_t reserved_26:6; }; uint32_t val; -} i2c_ana_mst_i2c1_ctrl_reg_t; +} lp_i2c_ana_mst_i2c1_ctrl_reg_t; /** Type of i2c0_conf register * need des @@ -62,7 +62,7 @@ typedef union { uint32_t i2c0_status:8; }; uint32_t val; -} i2c_ana_mst_i2c0_conf_reg_t; +} lp_i2c_ana_mst_i2c0_conf_reg_t; /** Type of i2c1_conf register * need des @@ -79,7 +79,7 @@ typedef union { uint32_t i2c1_status:8; }; uint32_t val; -} i2c_ana_mst_i2c1_conf_reg_t; +} lp_i2c_ana_mst_i2c1_conf_reg_t; /** Type of i2c_burst_conf register * need des @@ -92,7 +92,7 @@ typedef union { uint32_t i2c_mst_burst_ctrl:32; }; uint32_t val; -} i2c_ana_mst_i2c_burst_conf_reg_t; +} lp_i2c_ana_mst_i2c_burst_conf_reg_t; /** Type of i2c_burst_status register * need des @@ -118,7 +118,7 @@ typedef union { uint32_t i2c_mst_burst_timeout_cnt:12; }; uint32_t val; -} i2c_ana_mst_i2c_burst_status_reg_t; +} lp_i2c_ana_mst_i2c_burst_status_reg_t; /** Type of ana_conf0 register * need des @@ -135,7 +135,7 @@ typedef union { uint32_t ana_status0:8; }; uint32_t val; -} i2c_ana_mst_ana_conf0_reg_t; +} lp_i2c_ana_mst_ana_conf0_reg_t; /** Type of ana_conf1 register * need des @@ -152,7 +152,7 @@ typedef union { uint32_t ana_status1:8; }; uint32_t val; -} i2c_ana_mst_ana_conf1_reg_t; +} lp_i2c_ana_mst_ana_conf1_reg_t; /** Type of ana_conf2 register * need des @@ -169,7 +169,7 @@ typedef union { uint32_t ana_status2:8; }; uint32_t val; -} i2c_ana_mst_ana_conf2_reg_t; +} lp_i2c_ana_mst_ana_conf2_reg_t; /** Type of i2c0_ctrl1 register * need des @@ -187,7 +187,7 @@ typedef union { uint32_t reserved_11:21; }; uint32_t val; -} i2c_ana_mst_i2c0_ctrl1_reg_t; +} lp_i2c_ana_mst_i2c0_ctrl1_reg_t; /** Type of i2c1_ctrl1 register * need des @@ -205,7 +205,7 @@ typedef union { uint32_t reserved_11:21; }; uint32_t val; -} i2c_ana_mst_i2c1_ctrl1_reg_t; +} lp_i2c_ana_mst_i2c1_ctrl1_reg_t; /** Type of hw_i2c_ctrl register * need des @@ -227,7 +227,7 @@ typedef union { uint32_t reserved_12:20; }; uint32_t val; -} i2c_ana_mst_hw_i2c_ctrl_reg_t; +} lp_i2c_ana_mst_hw_i2c_ctrl_reg_t; /** Type of nouse register * need des @@ -240,7 +240,7 @@ typedef union { uint32_t i2c_mst_nouse:32; }; uint32_t val; -} i2c_ana_mst_nouse_reg_t; +} lp_i2c_ana_mst_nouse_reg_t; /** Type of clk160m register * need des @@ -254,7 +254,7 @@ typedef union { uint32_t reserved_1:31; }; uint32_t val; -} i2c_ana_mst_clk160m_reg_t; +} lp_i2c_ana_mst_clk160m_reg_t; /** Type of date register * need des @@ -272,31 +272,31 @@ typedef union { uint32_t reserved_29:3; }; uint32_t val; -} i2c_ana_mst_date_reg_t; +} lp_i2c_ana_mst_date_reg_t; typedef struct { - volatile i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl; - volatile i2c_ana_mst_i2c1_ctrl_reg_t i2c1_ctrl; - volatile i2c_ana_mst_i2c0_conf_reg_t i2c0_conf; - volatile i2c_ana_mst_i2c1_conf_reg_t i2c1_conf; - volatile i2c_ana_mst_i2c_burst_conf_reg_t i2c_burst_conf; - volatile i2c_ana_mst_i2c_burst_status_reg_t i2c_burst_status; - volatile i2c_ana_mst_ana_conf0_reg_t ana_conf0; - volatile i2c_ana_mst_ana_conf1_reg_t ana_conf1; - volatile i2c_ana_mst_ana_conf2_reg_t ana_conf2; - volatile i2c_ana_mst_i2c0_ctrl1_reg_t i2c0_ctrl1; - volatile i2c_ana_mst_i2c1_ctrl1_reg_t i2c1_ctrl1; - volatile i2c_ana_mst_hw_i2c_ctrl_reg_t hw_i2c_ctrl; - volatile i2c_ana_mst_nouse_reg_t nouse; - volatile i2c_ana_mst_clk160m_reg_t clk160m; - volatile i2c_ana_mst_date_reg_t date; -} i2c_ana_mst_dev_t; + volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl; + volatile lp_i2c_ana_mst_i2c1_ctrl_reg_t i2c1_ctrl; + volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf; + volatile lp_i2c_ana_mst_i2c1_conf_reg_t i2c1_conf; + volatile lp_i2c_ana_mst_i2c_burst_conf_reg_t i2c_burst_conf; + volatile lp_i2c_ana_mst_i2c_burst_status_reg_t i2c_burst_status; + volatile lp_i2c_ana_mst_ana_conf0_reg_t ana_conf0; + volatile lp_i2c_ana_mst_ana_conf1_reg_t ana_conf1; + volatile lp_i2c_ana_mst_ana_conf2_reg_t ana_conf2; + volatile lp_i2c_ana_mst_i2c0_ctrl1_reg_t i2c0_ctrl1; + volatile lp_i2c_ana_mst_i2c1_ctrl1_reg_t i2c1_ctrl1; + volatile lp_i2c_ana_mst_hw_i2c_ctrl_reg_t hw_i2c_ctrl; + volatile lp_i2c_ana_mst_nouse_reg_t nouse; + volatile lp_i2c_ana_mst_clk160m_reg_t clk160m; + volatile lp_i2c_ana_mst_date_reg_t date; +} lp_i2c_ana_mst_dev_t; -extern i2c_ana_mst_dev_t I2C_ANA_MST; +extern lp_i2c_ana_mst_dev_t LP_I2C_ANA_MST; #ifndef __cplusplus -_Static_assert(sizeof(i2c_ana_mst_dev_t) == 0x3c, "Invalid size of i2c_ana_mst_dev_t structure"); +_Static_assert(sizeof(lp_i2c_ana_mst_dev_t) == 0x3c, "Invalid size of lp_i2c_ana_mst_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/reg_base.h b/components/soc/esp32p4/register/hw_ver3/soc/reg_base.h index 7cc8687f63..a7e0950dd0 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/reg_base.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/reg_base.h @@ -149,7 +149,7 @@ #define DR_REG_LP_UART_BASE (DR_REG_LPPERIPH_BASE + 0x1000) #define DR_REG_LP_I2C_BASE (DR_REG_LPPERIPH_BASE + 0x2000) #define DR_REG_LP_SPI_BASE (DR_REG_LPPERIPH_BASE + 0x3000) -#define DR_REG_I2C_ANA_MST_BASE (DR_REG_LPPERIPH_BASE + 0x4000) +#define DR_REG_LP_I2C_ANA_MST_BASE (DR_REG_LPPERIPH_BASE + 0x4000) #define DR_REG_LP_I2S_BASE (DR_REG_LPPERIPH_BASE + 0x5000) #define DR_REG_LP_TRNG_BASE (DR_REG_LPPERIPH_BASE + 0x6000) #define DR_REG_LP_ADC_BASE (DR_REG_LPPERIPH_BASE + 0x7000) diff --git a/components/soc/esp32s2/register/soc/sens_struct.h b/components/soc/esp32s2/register/soc/sens_struct.h index c864c45d5d..1945c8e3dc 100644 --- a/components/soc/esp32s2/register/soc/sens_struct.h +++ b/components/soc/esp32s2/register/soc/sens_struct.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -11,8 +11,8 @@ extern "C" { #endif -typedef volatile struct sens_dev_s { - union { +typedef struct sens_dev_t { + volatile union { struct { uint32_t sar1_clk_div: 8; /*clock divider*/ uint32_t reserved8: 10; @@ -25,8 +25,8 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_reader1_ctrl; - uint32_t sar_reader1_status; /**/ - union { + volatile uint32_t sar_reader1_status; /**/ + volatile union { struct { uint32_t reserved0: 22; uint32_t rtc_saradc_reset: 1; @@ -38,7 +38,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_meas1_ctrl1; - union { + volatile union { struct { uint32_t meas1_data_sar: 16; /*SAR ADC1 data*/ uint32_t meas1_done_sar: 1; /*SAR ADC1 conversion done indication*/ @@ -49,22 +49,22 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_meas1_ctrl2; - union { + volatile union { struct { uint32_t reserved0: 31; uint32_t sar1_dig_force: 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/ }; uint32_t val; } sar_meas1_mux; - uint32_t sar_atten1; /*2-bit attenuation for each pad*/ - union { + volatile uint32_t sar_atten1; /*2-bit attenuation for each pad*/ + volatile union { struct { uint32_t sar_amp_wait1:16; uint32_t sar_amp_wait2:16; }; uint32_t val; } sar_amp_ctrl1; - union { + volatile union { struct { uint32_t sar1_dac_xpd_fsm_idle: 1; uint32_t xpd_sar_amp_fsm_idle: 1; @@ -78,7 +78,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_amp_ctrl2; - union { + volatile union { struct { uint32_t sar1_dac_xpd_fsm: 4; uint32_t xpd_sar_amp_fsm: 4; @@ -91,7 +91,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_amp_ctrl3; - union { + volatile union { struct { uint32_t sar2_clk_div: 8; /*clock divider*/ uint32_t reserved8: 8; @@ -105,8 +105,8 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_reader2_ctrl; - uint32_t sar_reader2_status; /**/ - union { + volatile uint32_t sar_reader2_status; /**/ + volatile union { struct { uint32_t sar2_cntl_state: 3; /*saradc2_cntl_fsm*/ uint32_t sar2_pwdet_cal_en: 1; /*rtc control pwdet enable*/ @@ -119,7 +119,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_meas2_ctrl1; - union { + volatile union { struct { uint32_t meas2_data_sar: 16; /*SAR ADC2 data*/ uint32_t meas2_done_sar: 1; /*SAR ADC2 conversion done indication*/ @@ -130,7 +130,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_meas2_ctrl2; - union { + volatile union { struct { uint32_t reserved0: 28; uint32_t sar2_pwdet_cct: 3; /*SAR2_PWDET_CCT*/ @@ -138,8 +138,8 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_meas2_mux; - uint32_t sar_atten2; /*2-bit attenuation for each pad*/ - union { + volatile uint32_t sar_atten2; /*2-bit attenuation for each pad*/ + volatile union { struct { uint32_t reserved0: 29; uint32_t force_xpd_sar: 2; @@ -147,7 +147,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_power_xpd_sar; - union { + volatile union { struct { uint32_t i2c_slave_addr1: 11; uint32_t i2c_slave_addr0: 11; @@ -156,7 +156,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_slave_addr1; - union { + volatile union { struct { uint32_t i2c_slave_addr3:11; uint32_t i2c_slave_addr2:11; @@ -164,7 +164,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_slave_addr2; - union { + volatile union { struct { uint32_t i2c_slave_addr5:11; uint32_t i2c_slave_addr4:11; @@ -172,7 +172,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_slave_addr3; - union { + volatile union { struct { uint32_t i2c_slave_addr7:11; uint32_t i2c_slave_addr6:11; @@ -180,7 +180,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_slave_addr4; - union { + volatile union { struct { uint32_t tsens_out: 8; /*temperature sensor data out*/ uint32_t tsens_ready: 1; /*indicate temperature sensor out ready*/ @@ -195,7 +195,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_tctrl; - union { + volatile union { struct { uint32_t tsens_xpd_wait: 12; uint32_t tsens_xpd_force: 2; @@ -206,7 +206,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_tctrl2; - union { + volatile union { struct { uint32_t sar_i2c_ctrl: 28; /*I2C control data*/ uint32_t sar_i2c_start: 1; /*start I2C*/ @@ -215,7 +215,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_i2c_ctrl; - union { + volatile union { struct { uint32_t touch_outen: 15; /*touch controller output enable*/ uint32_t touch_status_clr: 1; /*clear all touch active status*/ @@ -228,7 +228,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_touch_conf; - union { + volatile union { struct { uint32_t thresh: 22; /*Finger threshold for touch pad 1*/ uint32_t reserved22: 10; @@ -250,7 +250,7 @@ typedef volatile struct sens_dev_s { uint32_t reserved_c8; uint32_t reserved_cc; uint32_t reserved_d0; - union { + volatile union { struct { uint32_t touch_pad_active: 15; /*touch active status*/ uint32_t touch_channel_clr:15; /*Clear touch channel*/ @@ -259,7 +259,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_touch_chn_st; - union { + volatile union { struct { uint32_t touch_denoise_data:22; /*the counter for touch pad 0*/ uint32_t touch_scan_curr: 4; @@ -267,7 +267,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_touch_status0; - union { + volatile union { struct { uint32_t touch_pad_data: 22; uint32_t reserved22: 7; @@ -275,7 +275,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_touch_status[14]; - union { + volatile union { struct { uint32_t touch_slp_data: 22; uint32_t reserved22: 7; @@ -283,7 +283,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_touch_slp_status; - union { + volatile union { struct { uint32_t touch_approach_pad2_cnt: 8; uint32_t touch_approach_pad1_cnt: 8; @@ -292,7 +292,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_touch_appr_status; - union { + volatile union { struct { uint32_t sw_fstep: 16; /*frequency step for CW generator*/ uint32_t sw_tone_en: 1; /*1: enable CW generator*/ @@ -307,7 +307,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_dac_ctrl1; - union { + volatile union { struct { uint32_t dac_dc1: 8; /*DC offset for DAC1 CW generator*/ uint32_t dac_dc2: 8; /*DC offset for DAC2 CW generator*/ @@ -321,7 +321,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_dac_ctrl2; - union { + volatile union { struct { uint32_t reserved0: 25; uint32_t dbg_trigger: 1; /*trigger cocpu debug registers*/ @@ -334,7 +334,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_cocpu_state; - union { + volatile union { struct { uint32_t touch_done: 1; /*int from touch done*/ uint32_t touch_inactive: 1; /*int from touch inactive*/ @@ -349,7 +349,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_cocpu_int_raw; - union { + volatile union { struct { uint32_t touch_done: 1; uint32_t touch_inactive: 1; @@ -364,7 +364,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_cocpu_int_ena; - union { + volatile union { struct { uint32_t touch_done: 1; uint32_t touch_inactive: 1; @@ -379,7 +379,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_cocpu_int_st; - union { + volatile union { struct { uint32_t touch_done: 1; uint32_t touch_inactive: 1; @@ -394,7 +394,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_cocpu_int_clr; - union { + volatile union { struct { uint32_t pc: 13; /*cocpu Program counter*/ uint32_t mem_vld: 1; /*cocpu mem valid output*/ @@ -404,7 +404,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_cocpu_debug; - union { + volatile union { struct { uint32_t reserved0: 28; uint32_t xpd_hall: 1; /*Power on hall sensor and connect to VP and VN*/ @@ -414,8 +414,8 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_hall_ctrl; - uint32_t sar_nouse; /**/ - union { + volatile uint32_t sar_nouse; /**/ + volatile union { struct { uint32_t reserved0: 30; uint32_t iomux_reset: 1; @@ -423,7 +423,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_io_mux_conf; - union { + volatile union { struct { uint32_t sar_date: 28; uint32_t reserved28: 4; diff --git a/components/soc/esp32s3/register/soc/sens_struct.h b/components/soc/esp32s3/register/soc/sens_struct.h index b2a7bc5ece..9380a12c5a 100644 --- a/components/soc/esp32s3/register/soc/sens_struct.h +++ b/components/soc/esp32s3/register/soc/sens_struct.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -13,8 +13,8 @@ extern "C" { #endif -typedef volatile struct sens_dev_s { - union { +typedef struct sens_dev_t { + volatile union { struct { uint32_t sar1_clk_div : 8; /*clock divider*/ uint32_t reserved8 : 10; @@ -27,8 +27,8 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_reader1_ctrl; - uint32_t sar_reader1_status; - union { + volatile uint32_t sar_reader1_status; + volatile union { struct { uint32_t reserved0 : 24; uint32_t force_xpd_amp : 2; @@ -38,7 +38,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_meas1_ctrl1; - union { + volatile union { struct { uint32_t meas1_data_sar : 16; /*SAR ADC1 data*/ uint32_t meas1_done_sar : 1; /*SAR ADC1 conversion done indication*/ @@ -49,22 +49,22 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_meas1_ctrl2; - union { + volatile union { struct { uint32_t reserved0 : 31; uint32_t sar1_dig_force : 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/ }; uint32_t val; } sar_meas1_mux; - uint32_t sar_atten1; - union { + volatile uint32_t sar_atten1; + volatile union { struct { uint32_t sar_amp_wait1 : 16; uint32_t sar_amp_wait2 : 16; }; uint32_t val; } sar_amp_ctrl1; - union { + volatile union { struct { uint32_t sar1_dac_xpd_fsm_idle : 1; uint32_t xpd_sar_amp_fsm_idle : 1; @@ -78,7 +78,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_amp_ctrl2; - union { + volatile union { struct { uint32_t sar1_dac_xpd_fsm : 4; uint32_t xpd_sar_amp_fsm : 4; @@ -91,7 +91,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_amp_ctrl3; - union { + volatile union { struct { uint32_t sar2_clk_div : 8; /*clock divider*/ uint32_t reserved8 : 8; @@ -105,8 +105,8 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_reader2_ctrl; - uint32_t sar_reader2_status; - union { + volatile uint32_t sar_reader2_status; + volatile union { struct { uint32_t sar2_cntl_state : 3; /*saradc2_cntl_fsm*/ uint32_t sar2_pwdet_cal_en : 1; /*rtc control pwdet enable*/ @@ -119,7 +119,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_meas2_ctrl1; - union { + volatile union { struct { uint32_t meas2_data_sar : 16; /*SAR ADC2 data*/ uint32_t meas2_done_sar : 1; /*SAR ADC2 conversion done indication*/ @@ -130,7 +130,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_meas2_ctrl2; - union { + volatile union { struct { uint32_t reserved0 : 28; uint32_t sar2_pwdet_cct : 3; /*SAR2_PWDET_CCT*/ @@ -138,8 +138,8 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_meas2_mux; - uint32_t sar_atten2; - union { + volatile uint32_t sar_atten2; + volatile union { struct { uint32_t reserved0 : 29; uint32_t force_xpd_sar : 2; @@ -147,7 +147,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_power_xpd_sar; - union { + volatile union { struct { uint32_t i2c_slave_addr1 : 11; uint32_t i2c_slave_addr0 : 11; @@ -156,7 +156,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_slave_addr1; - union { + volatile union { struct { uint32_t i2c_slave_addr3 : 11; uint32_t i2c_slave_addr2 : 11; @@ -164,7 +164,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_slave_addr2; - union { + volatile union { struct { uint32_t i2c_slave_addr5 : 11; uint32_t i2c_slave_addr4 : 11; @@ -172,7 +172,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_slave_addr3; - union { + volatile union { struct { uint32_t i2c_slave_addr7 : 11; uint32_t i2c_slave_addr6 : 11; @@ -180,7 +180,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_slave_addr4; - union { + volatile union { struct { uint32_t tsens_out : 8; /*temperature sensor data out*/ uint32_t tsens_ready : 1; /*indicate temperature sensor out ready*/ @@ -195,7 +195,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_tctrl; - union { + volatile union { struct { uint32_t tsens_xpd_wait : 12; uint32_t tsens_xpd_force : 2; @@ -204,7 +204,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_tctrl2; - union { + volatile union { struct { uint32_t sar_i2c_ctrl : 28; /*I2C control data*/ uint32_t sar_i2c_start : 1; /*start I2C*/ @@ -213,7 +213,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_i2c_ctrl; - union { + volatile union { struct { uint32_t touch_outen : 15; /*touch controller output enable*/ uint32_t touch_status_clr : 1; /*clear all touch active status*/ @@ -226,21 +226,21 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_touch_conf; - union { + volatile union { struct { uint32_t touch_denoise_data : 22; uint32_t reserved22 : 10; }; uint32_t val; } sar_touch_denoise; - union { + volatile union { struct { uint32_t thresh : 22; /*Finger threshold for touch pad 1*/ uint32_t reserved22 : 10; }; uint32_t val; } touch_thresh[14]; - union { + volatile union { struct { uint32_t touch_pad_active : 15; /*touch active status*/ uint32_t touch_channel_clr : 15; /*Clear touch channel*/ @@ -249,7 +249,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_touch_chn_st; - union { + volatile union { struct { uint32_t touch_denoise_data : 22; /*the counter for touch pad 0*/ uint32_t touch_scan_curr : 4; @@ -257,7 +257,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_touch_status0; - union { + volatile union { struct { uint32_t touch_pad_data : 22; uint32_t reserved22 : 7; @@ -265,7 +265,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_touch_status[14]; - union { + volatile union { struct { uint32_t touch_slp_data : 22; uint32_t reserved22 : 7; @@ -273,7 +273,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_touch_slp_status; - union { + volatile union { struct { uint32_t touch_approach_pad2_cnt : 8; uint32_t touch_approach_pad1_cnt : 8; @@ -282,7 +282,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_touch_appr_status; - union { + volatile union { struct { uint32_t reserved0 : 25; uint32_t dbg_trigger : 1; /*trigger cocpu debug registers*/ @@ -295,7 +295,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_cocpu_state; - union { + volatile union { struct { uint32_t touch_done : 1; /*int from touch done*/ uint32_t touch_inactive : 1; /*int from touch inactive*/ @@ -313,7 +313,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_cocpu_int_raw; - union { + volatile union { struct { uint32_t touch_done : 1; uint32_t touch_inactive : 1; @@ -331,7 +331,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_cocpu_int_ena; - union { + volatile union { struct { uint32_t touch_done : 1; uint32_t touch_inactive : 1; @@ -349,7 +349,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_cocpu_int_st; - union { + volatile union { struct { uint32_t touch_done : 1; uint32_t touch_inactive : 1; @@ -367,7 +367,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_cocpu_int_clr; - union { + volatile union { struct { uint32_t pc : 13; /*cocpu Program counter*/ uint32_t mem_vld : 1; /*cocpu mem valid output*/ @@ -377,7 +377,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_cocpu_debug; - union { + volatile union { struct { uint32_t reserved0 : 28; uint32_t xpd_hall : 1; /*Power on hall sensor and connect to VP and VN*/ @@ -387,8 +387,8 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_hall_ctrl; - uint32_t sar_nouse; - union { + volatile uint32_t sar_nouse; + volatile union { struct { uint32_t reserved0 : 27; uint32_t rtc_i2c_clk_en : 1; @@ -399,7 +399,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_peri_clk_gate_conf; - union { + volatile union { struct { uint32_t reserved0 : 25; uint32_t reset : 1; @@ -412,7 +412,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_peri_reset_conf; - union { + volatile union { struct { uint32_t touch_done_w1ts : 1; uint32_t touch_inactive_w1ts : 1; @@ -430,7 +430,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_cocpu_int_ena_w1ts; - union { + volatile union { struct { uint32_t touch_done_w1tc : 1; uint32_t touch_inactive_w1tc : 1; @@ -448,7 +448,7 @@ typedef volatile struct sens_dev_s { }; uint32_t val; } sar_cocpu_int_ena_w1tc; - union { + volatile union { struct { uint32_t debug_bit_sel : 5; uint32_t reserved5 : 27; @@ -512,7 +512,7 @@ typedef volatile struct sens_dev_s { uint32_t reserved_1f0; uint32_t reserved_1f4; uint32_t reserved_1f8; - union { + volatile union { struct { uint32_t sar_date : 28; uint32_t reserved28 : 4; diff --git a/tools/test_apps/system/g1_components/CMakeLists.txt b/tools/test_apps/system/g1_components/CMakeLists.txt index 08f222f66b..e5d86c7338 100644 --- a/tools/test_apps/system/g1_components/CMakeLists.txt +++ b/tools/test_apps/system/g1_components/CMakeLists.txt @@ -26,6 +26,7 @@ set(esp_hal_components esp_hal_clock esp_hal_security esp_hal_systimer + esp_hal_regi2c ) set(COMPONENTS ${g0_components} ${g1_components} ${esp_hal_components} main)