diff --git a/components/esp_hal_clock/esp32h21/clk_tree_hal.c b/components/esp_hal_clock/esp32h21/clk_tree_hal.c index 9f914746ea..bc2f1059ea 100644 --- a/components/esp_hal_clock/esp32h21/clk_tree_hal.c +++ b/components/esp_hal_clock/esp32h21/clk_tree_hal.c @@ -17,8 +17,8 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src) return clk_ll_bbpll_get_freq_mhz(); case SOC_CPU_CLK_SRC_RC_FAST: return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ; - // case SOC_CPU_CLK_SRC_XTAL_X2: - // return clk_ll_xtal_x2_get_freq_mhz(); + case SOC_CPU_CLK_SRC_XTAL_X2: + return clk_ll_xtal_x2_get_freq_mhz(); default: // Unknown CPU_CLK mux input HAL_ASSERT(false); diff --git a/components/esp_hal_clock/esp32h21/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32h21/include/hal/clk_tree_ll.h index 8b3d0185bd..2d3843d8ba 100644 --- a/components/esp_hal_clock/esp32h21/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32h21/include/hal/clk_tree_ll.h @@ -24,7 +24,7 @@ #define MHZ (1000000) #define CLK_LL_PLL_48M_FREQ_MHZ (48) -// #define CLK_LL_PLL_64M_FREQ_MHZ (64) +#define CLK_LL_PLL_64M_FREQ_MHZ (64) #define CLK_LL_PLL_96M_FREQ_MHZ (96) #define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \ @@ -65,8 +65,7 @@ typedef struct { */ static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void) { - SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_BB_I2C | PMU_TIE_HIGH_XPD_BBPLL | PMU_TIE_HIGH_XPD_BBPLL_I2C); - SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_BBPLL_ICG); + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_BBPLL | PMU_TIE_HIGH_XPD_BBPLL_I2C); } /** @@ -74,32 +73,30 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void) */ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) { - CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_BB_I2C | PMU_TIE_HIGH_XPD_BBPLL | PMU_TIE_HIGH_XPD_BBPLL_I2C); - CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_BBPLL_ICG); - SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_BBPLL_I2C | PMU_TIE_LOW_XPD_BBPLL | PMU_TIE_LOW_XPD_BBPLL_I2C); - SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_BBPLL_ICG); + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_BBPLL_ICG) ; + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_BBPLL | PMU_TIE_LOW_XPD_BBPLL_I2C); } -// /** -// * @brief Power up XTAL_X2 circuit -// */ -// static inline __attribute__((always_inline)) void clk_ll_xtal_x2_enable(void) -// { -// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2); -// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG); -// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2); -// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_XTALX2_ICG); -// } +/** + * @brief Power up XTAL_X2 circuit + */ +static inline __attribute__((always_inline)) void clk_ll_xtal_x2_enable(void) +{ + CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2); + CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG); + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2); + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_XTALX2_ICG); +} -// /** -// * @brief Power down XTAL_X2 circuit -// */ -// static inline __attribute__((always_inline)) void clk_ll_xtal_x2_disable(void) -// { -// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2 | PMU_TIE_HIGH_GLOBAL_XTALX2_ICG); -// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2); -// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG); -// } +/** + * @brief Power down XTAL_X2 circuit + */ +static inline __attribute__((always_inline)) void clk_ll_xtal_x2_disable(void) +{ + CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2 | PMU_TIE_HIGH_GLOBAL_XTALX2_ICG); + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2); + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG); +} /** * @brief Enable the 32kHz crystal oscillator @@ -306,15 +303,15 @@ static inline __attribute__((always_inline)) bool clk_ll_bbpll_calibration_is_do return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); } -// /** -// * @brief Get XTAL_X2_CLK frequency -// * -// * @return XTAL_X2 clock frequency, in MHz -// */ -// static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_x2_get_freq_mhz(void) -// { -// return SOC_XTAL_FREQ_32M * 2; -// } +/** + * @brief Get XTAL_X2_CLK frequency + * + * @return XTAL_X2 clock frequency, in MHz + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_x2_get_freq_mhz(void) +{ + return SOC_XTAL_FREQ_32M * 2; +} /** * @brief To enable the change of soc_clk_sel, cpu_div_num, and ahb_div_num @@ -342,9 +339,9 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk case SOC_CPU_CLK_SRC_RC_FAST: PCR.sysclk_conf.soc_clk_sel = 2; break; - // case SOC_CPU_CLK_SRC_XTAL_X2: - // PCR.sysclk_conf.soc_clk_sel = 3; - // break; + case SOC_CPU_CLK_SRC_XTAL_X2: + PCR.sysclk_conf.soc_clk_sel = 3; + break; default: // Unsupported CPU_CLK mux input sel abort(); @@ -366,8 +363,8 @@ static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_sr return SOC_CPU_CLK_SRC_PLL; case 2: return SOC_CPU_CLK_SRC_RC_FAST; - // case 3: - // return SOC_CPU_CLK_SRC_XTAL_X2; + case 3: + return SOC_CPU_CLK_SRC_XTAL_X2; default: // Invalid SOC_CLK_SEL value return SOC_CPU_CLK_SRC_INVALID; diff --git a/components/esp_hw_support/include/esp_private/regi2c_ctrl.h b/components/esp_hw_support/include/esp_private/regi2c_ctrl.h index 2275364594..4a82ccd76b 100644 --- a/components/esp_hw_support/include/esp_private/regi2c_ctrl.h +++ b/components/esp_hw_support/include/esp_private/regi2c_ctrl.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_hw_support/port/esp32h21/esp_clk_tree.c b/components/esp_hw_support/port/esp32h21/esp_clk_tree.c index 8c6af0cb3e..98f65e7b5e 100644 --- a/components/esp_hw_support/port/esp32h21/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32h21/esp_clk_tree.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -33,9 +33,9 @@ uint32_t *freq_value) case SOC_MOD_CLK_PLL_F48M: clk_src_freq = CLK_LL_PLL_48M_FREQ_MHZ * MHZ; break; - // case SOC_MOD_CLK_XTAL_X2_F64M: - // clk_src_freq = CLK_LL_PLL_64M_FREQ_MHZ * MHZ; - // break; + case SOC_MOD_CLK_XTAL_X2_F64M: + clk_src_freq = CLK_LL_PLL_64M_FREQ_MHZ * MHZ; + break; case SOC_MOD_CLK_PLL_F96M: clk_src_freq = CLK_LL_PLL_96M_FREQ_MHZ * MHZ; break; @@ -60,22 +60,22 @@ uint32_t *freq_value) return ESP_OK; } -// static int16_t s_xtal_x2_ref_cnt = 0; +static int16_t s_xtal_x2_ref_cnt = 0; void esp_clk_tree_initialize(void) { - // // In bootloader, flash clock source will always be switched to use XTAL_X2 clock + // In bootloader, flash clock source will always be switched to use XTAL_X2 clock // s_xtal_x2_ref_cnt++; - // if (clk_ll_cpu_get_src() == SOC_CPU_CLK_SRC_XTAL_X2) { - // s_xtal_x2_ref_cnt++; - // } + if (clk_ll_cpu_get_src() == SOC_CPU_CLK_SRC_XTAL_X2) { + s_xtal_x2_ref_cnt++; + } } bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) { switch (clk_circuit) { - // case SOC_ROOT_CIRCUIT_CLK_XTAL_X2: - // return s_xtal_x2_ref_cnt > 0; + case SOC_ROOT_CIRCUIT_CLK_XTAL_X2: + return s_xtal_x2_ref_cnt > 0; default: break; } @@ -85,21 +85,21 @@ bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable) { switch (clk_circuit) { - // case SOC_ROOT_CIRCUIT_CLK_XTAL_X2: - // if (enable) { - // s_xtal_x2_ref_cnt++; - // } else { - // s_xtal_x2_ref_cnt--; - // } + case SOC_ROOT_CIRCUIT_CLK_XTAL_X2: + if (enable) { + s_xtal_x2_ref_cnt++; + } else { + s_xtal_x2_ref_cnt--; + } - // if (s_xtal_x2_ref_cnt == 1) { - // clk_ll_xtal_x2_enable(); - // } else if (s_xtal_x2_ref_cnt == 0) { - // clk_ll_xtal_x2_disable(); - // } + if (s_xtal_x2_ref_cnt == 1) { + clk_ll_xtal_x2_enable(); + } else if (s_xtal_x2_ref_cnt == 0) { + clk_ll_xtal_x2_disable(); + } - // assert(s_xtal_x2_ref_cnt >= 0); - // break; + assert(s_xtal_x2_ref_cnt >= 0); + break; default: break; } @@ -109,10 +109,10 @@ bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable) esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) { switch (clk_src) { - // case SOC_MOD_CLK_XTAL_X2_F64M: - // // later, here should handle ref count for XTAL_X2_F64M clock gating, then also handle XTAL_X2 circuit enable/disable - // esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable); - // break; + case SOC_MOD_CLK_XTAL_X2_F64M: + // later, here should handle ref count for XTAL_X2_F64M clock gating, then also handle XTAL_X2 circuit enable/disable + esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable); + break; default: break; } diff --git a/components/esp_hw_support/port/esp32h21/pmu_init.c b/components/esp_hw_support/port/esp32h21/pmu_init.c index 9ecd08d219..7aef03a4dd 100644 --- a/components/esp_hw_support/port/esp32h21/pmu_init.c +++ b/components/esp_hw_support/port/esp32h21/pmu_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,13 +13,12 @@ #include "hal/pmu_hal.h" #include "pmu_param.h" #include "esp_private/esp_pmu.h" -#include "soc/regi2c_pmu.h" #include "regi2c_ctrl.h" -#include "esp_private/ocode_init.h" -#include "esp_rom_sys.h" -#include "esp_hw_log.h" +#include "soc/rtc.h" +#include "soc/regi2c_lp_bias.h" +#include "soc/lp_aon_reg.h" -ESP_HW_LOG_ATTR_TAG(TAG, "pmu_init"); +static __attribute__((unused)) const char *TAG = "pmu_init"; typedef struct { const pmu_hp_system_power_param_t *power; @@ -193,7 +192,7 @@ static inline void pmu_hp_system_param_default(pmu_hp_mode_t mode, pmu_hp_system param->retent = pmu_hp_system_retention_param_default(mode); if (mode == PMU_MODE_HP_ACTIVE || mode == PMU_MODE_HP_MODEM) { - param->analog->regulator0.dbias = get_act_hp_dbias(); + param->analog->regulator1.drv_b = get_act_hp_drvb(); } } @@ -216,10 +215,6 @@ static inline void pmu_lp_system_param_default(pmu_lp_mode_t mode, pmu_lp_system param->power = pmu_lp_system_power_param_default(mode); *param->analog = *pmu_lp_system_analog_param_default(mode); //copy default value - - if (mode == PMU_MODE_LP_ACTIVE) { - param->analog->regulator0.dbias = get_act_lp_dbias(); - } } static void pmu_lp_system_init_default(pmu_context_t *ctx) @@ -234,27 +229,75 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx) } } -void pmu_init() +uint32_t get_ulp_ocode() { + uint32_t ulp_ocode = 0; + bool ulp_force_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE); + if (ulp_force_flag) + ulp_ocode = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_EXT_CODE); + else + ulp_ocode = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_OCODE); + return ulp_ocode; +} + +void pmu_init(void) +{ + WRITE_PERI_REG(PMU_POWER_PD_TOP_CNTL_REG, 0); + WRITE_PERI_REG(PMU_POWER_PD_HPAON_CNTL_REG, 0); + WRITE_PERI_REG(PMU_POWER_PD_HPCPU_CNTL_REG, 0); + WRITE_PERI_REG(PMU_POWER_PD_HPPERI_RESERVE_REG, 0); + WRITE_PERI_REG(PMU_POWER_PD_HPWIFI_CNTL_REG, 0); + WRITE_PERI_REG(PMU_POWER_PD_LPPERI_CNTL_REG, 0); + WRITE_PERI_REG(PMU_POWER_PD_MEM_CNTL_REG, 0); + + /* Peripheral reg i2c power up */ + SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); + SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFTX_I2C); + SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFRX_I2C); + pmu_hp_system_init_default(PMU_instance()); pmu_lp_system_init_default(PMU_instance()); pmu_power_domain_force_default(PMU_instance()); - /* No peripheral reg i2c power up required on the target */ -#if !CONFIG_IDF_ENV_FPGA - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, 0); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, 0); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG_SLP, 0); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG_SLP, 0); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_RTC_REG, 0); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_DIG_REG, 0); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_TRX, 0); -#endif -#if !CONFIG_IDF_ENV_FPGA - // TODO: IDF-11548 +// #if !CONFIG_IDF_ENV_FPGA + // TODO: IDF-12313 // if (esp_rom_get_reset_reason(0) == RESET_REASON_CHIP_POWER_ON) { // esp_ocode_calib_init(); // } -#endif +// #endif + uint32_t ulp_ocode = get_ulp_ocode(); + REG_SET_FIELD(PMU_BLE_BANDGAP_CTRL_REG, PMU_EXT_OCODE, ulp_ocode); + SET_PERI_REG_MASK(PMU_BLE_BANDGAP_CTRL_REG, PMU_EXT_FORCE_OCODE); + + //For dcdc ldo mode when VDD is low than about a certion value, eg 2.6v + CLEAR_PERI_REG_MASK(LP_AON_DATE_REG, LP_AON_DREG_LDO_HW); + REG_SET_FIELD(LP_AON_DATE_REG, LP_AON_DREG_LDO_SW, 15); + + + // For sleep + bool hp_ana_wait_sel_sosc = 1; + uint32_t lp_wait_us = 154; + uint32_t hp_wait_us = 150; + uint32_t xtl_stable_wait = 200; + + uint32_t slowclk_period = rtc_clk_cal(0, 128) * 4; + uint32_t fosc_period = rtc_clk_cal(3, 5000); + + uint32_t lp_wait_cycle = rtc_time_us_to_slowclk(lp_wait_us, slowclk_period); + uint32_t xtl_wait_cycle = rtc_time_us_to_slowclk(xtl_stable_wait, fosc_period); + uint32_t hp_wait_cycle; + + if (hp_ana_wait_sel_sosc) + { + REG_SET_BIT(PMU_SLP_WAKEUP_CNTL7_REG, PMU_ANA_WAIT_CLK_SEL); // hp_ana_wait_clk sel sosc + hp_wait_cycle = rtc_time_us_to_slowclk(hp_wait_us, slowclk_period); + } else { + REG_CLR_BIT(PMU_SLP_WAKEUP_CNTL7_REG, PMU_ANA_WAIT_CLK_SEL); // hp_ana_wait_clk sel fosc + hp_wait_cycle = rtc_time_us_to_slowclk(lp_wait_us, fosc_period); + } + + REG_SET_FIELD(PMU_SLP_WAKEUP_CNTL5_REG, PMU_LP_ANA_WAIT_TARGET, lp_wait_cycle); + REG_SET_FIELD(PMU_SLP_WAKEUP_CNTL7_REG, PMU_ANA_WAIT_TARGET, hp_wait_cycle); + REG_SET_FIELD(PMU_POWER_CK_WAIT_CNTL_REG, PMU_WAIT_XTL_STABLE, xtl_wait_cycle); } diff --git a/components/esp_hw_support/port/esp32h21/pmu_param.c b/components/esp_hw_support/port/esp32h21/pmu_param.c index ccb52da2f3..fe58c23e81 100644 --- a/components/esp_hw_support/port/esp32h21/pmu_param.c +++ b/components/esp_hw_support/port/esp32h21/pmu_param.c @@ -1,8 +1,9 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ + #include #include #include @@ -22,12 +23,21 @@ ESP_HW_LOG_ATTR_TAG(TAG, "pmu_param"); #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) #endif +/* + flash_mode : + 0: normal mode; + 1: off mode + 2: external mode; + 3: standby mode + 4: 4(through mode), only used when vdd low than 3v +*/ #define PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT() { \ .dig_power = { \ .vdd_flash_mode = 0, \ .mem_dslp = 0, \ .mem_pd_en = 0, \ .wifi_pd_en = 0, \ + .peri_pd_en = 0, \ .cpu_pd_en = 0, \ .aon_pd_en = 0, \ .top_pd_en = 0 \ @@ -45,19 +55,27 @@ ESP_HW_LOG_ATTR_TAG(TAG, "pmu_param"); } \ } +/* + flash_mode : + 0: normal mode; + 1: off mode + 2: external mode; + 3: standby mode + 4: 4(through mode), only used when vdd low than 3v +*/ #define PMU_HP_SLEEP_POWER_CONFIG_DEFAULT() { \ .dig_power = { \ .vdd_flash_mode = 0, \ .mem_dslp = 0, \ .mem_pd_en = 0, \ - .wifi_pd_en = 1, \ - .cpu_pd_en = 1, \ + .wifi_pd_en = 0, \ + .cpu_pd_en = 0, \ .aon_pd_en = 0, \ - .top_pd_en = 1 \ + .top_pd_en = 0 \ }, \ .clk_power = { \ .i2c_iso_en = 1, \ - .i2c_retention = 0, \ + .i2c_retention = 1, \ .xpd_bb_i2c = 0, \ .xpd_bbpll_i2c = 0, \ .xpd_bbpll = 0, \ @@ -153,10 +171,10 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp .bias = { \ .dcdc_ccm_enb = 0, \ .dcdc_clear_rdy = 0, \ - .dig_reg_dpcur_bias = 2, \ - .dig_reg_dsfmos = 10, \ - .dcm_vset = 24, \ + .dig_reg_dpcur_bias = 3, \ + .dig_reg_dsfmos = 15, \ .dcm_mode = 3, \ + .dcm_vset = DCDC_DREG_DEFAULT, \ .xpd_trx = 1, \ .xpd_bias = 1, \ .discnnt_dig_rtc = 0, \ @@ -174,10 +192,10 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp .xpd = 1, \ .slp_mem_dbias = 0, \ .slp_logic_dbias = 0, \ - .dbias = HP_CALI_DBIAS_DEFAULT \ + .dbias = 0 \ }, \ .regulator1 = { \ - .drv_b = 0x1a \ + .drv_b = HP_CALI_DRVB_DEFAULT \ } \ } @@ -186,9 +204,9 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp .dcdc_ccm_enb = 1, \ .dcdc_clear_rdy = 0, \ .dig_reg_dpcur_bias = 1, \ - .dig_reg_dsfmos = 8, \ - .dcm_vset = 0, \ + .dig_reg_dsfmos = 15, \ .dcm_mode = 3, \ + .dcm_vset = DCDC_DREG_DEFAULT, \ .xpd_trx = 0, \ .xpd_bias = 0, \ .discnnt_dig_rtc = 0, \ @@ -205,7 +223,7 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp .dbias = 0 \ }, \ .regulator1 = { \ - .drv_b = 26 \ + .drv_b = 20 \ } \ } @@ -261,11 +279,17 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm return &hp_retention[mode]; } - -/** LP system default parameter */ +/* + vdd_io_mode : + 0: normal mode; + 1: off mode + 2: external mode; + 3: standby mode + 4: 4(through mode), only used when vdd low than 3v +*/ #define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \ .dig_power = { \ - .vdd_io_mode = 4, \ + .vdd_io_mode = 0, \ .bod_source_sel = 0, \ .vddbat_mode = 2, \ .mem_dslp = 0, \ @@ -280,12 +304,20 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm } \ } +/* + vdd_io_mode : + 0: normal mode; + 1: off mode + 2: external mode; + 3: standby mode + 4: 4(through mode), only used when vdd low than 3v +*/ #define PMU_LP_SLEEP_POWER_CONFIG_DEFAULT() { \ .dig_power = { \ .vdd_io_mode = 3, \ .bod_source_sel = 0, \ - .vddbat_mode = 1, \ - .mem_dslp = 1, \ + .vddbat_mode = 0, \ + .mem_dslp = 0, \ .peri_pd_en = 0, \ }, \ .clk_power = { \ @@ -327,10 +359,10 @@ const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mod .bias = { \ .dcdc_ccm_enb = 1, \ .dcdc_clear_rdy = 0, \ - .dig_reg_dpcur_bias = 3, \ - .dig_reg_dsfmos = 5, \ - .dcm_vset = 0, \ + .dig_reg_dpcur_bias = 1, \ + .dig_reg_dsfmos = 15, \ .dcm_mode = 3, \ + .dcm_vset = 0, \ .xpd_bias = 0, \ .discnnt_dig_rtc = 1, \ .pd_cur = 1, \ @@ -340,7 +372,7 @@ const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mod .slp_xpd = 0, \ .xpd = 1, \ .slp_dbias = 0, \ - .dbias = 1 \ + .dbias = 3 \ }, \ .regulator1 = { \ .drv_b = 0 \ @@ -357,54 +389,12 @@ const pmu_lp_system_analog_param_t * pmu_lp_system_analog_param_default(pmu_lp_m return &lp_analog[mode]; } -uint32_t get_act_hp_dbias(void) +uint32_t get_act_hp_drvb(void) { - /* hp_cali_dbias is read from efuse to ensure that the hp_active_voltage is close to 0.93V */ - // TODO: PM-373 - //unsigned blk_version = efuse_hal_blk_version(); - uint32_t hp_cali_dbias = HP_CALI_DBIAS_DEFAULT; - //if (blk_version >= 3) { - // hp_cali_dbias = efuse_ll_get_active_hp_dbias(); - // if (hp_cali_dbias != 0) { - // //efuse dbias need to add 2 to meet the CPU frequency switching - // if (hp_cali_dbias + 2 > 31) { - // hp_cali_dbias = 31; - // } else { - // hp_cali_dbias += 2; - // } - // } else { - // hp_cali_dbias = HP_CALI_DBIAS_DEFAULT; - // ESP_HW_LOGD(TAG, "hp_cali_dbias not burnt in efuse or wrong value was burnt in blk version: %d\n", blk_version); - // } - //} else { - // ESP_HW_LOGD(TAG, "blk_version is less than 3, act dbias not burnt in efuse\n"); - //} - - return hp_cali_dbias; + return HP_CALI_DRVB_DEFAULT; } uint32_t get_act_lp_dbias(void) { - /* lp_cali_dbias are read from efuse to ensure that the lp_active_voltage is close to 0.925V */ - // TODO: PM-373 - //unsigned blk_version = efuse_hal_blk_version(); - uint32_t lp_cali_dbias = LP_CALI_DBIAS_DEFAULT; - //if (blk_version >= 3) { - // lp_cali_dbias = efuse_ll_get_active_lp_dbias(); - // if (lp_cali_dbias != 0) { - // //efuse dbias need to add 2 to meet the CPU frequency switching - // if (lp_cali_dbias + 2 > 31) { - // lp_cali_dbias = 31; - // } else { - // lp_cali_dbias += 2; - // } - // } else { - // lp_cali_dbias = LP_CALI_DBIAS_DEFAULT; - // ESP_HW_LOGD(TAG, "lp_cali_dbias not burnt in efuse or wrong value was burnt in blk version: %d\n", blk_version); - // } - //} else { - // ESP_HW_LOGD(TAG, "blk_version is less than 3, act dbias not burnt in efuse\n"); - //} - - return lp_cali_dbias; + return LP_CALI_DBIAS_DEFAULT; } diff --git a/components/esp_hw_support/port/esp32h21/pmu_sleep.c b/components/esp_hw_support/port/esp32h21/pmu_sleep.c index 11b40baa4e..308eac7fd5 100644 --- a/components/esp_hw_support/port/esp32h21/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32h21/pmu_sleep.c @@ -171,7 +171,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default( analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_slp_lp_dbias(); if (!(sleep_flags & PMU_SLEEP_PD_XTAL)){ analog_default.hp_sys.analog.xpd_trx = PMU_XPD_TRX_SLEEP_ON; - analog_default.hp_sys.analog.dbias = get_act_hp_dbias(); + analog_default.hp_sys.analog.drv_b = get_act_hp_drvb(); analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON; analog_default.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON; @@ -179,7 +179,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default( analog_default.lp_sys[LP(SLEEP)].analog.bias_sleep = PMU_BIASSLP_SLEEP_ON; analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_act_lp_dbias(); } else if (!(sleep_flags & PMU_SLEEP_PD_RC_FAST)) { - analog_default.hp_sys.analog.dbias = get_act_hp_dbias(); + analog_default.hp_sys.analog.drv_b = get_act_hp_drvb(); analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_act_lp_dbias(); } config->analog = analog_default; diff --git a/components/esp_hw_support/port/esp32h21/private_include/pmu_param.h b/components/esp_hw_support/port/esp32h21/private_include/pmu_param.h index 3d379d303a..fc2ce899f9 100644 --- a/components/esp_hw_support/port/esp32h21/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32h21/private_include/pmu_param.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,8 +16,9 @@ extern "C" { #endif -#define HP_CALI_DBIAS_DEFAULT 0 +#define HP_CALI_DRVB_DEFAULT 8 #define LP_CALI_DBIAS_DEFAULT 0 +#define DCDC_DREG_DEFAULT 12 // FOR XTAL FORCE PU IN SLEEP #define PMU_PD_CUR_SLEEP_ON 0 @@ -28,15 +29,15 @@ extern "C" { // FOR BOTH LIGHTSLEEP & DEEPSLEEP #define PMU_PD_CUR_SLEEP_DEFAULT 1 #define PMU_BIASSLP_SLEEP_DEFAULT 1 -#define PMU_LP_XPD_SLEEP_DEFAULT 1 #define PMU_XPD_TRX_SLEEP_DEFAULT 0 #define PMU_LP_SLP_XPD_SLEEP_DEFAULT 0 -#define PMU_LP_SLP_DBIAS_SLEEP_DEFAULT 0 +#define PMU_LP_SLP_DBIAS_SLEEP_DEFAULT 3 // FOR LIGHTSLEEP -#define PMU_HP_XPD_LIGHTSLEEP 1 -#define PMU_HP_DRVB_LIGHTSLEEP 0xFFFFF8 +#define PMU_HP_DRVB_LIGHTSLEEP 20 #define PMU_LP_DRVB_LIGHTSLEEP 0 +#define PMU_HP_XPD_LIGHTSLEEP 1 +#define PMU_LP_XPD_LIGHTSLEEP 1 #define PMU_HP_DBIAS_LIGHTSLEEP_0V6_DEFAULT 1 #define PMU_LP_DBIAS_SLEEP_0V7_DEFAULT 6 @@ -47,8 +48,10 @@ extern "C" { // FOR DEEPSLEEP #define PMU_HP_XPD_DEEPSLEEP 0 #define PMU_LP_DRVB_DEEPSLEEP 7 +/* To close hp_ldo in dslp */ +#define PMU_LP_XPD_DEEPSLEEP 0 -uint32_t get_act_hp_dbias(void); +uint32_t get_act_hp_drvb(void); uint32_t get_act_lp_dbias(void); typedef struct { @@ -284,10 +287,11 @@ typedef struct { } lp_sys[PMU_MODE_LP_MAX]; } pmu_sleep_power_config_t; +/* ESP32H21 ECO1 doesn't allow flash_ldo off or standby mode, todo PM-678 */ #define PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags) { \ .hp_sys = { \ .dig_power = { \ - .vdd_flash_mode = ((sleep_flags) & PMU_SLEEP_PD_VDDSDIO) ? 1 : 3, \ + .vdd_flash_mode = ((sleep_flags) & PMU_SLEEP_PD_VDDSDIO) ? 1 : 0, \ .wifi_pd_en = ((sleep_flags) & PMU_SLEEP_PD_MODEM) ? 1 : 0,\ .cpu_pd_en = ((sleep_flags) & PMU_SLEEP_PD_CPU) ? 1 : 0,\ .top_pd_en = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0,\ @@ -381,7 +385,7 @@ typedef struct { .dcdc_clear_rdy = 0, \ .dig_reg_dpcur_bias = 2, \ .dig_reg_dsfmos = 10, \ - .dcm_vset = 29, \ + .dcm_vset = 0, \ .dcm_mode = 3, \ .xpd_trx = PMU_XPD_TRX_SLEEP_DEFAULT, \ .xpd_bias = 1, \ @@ -422,7 +426,7 @@ typedef struct { .bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \ .slp_xpd = PMU_LP_SLP_XPD_SLEEP_DEFAULT, \ .slp_dbias = PMU_LP_SLP_DBIAS_SLEEP_DEFAULT, \ - .xpd = PMU_LP_XPD_SLEEP_DEFAULT, \ + .xpd = PMU_LP_XPD_LIGHTSLEEP, \ .dbias = PMU_LP_DBIAS_SLEEP_0V7_DEFAULT \ } \ } \ @@ -435,7 +439,7 @@ typedef struct { .dcdc_clear_rdy = 0, \ .dig_reg_dpcur_bias = 0, \ .dig_reg_dsfmos = 5, \ - .dcm_vset = 10, \ + .dcm_vset = 0, \ .dcm_mode = 3, \ .xpd_trx = PMU_XPD_TRX_SLEEP_DEFAULT, \ .xpd_bias = 0, \ @@ -476,7 +480,7 @@ typedef struct { .bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \ .slp_xpd = PMU_LP_SLP_XPD_SLEEP_DEFAULT, \ .slp_dbias = PMU_LP_SLP_DBIAS_SLEEP_DEFAULT, \ - .xpd = PMU_LP_XPD_SLEEP_DEFAULT, \ + .xpd = PMU_LP_XPD_DEEPSLEEP, \ .dbias = PMU_LP_DBIAS_SLEEP_0V7_DEFAULT \ } \ } \ diff --git a/components/esp_hw_support/port/esp32h21/rtc_clk.c b/components/esp_hw_support/port/esp32h21/rtc_clk.c index d9c7d9ea0a..56641c10b1 100644 --- a/components/esp_hw_support/port/esp32h21/rtc_clk.c +++ b/components/esp_hw_support/port/esp32h21/rtc_clk.c @@ -131,13 +131,13 @@ soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void) return clk_ll_rtc_fast_get_src(); } -static void rtc_clk_bbpll_disable(void) +static __attribute__((unused)) void rtc_clk_bbpll_disable(void) { clk_ll_bbpll_disable(); s_cur_pll_freq = 0; } -static void rtc_clk_bbpll_enable(void) +static __attribute__((unused)) void rtc_clk_bbpll_enable(void) { clk_ll_bbpll_enable(); } @@ -206,22 +206,22 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz); } -// /** -// * Switch to XTAL_X2 as cpu clock source. -// * On ESP32H21, XTAL_X2 frequency is 64MHz. -// * XTAL_X2 circuit must already been enabled. -// */ -// static void rtc_clk_cpu_freq_to_xtal_x2(uint32_t cpu_freq_mhz, uint32_t cpu_divider) -// { -// // f_hp_root = 64MHz -// clk_ll_cpu_set_divider(cpu_divider); -// // Constraint: f_ahb <= 32MHz; f_cpu = N * f_ahb (N = 1, 2, 3...) -// uint32_t ahb_divider = (cpu_divider == 1) ? 2 : cpu_divider; -// clk_ll_ahb_set_divider(ahb_divider); -// clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL_X2); -// clk_ll_bus_update(); -// esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz); -// } +/** + * Switch to XTAL_X2 as cpu clock source. + * On ESP32H21, XTAL_X2 frequency is 64MHz. + * XTAL_X2 circuit must already been enabled. + */ +static void rtc_clk_cpu_freq_to_xtal_x2(uint32_t cpu_freq_mhz, uint32_t cpu_divider) +{ + // f_hp_root = 64MHz + clk_ll_cpu_set_divider(cpu_divider); + // Constraint: f_ahb <= 32MHz; f_cpu = N * f_ahb (N = 1, 2, 3...) + uint32_t ahb_divider = (cpu_divider == 1) ? 2 : cpu_divider; + clk_ll_ahb_set_divider(ahb_divider); + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL_X2); + clk_ll_bus_update(); + esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz); +} bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config) { @@ -246,11 +246,11 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ; divider = 1; - // } else if (freq_mhz == 64) { - // real_freq_mhz = freq_mhz; - // source = SOC_CPU_CLK_SRC_XTAL_X2; - // source_freq_mhz = CLK_LL_PLL_64M_FREQ_MHZ; - // divider = 1; + } else if (freq_mhz == 64) { + real_freq_mhz = freq_mhz; + source = SOC_CPU_CLK_SRC_XTAL_X2; + source_freq_mhz = CLK_LL_PLL_64M_FREQ_MHZ; + divider = 1; } else if (freq_mhz == 48) { real_freq_mhz = freq_mhz; source = SOC_CPU_CLK_SRC_PLL; @@ -276,27 +276,42 @@ __attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id) static void rtc_clk_cpu_src_clk_enable(soc_cpu_clk_src_t new_src, uint32_t new_src_freq_mhz) { if (new_src == SOC_CPU_CLK_SRC_PLL) { + bool truly_enabled = false; +#if BOOTLOADER_BUILD rtc_clk_bbpll_enable(); - rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), new_src_freq_mhz); -// } else if (new_src == SOC_CPU_CLK_SRC_XTAL_X2) { -// #if BOOTLOADER_BUILD -// clk_ll_xtal_x2_enable(); -// #else -// esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, true); -// #endif + truly_enabled = true; +#else + truly_enabled = esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_BBPLL, true); +#endif + if (truly_enabled || (s_cur_pll_freq != new_src_freq_mhz)) { + rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), new_src_freq_mhz); + } + } else if (new_src == SOC_CPU_CLK_SRC_XTAL_X2) { +#if BOOTLOADER_BUILD + clk_ll_xtal_x2_enable(); +#else + esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, true); +#endif } } static void rtc_clk_cpu_src_clk_disable(soc_cpu_clk_src_t old_src) { if ((old_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) { +#if BOOTLOADER_BUILD rtc_clk_bbpll_disable(); -// } else if (old_src == SOC_CPU_CLK_SRC_XTAL_X2) { -// #if BOOTLOADER_BUILD -// clk_ll_xtal_x2_disable(); -// #else -// esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, false); -// #endif +#else + bool truly_disabled = esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_BBPLL, false); + if (truly_disabled) { + s_cur_pll_freq = 0; + } +#endif + } else if (old_src == SOC_CPU_CLK_SRC_XTAL_X2) { +#if BOOTLOADER_BUILD + clk_ll_xtal_x2_disable(); +#else + esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, false); +#endif } } @@ -316,8 +331,8 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP); } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { rtc_clk_cpu_freq_to_rc_fast(); - // } else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2) { - // rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div); + } else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2) { + rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div); } if (old_cpu_clk_src != config->source) { @@ -341,9 +356,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) case SOC_CPU_CLK_SRC_RC_FAST: source_freq_mhz = 20; break; - // case SOC_CPU_CLK_SRC_XTAL_X2: - // source_freq_mhz = clk_ll_xtal_x2_get_freq_mhz(); - // break; + case SOC_CPU_CLK_SRC_XTAL_X2: + source_freq_mhz = clk_ll_xtal_x2_get_freq_mhz(); + break; default: ESP_HW_LOGE(TAG, "unsupported frequency configuration"); abort(); @@ -367,9 +382,9 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { rtc_clk_cpu_freq_to_rc_fast(); - // } else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2 - // && esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_XTAL_X2)) { - // rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div); + } else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2 + && esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_XTAL_X2)) { + rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div); } else { /* fallback */ rtc_clk_cpu_freq_set_config(config); @@ -379,7 +394,11 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) void rtc_clk_cpu_freq_set_xtal(void) { rtc_clk_cpu_set_to_default_config(); +#if BOOTLOADER_BUILD rtc_clk_bbpll_disable(); +#else + esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_BBPLL, false); +#endif } FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void) @@ -417,9 +436,9 @@ static uint32_t rtc_clk_ahb_freq_get(void) case SOC_CPU_CLK_SRC_RC_FAST: soc_root_freq_mhz = 20; break; - // case SOC_CPU_CLK_SRC_XTAL_X2: - // soc_root_freq_mhz = clk_ll_xtal_x2_get_freq_mhz(); - // break; + case SOC_CPU_CLK_SRC_XTAL_X2: + soc_root_freq_mhz = clk_ll_xtal_x2_get_freq_mhz(); + break; default: // Unknown SOC_ROOT clock source soc_root_freq_mhz = 0; diff --git a/components/esp_hw_support/port/esp32h21/rtc_clk_init.c b/components/esp_hw_support/port/esp32h21/rtc_clk_init.c index 2d1c8fd970..f95c0dce22 100644 --- a/components/esp_hw_support/port/esp32h21/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32h21/rtc_clk_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,13 +14,13 @@ #include "esp_cpu.h" #include "regi2c_ctrl.h" #include "soc/lp_clkrst_reg.h" -#include "soc/regi2c_pmu.h" +#include "soc/regi2c_dcdc.h" #include "esp_hw_log.h" #include "hal/clk_tree_ll.h" #include "soc/pmu_reg.h" #include "pmu_param.h" -ESP_HW_LOG_ATTR_TAG(TAG, "rtc_clk_init"); +// ESP_HW_LOG_ATTR_TAG(TAG, "rtc_clk_init"); void rtc_clk_init(rtc_clk_config_t cfg) { @@ -35,13 +35,30 @@ void rtc_clk_init(rtc_clk_config_t cfg) * CLK_8M_DFREQ constant gives the best temperature characteristics. */ REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OC_SCK_DCAP, cfg.slow_clk_dcap); // TODO: IDF-11548 + REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.slow_clk_dcap); // h4 specific workaround (RC32K_DFREQ is used for RC_SLOW clock tuning) TODO: IDF-12313 - uint32_t hp_cali_dbias = get_act_hp_dbias(); - uint32_t lp_cali_dbias = get_act_lp_dbias(); - SET_PERI_REG_BITS(PMU_HP_MODEM_HP_REGULATOR0_REG, PMU_HP_MODEM_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_MODEM_HP_REGULATOR_DBIAS_S); - SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S); - SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, lp_cali_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S); + + // switch to ccm mode + REG_SET_FIELD(PMU_DCM_CTRL_REG, PMU_DCDC_CCM_SW_EN, 1); + REG_SET_FIELD(PMU_HP_ACTIVE_BIAS_REG, PMU_HP_ACTIVE_DCDC_CCM_ENB, 0); + + + // dcdc init + REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_CCM_DREG0, DCDC_DREG_DEFAULT); + REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_CCM_PCUR_LIMIT0, 4); + REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_VCM_DREG0, DCDC_DREG_DEFAULT); + REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_VCM_PCUR_LIMIT0, 2); + REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_XPD_TRX, 0); + // REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_PD_DBRNO, 0); + + // close rf_pll + CLEAR_PERI_REG_MASK(PMU_DATE_REG, BIT(25)); //bit25 control rfpll + + uint32_t hp_drvb = get_act_hp_drvb(); + uint32_t lp_dbias = get_act_lp_dbias(); + pmu_ll_hp_set_regulator_xpd(&PMU, PMU_MODE_HP_ACTIVE, true); + pmu_ll_hp_set_regulator_driver_bar(&PMU, PMU_MODE_HP_ACTIVE, hp_drvb); + pmu_ll_lp_set_regulator_dbias(&PMU, PMU_MODE_LP_ACTIVE, lp_dbias); // XTAL freq can be directly informed from register field PCR_CLK_XTAL_FREQ @@ -73,3 +90,8 @@ void rtc_clk_init(rtc_clk_config_t cfg) rtc_clk_fast_src_set(cfg.fast_clk_src); rtc_clk_slow_src_set(cfg.slow_clk_src); } + +__attribute__((weak)) uint8_t i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add) {return 0;} +__attribute__((weak)) uint8_t i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) {return 0;} +__attribute__((weak)) void i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) {}; +__attribute__((weak)) void i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) {}; diff --git a/components/esp_hw_support/port/esp32h21/rtc_time.c b/components/esp_hw_support/port/esp32h21/rtc_time.c index 7637d2d514..0b008078e4 100644 --- a/components/esp_hw_support/port/esp32h21/rtc_time.c +++ b/components/esp_hw_support/port/esp32h21/rtc_time.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -33,7 +33,7 @@ ESP_LOG_ATTR_TAG(TAG, "rtc_time"); * @param slowclk_cycles number of slow clock cycles to count * @return number of XTAL clock cycles within the given number of slow clock cycles */ -static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles) +uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles) { assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V); diff --git a/components/esp_hw_support/port/esp32h4/rtc_clk.c b/components/esp_hw_support/port/esp32h4/rtc_clk.c index f8dcf6a68e..95f8289a20 100644 --- a/components/esp_hw_support/port/esp32h4/rtc_clk.c +++ b/components/esp_hw_support/port/esp32h4/rtc_clk.c @@ -186,7 +186,7 @@ static void rtc_clk_cpu_freq_to_rc_fast(void) clk_ll_cpu_set_divider(1); clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST); clk_ll_bus_update(); - esp_rom_set_cpu_ticks_per_us(8); + esp_rom_set_cpu_ticks_per_us(20); } /** @@ -356,7 +356,7 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) break; } case SOC_CPU_CLK_SRC_RC_FAST: - source_freq_mhz = 8; + source_freq_mhz = 20; break; case SOC_CPU_CLK_SRC_XTAL_X2: source_freq_mhz = clk_ll_xtal_x2_get_freq_mhz(); @@ -447,7 +447,7 @@ static uint32_t rtc_clk_ahb_freq_get(void) soc_root_freq_mhz = clk_ll_bbpll_get_freq_mhz(); break; case SOC_CPU_CLK_SRC_RC_FAST: - soc_root_freq_mhz = 8; + soc_root_freq_mhz = 20; break; case SOC_CPU_CLK_SRC_XTAL_X2: soc_root_freq_mhz = clk_ll_xtal_x2_get_freq_mhz(); diff --git a/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c b/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c index 533cf08352..400c8f3a3c 100644 --- a/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c +++ b/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c @@ -377,7 +377,7 @@ RTC_NOINIT_ATTR #elif CONFIG_IDF_TARGET_ESP32C61 #define TEMP_RTC_STORE_REG LP_AON_DATE_REG #define TEMP_RTC_STORE_REG_M LP_AON_DATE_M -#elif CONFIG_IDF_TARGET_ESP32H4 +#elif CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32H21 #include "soc/pmu_reg.h" #define TEMP_RTC_STORE_REG PMU_DATE_REG #define TEMP_RTC_STORE_REG_M PMU_PMU_DATE_M diff --git a/components/esp_system/port/soc/esp32h21/Kconfig.cpu b/components/esp_system/port/soc/esp32h21/Kconfig.cpu index 9e09c847e0..50e396a100 100644 --- a/components/esp_system/port/soc/esp32h21/Kconfig.cpu +++ b/components/esp_system/port/soc/esp32h21/Kconfig.cpu @@ -11,9 +11,9 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ config ESP_DEFAULT_CPU_FREQ_MHZ_48 bool "48 MHz" depends on !IDF_ENV_FPGA - #config ESP_DEFAULT_CPU_FREQ_MHZ_64 - # bool "64 MHz" - # depends on !IDF_ENV_FPGA + config ESP_DEFAULT_CPU_FREQ_MHZ_64 + bool "64 MHz" + depends on !IDF_ENV_FPGA config ESP_DEFAULT_CPU_FREQ_MHZ_96 bool "96 MHz" depends on !IDF_ENV_FPGA @@ -23,5 +23,5 @@ config ESP_DEFAULT_CPU_FREQ_MHZ int default 32 if ESP_DEFAULT_CPU_FREQ_MHZ_32 default 48 if ESP_DEFAULT_CPU_FREQ_MHZ_48 - #default 64 if ESP_DEFAULT_CPU_FREQ_MHZ_64 + default 64 if ESP_DEFAULT_CPU_FREQ_MHZ_64 default 96 if ESP_DEFAULT_CPU_FREQ_MHZ_96 diff --git a/components/soc/esp32h21/include/soc/clk_tree_defs.h b/components/soc/esp32h21/include/soc/clk_tree_defs.h index ca0acdbd2d..ab9fad7e59 100644 --- a/components/soc/esp32h21/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h21/include/soc/clk_tree_defs.h @@ -68,7 +68,7 @@ typedef enum { */ typedef enum { SOC_ROOT_CIRCUIT_CLK_BBPLL, /*!< BBPLL_CLK is the output of the PLL generator circuit */ - // SOC_ROOT_CIRCUIT_CLK_XTAL_X2, /*!< XTAL_X2_CLK is the output of the XTAL_X2 generator circuit */ + SOC_ROOT_CIRCUIT_CLK_XTAL_X2, /*!< XTAL_X2_CLK is the output of the XTAL_X2 generator circuit */ } soc_root_clk_circuit_t; /** @@ -79,7 +79,7 @@ typedef enum { SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is one of the outputs of 32MHz crystal oscillator frequency multiplier, 96MHz) */ SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ - // SOC_CPU_CLK_SRC_XTAL_X2 = 3, /*!< Select XTAL_X2_CLK as CPU_CLK source (XTAL_X2_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */ + SOC_CPU_CLK_SRC_XTAL_X2 = 3, /*!< Select XTAL_X2_CLK as CPU_CLK source (XTAL_X2_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */ SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ } soc_cpu_clk_src_t; @@ -135,7 +135,7 @@ typedef enum { // For digital domain: peripherals, BLE SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */ SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 48MHz */ - // SOC_MOD_CLK_XTAL_X2_F64M, /*!< XTAL_X2_F64M_CLK is derived from XTAL_X2 (clock gating), it has a fixed frequency of 64MHz */ + SOC_MOD_CLK_XTAL_X2_F64M, /*!< XTAL_X2_F64M_CLK is derived from XTAL_X2 (clock gating), it has a fixed frequency of 64MHz */ SOC_MOD_CLK_PLL_F96M, /*!< PLL_F96M_CLK is derived from PLL (clock gating), it has a fixed frequency of 96MHz */ SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ @@ -447,9 +447,9 @@ typedef enum { typedef enum { FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - // FLASH_CLK_SRC_PLL_F64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select PLL_F64M as the source clock */ + FLASH_CLK_SRC_REF_F64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */ FLASH_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */ - FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default clock choice */ + FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the default clock choice */ FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ } soc_periph_flash_clk_src_t; @@ -478,7 +478,7 @@ typedef enum { typedef enum { I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default source clock */ I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */ - // I2S_CLK_SRC_PLL_64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select PLL_F64M as the source clock */ + I2S_CLK_SRC_PLL_64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */ I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */ } soc_periph_i2s_clk_src_t; diff --git a/components/soc/esp32h21/include/soc/regi2c_dcdc.h b/components/soc/esp32h21/include/soc/regi2c_dcdc.h new file mode 100644 index 0000000000..e5c5fd3db9 --- /dev/null +++ b/components/soc/esp32h21/include/soc/regi2c_dcdc.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#pragma once + +/** + * @file regi2c_dcdc.h + * @brief Register definitions for digital to get rtc voltage & digital voltage + * by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration. + */ + +#define I2C_DCDC 0x6D +#define I2C_DCDC_HOSTID 0 + +#define I2C_DCDC_XPD_TRX 1 +#define I2C_DCDC_XPD_TRX_MSB 7 +#define I2C_DCDC_XPD_TRX_LSB 7 + +#define I2C_DCDC_CCM_DREG0 7 +#define I2C_DCDC_CCM_DREG0_MSB 4 +#define I2C_DCDC_CCM_DREG0_LSB 0 + +#define I2C_DCDC_CCM_PCUR_LIMIT0 7 +#define I2C_DCDC_CCM_PCUR_LIMIT0_MSB 7 +#define I2C_DCDC_CCM_PCUR_LIMIT0_LSB 5 + +#define I2C_DCDC_VCM_DREG0 10 +#define I2C_DCDC_VCM_DREG0_MSB 4 +#define I2C_DCDC_VCM_DREG0_LSB 0 + +#define I2C_DCDC_VCM_PCUR_LIMIT0 10 +#define I2C_DCDC_VCM_PCUR_LIMIT0_MSB 7 +#define I2C_DCDC_VCM_PCUR_LIMIT0_LSB 5 + +#define I2C_DCDC_PD_DBRNO 13 +#define I2C_DCDC_PD_DBRNO_MSB 7 +#define I2C_DCDC_PD_DBRNO_LSB 7 diff --git a/components/soc/esp32h21/include/soc/regi2c_lp_bias.h b/components/soc/esp32h21/include/soc/regi2c_lp_bias.h index 1763e03718..48e7a2fa4c 100644 --- a/components/soc/esp32h21/include/soc/regi2c_lp_bias.h +++ b/components/soc/esp32h21/include/soc/regi2c_lp_bias.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -18,6 +18,22 @@ #define I2C_ULP 0x61 #define I2C_ULP_HOSTID 0 -#define I2C_ULP_IR_RESETB 0 -#define I2C_ULP_IR_RESETB_MSB 0 -#define I2C_ULP_IR_RESETB_LSB 0 +#define I2C_ULP_OCODE 4 +#define I2C_ULP_OCODE_MSB 7 +#define I2C_ULP_OCODE_LSB 0 + +#define I2C_ULP_IR_FORCE_CODE 5 +#define I2C_ULP_IR_FORCE_CODE_MSB 3 +#define I2C_ULP_IR_FORCE_CODE_LSB 3 + +#define I2C_ULP_EXT_CODE 6 +#define I2C_ULP_EXT_CODE_MSB 7 +#define I2C_ULP_EXT_CODE_LSB 0 + +#define I2C_ULP_CPREG_DREG 8 +#define I2C_ULP_CPREG_DREG_MSB 2 +#define I2C_ULP_CPREG_DREG_LSB 0 + +#define I2C_ULP_CPREG_DREG1P1 8 +#define I2C_ULP_CPREG_DREG1P1_MSB 4 +#define I2C_ULP_CPREG_DREG1P1_LSB 3 diff --git a/components/soc/esp32h21/include/soc/regi2c_pmu.h b/components/soc/esp32h21/include/soc/regi2c_pmu.h deleted file mode 100644 index 32b720eda8..0000000000 --- a/components/soc/esp32h21/include/soc/regi2c_pmu.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 OR MIT - */ - -#pragma once - -/** - * @file regi2c_pmu.h - * @brief Register definitions for digital to get rtc voltage & digital voltage - * by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration. - */ - -#define I2C_PMU 0x6d -#define I2C_PMU_HOSTID 0 - -#define I2C_PMU_EN_I2C_RTC_DREG 8 -#define I2C_PMU_EN_I2C_RTC_DREG_MSB 0 -#define I2C_PMU_EN_I2C_RTC_DREG_LSB 0 - -#define I2C_PMU_EN_I2C_DIG_DREG 8 -#define I2C_PMU_EN_I2C_DIG_DREG_MSB 1 -#define I2C_PMU_EN_I2C_DIG_DREG_LSB 1 - -#define I2C_PMU_EN_I2C_RTC_DREG_SLP 8 -#define I2C_PMU_EN_I2C_RTC_DREG_SLP_MSB 2 -#define I2C_PMU_EN_I2C_RTC_DREG_SLP_LSB 2 - -#define I2C_PMU_EN_I2C_DIG_DREG_SLP 8 -#define I2C_PMU_EN_I2C_DIG_DREG_SLP_MSB 3 -#define I2C_PMU_EN_I2C_DIG_DREG_SLP_LSB 3 - -#define I2C_PMU_OR_XPD_RTC_REG 9 -#define I2C_PMU_OR_XPD_RTC_REG_MSB 4 -#define I2C_PMU_OR_XPD_RTC_REG_LSB 4 - -#define I2C_PMU_OR_XPD_DIG_REG 9 -#define I2C_PMU_OR_XPD_DIG_REG_MSB 5 -#define I2C_PMU_OR_XPD_DIG_REG_LSB 5 - -#define I2C_PMU_OC_SCK_DCAP 14 -#define I2C_PMU_OC_SCK_DCAP_MSB 7 -#define I2C_PMU_OC_SCK_DCAP_LSB 0 - -#define I2C_PMU_OR_XPD_TRX 15 -#define I2C_PMU_OR_XPD_TRX_MSB 2 -#define I2C_PMU_OR_XPD_TRX_LSB 2 - -#define I2C_PMU_SEL_PLL8M_REF 21 -#define I2C_PMU_SEL_PLL8M_REF_MSB 6 -#define I2C_PMU_SEL_PLL8M_REF_LSB 6 diff --git a/components/soc/esp32h21/register/soc/lp_aon_reg.h b/components/soc/esp32h21/register/soc/lp_aon_reg.h index afbbb5b67b..de12fefac6 100644 --- a/components/soc/esp32h21/register/soc/lp_aon_reg.h +++ b/components/soc/esp32h21/register/soc/lp_aon_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -453,18 +453,26 @@ extern "C" { #define LP_AON_LINK_ADDR_AON_S 0 /** LP_AON_DATE_REG register - * need_des + * reserved */ #define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) -/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 38814352; +/** LP_AON_CLK_EN : R/W; bitpos: [5]; default: 0; + * 0: DREG_LDO control by SW; + * 1: DREG_LDO control by HW; + */ +#define LP_AON_DREG_LDO_HW BIT(5) +#define LP_AON_DREG_LDO_HW_M (LP_AON_DREG_LDO_HW_V << LP_AON_DREG_LDO_HW_S) +#define LP_AON_DREG_LDO_HW_V 0x00000001U +#define LP_AON_DREG_LDO_HW_S 5 +/** LP_AON_IO_LDO_ADJUST_SW : R/W; bitpos: [14:11]; default: 8; * need_des */ -#define LP_AON_DATE 0x7FFFFFFFU -#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S) -#define LP_AON_DATE_V 0x7FFFFFFFU -#define LP_AON_DATE_S 0 +#define LP_AON_DREG_LDO_SW 0x0000000FU +#define LP_AON_DREG_LDO_SW_M (LP_AON_DREG_LDO_SW_V << LP_AON_DREG_LDO_SW_S) +#define LP_AON_DREG_LDO_SW_V 0x0000000FU +#define LP_AON_DREG_LDO_SW_S 11 /** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0; - * need_des + * version register */ #define LP_AON_CLK_EN (BIT(31)) #define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S) diff --git a/components/soc/esp32h21/register/soc/lp_aon_struct.h b/components/soc/esp32h21/register/soc/lp_aon_struct.h index 522591efab..5e861fe42b 100644 --- a/components/soc/esp32h21/register/soc/lp_aon_struct.h +++ b/components/soc/esp32h21/register/soc/lp_aon_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -435,12 +435,21 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [30:0]; default: 38814352; - * need_des + uint32_t reserved_0:5; + /** aon_dreg_ldo_hw : R/W; bitpos: [5]; default: 0; + * control the ldo of dreg by hw or sw + * 0: DREG_LDO control by SW; + * 1: DREG_LDO control by HW; */ - uint32_t aon_date:31; + uint32_t aon_dreg_ldo_hw:1; + uint32_t reserved_6:5; + /** aon_dreg_ldo_sw : R/W; bitpos: [14:11]; default: 8; + * control the ldo of dreg by sw + */ + uint32_t aon_dreg_ldo_sw:4; + uint32_t reserved_7:16; /** aon_clk_en : R/W; bitpos: [31]; default: 0; - * need_des + * version register */ uint32_t aon_clk_en:1; }; diff --git a/components/soc/esp32h4/include/soc/regi2c_dcdc.h b/components/soc/esp32h4/include/soc/regi2c_dcdc.h index 9c40d352da..9b3d818cf4 100644 --- a/components/soc/esp32h4/include/soc/regi2c_dcdc.h +++ b/components/soc/esp32h4/include/soc/regi2c_dcdc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ diff --git a/components/soc/esp32h4/register/soc/lp_aon_reg.h b/components/soc/esp32h4/register/soc/lp_aon_reg.h index 5608544f51..25c493e242 100644 --- a/components/soc/esp32h4/register/soc/lp_aon_reg.h +++ b/components/soc/esp32h4/register/soc/lp_aon_reg.h @@ -675,16 +675,14 @@ extern "C" { #define LP_AON_DREG_LDO_HW BIT(5) #define LP_AON_DREG_LDO_HW_M (LP_AON_DREG_LDO_HW_V << LP_AON_DREG_LDO_HW_S) #define LP_AON_DREG_LDO_HW_V 0x00000001U -#define LP_AON_DREG_LDO_HW_S 31 - -/** LP_AON_IO_LDO_ADJUST_SW : R/W; bitpos: [30:23]; default: 0; +#define LP_AON_DREG_LDO_HW_S 5 +/** LP_AON_IO_LDO_ADJUST_SW : R/W; bitpos: [14:11]; default: 8; * need_des */ #define LP_AON_DREG_LDO_SW 0x0000000FU #define LP_AON_DREG_LDO_SW_M (LP_AON_DREG_LDO_SW_V << LP_AON_DREG_LDO_SW_S) #define LP_AON_DREG_LDO_SW_V 0x0000000FU #define LP_AON_DREG_LDO_SW_S 11 - /** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0; * version register */ diff --git a/components/soc/esp32h4/register/soc/lp_aon_struct.h b/components/soc/esp32h4/register/soc/lp_aon_struct.h index bd54333983..3faf6bf995 100644 --- a/components/soc/esp32h4/register/soc/lp_aon_struct.h +++ b/components/soc/esp32h4/register/soc/lp_aon_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -598,9 +598,9 @@ typedef union { } lp_aon_puf_conf_reg_t; /** Type of aon_date register - * reserved + * need_des */ -typedef union { + typedef union { struct { uint32_t reserved_0:5; /** aon_dreg_ldo_hw : R/W; bitpos: [5]; default: 0; @@ -609,11 +609,12 @@ typedef union { * 1: DREG_LDO control by HW; */ uint32_t aon_dreg_ldo_hw:1; - uint32_t reserved_6:17; - /** aon_dreg_ldo_sw : R/W; bitpos: [30:23]; default: 0; - * control the ldo of dreg by sw - */ - uint32_t aon_dreg_ldo_sw:8; + uint32_t reserved_6:5; + /** aon_dreg_ldo_sw : R/W; bitpos: [14:11]; default: 8; + * control the ldo of dreg by sw + */ + uint32_t aon_dreg_ldo_sw:4; + uint32_t reserved_7:16; /** aon_clk_en : R/W; bitpos: [31]; default: 0; * version register */