From 67a62f45ceecc643662dcd7997ff66843216c809 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Mon, 8 Dec 2025 17:06:17 +0800 Subject: [PATCH] fix(esp_system): fix rom secure boot fast wake feature for c5/c6/h2/h21 --- .../subproject/main/bootloader_start.c | 2 ++ .../src/bootloader_common_loader.c | 10 +++++++++- components/esp_rom/esp32c5/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32c5/esp_rom_caps.h | 1 + components/esp_rom/esp32c6/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32c6/esp_rom_caps.h | 1 + components/esp_rom/esp32h2/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32h2/esp_rom_caps.h | 1 + components/esp_rom/esp32h21/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32h21/esp_rom_caps.h | 1 + components/esp_system/ld/ld.common | 9 +++++++++ components/heap/port/esp32c5/memory_layout.c | 17 +++++++++++++++-- components/heap/port/esp32c6/memory_layout.c | 16 ++++++++++++++-- components/heap/port/esp32h2/memory_layout.c | 16 ++++++++++++++-- components/heap/port/esp32h21/memory_layout.c | 17 ++++++++++++++--- 15 files changed, 97 insertions(+), 10 deletions(-) diff --git a/components/bootloader/subproject/main/bootloader_start.c b/components/bootloader/subproject/main/bootloader_start.c index 64d80c77c9..147c382565 100644 --- a/components/bootloader/subproject/main/bootloader_start.c +++ b/components/bootloader/subproject/main/bootloader_start.c @@ -4,8 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ #include +#include "sdkconfig.h" #include "esp_log.h" #include "esp_rom_sys.h" +#include "esp_rom_caps.h" #include "bootloader_init.h" #include "bootloader_utility.h" #include "bootloader_common.h" diff --git a/components/bootloader_support/src/bootloader_common_loader.c b/components/bootloader_support/src/bootloader_common_loader.c index b46e43f4bd..058037df54 100644 --- a/components/bootloader_support/src/bootloader_common_loader.c +++ b/components/bootloader_support/src/bootloader_common_loader.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,9 @@ #include "esp_rom_crc.h" #include "esp_rom_gpio.h" #include "esp_flash_partitions.h" +#if CONFIG_SECURE_BOOT +#include "esp_secure_boot.h" +#endif #include "bootloader_flash.h" #include "bootloader_common.h" #include "soc/gpio_periph.h" @@ -274,7 +277,12 @@ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void) #define RETAIN_MEM_SIZE ALIGN_UP(sizeof(rtc_retain_mem_t), 8) #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_HIGH - RETAIN_MEM_SIZE) #endif //ESP_ROM_HAS_LP_ROM + +#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP + static rtc_retain_mem_t *const s_bootloader_retain_mem = (rtc_retain_mem_t *)RTC_RETAIN_MEM_ADDR - ESP_SECURE_BOOT_DIGEST_LEN; +#else static rtc_retain_mem_t *const s_bootloader_retain_mem = (rtc_retain_mem_t *)RTC_RETAIN_MEM_ADDR; +#endif return s_bootloader_retain_mem; #else static __attribute__((section(".bootloader_data_rtc_mem"))) rtc_retain_mem_t s_bootloader_retain_mem; diff --git a/components/esp_rom/esp32c5/Kconfig.soc_caps.in b/components/esp_rom/esp32c5/Kconfig.soc_caps.in index 0092c8f37e..f475909a2a 100644 --- a/components/esp_rom/esp32c5/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c5/Kconfig.soc_caps.in @@ -122,3 +122,7 @@ config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY config ESP_ROM_DELAY_US_PATCH bool default y + +config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP + bool + default y diff --git a/components/esp_rom/esp32c5/esp_rom_caps.h b/components/esp_rom/esp32c5/esp_rom_caps.h index 2d0fd6829e..1812656eb2 100644 --- a/components/esp_rom/esp32c5/esp_rom_caps.h +++ b/components/esp_rom/esp32c5/esp_rom_caps.h @@ -36,3 +36,4 @@ #define ESP_ROM_CLIC_INT_THRESH_PATCH (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access. #define ESP_ROM_DELAY_US_PATCH (1) // ROM ets_delay_us needs patch for U-mode operation +#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature diff --git a/components/esp_rom/esp32c6/Kconfig.soc_caps.in b/components/esp_rom/esp32c6/Kconfig.soc_caps.in index 45540e3414..2f6dba3eca 100644 --- a/components/esp_rom/esp32c6/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c6/Kconfig.soc_caps.in @@ -126,3 +126,7 @@ config ESP_ROM_NO_USB_SERIAL_OUTPUT_API config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY bool default y + +config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP + bool + default y diff --git a/components/esp_rom/esp32c6/esp_rom_caps.h b/components/esp_rom/esp32c6/esp_rom_caps.h index 1edcc24b96..1bd42f0899 100644 --- a/components/esp_rom/esp32c6/esp_rom_caps.h +++ b/components/esp_rom/esp32c6/esp_rom_caps.h @@ -37,3 +37,4 @@ #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) #define ESP_ROM_NO_USB_SERIAL_OUTPUT_API (1) // ROM does not export the usb-serial-jtag write char function #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access. +#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature diff --git a/components/esp_rom/esp32h2/Kconfig.soc_caps.in b/components/esp_rom/esp32h2/Kconfig.soc_caps.in index c1166324a1..57dae80a53 100644 --- a/components/esp_rom/esp32h2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h2/Kconfig.soc_caps.in @@ -118,3 +118,7 @@ config ESP_ROM_NO_USB_SERIAL_OUTPUT_API config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY bool default y + +config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP + bool + default y diff --git a/components/esp_rom/esp32h2/esp_rom_caps.h b/components/esp_rom/esp32h2/esp_rom_caps.h index 38e0777b98..cb9475c9ea 100644 --- a/components/esp_rom/esp32h2/esp_rom_caps.h +++ b/components/esp_rom/esp32h2/esp_rom_caps.h @@ -35,3 +35,4 @@ #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) #define ESP_ROM_NO_USB_SERIAL_OUTPUT_API (1) // ROM does not export the usb-serial-jtag write char function #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access. +#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature diff --git a/components/esp_rom/esp32h21/Kconfig.soc_caps.in b/components/esp_rom/esp32h21/Kconfig.soc_caps.in index e455d4e363..d7f1e52541 100644 --- a/components/esp_rom/esp32h21/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h21/Kconfig.soc_caps.in @@ -98,3 +98,7 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY bool default y + +config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP + bool + default y diff --git a/components/esp_rom/esp32h21/esp_rom_caps.h b/components/esp_rom/esp32h21/esp_rom_caps.h index 6dc77b3576..95e5fefff2 100644 --- a/components/esp_rom/esp32h21/esp_rom_caps.h +++ b/components/esp_rom/esp32h21/esp_rom_caps.h @@ -31,3 +31,4 @@ // #define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep. //TODO: [ESP32H21] IDF-11515 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access. +#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature diff --git a/components/esp_system/ld/ld.common b/components/esp_system/ld/ld.common index dfe698e4df..2af596f33e 100644 --- a/components/esp_system/ld/ld.common +++ b/components/esp_system/ld/ld.common @@ -11,6 +11,13 @@ /* CPU instruction prefetch padding size for flash mmap scenario */ #define _esp_flash_mmap_prefetch_pad_size 16 +/* Copy from esp_secure_boot.h */ +#ifdef CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS +#define ESP_SECURE_BOOT_DIGEST_LEN 48 +#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */ +#define ESP_SECURE_BOOT_DIGEST_LEN 32 +#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */ + /* * PMP region granularity size * Software may determine the PMP granularity by writing zero to pmp0cfg, then writing all ones @@ -70,6 +77,8 @@ has the required alignment */ #define ULP_ALIGNMENT_REQ_BYTES 256 #define RESERVE_RTC_MEM ALIGN_UP(ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC, ULP_ALIGNMENT_REQ_BYTES) + #elif CONFIG_SECURE_BOOT && CONFIG_ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP + #define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC + ESP_SECURE_BOOT_DIGEST_LEN) #else #define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC) #endif diff --git a/components/heap/port/esp32c5/memory_layout.c b/components/heap/port/esp32c5/memory_layout.c index 577ac688d0..09a92a0c23 100644 --- a/components/heap/port/esp32c5/memory_layout.c +++ b/components/heap/port/esp32c5/memory_layout.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,6 +11,7 @@ #include "soc/soc.h" #include "heap_memory_layout.h" #include "esp_heap_caps.h" +#include "esp_rom_caps.h" #if CONFIG_SECURE_ENABLE_TEE #define SRAM_DIRAM_TEE_ORG (SOC_DIRAM_IRAM_LOW) @@ -73,6 +74,18 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor */ #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) +#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP +#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS +#define ESP_SECURE_BOOT_DIGEST_LEN 48 +#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */ +#define ESP_SECURE_BOOT_DIGEST_LEN 32 +#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */ + +#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN) +#else +#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH) +#endif + const soc_memory_region_t soc_memory_regions[] = { #if CONFIG_SPIRAM { SOC_EXTRAM_DATA_LOW, (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW), SOC_MEMORY_TYPE_SPIRAM, 0, false}, //SPI SRAM, if available @@ -80,7 +93,7 @@ const soc_memory_region_t soc_memory_regions[] = { { SOC_DIRAM_DRAM_LOW, (APP_USABLE_DRAM_END - SOC_DIRAM_DRAM_LOW), SOC_MEMORY_TYPE_RAM, SOC_DIRAM_IRAM_LOW, false}, //D/IRAM, can be used as trace memory { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH - APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM, can be used as trace memory (ROM reserved area) #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP - { SOC_RTC_DATA_LOW, (SOC_RTC_DATA_HIGH - SOC_RTC_DATA_LOW), SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM + { SOC_RTC_DATA_LOW, (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW), SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM #endif }; diff --git a/components/heap/port/esp32c6/memory_layout.c b/components/heap/port/esp32c6/memory_layout.c index 05dadf5714..1610aa8245 100644 --- a/components/heap/port/esp32c6/memory_layout.c +++ b/components/heap/port/esp32c6/memory_layout.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,6 +11,7 @@ #include "soc/soc.h" #include "heap_memory_layout.h" #include "esp_heap_caps.h" +#include "esp_rom_caps.h" #if CONFIG_SECURE_ENABLE_TEE #define SRAM_DIRAM_TEE_ORG (SOC_DIRAM_IRAM_LOW) @@ -71,6 +72,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor */ #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) +#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP +#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS +#define ESP_SECURE_BOOT_DIGEST_LEN 48 +#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */ +#define ESP_SECURE_BOOT_DIGEST_LEN 32 +#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */ +#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN) +#else +#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH) +#endif + const soc_memory_region_t soc_memory_regions[] = { { 0x40800000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level0, can be used as trace memory { 0x40820000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40820000, false}, //D/IRAM level1, can be used as trace memory @@ -78,7 +90,7 @@ const soc_memory_region_t soc_memory_regions[] = { { 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_RAM, 0x40860000, false}, //D/IRAM level3, can be used as trace memory { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level3, can be used as trace memory (ROM reserved area) #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP - { 0x50000000, 0x4000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM + { 0x50000000, (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW), SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM #endif }; diff --git a/components/heap/port/esp32h2/memory_layout.c b/components/heap/port/esp32h2/memory_layout.c index 05071759e9..7e5710ef96 100644 --- a/components/heap/port/esp32h2/memory_layout.c +++ b/components/heap/port/esp32h2/memory_layout.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,6 +11,7 @@ #include "soc/soc.h" #include "heap_memory_layout.h" #include "esp_heap_caps.h" +#include "esp_rom_caps.h" #if CONFIG_SECURE_ENABLE_TEE #define SRAM_DIRAM_TEE_ORG (SOC_DIRAM_IRAM_LOW) @@ -69,6 +70,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor */ #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) +#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP +#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS +#define ESP_SECURE_BOOT_DIGEST_LEN 48 +#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */ +#define ESP_SECURE_BOOT_DIGEST_LEN 32 +#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */ +#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN) +#else +#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH) +#endif + const soc_memory_region_t soc_memory_regions[] = { { 0x40800000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level 0 { 0x40810000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40810000, false}, //D/IRAM level 1 @@ -77,7 +89,7 @@ const soc_memory_region_t soc_memory_regions[] = { { 0x40840000, APP_USABLE_DRAM_END-0x40840000, SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level 4 { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level 4 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP - { 0x50000000, 0x1000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory + { 0x50000000, (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW),SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory #endif }; diff --git a/components/heap/port/esp32h21/memory_layout.c b/components/heap/port/esp32h21/memory_layout.c index 9f4cdc0642..1263fdeec5 100644 --- a/components/heap/port/esp32h21/memory_layout.c +++ b/components/heap/port/esp32h21/memory_layout.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,7 +11,7 @@ #include "soc/soc.h" #include "heap_memory_layout.h" #include "esp_heap_caps.h" - +#include "esp_rom_caps.h" /** * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC. @@ -65,6 +65,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor */ #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) +#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP +#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS +#define ESP_SECURE_BOOT_DIGEST_LEN 48 +#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */ +#define ESP_SECURE_BOOT_DIGEST_LEN 32 +#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */ +#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN) +#else +#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH) +#endif + const soc_memory_region_t soc_memory_regions[] = { { 0x40800000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level 0 { 0x40810000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40810000, false}, //D/IRAM level 1 @@ -73,7 +84,7 @@ const soc_memory_region_t soc_memory_regions[] = { { 0x40840000, APP_USABLE_DRAM_END-0x40840000, SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level 4 { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level 4 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP - { 0x50000000, 0x1000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory + { 0x50000000, (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW),SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory #endif };