From 6bd852411564e503bf8f9bfb0a1715841770342c Mon Sep 17 00:00:00 2001 From: morris Date: Wed, 12 Nov 2025 18:09:08 +0800 Subject: [PATCH] feat(etm): support ETM driver on esp32h21 --- .../test_apps/i2s/main/test_i2s_etm.c | 8 +- components/esp_hw_support/etm/esp_etm.c | 18 +-- .../main/test_etm_core.c | 12 +- components/hal/CMakeLists.txt | 2 +- components/{soc => hal}/esp32c5/etm_periph.c | 2 +- components/hal/esp32c5/include/hal/etm_ll.h | 16 ++- components/{soc => hal}/esp32c6/etm_periph.c | 2 +- components/hal/esp32c6/include/hal/etm_ll.h | 11 +- components/{soc => hal}/esp32c61/etm_periph.c | 2 +- components/hal/esp32c61/include/hal/etm_ll.h | 16 ++- components/{soc => hal}/esp32h2/etm_periph.c | 2 +- components/hal/esp32h2/include/hal/etm_ll.h | 11 +- .../esp32h4 => hal/esp32h21}/etm_periph.c | 2 +- components/hal/esp32h21/include/hal/etm_ll.h | 126 ++++++++++++++++ .../hal/esp32h21/include/hal/gpio_etm_ll.h | 136 ++++++++++++++++++ components/hal/esp32h4/etm_periph.c | 44 ++++++ components/hal/esp32h4/include/hal/etm_ll.h | 14 +- components/{soc => hal}/esp32p4/etm_periph.c | 2 +- components/hal/esp32p4/include/hal/etm_ll.h | 14 +- .../soc => hal/include/hal}/etm_periph.h | 11 +- components/soc/CMakeLists.txt | 4 - .../soc/esp32c5/include/soc/soc_caps_full.h | 4 - .../soc/esp32c6/include/soc/soc_caps_full.h | 4 - .../soc/esp32c61/include/soc/soc_caps_full.h | 4 - .../soc/esp32h2/include/soc/soc_caps_full.h | 4 - .../esp32h21/include/soc/Kconfig.soc_caps.in | 20 +++ .../soc/esp32h21/include/soc/soc_caps.h | 10 +- .../soc/esp32h21/include/soc/soc_caps_full.h | 4 - .../soc/esp32h21/ld/esp32h21.peripherals.ld | 1 + .../esp32h21/register/soc/gpio_ext_struct.h | 19 ++- .../esp32h21/register/soc/soc_etm_struct.h | 2 +- .../soc/esp32h4/include/soc/soc_caps_full.h | 4 - .../soc/esp32p4/include/soc/soc_caps_full.h | 4 - docs/docs_not_updated/esp32h21.txt | 1 - .../peripherals/ledc/ledc_dimmer/README.md | 4 +- .../gptimer_capture_hc_sr04/README.md | 4 +- 36 files changed, 448 insertions(+), 96 deletions(-) rename components/{soc => hal}/esp32c5/etm_periph.c (98%) rename components/{soc => hal}/esp32c6/etm_periph.c (98%) rename components/{soc => hal}/esp32c61/etm_periph.c (98%) rename components/{soc => hal}/esp32h2/etm_periph.c (98%) rename components/{soc/esp32h4 => hal/esp32h21}/etm_periph.c (98%) create mode 100644 components/hal/esp32h21/include/hal/etm_ll.h create mode 100644 components/hal/esp32h21/include/hal/gpio_etm_ll.h create mode 100644 components/hal/esp32h4/etm_periph.c rename components/{soc => hal}/esp32p4/etm_periph.c (98%) rename components/{soc/include/soc => hal/include/hal}/etm_periph.h (75%) diff --git a/components/esp_driver_i2s/test_apps/i2s/main/test_i2s_etm.c b/components/esp_driver_i2s/test_apps/i2s/main/test_i2s_etm.c index 603dd9d8d2..01bf1cf806 100644 --- a/components/esp_driver_i2s/test_apps/i2s/main/test_i2s_etm.c +++ b/components/esp_driver_i2s/test_apps/i2s/main/test_i2s_etm.c @@ -28,7 +28,7 @@ static i2s_chan_handle_t s_tx_handle = NULL; static i2s_chan_handle_t s_rx_handle = NULL; -#if ETM_LL_SUPPORT_STATUS +#if ETM_LL_SUPPORT(STATUS_REG) static void s_i2s_etm_check_status(void) { i2s_dev_t *hw = I2S_LL_GET_HW(0); @@ -44,7 +44,7 @@ static void s_i2s_etm_check_status(void) TEST_ASSERT(is_tx_reach_thresh); TEST_ASSERT(is_rx_reach_thresh); } -#endif // ETM_LL_SUPPORT_STATUS +#endif // ETM_LL_SUPPORT(STATUS_REG) static void s_i2s_init(void *buf) { @@ -133,11 +133,11 @@ TEST_CASE("i2s_etm_event_test", "[etm]") TEST_ESP_OK(i2s_channel_read(s_rx_handle, buf, TEST_BUFF_SIZE, NULL, portMAX_DELAY)); -#if ETM_LL_SUPPORT_STATUS +#if ETM_LL_SUPPORT(STATUS_REG) s_i2s_etm_check_status(); #else TEST_ASSERT(gpio_get_level(TEST_GPIO_ETM_NUM)); -#endif // ETM_LL_SUPPORT_STATUS +#endif // ETM_LL_SUPPORT(STATUS_REG) /* Test finished, free the resources */ TEST_ESP_OK(i2s_channel_disable(s_rx_handle)); diff --git a/components/esp_hw_support/etm/esp_etm.c b/components/esp_hw_support/etm/esp_etm.c index 8ee03a9b8b..907eb9e2c2 100644 --- a/components/esp_hw_support/etm/esp_etm.c +++ b/components/esp_hw_support/etm/esp_etm.c @@ -16,7 +16,7 @@ #endif #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "soc/etm_periph.h" +#include "hal/etm_periph.h" #include "esp_log.h" #include "esp_check.h" #include "esp_heap_caps.h" @@ -46,16 +46,16 @@ typedef struct etm_group_t etm_group_t; typedef struct esp_etm_channel_t esp_etm_channel_t; struct etm_platform_t { - _lock_t mutex; // platform level mutex lock - etm_group_t *groups[SOC_ETM_ATTR(INST_NUM)]; // etm group pool - int group_ref_counts[SOC_ETM_ATTR(INST_NUM)]; // reference count used to protect group install/uninstall + _lock_t mutex; // platform level mutex lock + etm_group_t *groups[ETM_LL_GET(INST_NUM)]; // etm group pool + int group_ref_counts[ETM_LL_GET(INST_NUM)]; // reference count used to protect group install/uninstall }; struct etm_group_t { int group_id; // hardware group id etm_hal_context_t hal; // hardware abstraction layer context portMUX_TYPE spinlock; // to protect per-group light weight resource access - esp_etm_channel_t *chans[SOC_ETM_ATTR(CHANS_PER_INST)]; // array of channels in the group + esp_etm_channel_t *chans[ETM_LL_GET(CHANS_PER_INST)]; // array of channels in the group }; typedef enum { @@ -198,12 +198,12 @@ static esp_err_t etm_chan_register_to_group(esp_etm_channel_t *chan) { etm_group_t *group = NULL; int chan_id = -1; - for (int i = 0; i < SOC_ETM_ATTR(INST_NUM); i++) { + for (int i = 0; i < ETM_LL_GET(INST_NUM); i++) { group = etm_acquire_group_handle(i); ESP_RETURN_ON_FALSE(group, ESP_ERR_NO_MEM, TAG, "no mem for group (%d)", i); // loop to search free channel in the group esp_os_enter_critical(&group->spinlock); - for (int j = 0; j < SOC_ETM_ATTR(CHANS_PER_INST); j++) { + for (int j = 0; j < ETM_LL_GET(CHANS_PER_INST); j++) { if (!group->chans[j]) { chan_id = j; group->chans[j] = chan; @@ -405,11 +405,11 @@ esp_err_t esp_etm_dump(FILE *out_stream) fprintf(out_stream, "===========ETM Dump Start==========\r\n"); char line[80]; size_t len = sizeof(line); - for (int i = 0; i < SOC_ETM_ATTR(INST_NUM); i++) { + for (int i = 0; i < ETM_LL_GET(INST_NUM); i++) { group = etm_acquire_group_handle(i); ESP_RETURN_ON_FALSE(group, ESP_ERR_NO_MEM, TAG, "no mem for group (%d)", i); etm_hal_context_t *hal = &group->hal; - for (int j = 0; j < SOC_ETM_ATTR(CHANS_PER_INST); j++) { + for (int j = 0; j < ETM_LL_GET(CHANS_PER_INST); j++) { bool print_line = true; esp_os_enter_critical(&group->spinlock); etm_chan = group->chans[j]; diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_etm_core.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_etm_core.c index 7454ef2fb7..2b515210ee 100644 --- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_etm_core.c +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_etm_core.c @@ -10,15 +10,15 @@ #include "freertos/task.h" #include "unity.h" #include "esp_etm.h" -#include "soc/etm_periph.h" +#include "hal/etm_periph.h" TEST_CASE("etm_channel_install_uninstall", "[etm]") { printf("install etm channels exhaustively\r\n"); - esp_etm_channel_handle_t etm_chans[SOC_ETM_ATTR(INST_NUM)][SOC_ETM_ATTR(CHANS_PER_INST)]; + esp_etm_channel_handle_t etm_chans[ETM_LL_GET(INST_NUM)][ETM_LL_GET(CHANS_PER_INST)]; esp_etm_channel_config_t config = {}; - for (int i = 0; i < SOC_ETM_ATTR(INST_NUM); i++) { - for (int j = 0; j < SOC_ETM_ATTR(CHANS_PER_INST); j++) { + for (int i = 0; i < ETM_LL_GET(INST_NUM); i++) { + for (int j = 0; j < ETM_LL_GET(CHANS_PER_INST); j++) { TEST_ESP_OK(esp_etm_new_channel(&config, &etm_chans[i][j])); } TEST_ESP_ERR(ESP_ERR_NOT_FOUND, esp_etm_new_channel(&config, &etm_chans[0][0])); @@ -30,8 +30,8 @@ TEST_CASE("etm_channel_install_uninstall", "[etm]") TEST_ESP_ERR(ESP_ERR_INVALID_STATE, esp_etm_del_channel(etm_chans[0][0])); TEST_ESP_OK(esp_etm_channel_disable(etm_chans[0][0])); - for (int i = 0; i < SOC_ETM_ATTR(INST_NUM); i++) { - for (int j = 0; j < SOC_ETM_ATTR(CHANS_PER_INST); j++) { + for (int i = 0; i < ETM_LL_GET(INST_NUM); i++) { + for (int j = 0; j < ETM_LL_GET(CHANS_PER_INST); j++) { TEST_ESP_OK(esp_etm_del_channel(etm_chans[i][j])); } } diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index e73532a31b..23cad4af03 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -136,7 +136,7 @@ elseif(NOT BOOTLOADER_BUILD) endif() if(CONFIG_SOC_ETM_SUPPORTED) - list(APPEND srcs "etm_hal.c") + list(APPEND srcs "etm_hal.c" "${target}/etm_periph.c") endif() if(CONFIG_SOC_PARLIO_SUPPORTED) diff --git a/components/soc/esp32c5/etm_periph.c b/components/hal/esp32c5/etm_periph.c similarity index 98% rename from components/soc/esp32c5/etm_periph.c rename to components/hal/esp32c5/etm_periph.c index ea6b2ab7c4..afc54dbc54 100644 --- a/components/soc/esp32c5/etm_periph.c +++ b/components/hal/esp32c5/etm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/etm_periph.h" +#include "hal/etm_periph.h" #include "soc/soc_etm_reg.h" /** diff --git a/components/hal/esp32c5/include/hal/etm_ll.h b/components/hal/esp32c5/include/hal/etm_ll.h index ebed4861b5..7b03876980 100644 --- a/components/hal/esp32c5/include/hal/etm_ll.h +++ b/components/hal/esp32c5/include/hal/etm_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,12 +14,22 @@ #include "soc/soc_etm_struct.h" #include "soc/pcr_struct.h" +#define ETM_LL_GET(_attr) ETM_LL_ ## _attr +#define ETM_LL_SUPPORT(_feat) ETM_LL_SUPPORT_ ## _feat + +// Number of ETM instances +#define ETM_LL_INST_NUM 1 + +// Number of channels in each ETM instance +#define ETM_LL_CHANS_PER_INST 50 + +// Support to get and clear the status of the ETM event and task +#define ETM_LL_SUPPORT_STATUS_REG 1 + #ifdef __cplusplus extern "C" { #endif -#define ETM_LL_SUPPORT_STATUS 1 // Support to get and clear the status of the ETM event and task - /** * @brief Enable the clock for ETM register * diff --git a/components/soc/esp32c6/etm_periph.c b/components/hal/esp32c6/etm_periph.c similarity index 98% rename from components/soc/esp32c6/etm_periph.c rename to components/hal/esp32c6/etm_periph.c index ea6b2ab7c4..afc54dbc54 100644 --- a/components/soc/esp32c6/etm_periph.c +++ b/components/hal/esp32c6/etm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/etm_periph.h" +#include "hal/etm_periph.h" #include "soc/soc_etm_reg.h" /** diff --git a/components/hal/esp32c6/include/hal/etm_ll.h b/components/hal/esp32c6/include/hal/etm_ll.h index e77bfeec5f..5338ccbebd 100644 --- a/components/hal/esp32c6/include/hal/etm_ll.h +++ b/components/hal/esp32c6/include/hal/etm_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,6 +14,15 @@ #include "soc/soc_etm_struct.h" #include "soc/pcr_struct.h" +#define ETM_LL_GET(_attr) ETM_LL_ ## _attr +#define ETM_LL_SUPPORT(_feat) ETM_LL_SUPPORT_ ## _feat + +// Number of ETM instances +#define ETM_LL_INST_NUM 1 + +// Number of channels in each ETM instance +#define ETM_LL_CHANS_PER_INST 50 + #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32c61/etm_periph.c b/components/hal/esp32c61/etm_periph.c similarity index 98% rename from components/soc/esp32c61/etm_periph.c rename to components/hal/esp32c61/etm_periph.c index ea6b2ab7c4..afc54dbc54 100644 --- a/components/soc/esp32c61/etm_periph.c +++ b/components/hal/esp32c61/etm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/etm_periph.h" +#include "hal/etm_periph.h" #include "soc/soc_etm_reg.h" /** diff --git a/components/hal/esp32c61/include/hal/etm_ll.h b/components/hal/esp32c61/include/hal/etm_ll.h index ebed4861b5..7b03876980 100644 --- a/components/hal/esp32c61/include/hal/etm_ll.h +++ b/components/hal/esp32c61/include/hal/etm_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,12 +14,22 @@ #include "soc/soc_etm_struct.h" #include "soc/pcr_struct.h" +#define ETM_LL_GET(_attr) ETM_LL_ ## _attr +#define ETM_LL_SUPPORT(_feat) ETM_LL_SUPPORT_ ## _feat + +// Number of ETM instances +#define ETM_LL_INST_NUM 1 + +// Number of channels in each ETM instance +#define ETM_LL_CHANS_PER_INST 50 + +// Support to get and clear the status of the ETM event and task +#define ETM_LL_SUPPORT_STATUS_REG 1 + #ifdef __cplusplus extern "C" { #endif -#define ETM_LL_SUPPORT_STATUS 1 // Support to get and clear the status of the ETM event and task - /** * @brief Enable the clock for ETM register * diff --git a/components/soc/esp32h2/etm_periph.c b/components/hal/esp32h2/etm_periph.c similarity index 98% rename from components/soc/esp32h2/etm_periph.c rename to components/hal/esp32h2/etm_periph.c index ea6b2ab7c4..afc54dbc54 100644 --- a/components/soc/esp32h2/etm_periph.c +++ b/components/hal/esp32h2/etm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/etm_periph.h" +#include "hal/etm_periph.h" #include "soc/soc_etm_reg.h" /** diff --git a/components/hal/esp32h2/include/hal/etm_ll.h b/components/hal/esp32h2/include/hal/etm_ll.h index 210933eaba..b4745a782f 100644 --- a/components/hal/esp32h2/include/hal/etm_ll.h +++ b/components/hal/esp32h2/include/hal/etm_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,6 +14,15 @@ #include "soc/soc_etm_struct.h" #include "soc/pcr_struct.h" +#define ETM_LL_GET(_attr) ETM_LL_ ## _attr +#define ETM_LL_SUPPORT(_feat) ETM_LL_SUPPORT_ ## _feat + +// Number of ETM instances +#define ETM_LL_INST_NUM 1 + +// Number of channels in each ETM instance +#define ETM_LL_CHANS_PER_INST 50 + #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32h4/etm_periph.c b/components/hal/esp32h21/etm_periph.c similarity index 98% rename from components/soc/esp32h4/etm_periph.c rename to components/hal/esp32h21/etm_periph.c index 9f44803e7c..88496453b7 100644 --- a/components/soc/esp32h4/etm_periph.c +++ b/components/hal/esp32h21/etm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/etm_periph.h" +#include "hal/etm_periph.h" #include "soc/soc_etm_reg.h" /** diff --git a/components/hal/esp32h21/include/hal/etm_ll.h b/components/hal/esp32h21/include/hal/etm_ll.h new file mode 100644 index 0000000000..149c3f30ed --- /dev/null +++ b/components/hal/esp32h21/include/hal/etm_ll.h @@ -0,0 +1,126 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/soc_etm_struct.h" +#include "soc/pcr_struct.h" + +#define ETM_LL_GET(_attr) ETM_LL_ ## _attr +#define ETM_LL_SUPPORT(_feat) ETM_LL_SUPPORT_ ## _feat + +// Number of ETM instances +#define ETM_LL_INST_NUM 1 + +// Number of channels in each ETM instance +#define ETM_LL_CHANS_PER_INST 50 + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the clock for ETM register + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void etm_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + PCR.etm_conf.etm_clk_en = enable; +} + +/** + * @brief Reset the ETM register + * + * @param group_id Group ID + */ +static inline void etm_ll_reset_register(int group_id) +{ + (void)group_id; + PCR.etm_conf.etm_rst_en = 1; + PCR.etm_conf.etm_rst_en = 0; +} + +/** + * @brief Enable ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + */ +static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + hw->ch_ena_ad0_set.val = 1 << chan; + } else { + hw->ch_ena_ad1_set.val = 1 << (chan - 32); + } +} + +/** + * @brief Disable ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + */ +static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + hw->ch_ena_ad0_clr.val = 1 << chan; + } else { + hw->ch_ena_ad1_clr.val = 1 << (chan - 32); + } +} + +/** + * @brief Check whether the ETM channel is enabled or not + * + * @param hw ETM register base address + * @param chan Channel ID + * @return true if the channel is enabled, false otherwise + */ +static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + return hw->ch_ena_ad0.val & (1 << chan); + } else { + return hw->ch_ena_ad1.val & (1 << (chan - 32)); + } +} + +/** + * @brief Set the input event for the ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + * @param event Event ID + */ +static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, chn_evt_id, event); +} + +/** + * @brief Set the output task for the ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + * @param task Task ID + */ +static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, chn_task_id, task); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h21/include/hal/gpio_etm_ll.h b/components/hal/esp32h21/include/hal/gpio_etm_ll.h new file mode 100644 index 0000000000..ba4e7fd73f --- /dev/null +++ b/components/hal/esp32h21/include/hal/gpio_etm_ll.h @@ -0,0 +1,136 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/gpio_ext_struct.h" +#include "soc/soc_etm_source.h" + +#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch)) +#define GPIO_LL_ETM_EVENT_ID_NEG_EDGE(ch) (GPIO_EVT_CH0_FALL_EDGE + (ch)) +#define GPIO_LL_ETM_EVENT_ID_ANY_EDGE(ch) (GPIO_EVT_CH0_ANY_EDGE + (ch)) + +#define GPIO_LL_ETM_TASK_ID_SET(ch) (GPIO_TASK_CH0_SET + (ch)) +#define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) +#define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) + +#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set which GPIO to be bound to the event channel + * + * @note Different channels can be bound to one GPIO + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @param gpio_num GPIO number + */ +static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num) +{ + dev->etm_event_chn_cfg[chan].ext_etm_chn_event_sel = gpio_num; +} + +/** + * @brief Whether to enable the event channel + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable) +{ + dev->etm_event_chn_cfg[chan].ext_etm_chn_event_en = enable; +} + +/** + * @brief Get which GPIO is bound to the event channel + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @return GPIO number + */ +static inline uint32_t gpio_ll_etm_event_channel_get_gpio(gpio_etm_dev_t *dev, uint32_t chan) +{ + return dev->etm_event_chn_cfg[chan].ext_etm_chn_event_sel; +} + +/** + * @brief Set which GPIO to be bound to the task channel + * + * @note One channel can be bound to multiple different GPIOs + * + * @param dev Register base address + * @param chan GPIO ETM Task channel number + * @param gpio_num GPIO number + */ +static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + uint32_t reg_val = dev->etm_task_pn_cfg[g_p]; + reg_val &= ~(0x07 << (g_idx * 6)); + reg_val |= ((chan & 0x07) << (g_idx * 6)); + dev->etm_task_pn_cfg[g_p] = reg_val; +} + +/** + * @brief Whether to enable the GPIO to be managed by the task channel + * + * @param dev Register base address + * @param gpio_num GPIO number + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_etm_enable_task_gpio(gpio_etm_dev_t *dev, uint32_t gpio_num, bool enable) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + uint32_t reg_val = dev->etm_task_pn_cfg[g_p]; + reg_val &= ~(0x01 << (g_idx * 6 + 5)); + reg_val |= ((enable & 0x01) << (g_idx * 6 + 5)); + dev->etm_task_pn_cfg[g_p] = reg_val; +} + +/** + * @brief Check whether a GPIO has been enabled and managed by a task channel + * + * @param dev Register base address + * @param gpio_num GPIO number + * @return True if enabled, false otherwise + */ +static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_t gpio_num) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + return dev->etm_task_pn_cfg[g_p] & (0x01 << (g_idx * 6 + 5)); +} + +/** + * @brief Get the channel number that the GPIO is bound to + * + * @param dev Register base address + * @param gpio_num GPIO number + * @return GPIO ETM Task channel number + */ +static inline uint32_t gpio_ll_etm_gpio_get_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + return (dev->etm_task_pn_cfg[g_p] >> (g_idx * 6)) & 0x07; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h4/etm_periph.c b/components/hal/esp32h4/etm_periph.c new file mode 100644 index 0000000000..88496453b7 --- /dev/null +++ b/components/hal/esp32h4/etm_periph.c @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "hal/etm_periph.h" +#include "soc/soc_etm_reg.h" + +/** + * ETM Registers to be saved during sleep retention + * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG +*/ +#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1) + +static const regdma_entries_config_t etm_regdma_entries[] = { + // backup stage: save the status of enabled channels + // restore stage: store the enabled channels + [0] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00), + SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01), + SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02), + SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, +}; + +const soc_etm_retention_desc_t soc_etm_retention_info[1] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_ETM0, + .regdma_entry_array = etm_regdma_entries, + .array_size = ARRAY_SIZE(etm_regdma_entries) + }, +}; diff --git a/components/hal/esp32h4/include/hal/etm_ll.h b/components/hal/esp32h4/include/hal/etm_ll.h index 228a664ac1..2d5293c791 100644 --- a/components/hal/esp32h4/include/hal/etm_ll.h +++ b/components/hal/esp32h4/include/hal/etm_ll.h @@ -14,12 +14,22 @@ #include "soc/soc_etm_struct.h" #include "soc/pcr_struct.h" +#define ETM_LL_GET(_attr) ETM_LL_ ## _attr +#define ETM_LL_SUPPORT(_feat) ETM_LL_SUPPORT_ ## _feat + +// Number of ETM instances +#define ETM_LL_INST_NUM 1 + +// Number of channels in each ETM instance +#define ETM_LL_CHANS_PER_INST 50 + +// Support to get and clear the status of the ETM event and task +#define ETM_LL_SUPPORT_STATUS_REG 1 + #ifdef __cplusplus extern "C" { #endif -#define ETM_LL_SUPPORT_STATUS 1 // Support to get and clear the status of the ETM event and task - /** * @brief Enable the clock for ETM register * diff --git a/components/soc/esp32p4/etm_periph.c b/components/hal/esp32p4/etm_periph.c similarity index 98% rename from components/soc/esp32p4/etm_periph.c rename to components/hal/esp32p4/etm_periph.c index 88acc8cc77..bcc91bf669 100644 --- a/components/soc/esp32p4/etm_periph.c +++ b/components/hal/esp32p4/etm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/etm_periph.h" +#include "hal/etm_periph.h" #include "soc/soc_etm_reg.h" /** diff --git a/components/hal/esp32p4/include/hal/etm_ll.h b/components/hal/esp32p4/include/hal/etm_ll.h index b638ac2084..47ef4e2c39 100644 --- a/components/hal/esp32p4/include/hal/etm_ll.h +++ b/components/hal/esp32p4/include/hal/etm_ll.h @@ -14,12 +14,22 @@ #include "soc/soc_etm_struct.h" #include "soc/hp_sys_clkrst_struct.h" +#define ETM_LL_GET(_attr) ETM_LL_ ## _attr +#define ETM_LL_SUPPORT(_feat) ETM_LL_SUPPORT_ ## _feat + +// Number of ETM instances +#define ETM_LL_INST_NUM 1 + +// Number of channels in each ETM instance +#define ETM_LL_CHANS_PER_INST 50 + +// Support to get and clear the status of the ETM event and task +#define ETM_LL_SUPPORT_STATUS_REG 1 + #ifdef __cplusplus extern "C" { #endif -#define ETM_LL_SUPPORT_STATUS 1 // Support to get and clear the status of the ETM event and task - /** * @brief Enable the bus clock for ETM module * diff --git a/components/soc/include/soc/etm_periph.h b/components/hal/include/hal/etm_periph.h similarity index 75% rename from components/soc/include/soc/etm_periph.h rename to components/hal/include/hal/etm_periph.h index 7b64aba527..c4c7940890 100644 --- a/components/soc/include/soc/etm_periph.h +++ b/components/hal/include/hal/etm_periph.h @@ -7,16 +7,17 @@ #pragma once #include -#include "soc/soc_caps_full.h" +#include "soc/soc_caps.h" #include "soc/regdma.h" +#if SOC_HAS(ETM) +#include "hal/etm_ll.h" +#endif + #if SOC_HAS(PAU) #include "soc/retention_periph_defs.h" #endif -// helper macros to access module attributes -#define SOC_ETM_ATTR(_attr) SOC_MODULE_ATTR(ETM, _attr) - #ifdef __cplusplus extern "C" { #endif @@ -29,7 +30,7 @@ typedef struct { uint32_t array_size; // Size of the regdma_entry_array } soc_etm_retention_desc_t; -extern const soc_etm_retention_desc_t soc_etm_retention_info[SOC_ETM_ATTR(INST_NUM)]; +extern const soc_etm_retention_desc_t soc_etm_retention_info[ETM_LL_GET(INST_NUM)]; #endif // SOC_HAS(PAU) diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index 12bc810081..81312b33bc 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -81,10 +81,6 @@ if(CONFIG_SOC_DEBUG_PROBE_SUPPORTED) endif() -if(CONFIG_SOC_ETM_SUPPORTED) - list(APPEND srcs "${target_folder}/etm_periph.c") -endif() - if(CONFIG_SOC_GPSPI_SUPPORTED) list(APPEND srcs "${target_folder}/spi_periph.c") endif() diff --git a/components/soc/esp32c5/include/soc/soc_caps_full.h b/components/soc/esp32c5/include/soc/soc_caps_full.h index ad114f13eb..ac9540b2e9 100644 --- a/components/soc/esp32c5/include/soc/soc_caps_full.h +++ b/components/soc/esp32c5/include/soc/soc_caps_full.h @@ -17,10 +17,6 @@ #define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances #define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance -/*--------------------------- ETM (Event Task Matrix) ----------------------------*/ -#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances -#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance - /*------------------------------- I2S ---------------------------------------*/ // helper macros to access module attributes #define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances diff --git a/components/soc/esp32c6/include/soc/soc_caps_full.h b/components/soc/esp32c6/include/soc/soc_caps_full.h index ad114f13eb..ac9540b2e9 100644 --- a/components/soc/esp32c6/include/soc/soc_caps_full.h +++ b/components/soc/esp32c6/include/soc/soc_caps_full.h @@ -17,10 +17,6 @@ #define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances #define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance -/*--------------------------- ETM (Event Task Matrix) ----------------------------*/ -#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances -#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance - /*------------------------------- I2S ---------------------------------------*/ // helper macros to access module attributes #define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances diff --git a/components/soc/esp32c61/include/soc/soc_caps_full.h b/components/soc/esp32c61/include/soc/soc_caps_full.h index 822aab0820..d084a22c49 100644 --- a/components/soc/esp32c61/include/soc/soc_caps_full.h +++ b/components/soc/esp32c61/include/soc/soc_caps_full.h @@ -13,10 +13,6 @@ #define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ #define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ -/*--------------------------- ETM (Event Task Matrix) ----------------------------*/ -#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances -#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance - /*--------------------------- I2S CAPS ----------------------------------------*/ // helper macros to access module attributes #define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances diff --git a/components/soc/esp32h2/include/soc/soc_caps_full.h b/components/soc/esp32h2/include/soc/soc_caps_full.h index ad114f13eb..ac9540b2e9 100644 --- a/components/soc/esp32h2/include/soc/soc_caps_full.h +++ b/components/soc/esp32h2/include/soc/soc_caps_full.h @@ -17,10 +17,6 @@ #define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances #define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance -/*--------------------------- ETM (Event Task Matrix) ----------------------------*/ -#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances -#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance - /*------------------------------- I2S ---------------------------------------*/ // helper macros to access module attributes #define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index 6c9fe5ba1b..4c01c2a5e9 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -139,6 +139,10 @@ config SOC_TWAI_SUPPORTED bool default y +config SOC_ETM_SUPPORTED + bool + default y + config SOC_RMT_SUPPORTED bool default y @@ -351,6 +355,10 @@ config SOC_AHB_GDMA_VERSION int default 1 +config SOC_GDMA_SUPPORT_ETM + bool + default y + config SOC_GDMA_SUPPORT_SLEEP_RETENTION bool default y @@ -367,6 +375,10 @@ config SOC_GPIO_SUPPORT_PIN_HYS_FILTER bool default y +config SOC_GPIO_SUPPORT_ETM + bool + default y + config SOC_GPIO_SUPPORT_RTC_INDEPENDENT bool default y @@ -783,6 +795,10 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE bool default y +config SOC_SYSTIMER_SUPPORT_ETM + bool + default y + config SOC_LP_TIMER_BIT_WIDTH_LO int default 32 @@ -791,6 +807,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI int default 16 +config SOC_TIMER_SUPPORT_ETM + bool + default y + config SOC_TIMER_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 9ae287e1e3..7affe494fb 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -75,7 +75,7 @@ #define SOC_PCNT_SUPPORTED 1 // #define SOC_MCPWM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11601 #define SOC_TWAI_SUPPORTED 1 -// #define SOC_ETM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11576 +#define SOC_ETM_SUPPORTED 1 // #define SOC_PARLIO_SUPPORTED 1 //TODO: [ESP32H21] IDF-11570, IDF-11572 #define SOC_RMT_SUPPORTED 1 #define SOC_AES_SUPPORTED 1 @@ -187,7 +187,7 @@ /*-------------------------- GDMA CAPS -------------------------------------*/ #define SOC_AHB_GDMA_VERSION 1U -// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: IDF-11604 +#define SOC_GDMA_SUPPORT_ETM 1 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 /*-------------------------- GPIO CAPS ---------------------------------------*/ @@ -199,7 +199,7 @@ #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 // GPIO peripheral has the ETM extension -// #define SOC_GPIO_SUPPORT_ETM 1 +#define SOC_GPIO_SUPPORT_ETM 1 // Target has no full LP IO subsystem, GPIO5~11 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins) // Digital IOs have their own registers to control pullup/down/capability @@ -421,14 +421,14 @@ #define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source #define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) -// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event +#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event /*-------------------------- LP_TIMER CAPS ----------------------------------*/ #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part #define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ -// #define SOC_TIMER_SUPPORT_ETM (1) //TODO: [ESP32H21] IDF-11576 +#define SOC_TIMER_SUPPORT_ETM (1) #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1) /*--------------------------- WATCHDOG CAPS ---------------------------------------*/ diff --git a/components/soc/esp32h21/include/soc/soc_caps_full.h b/components/soc/esp32h21/include/soc/soc_caps_full.h index 6712b6ea04..203676a6d3 100644 --- a/components/soc/esp32h21/include/soc/soc_caps_full.h +++ b/components/soc/esp32h21/include/soc/soc_caps_full.h @@ -13,10 +13,6 @@ #define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances #define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance -/*--------------------------- ETM (Event Task Matrix) ----------------------------*/ -#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances -#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance - /*------------------------------- I2S ---------------------------------------*/ // helper macros to access module attributes #define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances diff --git a/components/soc/esp32h21/ld/esp32h21.peripherals.ld b/components/soc/esp32h21/ld/esp32h21.peripherals.ld index 85368c4a82..d7249c40b9 100644 --- a/components/soc/esp32h21/ld/esp32h21.peripherals.ld +++ b/components/soc/esp32h21/ld/esp32h21.peripherals.ld @@ -39,6 +39,7 @@ PROVIDE ( ECDSA = 0x6008E000 ); PROVIDE ( IO_MUX = 0x60090000 ); PROVIDE ( GPIO = 0x60091000 ); PROVIDE ( GPIO_EXT = 0x60091E00 ); +PROVIDE ( GPIO_ETM = 0x60091F18 ); PROVIDE ( MEM_MONITOR = 0x60092000 ); PROVIDE ( PAU = 0x60093000 ); PROVIDE ( HP_SYSTEM = 0x60095000 ); diff --git a/components/soc/esp32h21/register/soc/gpio_ext_struct.h b/components/soc/esp32h21/register/soc/gpio_ext_struct.h index dc07e35871..d0209380ad 100644 --- a/components/soc/esp32h21/register/soc/gpio_ext_struct.h +++ b/components/soc/esp32h21/register/soc/gpio_ext_struct.h @@ -145,12 +145,12 @@ typedef union { /** ext_etm_ch0_event_sel : R/W; bitpos: [4:0]; default: 0; * Etm event channel select gpio. */ - uint32_t ext_etm_ch0_event_sel:5; + uint32_t ext_etm_chn_event_sel:5; uint32_t reserved_5:2; /** ext_etm_ch0_event_en : R/W; bitpos: [7]; default: 0; * Etm event send enable bit. */ - uint32_t ext_etm_ch0_event_en:1; + uint32_t ext_etm_chn_event_en:1; uint32_t reserved_8:24; }; uint32_t val; @@ -556,6 +556,11 @@ typedef union { uint32_t val; } gpio_ext_version_reg_t; +typedef struct { + volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; + uint32_t reserved_080[8]; + volatile uint32_t etm_task_pn_cfg[6]; +} gpio_etm_dev_t; typedef struct { uint32_t reserved_000; @@ -567,14 +572,7 @@ typedef struct { uint32_t reserved_060[30]; volatile gpio_ext_glitch_filter_chn_reg_t ext_glitch_filter_chn[8]; uint32_t reserved_0f8[8]; - volatile gpio_ext_etm_event_chn_cfg_reg_t ext_etm_event_chn_cfg[8]; - uint32_t reserved_138[8]; - volatile gpio_ext_etm_task_p0_cfg_reg_t ext_etm_task_p0_cfg; - volatile gpio_ext_etm_task_p1_cfg_reg_t ext_etm_task_p1_cfg; - volatile gpio_ext_etm_task_p2_cfg_reg_t ext_etm_task_p2_cfg; - volatile gpio_ext_etm_task_p3_cfg_reg_t ext_etm_task_p3_cfg; - volatile gpio_ext_etm_task_p4_cfg_reg_t ext_etm_task_p4_cfg; - volatile gpio_ext_etm_task_p5_cfg_reg_t ext_etm_task_p5_cfg; + volatile gpio_etm_dev_t etm; uint32_t reserved_170[24]; volatile gpio_ext_int_raw_reg_t ext_int_raw; volatile gpio_ext_int_st_reg_t ext_int_st; @@ -585,6 +583,7 @@ typedef struct { volatile gpio_ext_version_reg_t ext_version; } gpio_ext_dev_t; +extern gpio_etm_dev_t GPIO_ETM; extern gpio_ext_dev_t GPIO_EXT; #ifndef __cplusplus diff --git a/components/soc/esp32h21/register/soc/soc_etm_struct.h b/components/soc/esp32h21/register/soc/soc_etm_struct.h index dc1a8c3a48..3a2b8b7b56 100644 --- a/components/soc/esp32h21/register/soc/soc_etm_struct.h +++ b/components/soc/esp32h21/register/soc/soc_etm_struct.h @@ -1029,7 +1029,7 @@ typedef union { } soc_etm_date_reg_t; -typedef struct { +typedef struct soc_etm_dev_t { volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0; volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set; volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr; diff --git a/components/soc/esp32h4/include/soc/soc_caps_full.h b/components/soc/esp32h4/include/soc/soc_caps_full.h index 6712b6ea04..203676a6d3 100644 --- a/components/soc/esp32h4/include/soc/soc_caps_full.h +++ b/components/soc/esp32h4/include/soc/soc_caps_full.h @@ -13,10 +13,6 @@ #define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances #define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance -/*--------------------------- ETM (Event Task Matrix) ----------------------------*/ -#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances -#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance - /*------------------------------- I2S ---------------------------------------*/ // helper macros to access module attributes #define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances diff --git a/components/soc/esp32p4/include/soc/soc_caps_full.h b/components/soc/esp32p4/include/soc/soc_caps_full.h index 8adb004c2b..ce043a1623 100644 --- a/components/soc/esp32p4/include/soc/soc_caps_full.h +++ b/components/soc/esp32p4/include/soc/soc_caps_full.h @@ -17,10 +17,6 @@ #define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances #define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance -/*--------------------------- ETM (Event Task Matrix) ----------------------------*/ -#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances -#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance - /*------------------------------- I2S ---------------------------------------*/ // helper macros to access module attributes #define _SOC_CAPS_I2S_INST_NUM 3 // Number of I2S instances diff --git a/docs/docs_not_updated/esp32h21.txt b/docs/docs_not_updated/esp32h21.txt index 72c78debd6..1733b450bd 100644 --- a/docs/docs_not_updated/esp32h21.txt +++ b/docs/docs_not_updated/esp32h21.txt @@ -125,7 +125,6 @@ api-reference/peripherals/mcpwm.rst api-reference/peripherals/usb_host.rst api-reference/peripherals/camera_driver.rst api-reference/peripherals/adc_oneshot.rst -api-reference/peripherals/etm.rst api-reference/peripherals/sdspi_share.rst api-reference/peripherals/ana_cmpr.rst api-reference/peripherals/i2c_slave_v1.rst diff --git a/examples/peripherals/ledc/ledc_dimmer/README.md b/examples/peripherals/ledc/ledc_dimmer/README.md index 2d94421fc8..b3895cacce 100644 --- a/examples/peripherals/ledc/ledc_dimmer/README.md +++ b/examples/peripherals/ledc/ledc_dimmer/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | -| ----------------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | +| ----------------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | # LEDC Dimmer Example diff --git a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md index 4c19e7787c..50398ef216 100644 --- a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md +++ b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | -| ----------------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | +| ----------------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | # HC-SR04 Example based on GPTimer Capture and ETM