diff --git a/components/esp_hal_uart/esp32c2/include/hal/uart_ll.h b/components/esp_hal_uart/esp32c2/include/hal/uart_ll.h
index c79102d39a..aa32d30c8f 100644
--- a/components/esp_hal_uart/esp32c2/include/hal/uart_ll.h
+++ b/components/esp_hal_uart/esp32c2/include/hal/uart_ll.h
@@ -33,7 +33,7 @@
 #define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
 
 #define UART_LL_FSM_IDLE                       (0x0)
-#define UART_LL_FSM_TX_WAIT_SEND               (0xf)
+#define UART_LL_FSM_TX_WAIT_SEND               (0xf)    // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/esp_hal_uart/esp32c3/include/hal/uart_ll.h b/components/esp_hal_uart/esp32c3/include/hal/uart_ll.h
index bcce4a72a0..e5d5ae3eb2 100644
--- a/components/esp_hal_uart/esp32c3/include/hal/uart_ll.h
+++ b/components/esp_hal_uart/esp32c3/include/hal/uart_ll.h
@@ -32,7 +32,7 @@
 #define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
 
 #define UART_LL_FSM_IDLE                       (0x0)
-#define UART_LL_FSM_TX_WAIT_SEND               (0xf)
+#define UART_LL_FSM_TX_WAIT_SEND               (0xf)    // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/esp_hal_uart/esp32c5/include/hal/uart_ll.h b/components/esp_hal_uart/esp32c5/include/hal/uart_ll.h
index 6ce3fa981f..10c2fa04b4 100644
--- a/components/esp_hal_uart/esp32c5/include/hal/uart_ll.h
+++ b/components/esp_hal_uart/esp32c5/include/hal/uart_ll.h
@@ -40,7 +40,7 @@
 #define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
 
 #define UART_LL_FSM_IDLE                       (0x0)
-#define UART_LL_FSM_TX_WAIT_SEND               (0xf)
+#define UART_LL_FSM_TX_WAIT_SEND               (0xf)    // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
 
 #define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val)  \
     if ((hw) == &UART0) { \
diff --git a/components/esp_hal_uart/esp32c6/include/hal/uart_ll.h b/components/esp_hal_uart/esp32c6/include/hal/uart_ll.h
index 6c49f03c4d..e48f7cda4e 100644
--- a/components/esp_hal_uart/esp32c6/include/hal/uart_ll.h
+++ b/components/esp_hal_uart/esp32c6/include/hal/uart_ll.h
@@ -40,7 +40,7 @@
 #define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
 
 #define UART_LL_FSM_IDLE                       (0x0)
-#define UART_LL_FSM_TX_WAIT_SEND               (0xf)
+#define UART_LL_FSM_TX_WAIT_SEND               (0xf)    // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
 
 #define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val)  \
     if ((hw) == &UART0) { \
diff --git a/components/esp_hal_uart/esp32c61/include/hal/uart_ll.h b/components/esp_hal_uart/esp32c61/include/hal/uart_ll.h
index 0626a20f98..1fa6f31294 100644
--- a/components/esp_hal_uart/esp32c61/include/hal/uart_ll.h
+++ b/components/esp_hal_uart/esp32c61/include/hal/uart_ll.h
@@ -36,7 +36,7 @@
 #define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
 
 #define UART_LL_FSM_IDLE                       (0x0)
-#define UART_LL_FSM_TX_WAIT_SEND               (0xf)
+#define UART_LL_FSM_TX_WAIT_SEND               (0xf)    // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
 
 #define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val)  \
     if ((hw) == &UART0) { \
diff --git a/components/esp_hal_uart/esp32h2/include/hal/uart_ll.h b/components/esp_hal_uart/esp32h2/include/hal/uart_ll.h
index ef4fd2d31e..c823e94661 100644
--- a/components/esp_hal_uart/esp32h2/include/hal/uart_ll.h
+++ b/components/esp_hal_uart/esp32h2/include/hal/uart_ll.h
@@ -35,7 +35,7 @@
 #define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
 
 #define UART_LL_FSM_IDLE                       (0x0)
-#define UART_LL_FSM_TX_WAIT_SEND               (0xf)
+#define UART_LL_FSM_TX_WAIT_SEND               (0xf)    // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
 
 #define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val)  \
     if ((hw) == &UART0) { \
diff --git a/components/esp_hal_uart/esp32h21/include/hal/uart_ll.h b/components/esp_hal_uart/esp32h21/include/hal/uart_ll.h
index 51896d4d91..3e0264942a 100644
--- a/components/esp_hal_uart/esp32h21/include/hal/uart_ll.h
+++ b/components/esp_hal_uart/esp32h21/include/hal/uart_ll.h
@@ -35,7 +35,7 @@
 #define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
 
 #define UART_LL_FSM_IDLE                       (0x0)
-#define UART_LL_FSM_TX_WAIT_SEND               (0xf)
+#define UART_LL_FSM_TX_WAIT_SEND               (0xf)    // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
 
 #define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val)  \
     if ((hw) == &UART0) { \
diff --git a/components/esp_hal_uart/esp32h4/include/hal/uart_ll.h b/components/esp_hal_uart/esp32h4/include/hal/uart_ll.h
index 90550a13b1..6e0d05f677 100644
--- a/components/esp_hal_uart/esp32h4/include/hal/uart_ll.h
+++ b/components/esp_hal_uart/esp32h4/include/hal/uart_ll.h
@@ -32,7 +32,7 @@
 #define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
 
 #define UART_LL_FSM_IDLE                       (0x0)
-#define UART_LL_FSM_TX_WAIT_SEND               (0xf)
+#define UART_LL_FSM_TX_WAIT_SEND               (0xf)    // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
 
 #define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val)  \
     if ((hw) == &UART0) { \
diff --git a/components/esp_hal_uart/esp32p4/include/hal/uart_ll.h b/components/esp_hal_uart/esp32p4/include/hal/uart_ll.h
index ea23ec91e0..7c3d5600db 100644
--- a/components/esp_hal_uart/esp32p4/include/hal/uart_ll.h
+++ b/components/esp_hal_uart/esp32p4/include/hal/uart_ll.h
@@ -45,7 +45,7 @@
 #define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
 
 #define UART_LL_FSM_IDLE                       (0x0)
-#define UART_LL_FSM_TX_WAIT_SEND               (0xf)
+#define UART_LL_FSM_TX_WAIT_SEND               (0xf)    // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/esp_hal_uart/esp32s3/include/hal/uart_ll.h b/components/esp_hal_uart/esp32s3/include/hal/uart_ll.h
index 3ff206503e..0048d64b57 100644
--- a/components/esp_hal_uart/esp32s3/include/hal/uart_ll.h
+++ b/components/esp_hal_uart/esp32s3/include/hal/uart_ll.h
@@ -32,7 +32,7 @@
 #define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
 
 #define UART_LL_FSM_IDLE          (0x0)
-#define UART_LL_FSM_TX_WAIT_SEND  (0xf)
+#define UART_LL_FSM_TX_WAIT_SEND  (0xf)    // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index 7a8398d628..d06ca00a55 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -647,7 +647,7 @@ static SLEEP_FN_ATTR void suspend_uarts(void)
         }
         uart_ll_force_xoff(i);
         s_suspended_uarts_bmap |= BIT(i);
-#if SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
+#ifdef UART_LL_FSM_TX_WAIT_SEND
         uint32_t uart_fsm = 0;
         do {
             uart_fsm = uart_ll_get_tx_fsm_status(i);
diff --git a/components/soc/esp32/include/soc/uart_pins.h b/components/soc/esp32/include/soc/uart_pins.h
index 8556145394..68f35eac67 100644
--- a/components/soc/esp32/include/soc/uart_pins.h
+++ b/components/soc/esp32/include/soc/uart_pins.h
@@ -6,8 +6,6 @@
 
 #pragma once
 
-#include "soc/io_mux_reg.h"
-
 /* Specify the GPIO pin number for each UART signal in the IOMUX */
 #define U0TXD_GPIO_NUM  (1)
 #define U0RXD_GPIO_NUM  (3)
@@ -32,23 +30,23 @@
 
 /* The following defines are necessary for reconfiguring the UART
  * to use IOMUX, at runtime. */
-#define U0TXD_MUX_FUNC  (FUNC_U0TXD_U0TXD)
-#define U0RXD_MUX_FUNC  (FUNC_U0RXD_U0RXD)
-#define U0RTS_MUX_FUNC  (FUNC_GPIO22_U0RTS)
-#define U0CTS_MUX_FUNC  (FUNC_GPIO19_U0CTS)
+#define U0TXD_MUX_FUNC  (0)
+#define U0RXD_MUX_FUNC  (0)
+#define U0RTS_MUX_FUNC  (3)
+#define U0CTS_MUX_FUNC  (3)
 #define U0DTR_MUX_FUNC  (-1)
 #define U0DSR_MUX_FUNC  (-1)
 
-#define U1TXD_MUX_FUNC  (FUNC_SD_DATA3_U1TXD)
-#define U1RXD_MUX_FUNC  (FUNC_SD_DATA2_U1RXD)
-#define U1RTS_MUX_FUNC  (FUNC_SD_CMD_U1RTS)
-#define U1CTS_MUX_FUNC  (FUNC_SD_CLK_U1CTS)
+#define U1TXD_MUX_FUNC  (4)
+#define U1RXD_MUX_FUNC  (4)
+#define U1RTS_MUX_FUNC  (4)
+#define U1CTS_MUX_FUNC  (4)
 #define U1DTR_MUX_FUNC  (-1)
 #define U1DSR_MUX_FUNC  (-1)
 
-#define U2TXD_MUX_FUNC  (FUNC_GPIO17_U2TXD)
-#define U2RXD_MUX_FUNC  (FUNC_GPIO16_U2RXD)
-#define U2RTS_MUX_FUNC  (FUNC_SD_DATA0_U2RTS)
-#define U2CTS_MUX_FUNC  (FUNC_SD_DATA1_U2CTS)
+#define U2TXD_MUX_FUNC  (4)
+#define U2RXD_MUX_FUNC  (4)
+#define U2RTS_MUX_FUNC  (4)
+#define U2CTS_MUX_FUNC  (4)
 #define U2DTR_MUX_FUNC  (-1)
 #define U2DSR_MUX_FUNC  (-1)
diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
index bd0b505509..808c7c8bc4 100644
--- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
@@ -663,10 +663,6 @@ config SOC_UART_SUPPORT_XTAL_CLK
     bool
     default y
 
-config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
-    bool
-    default y
-
 config SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE
     bool
     default y
diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h
index 6a1e185aca..d63eccff86 100644
--- a/components/soc/esp32c2/include/soc/soc_caps.h
+++ b/components/soc/esp32c2/include/soc/soc_caps.h
@@ -298,9 +298,6 @@
 #define SOC_UART_SUPPORT_RTC_CLK    (1)     /*!< Support RTC clock as the clock source */
 #define SOC_UART_SUPPORT_XTAL_CLK   (1)     /*!< Support XTAL clock as the clock source */
 
-// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
-#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
-
 #define SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE (1)
 
 /*-------------------------- COEXISTENCE CAPS -------------------------------*/
diff --git a/components/soc/esp32c2/include/soc/uart_pins.h b/components/soc/esp32c2/include/soc/uart_pins.h
index be50d7555b..4a5c2b6f54 100644
--- a/components/soc/esp32c2/include/soc/uart_pins.h
+++ b/components/soc/esp32c2/include/soc/uart_pins.h
@@ -6,8 +6,6 @@
 
 #pragma once
 
-#include "soc/io_mux_reg.h"
-
 /* Specify the GPIO pin number for each UART signal in the IOMUX */
 #define U0RXD_GPIO_NUM 19
 #define U0TXD_GPIO_NUM 20
@@ -25,8 +23,8 @@
 
 /* The following defines are necessary for reconfiguring the UART
  * to use IOMUX, at runtime. */
-#define U0TXD_MUX_FUNC  (FUNC_U0TXD_U0TXD)
-#define U0RXD_MUX_FUNC  (FUNC_U0RXD_U0RXD)
+#define U0TXD_MUX_FUNC  (0)
+#define U0RXD_MUX_FUNC  (0)
 /* No func for the following pins, they shall not be used */
 #define U0RTS_MUX_FUNC  (-1)
 #define U0CTS_MUX_FUNC  (-1)
diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
index 64b3cceef0..39c2ed275c 100644
--- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
@@ -887,10 +887,6 @@ config SOC_UART_SUPPORT_WAKEUP_INT
     bool
     default y
 
-config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
-    bool
-    default y
-
 config SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE
     bool
     default y
diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h
index 5b778c4929..1534438d59 100644
--- a/components/soc/esp32c3/include/soc/soc_caps.h
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@@ -387,9 +387,6 @@
 #define SOC_UART_SUPPORT_XTAL_CLK   (1)     /*!< Support XTAL clock as the clock source */
 #define SOC_UART_SUPPORT_WAKEUP_INT (1)         /*!< Support UART wakeup interrupt */
 
-// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
-#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
-
 #define SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE (1)
 
 /*--------------------------- UHCI CAPS -------------------------------------*/
diff --git a/components/soc/esp32c3/include/soc/uart_pins.h b/components/soc/esp32c3/include/soc/uart_pins.h
index ac57ebabdf..22d83e8e78 100644
--- a/components/soc/esp32c3/include/soc/uart_pins.h
+++ b/components/soc/esp32c3/include/soc/uart_pins.h
@@ -6,8 +6,6 @@
 
 #pragma once
 
-#include "soc/io_mux_reg.h"
-
 /* Specify the GPIO pin number for each UART signal in the IOMUX */
 #define U0RXD_GPIO_NUM 20
 #define U0TXD_GPIO_NUM 21
@@ -25,8 +23,8 @@
 
 /* The following defines are necessary for reconfiguring the UART
  * to use IOMUX, at runtime. */
-#define U0TXD_MUX_FUNC  (FUNC_U0TXD_U0TXD)
-#define U0RXD_MUX_FUNC  (FUNC_U0RXD_U0RXD)
+#define U0TXD_MUX_FUNC  (0)
+#define U0RXD_MUX_FUNC  (0)
 /* No func for the following pins, they shall not be used */
 #define U0RTS_MUX_FUNC  (-1)
 #define U0CTS_MUX_FUNC  (-1)
diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
index 3bc4775de9..e3fda631de 100644
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@@ -1379,10 +1379,6 @@ config SOC_UART_SUPPORT_SLEEP_RETENTION
     bool
     default y
 
-config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
-    bool
-    default y
-
 config SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN
     int
     default 5
diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h
index f6bfd64863..6da0a14551 100644
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@@ -557,9 +557,6 @@
 #define SOC_UART_HAS_LP_UART               (1)         /*!< Support LP UART */
 #define SOC_UART_SUPPORT_SLEEP_RETENTION   (1)         /*!< Support back up registers before sleep */
 
-// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
-#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
-
 #define SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN 5
 #define SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE (1)
 #define SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE   (1)
diff --git a/components/soc/esp32c5/include/soc/uart_pins.h b/components/soc/esp32c5/include/soc/uart_pins.h
index bce131e82f..d4f4e0f3fd 100644
--- a/components/soc/esp32c5/include/soc/uart_pins.h
+++ b/components/soc/esp32c5/include/soc/uart_pins.h
@@ -6,8 +6,6 @@
 
 #pragma once
 
-#include "soc/io_mux_reg.h"
-
 /* Specify the GPIO pin number for each UART signal in the IOMUX */
 #define U0RXD_GPIO_NUM 12
 #define U0TXD_GPIO_NUM 11
@@ -32,8 +30,8 @@
 
 /* The following defines are necessary for reconfiguring the UART
  * to use IOMUX, at runtime. */
-#define U0TXD_MUX_FUNC  (FUNC_U0TXD_U0TXD)
-#define U0RXD_MUX_FUNC  (FUNC_U0RXD_U0RXD)
+#define U0TXD_MUX_FUNC  (0)
+#define U0RXD_MUX_FUNC  (0)
 /* No func for the following pins, they shall not be used */
 #define U0RTS_MUX_FUNC  (-1)
 #define U0CTS_MUX_FUNC  (-1)
diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
index 2a4717712f..e601a03e95 100644
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@@ -1147,10 +1147,6 @@ config SOC_UART_SUPPORT_SLEEP_RETENTION
     bool
     default y
 
-config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
-    bool
-    default y
-
 config SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN
     int
     default 5
diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
index 694c51a515..39d5cd917c 100644
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -472,9 +472,6 @@
 #define SOC_UART_HAS_LP_UART            (1)         /*!< Support LP UART */
 #define SOC_UART_SUPPORT_SLEEP_RETENTION   (1)         /*!< Support back up registers before sleep */
 
-// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
-#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
-
 #define SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN 5
 #define SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE (1)
 #define SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE   (1)
diff --git a/components/soc/esp32c6/include/soc/uart_pins.h b/components/soc/esp32c6/include/soc/uart_pins.h
index 31c9229900..110cabbbe9 100644
--- a/components/soc/esp32c6/include/soc/uart_pins.h
+++ b/components/soc/esp32c6/include/soc/uart_pins.h
@@ -6,8 +6,6 @@
 
 #pragma once
 
-#include "soc/io_mux_reg.h"
-
 /* Specify the GPIO pin number for each UART signal in the IOMUX */
 #define U0RXD_GPIO_NUM 17
 #define U0TXD_GPIO_NUM 16
@@ -32,8 +30,8 @@
 
 /* The following defines are necessary for reconfiguring the UART
  * to use IOMUX, at runtime. */
-#define U0TXD_MUX_FUNC  (FUNC_U0TXD_U0TXD)
-#define U0RXD_MUX_FUNC  (FUNC_U0RXD_U0RXD)
+#define U0TXD_MUX_FUNC  (0)
+#define U0RXD_MUX_FUNC  (0)
 /* No func for the following pins, they shall not be used */
 #define U0RTS_MUX_FUNC  (-1)
 #define U0CTS_MUX_FUNC  (-1)
diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
index d3d25d0336..d73d6a60f4 100644
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@@ -1015,10 +1015,6 @@ config SOC_UART_SUPPORT_SLEEP_RETENTION
     bool
     default y
 
-config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
-    bool
-    default y
-
 config SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN
     int
     default 5
diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h
index 67e2df0c68..6599966a5d 100644
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -419,9 +419,6 @@
 #define SOC_UART_SUPPORT_WAKEUP_INT     (1)         /*!< Support UART wakeup interrupt */
 #define SOC_UART_SUPPORT_SLEEP_RETENTION   (1)      /*!< Support back up registers before sleep */
 
-// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
-#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
-
 #define SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN 5
 #define SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE (1)
 #define SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE   (1)
diff --git a/components/soc/esp32c61/include/soc/uart_pins.h b/components/soc/esp32c61/include/soc/uart_pins.h
index d261acca55..fa0d17cd26 100644
--- a/components/soc/esp32c61/include/soc/uart_pins.h
+++ b/components/soc/esp32c61/include/soc/uart_pins.h
@@ -6,8 +6,6 @@
 
 #pragma once
 
-#include "soc/io_mux_reg.h"
-
 /* Specify the GPIO pin number for each UART signal in the IOMUX */
 #define U0RXD_GPIO_NUM 10
 #define U0TXD_GPIO_NUM 11
@@ -32,8 +30,8 @@
 
 /* The following defines are necessary for reconfiguring the UART
  * to use IOMUX, at runtime. */
-#define U0TXD_MUX_FUNC  (FUNC_U0TXD_U0TXD)
-#define U0RXD_MUX_FUNC  (FUNC_U0RXD_U0RXD)
+#define U0TXD_MUX_FUNC  (0)
+#define U0RXD_MUX_FUNC  (0)
 /* No func for the following pins, they shall not be used */
 #define U0RTS_MUX_FUNC  (-1)
 #define U0CTS_MUX_FUNC  (-1)
diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
index 21648cfe1a..41d96b8b4d 100644
--- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@@ -1151,10 +1151,6 @@ config SOC_UART_SUPPORT_WAKEUP_INT
     bool
     default y
 
-config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
-    bool
-    default y
-
 config SOC_UART_SUPPORT_SLEEP_RETENTION
     bool
     default y
diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h
index 363f90be92..3efb3865d5 100644
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -492,9 +492,6 @@
 #define SOC_UART_SUPPORT_XTAL_CLK           (1)     /*!< Support XTAL clock as the clock source */
 #define SOC_UART_SUPPORT_WAKEUP_INT         (1)     /*!< Support UART wakeup interrupt */
 
-// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
-#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
-
 #define SOC_UART_SUPPORT_SLEEP_RETENTION   (1)         /*!< Support back up registers before sleep */
 
 #define SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN 5
diff --git a/components/soc/esp32h2/include/soc/uart_pins.h b/components/soc/esp32h2/include/soc/uart_pins.h
index eb29ce3abb..40d97cd65e 100644
--- a/components/soc/esp32h2/include/soc/uart_pins.h
+++ b/components/soc/esp32h2/include/soc/uart_pins.h
@@ -6,8 +6,6 @@
 
 #pragma once
 
-#include "soc/io_mux_reg.h"
-
 /* Specify the GPIO pin number for each UART signal in the IOMUX */
 #define U0RXD_GPIO_NUM 23
 #define U0TXD_GPIO_NUM 24
@@ -25,8 +23,8 @@
 
 /* The following defines are necessary for reconfiguring the UART
  * to use IOMUX, at runtime. */
-#define U0TXD_MUX_FUNC  (FUNC_U0TXD_U0TXD)
-#define U0RXD_MUX_FUNC  (FUNC_U0RXD_U0RXD)
+#define U0TXD_MUX_FUNC  (0)
+#define U0RXD_MUX_FUNC  (0)
 /* No func for the following pins, they shall not be used */
 #define U0RTS_MUX_FUNC  (-1)
 #define U0CTS_MUX_FUNC  (-1)
diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
index 76d66284a4..fbd504f680 100644
--- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
@@ -855,10 +855,6 @@ config SOC_UART_SUPPORT_WAKEUP_INT
     bool
     default y
 
-config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
-    bool
-    default y
-
 config SOC_UART_SUPPORT_SLEEP_RETENTION
     bool
     default y
diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h
index 3ac0807d88..e4a8446589 100644
--- a/components/soc/esp32h21/include/soc/soc_caps.h
+++ b/components/soc/esp32h21/include/soc/soc_caps.h
@@ -468,9 +468,6 @@
 #define SOC_UART_SUPPORT_XTAL_CLK           (1)     /*!< Support XTAL clock as the clock source */
 #define SOC_UART_SUPPORT_WAKEUP_INT         (1)     /*!< Support UART wakeup interrupt */
 
-// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
-#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
-
 #define SOC_UART_SUPPORT_SLEEP_RETENTION   (1)         /*!< Support back up registers before sleep */
 
 #define SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN 5
diff --git a/components/soc/esp32h21/include/soc/uart_pins.h b/components/soc/esp32h21/include/soc/uart_pins.h
index de6c3d269b..f473cd4ef7 100644
--- a/components/soc/esp32h21/include/soc/uart_pins.h
+++ b/components/soc/esp32h21/include/soc/uart_pins.h
@@ -6,8 +6,6 @@
 
 #pragma once
 
-#include "soc/io_mux_reg.h"
-
 /* Specify the GPIO pin number for each UART signal in the IOMUX */
 #define U0RXD_GPIO_NUM 15
 #define U0TXD_GPIO_NUM 16
@@ -25,8 +23,8 @@
 
 /* The following defines are necessary for reconfiguring the UART
  * to use IOMUX, at runtime. */
-#define U0TXD_MUX_FUNC  (FUNC_U0TXD_U0TXD)
-#define U0RXD_MUX_FUNC  (FUNC_U0RXD_U0RXD)
+#define U0TXD_MUX_FUNC  (0)
+#define U0RXD_MUX_FUNC  (0)
 /* No func for the following pins, they shall not be used */
 #define U0RTS_MUX_FUNC  (-1)
 #define U0CTS_MUX_FUNC  (-1)
diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
index 422b254cc8..ec830d1de9 100644
--- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
@@ -847,10 +847,6 @@ config SOC_UART_SUPPORT_WAKEUP_INT
     bool
     default y
 
-config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
-    bool
-    default y
-
 config SOC_UART_SUPPORT_SLEEP_RETENTION
     bool
     default y
diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h
index c047e3e1c5..11048016da 100644
--- a/components/soc/esp32h4/include/soc/soc_caps.h
+++ b/components/soc/esp32h4/include/soc/soc_caps.h
@@ -453,9 +453,6 @@
 #define SOC_UART_SUPPORT_XTAL_CLK       (1)         /*!< Support XTAL clock as the clock source */
 #define SOC_UART_SUPPORT_WAKEUP_INT     (1)         /*!< Support UART wakeup interrupt */
 
-// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
-#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
-
 #define SOC_UART_SUPPORT_SLEEP_RETENTION   (1)         /*!< Support back up registers before sleep */
 
 // #define SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN 5
diff --git a/components/soc/esp32h4/include/soc/uart_pins.h b/components/soc/esp32h4/include/soc/uart_pins.h
index 83ecbe9278..3ff90b59ad 100644
--- a/components/soc/esp32h4/include/soc/uart_pins.h
+++ b/components/soc/esp32h4/include/soc/uart_pins.h
@@ -6,8 +6,6 @@
 
 #pragma once
 
-#include "soc/io_mux_reg.h"
-
 /* Specify the GPIO pin number for each UART signal in the IOMUX */
 #define U0RXD_GPIO_NUM  23
 #define U0TXD_GPIO_NUM  24
@@ -25,8 +23,8 @@
 
 /* The following defines are necessary for reconfiguring the UART
  * to use IOMUX, at runtime. */
-#define U0TXD_MUX_FUNC  (FUNC_U0TXD_U0TXD)
-#define U0RXD_MUX_FUNC  (FUNC_U0RXD_U0RXD)
+#define U0TXD_MUX_FUNC  (0)
+#define U0RXD_MUX_FUNC  (0)
 /* No func for the following pins, they shall not be used */
 #define U0RTS_MUX_FUNC  (-1)
 #define U0CTS_MUX_FUNC  (-1)
diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
index 6a9ed4f129..556f6869a4 100644
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -1715,10 +1715,6 @@ config SOC_UART_SUPPORT_SLEEP_RETENTION
     bool
     default y
 
-config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
-    bool
-    default y
-
 config SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN
     int
     default 5
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
index eb3ae6c828..3f3836b667 100644
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -655,9 +655,6 @@
 #define SOC_UART_HAS_LP_UART            (1)         /*!< Support LP UART */
 #define SOC_UART_SUPPORT_SLEEP_RETENTION   (1)      /*!< Support back up registers before sleep */
 
-// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
-#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
-
 #define SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN 5
 #define SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE (1)
 #define SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE   (1)
diff --git a/components/soc/esp32p4/include/soc/uart_pins.h b/components/soc/esp32p4/include/soc/uart_pins.h
index 942e2a1115..d3d4ba3e72 100644
--- a/components/soc/esp32p4/include/soc/uart_pins.h
+++ b/components/soc/esp32p4/include/soc/uart_pins.h
@@ -6,8 +6,6 @@
 
 #pragma once
 
-#include "soc/io_mux_reg.h"
-
 /* Specify the GPIO pin number for each UART signal in the IOMUX */
 #define U0RXD_GPIO_NUM 38
 #define U0TXD_GPIO_NUM 37
@@ -53,18 +51,18 @@
 
 /* The following defines are necessary for reconfiguring the UART
  * to use IOMUX, at runtime. */
-#define U0TXD_MUX_FUNC  (FUNC_GPIO37_UART0_TXD_PAD)
-#define U0RXD_MUX_FUNC  (FUNC_GPIO38_UART0_RXD_PAD)
-#define U0RTS_MUX_FUNC  (FUNC_GPIO8_UART0_RTS_PAD)
-#define U0CTS_MUX_FUNC  (FUNC_GPIO9_UART0_CTS_PAD)
+#define U0TXD_MUX_FUNC  (0)
+#define U0RXD_MUX_FUNC  (0)
+#define U0RTS_MUX_FUNC  (2)
+#define U0CTS_MUX_FUNC  (2)
 #define U0DTR_MUX_FUNC  (-1)
 #define U0DSR_MUX_FUNC  (-1)
 
 /* Same goes for UART1 */
-#define U1TXD_MUX_FUNC  (FUNC_GPIO10_UART1_TXD_PAD)
-#define U1RXD_MUX_FUNC  (FUNC_GPIO11_UART1_RXD_PAD)
-#define U1RTS_MUX_FUNC  (FUNC_GPIO12_UART1_RTS_PAD)
-#define U1CTS_MUX_FUNC  (FUNC_GPIO13_UART1_CTS_PAD)
+#define U1TXD_MUX_FUNC  (2)
+#define U1RXD_MUX_FUNC  (2)
+#define U1RTS_MUX_FUNC  (2)
+#define U1CTS_MUX_FUNC  (2)
 #define U1DTR_MUX_FUNC  (-1)
 #define U1DSR_MUX_FUNC  (-1)
 
diff --git a/components/soc/esp32s2/include/soc/uart_pins.h b/components/soc/esp32s2/include/soc/uart_pins.h
index 02c79e02df..c6b8299de5 100644
--- a/components/soc/esp32s2/include/soc/uart_pins.h
+++ b/components/soc/esp32s2/include/soc/uart_pins.h
@@ -6,8 +6,6 @@
 
 #pragma once
 
-#include "soc/io_mux_reg.h"
-
 /* Specify the GPIO pin number for each UART signal in the IOMUX */
 #define U0RXD_GPIO_NUM  (44)
 #define U0TXD_GPIO_NUM  (43)
@@ -25,16 +23,16 @@
 
 /* The following defines are necessary for reconfiguring the UART
  * to use IOMUX, at runtime. */
-#define U0TXD_MUX_FUNC  (FUNC_U0TXD_U0TXD)
-#define U0RXD_MUX_FUNC  (FUNC_U0RXD_U0RXD)
-#define U0RTS_MUX_FUNC  (FUNC_XTAL_32K_P_U0RTS)
-#define U0CTS_MUX_FUNC  (FUNC_XTAL_32K_N_U0CTS)
+#define U0TXD_MUX_FUNC  (0)
+#define U0RXD_MUX_FUNC  (0)
+#define U0RTS_MUX_FUNC  (2)
+#define U0CTS_MUX_FUNC  (2)
 #define U0DTR_MUX_FUNC  (-1)
 #define U0DSR_MUX_FUNC  (-1)
 
-#define U1TXD_MUX_FUNC  (FUNC_DAC_1_U1TXD)
-#define U1RXD_MUX_FUNC  (FUNC_DAC_2_U1RXD)
-#define U1RTS_MUX_FUNC  (FUNC_GPIO19_U1RTS)
-#define U1CTS_MUX_FUNC  (FUNC_GPIO20_U1CTS)
+#define U1TXD_MUX_FUNC  (2)
+#define U1RXD_MUX_FUNC  (2)
+#define U1RTS_MUX_FUNC  (2)
+#define U1CTS_MUX_FUNC  (2)
 #define U1DTR_MUX_FUNC  (-1)
 #define U1DSR_MUX_FUNC  (-1)
diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
index f36b2a4208..b61c03d094 100644
--- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
@@ -863,10 +863,6 @@ config SOC_UART_BITRATE_MAX
     int
     default 5000000
 
-config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
-    bool
-    default y
-
 config SOC_UART_SUPPORT_WAKEUP_INT
     bool
     default y
diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h
index 59fd1dadd7..6c5d0d8068 100644
--- a/components/soc/esp32s3/include/soc/soc_caps.h
+++ b/components/soc/esp32s3/include/soc/soc_caps.h
@@ -356,8 +356,6 @@
 #define SOC_UART_HP_NUM             (3)
 #define SOC_UART_FIFO_LEN           (128)      /*!< The UART hardware FIFO length */
 #define SOC_UART_BITRATE_MAX        (5000000)  /*!< Max bit rate supported by UART */
-// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
-#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
 #define SOC_UART_SUPPORT_WAKEUP_INT (1)        /*!< Support UART wakeup interrupt */
 #define SOC_UART_SUPPORT_APB_CLK    (1)     /*!< Support APB as the clock source */
 #define SOC_UART_SUPPORT_RTC_CLK    (1)     /*!< Support RTC clock as the clock source */
diff --git a/components/soc/esp32s3/include/soc/uart_pins.h b/components/soc/esp32s3/include/soc/uart_pins.h
index f36741ea88..9989176418 100644
--- a/components/soc/esp32s3/include/soc/uart_pins.h
+++ b/components/soc/esp32s3/include/soc/uart_pins.h
@@ -6,8 +6,6 @@
 
 #pragma once
 
-#include "soc/io_mux_reg.h"
-
 /* Specify the GPIO pin number for each UART signal in the IOMUX */
 #define U0RXD_GPIO_NUM 44
 #define U0TXD_GPIO_NUM 43
@@ -32,17 +30,17 @@
 
 /* The following defines are necessary for reconfiguring the UART
  * to use IOMUX, at runtime. */
-#define U0TXD_MUX_FUNC  (FUNC_U0TXD_U0TXD)
-#define U0RXD_MUX_FUNC  (FUNC_U0RXD_U0RXD)
-#define U0RTS_MUX_FUNC  (FUNC_XTAL_32K_P_U0RTS)
-#define U0CTS_MUX_FUNC  (FUNC_XTAL_32K_N_U0CTS)
+#define U0TXD_MUX_FUNC  (0)
+#define U0RXD_MUX_FUNC  (0)
+#define U0RTS_MUX_FUNC  (2)
+#define U0CTS_MUX_FUNC  (2)
 #define U0DTR_MUX_FUNC  (-1)
 #define U0DSR_MUX_FUNC  (-1)
 
-#define U1TXD_MUX_FUNC  (FUNC_DAC_1_U1TXD)
-#define U1RXD_MUX_FUNC  (FUNC_DAC_2_U1RXD)
-#define U1RTS_MUX_FUNC  (FUNC_GPIO19_U1RTS)
-#define U1CTS_MUX_FUNC  (FUNC_GPIO20_U1CTS)
+#define U1TXD_MUX_FUNC  (2)
+#define U1RXD_MUX_FUNC  (2)
+#define U1RTS_MUX_FUNC  (2)
+#define U1CTS_MUX_FUNC  (2)
 #define U1DTR_MUX_FUNC  (-1)
 #define U1DSR_MUX_FUNC  (-1)
 
diff --git a/components/soc/linux/include/soc/uart_channel.h b/components/soc/linux/include/soc/uart_pins.h
similarity index 100%
rename from components/soc/linux/include/soc/uart_channel.h
rename to components/soc/linux/include/soc/uart_pins.h
diff --git a/docs/en/api-reference/peripherals/uart.rst b/docs/en/api-reference/peripherals/uart.rst
index 22316ff24a..6f684a34de 100644
--- a/docs/en/api-reference/peripherals/uart.rst
+++ b/docs/en/api-reference/peripherals/uart.rst
@@ -445,6 +445,6 @@ API Reference
 GPIO Lookup Macros
 ^^^^^^^^^^^^^^^^^^
 
-Some UART ports have dedicated IO_MUX pins to which they are connected directly. These can be useful if you need very high UART baud rates, which means you will have to use IO_MUX pins only. In other cases, any GPIO pin can be used for UART communication by routing the signals through the GPIO matrix. If the UART port has dedicated IO_MUX pins, :c:macro:`UART_NUM_x_TXD_DIRECT_GPIO_NUM` and :c:macro:`UART_NUM_x_RXD_DIRECT_GPIO_NUM` can be used to find the corresponding IO_MUX pin numbers.
+Some UART ports have dedicated IO_MUX pins to which they are connected directly. These can be useful if you need very high UART baud rates, which means you will have to use IO_MUX pins only. In other cases, any GPIO pin can be used for UART communication by routing the signals through the GPIO matrix. If the UART port has dedicated IO_MUX pins, :c:macro:`UxTXD_GPIO_NUM` and :c:macro:`UxRXD_GPIO_NUM` can be used to find the corresponding IO_MUX pin numbers.
 
-.. include-build-file:: inc/uart_channel.inc
+.. include-build-file:: inc/uart_pins.inc
diff --git a/docs/zh_CN/api-reference/peripherals/uart.rst b/docs/zh_CN/api-reference/peripherals/uart.rst
index e351eeb184..aaa3f45496 100644
--- a/docs/zh_CN/api-reference/peripherals/uart.rst
+++ b/docs/zh_CN/api-reference/peripherals/uart.rst
@@ -445,6 +445,6 @@ API 参考
 GPIO 查找宏指令
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-一些 UART 外设有供直接连接的专用 IO_MUX 管脚。这些管脚可用于需要极高 UART 波特率的场景，即仅可使用 IO_MUX 管脚。在其他情况下，任一 GPIO 管脚都可用于 UART 通信，只需将信号通过 GPIO 矩阵路由即可。当特定的 UART 外设有专用 IO_MUX 管脚时，:c:macro:`UART_NUM_x_TXD_DIRECT_GPIO_NUM` 和 :c:macro:`UART_NUM_x_RXD_DIRECT_GPIO_NUM` 可用于查找对应的 IO_MUX 管脚编号。
+一些 UART 外设有供直接连接的专用 IO_MUX 管脚。这些管脚可用于需要极高 UART 波特率的场景，即仅可使用 IO_MUX 管脚。在其他情况下，任一 GPIO 管脚都可用于 UART 通信，只需将信号通过 GPIO 矩阵路由即可。当特定的 UART 外设有专用 IO_MUX 管脚时，:c:macro:`UxTXD_GPIO_NUM` 和 :c:macro:`UxRXD_GPIO_NUM` 可用于查找对应的 IO_MUX 管脚编号。
 
-.. include-build-file:: inc/uart_channel.inc
+.. include-build-file:: inc/uart_pins.inc