diff --git a/components/esp_driver_gptimer/CMakeLists.txt b/components/esp_driver_gptimer/CMakeLists.txt index 55b8a07851..e86c7432b8 100644 --- a/components/esp_driver_gptimer/CMakeLists.txt +++ b/components/esp_driver_gptimer/CMakeLists.txt @@ -8,6 +8,10 @@ set(public_include "include") if(CONFIG_SOC_GPTIMER_SUPPORTED) list(APPEND srcs "src/gptimer.c" "src/gptimer_common.c") + + if(CONFIG_SOC_PAU_SUPPORTED AND CONFIG_SOC_TIMER_SUPPORT_SLEEP_RETENTION) + list(APPEND srcs "${target}/timer_retention.c") + endif() endif() if(CONFIG_SOC_TIMER_SUPPORT_ETM) @@ -18,6 +22,7 @@ set(requires esp_pm esp_hal_timg) idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${public_include} + PRIV_INCLUDE_DIRS "src" REQUIRES ${requires} LDFRAGMENTS "linker.lf" - ) + ) diff --git a/components/esp_driver_gptimer/esp32c5/timer_retention.c b/components/esp_driver_gptimer/esp32c5/timer_retention.c new file mode 100644 index 0000000000..5695c9b20f --- /dev/null +++ b/components/esp_driver_gptimer/esp32c5/timer_retention.c @@ -0,0 +1,114 @@ +/* + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "soc/timer_group_reg.h" +#include "gptimer_priv.h" + +/* Registers in retention context: + * TIMG_T0CONFIG_REG + * TIMG_T0ALARMLO_REG + * TIMG_T0ALARMHI_REG + * TIMG_T0LOADLO_REG + * TIMG_T0LOADHI_REG + * TIMG_INT_ENA_TIMERS_REG + * TIMG_REGCLK_REG + */ +#define TG_TIMER_RETENTION_REGS_CNT 7 +static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; + +const regdma_entries_config_t tg0_timer_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), + TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), + TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const regdma_entries_config_t tg1_timer_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), + TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), + TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const gptimer_retention_desc_t gptimer_retention_infos[2][1] = { + [0] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, + .regdma_entry_array = tg0_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg0_timer_regdma_entries) + } + }, + [1] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, + .regdma_entry_array = tg1_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg1_timer_regdma_entries) + } + }, +}; diff --git a/components/esp_driver_gptimer/esp32c6/timer_retention.c b/components/esp_driver_gptimer/esp32c6/timer_retention.c new file mode 100644 index 0000000000..5695c9b20f --- /dev/null +++ b/components/esp_driver_gptimer/esp32c6/timer_retention.c @@ -0,0 +1,114 @@ +/* + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "soc/timer_group_reg.h" +#include "gptimer_priv.h" + +/* Registers in retention context: + * TIMG_T0CONFIG_REG + * TIMG_T0ALARMLO_REG + * TIMG_T0ALARMHI_REG + * TIMG_T0LOADLO_REG + * TIMG_T0LOADHI_REG + * TIMG_INT_ENA_TIMERS_REG + * TIMG_REGCLK_REG + */ +#define TG_TIMER_RETENTION_REGS_CNT 7 +static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; + +const regdma_entries_config_t tg0_timer_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), + TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), + TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const regdma_entries_config_t tg1_timer_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), + TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), + TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const gptimer_retention_desc_t gptimer_retention_infos[2][1] = { + [0] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, + .regdma_entry_array = tg0_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg0_timer_regdma_entries) + } + }, + [1] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, + .regdma_entry_array = tg1_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg1_timer_regdma_entries) + } + }, +}; diff --git a/components/esp_driver_gptimer/esp32c61/timer_retention.c b/components/esp_driver_gptimer/esp32c61/timer_retention.c new file mode 100644 index 0000000000..5695c9b20f --- /dev/null +++ b/components/esp_driver_gptimer/esp32c61/timer_retention.c @@ -0,0 +1,114 @@ +/* + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "soc/timer_group_reg.h" +#include "gptimer_priv.h" + +/* Registers in retention context: + * TIMG_T0CONFIG_REG + * TIMG_T0ALARMLO_REG + * TIMG_T0ALARMHI_REG + * TIMG_T0LOADLO_REG + * TIMG_T0LOADHI_REG + * TIMG_INT_ENA_TIMERS_REG + * TIMG_REGCLK_REG + */ +#define TG_TIMER_RETENTION_REGS_CNT 7 +static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; + +const regdma_entries_config_t tg0_timer_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), + TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), + TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const regdma_entries_config_t tg1_timer_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), + TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), + TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const gptimer_retention_desc_t gptimer_retention_infos[2][1] = { + [0] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, + .regdma_entry_array = tg0_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg0_timer_regdma_entries) + } + }, + [1] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, + .regdma_entry_array = tg1_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg1_timer_regdma_entries) + } + }, +}; diff --git a/components/esp_driver_gptimer/esp32h2/timer_retention.c b/components/esp_driver_gptimer/esp32h2/timer_retention.c new file mode 100644 index 0000000000..5695c9b20f --- /dev/null +++ b/components/esp_driver_gptimer/esp32h2/timer_retention.c @@ -0,0 +1,114 @@ +/* + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "soc/timer_group_reg.h" +#include "gptimer_priv.h" + +/* Registers in retention context: + * TIMG_T0CONFIG_REG + * TIMG_T0ALARMLO_REG + * TIMG_T0ALARMHI_REG + * TIMG_T0LOADLO_REG + * TIMG_T0LOADHI_REG + * TIMG_INT_ENA_TIMERS_REG + * TIMG_REGCLK_REG + */ +#define TG_TIMER_RETENTION_REGS_CNT 7 +static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; + +const regdma_entries_config_t tg0_timer_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), + TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), + TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const regdma_entries_config_t tg1_timer_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), + TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), + TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const gptimer_retention_desc_t gptimer_retention_infos[2][1] = { + [0] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, + .regdma_entry_array = tg0_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg0_timer_regdma_entries) + } + }, + [1] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, + .regdma_entry_array = tg1_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg1_timer_regdma_entries) + } + }, +}; diff --git a/components/esp_driver_gptimer/esp32h21/timer_retention.c b/components/esp_driver_gptimer/esp32h21/timer_retention.c new file mode 100644 index 0000000000..ad7a617f33 --- /dev/null +++ b/components/esp_driver_gptimer/esp32h21/timer_retention.c @@ -0,0 +1,114 @@ +/* + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "soc/timer_group_reg.h" +#include "gptimer_priv.h" + +/* Registers in retention context: + * TIMG_T0CONFIG_REG + * TIMG_T0ALARMLO_REG + * TIMG_T0ALARMHI_REG + * TIMG_T0LOADLO_REG + * TIMG_T0LOADHI_REG + * TIMG_INT_ENA_TIMERS_REG + * TIMG_REGCLK_REG + */ +#define TG_TIMER_RETENTION_REGS_CNT 7 +static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; + +const regdma_entries_config_t tg0_timer_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), + TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), + TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const regdma_entries_config_t tg1_timer_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), + TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), + TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const gptimer_retention_desc_t gptimer_retention_infos[2][1] = { + [0] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, + .regdma_entry_array = tg0_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg0_timer_regdma_entries) + } + }, + [1] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, + .regdma_entry_array = tg1_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg1_timer_regdma_entries) + } + }, +}; diff --git a/components/esp_driver_gptimer/esp32h4/timer_retention.c b/components/esp_driver_gptimer/esp32h4/timer_retention.c new file mode 100644 index 0000000000..ad7a617f33 --- /dev/null +++ b/components/esp_driver_gptimer/esp32h4/timer_retention.c @@ -0,0 +1,114 @@ +/* + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "soc/timer_group_reg.h" +#include "gptimer_priv.h" + +/* Registers in retention context: + * TIMG_T0CONFIG_REG + * TIMG_T0ALARMLO_REG + * TIMG_T0ALARMHI_REG + * TIMG_T0LOADLO_REG + * TIMG_T0LOADHI_REG + * TIMG_INT_ENA_TIMERS_REG + * TIMG_REGCLK_REG + */ +#define TG_TIMER_RETENTION_REGS_CNT 7 +static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; + +const regdma_entries_config_t tg0_timer_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), + TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), + TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const regdma_entries_config_t tg1_timer_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), + TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), + TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const gptimer_retention_desc_t gptimer_retention_infos[2][1] = { + [0] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, + .regdma_entry_array = tg0_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg0_timer_regdma_entries) + } + }, + [1] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, + .regdma_entry_array = tg1_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg1_timer_regdma_entries) + } + }, +}; diff --git a/components/esp_driver_gptimer/esp32p4/timer_retention.c b/components/esp_driver_gptimer/esp32p4/timer_retention.c new file mode 100644 index 0000000000..c9b873f49f --- /dev/null +++ b/components/esp_driver_gptimer/esp32p4/timer_retention.c @@ -0,0 +1,216 @@ +/* + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "soc/timer_group_reg.h" +#include "gptimer_priv.h" + +/* Registers in retention context: + * TIMG_T0CONFIG_REG + * TIMG_T0ALARMLO_REG + * TIMG_T0ALARMHI_REG + * TIMG_T0LOADLO_REG + * TIMG_T0LOADHI_REG + * TIMG_INT_ENA_TIMERS_REG + * TIMG_REGCLK_REG + */ +#define TG0_TIMER0_RETENTION_REGS_BASE (REG_TIMG_BASE(0)) +#define TG1_TIMER0_RETENTION_REGS_BASE (REG_TIMG_BASE(1)) +#define TG_TIMER0_RETENTION_REGS_CNT 7 +static const uint32_t tg_timer0_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; + +/* Registers in retention context: + * TIMG_T1CONFIG_REG + * TIMG_T1ALARMLO_REG + * TIMG_T1ALARMHI_REG + * TIMG_T1LOADLO_REG + * TIMG_T1LOADHI_REG + * TIMG_INT_ENA_TIMERS_REG + * TIMG_REGCLK_REG + */ +#define TG0_TIMER1_RETENTION_REGS_BASE (REG_TIMG_BASE(0) + 0x24) +#define TG1_TIMER1_RETENTION_REGS_BASE (REG_TIMG_BASE(1) + 0x24) +#define TG_TIMER1_RETENTION_REGS_CNT 7 +static const uint32_t tg_timer1_regs_map[4] = {0x800f1, 0x400000, 0x0, 0x0}; + +const regdma_entries_config_t tg0_timer0_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), + TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), + .owner = ENTRY(0) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), + TG0_TIMER0_RETENTION_REGS_BASE, TG0_TIMER0_RETENTION_REGS_BASE, + TG_TIMER0_RETENTION_REGS_CNT, 0, 0, + tg_timer0_regs_map[0], tg_timer0_regs_map[1], + tg_timer0_regs_map[2], tg_timer0_regs_map[3]), + .owner = ENTRY(0) + }, +}; + +const regdma_entries_config_t tg0_timer1_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x05), + TIMG_T1UPDATE_REG(0), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1), + .owner = ENTRY(0) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x06), + TIMG_T1UPDATE_REG(0), 0x0, TIMG_T1_UPDATE_M, 0, 1), + .owner = ENTRY(0) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x07), + TIMG_T1LO_REG(0), TIMG_T1LOADLO_REG(0), 2, 0, 0), + .owner = ENTRY(0) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x08), + TIMG_T1LOAD_REG(0), 0x1, TIMG_T1_LOAD_M, 1, 0), + .owner = ENTRY(0) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x09), + TG0_TIMER1_RETENTION_REGS_BASE, TG0_TIMER1_RETENTION_REGS_BASE, + TG_TIMER1_RETENTION_REGS_CNT, 0, 0, + tg_timer1_regs_map[0], tg_timer1_regs_map[1], + tg_timer1_regs_map[2], tg_timer1_regs_map[3]), + .owner = ENTRY(0) + }, +}; + +const regdma_entries_config_t tg1_timer0_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), + TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), + .owner = ENTRY(0) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), + TG1_TIMER0_RETENTION_REGS_BASE, TG1_TIMER0_RETENTION_REGS_BASE, + TG_TIMER0_RETENTION_REGS_CNT, 0, 0, + tg_timer0_regs_map[0], tg_timer0_regs_map[1], + tg_timer0_regs_map[2], tg_timer0_regs_map[3]), + .owner = ENTRY(0) + }, +}; + +const regdma_entries_config_t tg1_timer1_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05), + TIMG_T1UPDATE_REG(1), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1), + .owner = ENTRY(0) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x06), + TIMG_T1UPDATE_REG(1), 0x0, TIMG_T1_UPDATE_M, 0, 1), + .owner = ENTRY(0) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x07), + TIMG_T1LO_REG(1), TIMG_T1LOADLO_REG(1), 2, 0, 0), + .owner = ENTRY(0) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x08), + TIMG_T1LOAD_REG(1), 0x1, TIMG_T1_LOAD_M, 1, 0), + .owner = ENTRY(0) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x09), + TG1_TIMER1_RETENTION_REGS_BASE, TG1_TIMER1_RETENTION_REGS_BASE, + TG_TIMER1_RETENTION_REGS_CNT, 0, 0, + tg_timer1_regs_map[0], tg_timer1_regs_map[1], + tg_timer1_regs_map[2], tg_timer1_regs_map[3]), + .owner = ENTRY(0) + }, +}; + +const gptimer_retention_desc_t gptimer_retention_infos[2][2] = { + [0] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, + .regdma_entry_array = tg0_timer0_regdma_entries, + .array_size = ARRAY_SIZE(tg0_timer0_regdma_entries) + }, + [1] = { + .module = SLEEP_RETENTION_MODULE_TG0_TIMER1, + .regdma_entry_array = tg0_timer1_regdma_entries, + .array_size = ARRAY_SIZE(tg0_timer1_regdma_entries) + }, + }, + [1] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, + .regdma_entry_array = tg1_timer0_regdma_entries, + .array_size = ARRAY_SIZE(tg1_timer0_regdma_entries) + }, + [1] = { + .module = SLEEP_RETENTION_MODULE_TG1_TIMER1, + .regdma_entry_array = tg1_timer1_regdma_entries, + .array_size = ARRAY_SIZE(tg1_timer1_regdma_entries) + }, + }, +}; diff --git a/components/esp_driver_gptimer/esp32s31/timer_retention.c b/components/esp_driver_gptimer/esp32s31/timer_retention.c new file mode 100644 index 0000000000..a52e88a175 --- /dev/null +++ b/components/esp_driver_gptimer/esp32s31/timer_retention.c @@ -0,0 +1,216 @@ +/* + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "soc/timer_group_reg.h" +#include "gptimer_priv.h" + +/* Registers in retention context: + * TIMG_T0CONFIG_REG + * TIMG_T0ALARMLO_REG + * TIMG_T0ALARMHI_REG + * TIMG_T0LOADLO_REG + * TIMG_T0LOADHI_REG + * TIMG_INT_ENA_TIMERS_REG + * TIMG_REGCLK_REG + */ +#define TG0_TIMER0_RETENTION_REGS_BASE (REG_TIMG_BASE(0)) +#define TG1_TIMER0_RETENTION_REGS_BASE (REG_TIMG_BASE(1)) +#define TG_TIMER0_RETENTION_REGS_CNT 7 +static const uint32_t tg_timer0_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; + +/* Registers in retention context: + * TIMG_T1CONFIG_REG + * TIMG_T1ALARMLO_REG + * TIMG_T1ALARMHI_REG + * TIMG_T1LOADLO_REG + * TIMG_T1LOADHI_REG + * TIMG_INT_ENA_TIMERS_REG + * TIMG_REGCLK_REG + */ +#define TG0_TIMER1_RETENTION_REGS_BASE (REG_TIMG_BASE(0) + 0x24) +#define TG1_TIMER1_RETENTION_REGS_BASE (REG_TIMG_BASE(1) + 0x24) +#define TG_TIMER1_RETENTION_REGS_CNT 7 +static const uint32_t tg_timer1_regs_map[4] = {0x800f1, 0x400000, 0x0, 0x0}; + +const regdma_entries_config_t tg0_timer0_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), + TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), + TG0_TIMER0_RETENTION_REGS_BASE, TG0_TIMER0_RETENTION_REGS_BASE, + TG_TIMER0_RETENTION_REGS_CNT, 0, 0, + tg_timer0_regs_map[0], tg_timer0_regs_map[1], + tg_timer0_regs_map[2], tg_timer0_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const regdma_entries_config_t tg0_timer1_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x05), + TIMG_T1UPDATE_REG(0), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x06), + TIMG_T1UPDATE_REG(0), 0x0, TIMG_T1_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x07), + TIMG_T1LO_REG(0), TIMG_T1LOADLO_REG(0), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x08), + TIMG_T1LOAD_REG(0), 0x1, TIMG_T1_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x09), + TG0_TIMER1_RETENTION_REGS_BASE, TG0_TIMER1_RETENTION_REGS_BASE, + TG_TIMER1_RETENTION_REGS_CNT, 0, 0, + tg_timer1_regs_map[0], tg_timer1_regs_map[1], + tg_timer1_regs_map[2], tg_timer1_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const regdma_entries_config_t tg1_timer0_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), + TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), + TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), + TG1_TIMER0_RETENTION_REGS_BASE, TG1_TIMER0_RETENTION_REGS_BASE, + TG_TIMER0_RETENTION_REGS_CNT, 0, 0, + tg_timer0_regs_map[0], tg_timer0_regs_map[1], + tg_timer0_regs_map[2], tg_timer0_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const regdma_entries_config_t tg1_timer1_regdma_entries[] = { + // backup stage: trigger a soft capture + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05), + TIMG_T1UPDATE_REG(1), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x06), + TIMG_T1UPDATE_REG(1), 0x0, TIMG_T1_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x07), + TIMG_T1LO_REG(1), TIMG_T1LOADLO_REG(1), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x08), + TIMG_T1LOAD_REG(1), 0x1, TIMG_T1_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [4] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x09), + TG1_TIMER1_RETENTION_REGS_BASE, TG1_TIMER1_RETENTION_REGS_BASE, + TG_TIMER1_RETENTION_REGS_CNT, 0, 0, + tg_timer1_regs_map[0], tg_timer1_regs_map[1], + tg_timer1_regs_map[2], tg_timer1_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const gptimer_retention_desc_t gptimer_retention_infos[2][2] = { + [0] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, + .regdma_entry_array = tg0_timer0_regdma_entries, + .array_size = ARRAY_SIZE(tg0_timer0_regdma_entries) + }, + [1] = { + .module = SLEEP_RETENTION_MODULE_TG0_TIMER1, + .regdma_entry_array = tg0_timer1_regdma_entries, + .array_size = ARRAY_SIZE(tg0_timer1_regdma_entries) + }, + }, + [1] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, + .regdma_entry_array = tg1_timer0_regdma_entries, + .array_size = ARRAY_SIZE(tg1_timer0_regdma_entries) + }, + [1] = { + .module = SLEEP_RETENTION_MODULE_TG1_TIMER1, + .regdma_entry_array = tg1_timer1_regdma_entries, + .array_size = ARRAY_SIZE(tg1_timer1_regdma_entries) + }, + }, +}; diff --git a/components/esp_driver_gptimer/src/gptimer.c b/components/esp_driver_gptimer/src/gptimer.c index fe90ffd3d9..cabbecf78d 100644 --- a/components/esp_driver_gptimer/src/gptimer.c +++ b/components/esp_driver_gptimer/src/gptimer.c @@ -17,9 +17,9 @@ static esp_err_t gptimer_create_sleep_retention_link_cb(void *timer) { int group_id = ((gptimer_t *)timer)->group->group_id; int timer_id = ((gptimer_t *)timer)->timer_id; - esp_err_t err = sleep_retention_entries_create(soc_timg_gptimer_retention_infos[group_id][timer_id].regdma_entry_array, - soc_timg_gptimer_retention_infos[group_id][timer_id].array_size, - REGDMA_LINK_PRI_GPTIMER, soc_timg_gptimer_retention_infos[group_id][timer_id].module); + esp_err_t err = sleep_retention_entries_create(gptimer_retention_infos[group_id][timer_id].regdma_entry_array, + gptimer_retention_infos[group_id][timer_id].array_size, + REGDMA_LINK_PRI_GPTIMER, gptimer_retention_infos[group_id][timer_id].module); return err; } @@ -27,7 +27,7 @@ static void gptimer_create_retention_module(gptimer_t *timer) { int group_id = timer->group->group_id; int timer_id = timer->timer_id; - sleep_retention_module_t module = soc_timg_gptimer_retention_infos[group_id][timer_id].module; + sleep_retention_module_t module = gptimer_retention_infos[group_id][timer_id].module; if (sleep_retention_is_module_inited(module) && !sleep_retention_is_module_created(module)) { if (sleep_retention_module_allocate(module) != ESP_OK) { // even though the sleep retention module create failed, GPTimer driver should still work, so just warning here @@ -65,7 +65,7 @@ static esp_err_t gptimer_register_to_group(gptimer_t *timer) ESP_RETURN_ON_FALSE(timer_id != -1, ESP_ERR_NOT_FOUND, TAG, "no free timer"); #if GPTIMER_USE_RETENTION_LINK - sleep_retention_module_t module = soc_timg_gptimer_retention_infos[group->group_id][timer_id].module; + sleep_retention_module_t module = gptimer_retention_infos[group->group_id][timer_id].module; sleep_retention_module_init_param_t init_param = { .cbs = { .create = { @@ -93,7 +93,7 @@ static void gptimer_unregister_from_group(gptimer_t *timer) portEXIT_CRITICAL(&group->spinlock); #if GPTIMER_USE_RETENTION_LINK - sleep_retention_module_t module = soc_timg_gptimer_retention_infos[group->group_id][timer_id].module; + sleep_retention_module_t module = gptimer_retention_infos[group->group_id][timer_id].module; if (sleep_retention_is_module_created(module)) { sleep_retention_module_free(module); } diff --git a/components/esp_driver_gptimer/src/gptimer_priv.h b/components/esp_driver_gptimer/src/gptimer_priv.h index 23ae985acc..d1c679203d 100644 --- a/components/esp_driver_gptimer/src/gptimer_priv.h +++ b/components/esp_driver_gptimer/src/gptimer_priv.h @@ -23,6 +23,7 @@ #include "esp_intr_alloc.h" #include "esp_heap_caps.h" #include "esp_pm.h" +#include "soc/regdma.h" #include "hal/timer_periph.h" #include "hal/timer_types.h" #include "hal/timer_hal.h" @@ -31,6 +32,7 @@ #include "esp_private/esp_clk_tree_common.h" #include "esp_private/sleep_retention.h" #include "esp_private/periph_ctrl.h" +#include "driver/gptimer_types.h" #ifdef __cplusplus extern "C" { @@ -102,6 +104,18 @@ gptimer_group_t *gptimer_acquire_group_handle(int group_id); void gptimer_release_group_handle(gptimer_group_t *group); esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t src_clk, uint32_t resolution_hz); +#if SOC_PAU_SUPPORTED && SOC_TIMER_SUPPORT_SLEEP_RETENTION +#include "soc/retention_periph_defs.h" + +typedef struct { + const periph_retention_module_t module; + const regdma_entries_config_t *regdma_entry_array; + const size_t array_size; +} gptimer_retention_desc_t; + +extern const gptimer_retention_desc_t gptimer_retention_infos[TIMG_LL_GET(INST_NUM)][TIMG_LL_GET(GPTIMERS_PER_INST)]; +#endif // SOC_PAU_SUPPORTED && SOC_TIMER_SUPPORT_SLEEP_RETENTION + #ifdef __cplusplus } #endif diff --git a/components/esp_hal_timg/esp32c5/timer_periph.c b/components/esp_hal_timg/esp32c5/timer_periph.c index 4584fc3feb..911b8e117d 100644 --- a/components/esp_hal_timg/esp32c5/timer_periph.c +++ b/components/esp_hal_timg/esp32c5/timer_periph.c @@ -22,108 +22,3 @@ const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][1] = { }, } }; - -/* Registers in retention context: - * TIMG_T0CONFIG_REG - * TIMG_T0ALARMLO_REG - * TIMG_T0ALARMHI_REG - * TIMG_T0LOADLO_REG - * TIMG_T0LOADHI_REG - * TIMG_INT_ENA_TIMERS_REG - * TIMG_REGCLK_REG - */ -#define TG_TIMER_RETENTION_REGS_CNT 7 -static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; - -const regdma_entries_config_t tg0_timer_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), - TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const regdma_entries_config_t tg1_timer_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), - TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[2][1] = { - [0] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, - .regdma_entry_array = tg0_timer_regdma_entries, - .array_size = ARRAY_SIZE(tg0_timer_regdma_entries) - } - }, - [1] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, - .regdma_entry_array = tg1_timer_regdma_entries, - .array_size = ARRAY_SIZE(tg1_timer_regdma_entries) - } - }, -}; diff --git a/components/esp_hal_timg/esp32c6/timer_periph.c b/components/esp_hal_timg/esp32c6/timer_periph.c index 4584fc3feb..911b8e117d 100644 --- a/components/esp_hal_timg/esp32c6/timer_periph.c +++ b/components/esp_hal_timg/esp32c6/timer_periph.c @@ -22,108 +22,3 @@ const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][1] = { }, } }; - -/* Registers in retention context: - * TIMG_T0CONFIG_REG - * TIMG_T0ALARMLO_REG - * TIMG_T0ALARMHI_REG - * TIMG_T0LOADLO_REG - * TIMG_T0LOADHI_REG - * TIMG_INT_ENA_TIMERS_REG - * TIMG_REGCLK_REG - */ -#define TG_TIMER_RETENTION_REGS_CNT 7 -static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; - -const regdma_entries_config_t tg0_timer_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), - TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const regdma_entries_config_t tg1_timer_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), - TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[2][1] = { - [0] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, - .regdma_entry_array = tg0_timer_regdma_entries, - .array_size = ARRAY_SIZE(tg0_timer_regdma_entries) - } - }, - [1] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, - .regdma_entry_array = tg1_timer_regdma_entries, - .array_size = ARRAY_SIZE(tg1_timer_regdma_entries) - } - }, -}; diff --git a/components/esp_hal_timg/esp32c61/timer_periph.c b/components/esp_hal_timg/esp32c61/timer_periph.c index 8c412b5c44..310d6ed893 100644 --- a/components/esp_hal_timg/esp32c61/timer_periph.c +++ b/components/esp_hal_timg/esp32c61/timer_periph.c @@ -22,108 +22,3 @@ const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][1] = { }, } }; - -/* Registers in retention context: - * TIMG_T0CONFIG_REG - * TIMG_T0ALARMLO_REG - * TIMG_T0ALARMHI_REG - * TIMG_T0LOADLO_REG - * TIMG_T0LOADHI_REG - * TIMG_INT_ENA_TIMERS_REG - * TIMG_REGCLK_REG - */ -#define TG_TIMER_RETENTION_REGS_CNT 7 -static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; - -const regdma_entries_config_t tg0_timer_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), - TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const regdma_entries_config_t tg1_timer_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), - TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[2][1] = { - [0] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, - .regdma_entry_array = tg0_timer_regdma_entries, - .array_size = ARRAY_SIZE(tg0_timer_regdma_entries) - } - }, - [1] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, - .regdma_entry_array = tg1_timer_regdma_entries, - .array_size = ARRAY_SIZE(tg1_timer_regdma_entries) - } - }, -}; diff --git a/components/esp_hal_timg/esp32h2/timer_periph.c b/components/esp_hal_timg/esp32h2/timer_periph.c index 4584fc3feb..911b8e117d 100644 --- a/components/esp_hal_timg/esp32h2/timer_periph.c +++ b/components/esp_hal_timg/esp32h2/timer_periph.c @@ -22,108 +22,3 @@ const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][1] = { }, } }; - -/* Registers in retention context: - * TIMG_T0CONFIG_REG - * TIMG_T0ALARMLO_REG - * TIMG_T0ALARMHI_REG - * TIMG_T0LOADLO_REG - * TIMG_T0LOADHI_REG - * TIMG_INT_ENA_TIMERS_REG - * TIMG_REGCLK_REG - */ -#define TG_TIMER_RETENTION_REGS_CNT 7 -static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; - -const regdma_entries_config_t tg0_timer_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), - TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const regdma_entries_config_t tg1_timer_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), - TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[2][1] = { - [0] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, - .regdma_entry_array = tg0_timer_regdma_entries, - .array_size = ARRAY_SIZE(tg0_timer_regdma_entries) - } - }, - [1] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, - .regdma_entry_array = tg1_timer_regdma_entries, - .array_size = ARRAY_SIZE(tg1_timer_regdma_entries) - } - }, -}; diff --git a/components/esp_hal_timg/esp32h21/timer_periph.c b/components/esp_hal_timg/esp32h21/timer_periph.c index eb9333209a..9fd9358c2e 100644 --- a/components/esp_hal_timg/esp32h21/timer_periph.c +++ b/components/esp_hal_timg/esp32h21/timer_periph.c @@ -22,108 +22,3 @@ const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][1] = { }, } }; - -/* Registers in retention context: - * TIMG_T0CONFIG_REG - * TIMG_T0ALARMLO_REG - * TIMG_T0ALARMHI_REG - * TIMG_T0LOADLO_REG - * TIMG_T0LOADHI_REG - * TIMG_INT_ENA_TIMERS_REG - * TIMG_REGCLK_REG - */ -#define TG_TIMER_RETENTION_REGS_CNT 7 -static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; - -const regdma_entries_config_t tg0_timer_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), - TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const regdma_entries_config_t tg1_timer_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), - TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[2][1] = { - [0] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, - .regdma_entry_array = tg0_timer_regdma_entries, - .array_size = ARRAY_SIZE(tg0_timer_regdma_entries) - } - }, - [1] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, - .regdma_entry_array = tg1_timer_regdma_entries, - .array_size = ARRAY_SIZE(tg1_timer_regdma_entries) - } - }, -}; diff --git a/components/esp_hal_timg/esp32h4/timer_periph.c b/components/esp_hal_timg/esp32h4/timer_periph.c index eb9333209a..9fd9358c2e 100644 --- a/components/esp_hal_timg/esp32h4/timer_periph.c +++ b/components/esp_hal_timg/esp32h4/timer_periph.c @@ -22,108 +22,3 @@ const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][1] = { }, } }; - -/* Registers in retention context: - * TIMG_T0CONFIG_REG - * TIMG_T0ALARMLO_REG - * TIMG_T0ALARMHI_REG - * TIMG_T0LOADLO_REG - * TIMG_T0LOADHI_REG - * TIMG_INT_ENA_TIMERS_REG - * TIMG_REGCLK_REG - */ -#define TG_TIMER_RETENTION_REGS_CNT 7 -static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; - -const regdma_entries_config_t tg0_timer_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), - TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const regdma_entries_config_t tg1_timer_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), - TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), - TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), - TG_TIMER_RETENTION_REGS_CNT, 0, 0, - tg_timer_regs_map[0], tg_timer_regs_map[1], - tg_timer_regs_map[2], tg_timer_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[2][1] = { - [0] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, - .regdma_entry_array = tg0_timer_regdma_entries, - .array_size = ARRAY_SIZE(tg0_timer_regdma_entries) - } - }, - [1] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, - .regdma_entry_array = tg1_timer_regdma_entries, - .array_size = ARRAY_SIZE(tg1_timer_regdma_entries) - } - }, -}; diff --git a/components/esp_hal_timg/esp32p4/timer_periph.c b/components/esp_hal_timg/esp32p4/timer_periph.c index a9563248eb..5bf11165c1 100644 --- a/components/esp_hal_timg/esp32p4/timer_periph.c +++ b/components/esp_hal_timg/esp32p4/timer_periph.c @@ -32,210 +32,3 @@ const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][2] = { }, } }; - -/* Registers in retention context: - * TIMG_T0CONFIG_REG - * TIMG_T0ALARMLO_REG - * TIMG_T0ALARMHI_REG - * TIMG_T0LOADLO_REG - * TIMG_T0LOADHI_REG - * TIMG_INT_ENA_TIMERS_REG - * TIMG_REGCLK_REG - */ -#define TG0_TIMER0_RETENTION_REGS_BASE (REG_TIMG_BASE(0)) -#define TG1_TIMER0_RETENTION_REGS_BASE (REG_TIMG_BASE(1)) -#define TG_TIMER0_RETENTION_REGS_CNT 7 -static const uint32_t tg_timer0_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; - -/* Registers in retention context: - * TIMG_T1CONFIG_REG - * TIMG_T1ALARMLO_REG - * TIMG_T1ALARMHI_REG - * TIMG_T1LOADLO_REG - * TIMG_T1LOADHI_REG - * TIMG_INT_ENA_TIMERS_REG - * TIMG_REGCLK_REG - */ -#define TG0_TIMER1_RETENTION_REGS_BASE (REG_TIMG_BASE(0) + 0x24) -#define TG1_TIMER1_RETENTION_REGS_BASE (REG_TIMG_BASE(1) + 0x24) -#define TG_TIMER1_RETENTION_REGS_CNT 7 -static const uint32_t tg_timer1_regs_map[4] = {0x800f1, 0x400000, 0x0, 0x0}; - -const regdma_entries_config_t tg0_timer0_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), - TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), - .owner = ENTRY(0) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), - TG0_TIMER0_RETENTION_REGS_BASE, TG0_TIMER0_RETENTION_REGS_BASE, - TG_TIMER0_RETENTION_REGS_CNT, 0, 0, - tg_timer0_regs_map[0], tg_timer0_regs_map[1], - tg_timer0_regs_map[2], tg_timer0_regs_map[3]), - .owner = ENTRY(0) - }, -}; - -const regdma_entries_config_t tg0_timer1_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x05), - TIMG_T1UPDATE_REG(0), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x06), - TIMG_T1UPDATE_REG(0), 0x0, TIMG_T1_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x07), - TIMG_T1LO_REG(0), TIMG_T1LOADLO_REG(0), 2, 0, 0), - .owner = ENTRY(0) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x08), - TIMG_T1LOAD_REG(0), 0x1, TIMG_T1_LOAD_M, 1, 0), - .owner = ENTRY(0) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x09), - TG0_TIMER1_RETENTION_REGS_BASE, TG0_TIMER1_RETENTION_REGS_BASE, - TG_TIMER1_RETENTION_REGS_CNT, 0, 0, - tg_timer1_regs_map[0], tg_timer1_regs_map[1], - tg_timer1_regs_map[2], tg_timer1_regs_map[3]), - .owner = ENTRY(0) - }, -}; - -const regdma_entries_config_t tg1_timer0_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), - TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), - .owner = ENTRY(0) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), - TG1_TIMER0_RETENTION_REGS_BASE, TG1_TIMER0_RETENTION_REGS_BASE, - TG_TIMER0_RETENTION_REGS_CNT, 0, 0, - tg_timer0_regs_map[0], tg_timer0_regs_map[1], - tg_timer0_regs_map[2], tg_timer0_regs_map[3]), - .owner = ENTRY(0) - }, -}; - -const regdma_entries_config_t tg1_timer1_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05), - TIMG_T1UPDATE_REG(1), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x06), - TIMG_T1UPDATE_REG(1), 0x0, TIMG_T1_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x07), - TIMG_T1LO_REG(1), TIMG_T1LOADLO_REG(1), 2, 0, 0), - .owner = ENTRY(0) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x08), - TIMG_T1LOAD_REG(1), 0x1, TIMG_T1_LOAD_M, 1, 0), - .owner = ENTRY(0) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x09), - TG1_TIMER1_RETENTION_REGS_BASE, TG1_TIMER1_RETENTION_REGS_BASE, - TG_TIMER1_RETENTION_REGS_CNT, 0, 0, - tg_timer1_regs_map[0], tg_timer1_regs_map[1], - tg_timer1_regs_map[2], tg_timer1_regs_map[3]), - .owner = ENTRY(0) - }, -}; - -const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[2][2] = { - [0] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, - .regdma_entry_array = tg0_timer0_regdma_entries, - .array_size = ARRAY_SIZE(tg0_timer0_regdma_entries) - }, - [1] = { - .module = SLEEP_RETENTION_MODULE_TG0_TIMER1, - .regdma_entry_array = tg0_timer1_regdma_entries, - .array_size = ARRAY_SIZE(tg0_timer1_regdma_entries) - }, - }, - [1] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, - .regdma_entry_array = tg1_timer0_regdma_entries, - .array_size = ARRAY_SIZE(tg1_timer0_regdma_entries) - }, - [1] = { - .module = SLEEP_RETENTION_MODULE_TG1_TIMER1, - .regdma_entry_array = tg1_timer1_regdma_entries, - .array_size = ARRAY_SIZE(tg1_timer1_regdma_entries) - }, - }, -}; diff --git a/components/esp_hal_timg/esp32s31/timer_periph.c b/components/esp_hal_timg/esp32s31/timer_periph.c index 308c093588..bc9f888fea 100644 --- a/components/esp_hal_timg/esp32s31/timer_periph.c +++ b/components/esp_hal_timg/esp32s31/timer_periph.c @@ -32,212 +32,3 @@ const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][2] = { }, } }; - -#if SOC_PAU_SUPPORTED && SOC_TIMER_SUPPORT_SLEEP_RETENTION -/* Registers in retention context: - * TIMG_T0CONFIG_REG - * TIMG_T0ALARMLO_REG - * TIMG_T0ALARMHI_REG - * TIMG_T0LOADLO_REG - * TIMG_T0LOADHI_REG - * TIMG_INT_ENA_TIMERS_REG - * TIMG_REGCLK_REG - */ -#define TG0_TIMER0_RETENTION_REGS_BASE (REG_TIMG_BASE(0)) -#define TG1_TIMER0_RETENTION_REGS_BASE (REG_TIMG_BASE(1)) -#define TG_TIMER0_RETENTION_REGS_CNT 7 -static const uint32_t tg_timer0_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; - -/* Registers in retention context: - * TIMG_T1CONFIG_REG - * TIMG_T1ALARMLO_REG - * TIMG_T1ALARMHI_REG - * TIMG_T1LOADLO_REG - * TIMG_T1LOADHI_REG - * TIMG_INT_ENA_TIMERS_REG - * TIMG_REGCLK_REG - */ -#define TG0_TIMER1_RETENTION_REGS_BASE (REG_TIMG_BASE(0) + 0x24) -#define TG1_TIMER1_RETENTION_REGS_BASE (REG_TIMG_BASE(1) + 0x24) -#define TG_TIMER1_RETENTION_REGS_CNT 7 -static const uint32_t tg_timer1_regs_map[4] = {0x800f1, 0x400000, 0x0, 0x0}; - -const regdma_entries_config_t tg0_timer0_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), - TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), - .owner = ENTRY(0) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04), - TG0_TIMER0_RETENTION_REGS_BASE, TG0_TIMER0_RETENTION_REGS_BASE, - TG_TIMER0_RETENTION_REGS_CNT, 0, 0, - tg_timer0_regs_map[0], tg_timer0_regs_map[1], - tg_timer0_regs_map[2], tg_timer0_regs_map[3]), - .owner = ENTRY(0) - }, -}; - -const regdma_entries_config_t tg0_timer1_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x05), - TIMG_T1UPDATE_REG(0), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x06), - TIMG_T1UPDATE_REG(0), 0x0, TIMG_T1_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x07), - TIMG_T1LO_REG(0), TIMG_T1LOADLO_REG(0), 2, 0, 0), - .owner = ENTRY(0) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x08), - TIMG_T1LOAD_REG(0), 0x1, TIMG_T1_LOAD_M, 1, 0), - .owner = ENTRY(0) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x09), - TG0_TIMER1_RETENTION_REGS_BASE, TG0_TIMER1_RETENTION_REGS_BASE, - TG_TIMER1_RETENTION_REGS_CNT, 0, 0, - tg_timer1_regs_map[0], tg_timer1_regs_map[1], - tg_timer1_regs_map[2], tg_timer1_regs_map[3]), - .owner = ENTRY(0) - }, -}; - -const regdma_entries_config_t tg1_timer0_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), - TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), - TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), - TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), - .owner = ENTRY(0) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03), - TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), - .owner = ENTRY(0) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04), - TG1_TIMER0_RETENTION_REGS_BASE, TG1_TIMER0_RETENTION_REGS_BASE, - TG_TIMER0_RETENTION_REGS_CNT, 0, 0, - tg_timer0_regs_map[0], tg_timer0_regs_map[1], - tg_timer0_regs_map[2], tg_timer0_regs_map[3]), - .owner = ENTRY(0) - }, -}; - -const regdma_entries_config_t tg1_timer1_regdma_entries[] = { - // backup stage: trigger a soft capture - [0] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05), - TIMG_T1UPDATE_REG(1), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: wait for the capture done - [1] = { - .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x06), - TIMG_T1UPDATE_REG(1), 0x0, TIMG_T1_UPDATE_M, 0, 1), - .owner = ENTRY(0) - }, - // backup stage: save the captured counter value - // restore stage: store the captured counter value to the loader register - [2] = { - .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x07), - TIMG_T1LO_REG(1), TIMG_T1LOADLO_REG(1), 2, 0, 0), - .owner = ENTRY(0) - }, - // restore stage: trigger a soft reload, so the timer can continue from where it was backed up - [3] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x08), - TIMG_T1LOAD_REG(1), 0x1, TIMG_T1_LOAD_M, 1, 0), - .owner = ENTRY(0) - }, - // backup stage: save other configuration and status registers - // restore stage: restore the configuration and status registers - [4] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x09), - TG1_TIMER1_RETENTION_REGS_BASE, TG1_TIMER1_RETENTION_REGS_BASE, - TG_TIMER1_RETENTION_REGS_CNT, 0, 0, - tg_timer1_regs_map[0], tg_timer1_regs_map[1], - tg_timer1_regs_map[2], tg_timer1_regs_map[3]), - .owner = ENTRY(0) - }, -}; - -const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[2][2] = { - [0] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG0_TIMER0, - .regdma_entry_array = tg0_timer0_regdma_entries, - .array_size = ARRAY_SIZE(tg0_timer0_regdma_entries) - }, - [1] = { - .module = SLEEP_RETENTION_MODULE_TG0_TIMER1, - .regdma_entry_array = tg0_timer1_regdma_entries, - .array_size = ARRAY_SIZE(tg0_timer1_regdma_entries) - }, - }, - [1] = { - [0] = { - .module = SLEEP_RETENTION_MODULE_TG1_TIMER0, - .regdma_entry_array = tg1_timer0_regdma_entries, - .array_size = ARRAY_SIZE(tg1_timer0_regdma_entries) - }, - [1] = { - .module = SLEEP_RETENTION_MODULE_TG1_TIMER1, - .regdma_entry_array = tg1_timer1_regdma_entries, - .array_size = ARRAY_SIZE(tg1_timer1_regdma_entries) - }, - }, -}; -#endif // SOC_PAU_SUPPORTED diff --git a/components/esp_hal_timg/include/hal/timer_periph.h b/components/esp_hal_timg/include/hal/timer_periph.h index 905dafe435..3b14071f7b 100644 --- a/components/esp_hal_timg/include/hal/timer_periph.h +++ b/components/esp_hal_timg/include/hal/timer_periph.h @@ -12,13 +12,8 @@ #include "soc/timer_group_struct.h" #include "soc/soc_caps.h" #include "soc/periph_defs.h" -#include "soc/regdma.h" #include "hal/timer_ll.h" -#if SOC_HAS(PAU) -#include "soc/retention_periph_defs.h" -#endif // SOC_HAS(PAU) - #ifdef __cplusplus extern "C" { #endif @@ -31,16 +26,6 @@ typedef struct { extern const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[TIMG_LL_GET(INST_NUM)][TIMG_LL_GET(GPTIMERS_PER_INST)]; -#if SOC_HAS(PAU) -typedef struct { - const periph_retention_module_t module; // ID of the GPTimer as a retention module - const regdma_entries_config_t *regdma_entry_array; // Array of regdma entries for retention - const size_t array_size; // Size of the regdma_entry_array -} soc_timg_gptimer_retention_desc_t; - -extern const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[TIMG_LL_GET(INST_NUM)][TIMG_LL_GET(GPTIMERS_PER_INST)]; -#endif // SOC_HAS(PAU) - #ifdef __cplusplus } #endif