diff --git a/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h b/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h
index cd8e4a0176..0abbdf81b5 100644
--- a/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h
+++ b/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,13 +23,13 @@
 #elif CONFIG_IDF_TARGET_ESP32S2
 #define IDF_TARGET_MAX_SPI_CLK_FREQ                 40*1000*1000
 #define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          15
-#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          15
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          13
 #define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          32
 #define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          30
 
 #elif CONFIG_IDF_TARGET_ESP32S3
 #define IDF_TARGET_MAX_SPI_CLK_FREQ                 40*1000*1000
-#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          15
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          17
 #define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          15
 #define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          32
 #define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          30
@@ -44,9 +44,9 @@
 #elif CONFIG_IDF_TARGET_ESP32C3
 #define IDF_TARGET_MAX_SPI_CLK_FREQ                 40*1000*1000
 #if !CONFIG_FREERTOS_SMP // IDF-5826
-#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          15
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          17
 #define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          15
-#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          33
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          35
 #define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          30
 #else
 #define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          17
@@ -58,7 +58,7 @@
 #elif CONFIG_IDF_TARGET_ESP32C6
 #define IDF_TARGET_MAX_SPI_CLK_FREQ                 26666*1000
 #define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          35  //TODO: IDF-9551, check perform
-#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          17
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          19
 #define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          32
 #define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          15
 
diff --git a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c
index ad904a6b62..2f741f685a 100644
--- a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c
+++ b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c
@@ -137,7 +137,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
 
 // Test All clock source
 #define TEST_CLK_BYTE_LEN           10000
-#define TEST_TRANS_TIME_BIAS_RATIO  (float)8.0/100   // think 8% transfer time bias as acceptable
+#define TEST_TRANS_TIME_BIAS_RATIO  (float)10.0/100   // think 10% transfer time bias as acceptable
 TEST_CASE("SPI Master clk_source and divider accuracy", "[spi]")
 {
     int64_t start = 0, end = 0;
diff --git a/components/esp_driver_spi/test_apps/param/main/test_spi_param.c b/components/esp_driver_spi/test_apps/param/main/test_spi_param.c
index b52f4c3887..d8617f9385 100644
--- a/components/esp_driver_spi/test_apps/param/main/test_spi_param.c
+++ b/components/esp_driver_spi/test_apps/param/main/test_spi_param.c
@@ -1460,14 +1460,16 @@ static void test_slave_fd_no_dma(void)
                     test_fill_random_to_buffers_dualboard(211 + mode + speed_level + i, slave_expect, slave_send, SOC_SPI_MAXIMUM_BUFFER_SIZE);
 
                     uint32_t test_trans_len = SOC_SPI_MAXIMUM_BUFFER_SIZE;
-                    spi_slave_transaction_t trans_cfg = {
+                    spi_slave_transaction_t *ret_trans, trans_cfg = {
                         .tx_buffer = slave_send,
                         .rx_buffer = slave_receive,
                         .length = test_trans_len * 8,
                         .flags = SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO,
                     };
+                    TEST_ESP_OK(spi_slave_queue_trans(TEST_SPI_HOST, &trans_cfg, portMAX_DELAY));
                     unity_send_signal("Slave ready");
-                    TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &trans_cfg, portMAX_DELAY));
+                    TEST_ESP_OK(spi_slave_get_trans_result(TEST_SPI_HOST, &ret_trans, portMAX_DELAY));
+                    TEST_ASSERT_EQUAL(&trans_cfg, ret_trans);
 
                     ESP_LOG_BUFFER_HEX("slave tx", slave_send, test_trans_len);
                     ESP_LOG_BUFFER_HEX_LEVEL("slave rx", slave_receive, test_trans_len, ESP_LOG_DEBUG);
@@ -1952,14 +1954,15 @@ static void test_slave_sio_no_dma(void)
                 for (int i = 0; i < TEST_STEP; i++) {
                     memset(slave_receive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE);
                     test_fill_random_to_buffers_dualboard(122 + mode + speed_level + i, slave_expect, slave_send, SOC_SPI_MAXIMUM_BUFFER_SIZE);
-                    spi_slave_transaction_t trans = {
+                    spi_slave_transaction_t *ret_trans, trans = {
                         .length = SOC_SPI_MAXIMUM_BUFFER_SIZE * 8,
                         .tx_buffer = slave_send,
                         .rx_buffer = slave_receive,
                         .flags = SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO,
                     };
+                    TEST_ESP_OK(spi_slave_queue_trans(TEST_SPI_HOST, &trans, portMAX_DELAY));
                     unity_send_signal("Slave ready");
-                    TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &trans, portMAX_DELAY));
+                    TEST_ESP_OK(spi_slave_get_trans_result(TEST_SPI_HOST, &ret_trans, portMAX_DELAY));
 
                     if (sio_master_in) {
                         ESP_LOG_BUFFER_HEX("Slave tx", trans.tx_buffer, SOC_SPI_MAXIMUM_BUFFER_SIZE);