diff --git a/components/efuse/esp32h4/esp_efuse_table.c b/components/efuse/esp32h4/esp_efuse_table.c index f6c50815a7..cd23214bb2 100644 --- a/components/efuse/esp32h4/esp_efuse_table.c +++ b/components/efuse/esp32h4/esp_efuse_table.c @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 39c442690c2273d557b5bb0db99fbe04 +// md5_digest_table 00c61e1122b40bab1153117e162a713c // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -407,8 +407,8 @@ static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = { {EFUSE_BLK0, 99, 1}, // [] Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: Disable, }; -static const esp_efuse_desc_t ECDSA_P384_ENABLE[] = { - {EFUSE_BLK0, 100, 1}, // [] Represents if the chip supports ECDSA P384, +static const esp_efuse_desc_t SECURE_BOOT_SHA384_EN[] = { + {EFUSE_BLK0, 100, 1}, // [] Represents if the chip supports Secure Boot using SHA-384, }; static const esp_efuse_desc_t SECURE_BOOT_EN[] = { @@ -1099,8 +1099,8 @@ const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_ECDSA_P384_ENABLE[] = { - &ECDSA_P384_ENABLE[0], // [] Represents if the chip supports ECDSA P384 +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_SHA384_EN[] = { + &SECURE_BOOT_SHA384_EN[0], // [] Represents if the chip supports Secure Boot using SHA-384 NULL }; diff --git a/components/efuse/esp32h4/esp_efuse_table.csv b/components/efuse/esp32h4/esp_efuse_table.csv index 79b91f8788..a45867b93b 100644 --- a/components/efuse/esp32h4/esp_efuse_table.csv +++ b/components/efuse/esp32h4/esp_efuse_table.csv @@ -109,7 +109,7 @@ SEC_DPA_LEVEL, EFUSE_BLK0, 94, 2, [] Repres XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 96, 2, [] Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 98, 1, [] Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable. ECC_FORCE_CONST_TIME, EFUSE_BLK0, 99, 1, [] Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: Disable -ECDSA_P384_ENABLE, EFUSE_BLK0, 100, 1, [] Represents if the chip supports ECDSA P384 +SECURE_BOOT_SHA384_EN, EFUSE_BLK0, 100, 1, [] Represents if the chip supports Secure Boot using SHA-384 SECURE_BOOT_EN, EFUSE_BLK0, 101, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled 0: disabled SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 102, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 103, 5, [] Represents whether the new key deployment of key manager is disabled. Bit0: Represents whether the new ECDSA key deployment is disabled0: Enabled1: DisabledBit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is disabled0: Enabled1: DisabledBit2: Represents whether the new HMAC key deployment is disabled0: Enabled1: DisabledBit3: Represents whether the new DS key deployment is disabled0: Enabled1: Disabled diff --git a/components/efuse/esp32h4/include/esp_efuse_table.h b/components/efuse/esp32h4/include/esp_efuse_table.h index 962ed586eb..56af793e4c 100644 --- a/components/efuse/esp32h4/include/esp_efuse_table.h +++ b/components/efuse/esp32h4/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 39c442690c2273d557b5bb0db99fbe04 +// md5_digest_table 00c61e1122b40bab1153117e162a713c // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -145,7 +145,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_P384_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_SHA384_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[]; diff --git a/components/soc/esp32c5/register/soc/efuse_reg.h b/components/soc/esp32c5/register/soc/efuse_reg.h index 68f499134a..27586bca8d 100644 --- a/components/soc/esp32c5/register/soc/efuse_reg.h +++ b/components/soc/esp32c5/register/soc/efuse_reg.h @@ -726,7 +726,7 @@ extern "C" { #define EFUSE_RD_RESERVE_0_158_M (EFUSE_RD_RESERVE_0_158_V << EFUSE_RD_RESERVE_0_158_S) #define EFUSE_RD_RESERVE_0_158_V 0x00000001U #define EFUSE_RD_RESERVE_0_158_S 30 -/** EFUSE_ECDSA_P384_ENABLE : RO; bitpos: [31]; default: 0; +/** EFUSE_SECURE_BOOT_SHA384_EN : RO; bitpos: [31]; default: 0; * Represents if the chip supports Secure Boot using SHA-384 */ #define EFUSE_SECURE_BOOT_SHA384_EN (BIT(31)) diff --git a/components/soc/esp32h4/register/soc/efuse_reg.h b/components/soc/esp32h4/register/soc/efuse_reg.h index 2d7660866a..26fd1f69b1 100644 --- a/components/soc/esp32h4/register/soc/efuse_reg.h +++ b/components/soc/esp32h4/register/soc/efuse_reg.h @@ -399,13 +399,13 @@ extern "C" { #define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) #define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U #define EFUSE_ECC_FORCE_CONST_TIME_S 3 -/** EFUSE_ECDSA_P384_ENABLE : RO; bitpos: [4]; default: 0; - * Represents if the chip supports ECDSA P384 +/** EFUSE_SECURE_BOOT_SHA384_EN : RO; bitpos: [4]; default: 0; + * Represents if the chip supports Secure Boot using SHA-384 */ -#define EFUSE_ECDSA_P384_ENABLE (BIT(4)) -#define EFUSE_ECDSA_P384_ENABLE_M (EFUSE_ECDSA_P384_ENABLE_V << EFUSE_ECDSA_P384_ENABLE_S) -#define EFUSE_ECDSA_P384_ENABLE_V 0x00000001U -#define EFUSE_ECDSA_P384_ENABLE_S 4 +#define EFUSE_SECURE_BOOT_SHA384_EN (BIT(4)) +#define EFUSE_SECURE_BOOT_SHA384_EN_M (EFUSE_SECURE_BOOT_SHA384_EN_V << EFUSE_SECURE_BOOT_SHA384_EN_S) +#define EFUSE_SECURE_BOOT_SHA384_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_SHA384_EN_S 4 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [5]; default: 0; * Represents whether secure boot is enabled or disabled. * 1: enabled @@ -1935,13 +1935,13 @@ extern "C" { #define EFUSE_ECC_FORCE_CONST_TIME_ERR_M (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S) #define EFUSE_ECC_FORCE_CONST_TIME_ERR_V 0x00000001U #define EFUSE_ECC_FORCE_CONST_TIME_ERR_S 3 -/** EFUSE_ECDSA_P384_ENABLE_ERR : RO; bitpos: [4]; default: 0; - * Represents the programming error of EFUSE_ECDSA_P384_ENABLE +/** EFUSE_SECURE_BOOT_SHA384_EN_ERR : RO; bitpos: [4]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_SHA384_EN */ -#define EFUSE_ECDSA_P384_ENABLE_ERR (BIT(4)) -#define EFUSE_ECDSA_P384_ENABLE_ERR_M (EFUSE_ECDSA_P384_ENABLE_ERR_V << EFUSE_ECDSA_P384_ENABLE_ERR_S) -#define EFUSE_ECDSA_P384_ENABLE_ERR_V 0x00000001U -#define EFUSE_ECDSA_P384_ENABLE_ERR_S 4 +#define EFUSE_SECURE_BOOT_SHA384_EN_ERR (BIT(4)) +#define EFUSE_SECURE_BOOT_SHA384_EN_ERR_M (EFUSE_SECURE_BOOT_SHA384_EN_ERR_V << EFUSE_SECURE_BOOT_SHA384_EN_ERR_S) +#define EFUSE_SECURE_BOOT_SHA384_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_SHA384_EN_ERR_S 4 /** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [5]; default: 0; * Represents the programming error of EFUSE_SECURE_BOOT_EN */ diff --git a/components/soc/esp32h4/register/soc/efuse_struct.h b/components/soc/esp32h4/register/soc/efuse_struct.h index 2fc43b043c..4c420bef16 100644 --- a/components/soc/esp32h4/register/soc/efuse_struct.h +++ b/components/soc/esp32h4/register/soc/efuse_struct.h @@ -229,10 +229,10 @@ typedef union { * 0: Disable. */ uint32_t ecc_force_const_time:1; - /** ecdsa_p384_enable : RO; bitpos: [4]; default: 0; - * Represents if the chip supports ECDSA P384 + /** secure_boot_sha384_en : RO; bitpos: [4]; default: 0; + * Represents if the chip supports Secure Boot using SHA-384 */ - uint32_t ecdsa_p384_enable:1; + uint32_t secure_boot_sha384_en:1; /** secure_boot_en : RO; bitpos: [5]; default: 0; * Represents whether secure boot is enabled or disabled. * 1: enabled @@ -873,10 +873,10 @@ typedef union { * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME */ uint32_t ecc_force_const_time_err:1; - /** ecdsa_p384_enable_err : RO; bitpos: [4]; default: 0; - * Represents the programming error of EFUSE_ECDSA_P384_ENABLE + /** secure_boot_sha384_en_err : RO; bitpos: [4]; default: 0; + * Represents the programming error of EFUSE_secure_boot_sha384_en */ - uint32_t ecdsa_p384_enable_err:1; + uint32_t secure_boot_sha384_en_err:1; /** secure_boot_en_err : RO; bitpos: [5]; default: 0; * Represents the programming error of EFUSE_SECURE_BOOT_EN */