diff --git a/components/bootloader_support/src/bootloader_common_loader.c b/components/bootloader_support/src/bootloader_common_loader.c
index ecc96cafca..1ca7b4c069 100644
--- a/components/bootloader_support/src/bootloader_common_loader.c
+++ b/components/bootloader_support/src/bootloader_common_loader.c
@@ -263,7 +263,11 @@ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void)
 #ifdef BOOTLOADER_BUILD
 
 #if ESP_ROM_HAS_LP_ROM
+#if CONFIG_IDF_TARGET_ESP32P4
+    #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_LOW + CONFIG_P4_REV3_MSPI_WORKAROUND_SIZE)
+#else
     #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_LOW)
+#endif
 #else
     /* Since the structure containing the retain_mem_t is aligned on 8 by the linker, make sure we align this
      * structure size here too */
diff --git a/components/esp_hal_mspi/esp32p4/include/hal/mspi_ll.h b/components/esp_hal_mspi/esp32p4/include/hal/mspi_ll.h
index 5978b568e4..4c0069fd9f 100644
--- a/components/esp_hal_mspi/esp32p4/include/hal/mspi_ll.h
+++ b/components/esp_hal_mspi/esp32p4/include/hal/mspi_ll.h
@@ -139,6 +139,20 @@ static inline void _mspi_timing_ll_reset_mspi(void)
         _mspi_timing_ll_reset_mspi(__VA_ARGS__); \
     } while(0)
 
+__attribute__((always_inline))
+static inline void _mspi_timing_ll_reset_mspi_apb(void)
+{
+    REG_SET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_APB);
+    REG_CLR_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_APB);
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define mspi_timing_ll_reset_mspi_apb(...) do { \
+        (void)__DECLARE_RCC_RC_ATOMIC_ENV; \
+        _mspi_timing_ll_reset_mspi_apb(__VA_ARGS__); \
+    } while(0)
+
 /*---------------------------------------------------------------
                     PSRAM tuning
 ---------------------------------------------------------------*/
diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt
index 9399a8c92c..f5aeb8c878 100644
--- a/components/esp_hw_support/CMakeLists.txt
+++ b/components/esp_hw_support/CMakeLists.txt
@@ -64,6 +64,7 @@ if(NOT non_os_build)
         list(APPEND srcs "sleep_modem.c"
                          "sleep_modes.c"
                          "sleep_console.c"
+                         "sleep_mspi.c"
                          "sleep_usb.c"
                          "sleep_gpio.c"
                          "sleep_event.c"
diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig
index a1e06c95db..010d5e422b 100644
--- a/components/esp_hw_support/Kconfig
+++ b/components/esp_hw_support/Kconfig
@@ -299,4 +299,5 @@ menu "Hardware Settings"
         bool "Place esp_intr_alloc functions in IRAM" if SPI_FLASH_AUTO_SUSPEND
         default y
 
+    orsource "./lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround"
 endmenu
diff --git a/components/esp_hw_support/include/esp_private/esp_pau.h b/components/esp_hw_support/include/esp_private/esp_pau.h
index ba975b7b8d..f82d0f7dbb 100644
--- a/components/esp_hw_support/include/esp_private/esp_pau.h
+++ b/components/esp_hw_support/include/esp_private/esp_pau.h
@@ -83,8 +83,10 @@ void pau_regdma_trigger_extra_link_restore(void);
  *        link entry configuration in always-on domain
  *
  * @param enable Set true to use always-on domain link configuration instead
+ *
+ * @return The origin aon link bypass enable status
  */
-void pau_regdma_enable_aon_link_entry(bool enable);
+bool pau_regdma_enable_aon_link_entry(bool enable);
 #endif
 
 #ifdef __cplusplus
diff --git a/components/esp_hw_support/include/esp_private/sleep_flash.h b/components/esp_hw_support/include/esp_private/sleep_flash.h
new file mode 100644
index 0000000000..ab8c95e098
--- /dev/null
+++ b/components/esp_hw_support/include/esp_private/sleep_flash.h
@@ -0,0 +1,25 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "soc/soc_caps.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if CONFIG_IDF_TARGET_ESP32P4 && (CONFIG_ESP_REV_MIN_FULL == 300)
+/**
+ * Workaround for esp32p4 v3 MPSI access failure after power up.
+ */
+void sleep_flash_p4_rev3_workaround(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf
index c37057f2c0..6a0de4b82d 100644
--- a/components/esp_hw_support/linker.lf
+++ b/components/esp_hw_support/linker.lf
@@ -40,6 +40,7 @@ entries:
         rtc_sleep:rtc_sleep_pu (noflash)
     if SOC_PMU_SUPPORTED = y && SOC_LIGHT_SLEEP_SUPPORTED = y:
         pmu_sleep (noflash)
+        sleep_mspi (noflash)
         if SPIRAM_FLASH_LOAD_TO_PSRAM = y:
             pmu_init (noflash)
             pmu_param (noflash)
diff --git a/components/esp_hw_support/lowpower/CMakeLists.txt b/components/esp_hw_support/lowpower/CMakeLists.txt
index cc05b16c05..7e110d605c 100644
--- a/components/esp_hw_support/lowpower/CMakeLists.txt
+++ b/components/esp_hw_support/lowpower/CMakeLists.txt
@@ -23,6 +23,12 @@ if(CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP OR
     endif()
 endif()
 
+if(CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND)
+    list(APPEND srcs "port/esp32p4/p4_rev3_mspi_workaround.S")
+    set_property(TARGET ${COMPONENT_LIB}
+                APPEND PROPERTY INTERFACE_LINK_LIBRARIES "-u p4_rev3_mspi_workaround")
+endif()
+
 if(CONFIG_SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD AND CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
     list(APPEND srcs "port/${target}/sleep_mmu.c")
 endif()
diff --git a/components/esp_hw_support/lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround b/components/esp_hw_support/lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround
new file mode 100644
index 0000000000..5810818f79
--- /dev/null
+++ b/components/esp_hw_support/lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround
@@ -0,0 +1,10 @@
+config P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
+    bool
+    depends on IDF_TARGET_ESP32P4
+    default y if ESP32P4_REV_MIN_300
+
+config P4_REV3_MSPI_WORKAROUND_SIZE
+    hex
+    depends on IDF_TARGET_ESP32P4
+    default 0x100 if ESP32P4_REV_MIN_300
+    default 0
diff --git a/components/esp_hw_support/lowpower/port/esp32p4/p4_rev3_mspi_workaround.S b/components/esp_hw_support/lowpower/port/esp32p4/p4_rev3_mspi_workaround.S
new file mode 100644
index 0000000000..64a105929d
--- /dev/null
+++ b/components/esp_hw_support/lowpower/port/esp32p4/p4_rev3_mspi_workaround.S
@@ -0,0 +1,110 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/reg_base.h"
+
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_REG     (DR_REG_HP_SYS_BASE + 0x1a4)
+
+/* Clock related */
+#define DR_REG_LP_CLKRST_BASE               (DR_REG_LPAON_BASE + 0x1000)
+#define LP_CLKRST_HPCPU_RESET_CTRL0_REG     (DR_REG_LP_CLKRST_BASE + 0x14)
+#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL   (1 << 15)
+
+#define HP_SYS_CLKRST_HP_RST_EN0_REG        (DR_REG_HP_SYS_CLKRST_BASE + 0xc0)
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI    (1 << 22)
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_APB    (1 << 24)
+
+
+/* SPIMEM related */
+#define DR_REG_FLASH_SPI0_BASE              (DR_REG_HPPERIPH0_BASE + 0x8C000)
+#define SPI_MEM_C_CACHE_FCTRL_REG           (DR_REG_FLASH_SPI0_BASE + 0x3c)
+#define SPI_MEM_C_CLOSE_AXI_INF_EN          (1 << 31)
+#define SPI_MEM_C_AXI_REQ_EN                (1 << 0)
+
+#define SPI_MEM_C_MMU_ITEM_INDEX_REG        (DR_REG_FLASH_SPI0_BASE + 0x380)
+#define SPI_MEM_C_MMU_ITEM_CONTENT_REG      (DR_REG_FLASH_SPI0_BASE + 0x37c)
+
+.macro REG_SET_BIT addr, value
+    li a0, \addr
+    li a1, \value
+    lw a2, (a0)
+    or a2, a2, a1
+    sw a2, (a0)
+.endm
+
+.macro REG_CLR_BIT addr, value
+    li a0, \addr
+    /* Since all our parameters will be constants, we can pre-calculate it at assemble time */
+    li a1, ~\value
+    lw a2, (a0)
+    and a2, a2, a1
+    sw a2, (a0)
+.endm
+
+.macro REG_WRITE addr, value
+    li a0, \addr
+    li a1, \value
+    sw a1, (a0)
+.endm
+
+.macro REG_READ addr
+    li  a0, \addr
+    lw  a1, (a0)
+.endm
+
+.macro DELAY_US us
+    li      t3, (40 * \us)     /* CPU @40MHz after reset */
+    csrr    t0, cycle
+    add     t1, t0, t3
+1:  csrr    t2, cycle
+    blt     t2, t1, 1b
+.endm
+
+/**
+ * @brief Workaround for MSPI issues on ESP32-P4 revision 3
+ *
+ * This function implements a workaround for MSPI-related issues on ESP32-P4 revision 3.
+ * It performs 2 flash dummy reads to stabilize the MSPI functionality before jumping to
+ * ROM code after deepsleep wakeup.
+ */
+.global p4_rev3_mspi_workaround
+.section .p4_rev3_mspi_workaround.rtc_text,"ax"
+
+p4_rev3_mspi_workaround:
+    # Recover the reset vector to HP ROM
+    REG_SET_BIT LP_CLKRST_HPCPU_RESET_CTRL0_REG, LP_CLKRST_HPCORE0_STAT_VECTOR_SEL
+
+    # Clear the bit to close AXI interface and then set the AXI request enable bit
+    REG_CLR_BIT SPI_MEM_C_CACHE_FCTRL_REG, SPI_MEM_C_CLOSE_AXI_INF_EN
+    REG_SET_BIT SPI_MEM_C_CACHE_FCTRL_REG, SPI_MEM_C_AXI_REQ_EN
+
+    # Set 1 mspi mmu entry for axi addr to flash addr
+    REG_WRITE SPI_MEM_C_MMU_ITEM_INDEX_REG, 0
+    REG_WRITE SPI_MEM_C_MMU_ITEM_CONTENT_REG, 0x1000
+
+    # Disable cpu get error response
+    REG_WRITE HP_SYSTEM_CORE_ERR_RESP_DIS_REG, 0x7
+
+    # Perform dummy reads
+    REG_READ 0x80000000
+    # Perform dummy reads again
+    REG_READ 0x80000080
+
+    # Delay 1us to wait MSPI read transmission done
+    DELAY_US 1
+
+    # Enable cpu get error response
+    REG_WRITE HP_SYSTEM_CORE_ERR_RESP_DIS_REG, 0
+
+    # Reset MSPI AXI and APB interfaces
+    REG_SET_BIT HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI
+    REG_SET_BIT HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_APB
+    REG_CLR_BIT HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI
+    REG_CLR_BIT HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_APB
+
+    # Jump to HP ROM first stage boot code
+    li  a5, 0x4fc00000
+    jr  a5
diff --git a/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c b/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c
index 7cb3d1f40e..02ea0f6c5f 100644
--- a/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c
+++ b/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c
@@ -276,7 +276,11 @@ static TCM_IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
         }
 #endif
 
-        return (*goto_sleep)(wakeup_opt, reject_opt, lslp_mem_inf_fpu, dslp);
+        uint32_t reject =  (*goto_sleep)(wakeup_opt, reject_opt, lslp_mem_inf_fpu, dslp);
+        if (reject) {
+            restore_mstatus(mstatus);
+            return reject;
+        }
     }
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
     else {
diff --git a/components/esp_hw_support/port/esp32p4/pmu_init.c b/components/esp_hw_support/port/esp32p4/pmu_init.c
index 64aa1880fa..2910f22dd3 100644
--- a/components/esp_hw_support/port/esp32p4/pmu_init.c
+++ b/components/esp_hw_support/port/esp32p4/pmu_init.c
@@ -14,9 +14,11 @@
 #include "soc/pmu_struct.h"
 #include "hal/efuse_hal.h"
 #include "hal/pmu_hal.h"
+#include "hal/lp_sys_ll.h"
 #include "pmu_param.h"
 #include "esp_private/esp_pmu.h"
 #include "soc/regi2c_dig_reg.h"
+#include "soc/lp_system_reg.h"
 #include "regi2c_ctrl.h"
 #include "esp_rom_sys.h"
 #include "soc/rtc.h"
@@ -175,6 +177,9 @@ static void pmu_hp_system_init_default(pmu_context_t *ctx)
         pmu_hp_system_param_default(mode, &param);
         pmu_hp_system_init(ctx, mode, &param);
     }
+#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
+    lp_sys_ll_set_hp_mem_lowpower_mode(MEM_AUX_DEEPSLEEP);
+#endif
 }
 
 static inline void pmu_lp_system_param_default(pmu_lp_mode_t mode, pmu_lp_system_param_t *param)
@@ -191,6 +196,9 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx)
         pmu_lp_system_param_default(mode, &param);
         pmu_lp_system_init(ctx, mode, &param);
     }
+#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
+    lp_sys_ll_set_lp_mem_lowpower_mode(MEM_AUX_DEEPSLEEP);
+#endif
 }
 
 void pmu_init(void)
diff --git a/components/esp_hw_support/port/esp32p4/pmu_sleep.c b/components/esp_hw_support/port/esp32p4/pmu_sleep.c
index 0064785ae6..7f2a2c012b 100644
--- a/components/esp_hw_support/port/esp32p4/pmu_sleep.c
+++ b/components/esp_hw_support/port/esp32p4/pmu_sleep.c
@@ -30,6 +30,7 @@
 #include "hal/pmu_hal.h"
 #include "hal/psram_ctrlr_ll.h"
 #include "hal/lp_sys_ll.h"
+#include "hal/lp_clkrst_ll.h"
 #include "esp_private/esp_pmu.h"
 #include "pmu_param.h"
 #include "esp_rom_sys.h"
@@ -39,6 +40,12 @@
 #include "hal/ldo_ll.h"
 #endif
 
+#if (CONFIG_ESP_REV_MIN_FULL == 300)
+#include "soc/hp_system_reg.h"
+#include "hal/mmu_ll.h"
+#include "hal/mspi_ll.h"
+#endif
+
 #define HP(state)   (PMU_MODE_HP_ ## state)
 #define LP(state)   (PMU_MODE_LP_ ## state)
 
@@ -205,7 +212,6 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         }
         power_default.hp_sys.dig_power.dcdc_switch_pd_en = 0;
         analog_default.hp_sys.analog.dcm_vset = CONFIG_ESP_SLEEP_DCM_VSET_VAL_IN_SLEEP;
-        analog_default.hp_sys.analog.xpd = 0;
         if (sleep_flags & PMU_SLEEP_PD_VDDSDIO) {
             analog_default.hp_sys.analog.xpd_0p1a = 0;
         } else {
@@ -415,6 +421,10 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
 #endif
             rtc_clk_mpll_disable();
         }
+    } else {
+#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
+        lp_clkrst_ll_boot_from_lp_ram(true);
+#endif
     }
 
 
@@ -438,12 +448,16 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
         ;
     }
 
-#if CONFIG_SPIRAM && CONFIG_ESP_LDO_RESERVE_PSRAM
-    // Enable PSRAM chip power supply after deepsleep request rejected
     if (dslp) {
+#if CONFIG_SPIRAM && CONFIG_ESP_LDO_RESERVE_PSRAM
+        // Enable PSRAM chip power supply after deepsleep request rejected
         ldo_ll_enable(LDO_ID2UNIT(CONFIG_ESP_LDO_CHAN_PSRAM_DOMAIN), true);
-    }
 #endif
+#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
+        // Set reset vector back to HP ROM after deepsleep request rejected
+        lp_clkrst_ll_boot_from_lp_ram(false);
+#endif
+    }
 
     return pmu_sleep_finish(dslp);
 }
diff --git a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
index ca28b67104..41dc4c4887 100644
--- a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
+++ b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
@@ -35,7 +35,7 @@ extern "C" {
 // FOR LIGHTSLEEP
 #define PMU_HP_DRVB_LIGHTSLEEP      0
 #define PMU_LP_DRVB_LIGHTSLEEP      0
-#define PMU_HP_XPD_LIGHTSLEEP       1
+#define PMU_HP_XPD_LIGHTSLEEP       0 // Always use DCDC power supply in lightsleep
 
 #define PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT    0
 #define PMU_HP_DBIAS_LIGHTSLEEP_0V6 1
diff --git a/components/esp_hw_support/port/pau_regdma.c b/components/esp_hw_support/port/pau_regdma.c
index a66d78b10b..03281ce7b7 100644
--- a/components/esp_hw_support/port/pau_regdma.c
+++ b/components/esp_hw_support/port/pau_regdma.c
@@ -137,8 +137,10 @@ void IRAM_ATTR pau_regdma_trigger_extra_link_restore(void)
 }
 
 #if SOC_PAU_IN_TOP_DOMAIN
-void pau_regdma_enable_aon_link_entry(bool enable)
+bool IRAM_ATTR pau_regdma_enable_aon_link_entry(bool enable)
 {
+    bool origin_bypass_en = lp_sys_ll_get_pau_aon_bypass();
     lp_sys_ll_set_pau_aon_bypass(enable);
+    return origin_bypass_en;
 }
 #endif
diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index e4a36e8b57..2cae1213ba 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -23,6 +23,7 @@
 #include "soc/rtc.h"
 #include "esp_private/sleep_event.h"
 #include "esp_private/system_internal.h"
+#include "esp_private/sleep_retention.h"
 #include "esp_private/io_mux.h"
 #include "esp_private/critical_section.h"
 #include "esp_log.h"
@@ -78,6 +79,7 @@
 #include "esp_private/sleep_console.h"
 #include "esp_private/sleep_cpu.h"
 #include "esp_private/sleep_modem.h"
+#include "esp_private/sleep_flash.h"
 #include "esp_private/sleep_usb.h"
 #include "esp_private/esp_clk.h"
 #include "esp_private/esp_task_wdt.h"
@@ -959,9 +961,14 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint
         }
 #endif
 
-#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
         if (sleep_flags & PMU_SLEEP_PD_TOP) {
+#if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
             esp_sleep_mmu_retention(true);
+#endif
+#if CONFIG_IDF_TARGET_ESP32P4 && (CONFIG_ESP_REV_MIN_FULL == 300)
+            sleep_retention_do_extra_retention(true);
+#endif
         }
 #endif
 
@@ -984,9 +991,15 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint
         result = call_rtc_sleep_start(reject_triggers, config->lslp_mem_inf_fpu, deep_sleep);
 #endif
 
-#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
         if (sleep_flags & PMU_SLEEP_PD_TOP) {
+#if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
             esp_sleep_mmu_retention(false);
+#endif
+#if CONFIG_IDF_TARGET_ESP32P4 && (CONFIG_ESP_REV_MIN_FULL == 300)
+            sleep_flash_p4_rev3_workaround();
+            sleep_retention_do_extra_retention(false);
+#endif
         }
 #endif
 
diff --git a/components/esp_hw_support/sleep_mspi.c b/components/esp_hw_support/sleep_mspi.c
new file mode 100644
index 0000000000..9f19826286
--- /dev/null
+++ b/components/esp_hw_support/sleep_mspi.c
@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "sdkconfig.h"
+
+#if CONFIG_IDF_TARGET_ESP32P4 && (CONFIG_ESP_REV_MIN_FULL == 300)
+#include "soc/hp_system_reg.h"
+#include "hal/mmu_ll.h"
+#include "hal/mspi_ll.h"
+
+void sleep_flash_p4_rev3_workaround(void)
+{
+    REG_CLR_BIT(SPI_MEM_C_CACHE_FCTRL_REG, SPI_MEM_C_CLOSE_AXI_INF_EN);
+    REG_SET_BIT(SPI_MEM_C_CACHE_FCTRL_REG, SPI_MEM_C_AXI_REQ_EN);
+    REG_SET_FIELD(HP_SYSTEM_CORE_ERR_RESP_DIS_REG, HP_SYSTEM_CORE_ERR_RESP_DIS, 0x7);
+    REG_WRITE(SPI_MEM_C_MMU_ITEM_INDEX_REG, 0);
+    uint32_t mmu_backup = mmu_ll_read_entry(MMU_LL_FLASH_MMU_ID, 0);
+    mmu_ll_write_entry(MMU_LL_FLASH_MMU_ID, 0, 0, MMU_TARGET_FLASH0);
+    __attribute__((unused)) volatile uint32_t val = 0;
+    val = REG_READ(0x80000000);
+    val = REG_READ(0x80000080);
+    mmu_ll_write_entry(MMU_LL_FLASH_MMU_ID, 0, mmu_backup, MMU_TARGET_FLASH0);
+    _mspi_timing_ll_reset_mspi();
+    _mspi_timing_ll_reset_mspi_apb();
+    REG_SET_FIELD(HP_SYSTEM_CORE_ERR_RESP_DIS_REG, HP_SYSTEM_CORE_ERR_RESP_DIS, 0);
+}
+#endif
diff --git a/components/esp_hw_support/sleep_retention.c b/components/esp_hw_support/sleep_retention.c
index 724ce38bbc..01fbdb2c77 100644
--- a/components/esp_hw_support/sleep_retention.c
+++ b/components/esp_hw_support/sleep_retention.c
@@ -968,7 +968,7 @@ void IRAM_ATTR sleep_retention_do_extra_retention(bool backup_or_restore)
         return;
     }
 #if SOC_PAU_IN_TOP_DOMAIN
-    pau_regdma_enable_aon_link_entry(false);
+    bool origin_bypass_en = pau_regdma_enable_aon_link_entry(false);
 #endif
     // Set extra linked list head pointer to hardware
     pau_regdma_set_extra_link_addr(s_retention.lists[s_retention.highpri].entries[EXTRA_LINK_NUM]);
@@ -982,6 +982,9 @@ void IRAM_ATTR sleep_retention_do_extra_retention(bool backup_or_restore)
     } else {
         pau_regdma_trigger_extra_link_restore();
     }
+#if SOC_PAU_IN_TOP_DOMAIN
+    pau_regdma_enable_aon_link_entry(origin_bypass_en);
+#endif
 }
 
 #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
diff --git a/components/esp_pm/Kconfig b/components/esp_pm/Kconfig
index fca3fae5b6..71573bbb14 100644
--- a/components/esp_pm/Kconfig
+++ b/components/esp_pm/Kconfig
@@ -178,7 +178,9 @@ menu "Power Management"
     config PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
         bool "Power down Digital Peripheral in light sleep (EXPERIMENTAL)"
         depends on SOC_PM_SUPPORT_TOP_PD && SOC_PAU_SUPPORTED
+        depends on !(IDF_TARGET_ESP32P4 && (ESP_REV_MIN_FULL = 300) && SPIRAM)
         select PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP if !ESP32P4_SELECTS_REV_LESS_V3
+        select ESP_SLEEP_POWER_DOWN_FLASH if (IDF_TARGET_ESP32P4 && (ESP_REV_MIN_FULL = 300))
         default n #TODO: enable by default if periph init/deinit management supported (WIFI-5252)
         help
             If enabled, digital peripherals will try to powered down in light sleep, then all related peripherals will
diff --git a/components/esp_system/ld/esp32p4/memory.ld.in b/components/esp_system/ld/esp32p4/memory.ld.in
index b5e42cfad1..107b00d98b 100644
--- a/components/esp_system/ld/esp32p4/memory.ld.in
+++ b/components/esp_system/ld/esp32p4/memory.ld.in
@@ -32,6 +32,12 @@
 #define SRAM_HIGH_END      SRAM_HIGH_START + SRAM_HIGH_SIZE
 #endif
 
+#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
+#define MSPI_WORKAROUND_SIZE   CONFIG_P4_REV3_MSPI_WORKAROUND_SIZE
+#else
+#define MSPI_WORKAROUND_SIZE   0x0
+#endif
+
 #define IDROM_SEG_SIZE   (CONFIG_MMU_PAGE_SIZE << 10)
 
 #define LP_ROM_DRAM_START 0x5010fa80 // Value taken from ROM elf, includes LP ROM stack
@@ -90,14 +96,17 @@ MEMORY
   /* (See irom_seg for meaning of 0x20 offset in the above.) */
 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 
+  /* Used to store the deep sleep workaround code of P4 rev3.0. The reset vector will be set here before the chip enters sleep. */
+  rev3_mspi_workaround_seg(RWX) :        org = 0x50108000, len = MSPI_WORKAROUND_SIZE
+
   /**
    * lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667
    */
 #if CONFIG_ULP_COPROC_ENABLED
-  lp_ram_seg(RW)  :                 org = 0x50108000 + RESERVE_RTC_MEM + CONFIG_ULP_COPROC_RESERVE_MEM,
+  lp_ram_seg(RW)  :                 org = 0x50108000 + MSPI_WORKAROUND_SIZE + RESERVE_RTC_MEM + CONFIG_ULP_COPROC_RESERVE_MEM,
                                     len = 0x8000 - CONFIG_ULP_COPROC_RESERVE_MEM - RESERVE_RTC_MEM - LP_ROM_DRAM_SIZE
 #else
-  lp_ram_seg(RW)  :                 org = 0x50108000 + RESERVE_RTC_MEM, len = 0x8000 - RESERVE_RTC_MEM
+  lp_ram_seg(RW)  :                 org = 0x50108000 + MSPI_WORKAROUND_SIZE + RESERVE_RTC_MEM, len = 0x8000 - RESERVE_RTC_MEM - MSPI_WORKAROUND_SIZE
 #endif // CONFIG_ULP_COPROC_ENABLED
 
   /* We reduced the size of lp_ram_seg by RESERVE_RTC_MEM value.
@@ -108,7 +117,7 @@ MEMORY
      The aim of this is to keep data that will not be moved around and have a fixed address.
      This segment is placed at the beginning of LP RAM, as the end of LP RAM is occupied by LP ROM stack/data
   */
-  lp_reserved_seg(RW) :        org = 0x50108000, len = RESERVE_RTC_MEM
+  lp_reserved_seg(RW) :        org = 0x50108000 + MSPI_WORKAROUND_SIZE, len = RESERVE_RTC_MEM
 
   /* PSRAM seg */
   extern_ram_seg(RWX) :        org = 0x48000000, len = IDROM_SEG_SIZE
diff --git a/components/esp_system/ld/esp32p4/sections.rev3.ld.in b/components/esp_system/ld/esp32p4/sections.rev3.ld.in
index cc4c34afb2..e370942abf 100644
--- a/components/esp_system/ld/esp32p4/sections.rev3.ld.in
+++ b/components/esp_system/ld/esp32p4/sections.rev3.ld.in
@@ -115,6 +115,15 @@ SECTIONS
     ALIGNED_SYMBOL(4, _rtc_force_slow_end)
   } > lp_ram_seg
 
+#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
+  .rtc.p4_rev3_mspi_workaround :
+  {
+    ALIGNED_SYMBOL(4, _rtc_p4_rev3_mspi_workaround_start)
+    KEEP (*(.p4_rev3_mspi_workaround.rtc_text .p4_rev3_mspi_workaround.rtc_text.*))
+    ALIGNED_SYMBOL(4, _rtc_p4_rev3_mspi_workaround_end)
+  } > rev3_mspi_workaround_seg
+#endif
+
   /**
    * This section holds RTC data that should have fixed addresses.
    * The data are not initialized at power-up and are retained during deep
diff --git a/components/hal/esp32p4/include/hal/lp_clkrst_ll.h b/components/hal/esp32p4/include/hal/lp_clkrst_ll.h
new file mode 100644
index 0000000000..68f4b424f2
--- /dev/null
+++ b/components/hal/esp32p4/include/hal/lp_clkrst_ll.h
@@ -0,0 +1,35 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for ESP32-P4 LP_CLKRST register operations
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdlib.h>
+#include "soc/soc.h"
+#include "soc/lp_clkrst_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * Select CPU reset vector
+ * @param boot_from_lp_ram
+ *        true:     boot from LP TCM RAM:   0x50108000
+ *        false:    boot from HP TCM ROM:   0x4FC00000
+ */
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_boot_from_lp_ram(bool boot_from_lp_ram)
+{
+    LP_AON_CLKRST.hpcpu_reset_ctrl0.hpcore0_stat_vector_sel = !boot_from_lp_ram;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32p4/include/hal/lp_sys_ll.h b/components/hal/esp32p4/include/hal/lp_sys_ll.h
index e28a69a678..366edbd4d5 100644
--- a/components/hal/esp32p4/include/hal/lp_sys_ll.h
+++ b/components/hal/esp32p4/include/hal/lp_sys_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,6 +13,7 @@
 #include "soc/soc.h"
 #include "soc/lp_system_struct.h"
 #include "hal/misc.h"
+#include "hal/config.h"
 #include "esp32p4/rom/rtc.h"
 
 
@@ -20,6 +21,10 @@
 extern "C" {
 #endif
 
+#define MEM_AUX_SHUTDOWN         BIT(0)
+#define MEM_AUX_LIGHTSLEEP       BIT(1)
+#define MEM_AUX_DEEPSLEEP        BIT(2)
+
 /**
  * @brief ROM obtains the wake-up type through LP_SYS_STORE9_REG[0].
  *         Set the flag to inform
@@ -40,6 +45,11 @@ FORCE_INLINE_ATTR void lp_sys_ll_set_pau_aon_bypass(bool bypass)
     LP_SYS.backup_dma_cfg1.aon_bypass = bypass ? 1 : 0;
 }
 
+FORCE_INLINE_ATTR bool lp_sys_ll_get_pau_aon_bypass(void)
+{
+    return LP_SYS.backup_dma_cfg1.aon_bypass;
+}
+
 FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_tout_thres(uint32_t tout)
 {
     LP_SYS.backup_dma_cfg0.link_tout_thres_aon = tout;
@@ -60,6 +70,17 @@ FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_addr(uint32_t addr)
     LP_SYS.backup_dma_cfg2.link_addr_aon = addr;
 }
 
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+FORCE_INLINE_ATTR void lp_sys_ll_set_hp_mem_lowpower_mode(uint32_t mode)
+{
+    LP_SYS.hp_mem_aux_ctrl.hp_mem_lowpower_mode = mode;
+}
+
+FORCE_INLINE_ATTR void lp_sys_ll_set_lp_mem_lowpower_mode(uint32_t mode)
+{
+    LP_SYS.lp_mem_aux_ctrl.lp_mem_lowpower_mode = mode;
+}
+#endif
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/heap/port/esp32p4/memory_layout.c b/components/heap/port/esp32p4/memory_layout.c
index a495363432..d26238bc97 100644
--- a/components/heap/port/esp32p4/memory_layout.c
+++ b/components/heap/port/esp32p4/memory_layout.c
@@ -121,6 +121,9 @@ const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_m
 extern int _data_start_low, _data_start_high, _heap_start_low, _heap_start_high, _iram_start, _iram_end, _rtc_force_slow_end;
 #else
 extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
+#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
+extern int _rtc_p4_rev3_mspi_workaround_start, _rtc_p4_rev3_mspi_workaround_end;
+#endif
 #endif
 extern int _tcm_text_start, _tcm_data_end;
 extern int _rtc_reserved_start, _rtc_reserved_end;
@@ -154,5 +157,7 @@ SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_LOW, SOC_EXTRAM_HIGH, extram_region);
 SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data);
 /* This includes any memory reserved for ULP RAM */
 SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_end, (intptr_t)&_rtc_force_slow_end, rtcram_data);
-
+#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
+SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_p4_rev3_mspi_workaround_start, (intptr_t)&_rtc_p4_rev3_mspi_workaround_end, p4_rev3_mspi_workaround);
+#endif
 #endif
diff --git a/components/soc/esp32p4/include/soc/system_periph_retention.h b/components/soc/esp32p4/include/soc/system_periph_retention.h
index 590c7ed3aa..805c5a8de5 100644
--- a/components/soc/esp32p4/include/soc/system_periph_retention.h
+++ b/components/soc/esp32p4/include/soc/system_periph_retention.h
@@ -32,7 +32,7 @@ extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTIO
  * This is an internal function of the sleep retention driver, and is not
  * useful for external use.
  */
-#define CACHE_RETENTION_LINK_LEN 10
+#define CACHE_RETENTION_LINK_LEN 12
 extern const regdma_entries_config_t cache_regs_retention[CACHE_RETENTION_LINK_LEN];
 
 /**
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_system_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_system_reg.h
index 3719697ee9..c137a56775 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/lp_system_reg.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_system_reg.h
@@ -1083,7 +1083,15 @@ extern "C" {
  *  need_des
  */
 #define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x180)
-/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+/** LP_SYSTEM_REG_HP_MEM_LOWPOWER_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_MEM_LOWPOWER_MODE    0x7U
+#define LP_SYSTEM_REG_HP_MEM_LOWPOWER_MODE_M  (LP_SYSTEM_REG_HP_MEM_LOWPOWER_MODE_V << LP_SYSTEM_REG_HP_MEM_LOWPOWER_MODE_S)
+#define LP_SYSTEM_REG_HP_MEM_LOWPOWER_MODE_V  0x7U
+#define LP_SYSTEM_REG_HP_MEM_LOWPOWER_MODE_S  0
+
+/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL : R/W; bitpos: [31:3]; default: 1038;
  *  need_des
  */
 #define LP_SYSTEM_REG_HP_MEM_AUX_CTRL    0xFFFFFFFFU
@@ -1095,7 +1103,14 @@ extern "C" {
  *  need_des
  */
 #define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x184)
-/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+/** LP_SYSTEM_REG_LP_MEM_LOWPOWER_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_MEM_LOWPOWER_MODE    0x7U
+#define LP_SYSTEM_REG_LP_MEM_LOWPOWER_MODE_M  (LP_SYSTEM_REG_LP_MEM_LOWPOWER_MODE_V << LP_SYSTEM_REG_LP_MEM_LOWPOWER_MODE_S)
+#define LP_SYSTEM_REG_LP_MEM_LOWPOWER_MODE_V  0x7U
+#define LP_SYSTEM_REG_LP_MEM_LOWPOWER_MODE_S  0
+/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL : R/W; bitpos: [31:3]; default: 1038;
  *  need_des
  */
 #define LP_SYSTEM_REG_LP_MEM_AUX_CTRL    0xFFFFFFFFU
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_system_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_system_struct.h
index 1b63f5af86..5d674d89d4 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/lp_system_struct.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_system_struct.h
@@ -768,10 +768,14 @@ typedef union {
  */
 typedef union {
     struct {
-        /** hp_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
+        /** hp_mem_lowpower_mode : R/W; bitpos: [2:0]; default: 0;
          *  need_des
          */
-        uint32_t hp_mem_aux_ctrl:32;
+        uint32_t hp_mem_lowpower_mode:3;
+        /** hp_mem_aux_ctrl : R/W; bitpos: [31:3]; default: 1038;
+         *  need_des
+         */
+        uint32_t hp_mem_aux_ctrl:29;
     };
     uint32_t val;
 } lp_system_reg_hp_mem_aux_ctrl_reg_t;
@@ -781,10 +785,14 @@ typedef union {
  */
 typedef union {
     struct {
-        /** lp_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
+        /** lp_mem_lowpower_mode : R/W; bitpos: [2:0]; default: 0;
          *  need_des
          */
-        uint32_t lp_mem_aux_ctrl:32;
+        uint32_t lp_mem_lowpower_mode:3;
+        /** lp_mem_aux_ctrl : R/W; bitpos: [31:3]; default: 1038;
+         *  need_des
+         */
+        uint32_t lp_mem_aux_ctrl:29;
     };
     uint32_t val;
 } lp_system_reg_lp_mem_aux_ctrl_reg_t;
diff --git a/components/soc/esp32p4/system_retention_periph.c b/components/soc/esp32p4/system_retention_periph.c
index 01f300e737..0bcff04f94 100644
--- a/components/soc/esp32p4/system_retention_periph.c
+++ b/components/soc/esp32p4/system_retention_periph.c
@@ -45,17 +45,23 @@ static const uint32_t l1_cache_regs_map[4] = {0x7, 0x0, 0xc000000, 0x0};
     CACHE_L2_CACHE_ACS_FAIL_CTRL_REG & CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG */
 #define L2_CACHE_RETENTION_REGS_CNT     (6)
 #define L2_CACHE_RETENTION_REGS_BASE    (CACHE_L2_CACHE_CTRL_REG)
+#define L1_CACHE_ACS_FAIL_INR_CLR       (CACHE_L1_ICACHE0_FAIL_INT_CLR | CACHE_L1_ICACHE1_FAIL_INT_CLR | CACHE_L1_ICACHE2_FAIL_INT_CLR | CACHE_L1_ICACHE3_FAIL_INT_CLR |CACHE_L1_DCACHE_FAIL_INT_CLR)
+#define L1_CACHE_ACS_FAIL_INR_CLR_M     (CACHE_L1_ICACHE0_FAIL_INT_CLR_M | CACHE_L1_ICACHE1_FAIL_INT_CLR_M | CACHE_L1_ICACHE2_FAIL_INT_CLR_M | CACHE_L1_ICACHE3_FAIL_INT_CLR_M |CACHE_L1_DCACHE_FAIL_INT_CLR_M)
+
 static const uint32_t l2_cache_regs_map[4] = {0xc000000f, 0x0, 0x0, 0x0};
 const regdma_entries_config_t cache_regs_retention[] = {
-    [0] = {
-        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x00), L1_CACHE_RETENTION_REGS_BASE, L1_CACHE_RETENTION_REGS_BASE, \
+    // Clear the cache error status, since the auto clock gating added to the cache after version v3, it may falsely report cache acs fail when the module is reset.
+    [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x00), CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG,  L1_CACHE_ACS_FAIL_INR_CLR,      L1_CACHE_ACS_FAIL_INR_CLR_M,    1, 0), .owner = ENTRY(0) },
+    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x01), CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG,  CACHE_L2_CACHE_FAIL_INT_CLR,    CACHE_L2_CACHE_FAIL_INT_CLR_M,  1, 0), .owner = ENTRY(0) },
+    [2] = {
+        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x02), L1_CACHE_RETENTION_REGS_BASE, L1_CACHE_RETENTION_REGS_BASE, \
                                             L1_CACHE_RETENTION_REGS_CNT, 0, 0,              \
                                             l1_cache_regs_map[0], l1_cache_regs_map[1],     \
                                             l1_cache_regs_map[2], l1_cache_regs_map[3]),    \
         .owner = ENTRY(0)
     },
-    [1] = {
-        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x01),                                    \
+    [3] = {
+        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x03),                                    \
                                             L2_CACHE_RETENTION_REGS_BASE, L2_CACHE_RETENTION_REGS_BASE, \
                                             L2_CACHE_RETENTION_REGS_CNT, 0, 0,                          \
                                             l2_cache_regs_map[0], l2_cache_regs_map[1],                 \
@@ -63,15 +69,15 @@ const regdma_entries_config_t cache_regs_retention[] = {
         .owner = ENTRY(0)
     },
     // Invalidate L1 Cache
-    [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x02), CACHE_SYNC_ADDR_REG, 0,                       CACHE_SYNC_ADDR_M,      1, 0), .owner = ENTRY(0) },
-    [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x03), CACHE_SYNC_SIZE_REG, 0,                       CACHE_SYNC_SIZE_M,      1, 0), .owner = ENTRY(0) },
-    [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x04), CACHE_SYNC_MAP_REG,  CACHE_MAP_L1_CACHE_MASK, CACHE_SYNC_MAP_M,       1, 0), .owner = ENTRY(0) },
-    [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x05), CACHE_SYNC_CTRL_REG, 0,                       CACHE_SYNC_RGID_M,      1, 0), .owner = ENTRY(0) },
-    [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x06), CACHE_SYNC_CTRL_REG, CACHE_INVALIDATE_ENA,    CACHE_INVALIDATE_ENA_M, 1, 0), .owner = ENTRY(0) },
-    [7] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_CACHE_LINK(0x07),  CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE,         CACHE_SYNC_DONE_M,      1, 0), .owner = ENTRY(0) },
+    [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x04), CACHE_SYNC_ADDR_REG, 0,                       CACHE_SYNC_ADDR_M,      1, 0), .owner = ENTRY(0) },
+    [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x05), CACHE_SYNC_SIZE_REG, 0,                       CACHE_SYNC_SIZE_M,      1, 0), .owner = ENTRY(0) },
+    [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x06), CACHE_SYNC_MAP_REG,  CACHE_MAP_L1_CACHE_MASK, CACHE_SYNC_MAP_M,       1, 0), .owner = ENTRY(0) },
+    [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x07), CACHE_SYNC_CTRL_REG, 0,                       CACHE_SYNC_RGID_M,      1, 0), .owner = ENTRY(0) },
+    [8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x08), CACHE_SYNC_CTRL_REG, CACHE_INVALIDATE_ENA,    CACHE_INVALIDATE_ENA_M, 1, 0), .owner = ENTRY(0) },
+    [9] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_CACHE_LINK(0x09),  CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE,         CACHE_SYNC_DONE_M,      1, 0), .owner = ENTRY(0) },
     // Reset L2 CACHE SYNC
-    [8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x08), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, CACHE_L2_CACHE_SYNC_RST,    CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) },
-    [9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x09), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, 0,    CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) },
+    [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x10), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, CACHE_L2_CACHE_SYNC_RST,    CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) },
+    [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x11), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, 0,    CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) },
 
 };
 _Static_assert(ARRAY_SIZE(cache_regs_retention) == CACHE_RETENTION_LINK_LEN, "Inconsistent L2 CACHE retention link length definitions");
@@ -127,19 +133,23 @@ _Static_assert(ARRAY_SIZE(iomux_regs_retention) == IOMUX_RETENTION_LINK_LEN, "In
 #define N_REGS_SPI0_C_MEM_1()     (((SPI_MEM_C_SMEM_AC_REG - SPI_MEM_C_FMEM__PMS0_ATTR_REG) / 4) + 1)
 #define N_REGS_SPI0_C_MEM_2()     (1)
 #define N_REGS_SPI0_C_MEM_3()     (((SPI_MEM_C_DPA_CTRL_REG - SPI_MEM_C_MMU_POWER_CTRL_REG) / 4) + 1)
-
+#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
+#define FLASH_SPIMEM_RETENTION_ENTRY     (ENTRY(0) | REGDMA_SW_TRIGGER_ENTRY)
+#else
+#define FLASH_SPIMEM_RETENTION_ENTRY     ENTRY(0)
+#endif
 const regdma_entries_config_t flash_spimem_regs_retention[] = {
     /* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
-    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), DR_REG_FLASH_SPI1_BASE,            DR_REG_FLASH_SPI1_BASE,      N_REGS_SPI1_C_MEM_0(), 0, 0), .owner = ENTRY(0) }, /* spi1_mem */
-    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI1_MEM_C_INT_ENA_REG,            SPI1_MEM_C_INT_ENA_REG,      N_REGS_SPI1_C_MEM_1(), 0, 0), .owner = ENTRY(0) },
-    [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), SPI1_MEM_C_TIMING_CALI_REG,        SPI1_MEM_C_TIMING_CALI_REG,  N_REGS_SPI1_C_MEM_2(), 0, 0), .owner = ENTRY(0) },
+    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), DR_REG_FLASH_SPI1_BASE,            DR_REG_FLASH_SPI1_BASE,      N_REGS_SPI1_C_MEM_0(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY }, /* spi1_mem */
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI1_MEM_C_INT_ENA_REG,            SPI1_MEM_C_INT_ENA_REG,      N_REGS_SPI1_C_MEM_1(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY },
+    [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), SPI1_MEM_C_TIMING_CALI_REG,        SPI1_MEM_C_TIMING_CALI_REG,  N_REGS_SPI1_C_MEM_2(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY },
 
     /* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
-    [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), DR_REG_FLASH_SPI0_BASE,            DR_REG_FLASH_SPI0_BASE,          N_REGS_SPI0_C_MEM_0(), 0, 0), .owner = ENTRY(0) }, /* spi0_mem */
-    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_C_FMEM__PMS0_ATTR_REG,     SPI_MEM_C_FMEM__PMS0_ATTR_REG,   N_REGS_SPI0_C_MEM_1(), 0, 0), .owner = ENTRY(0) },
-    [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_C_CLOCK_GATE_REG,          SPI_MEM_C_CLOCK_GATE_REG,        N_REGS_SPI0_C_MEM_2(), 0, 0), .owner = ENTRY(0) },
-    [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x07), SPI_MEM_C_MMU_POWER_CTRL_REG,      SPI_MEM_C_MMU_POWER_CTRL_REG,    N_REGS_SPI0_C_MEM_3(), 0, 0), .owner = ENTRY(0) },
-    [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SPIMEM_LINK(0x08), SPI_MEM_C_TIMING_CALI_REG,         SPI_MEM_C_TIMING_CALI_UPDATE,    SPI_MEM_C_TIMING_CALI_UPDATE_M, 1, 0), .owner = ENTRY(0) },
+    [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), DR_REG_FLASH_SPI0_BASE,            DR_REG_FLASH_SPI0_BASE,          N_REGS_SPI0_C_MEM_0(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY }, /* spi0_mem */
+    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_C_FMEM__PMS0_ATTR_REG,     SPI_MEM_C_FMEM__PMS0_ATTR_REG,   N_REGS_SPI0_C_MEM_1(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY },
+    [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_C_CLOCK_GATE_REG,          SPI_MEM_C_CLOCK_GATE_REG,        N_REGS_SPI0_C_MEM_2(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY },
+    [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x07), SPI_MEM_C_MMU_POWER_CTRL_REG,      SPI_MEM_C_MMU_POWER_CTRL_REG,    N_REGS_SPI0_C_MEM_3(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY },
+    [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SPIMEM_LINK(0x08), SPI_MEM_C_TIMING_CALI_REG,         SPI_MEM_C_TIMING_CALI_UPDATE,    SPI_MEM_C_TIMING_CALI_UPDATE_M, 1, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY },
 };
 _Static_assert(ARRAY_SIZE(flash_spimem_regs_retention) == SPIMEM_FLASH_RETENTION_LINK_LEN, "Inconsistent Flash SPI Mem retention link length definitions");
 
diff --git a/examples/system/deep_sleep/main/CMakeLists.txt b/examples/system/deep_sleep/main/CMakeLists.txt
index 73604b48a3..bc399df70f 100644
--- a/examples/system/deep_sleep/main/CMakeLists.txt
+++ b/examples/system/deep_sleep/main/CMakeLists.txt
@@ -4,5 +4,5 @@ set(srcs "deep_sleep_example_main.c"
 set(includes ".")
 
 idf_component_register(SRCS ${srcs}
-                       PRIV_REQUIRES nvs_flash ulp esp_driver_gpio
+                       PRIV_REQUIRES nvs_flash esp_driver_gpio
                        INCLUDE_DIRS ${includes})
diff --git a/examples/system/deep_sleep/sdkconfig.ci.basic b/examples/system/deep_sleep/sdkconfig.ci.basic
index 1e9cf53a7e..ffd95a3d15 100644
--- a/examples/system/deep_sleep/sdkconfig.ci.basic
+++ b/examples/system/deep_sleep/sdkconfig.ci.basic
@@ -2,8 +2,6 @@
 CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y
 CONFIG_EXAMPLE_EXT1_WAKEUP=n
 
-CONFIG_ULP_COPROC_ENABLED=y
-CONFIG_ULP_COPROC_RESERVE_MEM=512
 CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT=y
 CONFIG_RTC_CLK_SRC_INT_RC=y
 CONFIG_PARTITION_TABLE_CUSTOM=y
diff --git a/examples/system/deep_sleep/sdkconfig.ci.esp32_singlecore b/examples/system/deep_sleep/sdkconfig.ci.esp32_singlecore
index bc9053c45f..23f627840f 100644
--- a/examples/system/deep_sleep/sdkconfig.ci.esp32_singlecore
+++ b/examples/system/deep_sleep/sdkconfig.ci.esp32_singlecore
@@ -9,8 +9,6 @@ CONFIG_EXAMPLE_EXT1_WAKEUP=n
 
 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80=y
 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=80
-CONFIG_ULP_COPROC_ENABLED=y
-CONFIG_ULP_COPROC_RESERVE_MEM=512
 CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT=y
 CONFIG_RTC_CLK_SRC_INT_RC=y
 CONFIG_PARTITION_TABLE_CUSTOM=y
diff --git a/examples/system/deep_sleep/sdkconfig.defaults b/examples/system/deep_sleep/sdkconfig.defaults
index 1a61739cba..b3ef018be4 100644
--- a/examples/system/deep_sleep/sdkconfig.defaults
+++ b/examples/system/deep_sleep/sdkconfig.defaults
@@ -1,5 +1,3 @@
-CONFIG_ULP_COPROC_ENABLED=y
-CONFIG_ULP_COPROC_RESERVE_MEM=512
 CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT=y
 CONFIG_RTC_CLK_SRC_INT_RC=y
 CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y