diff --git a/components/espcoredump/src/port/riscv/core_dump_port.c b/components/espcoredump/src/port/riscv/core_dump_port.c
index 8c947a1eee..49e0d40455 100644
--- a/components/espcoredump/src/port/riscv/core_dump_port.c
+++ b/components/espcoredump/src/port/riscv/core_dump_port.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -28,8 +28,9 @@ const static char TAG[] __attribute__((unused)) = "esp_core_dump_port";
 #define COREDUMP_EM_RISCV                   0xF3
 
 #define COREDUMP_INVALID_CAUSE_VALUE        0xFFFF
-#define COREDUMP_FAKE_STACK_START           0x20000000U
-#define COREDUMP_FAKE_STACK_LIMIT           0x30000000U
+// Fake stack range is outside of DRAM and EXTRAM regions
+#define COREDUMP_FAKE_STACK_START           0x70000000U
+#define COREDUMP_FAKE_STACK_LIMIT           0x80000000U
 
 #define min(a,b) ((a) < (b) ? (a) : (b))
 #define max(a,b) ((a) < (b) ? (b) : (a))
diff --git a/tools/test_apps/system/panic/test_panic_util/panic_dut.py b/tools/test_apps/system/panic/test_panic_util/panic_dut.py
index 1209e935b6..68070f5e73 100644
--- a/tools/test_apps/system/panic/test_panic_util/panic_dut.py
+++ b/tools/test_apps/system/panic/test_panic_util/panic_dut.py
@@ -65,7 +65,7 @@ class PanicTestDut(IdfDut):
 
     @property
     def is_multi_core(self) -> bool:
-        return self.target in ['esp32', 'esp32s3', 'esp32p4']
+        return self.target in ['esp32', 'esp32s3', 'esp32p4', 'esp32h4', 'esp32s31']
 
     def run_test_func(self, test_func_name: str) -> None:
         if self.target == 'esp32p4' and not self.app.sdkconfig.get('ESP32P4_SELECTS_REV_LESS_V3'):