From 50051b74a57aeed09b511e6114a393e731672e8a Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 12 Mar 2026 21:27:06 +0800 Subject: [PATCH] feat(clk): support for esp32s31 clock tree --- Kconfig | 1 - .../src/esp32s31/bootloader_esp32s31.c | 2 +- .../test_apps/rtc_custom_section/README.md | 4 +- .../esp32c3/include/hal/clk_tree_ll.h | 2 +- .../esp32c5/include/hal/clk_tree_ll.h | 2 +- .../esp32c6/include/hal/clk_tree_ll.h | 2 +- .../esp32c61/include/hal/clk_tree_ll.h | 4 +- .../esp32h2/include/hal/clk_tree_ll.h | 2 +- .../esp32h21/include/hal/clk_tree_ll.h | 2 +- .../esp32h4/include/hal/clk_tree_ll.h | 2 +- .../esp32p4/include/hal/clk_tree_ll.h | 2 +- .../esp32s2/include/hal/clk_tree_ll.h | 2 +- .../esp32s3/include/hal/clk_tree_ll.h | 2 +- .../esp_hal_clock/esp32s31/clk_tree_hal.c | 34 +- .../esp32s31/include/hal/clk_tree_ll.h | 453 +++++++++--------- .../esp32s31/include/hal/mspi_ll.h | 2 +- .../esp32s31/include/hal/spimem_flash_ll.h | 2 +- .../esp_hal_pmu/esp32s31/include/hal/pmu_ll.h | 5 + .../esp_hal_regi2c/esp32h21/regi2c_impl.c | 2 +- .../esp32s31/include/hal/regi2c_ctrl_ll.h | 6 +- .../test_apps/main/test_regi2c.c | 5 + components/esp_hw_support/clk_ctrl_os.c | 2 +- .../port/esp32s31/CMakeLists.txt | 1 + .../esp_hw_support/port/esp32s31/Kconfig.rtc | 11 +- .../port/esp32s31/esp_clk_tree.c | 65 ++- .../port/esp32s31/include/soc/rtc.h | 81 +--- .../esp_hw_support/port/esp32s31/pmu_init.c | 6 +- .../esp_hw_support/port/esp32s31/pmu_param.c | 68 +-- .../port/esp32s31/private_include/pmu_param.h | 4 +- .../esp_hw_support/port/esp32s31/rtc_clk.c | 408 +++++++++++++--- .../port/esp32s31/rtc_clk_init.c | 76 +++ .../esp_hw_support/port/esp32s31/rtc_time.c | 125 +++-- .../test_apps/rtc_clk/README.md | 4 +- components/esp_rom/CMakeLists.txt | 7 + .../esp32s31/include/esp32s31/rom/rtc.h | 3 +- .../esp_system/ld/esp32s31/memory.ld.in | 8 + .../esp_system/ld/esp32s31/sections.ld.in | 2 + components/esp_system/port/soc/esp32h4/clk.c | 1 - components/esp_system/port/soc/esp32p4/clk.c | 7 +- .../esp_system/port/soc/esp32s31/Kconfig.cpu | 7 + components/esp_system/port/soc/esp32s31/clk.c | 64 ++- components/heap/port/esp32s31/memory_layout.c | 4 +- .../esp32h21/include/soc/regi2c_brownout.h | 6 +- .../soc/esp32h21/include/soc/regi2c_dcdc.h | 4 +- .../esp32s31/include/soc/Kconfig.soc_caps.in | 26 +- .../soc/esp32s31/include/soc/clk_tree_defs.h | 89 ++-- .../soc/esp32s31/include/soc/regi2c_bbpll.h | 123 +++++ .../soc/esp32s31/include/soc/regi2c_dig_reg.h | 64 +++ .../soc/esp32s31/include/soc/regi2c_saradc.h | 2 +- components/soc/esp32s31/include/soc/soc.h | 7 +- .../soc/esp32s31/include/soc/soc_caps.h | 16 +- .../soc/esp32s31/register/soc/pmu_reg.h | 62 ++- .../en/api-reference/peripherals/clk_tree.rst | 4 +- .../api-reference/peripherals/clk_tree.rst | 4 +- 54 files changed, 1241 insertions(+), 658 deletions(-) create mode 100644 components/esp_hw_support/port/esp32s31/rtc_clk_init.c create mode 100644 components/soc/esp32s31/include/soc/regi2c_bbpll.h create mode 100644 components/soc/esp32s31/include/soc/regi2c_dig_reg.h diff --git a/Kconfig b/Kconfig index a4c2de5aa9..63932abd5e 100644 --- a/Kconfig +++ b/Kconfig @@ -151,7 +151,6 @@ mainmenu "Espressif IoT Development Framework Configuration" bool default "y" if IDF_TARGET="esp32s31" select IDF_TARGET_ARCH_RISCV - select IDF_ENV_FPGA select IDF_ENV_BRINGUP config IDF_TARGET_LINUX diff --git a/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c b/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c index 3771709893..fb4ba10b2c 100644 --- a/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c +++ b/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c @@ -36,7 +36,7 @@ static inline void bootloader_hardware_init(void) modem_lpcon_ll_enable_bus_clock(true); -#if !CONFIG_IDF_ENV_FPGA || SOC_REGI2C_SUPPORTED +#if !CONFIG_IDF_ENV_FPGA /* Enable analog i2c master clock */ _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-14678 Remove this? diff --git a/components/bootloader_support/test_apps/rtc_custom_section/README.md b/components/bootloader_support/test_apps/rtc_custom_section/README.md index f921835020..dbabd572b8 100644 --- a/components/bootloader_support/test_apps/rtc_custom_section/README.md +++ b/components/bootloader_support/test_apps/rtc_custom_section/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | --------- | diff --git a/components/esp_hal_clock/esp32c3/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32c3/include/hal/clk_tree_ll.h index a1f4228ab0..c5da415cc2 100644 --- a/components/esp_hal_clock/esp32c3/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32c3/include/hal/clk_tree_ll.h @@ -59,7 +59,7 @@ typedef enum { * @brief XTAL32K_CLK configuration structure */ typedef struct { - uint32_t dac : 6; + uint32_t dac : 3; uint32_t dres : 3; uint32_t dgm : 3; uint32_t dbuf: 1; diff --git a/components/esp_hal_clock/esp32c5/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32c5/include/hal/clk_tree_ll.h index 7e2c3f8d18..a9b4204f8a 100644 --- a/components/esp_hal_clock/esp32c5/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32c5/include/hal/clk_tree_ll.h @@ -62,7 +62,7 @@ typedef enum { * @brief XTAL32K_CLK configuration structure */ typedef struct { - uint32_t dac : 6; + uint32_t dac : 3; uint32_t dres : 3; uint32_t dgm : 3; uint32_t dbuf: 1; diff --git a/components/esp_hal_clock/esp32c6/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32c6/include/hal/clk_tree_ll.h index cfc119fc3c..4a9adca83f 100644 --- a/components/esp_hal_clock/esp32c6/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32c6/include/hal/clk_tree_ll.h @@ -64,7 +64,7 @@ typedef enum { * @brief XTAL32K_CLK configuration structure */ typedef struct { - uint32_t dac : 6; + uint32_t dac : 3; uint32_t dres : 3; uint32_t dgm : 3; uint32_t dbuf: 1; diff --git a/components/esp_hal_clock/esp32c61/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32c61/include/hal/clk_tree_ll.h index 4d355cafee..fac24b343f 100644 --- a/components/esp_hal_clock/esp32c61/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32c61/include/hal/clk_tree_ll.h @@ -57,7 +57,7 @@ typedef enum { * @brief XTAL32K_CLK configuration structure */ typedef struct { - uint32_t dac : 6; + uint32_t dac : 3; uint32_t dres : 3; uint32_t dgm : 3; uint32_t dbuf: 1; @@ -218,8 +218,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_get_freq_mhz(v return PCR.sysclk_conf.clk_xtal_freq; } -#define clk_ll_xtal_load_freq_mhz() clk_ll_xtal_get_freq_mhz() - /** * @brief Get SPLL_CLK frequency * diff --git a/components/esp_hal_clock/esp32h2/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32h2/include/hal/clk_tree_ll.h index 766869cc6f..be939c1b8e 100644 --- a/components/esp_hal_clock/esp32h2/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32h2/include/hal/clk_tree_ll.h @@ -63,7 +63,7 @@ typedef enum { * @brief XTAL32K_CLK configuration structure */ typedef struct { - uint32_t dac : 6; + uint32_t dac : 3; uint32_t dres : 3; uint32_t dgm : 3; uint32_t dbuf: 1; diff --git a/components/esp_hal_clock/esp32h21/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32h21/include/hal/clk_tree_ll.h index 2d3843d8ba..2c938c289a 100644 --- a/components/esp_hal_clock/esp32h21/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32h21/include/hal/clk_tree_ll.h @@ -54,7 +54,7 @@ typedef enum { * @brief XTAL32K_CLK configuration structure */ typedef struct { - uint32_t dac : 6; + uint32_t dac : 3; uint32_t dres : 3; uint32_t dgm : 3; uint32_t dbuf: 1; diff --git a/components/esp_hal_clock/esp32h4/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32h4/include/hal/clk_tree_ll.h index 1a8e16f053..f89b1bd89b 100644 --- a/components/esp_hal_clock/esp32h4/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32h4/include/hal/clk_tree_ll.h @@ -54,7 +54,7 @@ typedef enum { * @brief XTAL32K_CLK configuration structure */ typedef struct { - uint32_t dac : 6; + uint32_t dac : 3; uint32_t dres : 3; uint32_t dgm : 3; uint32_t dbuf: 1; diff --git a/components/esp_hal_clock/esp32p4/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32p4/include/hal/clk_tree_ll.h index b33e7d4da4..3fc6043000 100644 --- a/components/esp_hal_clock/esp32p4/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32p4/include/hal/clk_tree_ll.h @@ -86,7 +86,7 @@ typedef enum { * @brief XTAL32K_CLK configuration structure */ typedef struct { - uint32_t dac : 6; + uint32_t dac : 3; uint32_t dres : 3; uint32_t dgm : 3; uint32_t dbuf: 1; diff --git a/components/esp_hal_clock/esp32s2/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32s2/include/hal/clk_tree_ll.h index 95ea91cce5..430940489f 100644 --- a/components/esp_hal_clock/esp32s2/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32s2/include/hal/clk_tree_ll.h @@ -82,7 +82,7 @@ typedef enum { * @brief XTAL32K_CLK configuration structure */ typedef struct { - uint32_t dac : 6; + uint32_t dac : 3; uint32_t dres : 3; uint32_t dgm : 3; uint32_t dbuf: 1; diff --git a/components/esp_hal_clock/esp32s3/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32s3/include/hal/clk_tree_ll.h index d55680c3ab..b097ef6293 100644 --- a/components/esp_hal_clock/esp32s3/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32s3/include/hal/clk_tree_ll.h @@ -60,7 +60,7 @@ typedef enum { * @brief XTAL32K_CLK configuration structure */ typedef struct { - uint32_t dac : 6; + uint32_t dac : 3; uint32_t dres : 3; uint32_t dgm : 3; uint32_t dbuf: 1; diff --git a/components/esp_hal_clock/esp32s31/clk_tree_hal.c b/components/esp_hal_clock/esp32s31/clk_tree_hal.c index 90e39e281f..de38f5973b 100644 --- a/components/esp_hal_clock/esp32s31/clk_tree_hal.c +++ b/components/esp_hal_clock/esp32s31/clk_tree_hal.c @@ -10,10 +10,6 @@ #include "hal/assert.h" #include "hal/log.h" -static const char *CLK_HAL_TAG = "clk_hal"; - -// TODO: [ESP32S31] IDF-14733 - uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src) { switch (cpu_clk_src) { @@ -23,6 +19,8 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src) return clk_ll_cpll_get_freq_mhz(clk_hal_xtal_get_freq_mhz()); case SOC_CPU_CLK_SRC_RC_FAST: return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ; + case SOC_CPU_CLK_SRC_PLL_F240M: + return CLK_LL_PLL_240M_FREQ_MHZ; default: // Unknown CPU_CLK mux input HAL_ASSERT(false); @@ -42,14 +40,9 @@ uint32_t clk_hal_cpu_get_freq_hz(void) return clk_hal_soc_root_get_freq_mhz(source) * MHZ * denominator / (integer * denominator + numerator); } -static uint32_t clk_hal_mem_get_freq_hz(void) -{ - return clk_hal_cpu_get_freq_hz() / clk_ll_mem_get_divider(); -} - uint32_t clk_hal_sys_get_freq_hz(void) { - return clk_hal_mem_get_freq_hz() / clk_ll_sys_get_divider(); + return clk_hal_cpu_get_freq_hz() / clk_ll_sys_get_divider(); } uint32_t clk_hal_apb_get_freq_hz(void) @@ -64,8 +57,6 @@ uint32_t clk_hal_lp_slow_get_freq_hz(void) return SOC_CLK_RC_SLOW_FREQ_APPROX; case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX; - case SOC_RTC_SLOW_CLK_SRC_RC32K: - return SOC_CLK_RC32K_FREQ_APPROX; default: // Unknown RTC_SLOW_CLK mux input HAL_ASSERT(false); @@ -75,11 +66,8 @@ uint32_t clk_hal_lp_slow_get_freq_hz(void) IRAM_ATTR uint32_t clk_hal_xtal_get_freq_mhz(void) { - uint32_t freq = clk_ll_xtal_load_freq_mhz(); - if (freq == 0) { - HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz"); - return (uint32_t)SOC_XTAL_FREQ_40M; - } + uint32_t freq = clk_ll_xtal_get_freq_mhz(); + HAL_ASSERT(freq == SOC_XTAL_FREQ_40M); return freq; } @@ -96,15 +84,3 @@ uint32_t clk_hal_apll_get_freq_hz(void) uint32_t apll_freq_hz = (uint32_t)((xtal_freq_hz * numerator) / denominator); return apll_freq_hz; } - -// void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id) -// { -// clk_ll_bind_output_channel(clk_sig, channel_id); -// clk_ll_set_output_channel_divider(channel_id, 1); -// clk_ll_enable_output_channel(channel_id, true); -// } - -// void clk_hal_clock_output_teardown(clock_out_channel_t channel_id) -// { -// clk_ll_enable_output_channel(channel_id, false); -// } diff --git a/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h index 3e7a3e81f1..1a3dab1537 100644 --- a/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h @@ -15,13 +15,12 @@ #include "soc/lp_clkrst_reg.h" #include "soc/lp_clkrst_struct.h" #include "soc/hp_alive_sys_reg.h" +#include "soc/hp_alive_sys_struct.h" #include "soc/pmu_reg.h" -// #include "hal/clkout_channel.h" #include "hal/assert.h" #include "hal/log.h" #include "esp32s31/rom/rtc.h" #include "hal/misc.h" -#include "hal/efuse_hal.h" #define MHZ (1000000) @@ -30,10 +29,8 @@ #define CLK_LL_PLL_80M_FREQ_MHZ (80) #define CLK_LL_PLL_160M_FREQ_MHZ (160) #define CLK_LL_PLL_240M_FREQ_MHZ (240) -#define CLK_LL_PLL_SDIO_FREQ_MHZ (200) -#define CLK_LL_PLL_360M_FREQ_MHZ (360) -#define CLK_LL_PLL_400M_FREQ_MHZ (400) +#define CLK_LL_PLL_320M_FREQ_MHZ (320) #define CLK_LL_PLL_480M_FREQ_MHZ (480) #define CLK_LL_PLL_500M_FREQ_MHZ (500) @@ -58,9 +55,9 @@ #define CLK_LL_APLL_MAX_HZ (125000000) // 125MHz, refer to 'periph_rtc_apll_freq_set' for the calculation #define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \ - .dac = 3, \ - .dres = 3, \ - .dgm = 3, \ + .dac = 7, \ + .dres = 7, \ + .dgm = 7, \ .dbuf = 1, \ } @@ -80,7 +77,7 @@ typedef enum { * @brief XTAL32K_CLK configuration structure */ typedef struct { - uint32_t dac : 6; + uint32_t dac : 3; uint32_t dres : 3; uint32_t dgm : 3; uint32_t dbuf: 1; @@ -91,7 +88,8 @@ typedef struct { */ static inline __attribute__((always_inline)) void clk_ll_cpll_enable(void) { - // TODO: [ESP32S31] IDF-14733 + SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_CPLL); + SET_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN); } /** @@ -99,7 +97,8 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_enable(void) */ static inline __attribute__((always_inline)) void clk_ll_cpll_disable(void) { - // TODO: [ESP32S31] IDF-14733 + CLEAR_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN); + CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_CPLL); } /** @@ -107,7 +106,8 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_disable(void) */ static inline __attribute__((always_inline)) void clk_ll_apll_enable(void) { - // TODO: [ESP32S31] IDF-14733 + SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_APLL); + SET_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN); } /** @@ -115,23 +115,8 @@ static inline __attribute__((always_inline)) void clk_ll_apll_enable(void) */ static inline __attribute__((always_inline)) void clk_ll_apll_disable(void) { - // TODO: [ESP32S31] IDF-14733 -} - -/** - * @brief Enable the internal oscillator output for LP_PLL_CLK - */ -static inline __attribute__((always_inline)) void clk_ll_lp_pll_enable(void) -{ - // TODO: [ESP32S31] IDF-14733 -} - -/** - * @brief Disable the internal oscillator output for LP_PLL_CLK - */ -static inline __attribute__((always_inline)) void clk_ll_lp_pll_disable(void) -{ - // TODO: [ESP32S31] IDF-14733 + CLEAR_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN); + CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_APLL); } /** @@ -140,7 +125,8 @@ static inline __attribute__((always_inline)) void clk_ll_lp_pll_disable(void) static inline __attribute__((always_inline)) void clk_ll_mpll_enable(void) { REG_SET_BIT(PMU_PSRAM_CFG_REG, PMU_PSRAM_XPD); - REG_SET_BIT(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN); + SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_MPLL); + SET_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN); } /** @@ -149,6 +135,8 @@ static inline __attribute__((always_inline)) void clk_ll_mpll_enable(void) static inline __attribute__((always_inline)) void clk_ll_mpll_disable(void) { REG_CLR_BIT(PMU_PSRAM_CFG_REG, PMU_PSRAM_XPD); + CLEAR_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN); + CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_MPLL); } /** @@ -158,7 +146,15 @@ static inline __attribute__((always_inline)) void clk_ll_mpll_disable(void) */ static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { - // TODO: [ESP32S31] IDF-14733 + // Configure xtal32k + clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT(); + LP_CLKRST.xtal32k.dac_xtal32k = cfg.dac; + LP_CLKRST.xtal32k.dres_xtal32k = cfg.dres; + LP_CLKRST.xtal32k.dgm_xtal32k = cfg.dgm; + LP_CLKRST.xtal32k.dbuf_xtal32k = cfg.dbuf; + // Enable xtal32k xpd + SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K); + REG_SET_BIT(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN); } /** @@ -166,9 +162,9 @@ static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_x */ static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { + REG_CLR_BIT(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN); // Disable xtal32k xpd - //ESP32S31-TODO - // CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K); + CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K); } /** @@ -178,8 +174,7 @@ static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) */ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { - //ESP32S31-TODO// TODO: [ESP32S31] IDF-14733 - return 0; + return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K) == 1; } /** @@ -187,7 +182,9 @@ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void */ static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void) { - // TODO: [ESP32S31] IDF-14733 + REG_SET_BIT(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_RC_32K_CLK_EN); + // Enable rc32k xpd status + SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); } /** @@ -195,7 +192,9 @@ static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void) */ static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void) { - // TODO: [ESP32S31] IDF-14733 + // Disable rc32k xpd status + CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); + REG_CLR_BIT(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_RC_32K_CLK_EN); } /** @@ -205,8 +204,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void) */ static inline __attribute__((always_inline)) bool clk_ll_rc32k_is_enabled(void) { - //ESP32S31-TODO - return 0; + return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K) == 1; } /** @@ -214,7 +212,7 @@ static inline __attribute__((always_inline)) bool clk_ll_rc32k_is_enabled(void) */ static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void) { - // TODO: [ESP32S31] IDF-14733 + SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK); } /** @@ -222,7 +220,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void) */ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) { - // TODO: [ESP32S31] IDF-14733 + CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK); } /** @@ -232,8 +230,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) */ static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { - // TODO: [ESP32S31] IDF-14733 - return 0;// TODO: [ESP32S31] IDF-14733 + return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK) == 1; } /** @@ -241,7 +238,7 @@ static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void */ static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { - // TODO: [ESP32S31] IDF-14733 + HP_ALIVE_SYS.hp_clk_ctrl.hp_fosc_20m_clk_en = 1; } /** @@ -249,7 +246,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(voi */ static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { - // TODO: [ESP32S31] IDF-14733 + HP_ALIVE_SYS.hp_clk_ctrl.hp_fosc_20m_clk_en = 0; } /** @@ -259,8 +256,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(vo */ static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { - return 0; - // TODO: [ESP32S31] IDF-14733 + return HP_ALIVE_SYS.hp_clk_ctrl.hp_fosc_20m_clk_en; } /** @@ -268,7 +264,7 @@ static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled */ static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { - // TODO: [ESP32S31] IDF-14733 + HP_ALIVE_SYS.hp_clk_ctrl.hp_xtal_32k_clk_en = 1; } /** @@ -276,7 +272,7 @@ static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(voi */ static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { - // TODO: [ESP32S31] IDF-14733 + HP_ALIVE_SYS.hp_clk_ctrl.hp_xtal_32k_clk_en = 0; } /** @@ -286,28 +282,15 @@ static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(vo */ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { - return 0; - // TODO: [ESP32S31] IDF-14733 + return HP_ALIVE_SYS.hp_clk_ctrl.hp_xtal_32k_clk_en; } -/** - * @brief Get XTAL_CLK frequency - * - * @return Main XTAL clock frequency, in MHz. - */ -static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_get_freq_mhz(void) -{ - return 40; -} - -#define clk_ll_xtal_load_freq_mhz() clk_ll_xtal_get_freq_mhz() - /** * @brief Enable the digital RC32K_CLK, which is used to support peripherals. */ static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void) { - // TODO: [ESP32S31] IDF-14733 + HP_ALIVE_SYS.hp_clk_ctrl.hp_rc_32k_clk_en = 1; } /** @@ -315,7 +298,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void) */ static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void) { - // TODO: [ESP32S31] IDF-14733 + HP_ALIVE_SYS.hp_clk_ctrl.hp_rc_32k_clk_en = 0; } /** @@ -325,8 +308,17 @@ static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void */ static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void) { - return 0; - // TODO: [ESP32S31] IDF-14733 + return HP_ALIVE_SYS.hp_clk_ctrl.hp_rc_32k_clk_en; +} + +/** + * @brief Get XTAL_CLK frequency + * + * @return Main XTAL clock frequency, in MHz. + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_get_freq_mhz(void) +{ + return LP_CLKRST.hp_clk_ctrl.clk_xtal_freq; } /** @@ -338,8 +330,9 @@ static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(v */ static inline __attribute__((always_inline)) uint32_t clk_ll_cpll_get_freq_mhz(uint32_t xtal_freq_mhz) { - // TODO: [ESP32S31] IDF-14733 - return 0; + uint8_t fb_div = HAL_FORCE_READ_U32_REG_FIELD(LP_CLKRST.cpll_div, cpll_fb_div); + uint8_t ref_div = LP_CLKRST.cpll_div.cpll_ref_div; + return xtal_freq_mhz * fb_div / ref_div; } /** @@ -347,10 +340,24 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpll_get_freq_mhz(u * * @param cpll_freq_mhz CPLL frequency, in MHz */ -static inline __attribute__((always_inline)) void clk_ll_cpll_set_freq_mhz(uint32_t cpll_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_cpll_set_freq_mhz(uint32_t cpll_freq_mhz, uint32_t xtal_freq_mhz) { - // Do nothing. CPLL frequency controlled by analog only on the target. - (void)cpll_freq_mhz; + HAL_ASSERT(xtal_freq_mhz == 40); + // cpll_freq = freq_xtal * fb_div / ref_div + uint8_t fb_div = 8; + uint8_t ref_div = 1; + + switch (cpll_freq_mhz) { + case CLK_LL_PLL_320M_FREQ_MHZ: + default: + /* Configure 320M CPLL */ + fb_div = 8; + ref_div = 1; + break; + } + + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_CLKRST.cpll_div, cpll_fb_div, fb_div); + LP_CLKRST.cpll_div.cpll_ref_div = ref_div; } /** @@ -361,7 +368,9 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_set_freq_mhz(uint3 */ static inline __attribute__((always_inline)) void clk_ll_cpll_set_config(uint32_t cpll_freq_mhz, uint32_t xtal_freq_mhz) { - // TODO: [ESP32S31] IDF-14733 + // Do nothing. CPLL frequency controlled by digital only on the target. + HAL_ASSERT(xtal_freq_mhz == 40); + HAL_ASSERT(cpll_freq_mhz == CLK_LL_PLL_320M_FREQ_MHZ); } /** @@ -404,7 +413,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_mpll_get_freq_mhz(u } /** - * @brief Set MPLL frequency from XTAL source (Analog part - through regi2c) + * @brief Set MPLL frequency from XTAL source * * @param mpll_freq_mhz MPLL frequency, in MHz * @param xtal_freq_mhz XTAL frequency, in MHz @@ -454,7 +463,7 @@ static inline __attribute__((always_inline)) bool clk_ll_mpll_calibration_is_don */ static inline __attribute__((always_inline)) void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2) { - // TODO: [ESP32S31] IDF-14733 + // TODO: IDF-14771, IDF-14750 } /** @@ -467,7 +476,7 @@ static inline __attribute__((always_inline)) void clk_ll_apll_get_config(uint32_ */ static inline __attribute__((always_inline)) void clk_ll_apll_set_config(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2) { - // TODO: [ESP32S31] IDF-14733 + // TODO: IDF-14771, IDF-14750 } /** @@ -475,7 +484,7 @@ static inline __attribute__((always_inline)) void clk_ll_apll_set_config(uint32_ */ static inline __attribute__((always_inline)) void clk_ll_apll_set_calibration(void) { - // TODO: [ESP32S31] IDF-14733 + // TODO: IDF-14771, IDF-14750 } /** @@ -485,12 +494,12 @@ static inline __attribute__((always_inline)) void clk_ll_apll_set_calibration(vo */ static inline __attribute__((always_inline)) bool clk_ll_apll_calibration_is_done(void) { - // TODO: [ESP32S31] IDF-14733 + // TODO: IDF-14771, IDF-14750 return 0; } /** - * @brief To enable the change of cpu_div_num, mem_div_num, sys_div_num, and apb_div_num + * @brief To enable the change of soc_clk_sel, cpu_div_num, mem_div_num, sys_div_num, and apb_div_num */ static inline __attribute__((always_inline)) void clk_ll_bus_update(void) { @@ -505,7 +514,6 @@ static inline __attribute__((always_inline)) void clk_ll_bus_update(void) */ static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk_src_t in_sel) { - // TODO: [ESP32S31] IDF-14733 switch (in_sel) { case SOC_CPU_CLK_SRC_XTAL: HP_SYS_CLKRST.soc_clk_sel.reg_soc_clk_sel = 0; @@ -516,6 +524,9 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk case SOC_CPU_CLK_SRC_RC_FAST: HP_SYS_CLKRST.soc_clk_sel.reg_soc_clk_sel = 2; break; + case SOC_CPU_CLK_SRC_PLL_F240M: + HP_SYS_CLKRST.soc_clk_sel.reg_soc_clk_sel = 3; + break; default: // Unsupported CPU_CLK mux input sel abort(); @@ -529,7 +540,6 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk */ static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_src(void) { - // TODO: [ESP32S31] IDF-14733 uint32_t clk_sel = HP_SYS_CLKRST.soc_clk_sel.reg_soc_clk_sel; switch (clk_sel) { case 0: @@ -538,6 +548,8 @@ static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_sr return SOC_CPU_CLK_SRC_CPLL; case 2: return SOC_CPU_CLK_SRC_RC_FAST; + case 3: + return SOC_CPU_CLK_SRC_PLL_F240M; default: // Invalid HP_ROOT_CLK_SRC_SEL value return SOC_CPU_CLK_SRC_INVALID; @@ -553,13 +565,12 @@ static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_sr */ static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t integer, uint32_t numerator, uint32_t denominator) { - // TODO: [ESP32S31] IDF-14733 HAL_ASSERT(integer >= 1 && integer <= HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_V); HAL_ASSERT(numerator <= HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_V); HAL_ASSERT(denominator <= HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_V); HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.cpu_freq_ctrl0, reg_cpu_clk_div_num, integer - 1); - HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.cpu_freq_ctrl0, reg_cpu_clk_div_numerator, numerator); - HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.cpu_freq_ctrl0, reg_cpu_clk_div_denominator, denominator); + HP_SYS_CLKRST.cpu_freq_ctrl0.reg_cpu_clk_div_numerator = numerator; + HP_SYS_CLKRST.cpu_freq_ctrl0.reg_cpu_clk_div_denominator = denominator; } /** @@ -571,16 +582,13 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_ */ static inline __attribute__((always_inline)) void clk_ll_cpu_get_divider(uint32_t *integer, uint32_t *numerator, uint32_t *denominator) { - // TODO: [ESP32S31] IDF-14733 *integer = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.cpu_freq_ctrl0, reg_cpu_clk_div_num) + 1; - *numerator = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.cpu_freq_ctrl0, reg_cpu_clk_div_numerator); - *denominator = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.cpu_freq_ctrl0, reg_cpu_clk_div_denominator); + *numerator = HP_SYS_CLKRST.cpu_freq_ctrl0.reg_cpu_clk_div_numerator; + *denominator = HP_SYS_CLKRST.cpu_freq_ctrl0.reg_cpu_clk_div_denominator; } /** - * @brief Set MEM_CLK divider. freq of MEM_CLK = freq of CPU_CLK / divider - * - * ESP32P4 MEM_CLK supports fractional divnum (not supported in software yet) + * @brief Set MEM_CLK (ROM_CLK) divider. freq of MEM_CLK = freq of CPU_CLK / divider * * @note There is constraint on the mem divider. Hardware could change the actual divider if the configured value is * unachievable. Be careful on this. Check TRM or upper layer. @@ -589,34 +597,29 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_get_divider(uint32_ */ static inline __attribute__((always_inline)) void clk_ll_mem_set_divider(uint32_t divider) { - // TODO: [ESP32S31] IDF-14733 - HAL_ASSERT(divider >= 1 && divider <= 2); // We haven't confirmed the reliable functionality of cache when cpu_clk freq is more than 2 times faster than the cache clk freq. Need to verify before removing the constraint of divider <= 2. - HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.mem_freq_ctrl0, reg_mem_clk_div_num, divider - 1); + HAL_ASSERT(divider == 1 || divider == 2); // 1-bit field + HP_SYS_CLKRST.mem_freq_ctrl0.reg_mem_clk_div_num = divider - 1; } /** - * @brief Get MEM_CLK divider - * - * Fractional divnum not used now. + * @brief Get MEM_CLK (ROM_CLK) divider * * @return Divider. Divider = (CLK_DIV_NUM + 1). */ static inline __attribute__((always_inline)) uint32_t clk_ll_mem_get_divider(void) { - // TODO: [ESP32S31] IDF-14733 - return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.mem_freq_ctrl0, reg_mem_clk_div_num) + 1; + return HP_SYS_CLKRST.mem_freq_ctrl0.reg_mem_clk_div_num + 1; } /** - * @brief Set SYS_CLK divider. freq of SYS_CLK = freq of MEM_CLK / divider + * @brief Set SYS_CLK divider. freq of SYS_CLK = freq of CPU_CLK / divider * - * ESP32P4 SYS_CLK supports fractional divnum (not supported in software yet) + * ESP32S31 SYS_CLK supports fractional divnum (not supported in software yet) * * @param divider Divider. CLK_DIV_NUM = divider - 1. */ static inline __attribute__((always_inline)) void clk_ll_sys_set_divider(uint32_t divider) { - // TODO: [ESP32S31] IDF-14733 HAL_ASSERT(divider >= 1); HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.sys_freq_ctrl0, reg_sys_clk_div_num, divider - 1); } @@ -630,14 +633,13 @@ static inline __attribute__((always_inline)) void clk_ll_sys_set_divider(uint32_ */ static inline __attribute__((always_inline)) uint32_t clk_ll_sys_get_divider(void) { - // TODO: [ESP32S31] IDF-14733 return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.sys_freq_ctrl0, reg_sys_clk_div_num) + 1; } /** * @brief Set APB_CLK divider. freq of APB_CLK = freq of SYS_CLK / divider * - * ESP32P4 APB_CLK supports fractional divnum (not supported in software yet) + * ESP32S31 APB_CLK supports fractional divnum (not supported in software yet) * * @note There is constraint on the apb divider. Hardware could change the actual divider if the configured value is * unachievable. Be careful on this. Check TRM or upper layer. @@ -646,7 +648,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_sys_get_divider(voi */ static inline __attribute__((always_inline)) void clk_ll_apb_set_divider(uint32_t divider) { - // TODO: [ESP32S31] IDF-14733 HAL_ASSERT(divider >= 1); HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.apb_freq_ctrl0, reg_apb_clk_div_num, divider - 1); } @@ -660,10 +661,17 @@ static inline __attribute__((always_inline)) void clk_ll_apb_set_divider(uint32_ */ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(void) { - // TODO: [ESP32S31] IDF-14733 return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.apb_freq_ctrl0, reg_apb_clk_div_num) + 1; } +// TODO: IDF-14730 +// static inline __attribute__((always_inline)) void clk_ll_ref_500m_set_src(soc_ref_500m_clk_src_t in_sel) +// { +// // 0: cpll (320MHz) +// // 1: mpll (500MHz) +// HP_SYS_CLKRST.ref_500m_ctrl0.reg_ref_500m_sel = in_sel; +// } + /** * @brief Set PLL_F50M_CLK divider. freq of PLL_F50M_CLK = freq of MPLL_CLK / divider * @@ -671,7 +679,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi */ static inline __attribute__((always_inline)) void clk_ll_pll_f50m_set_divider(uint32_t divider) { - // TODO: [ESP32S31] IDF-14733 HAL_ASSERT(divider >= 1); HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.ref_50m_ctrl0, reg_ref_50m_clk_div_num, divider - 1); } @@ -683,7 +690,6 @@ static inline __attribute__((always_inline)) void clk_ll_pll_f50m_set_divider(ui */ static inline __attribute__((always_inline)) void clk_ll_pll_f25m_set_divider(uint32_t divider) { - // TODO: [ESP32S31] IDF-14733 HAL_ASSERT(divider >= 1); HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.ref_25m_ctrl0, reg_ref_25m_clk_div_num, divider - 1); } @@ -695,7 +701,6 @@ static inline __attribute__((always_inline)) void clk_ll_pll_f25m_set_divider(ui */ static inline __attribute__((always_inline)) void clk_ll_pll_f20m_set_divider(uint32_t divider) { - // TODO: [ESP32S31] IDF-14733 HAL_ASSERT(divider >= 1); HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.ref_20m_ctrl0, reg_ref_20m_clk_div_num, divider - 1); } @@ -707,10 +712,82 @@ static inline __attribute__((always_inline)) void clk_ll_pll_f20m_set_divider(ui */ static inline __attribute__((always_inline)) uint32_t clk_ll_pll_f20m_get_divider(void) { - // TODO: [ESP32S31] IDF-14733 return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.ref_20m_ctrl0, reg_ref_20m_clk_div_num) + 1; } +/** + * @brief Select the frequency calculation clock source for timergroup0 + * + * @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t + */ +static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel) +{ + int timg_cali_clk_sel = -1; + + switch (clk_sel) { + case CLK_CAL_MPLL: + timg_cali_clk_sel = 0; + break; + case CLK_CAL_BBPLL: + timg_cali_clk_sel = 1; + break; + case CLK_CAL_CPLL: + timg_cali_clk_sel = 2; + break; + case CLK_CAL_APLL: + timg_cali_clk_sel = 3; + break; + case CLK_CAL_AHB: + timg_cali_clk_sel = 4; + break; + case CLK_CAL_APB: + timg_cali_clk_sel = 5; + break; + case CLK_CAL_ROM: + timg_cali_clk_sel = 6; + break; + case CLK_CAL_RC_FAST: + timg_cali_clk_sel = 7; + break; + case CLK_CAL_RC_SLOW: + timg_cali_clk_sel = 8; + break; + case CLK_CAL_32K_XTAL: + timg_cali_clk_sel = 10; + break; + case CLK_CAL_XTAL: + timg_cali_clk_sel = 12; + break; + case CLK_CAL_UART0_PAD: + timg_cali_clk_sel = 13; + break; + case CLK_CAL_CORE0: + timg_cali_clk_sel = 14; + break; + case CLK_CAL_CORE1: + timg_cali_clk_sel = 15; + break; + default: + // Unsupported CLK_CAL mux input + abort(); + } + + if (timg_cali_clk_sel >= 0) { + HP_SYS_CLKRST.timergrp0_tgrt_ctrl0.reg_timergrp0_tgrt_clk_src_sel = timg_cali_clk_sel; + } +} + +/** + * @brief Set a divider for the clock to be frequency calculated by timergroup0 + * + * @param divider Divider. PRE_DIV_CNT = divider - 1. + */ +static inline __attribute__((always_inline)) void clk_ll_freq_calculation_set_divider(uint32_t divider) +{ + HAL_ASSERT(divider >= 1); + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.timergrp0_tgrt_ctrl0, reg_timergrp0_tgrt_clk_div_num, divider - 1); +} + /** * @brief Select the clock source for RTC_SLOW_CLK * @@ -718,7 +795,20 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_pll_f20m_get_divide */ static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { - // TODO: [ESP32S31] IDF-14733 + switch (in_sel) { + case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: + LP_CLKRST.root_clk_conf.slow_clk_sel = 0; + break; + case SOC_RTC_SLOW_CLK_SRC_XTAL32K: + LP_CLKRST.root_clk_conf.slow_clk_sel = 1; + break; + // LP_CLKRST.root_clk_conf.slow_clk_sel = 3 is for SOC_RTC_SLOW_CLK_SRC_OSC_SLOW (a 32kHz clock signal generated + // by an external circuit connecting to XTAL_32K_N (i.e. GPIO0)), but we don't use it on ESP32S31, since osc_slow + // clock can not be calibrated to get its actual frequency + default: + // Unsupported RTC_SLOW_CLK mux input sel + abort(); + } } /** @@ -728,41 +818,15 @@ static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rt */ static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { - // TODO: [ESP32S31] IDF-14733 - return SOC_RTC_SLOW_CLK_SRC_RC_SLOW; -} - -/** - * @brief Select the clock source for LP_PLL_CLK - * - * @param in_sel One of the clock sources in soc_lp_pll_clk_src_t - */ -static inline __attribute__((always_inline)) void clk_ll_lp_pll_set_src(soc_lp_pll_clk_src_t in_sel) -{ - // TODO: [ESP32S31] IDF-14733 -} - -/** - * @brief Get the clock source for LP_PLL_CLK - * - * @return Currently selected clock source (one of soc_lp_pll_clk_src_t values) - */ -static inline __attribute__((always_inline)) soc_lp_pll_clk_src_t clk_ll_lp_pll_get_src(void) -{ - // TODO: [ESP32S31] IDF-14733 - return SOC_LP_PLL_CLK_SRC_RC32K; -} - -/** - * @brief Get LP_PLL_CLK frequency - * - * @return LP_PLL clock frequency, in MHz - */ -static inline __attribute__((always_inline)) uint32_t clk_ll_lp_pll_get_freq_mhz(void) -{ - // TODO: [ESP32S31] IDF-14733 - // The target has a fixed 8MHz LP_PLL - return CLK_LL_PLL_8M_FREQ_MHZ; + uint32_t clk_sel = LP_CLKRST.root_clk_conf.slow_clk_sel; + switch (clk_sel) { + case 0: + return SOC_RTC_SLOW_CLK_SRC_RC_SLOW; + case 1: + return SOC_RTC_SLOW_CLK_SRC_XTAL32K; + default: + return SOC_RTC_SLOW_CLK_SRC_INVALID; + } } /** @@ -772,7 +836,17 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_lp_pll_get_freq_mhz */ static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { - // TODO: [ESP32S31] IDF-14733 + switch (in_sel) { + case SOC_RTC_FAST_CLK_SRC_RC_FAST: + LP_CLKRST.root_clk_conf.fast_clk_sel = 0; + break; + case SOC_RTC_FAST_CLK_SRC_XTAL: + LP_CLKRST.root_clk_conf.fast_clk_sel = 1; + break; + default: + // Unsupported RTC_FAST_CLK mux input sel + abort(); + } } /** @@ -782,8 +856,15 @@ static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rt */ static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { - // TODO: [ESP32S31] IDF-14733 - return SOC_RTC_FAST_CLK_SRC_RC_FAST; + uint32_t clk_sel = LP_CLKRST.root_clk_conf.fast_clk_sel; + switch (clk_sel) { + case 0: + return SOC_RTC_FAST_CLK_SRC_RC_FAST; + case 1: + return SOC_RTC_FAST_CLK_SRC_XTAL; + default: + return SOC_RTC_FAST_CLK_SRC_INVALID; + } } /** @@ -794,7 +875,6 @@ static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_f static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { // No divider on the target - // TODO: [ESP32S31] IDF-14733 HAL_ASSERT(divider == 1); } @@ -806,7 +886,6 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uin static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { // No divider on the target, always return divider = 1 - // TODO: [ESP32S31] IDF-14733 return 1; } @@ -818,62 +897,9 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { // No divider on the target - // TODO: [ESP32S31] IDF-14733 HAL_ASSERT(divider == 1); } -/************************** CLOCK OUTPUT **************************/ -// /** -// * @brief Clock output channel configuration -// * -// * @param clk_sig The clock signal source to be mapped to GPIOs -// * @param channel_id The clock output channel ID -// */ -// static inline __attribute__((always_inline)) void clk_ll_bind_output_channel(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id) -// { -// if (channel_id == CLKOUT_CHANNEL_1) { -// HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl0, reg_dbg_ch0_sel, clk_sig); -// } else if (channel_id == CLKOUT_CHANNEL_2) { -// HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl0, reg_dbg_ch1_sel, clk_sig); -// } else { -// abort(); -// } -// } - -// /** -// * @brief Enable the clock output channel -// * -// * @param channel_id The clock output channel ID -// * @param enable Enable or disable the clock output channel -// */ -// static inline __attribute__((always_inline)) void clk_ll_enable_output_channel(clock_out_channel_t channel_id, bool enable) -// { -// if (channel_id == CLKOUT_CHANNEL_1) { -// HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl1, reg_dbg_ch0_en, enable); -// } else if (channel_id == CLKOUT_CHANNEL_2) { -// HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl1, reg_dbg_ch1_en, enable); -// } else { -// abort(); -// } -// } - -// /** -// * @brief Output the mapped clock after frequency division -// * -// * @param channel_id The clock output channel ID -// * @param divider Clock frequency division value -// */ -// static inline __attribute__((always_inline)) void clk_ll_set_output_channel_divider(clock_out_channel_t channel_id, uint32_t div_num) -// { -// if (channel_id == CLKOUT_CHANNEL_1) { -// HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl0, reg_dbg_ch0_div_num, div_num - 1); -// } else if (channel_id == CLKOUT_CHANNEL_2) { -// HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl1, reg_dbg_ch1_div_num, div_num - 1); -// } else { -// abort(); -// } -// } - /************************** LP STORAGE REGISTER STORE/LOAD **************************/ /** * @brief Store RTC_SLOW_CLK calibration value in RTC storage register @@ -885,7 +911,6 @@ static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uin */ static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { - // TODO: [ESP32S31] IDF-14733 REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -898,29 +923,9 @@ static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint */ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { - // TODO: [ESP32S31] IDF-14733 return REG_READ(RTC_SLOW_CLK_CAL_REG); } -/** - * @brief Load the rtc_fix_ticks from RTC storage register - * - * @return The value used to correct the time obtained from the rtc timer when the calibration value changes - */ -static inline __attribute__((always_inline)) uint64_t clk_ll_rtc_slow_load_rtc_fix_us(void) -{ - return 0;// TODO: [ESP32S31] IDF-14733 -} - -/** -* @brief Store rtc_fix_us in RTC storage register -* -* @param rtc_fix_us The value used to correct the time obtained from the rtc timer when the calibration value changes -*/ -static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us) -{ - // TODO: [ESP32S31] IDF-14733 -} #ifdef __cplusplus } #endif diff --git a/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h b/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h index ecb8c85f40..859162f39a 100644 --- a/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h +++ b/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h @@ -200,7 +200,7 @@ static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_perip case FLASH_CLK_SRC_XTAL: clk_val = 0; break; - case FLASH_CLK_SRC_SPLL: + case FLASH_CLK_SRC_BBPLL: clk_val = 1; break; case FLASH_CLK_SRC_CPLL: diff --git a/components/esp_hal_mspi/esp32s31/include/hal/spimem_flash_ll.h b/components/esp_hal_mspi/esp32s31/include/hal/spimem_flash_ll.h index bab1245387..b22e3a3afb 100644 --- a/components/esp_hal_mspi/esp32s31/include/hal/spimem_flash_ll.h +++ b/components/esp_hal_mspi/esp32s31/include/hal/spimem_flash_ll.h @@ -688,7 +688,7 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) source_clk_mhz = CLK_LL_PLL_480M_FREQ_MHZ; // SPLL break; case 2: - source_clk_mhz = CLK_LL_PLL_400M_FREQ_MHZ; // CPLL + source_clk_mhz = CLK_LL_PLL_320M_FREQ_MHZ; // CPLL break; default: break; diff --git a/components/esp_hal_pmu/esp32s31/include/hal/pmu_ll.h b/components/esp_hal_pmu/esp32s31/include/hal/pmu_ll.h index 5a946239ad..3b1140461d 100644 --- a/components/esp_hal_pmu/esp32s31/include/hal/pmu_ll.h +++ b/components/esp_hal_pmu/esp32s31/include/hal/pmu_ll.h @@ -257,6 +257,11 @@ FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias_init(pmu_dev_t *hw, pmu_hp_ hw->hp_sys[mode].regulator0.dig_dbias_init = init; } +FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_connect_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool enable) +{ + hw->hp_sys[mode].regulator0.slp_connect_en = enable; +} + FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd) { hw->hp_sys[mode].regulator0.slp_logic_xpd = slp_xpd; diff --git a/components/esp_hal_regi2c/esp32h21/regi2c_impl.c b/components/esp_hal_regi2c/esp32h21/regi2c_impl.c index 6fdb361392..c7e9e5cb5a 100644 --- a/components/esp_hal_regi2c/esp32h21/regi2c_impl.c +++ b/components/esp_hal_regi2c/esp32h21/regi2c_impl.c @@ -12,7 +12,7 @@ /* SLAVE */ #define REGI2C_BBPLL 0x66 // regi2c_bbpll.h #define REGI2C_BBTOP 0x67 -#define REGI2C_DCDC 0x6D // regi2c_pmu.h +#define REGI2C_DCDC 0x6D // regi2c_dcdc.h #define REGI2C_PERIF 0x69 // regi2c_saradc.h #define REGI2C_RFPLL 0x62 #define REGI2C_SDM 0x63 diff --git a/components/esp_hal_regi2c/esp32s31/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32s31/include/hal/regi2c_ctrl_ll.h index 3635ba77e2..28574d071a 100644 --- a/components/esp_hal_regi2c/esp32s31/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32s31/include/hal/regi2c_ctrl_ll.h @@ -70,17 +70,19 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configur /** * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers */ -static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_i2c_sar_periph_enable(void) { // TODO: IDF-14632, IDF-14744 + //Enable REGI2C for SAR_ADC and TSENS SET_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_XPD_PERIF_I2C); + //Release regi2c reset mode, enter work mode SET_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_RSTB_PERIF_I2C); } /** * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register */ -static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_i2c_sar_periph_disable(void) { // TODO: IDF-14632, IDF-14744 CLEAR_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_XPD_PERIF_I2C); diff --git a/components/esp_hal_regi2c/test_apps/main/test_regi2c.c b/components/esp_hal_regi2c/test_apps/main/test_regi2c.c index a69a8ea7d4..b8766a7748 100644 --- a/components/esp_hal_regi2c/test_apps/main/test_regi2c.c +++ b/components/esp_hal_regi2c/test_apps/main/test_regi2c.c @@ -9,9 +9,14 @@ #include "unity.h" #include "test_regi2c.h" #include "esp_private/regi2c_ctrl.h" +#include "sdkconfig.h" TEST_CASE("regi2c basic read/write test", "[regi2c]") { +#if CONFIG_IDF_ENV_FPGA + TEST_PASS_MESSAGE("regi2c is not supported on FPGA, skip this test"); +#endif + #if CONFIG_IDF_TARGET_ESP32 // For ESP32, we need to enable the APLL clock before accessing the APLL regi2c registers periph_rtc_apll_acquire(); diff --git a/components/esp_hw_support/clk_ctrl_os.c b/components/esp_hw_support/clk_ctrl_os.c index 65a50c2a9b..f8d457d194 100644 --- a/components/esp_hw_support/clk_ctrl_os.c +++ b/components/esp_hw_support/clk_ctrl_os.c @@ -195,7 +195,7 @@ esp_err_t IRAM_ATTR periph_rtc_mpll_freq_set(uint32_t expt_freq_hz, uint32_t *re /* If MPLL is not in use or only one peripheral in use, its frequency can be changed as will * But when more than one peripheral refers MPLL, its frequency is not allowed to change once it is set */ if (s_cur_mpll_freq_hz == 0 || s_mpll_ref_cnt < 2) { - uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz(); + uint32_t xtal_freq_mhz = clk_hal_xtal_get_freq_mhz(); rtc_clk_mpll_configure(xtal_freq_mhz, expt_freq_hz / MHZ, false); s_cur_mpll_freq_hz = clk_ll_mpll_get_freq_mhz(xtal_freq_mhz) * MHZ; } else { diff --git a/components/esp_hw_support/port/esp32s31/CMakeLists.txt b/components/esp_hw_support/port/esp32s31/CMakeLists.txt index 9d5abf9c48..a5d1fb969a 100644 --- a/components/esp_hw_support/port/esp32s31/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32s31/CMakeLists.txt @@ -1,6 +1,7 @@ target_include_directories(${COMPONENT_LIB} PUBLIC .) set(srcs + "rtc_clk_init.c" "rtc_clk.c" "rtc_time.c" "chip_info.c" diff --git a/components/esp_hw_support/port/esp32s31/Kconfig.rtc b/components/esp_hw_support/port/esp32s31/Kconfig.rtc index b524e4867e..e24e5995de 100644 --- a/components/esp_hw_support/port/esp32s31/Kconfig.rtc +++ b/components/esp_hw_support/port/esp32s31/Kconfig.rtc @@ -1,5 +1,3 @@ -# The content of this file is not accurate, please check IDF-14678 - choice RTC_CLK_SRC prompt "RTC clock source" default RTC_CLK_SRC_INT_RC @@ -11,18 +9,13 @@ choice RTC_CLK_SRC config RTC_CLK_SRC_EXT_CRYS bool "External 32 kHz crystal" select ESP_SYSTEM_RTC_EXT_XTAL - config RTC_CLK_SRC_EXT_OSC - bool "External 32 kHz oscillator at 32K_XP pin" - select ESP_SYSTEM_RTC_EXT_OSC - config RTC_CLK_SRC_INT_8MD256 - bool "Internal 17.5 MHz oscillator, divided by 256" endchoice config RTC_CLK_CAL_CYCLES int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + default 3000 if RTC_CLK_SRC_EXT_CRYS default 1024 if RTC_CLK_SRC_INT_RC - range 0 8190 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + range 0 8190 if RTC_CLK_SRC_EXT_CRYS range 0 32766 if RTC_CLK_SRC_INT_RC help When the startup code initializes RTC_SLOW_CLK, it can perform diff --git a/components/esp_hw_support/port/esp32s31/esp_clk_tree.c b/components/esp_hw_support/port/esp32s31/esp_clk_tree.c index f2aa1711c4..8e93d82156 100644 --- a/components/esp_hw_support/port/esp32s31/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32s31/esp_clk_tree.c @@ -16,13 +16,6 @@ ESP_LOG_ATTR_TAG(TAG, "esp_clk_tree"); -/* TODO: [ESP32S31] IDF-14733 */ - -void esp_clk_tree_initialize(void) -{ - /* TODO: [ESP32S31] IDF-14733 */ -} - esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision, uint32_t *freq_value) { @@ -32,11 +25,9 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr uint32_t clk_src_freq = 0; switch (clk_src) { -#if SOC_CLK_TREE_SUPPORTED case SOC_MOD_CLK_CPU: clk_src_freq = clk_hal_cpu_get_freq_hz(); break; -#endif // SOC_CLK_TREE_SUPPORTED case SOC_MOD_CLK_XTAL: clk_src_freq = SOC_XTAL_FREQ_40M * MHZ; break; @@ -52,19 +43,15 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr case SOC_MOD_CLK_PLL_F240M: clk_src_freq = CLK_LL_PLL_240M_FREQ_MHZ * MHZ; break; -#if SOC_CLK_TREE_SUPPORTED case SOC_MOD_CLK_CPLL: clk_src_freq = clk_ll_cpll_get_freq_mhz(clk_hal_xtal_get_freq_mhz()) * MHZ; break; - case SOC_MOD_CLK_SPLL: + case SOC_MOD_CLK_BBPLL: clk_src_freq = CLK_LL_PLL_480M_FREQ_MHZ * MHZ; break; case SOC_MOD_CLK_MPLL: clk_src_freq = clk_ll_mpll_get_freq_mhz(clk_hal_xtal_get_freq_mhz()) * MHZ; break; - case SOC_MOD_CLK_SDIO_PLL: - clk_src_freq = CLK_LL_PLL_SDIO_FREQ_MHZ * MHZ; - break; case SOC_MOD_CLK_RTC_SLOW: clk_src_freq = esp_clk_tree_lp_slow_get_freq_hz(precision); break; @@ -82,10 +69,6 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr case SOC_MOD_CLK_XTAL_D2: clk_src_freq = (clk_hal_xtal_get_freq_mhz() * MHZ) >> 1; break; - case SOC_MOD_CLK_LP_PLL: - clk_src_freq = clk_ll_lp_pll_get_freq_mhz() * MHZ; - break; -#endif // SOC_CLK_TREE_SUPPORTED default: break; } @@ -97,8 +80,52 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr return ESP_OK; } +static int16_t s_cpll_ref_cnt = 0; + +void esp_clk_tree_initialize(void) +{ + // Power + soc_cpu_clk_src_t cpu_clk_src_btld = clk_ll_cpu_get_src(); + if (cpu_clk_src_btld == SOC_CPU_CLK_SRC_CPLL) { + s_cpll_ref_cnt++; + } else if (cpu_clk_src_btld == SOC_CPU_CLK_SRC_PLL_F240M) { + // TODO: IDF-15502 + // pll_f240m clock gating ref count ++ + } + + // Gating +} + +bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable) +{ + bool toggled = false; + switch (clk_circuit) { + case SOC_ROOT_CIRCUIT_CLK_CPLL: + if (enable) { + s_cpll_ref_cnt++; + } else { + s_cpll_ref_cnt--; + } + + // Note that a calibration is usually needed after enabling CPLL + if (s_cpll_ref_cnt == 1) { + clk_ll_cpll_enable(); + toggled = true; + } else if (s_cpll_ref_cnt == 0) { + clk_ll_cpll_disable(); + toggled = true; + } + + assert(s_cpll_ref_cnt >= 0); + break; + default: + break; + } + return toggled; +} + esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) { - /* TODO: [ESP32S31] IDF-14733 */ + // TODO: IDF-15502 return ESP_OK; } diff --git a/components/esp_hw_support/port/esp32s31/include/soc/rtc.h b/components/esp_hw_support/port/esp32s31/include/soc/rtc.h index 388ee01576..7d0dadb89f 100644 --- a/components/esp_hw_support/port/esp32s31/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32s31/include/soc/rtc.h @@ -16,8 +16,6 @@ extern "C" { #endif -// TODO: [ESP32S31] IDF-14678 - /************************************************************************************/ /***************** THIS FILE IS CONSIDERED AS A PRIVATE HEADER FILE *****************/ /*** IT IS NOT RECOMMENDED TO USE THE APIS IN THIS FILE DIRECTLY IN APPLICATIONS ****/ @@ -52,6 +50,15 @@ extern "C" { #define MHZ (1000000) +/* Delays for various clock sources to be enabled/switched. + * All values are in microseconds. + */ +#define SOC_DELAY_RTC_FAST_CLK_SWITCH 3 +#define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300 +#define SOC_DELAY_RC_FAST_ENABLE 50 +#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 +#define SOC_DELAY_RC32K_ENABLE 300 + #define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 #define RTC_CNTL_SCK_DCAP_DEFAULT 128 #define RTC_CNTL_RC32K_DFREQ_DEFAULT 700 @@ -68,28 +75,6 @@ typedef struct rtc_cpu_freq_config_s { #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal -/** - * @brief Clock source to be calibrated using rtc_clk_cal function - * - * @note On ESP32S31, the enum values somehow reflects the register field values of HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL. - */ -typedef enum { - RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK - RTC_CAL_MPLL = 0, //!< 500MHz MSPI_PLL_CLK - RTC_CAL_SPLL = 1, //!< 480MHz SYS_PLL_CLK - RTC_CAL_CPLL = 2, //!< 400MHz CPU_PLL_CLK - RTC_CAL_APLL = 3, //!< AUDIO_PLL_CLK - RTC_CAL_SDIO_PLL0 = 4, //!< SDIO_PLL0_CLK - RTC_CAL_SDIO_PLL1 = 5, //!< SDIO_PLL1_CLK - RTC_CAL_SDIO_PLL2 = 6, //!< SDIO_PLL2_CLK - RTC_CAL_RC_FAST = 7, //!< Internal 20MHz RC oscillator - RTC_CAL_RC_SLOW = 8, //!< Internal 150kHz RC oscillator - RTC_CAL_RC32K = 9, //!< Internal 32kHz RC oscillator, as one type of 32k clock - RTC_CAL_32K_XTAL = 10, //!< External 32kHz XTAL, as one type of 32k clock - RTC_CAL_LP_PLL = 11, //!< 8MHz LP_PLL_CLK - RTC_CAL_INVALID_CLK, //!< Clock not available to calibrate -} rtc_cal_sel_t; - /** * Initialization parameters for rtc_clk_init */ @@ -110,7 +95,7 @@ typedef struct { */ #define RTC_CLK_CONFIG_DEFAULT() { \ .xtal_freq = CONFIG_XTAL_FREQ, \ - .cpu_freq_mhz = 90, \ + .cpu_freq_mhz = CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ, \ .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ .clk_rtc_clk_div = 0, \ @@ -137,16 +122,6 @@ void rtc_clk_init(rtc_clk_config_t cfg); */ soc_xtal_freq_t rtc_clk_xtal_freq_get(void); -/** - * @brief Update XTAL frequency - * - * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored - * after startup. - * - * @param xtal_freq New frequency value - */ -void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq); - /** * @brief Enable or disable 32 kHz XTAL oscillator * @param en true to enable, false to disable @@ -190,20 +165,6 @@ void rtc_clk_8m_enable(bool clk_8m_en); */ bool rtc_clk_8m_enabled(void); -/** - * @brief Enable or disable LP_PLL_CLK - * Note that to be able to use LP_PLL clock, besides turn on the power for LP_PLL, also needs to turn on the power for - * the LP_PLL clock source (either XTAL32K or RC32K). - * @param enable true to enable, false to disable - */ -void rtc_clk_lp_pll_enable(bool enable); - -/** - * @brief Select clock source for LP_PLL_CLK - * @param clk_src clock source (one of soc_lp_pll_clk_src_t values) - */ -void rtc_clk_lp_pll_src_set(soc_lp_pll_clk_src_t clk_src); - /** * @brief Select source for RTC_SLOW_CLK * @param clk_src clock source (one of soc_rtc_slow_clk_src_t values) @@ -310,26 +271,6 @@ void rtc_clk_cpu_freq_set_xtal(void); */ uint32_t rtc_clk_apb_freq_get(void); -/** - * @brief Clock calibration function used by rtc_clk_cal - * - * Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. - * This feature counts the number of XTAL clock cycles within a given number of - * RTC_SLOW_CLK cycles. - * - * Slow clock calibration feature has two modes of operation: one-off and cycling. - * In cycling mode (which is enabled by default on SoC reset), counting of XTAL - * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled - * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed - * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is - * enabled using TIMG_RTC_CALI_START bit. - * - * @param cal_clk which clock to calibrate - * @param slowclk_cycles number of slow clock cycles to count - * @return number of XTAL clock cycles within the given number of slow clock cycles - */ -uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); - /** * @brief Measure RTC slow clock's period, based on main XTAL frequency * @@ -348,7 +289,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); * @return average slow clock period in microseconds, Q13.19 fixed point format, * or 0 if calibration has timed out */ -uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); +uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk, uint32_t slow_clk_cycles); /** * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles diff --git a/components/esp_hw_support/port/esp32s31/pmu_init.c b/components/esp_hw_support/port/esp32s31/pmu_init.c index 11954e8c5a..a540ba0ec9 100644 --- a/components/esp_hw_support/port/esp32s31/pmu_init.c +++ b/components/esp_hw_support/port/esp32s31/pmu_init.c @@ -96,6 +96,7 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, pmu_hp_system_pa pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, mode, anlg->regulator0.slp_logic_dbias); pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, mode, anlg->regulator0.dbias); pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, mode, anlg->regulator0.xpd); + pmu_ll_hp_set_regulator_sleep_connect_enable(ctx->hal->dev, mode, anlg->regulator0.slp_connect_en); pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, mode, anlg->regulator1.drv_b); /* Default configuration of hp-system retention sub-system in active, modem @@ -203,9 +204,12 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx) void pmu_init(void) { + /* Peripheral reg i2c power up */ + regi2c_ctrl_ll_i2c_sar_periph_enable(); + pmu_hp_system_init_default(PMU_instance()); pmu_lp_system_init_default(PMU_instance()); pmu_power_domain_force_default(PMU_instance()); - regi2c_ctrl_ll_i2c_sar_periph_enable(); // TODO: IDF-14733 + WRITE_PERI_REG(PMU_POWER_PD_MEM_CNTL_REG, 0); } diff --git a/components/esp_hw_support/port/esp32s31/pmu_param.c b/components/esp_hw_support/port/esp32s31/pmu_param.c index 4a5a8bd05e..b284bd2081 100644 --- a/components/esp_hw_support/port/esp32s31/pmu_param.c +++ b/components/esp_hw_support/port/esp32s31/pmu_param.c @@ -38,9 +38,9 @@ ESP_HW_LOG_ATTR_TAG(TAG, "pmu_param"); .clk_power = { \ .i2c_iso_en = 0, \ .i2c_retention = 0, \ - .xpd_bb_i2c = 1, \ - .xpd_pll_i2c = 0xf, \ - .xpd_pll = 0xf \ + .xpd_bb_i2c = 0, \ + .xpd_pll_i2c = 0x3, \ + .xpd_pll = 0x3 \ }, \ .xtal = { \ .xpd_xtal = 1 \ @@ -55,16 +55,16 @@ ESP_HW_LOG_ATTR_TAG(TAG, "pmu_param"); .hp_mem_pd_en = 0, \ .modem_top_pd_en = 0, \ .hp_cnnt_pd_en = 0, \ - .hp_cpu_pd_en = 1, \ + .hp_cpu_pd_en = 0, \ .modem_pwr_pd_en = 0, \ .top_pd_en = 0 \ }, \ .clk_power = { \ - .i2c_iso_en = 0, \ - .i2c_retention = 0, \ - .xpd_bb_i2c = 1, \ - .xpd_pll_i2c = 0xf, \ - .xpd_pll = 0xf \ + .i2c_iso_en = 1, \ + .i2c_retention = 1, \ + .xpd_bb_i2c = 0, \ + .xpd_pll_i2c = 0x3, \ + .xpd_pll = 0x3 \ }, \ .xtal = { \ .xpd_xtal = 1 \ @@ -73,22 +73,22 @@ ESP_HW_LOG_ATTR_TAG(TAG, "pmu_param"); #define PMU_HP_SLEEP_POWER_CONFIG_DEFAULT() { \ .dig_power = { \ - .vdd_spi_pd_en = 1, \ - .pd_hp_alive_pd_en = 1, \ - .hp_mem_dslp = 1, \ + .vdd_spi_pd_en = 0, \ + .pd_hp_alive_pd_en = 0, \ + .hp_mem_dslp = 0, \ .hp_mem_pd_en = 0, \ - .modem_top_pd_en = 1, \ - .hp_cnnt_pd_en = 1, \ - .hp_cpu_pd_en = 1, \ + .modem_top_pd_en = 0, \ + .hp_cnnt_pd_en = 0, \ + .hp_cpu_pd_en = 0, \ .modem_pwr_pd_en = 0, \ - .top_pd_en = 1 \ + .top_pd_en = 0 \ }, \ .clk_power = { \ - .i2c_iso_en = 0, \ - .i2c_retention = 0, \ - .xpd_bb_i2c = 1, \ - .xpd_pll_i2c = 0xf, \ - .xpd_pll = 0xf \ + .i2c_iso_en = 1, \ + .i2c_retention = 1, \ + .xpd_bb_i2c = 0, \ + .xpd_pll_i2c = 0, \ + .xpd_pll = 0 \ }, \ .xtal = { \ .xpd_xtal = 0 \ @@ -186,13 +186,19 @@ const pmu_hp_system_clock_param_t * pmu_hp_system_clock_param_default(pmu_hp_mod } \ } +/** + * - hp_pad_hold_all: + * - when top off: must set to 1; + * - when top on: 0 if use pad; 1 if not use pad + * - dig_pad_slp_sel: must set to 1 when sleep + */ #define PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT() { \ .syscntl = { \ - .c_channel = 1, \ + .c_channel = 0, \ .uart_wakeup_en = 1, \ .lp_pad_hold_all = 0, \ - .hp_pad_hold_all = 0, \ - .dig_pad_slp_sel = 0, \ + .hp_pad_hold_all = 1, \ + .dig_pad_slp_sel = 1, \ .dig_pause_wdt = 1, \ .dig_cpu_stall = 1 \ } \ @@ -259,17 +265,17 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp .bias = { \ .xpd_bias = 0, \ .dbg_atten = 0x0, \ - .pd_cur = 0, \ - .bias_sleep = 0 \ + .pd_cur = 1, \ + .bias_sleep = 1 \ }, \ .regulator0 = { \ .slp_connect_en = 0, \ .slp_mem_xpd = 0, \ .slp_logic_xpd = 0, \ .xpd = 1, \ - .slp_mem_dbias = 1, \ + .slp_mem_dbias = 0, \ .slp_logic_dbias = 0, \ - .dbias = 1 \ + .dbias = 0 \ }, \ .regulator1 = { \ .drv_b = 0x0 \ @@ -357,8 +363,8 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm .peri_pd_en = 0, \ }, \ .clk_power = { \ - .xpd_xtal32k = 1, \ - .xpd_rc32k = 1, \ + .xpd_xtal32k = 0, \ + .xpd_rc32k = 0, \ .xpd_fosc = 1, \ .pd_osc = 0 \ } \ @@ -413,7 +419,7 @@ const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mod .slp_xpd = 0, \ .xpd = 1, \ .slp_dbias = 0, \ - .dbias = 12 \ + .dbias = 0 \ }, \ .regulator1 = { \ .drv_b = 0x0 \ diff --git a/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h b/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h index 92137f4d3c..71a473fa54 100644 --- a/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h @@ -16,8 +16,8 @@ extern "C" { #endif -#define HP_CALI_DBIAS_DEFAULT 28 -#define LP_CALI_DBIAS_DEFAULT 28 +#define HP_CALI_DBIAS_DEFAULT 24 +#define LP_CALI_DBIAS_DEFAULT 24 #define HP_CALI_DBIAS_SLP_1V1 22 #define LP_CALI_DBIAS_SLP_1V1 22 diff --git a/components/esp_hw_support/port/esp32s31/rtc_clk.c b/components/esp_hw_support/port/esp32s31/rtc_clk.c index 5d9e39e9d3..6f98ad29e6 100644 --- a/components/esp_hw_support/port/esp32s31/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s31/rtc_clk.c @@ -13,27 +13,28 @@ #include "esp32s31/rom/rtc.h" #include "soc/rtc.h" #include "esp_private/rtc_clk.h" -#include "esp_attr.h" #include "esp_hw_log.h" #include "esp_rom_sys.h" #include "hal/clk_tree_ll.h" -#include "hal/regi2c_ctrl_ll.h" -#include "hal/gpio_ll.h" -#include "soc/io_mux_reg.h" #include "esp_private/sleep_event.h" #include "esp_private/regi2c_ctrl.h" #include "esp_attr.h" static const char *TAG = "rtc_clk"; -// TODO: [ESP32S31] IDF-14678 - -// CPLL frequency option, in 360/400MHz. Zero if CPLL is not enabled. +// CPLL frequency option, in 320MHz. Zero if CPLL is not enabled. static int s_cur_cpll_freq = 0; -// MPLL frequency option, 400MHz. Zero if MPLL is not enabled. +// MPLL frequency option, 500MHz. Zero if MPLL is not enabled. static uint32_t s_cur_mpll_freq = 0; +#if !BOOTLOADER_BUILD +// Indicate whether the specific clock sources are acquired by the hp root clock (i.e. whether ref_cnt in esp_clk_tree.c is incremented by the hp root clock) +static bool s_is_cpll_acquired = (CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ == 80 || CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ == 160 || CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ == 320); +static bool s_is_pll_f240m_acquired = (CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ == 240); +#endif + + void rtc_clk_32k_enable(bool enable) { if (enable) { @@ -45,7 +46,7 @@ void rtc_clk_32k_enable(bool enable) void rtc_clk_32k_bootstrap(uint32_t cycle) { - /* No special bootstrapping needed for ESP32-P4, 'cycle' argument is to keep the signature + /* No special bootstrapping needed for ESP32-S31, 'cycle' argument is to keep the signature * same as for the ESP32. Just enable the XTAL here. */ (void)cycle; @@ -59,12 +60,22 @@ bool rtc_clk_32k_enabled(void) void rtc_clk_rc32k_enable(bool enable) { - // TODO: ["ESP32S31"] IDF-14678 + if (enable) { + clk_ll_rc32k_enable(); + esp_rom_delay_us(SOC_DELAY_RC32K_ENABLE); + } else { + clk_ll_rc32k_disable(); + } } void rtc_clk_8m_enable(bool clk_8m_en) { - // TODO: ["ESP32S31"] IDF-14678 + if (clk_8m_en) { + clk_ll_rc_fast_enable(); + esp_rom_delay_us(SOC_DELAY_RC_FAST_ENABLE); + } else { + clk_ll_rc_fast_disable(); + } } bool rtc_clk_8m_enabled(void) @@ -72,19 +83,23 @@ bool rtc_clk_8m_enabled(void) return clk_ll_rc_fast_is_enabled(); } -void rtc_clk_lp_pll_enable(bool enable) -{ - // TODO: ["ESP32S31"] IDF-14678 -} - -void rtc_clk_lp_pll_src_set(soc_lp_pll_clk_src_t clk_src) -{ - // TODO: ["ESP32S31"] IDF-14678 -} - void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src) { - // TODO: ["ESP32S31"] IDF-14678 + clk_ll_rtc_slow_set_src(clk_src); + esp_rom_delay_us(SOC_DELAY_RTC_SLOW_CLK_SWITCH); + // TODO: IDF-14645 +// #ifndef BOOTLOADER_BUILD +// if (clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { +// esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL32K, ESP_PD_OPTION_ON); +// } else { +// esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL32K, ESP_PD_OPTION_AUTO); +// } +// if (clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { +// esp_sleep_pd_config(ESP_PD_DOMAIN_RC32K, ESP_PD_OPTION_ON); +// } else { +// esp_sleep_pd_config(ESP_PD_DOMAIN_RC32K, ESP_PD_OPTION_AUTO); +// } +// #endif } soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void) @@ -94,18 +109,17 @@ soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void) uint32_t rtc_clk_slow_freq_get_hz(void) { - // TODO: ["ESP32S31"] IDF-14678 switch (rtc_clk_slow_src_get()) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX; case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX; - case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX; default: return 0; } } void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src) { - // TODO: ["ESP32S31"] IDF-14678 + clk_ll_rtc_fast_set_src(clk_src); + esp_rom_delay_us(SOC_DELAY_RTC_FAST_CLK_SWITCH); } soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void) @@ -113,23 +127,49 @@ soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void) return clk_ll_rtc_fast_get_src(); } +#if BOOTLOADER_BUILD static void rtc_clk_cpll_disable(void) { clk_ll_cpll_disable(); s_cur_cpll_freq = 0; } +static void rtc_clk_cpll_enable(void) +{ + clk_ll_cpll_enable(); +} +#endif + +static void rtc_clk_cpll_configure(soc_xtal_freq_t xtal_freq, int cpll_freq) +{ + /* Digital part */ + clk_ll_cpll_set_freq_mhz(cpll_freq, xtal_freq); + + /* Analog part */ + ANALOG_CLOCK_ENABLE(); + /* CPLL CALIBRATION START */ + clk_ll_cpll_calibration_start(); + clk_ll_cpll_set_config(cpll_freq, xtal_freq); + /* WAIT CALIBRATION DONE */ + while(!clk_ll_cpll_calibration_is_done()); + esp_rom_delay_us(10); // wait for true stop + /* CPLL CALIBRATION STOP */ + clk_ll_cpll_calibration_stop(); + ANALOG_CLOCK_DISABLE(); + + s_cur_cpll_freq = cpll_freq; +} + /** * Switch to use XTAL as the CPU clock source. * Must satisfy: cpu_freq = XTAL_FREQ / div. * Does not disable the PLL. * - * If to_default is set, then will configure CPU - MEM - SYS - APB frequencies back to power-on reset configuration (40 - 20 - 20 - 10) + * If to_default is set, then will configure CPU - MEM - SYS - APB frequencies back to power-on reset configuration (40 - 20 - 40/3 - 40/6) * If to_default is not set, then will configure to 40 - 40 - 40 - 40 */ static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div, bool to_default) { - // TODO: ["ESP32S31"] IDF-14678 // let f_cpu = f_mem = f_sys = f_apb uint32_t mem_divider = 1; uint32_t sys_divider = 1; @@ -137,24 +177,156 @@ static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div, bool if (to_default) { // f_cpu = 2 * f_mem = 2 * f_sys = 4 * f_apb mem_divider = 2; + sys_divider = 3; apb_divider = 2; } - // Update bit does not control CPU clock sel mux. Therefore, there will be a middle state during the switch (CPU falls) - // Since before the switch, the clock source is CPLL, there is divider value constraints. - // Setting the new dividers first is unguaranteed (hardware could automatically modify the real dividers) - // Therefore, we will switch cpu clock source first, and then set the desired dividers. - clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL); clk_ll_cpu_set_divider(div, 0, 0); clk_ll_mem_set_divider(mem_divider); clk_ll_sys_set_divider(sys_divider); clk_ll_apb_set_divider(apb_divider); + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL); clk_ll_bus_update(); esp_rom_set_cpu_ticks_per_us(cpu_freq); } +static void rtc_clk_cpu_freq_to_rc_fast(void) +{ + // let f_cpu = f_mem = f_sys = f_apb + clk_ll_cpu_set_divider(1, 0, 0); + clk_ll_mem_set_divider(1); + clk_ll_sys_set_divider(1); + clk_ll_apb_set_divider(1); + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST); + clk_ll_bus_update(); + esp_rom_set_cpu_ticks_per_us(20); +} + +/** + * Switch to PLL_F240M as cpu clock source. + * PLL must already be enabled. + * @param cpu_freq new CPU frequency + */ +static void rtc_clk_cpu_freq_to_pll_240_mhz(int cpu_freq_mhz) +{ + // f_hp_root = 240MHz + assert(cpu_freq_mhz == 240); + uint32_t cpu_divider = CLK_LL_PLL_240M_FREQ_MHZ / cpu_freq_mhz; + clk_ll_cpu_set_divider(cpu_divider, 0, 0); + clk_ll_mem_set_divider(2); // 120MHz + clk_ll_sys_set_divider(3); // 80MHz + clk_ll_apb_set_divider(2); // 40MHz + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL_F240M); + clk_ll_bus_update(); + esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz); +} + +/** + * Switch to one of CPLL-based frequencies. Current frequency can be XTAL or CPLL. + * CPLL must already be enabled. + * @param cpu_freq new CPU frequency + */ +static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t *div) +{ + /** + * Constraint: MEM_CLK <= 160MHz, SYS_CLK <= (320/3)MHz, APB_CLK <= (320/6)MHz + * This implies that when clock source is CPLL, + * If cpu_divider < 2, mem_divider must be larger or equal to 2, sys_divider must be larger or equal to 3 + * If cpu_divider < 2, sys_divider = 3, apb_divider must be larger or equal to 2 + * + * Current available configurations: + * CPLL -> CPU_CLK -> MEM_CLK + * -> SYS_CLK -> APB_CLK + * 320 div1 320 div2 160 + * div4 80 div2 40 + * 320 div2 160 div1 160 + * div2 80 div2 40 + * 320 div4 80 div1 80 + * div1 80 div2 40 + */ + uint32_t mem_divider = 1; + uint32_t sys_divider = 1; + uint32_t apb_divider = 1; + switch (cpu_freq_mhz) { + case 320: + mem_divider = 2; + sys_divider = 4; + apb_divider = 2; + break; + case 160: + mem_divider = 1; + sys_divider = 2; + apb_divider = 2; + break; + case 80: + mem_divider = 1; + sys_divider = 1; + apb_divider = 2; + break; + default: + // Unsupported configuration + // This is dangerous to modify dividers. Hardware could automatically correct the divider, and it won't be + // reflected to the registers. Therefore, you won't even be able to calculate out the real mem_clk, apb_clk freq. + // To avoid such case, we will strictly do abort here. + abort(); + } + clk_ll_cpu_set_divider(div->integer, div->numerator, div->denominator); + clk_ll_mem_set_divider(mem_divider); + clk_ll_sys_set_divider(sys_divider); + clk_ll_apb_set_divider(apb_divider); + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_CPLL); + clk_ll_bus_update(); + esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz); +} + bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config) { - // TODO: ["ESP32S31"] IDF-14678 + uint32_t source_freq_mhz; + soc_cpu_clk_src_t source; + hal_utils_clk_div_t divider = {0}; // divider = freq of HP_ROOT_CLK / freq of CPU_CLK + uint32_t real_freq_mhz; + + // Keep default CPLL at 320MHz + uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get(); + if (freq_mhz <= xtal_freq && freq_mhz != 0) { + divider.integer = xtal_freq / freq_mhz; + real_freq_mhz = (xtal_freq + divider.integer / 2) / divider.integer; /* round */ + if (real_freq_mhz != freq_mhz) { + // no suitable divider + return false; + } + source_freq_mhz = xtal_freq; + source = SOC_CPU_CLK_SRC_XTAL; + } else if (freq_mhz == 80) { + real_freq_mhz = freq_mhz; + source = SOC_CPU_CLK_SRC_CPLL; + source_freq_mhz = CLK_LL_PLL_320M_FREQ_MHZ; + divider.integer = 4; + } else if (freq_mhz == 160) { + real_freq_mhz = freq_mhz; + source = SOC_CPU_CLK_SRC_CPLL; + source_freq_mhz = CLK_LL_PLL_320M_FREQ_MHZ; + divider.integer = 2; + } else if (freq_mhz == 240) { + real_freq_mhz = freq_mhz; + source = SOC_CPU_CLK_SRC_PLL_F240M; + source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ; + divider.integer = 1; + } else if (freq_mhz == 320) { + real_freq_mhz = freq_mhz; + source = SOC_CPU_CLK_SRC_CPLL; + source_freq_mhz = CLK_LL_PLL_320M_FREQ_MHZ; + divider.integer = 1; + } else { + // unsupported frequency + return false; + } + + *out_config = (rtc_cpu_freq_config_t) { + .source = source, + .div = divider, + .source_freq_mhz = source_freq_mhz, + .freq_mhz = real_freq_mhz + }; return true; } @@ -162,61 +334,179 @@ __attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id) { } +static void rtc_clk_cpu_src_clk_enable(soc_cpu_clk_src_t new_src, uint32_t new_src_freq_mhz) +{ + if (new_src == SOC_CPU_CLK_SRC_CPLL) { + bool truly_enabled = false; +#if BOOTLOADER_BUILD + rtc_clk_cpll_enable(); + truly_enabled = true; +#else + if (!s_is_cpll_acquired) { + truly_enabled = esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_CPLL, true); + s_is_cpll_acquired = true; + } +#endif + if (truly_enabled || (s_cur_cpll_freq != new_src_freq_mhz)) { + rtc_clk_cpll_configure(rtc_clk_xtal_freq_get(), new_src_freq_mhz); + } + } else if (new_src == SOC_CPU_CLK_SRC_PLL_F240M) { +#if !BOOTLOADER_BUILD + if (!s_is_pll_f240m_acquired) { + esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, true); + s_is_pll_f240m_acquired = true; + } +#endif + } +} + +static void rtc_clk_cpu_src_clk_disable(soc_cpu_clk_src_t old_src) +{ + if (old_src == SOC_CPU_CLK_SRC_CPLL) { +#if BOOTLOADER_BUILD + rtc_clk_cpll_disable(); +#else + assert(s_is_cpll_acquired); + bool truly_disabled = esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_CPLL, false); + s_is_cpll_acquired = false; + if (truly_disabled) { + s_cur_cpll_freq = 0; + } +#endif + } else if (old_src == SOC_CPU_CLK_SRC_PLL_F240M) { +#if !BOOTLOADER_BUILD + assert(s_is_pll_f240m_acquired); + s_is_pll_f240m_acquired = false; + esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, false); +#endif + } +} + void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) { - // TODO: ["ESP32S31"] IDF-14678 + soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src(); + if (old_cpu_clk_src != config->source) { + rtc_clk_cpu_src_clk_enable(config->source, config->source_freq_mhz); + } + + if (config->source == SOC_CPU_CLK_SRC_XTAL) { + rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div.integer, false); + } else if (config->source == SOC_CPU_CLK_SRC_CPLL) { + rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START); + rtc_clk_cpu_freq_to_cpll_mhz(config->freq_mhz, (hal_utils_clk_div_t *)&config->div); + rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP); + } else if (config->source == SOC_CPU_CLK_SRC_PLL_F240M) { + rtc_clk_cpu_freq_to_pll_240_mhz(config->freq_mhz); + } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { + rtc_clk_cpu_freq_to_rc_fast(); + } + + if (old_cpu_clk_src != config->source) { + rtc_clk_cpu_src_clk_disable(old_cpu_clk_src); + } } static uint32_t rtc_clk_hp_root_get_freq_mhz(soc_cpu_clk_src_t clk_src) { uint32_t source_freq_mhz = 0; - // TODO: ["ESP32S31"] IDF-14678 + switch (clk_src) { + case SOC_CPU_CLK_SRC_XTAL: + source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get(); + break; + case SOC_CPU_CLK_SRC_CPLL: + source_freq_mhz = clk_ll_cpll_get_freq_mhz((uint32_t)rtc_clk_xtal_freq_get()); + break; + case SOC_CPU_CLK_SRC_RC_FAST: + source_freq_mhz = 20; + break; + case SOC_CPU_CLK_SRC_PLL_F240M: + source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ; + break; + default: + // Unknown HP_ROOT clock source + ESP_HW_LOGE(TAG, "Invalid HP_ROOT_CLK"); + break; + } return source_freq_mhz; } void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) { - // TODO: ["ESP32S31"] IDF-14678 + soc_cpu_clk_src_t source = clk_ll_cpu_get_src(); + uint32_t source_freq_mhz = rtc_clk_hp_root_get_freq_mhz(source); + if (source_freq_mhz == 0) { + // unsupported frequency configuration + abort(); + } + hal_utils_clk_div_t div = {0}; // div = freq of SOC_ROOT_CLK / freq of CPU_CLK + clk_ll_cpu_get_divider(&div.integer, &div.numerator, &div.denominator); + if (div.denominator == 0) { + div.denominator = 1; + div.numerator = 0; + } + uint32_t freq_mhz = source_freq_mhz * div.denominator / (div.integer * div.denominator + div.numerator); + *out_config = (rtc_cpu_freq_config_t) { + .source = source, + .source_freq_mhz = source_freq_mhz, + .div = div, + .freq_mhz = freq_mhz + }; } void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) { - // TODO: ["ESP32S31"] IDF-14678 + if (config->source == SOC_CPU_CLK_SRC_XTAL) { + rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div.integer, false); + } else if (config->source == SOC_CPU_CLK_SRC_CPLL && + s_cur_cpll_freq == config->source_freq_mhz) { + rtc_clk_cpu_freq_to_cpll_mhz(config->freq_mhz, (hal_utils_clk_div_t *)&config->div); + } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { + rtc_clk_cpu_freq_to_rc_fast(); + } else if (config->source == SOC_CPU_CLK_SRC_PLL_F240M +#if !BOOTLOADER_BUILD + && s_is_pll_f240m_acquired +#endif + ) { + rtc_clk_cpu_freq_to_pll_240_mhz(config->freq_mhz); + } else { + /* fallback */ + rtc_clk_cpu_freq_set_config(config); + } } void rtc_clk_cpu_freq_set_xtal(void) { + soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src(); int freq_mhz = (int)rtc_clk_xtal_freq_get(); rtc_clk_cpu_freq_to_xtal(freq_mhz, 1, false); - rtc_clk_cpll_disable(); + if (old_cpu_clk_src != SOC_CPU_CLK_SRC_XTAL) { + rtc_clk_cpu_src_clk_disable(old_cpu_clk_src); + } } FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void) { - // TODO: ["ESP32S31"] IDF-14678 + int freq_mhz = (int)rtc_clk_xtal_freq_get(); + + rtc_clk_cpu_freq_to_xtal(freq_mhz, 1, true); } void rtc_clk_cpu_freq_set_xtal_for_sleep(void) { - // TODO: ["ESP32S31"] IDF-14678 + int freq_mhz = (int)rtc_clk_xtal_freq_get(); + + rtc_clk_cpu_freq_to_xtal(freq_mhz, 1, false); + s_cur_cpll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep } -soc_xtal_freq_t rtc_clk_xtal_freq_get(void) +FORCE_IRAM_ATTR soc_xtal_freq_t rtc_clk_xtal_freq_get(void) { uint32_t xtal_freq_mhz = clk_ll_xtal_get_freq_mhz(); - if (xtal_freq_mhz == 0) { - ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz"); - return SOC_XTAL_FREQ_40M; - } + assert(xtal_freq_mhz == SOC_XTAL_FREQ_40M); return (soc_xtal_freq_t)xtal_freq_mhz; } -void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq) -{ - // clk_ll_xtal_store_freq_mhz(xtal_freq); -} - uint32_t rtc_clk_apb_freq_get(void) { soc_cpu_clk_src_t source = clk_ll_cpu_get_src(); @@ -228,14 +518,17 @@ uint32_t rtc_clk_apb_freq_get(void) numerator = 0; } uint32_t cpu_freq_hz = source_freq_mhz * MHZ * denominator / (integer * denominator + numerator); - uint32_t mem_freq_hz = cpu_freq_hz / clk_ll_mem_get_divider(); - uint32_t sys_freq_hz = mem_freq_hz / clk_ll_sys_get_divider(); + uint32_t sys_freq_hz = cpu_freq_hz / clk_ll_sys_get_divider(); return sys_freq_hz / clk_ll_apb_get_divider(); } void rtc_clk_apll_enable(bool enable) { - // TODO: ["ESP32S31"] IDF-14678 + if (enable) { + clk_ll_apll_enable(); + } else { + clk_ll_apll_disable(); + } } uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm0, uint32_t *_sdm1, uint32_t *_sdm2) @@ -299,17 +592,19 @@ uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2) { - // TODO: ["ESP32S31"] IDF-14678 + // TODO: IDF-14771, IDF-14750 } void rtc_dig_clk8m_enable(void) { - // TODO: ["ESP32S31"] IDF-14678 + clk_ll_rc_fast_digi_enable(); + esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH); } void rtc_dig_clk8m_disable(void) { - // TODO: ["ESP32S31"] IDF-14678 + clk_ll_rc_fast_digi_disable(); + esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH); } bool rtc_dig_8m_enabled(void) @@ -331,7 +626,6 @@ IRAM_ATTR void rtc_clk_mpll_enable(void) void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq, bool thread_safe) { - /* Analog part */ if (thread_safe) { _regi2c_ctrl_ll_master_enable_clock(true); } else { diff --git a/components/esp_hw_support/port/esp32s31/rtc_clk_init.c b/components/esp_hw_support/port/esp32s31/rtc_clk_init.c new file mode 100644 index 0000000000..0e14f89fbf --- /dev/null +++ b/components/esp_hw_support/port/esp32s31/rtc_clk_init.c @@ -0,0 +1,76 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include "esp32s31/rom/ets_sys.h" +#include "esp32s31/rom/rtc.h" +#include "soc/rtc.h" +#include "esp_cpu.h" +#include "regi2c_ctrl.h" +#include "soc/regi2c_dig_reg.h" +#include "soc/lp_clkrst_reg.h" +#include "soc/lp_system_reg.h" +#include "soc/pmu_reg.h" +#include "soc/chip_revision.h" +#include "esp_hw_log.h" +#include "sdkconfig.h" +#include "esp_rom_serial_output.h" +#include "esp_private/esp_pmu.h" +#include "hal/clk_tree_ll.h" +#include "hal/efuse_hal.h" + +ESP_HW_LOG_ATTR_TAG(TAG, "rtc_clk_init"); + +void rtc_clk_init(rtc_clk_config_t cfg) +{ + rtc_cpu_freq_config_t old_config, new_config; + + /* Set tuning parameters for RC_FAST, RC_SLOW, and RC32K clocks. + * Note: this doesn't attempt to set the clocks to precise frequencies. + * Instead, we calibrate these clocks against XTAL frequency later, when necessary. + * - SCK_DCAP value controls tuning of RC_SLOW clock. + * The higher the value of DCAP is, the lower is the frequency. + * - CK8M_DFREQ value controls tuning of RC_FAST clock. + * CLK_8M_DFREQ constant gives the best temperature characteristics. + */ + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, cfg.slow_clk_dcap); + + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0); + + // XTAL freq determined by efuse, and can be directly informed from register field LP_AONCLKRST_CLK_XTAL_FREQ + + // No need to wait UART0 TX idle since its default clock source is XTAL, should not be affected by system clock configuration + + /* Set CPU frequency */ + rtc_clk_cpu_freq_get_config(&old_config); + uint32_t freq_before = old_config.freq_mhz; + bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config); + if (!res) { + ESP_HW_LOGE(TAG, "invalid CPU frequency value"); + abort(); + } + rtc_clk_cpu_freq_set_config(&new_config); + + /* Re-calculate the ccount to make time calculation correct. */ + esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); + + /* Slow & fast clocks setup */ + // We will not power off RC_FAST in bootloader stage even if it is not being used as any + // cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage. + bool need_rc_fast_en = true; + if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { + rtc_clk_32k_enable(true); + } + rtc_clk_8m_enable(need_rc_fast_en); + rtc_clk_fast_src_set(cfg.fast_clk_src); + rtc_clk_slow_src_set(cfg.slow_clk_src); +} diff --git a/components/esp_hw_support/port/esp32s31/rtc_time.c b/components/esp_hw_support/port/esp32s31/rtc_time.c index 76331a7b18..6c60a93f95 100644 --- a/components/esp_hw_support/port/esp32s31/rtc_time.c +++ b/components/esp_hw_support/port/esp32s31/rtc_time.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,14 +10,12 @@ #include "soc/rtc.h" #include "hal/rtc_timer_hal.h" #include "hal/clk_tree_ll.h" -// #include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "soc/hp_sys_clkrst_reg.h" #include "soc/timer_group_reg.h" #include "esp_rom_sys.h" #include "esp_private/periph_ctrl.h" -// TODO: [ESP32S31] IDF-14678 - __attribute__((unused)) static const char *TAG = "rtc_time"; /* Calibration of clock frequency is performed using a special feature of TIMG0. @@ -25,46 +23,57 @@ __attribute__((unused)) static const char *TAG = "rtc_time"; * clock cycles. */ -#define CLK_CAL_TIMEOUT_THRES(cal_clk, cycles) ((cal_clk == RTC_CAL_RC32K || cal_clk == RTC_CAL_32K_XTAL) ? (cycles << 12) : (cycles << 10)) +#define CLK_CAL_TIMEOUT_THRES(cal_clk_sel, cycles) ((cal_clk_sel == CLK_CAL_32K_XTAL) ? (cycles << 12) : (cycles << 10)) // Calibration can only be performed on relatively slow speed clock signal. Therefore, for high-speed clocks, // calibration is performed on their DIV_CLKs. The divider is configurable. We set: -#define CLK_CAL_DIV_VAL(cal_clk) \ - ((cal_clk == RTC_CAL_RC_SLOW || cal_clk == RTC_CAL_RC32K || cal_clk == RTC_CAL_32K_XTAL) ? 1 : \ - (cal_clk == RTC_CAL_LP_PLL) ? 25 : \ - (cal_clk == RTC_CAL_RC_FAST) ? 50 : \ - (cal_clk == RTC_CAL_APLL) ? 200 : \ +#define CLK_CAL_DIV_VAL(cal_clk_sel) \ + ((cal_clk_sel == CLK_CAL_RC_SLOW || cal_clk_sel == CLK_CAL_32K_XTAL) ? 1 : \ + (cal_clk_sel == CLK_CAL_RC_FAST) ? 50 : \ + (cal_clk_sel == CLK_CAL_APLL || cal_clk_sel == CLK_CAL_AHB || cal_clk_sel == CLK_CAL_ROM) ? 200 : \ + (cal_clk_sel == CLK_CAL_XTAL || cal_clk_sel == CLK_CAL_APB) ? 100 : \ + (cal_clk_sel == CLK_CAL_CORE0 || cal_clk_sel == CLK_CAL_CORE1) ? 1000 : \ 4000) // CLK_CAL_FREQ_APPROX = CLK_FREQ_APPROX / CLK_CAL_DIV_VAL -#define CLK_CAL_FREQ_APPROX(cal_clk) \ - ((cal_clk == RTC_CAL_MPLL) ? (CLK_LL_PLL_500M_FREQ_MHZ * MHZ / 4000) : \ - (cal_clk == RTC_CAL_SPLL) ? (CLK_LL_PLL_480M_FREQ_MHZ * MHZ / 4000) : \ - (cal_clk == RTC_CAL_CPLL) ? (CLK_LL_PLL_400M_FREQ_MHZ * MHZ / 4000) : \ - (cal_clk == RTC_CAL_APLL) ? (105 * MHZ / 200) : \ - (cal_clk == RTC_CAL_SDIO_PLL0 || cal_clk == RTC_CAL_SDIO_PLL1 || cal_clk == RTC_CAL_SDIO_PLL2) ? (200 * MHZ / 4000) : \ - (cal_clk == RTC_CAL_RC_FAST) ? (SOC_CLK_RC_FAST_FREQ_APPROX / 50) : \ - (cal_clk == RTC_CAL_RC_SLOW) ? (SOC_CLK_RC_SLOW_FREQ_APPROX) : \ - (cal_clk == RTC_CAL_RC32K) ? (SOC_CLK_RC32K_FREQ_APPROX) : \ - (cal_clk == RTC_CAL_32K_XTAL) ? (SOC_CLK_XTAL32K_FREQ_APPROX) : \ - (cal_clk == RTC_CAL_LP_PLL) ? (CLK_LL_PLL_8M_FREQ_MHZ * MHZ / 25) : \ +#define CLK_CAL_FREQ_APPROX(cal_clk_sel) \ + ((cal_clk_sel == CLK_CAL_MPLL) ? (CLK_LL_PLL_500M_FREQ_MHZ * MHZ / 4000) : \ + (cal_clk_sel == CLK_CAL_BBPLL) ? (CLK_LL_PLL_480M_FREQ_MHZ * MHZ / 4000) : \ + (cal_clk_sel == CLK_CAL_CPLL) ? (CLK_LL_PLL_320M_FREQ_MHZ * MHZ / 4000) : \ + (cal_clk_sel == CLK_CAL_APLL) ? (105 * MHZ / 200) : \ + (cal_clk_sel == CLK_CAL_AHB || cal_clk_sel == CLK_CAL_ROM) ? (100 * MHZ / 200) : \ + (cal_clk_sel == CLK_CAL_RC_FAST) ? (SOC_CLK_RC_FAST_FREQ_APPROX / 50) : \ + (cal_clk_sel == CLK_CAL_RC_SLOW) ? (SOC_CLK_RC_SLOW_FREQ_APPROX) : \ + (cal_clk_sel == CLK_CAL_32K_XTAL) ? (SOC_CLK_XTAL32K_FREQ_APPROX) : \ + (cal_clk_sel == CLK_CAL_XTAL || cal_clk_sel == CLK_CAL_APB) ? (40 * MHZ / 100) : \ + (cal_clk_sel == CLK_CAL_CORE0 || cal_clk_sel == CLK_CAL_CORE1) ? (CLK_LL_PLL_320M_FREQ_MHZ * MHZ / 1000) : \ 0) -uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) +/** + * @brief Clock frequency calculation function used by rtc_clk_cal + * + * Calculation of clock frequency is performed using a special feature of TIMG0. + * This feature counts the number of XTAL clock cycles within a given number of + * clock cycles. + * + * @param cal_clk_sel which clock to calculate frequency + * @param slowclk_cycles number of slow clock cycles to count + * @return number of XTAL clock cycles within the given number of slow clock cycles + */ +uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles) { assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V); - if (cal_clk == RTC_CAL_RTC_MUX) { + if (cal_clk_sel == CLK_CAL_RTC_SLOW) { soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) { - cal_clk = RTC_CAL_RC_SLOW; + cal_clk_sel = CLK_CAL_RC_SLOW; } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { - cal_clk = RTC_CAL_RC32K; + cal_clk_sel = CLK_CAL_32K_XTAL; } } - if (cal_clk < 0 || cal_clk >= RTC_CAL_INVALID_CLK) { + + if (cal_clk_sel < 0) { ESP_EARLY_LOGE(TAG, "clock not supported to be calibrated"); return 0; } @@ -74,13 +83,13 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) // Only enable if originally was disabled, and set back to the disable state after calibration is done // If the clock is already on, then do nothing bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); - if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { + if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) { clk_ll_xtal32k_digi_enable(); } bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled(); - if (cal_clk == RTC_CAL_RC_FAST) { + if (cal_clk_sel == CLK_CAL_RC_FAST) { if (!rc_fast_enabled) { rtc_clk_8m_enable(true); } @@ -89,17 +98,6 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) } } - bool rc32k_enabled = clk_ll_rc32k_is_enabled(); - bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled(); - if (cal_clk == RTC_CAL_RC32K) { - if (!rc32k_enabled) { - rtc_clk_rc32k_enable(true); - } - if (!dig_rc32k_enabled) { - clk_ll_rc32k_digi_enable(); - } - } - /* There may be another calibration process already running during we call this function, * so we should wait the last process is done. */ @@ -114,16 +112,16 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) } /* Prepare calibration */ - REG_SET_FIELD(HP_SYS_CLKRST_TIMERGRP0_TGRT_CTRL0_REG, HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL, cal_clk); - uint32_t clk_cal_divider = CLK_CAL_DIV_VAL(cal_clk); - REG_SET_FIELD(HP_SYS_CLKRST_TIMERGRP0_TGRT_CTRL0_REG, HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM, clk_cal_divider - 1); + clk_ll_freq_calulation_set_target(cal_clk_sel); + uint32_t clk_cal_divider = CLK_CAL_DIV_VAL(cal_clk_sel); + clk_ll_freq_calculation_set_divider(clk_cal_divider); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); /* Figure out how long to wait for calibration to finish */ /* Set timeout reg and expect time delay*/ - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk, slowclk_cycles)); - uint32_t expected_freq = CLK_CAL_FREQ_APPROX(cal_clk); + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk_sel, slowclk_cycles)); + uint32_t expected_freq = CLK_CAL_FREQ_APPROX(cal_clk_sel); assert(expected_freq); uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ @@ -145,14 +143,14 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) } } CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); - CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_TIMERGRP0_TGRT_CTRL0_REG, HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_M); + clk_ll_freq_calculation_set_divider(1); /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ - if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { + if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) { clk_ll_xtal32k_digi_disable(); } - if (cal_clk == RTC_CAL_RC_FAST) { + if (cal_clk_sel == CLK_CAL_RC_FAST) { if (!dig_rc_fast_enabled) { rtc_dig_clk8m_disable(); } @@ -161,15 +159,6 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) } } - if (cal_clk == RTC_CAL_RC32K) { - if (!dig_rc32k_enabled) { - clk_ll_rc32k_digi_disable(); - } - if (!rc32k_enabled) { - rtc_clk_rc32k_enable(false); - } - } - return cal_val; } @@ -180,14 +169,14 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); } -uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) +uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles) { - slowclk_cycles /= (cal_clk == RTC_CAL_RTC_MUX) ? 1 : CLK_CAL_DIV_VAL(cal_clk); + slowclk_cycles /= (cal_clk_sel == CLK_CAL_RTC_SLOW) ? 1 : CLK_CAL_DIV_VAL(cal_clk_sel); assert(slowclk_cycles); soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); - uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); + uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles); - if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { + if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { return 0; } @@ -230,5 +219,15 @@ uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal __attribute__((constructor)) static void enable_timer_group0_for_calibration(void) { - // TODO: ["ESP32S31"] IDF-14871 +#ifndef BOOTLOADER_BUILD + PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) { + if (ref_count == 0) { + timg_ll_enable_bus_clock(0, true); + timg_ll_reset_register(0); + } + } +#else + _timg_ll_enable_bus_clock(0, true); + _timg_ll_reset_register(0); +#endif } diff --git a/components/esp_hw_support/test_apps/rtc_clk/README.md b/components/esp_hw_support/test_apps/rtc_clk/README.md index 44f3780f1d..d76348d52c 100644 --- a/components/esp_hw_support/test_apps/rtc_clk/README.md +++ b/components/esp_hw_support/test_apps/rtc_clk/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 815d368453..5bdf6c7757 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -306,6 +306,13 @@ else() # Regular app build if(CONFIG_ESP32C61_REV_MIN_FULL GREATER_EQUAL 101) rom_linker_script("eco4") endif() + elseif(target STREQUAL "esp32s31") + # esp32s31.rom.api.ld has been split to several lds by components. + # esp32s31.rom.api.ld is still reserved to map the APIs + rom_linker_script("phy") + rom_linker_script("coexist") + rom_linker_script("net80211") + rom_linker_script("pp") endif() diff --git a/components/esp_rom/esp32s31/include/esp32s31/rom/rtc.h b/components/esp_rom/esp32s31/include/esp32s31/rom/rtc.h index 778061b948..b3d74f4c08 100644 --- a/components/esp_rom/esp32s31/include/esp32s31/rom/rtc.h +++ b/components/esp_rom/esp32s31/include/esp32s31/rom/rtc.h @@ -42,7 +42,7 @@ extern "C" { * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value * RTC_CNTL_STORE2_REG Boot time, low word * RTC_CNTL_STORE3_REG Boot time, high word - * RTC_CNTL_STORE4_REG External XTAL frequency + * RTC_CNTL_STORE4_REG Status of whether to disable LOG from ROM at bit[0] * RTC_CNTL_STORE5_REG FAST_RTC_MEMORY_LENGTH * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC @@ -52,7 +52,6 @@ extern "C" { #define RTC_SLOW_CLK_CAL_REG LP_SYSTEM_REG_LP_STORE1_REG #define RTC_BOOT_TIME_LOW_REG LP_SYSTEM_REG_LP_STORE2_REG #define RTC_BOOT_TIME_HIGH_REG LP_SYSTEM_REG_LP_STORE3_REG -#define RTC_XTAL_FREQ_REG LP_SYSTEM_REG_LP_STORE4_REG #define RTC_ENTRY_LENGTH_REG LP_SYSTEM_REG_LP_STORE5_REG #define RTC_ENTRY_ADDR_REG LP_SYSTEM_REG_LP_STORE6_REG #define RTC_RESET_CAUSE_REG LP_SYSTEM_REG_LP_STORE6_REG diff --git a/components/esp_system/ld/esp32s31/memory.ld.in b/components/esp_system/ld/esp32s31/memory.ld.in index ce06cdc199..866f4c6f93 100644 --- a/components/esp_system/ld/esp32s31/memory.ld.in +++ b/components/esp_system/ld/esp32s31/memory.ld.in @@ -66,6 +66,7 @@ MEMORY * lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667 */ /* TODO: ["ESP32S31"] IDF-14640 */ + lp_ram_seg(RW) : org = 0x2E000000, len = 0x8000 - RESERVE_RTC_MEM /* We reduced the size of lp_ram_seg by RESERVE_RTC_MEM value. It reserves the amount of LP memory that we use for this memory segment. @@ -76,6 +77,7 @@ MEMORY This segment is placed at the beginning of LP RAM, as the end of LP RAM is occupied by LP ROM stack/data */ /* TODO: ["ESP32S31"] IDF-14640 */ + lp_reserved_seg(RW) : org = 0x2E000000 + 0x8000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM /* PSRAM seg */ extern_ram_seg(RWX) : org = 0x50000000, len = IDROM_SEG_SIZE @@ -94,6 +96,12 @@ REGION_ALIAS("dram_seg", sram_seg); */ /* TODO: ["ESP32S31"] IDF-14640 */ +REGION_ALIAS("rtc_text_seg", lp_ram_seg); +REGION_ALIAS("rtc_data_seg", lp_ram_seg); +REGION_ALIAS("rtc_slow_seg", lp_ram_seg); +REGION_ALIAS("rtc_force_fast_seg", lp_ram_seg); +REGION_ALIAS("rtc_force_slow_seg", lp_ram_seg); +REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg ); #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS REGION_ALIAS("flash_text_seg", irom_seg); diff --git a/components/esp_system/ld/esp32s31/sections.ld.in b/components/esp_system/ld/esp32s31/sections.ld.in index 4846cf4694..ed29eb2150 100644 --- a/components/esp_system/ld/esp32s31/sections.ld.in +++ b/components/esp_system/ld/esp32s31/sections.ld.in @@ -12,6 +12,8 @@ SECTIONS /** * RTC memory should be implemented here TODO: [ESP32S31] IDF-14640 */ +#include "ld.rtc.sections" + #include "ld.iram.sections" #include "ld.dram.sections" diff --git a/components/esp_system/port/soc/esp32h4/clk.c b/components/esp_system/port/soc/esp32h4/clk.c index b3c3af9966..d6a9784d96 100644 --- a/components/esp_system/port/soc/esp32h4/clk.c +++ b/components/esp_system/port/soc/esp32h4/clk.c @@ -50,7 +50,6 @@ __attribute__((weak)) void esp_rtc_init(void) __attribute__((weak)) void esp_clk_init(void) { #if !CONFIG_IDF_ENV_FPGA - pmu_init(); assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_32M); rtc_clk_8m_enable(true); diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c index bc5c51f050..702a6b1178 100644 --- a/components/esp_system/port/soc/esp32p4/clk.c +++ b/components/esp_system/port/soc/esp32p4/clk.c @@ -138,11 +138,8 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) * will time out, returning 0. */ ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up"); - soc_clk_freq_calculation_src_t cal_sel = -1; - if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - rtc_clk_32k_enable(true); - cal_sel = CLK_CAL_32K_XTAL; - } + rtc_clk_32k_enable(true); + soc_clk_freq_calculation_src_t cal_sel = CLK_CAL_32K_XTAL; // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. if (SLOW_CLK_CAL_CYCLES > 0) { cal_val = rtc_clk_cal(cal_sel, SLOW_CLK_CAL_CYCLES); diff --git a/components/esp_system/port/soc/esp32s31/Kconfig.cpu b/components/esp_system/port/soc/esp32s31/Kconfig.cpu index 6c1ac26398..152ab30cb6 100644 --- a/components/esp_system/port/soc/esp32s31/Kconfig.cpu +++ b/components/esp_system/port/soc/esp32s31/Kconfig.cpu @@ -1,14 +1,21 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ prompt "CPU frequency" default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA || ESP_BRINGUP_BYPASS_CPU_CLK_SETTING + default ESP_DEFAULT_CPU_FREQ_MHZ_320 help CPU frequency to be set on application startup. config ESP_DEFAULT_CPU_FREQ_MHZ_40 bool "40 MHz" depends on IDF_ENV_FPGA || ESP_BRINGUP_BYPASS_CPU_CLK_SETTING + config ESP_DEFAULT_CPU_FREQ_MHZ_240 + bool "240 MHz" + config ESP_DEFAULT_CPU_FREQ_MHZ_320 + bool "320 MHz" endchoice config ESP_DEFAULT_CPU_FREQ_MHZ int default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40 + default 240 if ESP_DEFAULT_CPU_FREQ_MHZ_240 + default 320 if ESP_DEFAULT_CPU_FREQ_MHZ_320 diff --git a/components/esp_system/port/soc/esp32s31/clk.c b/components/esp_system/port/soc/esp32s31/clk.c index ea09bb9733..3e478e55ea 100644 --- a/components/esp_system/port/soc/esp32s31/clk.c +++ b/components/esp_system/port/soc/esp32s31/clk.c @@ -18,17 +18,7 @@ #include "soc/soc.h" #include "soc/rtc.h" #include "soc/rtc_periph.h" -#include "soc/i2s_reg.h" -#include "soc/hp_sys_clkrst_reg.h" #include "esp_cpu.h" -#include "soc/hp_sys_clkrst_reg.h" -#include "soc/lp_clkrst_reg.h" -#include "soc/lp_system_reg.h" -#include "soc/spi_mem_c_reg.h" -#include "soc/spi_mem_s_reg.h" -#include "soc/usb_serial_jtag_reg.h" -#include "soc/hp_alive_sys_reg.h" -#include "hal/uart_ll.h" #if SOC_WDT_SUPPORTED || SOC_RTC_WDT_SUPPORTED #include "hal/wdt_hal.h" #endif @@ -39,22 +29,21 @@ #include "esp_rom_serial_output.h" #include "esp_rom_sys.h" -// TODO: ["ESP32S31"] IDF-14733 - /* Number of cycles to wait from the 32k XTAL oscillator to consider it running. * Larger values increase startup delay. Smaller values may cause false positive * detection (i.e. oscillator runs for a few cycles and then stops). */ +#define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES #define MHZ (1000000) static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src); -static const char *TAG = "clk"; +ESP_LOG_ATTR_TAG(TAG, "clk"); -void IRAM_ATTR esp_rtc_init(void) +__attribute__((weak)) void IRAM_ATTR esp_rtc_init(void) { -#if SOC_PMU_SUPPORTED +#if SOC_PMU_SUPPORTED && !CONFIG_IDF_ENV_FPGA pmu_init(); #endif //SOC_PMU_SUPPORTED } @@ -64,6 +53,7 @@ __attribute__((weak)) void esp_clk_init(void) assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M); rtc_clk_8m_enable(true); + rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); #if defined(CONFIG_BOOTLOADER_WDT_ENABLE) && SOC_RTC_WDT_SUPPORTED // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed. @@ -123,8 +113,11 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) /* number of times to repeat 32k XTAL calibration * before giving up and switching to the internal RC */ + int retry_32k_xtal = 3; + soc_rtc_slow_clk_src_t old_rtc_slow_clk_src = rtc_clk_slow_src_get(); do { + bool revoke_32k_enable = false; if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { /* 32k XTAL oscillator needs to be enabled and running before it can * be used. Hardware doesn't have a direct way of checking if the @@ -134,24 +127,47 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) * will time out, returning 0. */ ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up"); - if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - rtc_clk_32k_enable(true); + rtc_clk_32k_enable(true); + soc_clk_freq_calculation_src_t cal_sel = CLK_CAL_32K_XTAL; + // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. + if (SLOW_CLK_CAL_CYCLES > 0) { + cal_val = rtc_clk_cal(cal_sel, SLOW_CLK_CAL_CYCLES); + if (cal_val == 0) { + if (retry_32k_xtal-- > 0) { + continue; + } + ESP_EARLY_LOGW(TAG, "32 kHz clock not found, switching to internal 136 kHz oscillator"); + rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW; + revoke_32k_enable = true; + } } - - } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { - rtc_clk_rc32k_enable(true); } rtc_clk_slow_src_set(rtc_slow_clk_src); // Disable unused clock sources after clock source switching is complete. // Regardless of the clock source selection, the internal 136K clock source will always keep on. - if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) { + if (revoke_32k_enable || \ + ((old_rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K)) { rtc_clk_32k_enable(false); } - if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) { - rtc_clk_rc32k_enable(false); - } + // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection. + pmu_lp_power_t lp_clk_power = { + .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K), + .xpd_rc32k = 0, + .xpd_fosc = 1, + .pd_osc = 0 + }; + pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val); + if (SLOW_CLK_CAL_CYCLES > 0) { + /* TODO: 32k XTAL oscillator has some frequency drift at startup. + * Improve calibration routine to wait until the frequency is stable. + */ + cal_val = rtc_clk_cal(CLK_CAL_RTC_SLOW, SLOW_CLK_CAL_CYCLES); + } else { + const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; + cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz()); + } } while (cal_val == 0); ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %" PRIu32, cal_val); esp_clk_slowclk_cal_set(cal_val); diff --git a/components/heap/port/esp32s31/memory_layout.c b/components/heap/port/esp32s31/memory_layout.c index ecda25d9c3..a3bd7eddc7 100644 --- a/components/heap/port/esp32s31/memory_layout.c +++ b/components/heap/port/esp32s31/memory_layout.c @@ -103,8 +103,6 @@ SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_LOW, SOC_EXTRAM_HIGH, extram_region); #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP +SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data); SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data); -/* This includes any memory reserved for ULP RAM */ -SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_end, (intptr_t)&_rtc_force_slow_end, rtcram_data); - #endif diff --git a/components/soc/esp32h21/include/soc/regi2c_brownout.h b/components/soc/esp32h21/include/soc/regi2c_brownout.h index bad3a1ef29..4e890e1847 100644 --- a/components/soc/esp32h21/include/soc/regi2c_brownout.h +++ b/components/soc/esp32h21/include/soc/regi2c_brownout.h @@ -6,6 +6,8 @@ #pragma once +#include "regi2c_dcdc.h" + /** * @file regi2c_brownout.h * @brief Register definitions for brownout detector @@ -14,8 +16,8 @@ * bus. These definitions are used via macros defined in regi2c_ctrl.h. */ -#define I2C_BOD 0x6D -#define I2C_BOD_HOSTID 0 +#define I2C_BOD I2C_DCDC +#define I2C_BOD_HOSTID I2C_DCDC_HOSTID #define I2C_BOD_THRESHOLD 0xD #define I2C_BOD_THRESHOLD_MSB 6 diff --git a/components/soc/esp32h21/include/soc/regi2c_dcdc.h b/components/soc/esp32h21/include/soc/regi2c_dcdc.h index e5c5fd3db9..6b0dc05d74 100644 --- a/components/soc/esp32h21/include/soc/regi2c_dcdc.h +++ b/components/soc/esp32h21/include/soc/regi2c_dcdc.h @@ -12,8 +12,8 @@ * by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration. */ -#define I2C_DCDC 0x6D -#define I2C_DCDC_HOSTID 0 +#define I2C_DCDC 0x6D +#define I2C_DCDC_HOSTID 0 #define I2C_DCDC_XPD_TRX 1 #define I2C_DCDC_XPD_TRX_MSB 7 diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in index b0db8d1da9..079ebb4901 100644 --- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in @@ -47,6 +47,14 @@ config SOC_EFUSE_SUPPORTED bool default y +config SOC_RTC_FAST_MEM_SUPPORTED + bool + default y + +config SOC_RTC_MEM_SUPPORTED + bool + default y + config SOC_SDM_SUPPORTED bool default y @@ -83,6 +91,10 @@ config SOC_PSRAM_DMA_CAPABLE bool default y +config SOC_CLK_TREE_SUPPORTED + bool + default y + config SOC_WDT_SUPPORTED bool default y @@ -447,7 +459,7 @@ config SOC_MODEM_CLOCK_IS_INDEPENDENT bool default y -config SOC_CLK_APLL_SUPPORTED +config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION bool default y @@ -455,22 +467,18 @@ config SOC_CLK_MPLL_SUPPORTED bool default y +config SOC_CLK_XTAL32K_SUPPORTED + bool + default y + config SOC_CLK_RC32K_SUPPORTED bool default y -config SOC_CLK_LP_FAST_SUPPORT_LP_PLL - bool - default y - config SOC_CLK_LP_FAST_SUPPORT_XTAL bool default y -config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE - bool - default y - config SOC_RCC_IS_INDEPENDENT bool default y diff --git a/components/soc/esp32s31/include/soc/clk_tree_defs.h b/components/soc/esp32s31/include/soc/clk_tree_defs.h index 4c9e9dd213..bd695b943f 100644 --- a/components/soc/esp32s31/include/soc/clk_tree_defs.h +++ b/components/soc/esp32s31/include/soc/clk_tree_defs.h @@ -11,8 +11,6 @@ extern "C" { #endif -// TODO: to be checked IDF-14696 - /* ************************* ESP32S31 Root Clock Source **************************** * 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description) @@ -25,12 +23,12 @@ extern "C" { * * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referred as SOSC in TRM or reg. description) * - * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock - * can be computed in runtime through calibration. + * This RC oscillator generates from a ~600kHz clock signal with a divider of 4 output as the RC_SLOW_CLK. + * The exact frequency of this clock can be computed in runtime through calibration. * * 4) Internal 32kHz RC Oscillator: RC32K [NOT RECOMMENDED TO USE] * - * The exact frequency of this clock can be computed in runtime through calibration. + * The exact frequency of this clock can **not** be computed in runtime through calibration. * * 5) External 32kHz Crystal Clock (optional): XTAL32K * @@ -43,20 +41,15 @@ extern "C" { * PLL Clocks: * * from 40MHz XTAL oscillator frequency multipliers: - * 1) CPLL (320/360/400MHz), CPU_PLL, used for CPU, MSPI-Flash, MSPI-PSRAM clock source - * 2) MPLL (configurable, 400MHz at power-on reset), MSPI_PLL, used for MSPI-PSRAM clock source; and is further divided to PLL_F50M, PLL_F25M, to be used for peripheral's clock sources - * 3) SPLL (480MHz), SYS_PLL (AXI/AHB), directly used for MSPI-Flash, MSPI-PSRAM, GPSPI clock sources; and is further divided to PLL_F240M, PLL_F160M, PLL_F120M, PLL_F80M, PLL_F20M, to be used for peripherals' clock sources + * 1) CPLL (320MHz), CPU_PLL, used for CPU, MSPI-Flash, MSPI-PSRAM clock source + * 2) MPLL (configurable), MSPI_PLL, used for MSPI-PSRAM clock source; and is further divided to PLL_F50M, PLL_F25M, to be used for peripheral's clock sources + * 3) BBPLL (480MHz), SYS_PLL (AXI/AHB), directly used for MSPI-Flash, GPSPI clock sources; and is further divided to PLL_F240M, PLL_F160M, PLL_F120M, PLL_F80M, PLL_F20M, to be used for peripherals' clock sources * 4) APLL (configurable), AUDIO_PLL, can be the clock source for peripherals (I2S, GPSPI, LCD, CAM, etc.) - * 5) SDIO_PLL0/1/2 - * - * from 32kHz slow clock oscillator frequency multiplier: - * 6) LP_PLL (8MHz), used for RTC_FAST_CLK clock source and LP peripherals' clock sources */ /* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ #define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ #define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ -#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */ #define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ // Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr] @@ -71,8 +64,9 @@ typedef enum { SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */ SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */ - SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */ - SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin1 */ + // The following exist but will not be used + // SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */ + // SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin1 */ } soc_root_clk_t; /** @@ -80,6 +74,9 @@ typedef enum { */ typedef enum { SOC_ROOT_CIRCUIT_CLK_BBPLL, /*!< BBPLL_CLK is the output of the BBPLL generator circuit */ + SOC_ROOT_CIRCUIT_CLK_CPLL, /*!< CPLL_CLK is the output of the CPLL generator circuit */ + SOC_ROOT_CIRCUIT_CLK_MPLL, /*!< MPLL_CLK is the output of the MPLL generator circuit */ + SOC_ROOT_CIRCUIT_CLK_APLL, /*!< APLL_CLK is the output of the APLL generator circuit */ } soc_root_clk_circuit_t; /** @@ -88,9 +85,9 @@ typedef enum { */ typedef enum { SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_CPLL = 1, /*!< Select CPLL_CLK as CPU_CLK source (CPLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 320/360/400MHz) */ - SOC_CPU_CLK_SRC_PLL = SOC_CPU_CLK_SRC_CPLL, /*!< Alias name for `SOC_CPU_CLK_SRC_CPLL` */ + SOC_CPU_CLK_SRC_CPLL = 1, /*!< Select CPLL_CLK as CPU_CLK source (CPLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 320MHz) */ SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL_F240M = 3, /*!< Select PLL_F240M_CLK as CPU_CLK source (PLL_F240M_CLK is derived from BBPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier) */ SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ } soc_cpu_clk_src_t; @@ -101,7 +98,6 @@ typedef enum { typedef enum { SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ SOC_RTC_SLOW_CLK_SRC_DEFAULT = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, /*!< RC_SLOW_CLK is the default clock source for RTC_SLOW_CLK */ } soc_rtc_slow_clk_src_t; @@ -113,24 +109,11 @@ typedef enum { typedef enum { SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_XTAL = 1, /*!< Select XTAL_CLK as RTC_FAST_CLK source */ - SOC_RTC_FAST_CLK_SRC_LP_PLL = 2, /*!< Select LP_PLL_CLK as RTC_FAST_CLK source (LP_PLL_CLK is a 8MHz clock sourced from RC32K or XTAL32K) */ SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL, /*!< XTAL_CLK is the default clock source for RTC_FAST_CLK */ - - SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL` */ } soc_rtc_fast_clk_src_t; -/** - * @brief LP_PLL_CLK mux inputs, which are the supported clock sources for the LP_PLL_CLK - * @note Enum values are matched with the register field values on purpose - */ -typedef enum { - SOC_LP_PLL_CLK_SRC_RC32K = 0, /*!< Select RC32K_CLK as LP_PLL_CLK source */ - SOC_LP_PLL_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as LP_PLL_CLK source */ - SOC_LP_PLL_CLK_SRC_INVALID, /*!< Invalid LP_PLL_CLK source */ -} soc_lp_pll_clk_src_t; - /** * @brief Possible main XTAL frequency options on the target * @note Enum values equal to the frequency value in MHz @@ -153,26 +136,24 @@ typedef enum { // For CPU domain SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, CPLL, or RC_FAST by configuring soc_cpu_clk_src_t */ // For RTC domain - SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL, RC_FAST, or LP_PLL by configuring soc_rtc_fast_clk_src_t */ + SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL, or RC_FAST by configuring soc_rtc_fast_clk_src_t */ SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC32K by configuring soc_rtc_slow_clk_src_t */ // For digital domain: peripherals - SOC_MOD_CLK_PLL_F20M, /*!< PLL_F20M_CLK is derived from SPLL (clock gating + default divider 24), its default frequency is 20MHz */ + SOC_MOD_CLK_PLL_F20M, /*!< PLL_F20M_CLK is derived from BBPLL (clock gating + default divider 24), its default frequency is 20MHz */ SOC_MOD_CLK_PLL_F25M, /*!< PLL_F25M_CLK is derived from MPLL (clock gating + configurable divider), it will have a frequency of 25MHz */ SOC_MOD_CLK_PLL_F50M, /*!< PLL_F50M_CLK is derived from MPLL (clock gating + configurable divider 10), it will have a frequency of 50MHz */ - SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from SPLL (clock gating + default divider 6), its default frequency is 80MHz */ - SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from SPLL (clock gating + default divider 3), its default frequency is 160MHz */ - SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from SPLL (clock gating + default divider 2), its default frequency is 240MHz */ + SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from BBPLL (clock gating + default divider 6), its default frequency is 80MHz */ + SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from BBPLL (clock gating + default divider 3), its default frequency is 160MHz */ + SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from BBPLL (clock gating + default divider 2), its default frequency is 240MHz */ SOC_MOD_CLK_CPLL, /*!< CPLL is from 40MHz XTAL oscillator frequency multipliers */ - SOC_MOD_CLK_SPLL, /*!< SPLL is from 40MHz XTAL oscillator frequency multipliers, its default frequency is 480MHz */ + SOC_MOD_CLK_BBPLL, /*!< BBPLL is from 40MHz XTAL oscillator frequency multipliers, its default frequency is 480MHz */ SOC_MOD_CLK_MPLL, /*!< MPLL is from 40MHz XTAL oscillator frequency multipliers */ - SOC_MOD_CLK_SDIO_PLL, /*!< SDIO PLL is from 40MHz XTAL oscillator frequency multipliers, its default frequency is 200MHz */ SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */ SOC_MOD_CLK_APLL, /*!< Audio PLL is sourced from PLL, and its frequency is configurable through APLL configuration registers */ // For LP peripherals SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */ - SOC_MOD_CLK_LP_PLL, /*!< LP_PLL is from 32kHz XTAL oscillator frequency multipliers, it has a fixed frequency of 8MHz */ SOC_MOD_CLK_LP_DYN_FAST, /*!< LP_DYN_FAST can be derived from RTC_SLOW_CLK or RTC_FAST_CLK depending on the chip’s power mode: Only in LP_SLEEP mode, select RTC_SLOW_CLK as the clock source; In other non-LP_SLEEP mode, select RTC_FAST_CLK as the clock source; */ @@ -262,7 +243,7 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of SPI */ -#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL} +#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_BBPLL} /** * @brief Type of SPI clock source. @@ -270,8 +251,8 @@ typedef enum { typedef enum { SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST_20M as SPI source clock */ - SPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as SPI source clock */ - SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_SPLL, /*!< Select XTAL as default source clock */ + SPI_CLK_SRC_BBPLL = SOC_MOD_CLK_BBPLL, /*!< Select BBPLL as SPI source clock */ + SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_BBPLL, /*!< Select BBPLL as default source clock */ } soc_periph_spi_clk_src_t; /////////////////////////////////////////////////PSRAM//////////////////////////////////////////////////////////////////// @@ -296,16 +277,16 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of FLASH */ -#define SOC_FLASH_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_CPLL, SOC_MOD_CLK_SPLL} +#define SOC_FLASH_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_CPLL, SOC_MOD_CLK_BBPLL} /** * @brief Type of FLASH clock source. */ typedef enum { - FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_SPLL, /*!< Select SOC_MOD_CLK_SPLL as FLASH source clock */ + FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_BBPLL, /*!< Select SOC_MOD_CLK_BBPLL as FLASH source clock */ FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select SOC_MOD_CLK_XTAL as FLASH source clock */ FLASH_CLK_SRC_CPLL = SOC_MOD_CLK_CPLL, /*!< Select SOC_MOD_CLK_CPLL as FLASH source clock */ - FLASH_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SOC_MOD_CLK_SPLL as FLASH source clock */ + FLASH_CLK_SRC_BBPLL = SOC_MOD_CLK_BBPLL, /*!< Select SOC_MOD_CLK_BBPLL as FLASH source clock */ } soc_periph_flash_clk_src_t; //////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// @@ -384,8 +365,8 @@ typedef enum { //////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// typedef enum { CLKOUT_SIG_MPLL = 0, /*!< MPLL is from 40MHz XTAL oscillator frequency multipliers */ - CLKOUT_SIG_SPLL = 1, /*!< SPLL is from 40MHz XTAL oscillator frequency multipliers, its default frequency is 480MHz */ - CLKOUT_SIG_CPLL = 2, /*!< CPLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 320/360/400MHz */ + CLKOUT_SIG_BBPLL = 1, /*!< BBPLL is from 40MHz XTAL oscillator frequency multipliers, its default frequency is 480MHz */ + CLKOUT_SIG_CPLL = 2, /*!< CPLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 320MHz */ CLKOUT_SIG_XTAL = 3, /*!< External 40MHz crystal */ CLKOUT_SIG_RC_FAST = 4, /*!< Internal 17.5MHz RC oscillator */ CLKOUT_SIG_RC_SLOW = 5, /*!< Internal 136kHz RC oscillator */ @@ -409,17 +390,19 @@ typedef enum { typedef enum { CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */ CLK_CAL_MPLL, /*!< Select to calculate frequency of MPLL_CLK */ - CLK_CAL_SPLL, /*!< Select to calculate frequency of SPLL_CLK */ + CLK_CAL_BBPLL, /*!< Select to calculate frequency of BBPLL_CLK */ CLK_CAL_CPLL, /*!< Select to calculate frequency of CPLL_CLK */ CLK_CAL_APLL, /*!< Select to calculate frequency of APLL_CLK */ - CLK_CAL_SDIO_PLL0, /*!< Select to calculate frequency of SDIO_PLL0_CLK */ - CLK_CAL_SDIO_PLL1, /*!< Select to calculate frequency of SDIO_PLL1_CLK */ - CLK_CAL_SDIO_PLL2, /*!< Select to calculate frequency of SDIO_PLL2_CLK */ + CLK_CAL_AHB, /*!< Select to calculate frequency of AHB_CLK */ + CLK_CAL_APB, /*!< Select to calculate frequency of APB_CLK */ + CLK_CAL_ROM, /*!< Select to calculate frequency of ROM_CLK */ CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */ CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */ - CLK_CAL_RC32K, /*!< Select to calculate frequency of RC32K_CLK */ CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */ - CLK_CAL_LP_PLL, /*!< Select to calculate frequency of LP_PLL_CLK */ + CLK_CAL_XTAL, /*!< Select to calculate frequency of XTAL_CLK */ + CLK_CAL_UART0_PAD, /*!< Select to calculate frequency of UART0_PAD_CLK */ + CLK_CAL_CORE0, /*!< Select to calculate frequency of CORE0_CLK */ + CLK_CAL_CORE1, /*!< Select to calculate frequency of CORE1_CLK */ } soc_clk_freq_calculation_src_t; //////////////////////////////////////////////////CORDIC/////////////////////////////////////////////////////////// diff --git a/components/soc/esp32s31/include/soc/regi2c_bbpll.h b/components/soc/esp32s31/include/soc/regi2c_bbpll.h new file mode 100644 index 0000000000..737bbf7dc3 --- /dev/null +++ b/components/soc/esp32s31/include/soc/regi2c_bbpll.h @@ -0,0 +1,123 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#pragma once + +/** + * @file regi2c_bbpll.h + * @brief Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 0 + +#define I2C_BBPLL_IR_CAL_DELAY 0 +#define I2C_BBPLL_IR_CAL_DELAY_MSB 3 +#define I2C_BBPLL_IR_CAL_DELAY_LSB 0 + +#define I2C_BBPLL_IR_CAL_CK_DIV 0 +#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7 +#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4 + +#define I2C_BBPLL_IR_CAL_EXT_CAP 1 +#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3 +#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_BBPLL_IR_CAL_ENX_CAP 1 +#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4 +#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4 + +#define I2C_BBPLL_IR_CAL_RSTB 1 +#define I2C_BBPLL_IR_CAL_RSTB_MSB 5 +#define I2C_BBPLL_IR_CAL_RSTB_LSB 5 + +#define I2C_BBPLL_IR_CAL_START 1 +#define I2C_BBPLL_IR_CAL_START_MSB 6 +#define I2C_BBPLL_IR_CAL_START_LSB 6 + +#define I2C_BBPLL_IR_CAL_UNSTOP 1 +#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 +#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DCHGP 2 +#define I2C_BBPLL_OC_DCHGP_MSB 6 +#define I2C_BBPLL_OC_DCHGP_LSB 4 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#define I2C_BBPLL_RSTB_DIV_ADC 4 +#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0 +#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0 + +#define I2C_BBPLL_MODE_HF 4 +#define I2C_BBPLL_MODE_HF_MSB 1 +#define I2C_BBPLL_MODE_HF_LSB 1 + +#define I2C_BBPLL_DIV_DAC 4 +#define I2C_BBPLL_DIV_DAC_MSB 4 +#define I2C_BBPLL_DIV_DAC_LSB 4 + +#define I2C_BBPLL_DIV_CPU 4 +#define I2C_BBPLL_DIV_CPU_MSB 5 +#define I2C_BBPLL_DIV_CPU_LSB 5 + +#define I2C_BBPLL_OC_DR1 5 +#define I2C_BBPLL_OC_DR1_MSB 2 +#define I2C_BBPLL_OC_DR1_LSB 0 + +#define I2C_BBPLL_OC_DR3 5 +#define I2C_BBPLL_OC_DR3_MSB 6 +#define I2C_BBPLL_OC_DR3_LSB 4 + +#define I2C_BBPLL_EN_USB 5 +#define I2C_BBPLL_EN_USB_MSB 7 +#define I2C_BBPLL_EN_USB_LSB 7 + +#define I2C_BBPLL_OC_DHREF_SEL 6 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 6 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 + +#define I2C_BBPLL_OR_CAL_UDF 8 +#define I2C_BBPLL_OR_CAL_UDF_MSB 4 +#define I2C_BBPLL_OR_CAL_UDF_LSB 4 + +#define I2C_BBPLL_OR_CAL_OVF 8 +#define I2C_BBPLL_OR_CAL_OVF_MSB 5 +#define I2C_BBPLL_OR_CAL_OVF_LSB 5 + +#define I2C_BBPLL_OR_CAL_END 8 +#define I2C_BBPLL_OR_CAL_END_MSB 6 +#define I2C_BBPLL_OR_CAL_END_LSB 6 + +#define I2C_BBPLL_OR_LOCK 8 +#define I2C_BBPLL_OR_LOCK_MSB 7 +#define I2C_BBPLL_OR_LOCK_LSB 7 + +#define I2C_BBPLL_OC_VCO_DBIAS 9 +#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1 +#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0 + +#define I2C_BBPLL_ENT_PLL 10 +#define I2C_BBPLL_ENT_PLL_MSB 3 +#define I2C_BBPLL_ENT_PLL_LSB 3 + +#define I2C_BBPLL_DTEST 10 +#define I2C_BBPLL_DTEST_MSB 5 +#define I2C_BBPLL_DTEST_LSB 4 diff --git a/components/soc/esp32s31/include/soc/regi2c_dig_reg.h b/components/soc/esp32s31/include/soc/regi2c_dig_reg.h new file mode 100644 index 0000000000..bfd577ad7c --- /dev/null +++ b/components/soc/esp32s31/include/soc/regi2c_dig_reg.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#pragma once + +/** + * @file regi2c_dig_reg.h + * @brief Register definitions for digital to get rtc voltage & digital voltage + * by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration. + */ + +#define I2C_DIG_REG 0x6D +#define I2C_DIG_REG_HOSTID 0 + +#define I2C_DIG_REG_EXT_RTC_DREG 4 +#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4 +#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0 + +#define I2C_DIG_REG_ENX_RTC_DREG 4 +#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7 +#define I2C_DIG_REG_ENX_RTC_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5 +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4 +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0 + +#define I2C_DIG_REG_ENIF_RTC_DREG 5 +#define I2C_DIG_REG_ENIF_RTC_DREG_MSB 7 +#define I2C_DIG_REG_ENIF_RTC_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_DIG_DREG 6 +#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4 +#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0 + +#define I2C_DIG_REG_ENX_DIG_DREG 6 +#define I2C_DIG_REG_ENX_DIG_DREG_MSB 7 +#define I2C_DIG_REG_ENX_DIG_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7 +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4 +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0 + +#define I2C_DIG_REG_ENIF_DIG_DREG 7 +#define I2C_DIG_REG_ENIF_DIG_DREG_MSB 7 +#define I2C_DIG_REG_ENIF_DIG_DREG_LSB 7 + +#define I2C_DIG_REG_OR_EN_CONT_CAL 9 +#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7 +#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7 + +#define I2C_DIG_REG_XPD_RTC_REG 13 +#define I2C_DIG_REG_XPD_RTC_REG_MSB 2 +#define I2C_DIG_REG_XPD_RTC_REG_LSB 2 + +#define I2C_DIG_REG_XPD_DIG_REG 13 +#define I2C_DIG_REG_XPD_DIG_REG_MSB 3 +#define I2C_DIG_REG_XPD_DIG_REG_LSB 3 + +#define I2C_DIG_REG_SCK_DCAP 14 +#define I2C_DIG_REG_SCK_DCAP_MSB 7 +#define I2C_DIG_REG_SCK_DCAP_LSB 0 diff --git a/components/soc/esp32s31/include/soc/regi2c_saradc.h b/components/soc/esp32s31/include/soc/regi2c_saradc.h index c2f29bce5c..a6602637ff 100644 --- a/components/soc/esp32s31/include/soc/regi2c_saradc.h +++ b/components/soc/esp32s31/include/soc/regi2c_saradc.h @@ -1,4 +1,3 @@ - /* * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD * @@ -6,6 +5,7 @@ */ #pragma once + /** * @file regi2c_saradc.h * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC. diff --git a/components/soc/esp32s31/include/soc/soc.h b/components/soc/esp32s31/include/soc/soc.h index bfbe3f5b44..10a2a8943a 100644 --- a/components/soc/esp32s31/include/soc/soc.h +++ b/components/soc/esp32s31/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -127,11 +127,8 @@ //}} //Periheral Clock {{ -#define APB_CLK_FREQ_ROM ( 10*1000000 ) -#define CPU_CLK_FREQ_ROM ( 40*1000000 ) -#define APB_CLK_FREQ ( 90*1000000 ) +#define APB_CLK_FREQ ( 40*1000000 ) #define REF_CLK_FREQ ( 1000000 ) -#define XTAL_CLK_FREQ (40*1000000) //}} // TODO: to be checked IDF-14669 diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h index bd2fab13ab..c49e481951 100644 --- a/components/soc/esp32s31/include/soc/soc_caps.h +++ b/components/soc/esp32s31/include/soc/soc_caps.h @@ -52,7 +52,8 @@ // #define SOC_LP_CORE_SUPPORTED 1 // TODO: [ESP32S31] IDF-14640 #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32S31] IDF-14688 #define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32S31] IDF-14688 -// #define SOC_RTC_MEM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14678 +#define SOC_RTC_FAST_MEM_SUPPORTED 1 +#define SOC_RTC_MEM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14645 // #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32S31] IDF-14794 // #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32S31] IDF-14771 #define SOC_SDM_SUPPORTED 1 @@ -83,7 +84,7 @@ #define SOC_SPIRAM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14718 #define SOC_PSRAM_DMA_CAPABLE 1 // #define SOC_SDMMC_HOST_SUPPORTED 1 // TODO: [ESP32S31] IDF-14705 -// #define SOC_CLK_TREE_SUPPORTED 1 // TODO: [ESP32S31] IDF-14733 +#define SOC_CLK_TREE_SUPPORTED 1 // #define SOC_ASSIST_DEBUG_SUPPORTED 1 // TODO: [ESP32S31] IDF-14675 // #define SOC_DEBUG_PROBE_SUPPORTED 1 // TODO: [ESP32S31] IDF-14798 #define SOC_WDT_SUPPORTED 1 @@ -287,18 +288,17 @@ #define SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE (1) // /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/ -// TODO: [ESP32S31] IDF-14733 #define SOC_MODEM_CLOCK_IS_INDEPENDENT (1) -#define SOC_CLK_APLL_SUPPORTED (1) /*!< Support Audio PLL */ -#define SOC_CLK_MPLL_SUPPORTED (1) /*!< Support MSPI PLL */ +#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1) + +// #define SOC_CLK_APLL_SUPPORTED (1) /*!< Support Audio PLL */ // TODO: IDF-14771, IDF-14750 +#define SOC_CLK_MPLL_SUPPORTED (1) /*!< Support MSPI PLL */ // TODO: IDF-14718 +#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */ #define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */ -#define SOC_CLK_LP_FAST_SUPPORT_LP_PLL (1) /*!< Support LP_PLL clock as the LP_FAST clock source */ #define SOC_CLK_LP_FAST_SUPPORT_XTAL (1) /*!< Support XTAL clock as the LP_FAST clock source */ -#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (1) /*!< Any regi2c operation needs enable the analog i2c master clock first */ - #define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control has own registers for each module */ /*-------------------------- Power Management CAPS ----------------------------*/ diff --git a/components/soc/esp32s31/register/soc/pmu_reg.h b/components/soc/esp32s31/register/soc/pmu_reg.h index fbd4da4aee..73c15cb03b 100644 --- a/components/soc/esp32s31/register/soc/pmu_reg.h +++ b/components/soc/esp32s31/register/soc/pmu_reg.h @@ -224,20 +224,62 @@ extern "C" { #define PMU_HP_ACTIVE_XPD_BB_I2C_M (PMU_HP_ACTIVE_XPD_BB_I2C_V << PMU_HP_ACTIVE_XPD_BB_I2C_S) #define PMU_HP_ACTIVE_XPD_BB_I2C_V 0x00000001U #define PMU_HP_ACTIVE_XPD_BB_I2C_S 22 -/** PMU_HP_ACTIVE_XPD_PLL_I2C : R/W; bitpos: [26:23]; default: 0; +/** PMU_HP_ACTIVE_XPD_CPLL_I2C : R/W; bitpos: [23]; default: 0; * need_des */ -#define PMU_HP_ACTIVE_XPD_PLL_I2C 0x0000000FU -#define PMU_HP_ACTIVE_XPD_PLL_I2C_M (PMU_HP_ACTIVE_XPD_PLL_I2C_V << PMU_HP_ACTIVE_XPD_PLL_I2C_S) -#define PMU_HP_ACTIVE_XPD_PLL_I2C_V 0x0000000FU -#define PMU_HP_ACTIVE_XPD_PLL_I2C_S 23 -/** PMU_HP_ACTIVE_XPD_PLL : R/W; bitpos: [30:27]; default: 0; +#define PMU_HP_ACTIVE_XPD_CPLL_I2C 0x00000001U +#define PMU_HP_ACTIVE_XPD_CPLL_I2C_M (PMU_HP_ACTIVE_XPD_CPLL_I2C_V << PMU_HP_ACTIVE_XPD_CPLL_I2C_S) +#define PMU_HP_ACTIVE_XPD_CPLL_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_CPLL_I2C_S 23 +/** PMU_HP_ACTIVE_XPD_BBPLL_I2C : R/W; bitpos: [24]; default: 0; * need_des */ -#define PMU_HP_ACTIVE_XPD_PLL 0x0000000FU -#define PMU_HP_ACTIVE_XPD_PLL_M (PMU_HP_ACTIVE_XPD_PLL_V << PMU_HP_ACTIVE_XPD_PLL_S) -#define PMU_HP_ACTIVE_XPD_PLL_V 0x0000000FU -#define PMU_HP_ACTIVE_XPD_PLL_S 27 +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_M (PMU_HP_ACTIVE_XPD_BBPLL_I2C_V << PMU_HP_ACTIVE_XPD_BBPLL_I2C_S) +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_S 24 +/** PMU_HP_ACTIVE_XPD_APLL_I2C : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_APLL_I2C 0x00000001U +#define PMU_HP_ACTIVE_XPD_APLL_I2C_M (PMU_HP_ACTIVE_XPD_APLL_I2C_V << PMU_HP_ACTIVE_XPD_ACPLL_I2C_S) +#define PMU_HP_ACTIVE_XPD_APLL_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_APLL_I2C_S 25 +/** PMU_HP_ACTIVE_XPD_MPLL_I2C : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_MLL_I2C 0x00000001U +#define PMU_HP_ACTIVE_XPD_MPLL_I2C_M (PMU_HP_ACTIVE_XPD_MPLL_I2C_V << PMU_HP_ACTIVE_XPD_MPLL_I2C_S) +#define PMU_HP_ACTIVE_XPD_MPLL_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_MPLL_I2C_S 26 +/** PMU_HP_ACTIVE_XPD_CPLL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_CPLL 0x00000001U +#define PMU_HP_ACTIVE_XPD_CPLL_M (PMU_HP_ACTIVE_XPD_CPLL_V << PMU_HP_ACTIVE_XPD_CPLL_S) +#define PMU_HP_ACTIVE_XPD_CPLL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_CPLL_S 27 +/** PMU_HP_ACTIVE_XPD_BBPLL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BBPLL 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_M (PMU_HP_ACTIVE_XPD_BBPLL_V << PMU_HP_ACTIVE_XPD_BBPLL_S) +#define PMU_HP_ACTIVE_XPD_BBPLL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_S 28 +/** PMU_HP_ACTIVE_XPD_APLL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_APLL 0x00000001U +#define PMU_HP_ACTIVE_XPD_APLL_M (PMU_HP_ACTIVE_XPD_APLL_V << PMU_HP_ACTIVE_XPD_APLL_S) +#define PMU_HP_ACTIVE_XPD_APLL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_APLL_S 29 +/** PMU_HP_ACTIVE_XPD_MPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_MPLL 0x00000001U +#define PMU_HP_ACTIVE_XPD_MPLL_M (PMU_HP_ACTIVE_XPD_MPLL_V << PMU_HP_ACTIVE_XPD_MPLL_S) +#define PMU_HP_ACTIVE_XPD_MPLL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_MPLL_S 30 /** PMU_HP_ACTIVE_BIAS_REG register * need_des diff --git a/docs/en/api-reference/peripherals/clk_tree.rst b/docs/en/api-reference/peripherals/clk_tree.rst index 8201eede15..ae3a9f391c 100644 --- a/docs/en/api-reference/peripherals/clk_tree.rst +++ b/docs/en/api-reference/peripherals/clk_tree.rst @@ -63,11 +63,11 @@ Root clocks generate reliable clock signals. These clock signals then pass throu The clock source for this ``XTAL32K_CLK`` can be either a 32 kHz crystal connecting to the ``32K_XP`` and ``32K_XN`` pins or a 32 kHz clock signal generated by an external circuit. The external signal must be connected to the ``32K_XN`` pin. Additionally, a 1 nF capacitor must be placed between the ``32K_XP`` pin and ground. In this case, the ``32K_XP`` pin cannot be used as a GPIO pin. - .. only:: esp32p4 + .. only:: esp32p4 or esp32s31 The clock source for this ``XTAL32K_CLK`` is a 32 kHz crystal connecting to the ``XTAL_32K_P`` and ``XTAL_32K_N`` pins. - .. only:: not esp32 and not esp32p4 + .. only:: not esp32 and not esp32p4 and not esp32s31 The clock source for this ``XTAL32K_CLK`` can be either a 32 kHz crystal connecting to the ``XTAL_32K_P`` and ``XTAL_32K_N`` pins or a 32 kHz clock signal generated by an external circuit. The external signal must be connected to the ``XTAL_32K_P`` pin. diff --git a/docs/zh_CN/api-reference/peripherals/clk_tree.rst b/docs/zh_CN/api-reference/peripherals/clk_tree.rst index 3e41295906..b2aff6241d 100644 --- a/docs/zh_CN/api-reference/peripherals/clk_tree.rst +++ b/docs/zh_CN/api-reference/peripherals/clk_tree.rst @@ -63,11 +63,11 @@ ``XTAL32K_CLK`` 的时钟源可以是连接到 ``32K_XP`` 和 ``32K_XN`` 管脚的 32 kHz 晶振，也可以是外部电路生成的 32 kHz 时钟信号。如果使用外部电路生成的时钟信号，该信号必须连接到 ``32K_XN`` 管脚，并且在 ``32K_XP`` 管脚和地之间连接一个 1 nF 的电容。此时，``32K_XP`` 管脚不能用作 GPIO 管脚。 - .. only:: esp32p4 + .. only:: esp32p4 or esp32s31 ``XTAL32K_CLK`` 的时钟源是连接到 ``XTAL_32K_P`` 和 ``XTAL_32K_N`` 管脚的 32 kHz 晶振。 - .. only:: not esp32 and not esp32p4 + .. only:: not esp32 and not esp32p4 and not esp32s31 ``XTAL32K_CLK`` 的时钟源可以是连接到 ``XTAL_32K_P`` 和 ``XTAL_32K_N`` 管脚的 32 kHz 晶振，也可以是外部电路生成的 32 kHZ 时钟信号。如果使用外部电路生成的时钟信号，该信号必须连接到 ``XTAL_32K_P`` 管脚。