From 968c42d88c26db0243f525b148d9508971c21dc6 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Thu, 2 Sep 2021 20:48:39 +0800 Subject: [PATCH] 822 FPGA rnv init --- Kconfig | 1 + .../port/esp32h2/rtc_clk_init.c | 4 + .../esp_hw_support/port/esp32h2/rtc_init.c | 5 + .../esp_hw_support/port/esp32h2/rtc_sleep.c | 70 + components/esp_rom/eagle.pro.rom.out | Bin 0 -> 1719032 bytes .../esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld | 1130 +++--- .../esp32h2/ld/rev2/esp32h2.rom.libgcc.ld | 184 +- .../ld/rev2/esp32h2.rom.newlib-nano.ld | 28 +- .../esp32h2/ld/rev2/esp32h2.rom.newlib.ld | 156 +- .../esp32h2/ld/rev2/esp32h2.rom.version.ld | 2 +- components/esptool_py/Kconfig.projbuild | 2 + components/soc/esp32h2/CMakeLists.txt | 12 +- components/soc/esp32h2/gpio_periph.c | 18 +- .../include/soc/{ => rev1}/assist_debug_reg.h | 18 +- .../include/soc/{ => rev1}/gpio_sd_reg.h | 18 +- .../soc/{ => rev1}/interrupt_core0_reg.h | 18 +- .../include/soc/{ => rev1}/io_mux_reg.h | 18 +- .../include/soc/{ => rev1}/rtc_cntl_reg.h | 18 +- .../include/soc/{ => rev1}/rtc_cntl_struct.h | 18 +- .../include/soc/{ => rev1}/sensitive_reg.h | 18 +- .../include/soc/rev2/assist_debug_reg.h | 685 ++++ .../esp32h2/include/soc/rev2/gpio_sd_reg.h | 175 + .../include/soc/rev2/interrupt_core0_reg.h | 920 +++++ .../soc/esp32h2/include/soc/rev2/io_mux_reg.h | 268 ++ .../esp32h2/include/soc/rev2/rtc_cntl_reg.h | 3276 +++++++++++++++++ .../include/soc/rev2/rtc_cntl_struct.h | 1021 +++++ .../esp32h2/include/soc/rev2/sensitive_reg.h | 2532 +++++++++++++ components/soc/esp32h2/include/soc/rtc.h | 31 +- components/soc/esp32h2/include/soc/soc_caps.h | 5 + tools/ci/check_copyright_ignore.txt | 7 +- 30 files changed, 9776 insertions(+), 882 deletions(-) create mode 100755 components/esp_rom/eagle.pro.rom.out rename components/soc/esp32h2/include/soc/{ => rev1}/assist_debug_reg.h (98%) rename components/soc/esp32h2/include/soc/{ => rev1}/gpio_sd_reg.h (84%) rename components/soc/esp32h2/include/soc/{ => rev1}/interrupt_core0_reg.h (98%) rename components/soc/esp32h2/include/soc/{ => rev1}/io_mux_reg.h (94%) rename components/soc/esp32h2/include/soc/{ => rev1}/rtc_cntl_reg.h (99%) rename components/soc/esp32h2/include/soc/{ => rev1}/rtc_cntl_struct.h (98%) rename components/soc/esp32h2/include/soc/{ => rev1}/sensitive_reg.h (99%) create mode 100644 components/soc/esp32h2/include/soc/rev2/assist_debug_reg.h create mode 100644 components/soc/esp32h2/include/soc/rev2/gpio_sd_reg.h create mode 100644 components/soc/esp32h2/include/soc/rev2/interrupt_core0_reg.h create mode 100644 components/soc/esp32h2/include/soc/rev2/io_mux_reg.h create mode 100644 components/soc/esp32h2/include/soc/rev2/rtc_cntl_reg.h create mode 100644 components/soc/esp32h2/include/soc/rev2/rtc_cntl_struct.h create mode 100644 components/soc/esp32h2/include/soc/rev2/sensitive_reg.h diff --git a/Kconfig b/Kconfig index a2fa4e06b9..d6b535b449 100644 --- a/Kconfig +++ b/Kconfig @@ -11,6 +11,7 @@ mainmenu "Espressif IoT Development Framework Configuration" config IDF_ENV_FPGA # This option is for internal use only bool + default "y" if IDF_TARGET_ESP32H2_BETA_VERSION_2 # ESP32H2-TODO: IDF-3378 option env="IDF_ENV_FPGA" config IDF_TARGET_ARCH_RISCV diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk_init.c b/components/esp_hw_support/port/esp32h2/rtc_clk_init.c index 38c2ac8e34..ff7f67767a 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32h2/rtc_clk_init.c @@ -43,7 +43,11 @@ void rtc_clk_init(rtc_clk_config_t cfg) * - CK8M_DFREQ value controls tuning of 8M clock. * CLK_8M_DFREQ constant gives the best temperature characteristics. */ +#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 + REG_SET_FIELD(RTC_CNTL_REGULATOR_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); +#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); +#endif REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); /* enable modem clk */ diff --git a/components/esp_hw_support/port/esp32h2/rtc_init.c b/components/esp_hw_support/port/esp32h2/rtc_init.c index 7b684d3d3d..b22c2a101c 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_init.c +++ b/components/esp_hw_support/port/esp32h2/rtc_init.c @@ -80,8 +80,13 @@ void rtc_init(rtc_config_t cfg) SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU); } +#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 + CLEAR_PERI_REG_MASK(RTC_CNTL_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_REGULATOR_REG, RTC_CNTL_DBOOST_FORCE_PU); +#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU); +#endif // clear i2c_reset_protect pd force, need tested in low temperature. CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_I2C_RESET_POR_FORCE_PD); diff --git a/components/esp_hw_support/port/esp32h2/rtc_sleep.c b/components/esp_hw_support/port/esp32h2/rtc_sleep.c index 97d8ddae6a..2a30694de5 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32h2/rtc_sleep.c @@ -75,7 +75,33 @@ void dcdc_ctl(uint32_t mode) void regulator_set(regulator_cfg_t cfg) { +#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 // DIG REGULATOR0 + if (cfg.dig_regul0_en) { + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0); + } else { + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 1); + } + // DIG REGULATOR1 + if (cfg.dig_regul1_en) { + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 0); + } else { + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 1); + } + // RTC REGULATOR0 + if (cfg.rtc_regul0_en) { + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PD, 0); + } else { + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PD, 1); + } +#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 + // DIG REGULATOR0 if (cfg.dig_regul0_en) { REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0); REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0); @@ -99,11 +125,30 @@ void regulator_set(regulator_cfg_t cfg) REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PD, 1); } +#endif } void regulator_slt(regulator_config_t regula_cfg) { +#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 // dig regulator + if (regula_cfg.dig_source == 1) { + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP, regula_cfg.dig_slp_dbias); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE, regula_cfg.dig_active_dbias); + } else { + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP, regula_cfg.dig_slp_dbias); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE, regula_cfg.dig_active_dbias); + } + // rtc regulator + if (regula_cfg.rtc_source == 1) { + REG_SET_FIELD(RTC_CNTL_REGULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_SLP, regula_cfg.rtc_slp_dbias); + REG_SET_FIELD(RTC_CNTL_REGULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias); + } else { + REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_SLP, regula_cfg.rtc_slp_dbias); + REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias); + } +#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 + // dig regulator if (regula_cfg.dig_source == 1) { REG_SET_FIELD(RTC_CNTL_DIGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP, regula_cfg.dig_slp_dbias); REG_SET_FIELD(RTC_CNTL_DIGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE, regula_cfg.dig_active_dbias); @@ -119,13 +164,20 @@ void regulator_slt(regulator_config_t regula_cfg) REG_SET_FIELD(RTC_CNTL_RTCULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_SLP, regula_cfg.rtc_slp_dbias); REG_SET_FIELD(RTC_CNTL_RTCULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias); } +#endif } void dbias_switch_set(dbias_swt_cfg_t cfg) { +#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp); +#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp); +#endif } void left_up_trx_fpu(bool fpu) @@ -186,7 +238,24 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT); + // ESP32-H2 TO-DO: IDF-3693 +#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 + if (cfg.deep_slp) { + // REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0); + // CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU); + SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); + CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, + RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | + RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU); + } else { + SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); + // SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); + } +#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 if (cfg.deep_slp) { // REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0); // CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); @@ -201,6 +270,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) // SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); } +#endif /* enable VDDSDIO control by state machine */ REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); diff --git a/components/esp_rom/eagle.pro.rom.out b/components/esp_rom/eagle.pro.rom.out new file mode 100755 index 0000000000000000000000000000000000000000..ccd13ee4e7efe5edb910293075391a9cb5fc9198 GIT binary patch literal 1719032 zcmeFZdsq}#(l~s2db)cCLBQswK}7~Zh#}}Gs2g!cnHfMO=mMgm0Xw2G(Z+bsN-{7s zI2r_OnGquiV$|sOOI~DFX2ZS;C>J$e&?u;DTy!F=ZVX@q)CBm|88n)_o89;Om@vR~n^Lj9|N_j=m?ukkHVzvU_ZU)BEy;Qs-5Z>aAGZR75|$loJq z{}JHFJZ&Gh@gn{wsQ=SbJjVSRza>zDwtRVZ+E}RnukiWfB`E*FxoIJQhwApf7u(-6 zMS}J``E7g|;LH9Ez6J0t{|^5L!2dYV{=eeS`!xyj{^{Jb3BaEV=pVz2{OPAjkRJLU z!AMkC_P>_@9>DJb{4Bu#tM)$y{HK7A1-!lU@bAU;{}15*&%eR{8SsDpH+U2S7WHxG zH1sj0%AbM|2F%AZ`}`>n>#uX#PyN)-{5``z4Y(cM1G1f!`(Yy99oh z!0!_HT>`&L;Qvn&;E~Jx7x{H~n&4ZK-{)JZ-{V`*2Yic*6W^Hc&HEg2i>S{N>F^z}(X?$77TE47oG4FHn6#!4($8`knQxM4ebdKhI=1k#zh&SO0d2>eb zJ~iujmz3drODqNL)6o7CjFJ@1rJppOg)JV+hNK zG@KDHV_mB7cg0O;fSSOlPt8^}+Fypni6BrOois(6))l2?^Y;Ze$L z9*y(hL&in&u>}hNGyu@foCsc3^D?j6JAqe?dJW!Z@~VubyeefqA95=RzzcAWfZGgt z8{mnci~`?UAF}#QKIGyXfD7VP>gB*U2>|j+NeAAN0eC)S?^588gR*{nNKFJELcGO?%<+Z% zKq%)9dC-Tw1hh95@+a{wqlSR4+<2Faq42KcU5M!bQSctkyX>9KyWEQ9UDWfS%zQpJ z;}1Yv4SX%;V@JIOd;yFa2hSxg3AVI)CfL{!_{Cj zN0!3-3dmmx_%yJ+mAq;W!K(@YR)Y>N4&hZtUV^;IkQdIY#?64V4$^Y~zmQkC0*^Ha z_$8rF6!1F;WcMDQ4E;>bm<)QDWY>ji9O!!v;zQI?ygq~BJND}Mj!_f&4z&uNA$-S? zK>&~@Ht`*+$MYQpK9G)pv@@?)OZX1gSiU3UCB7rY8|n;)Cjc=L0LtA00R49m3IIPy z1JsP>JH|nsaWT-=Y^dW8xG{j63ba!ImIAB-T8>aRjqkW9hq5H!(di7}2K1oqBcmW6 z>a7lj_X&^>{9T*`xXA#(8vrVMl}8;f1B~ZUtdd9h6X6|$8fe7>&6&XK49E}U5%>WV z3(&~(E_#}G@d2NqAI|&uuuv8O&yZL4F2D-jrEw-a!Dd|M^De4j-lfEscS!~)Nr8G$ zCizu(0#rku9-!KrcWGG!_(goO>o`7n96*5*#?AytPlWd{$OCVI8U^`r1MgrH$*!q<@(}>n)$jx;SOaZsfbx-$js}4Dg7^8f6pBwH9Qd>vfDC8A z&xCejAnn4Z?HvM7FTlUVr;Qo~py1PPjpoxp7isDMNRNSZAmCqya$!(E0`jAw&H0dC z2=$X7oy>QjAn=>h`Laee_`!92hYEDt0)U{6TPaZHEr7S7-n-By4|$9Ev^fl)=1Raj z@TlGlZEb?*T7dO@+G@zpSOR6=0CoIl7J&~>6QG<5%4nh98oo^RF2sf< zfQLAg_9rO6k*_ZCfHEHd9fGe`Iq=nb7l>IgkRAe{;j3E!l63%+p{#w251uM019?7C z@E!#3usetl)SbjvBY$Wo3~&(d(%ymeSje9O0C^ZnK!<5>0w0?|7Bs}g&3uc`RDfuZ zWf;IjzGO}i-!8cc33?}0eR3b*S8>l4U`Fne6UyGp$up=x=NvK7TPBHGKk%c za|T1(evsz_c}{$O!5{gSf@yrR$`$fnf%jLT4-rt$6W)REjHyr_^jtvm)fqD2Z3N)7 zkRJ>0v-w8#20kBRU_P-K^45dhjRy$etJMtOcu@oSARqOs&=$mm{1JQ!0pqS3Y_1># zo=JR(8u|l%pn4AU9oqM~wVe0KSjPM8O$AsCcA?|-9i#b@*lB!8$Yg*80Q2~gw0M9- zzRYJV;52+%SumfLp9E!B@OpSJQO)A@AwaKW7GL6%#+M)%hq1nVezk#MSpa@q!7?*ru# z4R|T9Z*k=HB`%QmgtRyC7z=b~1N|7jBtH!L5e98<U|#$t5^Z+UV1W-*t8bAer0ICtB0aR$+YWjr7nPF!~ocC?? zzZ7&ixM}>=(Cbrfgx@?-U4P1@XMU*zW zDLQp#_e?s;l;pptVv%-n)8f=Oy5I0suR%T`zf|oS7w8cjHa?{@L{TC^!t^!y5{;B!I>}D;RrMatf>+Dd~rZtfP@ZLnDDvpaV#uuRy&Xb=IR+ zg^xQ@)ky0U{-X)Sn2CfUNJA*b#uJL*rG&y~9jWjYNQGY^sqo)VD#jco6+xpVgeFsO z@S%`OE!B{Lb;uA%5hTn^1$sTn_!G)Q6 zabA~tYVPpdOugDwsXHpMEITUUqAA2(W)Q{X=1mcf3u+=$Z%gXvOZWW3Tvzq~zJ^?P zI7ca~LtI`fl4tHxd#hck0!k5lr%&-kS6{k^O;_Cqy{M-U*}#BQ1ZrPibKkzaJAF## zk;)d)0$9S;_pJY!=uhbo=tX#_!KNZ41gO|1fl$F+$!ZO6&VA6Y^2UOpCFQEYevVb`na52?TfBN^^Ik zNv>d!ccm&QVt0f?RQLSU1x*XI3o91-!&sshbCzMgHNMiVP124&+CF@k1d(1%~Pkp7OyP32Op@VSASa#t9ejKnN1^_Xj^unP0| zdWn>{U-&I~zzJba6(y$uzCo=;)U4LxTU9HvOO3Oua360AzCz%{bo=}F(7)b4bXLjl z7k)?j%aOs~3Ho==-bW?$pPDs(HuvVSL8Zb9pkZN()#3Fv(2emdZs{ISu2D|@48Na& z67hfNw35(*0eDc9;8wmt<7ca_&m=qN4^F?5YVU7K)%Ga*PJ;1D)pcn5&L6n%#}d6S zvF1OZJ+g2!Ihy&&Fk1IhREe!?tj!W%MEVNFpV=74pDbIas+HMB75DWSl#uOOe<0f; zoKr!6|DdFU)JmsAY9(z_b8F6_6$4o6jB1t8H8}yaa9GXt9435oRv3e_5^|>qwg>;` z$6}o&zL>OqzoF+DZG}(HPr@MO{300f0lh(4QGZpt`qt9*EYoWDNx@m%lQ!@hl-(zl zt9&Ey2tB0ZMsy=Ci9#aNC{gIUK+`2EK~q{N55HTLp}AAFvMNxUq1k`y3VL0xg9jg$`HwY%n%sE%Jh`j)8oXM87G6z6V+(tOxR$g=XMT8 zY)oIj<=vYSVg?bpf5x5Hm2cdXh+CLm?mkP^=Wy4XX--Sh>3`%_I1`*3K>Y(m%}{Qk z$?#nigLyh#rFNz3+grxXDpy_8dDjpcEQKjsj#x!mnS{&oBr;+?x7zst{;pJsTY7%v z?u;bF9P>{aE2JKCZT8fYsH*fouCsFUNsye6#JlF*Ew1;b3z>Q@YcNvEkb2#9P6{}x zr{D3!9jnM7GPiH9c6b%;tL;Ok^N{uxYx*(lp};R?1=o+SZBHBJUal$CK2QZ`mkLWF zsFY2=#XT zC-?C|&=$y@dMfv#gAUK+o}Oq~d{vSWNoe*@U;4Uo%~c7DrTwjhI+4R&1Zkg>NqZBy ze|~|uodCKYkPxZdazLUK7-B%)HC0o#?6C2)`JfY zX^X6x`YT6&A>HITAN*2!7k`aU|0O>D=%UrWm+7YQH$rb#Rv$lcqPD(1C~Ih)_iSTZ zaD97P3SF)V&UTEL;N>fXo_F^xkM)g90e=ni1c*BH`NLVkm&RWXZJKg5{QC48+MDgk z<2D3k$)SFctvxM6;usO<;t#$zwEm9IKm@`wgvqNzo7TF}=bzOIt-lLcj9Ik$_=(rN z=qBIG!NA7=SD2^p^Xs%t_{Ih-`NGT(hy(o z>A?b<~)vmRoZD z)LgC;`aU}vG#4Z6pV~W*bL{fkk?_4K^b#(|35-|oJl5!jB&Q_j!_P?0?voSJ%*(=T zgGP?rwJi13+wF}738Hi;I-#3{}ilHZcDJvj)c%IqnFR*qPvM8f5^N*?IW zWMybaYXdbTP!R<;z`)2}*Gd`XBDK9Ga1?p-T&a|gI4L?2ZlN+a?-NG%y-%wFY1VM zV$RHWhUbE`r55u+G+iS|7v%<>!lj0SL~`H3@={2TNZK1aBSxR&%np+2x>6mxfpL*v zC}6^Ccg(wF4!=}<>^T>!t;Ni(kM=TGtdo#Pzw@qdwxbMeD0#KEcV5s|n^)IQ|H_i) z_zYOm5g%-Q>G5EXQk$8%J|upr<;8ZWpp{j>^hE`szw|ZV9NDxw;mn?>%B{OJzL)(k z#hjmemTrn}TySb}Jsuh5S)p6GuiH>%&Yo&gH$gh|q`>T{_ErH!Nk+pSl@U^8pcJv2 z-a_0k(DR_3MDN0+h+V3pJZ{!wskh3Yogl@fEuoEQ|36uJg7gwtT;^`DII;`yu39L& zEiNJ>f-^TDOI9n)Rir2*!aKq%l8fs>MR~_}5>anS(-(5P{3z@b1nq+Cfi}1i>xlGt z?00s=N#;L@S`vLJdiu=rnHm^Fl>GB5C36{8W{BKJG)PHZoK(#5K&56Qy)UCpT3jV) zeV?{t8@%*KO0KbP0>A5jDY`M{Jl!<+Y{HoZrz(twdVvs`7J9r9{Aw1PJyFVS@Al?y zH`5{$LUWnj4&41_#BHHR!0eXdvb#M*2S2HTxGa6^Gnk{$kOTIaPumK+`@B`M8Dcjh z6DbX)aQshFHI*=eX$@D~b|5D8d~ z)Bn^l*6_Z}D^lE3EH6ipEao1s);J`S$WF37?ucj*?@$uQYPIgmA01UrS=zjI&YfBYHp%^ne^bJV|^eJ1KV4(mgY}t}F7b zNHIo=%C{C(dCzE6XK1i&-A)<~Gbll5ZyZMvbxJB;9a){E@;-%SG}Y=BnE)#Se<8ET z=Aik(TV>pq+g7fNjIhOZJqQ<^tb+DAerYG=kQ6aqSCnVdJn6ezMMR6Rc1vH_W%br( zv}NeRVYX*zu0xAfm)4%CPPm?3f8a#S&AB%gTwUC>2Pg zsB2$gFF_u5Kx|I{;@p|R!ZvO@FRQ83G-U!7mz( za_GH!Ae&qB5xSo39p@N}BY&oui!E`$Z5%E#ey9`lq(zD?OOI z_fQ7!kr(R?uS5`zk(S*5CN1)#Dlum$I$*Y(`<&!{=takK!IP_IpZp#;Z%-zohu=A( zQ}{eaSh_G8r3#OSsCVAyRx8kD&;GL?WE&xV^<#hTEcxu!R>#Pg?4bJg#+0`(^>T;` zJyv!ZBU5;Mi@Z-Mg8odLH(PS2s=ccfet#woccsjF2_jxK1yZhv8Sg8 z^LWS#o^|O#g!Oq@a(sY}F$So#H{MzSephA52~)?Iy=%RyFZN?S-5NFLT42?I9B$1X zbTh}&&@Ax+?JNK~mh5JU#C+Iji!SNDbIdN|z-X9-jdECN;bz`ISc|w^rulG|ZAQt> zi^rDO>7=~r9dSF$l9QwMuJu;khThz=;7EmcP3ZG6_26q^F8FlLnyjAp^PFtxL%Le! zJ!8;Okx#_Vp3otx4DU#E6+5HC*_{tsc2#SLFC{VG_JgXJ@Fak;# zVf6tm2-`Bgg88Y(V|)2Jf2aF+h8Zn9-wvq6Z@ZtuBPjQAgY4(gdhI7cPUXn_s;vFq*_IK zf<1XMM2$i0&Oyh%2Tx5Df4|>uYhW>8XWv51$Mf7B5t1mpj{GH$HP3l`>EV;=2u)SN zw!(&4i3O)cCPK;yT?pI6tr3bKsRYXa&ymF*YcIA9??|vK$P?Rg&_Ft)9j93a`9KsO z!wGHnalLYkJ-5dbQ4L9vc&3e`m-kt3ShF4b!QcrsdKlTbzdsun8CAw@gs#Ar80l5p zSv7q1fiquZ84B;9(zDs;$7gXjC}d~`PGA=lsK^f4ASTE%N@8W9^}y-ya;;5G_1)G@ zU6!8rctfRGw0fdFC$e>1LWjh=`oB-@T?Q*K73a`{sHH4L=>s8lBB^&Zq3KqoMl?l? z25*2{^scV6V$V6CCv0oRZNXW_3nH@?N_(FYbV;Y4tuXNFVl4_mhqH{+N;N@7e>|of zi2G0b=9ALj`4OI1Vkv>db6^&p)Ar7u%UCY5YS}61IgIUxs1({P*A-kaxPObFjab)B z#A#dx*Y>p6#wq1nkKx^qh_V{Y1N^aOhEN;udJgX+itBTLli;lT-&4zA#;m`VcU7%0 zbs=tc3;K(ii*A82_l)y_-NeMW^k(u9Xx0=)DBu8=YocXok(gG&wxWh4)$r{}iA5)0 z!%rBa8Cr-<=H7XRgj&Q6??QW2>vUX7k1UK)`B02<9!PfED_`|)5OaDy@QUop!*d3& zYTQ3;J*+v5;1U_|ew-VwTVPv$YF476#ErStD>rV=r?4La9(RadYh9tpBk_j9tCdK3k8y zxOCIAkvWXBdy_@a(jK-E4aw&cj*{AnX*t1$f7B0^nrlG~e_7XQR)sSzD&ZoSIvoP`lv7 zVKb!_BAmEl4LkV!aB=&2CsroA%*s1Pid(kCvCbDLG4DdJn0aE6XgE35D;{>{rG`L_ zl)K#~&0TibOg01%hUS3%#aavK+;Z;;sw`6Y#ZwC3iBy`}dw$}4?q0pmyAih|=0=@} z8XsL6J!GcxXdA*Z#{1=*y9xHp*;K}b-Qa-?^^hZHyr5M?p7BJvj4z{HrX$$h9_ZcO zJ|btn+^HNkg|MtxKw!Gpi!fzFkVZP^}7VUwZBAMM_4I1@x#OrZoB?SOFYrlJXTnCeDi2w%jOZ6 zOq1%?)@)RBt#@QpX8bWY?I7W_gXA7X5$x8XFo)ET3jJGzAyANt*NjNv2R#A4ZVjDi zb(;@wP%@MdjUG^PB9sKaHG4BB)U8$D@>p9lwTfMk11CAJ6PWM!cOUwfbrOD2=S!>C z{J8ntre-ujBg(=1;C4|nnxq+Jm{hk>o#MH%CIePYS5PVRf0+5OiHr{DB%A#~XG%}d z_X_CM&-&h|wsqZk@Sj_}RmDAO0~&0$Cvv%_(6^!2Ge6~R2zjE-k5PaHez^JUoXOU?e-#|x(v zwpY)Idu`SM^J`}}&l2)BpEW@F<2yGeDg1ZJvQEAhOK370md|1*x}$-JiQ^?p5c|^C zDEu;#6ut#X3ZGGn6v5*bDuU)LRE$YksPJD6;F_cut6m6Y77A|;E2!L-zE;eU&i9fX z-dbs9soI0V#&TnZhNV@q@WRk-?bYKJbA~}KB87%ns4peBtedRD?37w+CUh+A-x*$S zVXUa!+yv)t3@X=B%vPqtY&g(xP@olGG#{`P-0h>5iHz z*TkHLgB9i}CZm?not+`Txni)HX1wZMY1{n2^+9wSqLe?DbP^j79&*((~tjou$hm*q{OoZq;6g8O@`7mB-N^UDW z{S(CvD=_%fB#|I1gP%Hy3?z~afi(-spp1ovAoW7>Wn!V><(dWL*o*}r)kPp%2jr)8 zh$4kl`7%t+MaD7#L(5GW5gEGBopa5i$rDwYnoML9jpS!UlONccBEP;vQPABXNCjBk zKJKI5^p;VnEG50h(zHIjFhc|KjqF`7GFSu9YDcA+&>lB&1+}yQJ!Xb_$tulzX2@eW z@geLrLyV-EYutT~9FdeLnASw!R8st0wgb8-^%ch$v zb`ctJFj86Q9(1Hc^z=udC0PAZOOcH2>2Ve*YJO><14!R6n$hny0Cg9E!ZKtTYQC>| zD^qDE55iUeO)-j+HvJJ;SC$IlS?tJ(aJow9lv^Hw#Qy<%_1%aZBSQtubhFLW+#kG! zn86jlNmCT`S!MI6>#g}t90b-hXcOu54oi*ggq@5b8Jfj~3E1YtAV-)Bl7U=5oHH(z zTGqP(_ry(xZ6(xPX%;k1A2}_*JcBj+p-rB?=1_stmiUF{a9_htsZOAZK7`ZhIe+a- zu^8sb5JkGmEX{3dI0bRWwh6r`6P>|Jl=K`i1f1%3V0_KqCy!JKI1?^*J`hp|Y@ysVV8^1z%P^;W2^}}Fl#4`k z4?xEY^QV8PrkG$;{t27c!9FS#TBqsxV6)JhVAFyeBC_24w4_=|{Zp0hsq{F2#_w9! z!;(Mtvz`hRZWflMuLq4lEg_Pn>kocmw(MF?gqv)Gy#BdodZp0ox#z_0oGoh3i5em> z>F!&ZEj8ul4`&#u4^O6h-K{drlOl3n1oS2XQQAtg!sQ`I%BW+vJnTOqaFH}Af-G-& zDw&69FQagQerI3qFEytpbb4~;da%uJ`w1rJf4i7&z2mKGYWQi!`|Mr>gK@+~Ce zA=UGlRFUriXBCS4I>a@aB_iOUoWw&- ziY}l(w+hh80kpCTmk^l4fUQ8^Sjpy`{$3BPGprq;w5P4_NYx8Gc-Em_Pvw?wmCfYY z|3$V_o|0-t6#^Ia8Dc%Xplut$+&-Q?x=Jkc2i`EfUXRYIUe8W0@L9gVNns zdoDIjH!0*59q|^i%LCEO?7Uu2AyaeQX_?wpWCA)_Cg2J7??G9I%|Yh9T7khQ=C5j)DIk;3_Dqz2g(})3lv0NSkt(vGNvIF~_r0q+MK;%ws&hbg)B6Kkg^m z#v5&(O?|n`9!Eh5QqU@Me#U1%?&nCxC-+TJ@au$q{Xz$!y*gtFq{tXZDXCEeq*LTr zPAM#%ECIQIoc6wJT&{GOOt4gkGxkpz5k%zB*Ojyzp`MZZx;*C4^wTkQGelG(6CFAj z3r!G)IvR1iDes~S+|s^bqK7+p@Ol&ZH~*CIj}%3zDF@7)X!fF*3?0XMO2~PsoEvq( z1Qw`oy03Vtb%`6r=D0!pF-jF^-hDzx$$|x&o5PP>784}baqsl_vu1Z>Oa*^sHY5b3 z95*S3HYY=?MP@%jSFD|_HG&S?JN|Citdjpqi^bZ_s!0*tKfA}W^2hDUp^sr@br%&f z3O_$;bM;f~cim%qhgymrBg@?Z+yua3{f~*@R`rav)^$!ht%W-_51p2$&r@bsAW};s zU$Amg>+epq_IlV%t$j{9?(0^Rt7UVV`jwtNC@QajnN&N_4)=CX5TSEgUL0x3xr1=L zPg9kePe9}ka90*KfE_u}Y1OCmuq|<|kAf)1cBAztYAK$>XK0-`mJ(8nBd5l&vQz0? zn<)q)a1cb`Ac(+05P^dr0tZ3_4ul9C2oX3CBJdc9z+=E7U(VE*8*T1QH}Cv)r{sW1 zp+A5isva{W_;WJKzYyjcXz6!~p-oFK@a-w?=p@Z$R7F?x8!@;5a*v# zxl=LJlpJd2+?u7_w*3yE>lJ-6*3%uVQEN8DfmWb|Il02j?Sh?f&{wIs-b^+Jq=;D_ z*xMAfC3{n#Ieo=<8M<-DvLqEd6?!QW=yWT)%?+`R#2E2UJrL;;gEiyred8ZY_8kT5u3jMd= zVJ&=-HTkat*k#-mjD4wLNt7LX&gz{Qo5=MvplALF=FuxrNJ@{4k~TjiBFE0Nn|MPnnx!FYvp8CE!$9;|SH60C5l z)m7!$E01_-@GcNOcOJN@m2g7zXh1<(!CS#^U8m6`b<*sjyu>+{upT5fz?rp*dx`Pb zm_+*5%G_o+!7fZrQNea@b+ZQ<7{QD$a#|J_$1>(!(PqUMKQi&EVyslE2$o981{%2} zDd#n)6#7==mE;ze;>m`2B4tji%ImUMgy;c#CnxD4YgHh3=1jjG2P?=qc>=w*dQxq% z)({vWl_na3vZUO1p`P3x#>+dxS76O>>NJD#N=$;YAqm&l=F#3U(hPpF<%7P&Bv@7Z zdM65b0>gdV<~vE1GzPP)8T=XKfpMq<)yDrq7}N>XWlt$K5;CCg7O zFq<2>eCgQbv(A0`%3G{FFu=D+b97^@Z3Oe(MwLkG8KtQeBJ(I_WA(-D6F^2ARW6B< ziDM(U`>k-kYXR)J?W33pwHv|bd*N}j5!b;hN1VwkeyixOane_cG7M zDfdp7B;B)=Uirg)%m2Q|@dF;t?tz|h`Jx9}WX*-Sn%!ns^hgfU`6!0BVVO>Mzm#trso zUgTA6^-{fpXIcTih16FeiH3j(*@UD6LP1`vYR?IY*~U_rdgpDvoF4yt*VZ?Bhy6|q z-ofBT9Fl;q31kqg>Q&qieuTeqW8z^UI$KHgp!PCX4K9Vp${Cn{K9t$ENzW?A`cZG5 z?K}dJ8TLLd9-%nVgCbaxTv(H-&aiAum0UZgUR4~U84-1x^`rX?~I_}X=lH0m<@py0Mk`Djxi(M6WGcIQS@%h0EK3*_*Vc*PEvu@6cnSFe= zYYNCW;53PEl8RI;8D4Afi-KFvM$+(#TtdDa1-G1y65H*%^G1ri|)(dglr5@a>txn~}@wwx-mFJ4<#-MLb3-+_2)~$2lz6PZ! z)hT?7kYem)QW5-E0zCSB33oH!g4@`KNToDFtv`8NXW6=2ttgpCh#PjHyyABmZoU&mu6V=S~}+a=Nz)_iSz!m$r2fzT-tn z75-nM`JWk{)+;wE{H~#aKAyJD&GOH#vD(sKXxINVBK?hsRGdcXF`|1m+FfYrsw3Go zq{MP(Dcrs+xFfFXMz`FR$}*UHMWSKb1e~>(=!6MaQrX%CqKI&CR-F#q!OFB4)$6?rd&Z7Q?O|gK~A87d=Ah zVS=^9X|z`=*V@*Y`q=JGND*`zQJIRdr;&JVGU{^U+-N_xdoAL6Yo$<|!nF%^+)#Sh z^V)TG8cXdx#nQu4Y~4EBN@}r$-m1bJ-1-&v^i%B0D%`r|+G%ua7cukb+2LAll}W-a z&mu9UA|23odrs+`ozgeIYOC&PTeqq#)LVp8YOqOxLd9Edcz2o_rPZH*jm-MhgtX;C@|#F#Xc7#`dzBw4 z=42nF-S+(E!@l#vXES=^r(PuNWSg26c(b{+wn-Lk!I{8W`@;+ucztv7vNbx;`(ZTw%5;f zHgEbL&-;Dt1>1Q(GM?M(^Oo?pDwLLGUq+Z}x`%RID3SZ2<=U4Buj^q|-;4b#OK(FC zbhIhBFtVN+1f%v(sXcgSg!&7XWCoTQXzW(9B$1d2S|YinUrA$UFV?w+5uGy_ zLQBM)QWsFJ&Os)cR`^~(K_A<8RrS>@g0F_8hx10AW}OK~)?+k!&qTgj|Dz}w3DGR!$>B^wE3O%dXu5ZZ zvh^fl-x!H(yCi*F%V$z{WFb=W7l`T3!t3lC&T3`he<9JiV;cA41w;)NXq$NcN04!G zgBvk3uv8rBfhs>y>o31+_e7&cl`aNf zv=}IYw^$Ef*PJA<&FmdHJ`tiSk?w)x*3d5lwYCkWhley!YP7QHOZ#^a)Yf-R*fs`w z$Qs;{EpG5bHhVPME!g^Me;Q{Wsex5^d^{hiu2lnLU>ro4f9Dmtjs?O^T57aNfwr1X zBX-6Q{nXZB&nSXKg0pSY$-XPc)LL%nNyK>$LUp>7@&R8sFuv;3hndLPbU)YkDfuk^ zoz~gh=ue+Z{EFR9e>?sS_zKPY-xpF^@+8#{Ck-GK<@!)!yyyfcQ`#NTh3Xi~wL^p@ z>r?dtIEUfP=LoEmV3R=;x?@=OQ=jjReg3eIgrk_lE4s&j`BKB#3Z;U^R#W!{);IXS zL3U|kZBHj@HbGPkJptAtfmxFrTgx{(n+Lt?IqzUCYfV4>qV7vjch(?UjQ>c*{^`e& zEZyP!)KXqgb%*HI@kFN3uOI}6Lw^RHt~EV5q`~^6wkqjV6-#$VKjVNEK%ajkpJ06+ zw(IkAyFT~-N}st;_4&CKcDJ7D%HA4y)~BrjPgqxj`f{so>DHCu{uftqt3;U9xIr|K zLR|2rXK#PjuNvu#JuDK4HfHFX1x^o}C#mcUCb{U{D z>b&6a-nIc*BNv|(_8JHp6!SlZ-&m^!{dd0d=e~&Oaq}!$S_*XK&^;G6HRh0I*J!1RAb~yec@JOjY zd!%!9gP+QCDj?7w*5&51w-Y_O-_JlZd@pHoY;MK4T(HU|$im zqZn^evFp1>;(j{N(93VjO#^m@`}uUt+<+1A3X~t@G#Eyp6O2GRmHTiSK!5j~$`!C2 z+Xtp@YN_47{N>;HmxY77pZk|X_K~~yS2I`R)0yilRR*vwHXF}6ET(#}wQphUn$Sg< zbzFm4$17H#hds<+@X5EO=^DawSYd0q=`h@Q80hI2pl`Zwz>gLEicZE;I-~!k4$6y9 z=qx!;RN=MUk5=M=4$l~4;Wudh>%4vRSC#6T1ZB2WeL|;PzaCB{xgXA;a-m#zy^#Cf zN+%fP8a#W+b#S8hZLjPzXj=OfdHC7gzYm@w^|yZR^`lZQuIwLV3=MPGGX!Va4}J7N z`}Akv-U>(X9T!@GCj1`Fg|9Kqa-Hq*lfF`&;P4{dQXQUe;d8h%ec`pe@!X(6x6@y` zSe0N1-geAB-uaH#ui7@h=)s}I<^dnhcf8vC;#%WaEzHe%SZlmBVAXKjUBV5g&py}n zz`EwjuVndr_9k{co1Mc-nV<$?zW{Sr`1Zo~Zt9OB{uT@7zYq2~%FSeb9qfY`E_C&Wn+y$C0EeG<;8_m%T zwWa^b9*a<@w&eUb;@Uk4%hq9POaBGD+p)eLbdmRAtDwyLSbfVXI2sy$0?O~3E>^8u zL%70v)jS! zP{{s6iz>|-aGIzsgl}}<+rp8ZoQ6VhIuG~v6h83f3SQ6u*RX;IDnf(5>Vq>))p#Ag zIh=m6&iafxeSYajn0nVncDW9AK*=(wRVL<~iUlfSaDBPJW^aiVx5(y%)>fJiX9wjB zGbt&Skeq67>Ax$#J6`jg4yKVFUsshL5Bo27hn~Q_*aX(aysz+KV6SP>>H{aT>+!91 zd|y4``inQ#$6gEhX6?0&-za>K$}%EcPe`YeV<^}^D3mGuDVf5jOU6#}g75r_Zd)d` zAnqkEk{nYKEzaK}!v$yg4(2^`sk5b_hp;rvL-+Ht;Y_{TZ1{UX06uk5xb_f= zA|@cpnm9|oJl!kU%u;Rr%JmFk*+3DnQ)^akU|=LLa{E~`wDx5l%lNoB<#9j2t<@am z_PeO)L*w#bGqv2S5pKu0qjms@t{sKFd9z?|!g|8dQdBC0* zY19^+Jf3ZMH47PnYY90Q#>f%;dPGk zXaUP~^()sbL%t#zNy?SXrzk_q?YSbA>x4)ywK*|Ed!!U3SO*eh;O4N*D&y{)M_Q1Z zRknlqJkJ7Oq=|)|aC6~Fp>o4gWVkds;C=IeH0HtW21U_+f93jAL{S-5iZMj?$ZVqQ zM}b~l#dTNAWv#S?g|C1eKzatB2GGtGIQcv=*f5=u8)o##SSP8R&<5qOA8r%Hn}dm7 z7tV+rme||JXI$|om0P}7O_#BWGJ^X~CRc7)hLnSwk?+Uk>x1Q-#~X-@>63Bv`}FfV zqrZBg&TScEud}`N*L57kU6K}kuD zarmsf!klyi*Yl1`_YmW=A#ydqyCTC1|0Cma8Sl#m9e6PV+@F4=KwZc?sn?UsWrld) zV7s~)`y69K_efEwqYf8d2RrTZT z*X6{^$BypRdEfAkW8ut4b~)*C`mtZ)A0HlfFEPot5F{?g8itxQoDE-wb8Zv|I)O!t&u@VfCowJT_EJ)>!_nRvOgs%Dv`zaJ$p$J& zxdr@h^?&T-|6cp>ec#d-wQtnferUe^pKXBnm8{fN19C~Lop5UNsZmvhaL@3d|6z0P z+u^lh&dULKc7NFXg^?Zf)gt%}ha^?*}0_+6KS$SZCi zYKH#`q5=LpFq z-zKu}xBYMhjnBazQJxCpA|YU^fbTuL26u4Y?UCRSLsKk_nV_G?49t#x9y1f*-0jwp zj7V+v#R^+z{Sn_!4AY&#H}=b>XFtfU`)~Yp_xSpXoHV#Um!YN4w|6+h*V}l8Ai%w_ zUeAFWzg>B;HAcosYiWR6Z_Tanm4Rc8TV3Mmpe%t&suP?2;Y-t=X+{R)AsU_*%{0NC zVbCunnd1NA*)l#^_P+5sz6l!u*6=3WTD+Qc6`xKE_{8}vNLdQ=BYZk9!4ije3B1Ex zLrMckA&-VU8uFy}Q+$7T4}y2_5(!pD^$OFIrupDMdve_UfIImK>4$MskFgOR#QC@s*TD{;5`TtO8@u?;C zskMfe1w@XmLx!;wvL0N~OpehYF(*fN-K@+p!yI56f#aWHp9WbPa)?TESVhA>Sn~#$ zQ>L!FV;Et&mUqIeWU>jRb|aC#o!loNrFK0r#bjOYswL!_KDlICc}RTgy>a|=49d%UTb8?XX2JgDSf-bO%=N=+8*HT%kA~1 zgtOw+Ze%!IN7U1nRw%bi+beGIif!6eZmQh%0&k_1`Jzs)+oIwbm& zP;>Yv&t&$*%ziS!R~te8mxi2sKJ2|+y{yBOq3`Vm&UQcJY_5qNHXtu8K^_*!6(_=G zZ#uv_-JdkK7`Q8b#@#*B*+uL(1N@sKrmAM0oF-J7-!C3ttOV_>+dg^w3KKir zgcgC6fXd3n{y=4axar+u;H16*J>Gt7`#lp|+=@%E;+L^b#jk{$68;4rtE#bPtc!wj z;TCu9=ckmjo6wo!%3|e)UNkOmm05hM8!KU*{iI*aePw5;`F!#5VvFuR`X1~gt)qA)SlEzvf40*jcH5wdngQFGeW#aoI;WrevyD!) zTZS1e9gjSN0-n^UaxJj`>Nqc?wX$ zR%~fFNR*pdlNDVtT+9ng_-i-p%vL0r?ty1hY7Y`qw}+an=cQ|U8+6v;!?Z-``xdL6u{ARl~to`!;rR?1Unz*t*@R>{|1BeKYJhZ4t z6fE2IYt3p}S1}Qi5wxhSkNT=;s`l~SZS7XAyR{{TB%%V+QNU`uRw`J(yZyDKHEw_1 zDhP?%7R3i(YpqI=KGveGfOZvrpEHwyeeC1+2V`dM>)dnBJ@?#m&plUm&kZRrc@I_x zgYOD67A?uKI@Y{?QGqvkgBGbLx=O|s6LuS!w+n&a&q|o{f-?R-JAD>ZN5UIwSUn)ym<$=Ah(2Ran|jC)0n`8)8l2>AJo@w#>om0hmmZ$b); zEB5$W8IP}=#YvQ6qC$Ovan4_AMBSX_gNnb#4B?R~*mnzoy#|5-*h{+mx~Q`bAG2eB z$@~&=>g{gBlmBE4Q$J=bo05wx*Wg{0QuYXCbY27mHg7f~o@Jqq$B|JK(e3 zG9Zvez(^1bDV8512n@?tGhWBur)0X>P}r}cke{R0+gkKSYpG`rZ* z@i=t*aT~_)frVAx*7r(r+Uaro1?L>Wptrp=IJ$1#Z?(OFtu z-GeoAs^=d<%z~q8%pqHQ39~Q*8s||iIfIqwo@VoN-Ye0k++^hI*EumPkA3@)9EPYb z8(%gV_?H>mi?i57#Kv2SGosW?dnrs zG;B}Wx;xjfDUX2{J?G(fm~2;GX5`tALL*~t8C}WzSJ6(R_CaUcma64c z1H20_$hq2E*StG3%uz|z`3`8roSf@q4eskqVhx=smvzhy?D=phd32gjrWwXUl07dA03RQJ2HnEjWw2W!N9$r_k34M;1CPM0G;Z%3@Mr?w1xTGTzw4KA=->b(P3mVdG@cO+_9#*hLfjV=MlMSx^2i-CewKjW1rM9WBIIxS=M>`=OxWYFs*jCn}bckDTvYvL?&tNYTiBWQpA!GodcOOV<*x{E#MvSZK+zQ)(w8hptwp-t?c(B zV&rwyIZLTC_1rO6l|-dOEr};GPo|!KVC=r!Xs?I=C$rhSx!U8T-y$LW@Jz(=8RLT$ z*8MDVAAB5ib!W$_D=I`T6&S`=cLu)+jP2Nd^?i9Q<1vjQvwsQMW#EW)I9VU=}w5<}ldm3I1Hb zUaG>*y&=So)$a1s1(6o{v|?RD4)G(L#l}=ox*|Yk@ven?)=2!|!~bnZPC6 z8F^wf@(5^8p!SCv#$t@Ddl&5m>!}}%`WZ)Z71~5T{GqORzKwk9Upi1TFA~`j@Kp2jA->Z83Zz@nHa-ezpic;ST&pfL5wZYEZ|qqr$yL z&J*sSOHp`Fo;g}|{38!e?E*(Zyv+>j$4bLsm627-U`*Ya$MCG13FZmHVfez0c8b{l42${2o;*K+ zMGT81ne)k=ZF!z8>1oUJMTv?pSKlAQvo^U0<{*9zUnR4M>-bzxTmKTr=G8rUei6rn zznM`gF9gT&Oq^+_F{O;T$;MA0mq#311D=aeaE>t>7=L{g*+R79mGK|0mP4Jm|3fWP z)JFy%L(XX-v$Zs?X*@$_Ya#0pXQB%65$qh~9EVeF98R?%8nhkJpv~};W)Tg#iiOPL z1M^BJWU-)6SRy!5*if+#WYs-(o#+y1ZV~h&U*pAGl40OG>?@IM5}m3%!JMOmtP90F zgx`AwnPPf^KlH=Rf_~IWUJL_2^$DT+c;w;rNpJIzuhFOz8s*#YE`XeI5wGKy@G_%b z)Zc@&QFo@1T*g?L5!D~E5_ZP7HKGprgEE`O(TtgqkRKY_W&L4VMhsCY#~O2t0#cBqvD@A{}u*`Fo(vGPalc-lNQM zE|M{TRl!&N0^k|8TEH5lffI0nhk&p7J^i3Gd{bzI^tKuHS;02t2?Vp+t|EKUHqswd zV19lZ`|~!dW+*W0!I%0fz|5gu4lv`_$)RjjmMt;>^Q+-0ww--{1KNO=X0{jiGiUUC zBRNR;?4e6lrfmq}SH&aYkZ=k7W&jrvLB8nCUj%Gm0F4Se4`4>wz*GQHFG; zAMq1wpfYl>ohG#%N1z><+W8ruRs9d=S~tkvBueY{py?ioZ=5OQc6aR*`(xkHlJI_)Nm#{k{4y%{wH2>tp1; zC>yF}jHjWSC*?lpNUC{G){;E2k8?nmgWO4-GBk<20zh?(X^%xAaJMqgHGdt?=Zc@k&W@hzz@ zKwnS;xSk9m@9ei*DQ~@Qj57VG%#1*h90lz=|&zr z3IAvPaJz=|e$T2i3{GUB%_8iB4TFv!rP1GG#%&H*=Zsu}HQGvey%#tuE(BU&Zl9>?3nbG>e=zr@G(@<2PSxj0k3ip_uIeL$9&Oq7)ylk>U4K8llRgkg z4^?pbw0S}x-Kf+HyorRn?4l>2|08m0K*!83dK~i^bXcr06*!6>gB*sgf_J6;q7{%+ z5mYD5A1J>Z;}(1o&`+|9mLWY{(Z62zudxO7v)6^SY8k-#v|WKuDWlf;BEbYYX+ReZ z!A02WRU0A7!NvRgd1uyMXyQ z1t-~Nn~IYntO?L2;Y{rla7p;nk}mlV6>g#d&ekhysbJsh=ZL?>ngl$r=J) zd74d7zt5bG@)4?D9gwZRpnC_~CmkI86R+YXNT;Z&KU#}qM`fbUkf1#Jv3{G{lN7vTPFHlJ?3t-Q!h0{i`YPpu@7eXgZ63lm_2RvLe6tSkz4W^u z=?y`=0pFnkeBamHAKz&WiTN}LBgt*UkJb$;oz!)M8Tu~uH$c1WsNehq-v*4U9(>=q zMp60=KBTn@@cTedJ-{d4r`>^XBaKV&^HeIM;+palWvaNQwv{oO(Sz&k`ae+_;P*(d zA5UE!dIMwWCUkPGV>l~7@8#rt*jvy)+27f%zXxjyt-u&M5tVS{FrMreGGw-44I(b3 zz-BS>HORNu7%?CH4aeF5a$Iyl_lFLMbpVg@uxG#qGTe;Q@iTd>EpVn~B`3pk3UW~p zH-|um*IR9~_#vt;LvRP?0+ZRK^nWA9W6lU6@7n7?gwl!@jOWggL?EanZ8f9m`& zbGkaO0ym?JCUOBCzs+PHAN;P!2b$x0%0x{Q1NC6;y}P%JS(Tp(JecoD@8JXUo~cNW zHA1+EwTQZo3AP`V2$@P}$$&SKqrtuvC4eX5dcG?NUsU0UY`Xd27|-R1@G!XPdg z^ItO7>47y?&)UvpejYp#7sSyWy!Aq`Z@}*#VHX2G0dDBsy?CGbd~cqrHQ>bo1g}xi zqd_moJCXsOTO|R#w3p{R|69VgnP#fG2;sDchl2E|dIs_hYu}%a5%Wq#PagnU1ax1T zYiMqvcd|36_yvDpoahtYrglVvh58=k6XJhGwt`QP9u@3I&-fk9z9{CSztCZ2=%HdR z>{_IYmO~dUuXzq*CW7=s;s-^yfjw8@N#YSFWCyLAP4#_#-Y(e+QLi%Y>O+6lt|@9o zuno*-AO4gs`g^E9^^bBR?a%{3bFzEDjzaUIIwnXKvWq#;!I5lcRa=0%uI{Bd+hYsB zx)}WQQ@Yka(o=U}90l`$pXN2k@YTWke}SLoVop31&*>Zm+Xvwe zHer+fq2@ULeU*QJry&2_ggx*lFnS(`PGXult5*j7v=7Sq|CjjZfuHgZ&7DEJp2|NY zTY_WU{#1~!f^E?lQ0I8ejVAl=g7Ejq@zLf5L79y7C#fHDKI&A)9{NQ*LOkCif6b38 zc{YO2h(}4!A=|%V%L>B5B6gyRClS0uyo>&)2iw7XyjP5cFV(#N0r?nO3byvl? zPLp9xqw+3BJF!-TSNp0K#?Vrs>^pe{mJu7B3}P%^^{k0SL;)vjSl+>)94nU~e+crU zF2kBH8LC^3p>%jCQA_0PB9XUtNX4RIae&)Th=A>G)nC7Yt{G;mxCPk)7v(C+GXE&MF|dEVW_ z$lJyS+V!H{cNy;-0yhx&s_uy#y#8o`*!SE5iE=U zN$uETE~5;i^xGq#yb#NHTrG^^3+?OZZq8}!GB_Je$~+dxC%XY>2y~(i(0wpJ%LTO8 zrb`LJWV`Nny5JV}NuW5hWjtf!++BgclYa-+bCvm;o~dA!4S1Rg}FtC5p8;6!ZKe!#3_ z6S#5Q3K++mY#5QjLzf?4Jx6&wWn zFFzc?8rpptPlFGU9eLLCSTyS?XoRkTb1Gd;tYL+MBLN)5a(CiDhVF{{9u*wOt{Xi#kX>IYI8fRm96WXgdi2n%Ui4E&f19(LuA?8s z*WVlB9%DS`{qRIUd!Qx7!=Q2LY5YJ#w3K5&!v-DT|3D)@0=jJIQ2Jn4c7~M;aJJ?J z(4Ob<+}Uk=jAw1Dqw$QhCHUqEi8dSB4`@VqOo?+)wh7PFe|HS$!QM3K-nK5Z1$v7L z{KNyGEx}KGu?>9V>M(g)Y6<>tY+X2A1G%M7r~nPU3SH43q%Cgt^5EO=_Umv`9OLeD zW!!o9UYlfSBAz<(wIL*qbxaRoJcS3ToCf>VX4_U?YlD2DI&A-oen-@raG!z6Ft!%- zDL3H+4`MP1=ky7F?E5wXU!R{d62H)Ryrlc5Ivzj2X?VB;k)^@Q%P}s_ce3(%^!2&( zoZ+E%;MB`_R(#Kh2#+d0#Ia(Nz*1ZSL-f0h;gRzk@u>lHH}pHq$srgMFMP=wLYe>* z#>8Vy7>i$mX5V(xH$%vmX2Xk3h(HSd#<(&(+{B4P`>}=yjx*T0A!mTk7Y>6LPvIH- z@YpGoKa72?FT0g*Xv@n%W`B7DFVs4;WtXfi~5gXT63q6x4Bs z!U#N9t1yQ=%-Ehi0ytk}j1iFK5nbK#BPjD6%Ey6sI{m=ex2#9F!Pu6cVr`M9INJ;D zjKSqMdAxr3d|+-U=rX|v7+w$HdmU~B654@lyE;!4E8f^7@h`H$4@3d zspbcSu8_%QJHdsrh$v^&)=fgRrz;d!4%X_p%ppye!*l9PambU zlyRlfV#%lPBWv)@xxR$vt7Z8kYl6|H$Pb^5N;>8xXe$U>s>dCxl*fCeB_&sRM_F?| zm7*F5D_F9;sXUk?y?W#-PEPih5;|!$Z1zR?oEtA*aX?Mkum7tv*gT!FAT*S z3K>LmES;gCxa)L|g3cb14q@G3^^q~Ha>@hVMJpd^@b;;jbnH-So}*&wl?TspnRcEl z^AF5AU!6y1Aj_-i{NqyG*Rwx&%;pC-$ig-Dm`l`MWXI=bxgFD3e&5DXo2bUhDF)q6 zidX9{MPxi)=RvelLyVtsSg*01bdkLsyDr94QUbYBj7Wu@-6A~k+6&hfIIL!#L)!-2 zrROOwW^opB(3wJW!Gjy!4XrfOVrgCz;_b|jOq&pRQ0A1->Y7AT$wvA(>WP8 z<7ymtz;IXZ8{LWk9v?K$H@;?lNupF~bxPlvwih^c6uA(wjc2!**5%X4ByL~3GU?<8 zxxtz;Pb8k^-jMF1@^t6foMXBM+;_IIa^tw%@fbs6B&W4<#=y-yPLaD1_n0CI%FwG; z*2rL8 zulaGcl||=EtZ5q^DH?0o?1i&XD^72cBxA;$EnIk-zT_Zw5k0q!ek)RW@1`6JPY3Ts zT%S`U*}kaIs`679MA9+dyxwhG#$=0pZ4}PuNc7zNa(frz(BfT9;rsWbY@`$m-YMm? zgY^IGLDc$fP%2Az1#5Lm85Z02cI70CQ(`SPxt$qdp_)cmnqO(}$_PAPJ4l!sqzmI6 z71qcP_>6)F3fMJXUc+3A<{_(pSFor+T%N?}cl&@5!j=%#oF#M-)>bJP`$g#+PyU`X z{#D-Gms>{?HJQ5k#xIRXgGr#{dm=z(`+Y>3GxbW0q@7(!FPdoGj1)Q zIC|nNCu4R@)|zwV*cFVt8eUkPLOe#=CW?HMRDHIPq^!7Fr{N%3>kGv>BbZ?u>DR(U zZ5(LllKt^`TRno&`4$!AS$K=4gk-X~TpOqQVRB{uc&CN6n6b$~t@g|@KGq5jR?^fS zvQ{U}BJqf&r_4B1o=UTbnauw}`J`&fy)T!_MFq+P>xd4#i#k)BS}V>YDYc5aErBmT zZ70d~Qu;5q6om9&wGwPKSR+CF%RLEVBEZ2HO4H7z1?5tzuXpYhhGrfa54kjw85N*E z?mkiK?Cr-P;m7#Obp5zhc-01S1mR9{sU?Eg3BpO~ch0Wls~enMxj8&&OT9^~abji- zB|L({+??TzT3g?qFX@a5L2sT%nO-i)v-DM{7#IVQRjY5utSZ#+B8eeDe%wIJclF&U z;0%VYvzxxJDvYkefo290r6=bJC8rnb9QEt^oS&v$@v^mllWg@Bnte_q)~)6!$b%8M z#dyYrwUs7*8KgxqMM}5zZD+Pw)$F~^W7{=s+L>lGS7cBVVY4oq{z>ESDY=JfcKSaNSe~q+Q8HE(^e@@L~GnW zf;L$xUx8(y_3skFvPGxD5+!X5e9!Co?iIqbo2C+!z=^5p!=~xtn$Ckw$Df}z3@s`U z2quQwPE03Udj)Ow-s!5g35naI2Mc=K%~MM;7A8WX-kIX26j%vW&DP=PnJCHjyH1U_ z92St0SVnf~hQC)l-W9Nj3?Ea%l|rY9!PFwz9>9w3vvO^|)%JCV)+yjVNce!?J>@g+ z+lOz*nxp6}_?^;-gC+znPYB4O9z5(*XhL`(ob%FnC-r5#bA6619D*NlyXN*9(e0n< zakgj%3T~ zJKt*H&uF}@%1jzAuEG5tnE5jb^}AccF$R<`XY=*1dk1h8QaG@kpr+t?P3PzI3}`w> zFxy+5d5}ety=4sQzCE`u>cyEo)ayu+!bxMoJ&;P>M+>kj40j|6;qn<5i?|@nnv|uZ5eZ3IOgy#6%Ao`2Ov?} zOLoWD8lh)W*-jy{<YG9azHzIeD0M zkK_a=ClDtmr(X%k(LwaZK2@dmzPu=j#xIRAHSc!hLDSCa$Nhzh!Fku8+9$M{Dalfp;R3!L1OR?SI$@H&LDQosJ4YADF8EBP)?? z$j3du!vLG6v;()o8E^(;Dc_K8&Dfujlv$jqoBG{?r3+6koV=)V(Gur~C6H^SVa!XC z?VDC^w`6;)TO*f*vsDh;s{i3WDXA9lWV@{)*eHIHGo@`t&d9r`W_X>`oSA12=1)6% z&?EfQgu9P!-)1P6%wLFB^D#+cp9|5i9pnIMsx!5YOBVFbKJzzfO1_gsAzOPXFLhJ% zmT$ftd{D-nbvBF+8t1V3X%KCcYr)9_x&ajLVMS7NpO!8>MdnGLd7V;=7bE{46^x8H z{nRFK_3KpS#t|ANOvw5iNRSfnTe;*g>X;l+>gc{%px@WH9wWrz)rI8Tj+t4g-`lFZ zn^$8d!838kZyu5_yV&2H!f!{%?cbbwcKWpf`Eq&8v&S)-P?Fg~@)*A+%qII<*P|Vj zx-s3W%TeZ;8^`JSLg4wpRMPg=?l|z_0V~Y~2Yd&n;y3)jhe4f-D|7eLIAmCKC*}{% zrA=dlTy<>OEEk(RBaycHF1wRpJ|Q z6}lLYyHhjJjkALA82yUj_E=*KLaWALc^A>qBlyAjwuc~K5c@g(iXG#|9i{U4Fdnm; z6Y+g^Fg&d~h$7RD#!itaVk zSOjhSCEaHQ)WfCew4&n5q`TBv`z;-<1<7jhX08|9o%oU2nvyF!ofpEKh%b;`CE`|w zmJ)5gX5X`&GMwT zoJ==6N&81+&RJVc>o5k}yA89hnRb-8|5>mZ|djTh%F*P#3$W8;P+xWizB{&hUJZa<5=3$}a5 z&03B620^yeejPSNoFjqq6F1qG?9~Kp za=!|${v3WCVsj7MMZZOkyDjgzY=3BB-mvO(&fxzTx9xi$gIlC?=vyk@I`F2qw*Z?C ze++ZhOaCw8e-dstqW`P#e;l(8U&b*OJX@IuyvAhM=jM(jOP=dJ+`hFlZ7`yPdm1ay zGU9+JI??)^B~qo^_K=^sD2cG1n%#D3pw;7QS8O+HfC$7wcxKl7sFl}*jB_`BZEyc_c1{bTQEk_37GSX;tdaU=s@ zu^yPZ#4&hN^Wes=pUT4<-IXSin>UUtx*c+dE*ITG2qNRSg|Go>Q9>wxtw2BYOjq-u zPJ#>eMfHZQALPpbk_H)9!Z7=}>3J^8q;92k=~uVJ*~67}F0F5g zyA|mKi(yjr@EH?kMDR=UUfHoIKggLn-^df-&H)!UtS^}`qtf)sj?Xp^KSB4+5}Z^v zsaogDJhU&D#&qb%G+O_auFw~9O2GV{l9z|O`R>eT@6jnpzGgaux7ivSS;%?!hnP(g zL{~@mwL<7n_jDd}B>SCJJM^PEb77+^;Texm!O*=L+hHlJau8iZb!NAr*vHtW!s4tu zVG_5w*d>U$uiw%Ro-*)l_ej0gZ(x~DXX-8>q}_PoA6MjiD)_D z6!n_q4(a%$;j7kCAu1&|^T;?SZUS_Y&4^OQNFrkHgBId@I9q9U!7k+#g-0RT5HE@M zxRcFg{o1>l2ex$GxmN6(KOfR*eU3+X*YtN`?aFFFy@P&#ULx+JuX5b9j>@y$>0L<@UH^2%DA8C3a9M@jVx7#ds8O^Qkjbm*N{+MXBI}MA)({b}N;nJxPvqU+Bh| zrJ?b1(2MhR;%eb)N(r>!ewh1TZyliIS@CoIxcR01x2V=6STrTnTR9_f7N|B$Gw-_$ z3wSEJMZwxs!s5*x6F%fEZ3)?r(I^=#1;?=2_Mp`Mzt}j_;&;U1n&Xh zA3DOR0}qKSVwnR96@I>Al(1rySHs5FqjhqigKX4BCZ=oliUm3)03hoA&3uw~0m?`+za5 zZqjShY+Lqmzhpx`Ic@R-iXAyQ^NLLy8p54MTp*mOU5^>uF5L&tg#A`%XC5ix<_b(6 zZg0EHG;b^E=H^y0j@cI(ZuV=?;3`-j|5?6A_&=8H%@O=S$3Ee+e0lDpur77>`z+rv z*UpH~Ugr$1*V#(pDAvLp+T&)2GZET{=gvWV`Hp^7`HS*3C4ArQ2j$qoOkD|gnpPA3 z2!e&?K<7bDidJ}&G?GMNQK3T`!Bi{1W0_0B*}`+jIB7O=SQs^RSs-ZajeYATdH;HCQl%sh&BILv zg=X$}EK@B#=zccRQ_yX4BtLMa?p4^-HI6cA_-bc^`)^a`Z;<(V%^&Mt_-OU9^)e?^ zX`Y$RS?e_(*AB+euhoorSFA_aiRhYs=495T>9$SbjKig4R&VHXmpkF>^FM8-3y&Kj zhOl_ak1>epO!{l@+oNwbP)>E?B0EYEDnv`*bWHECM$G~EN=En0?=(JQz0F)VZ? zmKlYc8ph=f{Ll!_=aQu>)vi<*m+bEUzl^5DVF3?V!3)-UW+NY_+o&Tgj_67H5Txdm zU#HzaMFbb%KF5w5%owNb56#RdC*2iC`x2prONAwFgY!CWhyDUlqgpV#HE$Pg-zjnQ zjFW+GktP12tDkMT$li_!vaER4MTqnl3S=d!$1on3Y^@Zl;iNd;=l^7>GKUtqMc;ypK z+yksY>*8Zae!MdNeS-_PfY6C{bX5VJ;8sskV8cD!o&MaDCLVGjxdzs-P`q3)m zN{Y`A@rZf;tB(Ii8a_Efd?dnr$^D4?S;T|7$b#qCXPif;EZ^|QnrEul|9Sr$hfu{< zW|bGyE>g@K-CTGCnD@Ub7Y|?%jdadMmTo3%WXoscZd7nXJzKu5f0jN6V`;iAqA$aR z^n*5!(cGY8zT2Si<-KjDY?D*_H>vs0*RRtG_m|hUBfyV}^qpR{T6Te_I)$sSOt2G< zPk5-kP`Rfw=S<;*QzRKn(=Z2XXBU3kEb53cf<7o0wO-YD}v=-LN&8>}c>=ks} zls!?7xy~qub!N^y zYScQHraLSnh6dwfaAgu%kE404;DT~Uy{A41E%ml{&pgZbAolb~3jimGcGb$gx3xdL zktN&vIPE&aI?>-z5gJ8(6gTGH!pwMFv9j&G8ObH%WCrRSVRcwz3HNu|Eh%}bO*xo$ zH`0;=X=)0UAX=)LlS%`l?EbZ^%f*`$t&!NFocQWl)QHz`MZfLvI0W>0{n z#l&C?A2(toIg*7a;N^4u$j(Tr;apmEt|($%p0 zbot3+C+g}re`6owGFrdunTs0E-`d9*3d&$rQKr0i_R+KST?j8zeq+P+8hTF-FH?Sv z;d+kVrSLN4cW$^|dr@Ot^CUbOz5B=4jQ5c(*t=gJcM<-CoE9tJgz?9Wf)IkJG}+@n z;*nbMmVO9kOaF@SGL+@~Yp4w^=XX;Z_${F}@LNG`;MYrS;MY(2@!J@#=jpdKyiECp zb=EKR)$1;5jVqQe#ri#Ie1ma??NQ~aX&_pZR_g~{)WGhcHO7X868^B_&KZ9WYyXfa z0aS|}e_j+!3Hr#3T5vFIQB|?)@?{~kdtJVL&4F||uT$Ymx+#8MKE}nMy*1~U`{JIB zjEtNXf?H;$+&x7jzn?CKhF)hSPp6Ufv?jCf*HB9&%Rqf_GVLm?FJZq@+UIlTg8HCf zuNFdD2kjNSKV4m|5v6FwCYF>i%4mUPu+0~=H2P5^EcPjRfw63<2t#edz#B-zjboVU z+<~`nQwr(+!(`_k$f|e~t=sh5lS6ygZjdxblS3CBq*kd-f=`u`Qe5UCY8h5xjIW)j zNna?0P&#l1&V}ssw}!HQTK&aI4u4~){XD=%Q&}5LbQ`Qc9+_xP5 z+R$ys9qtiB$4Vk^;%%9o@bc^I-X_uh!o57{yTNsa!}o3|Y*1zXMA+)X$c~|LP;~0u z3d|%m9V4}j%U50}od3SaQ5(53VYtJ&AynKjGD>z&iIiPa`b9=M z@(v7jY}^}~lBbbXxoL3EGm9?E5Ql4a?3fzS<%}OwExPvHHOe>U(1S;~H~qtx3i1Yv zR@}g2$D@T=;*N}zo$WE`;j7eIq=~g~dnLUnSP|F2H$c|8;{Rqre61nsz7omXpmh1M z9|!qw^m+^B-BRZTu0#rbuqI_Aw=G%W-=t$%K2SVzPPMLXVE&sME3sSpiX?{S-6~4A z9j;*V(s9EVL%F$<6-tSL`IH~hUfPD;45Seiw@IOx@nR^Sret5PEiWvL(j4xJp*9D2 z3VDcjXp7&@~YBnat6t-mmtBUB-X-X#&Hz4hBccSZ#jyEKFuFp z{(;~vL)%?bva*czfri;7xqLJU5MkM}aCi_vNa*OKn$LXru_gQd0<$$z+F( zOLCIGRPU@z+{Nj&jA~6F50>;ReI-tJc&LLv96P>R6b{`?sTqF=e4!UZ$_B}TO+Zw3 zjjVI%L|%@SL&^pQ`2wB^3ST54%Cas_)?JRR0$-F54Dv;fCyg@K5ENdFt{bG)g^2tG zZtad6hspAe)%Ay@)s;?%hIhOa^M|^>T6+BbskB0IB)MsBodmD-Lz8ugrgqlssuuLc zzOX6>SK=CKd$K(Y`*E$XvCS%n)}PZVZiAK0De9Q7)i2D~u+g|}3p!yzHVA%Lvv0;m zNgjWzCUmdulUDLa@3wvF*UEy_t>4)(g!AtYbD-wC{h|>0rOn^Uz#{f#s8T}zQb)|& zRl%{$ZL`LhqdevSDcS7OD<5{YRxcidVT+g#WB zgPK>(`BTl#2~Kt29rQ&2T_aSwiu}{M?U2E$OiAa%2hg1T?~ex0f# zbLCRF(+W@1Nce%A5ZxW!u(iMfV|c8AiTap>9j3Gj`f^`-YO2cDy~a1c8gmvWzFhMX1v%K1Z$q!w<*X`%wKlR8yY9ETq36H2 zs_?7jpzfz=p}$uLZ&B#}*s)1sh9LI^MZ4}#a|TH`>B=YBPBOg5>&wtw$Z@{;1PO$+p0i>-uc@m@BvTIf4JK zK3nP?<-R_r>m5mgYwH;<+3#*T(=@mAZ0Yo-vrW@WKP#Qu^jXu?164QDZd7pvMLR2?Bjm=ZSM>{6DnQf_>H#=PcM&J+U=If#B2A8TvOHBey(2 z5a{>%!cIJ(-{%Y4GE@H-JkQj>=?mLBTc6PAIz3xIs?k+Cuc@(V9{7Jz)A6Q7r5_$J zH+^`+j1gi1t|M<)^yRJL2Qol`{${TcJ&a!fT{ANNQ(%q8&H`A_+Dbn?J(qm2M0j3Y zE5K9g*@DxJO>;4#Qdbtj`=L?I-Gnj520Soc#44ugc{oF78)6s7B@O%d5V*^!?<$gom5_%1_$1d!#XpE-(RK+I1nigS>PBMc9P*`Kfsk4ZzuLwU zvT+U7$6R9;P6k$o>IYoJ>5;(K*lSFXOO>?fi;SZ}fUc~@LJMjhfnH#ZMr*-+x%=D$ zrR`QW;Qyg1jW;DZ-=9kG2F5R+1Pe526gJ-;+B(Z`egzQyMuDmWrpwHH3YA1#bO zT(uk{Fywa3ZoWNVUD>zOUgvNxxQMuQA@Lx4JEpzx68~}G!bW<}VIJXE<>MEe(q6bI ze+qFYtr=k3FbcN=yQv%#b&-`24-zS~is;QVQ}KMccg4@r*O1TjT+=@6$81RpeeC9Q z>*5TnaZ2I_k5fH5cFWtVTMEE^%%nuH-9 z-CHK!3LI+04La5^BGz`1x1(@Iy9j^LkMH`2vq3T`CuD| zvoZM=+;LQFp}T_+xp@$`JH&H&IZhy81`25P?VgJKT$ zLiJ5|Kkkyj+eZFO{;ahAy88TetFIM&T<|j9r%}0!9sLO|QRf<;T1;geypEwSvdf2v z71rM>Fro%Wh>n?&_7cBQhsc`Ix4H?A+tHOe*tQC0QB4;*BGj6E6MkBgZUX9`_=`31 z+CWXmdTVOy2vKXYrv6e*x=D0T4)w~hK>$p!PnKA)-UNSDc@V?+T4{&avFVERhyf$D78(ulLq;r!~uo zwMz6Jj9T(PYSF|)4}X99`jWFp;!P)=pSW&KpW{;Ulnh`YFU||Pbpt)8aeMiOJx2!C zDkTG+OYtUNDe1+G#qDv|U`DH{oFUI~vLd#H4AEy8b!;ZiqTQ6GnI|(RPc>M^a^Gdp z=w!NA70!d_Qbmmg`uyY4+Xtzhrl~g-t4Py_&VzQ#+JoK(HhX85>Xo*$Zr;IaU46kH z`3~V|K^OmmU_|PoLU4}2m}Z?{RCr%CB-RSiE$y&{wqVs^+(CXLx7Q$^>f@=~ux7Hf zYiP$D9#Hru*iyIEE8iyaSG@OINDgVT7fNA#RNlwfH=N>!OrSXsvl`jt0y-otc%{b) z)*JBni)DIsO*QxXQ$d4P%%O);;n4*h5E>-$%7m%vz7YA=n%x-jU#qFi*Q&o)PfN=D z7HCUj#2nYtvSJ@pQ*s#ZY)(n>&gHVVroFv_l@JkgY)FG&+Bta&C!JhBUYPIEb}`>3)?U~+Ac2R z50RHnPU}8s#VtyGB!@-R88`jMwUTc9+H!kLvCv+4arJE-c{Wns_~Y@@$tD_q92f%y z-=A!xm_kx#_szl=Aobq|6??v${>ZP*NBSZ1jaihx7ikJMX|_m!HHa*?!0rZ#?Df&u zDd3sifgK;tGM1^vZqHJF5qxc^#?r}N;X=3U?tF1w;oZw;7M50f;pOe9aP~8=fq!1V zn}v{{hw2OUe`$}nHODC2?Dl#uVP(*oajSu}4M&B}qM)_kR_x}bRjuNeW5)h7 z^c>TH!w1rEQ{YuRYY!a0j#WlCa|M#@`iJj4WCX_}tsnF!Yd170T~2+$JEz{6PJVat zWvlL;L?(LLLV2F334sckmpx<*gxscOA;AZ;?gN%kdoW;H^@) z8hT!&VspPmta3@*BCE|E2REZPbh3!D}Dpd$lczsrn%_*)kM+>TrUPz2=l;GIb-JKA5pYe z)tjrSkvti0KrYdKf$RSz{G(-~HkLRJTr(cJcn#r7lidW%J_AY6#JrUtN@cQ7nYF+eKg_q!Eq~CQWY<#gpz>F)vQ>>itTU`Q5 zUnqy47)yLU^d|Xl?rkTJO!)HL-U9dFITBt!tyi&5z;jG2beWl; zXoN9&$WZvt)Pqa#oCph!Ksb-+U2XPisScbKBW-kF?oL=}Rr%V!W1&CZgp|RQ!drqq z^z?@L3|~Rb>~qlUnUOTw&V520i?J7PUITBm!f4QT?riwN?dpgpJvRw!I(M9^=k!CX^9XV_p%2^V?(2OUp4Q{t+Ye$WsS zUx%G3J)AuDgh=?@g^wLU?^x$|Vl?1g^|?!dZ`T{XVLpSAR^K;w4Bn+^ zCrYYfWkV|N9NKcdE0~9%QS7x?D-#ExcQnIb95bdfh4IIus*1j%FAJxuJA$2k7Gg}} z4SUb@<>SKIgM2Nm0nno;WuNd6@S*OvD0>S+6vj%=`ha94St2?ntx}{Uy+d{#CyBW} z=M~BJRRu%7+|YnH1H8M}=e%K8-rL(J$?bf?_9}3}p?59)dGdZ#XMUA)xINMpJV8e$ zEtPb4vI#<8CN0{8`1oe{y_%m&$axB9C~~}BZFUnpNFZ}gHO(EnLs@~-x4Fu<#-@iL zl}^!!Bre=`RD8CfyV4!~1uxkitn%S=d>FG$% zt_^xL{g6U7G4yufLt`vO%OPD)IpD2G(gl{9K3{!I`<(ie&M?vlE`AvNuJQzZf7n7Y z+^D-TRR5ROus93mk+6r&@E`7zC9Eto>OwB8gSJ1Le1607K90-K?`jQym~15BaSuQm zhCloO>kKg@l$FIHK<>+OFwGZT%q7&)&b%gN;*CN_H{6!n| z49k=;^~|W6G1Y4)R?Z;ZdhN=kHMEkTm4$jLaQ=};eB$OCxW(}*Z(HIB<zLD6OI-8X z}}w(NzWmk9t@r~;v7l*LpOKCpK?lEg)66d2>A=DUuopWpHj+!=TQbczewSE zQRwK#s!U_M)T(nzBdY%PF$*uZET6ZA%a#WwDfcCe$sLuK1@1;E5SVfNH)${Ed%SNiY`#(f3@M}R&59dA$>P6Bp7J@V z-d2t{_CnNQwuRy%t!~xnzAB@N z?(+ivdD}l$2*xkK4GCK>z}B|$?~^8e>=>@SxaS`v-9+e=uufbIa{}KMIW&U}%a!}E z8ZITB2{F|FI<_?S#Ji@Lk8$I?J@C5*zWG3oR-*jH*ZQ-(EL2>fC+D5bEd+W4}y;F9!crm+$ z@+meq{&-!A&7n&{1g@76fo&P0u|0~YY>y&(+oOo+whU3)mg$F^m+2FhAZ?`$X*Q(U zoSC+7zaHQiX`Ld50Gp4+MZcN1FE`H;!j0cJ27Xp;qfG#x zU>g@x=oz)^fN$mb60pxsX&Y_6n<#n@=)*!LEE!2H;CU(JLvob$6Fi&od@%_(xP&0W zL5_a-wWa!`YfGt=ZNU6K$DAW0kv<$6(3Co-*}C(P=uBtYMpx??u)WZ9^G|#6A6mnvs2)Ow+qVpHFh;`Gj`t-HOl$Mm`v1gPn0aC{UvO)0xnzuG~iMnh~gueMsBzF(>9vX-lMdfGhp7kWG|<&NwY4_Me0T)`lWL!PCHJ642rzEg571TU}=sW zTD6+Bv=>5y9EkaJ2xRiuds#Y3$)C{qu1$grYuUbn^1@!a5BnJL7?~-Z@hCaix#>!G zpcdu1(xgf?FLIL~l^*_8I0eAy%kj4tfBW$F7yP}6zg>a`=^CVyW+mBfVr68(3}Ojt zEo3K8$t7r1SnQKlT?;}|u}6#^j+lp?@#3-(&<`pUc=7fF&p9e zfe{oELVgJ@-<(hO<6fMi)nZ-^_3BnK%Ugc#0f3u}G|gX(?@n@FnYgU}s6lqW(~UEr zbcUtk+N6yF;$Y!caI8Argbip*{dQWHYS(VY(=}ziw>ifL-S)S$uVuk98WPf$aPOjN zOh`z(GPc7*jC&x*60R*UzRqUfYn=wUrq$qmev)&Eq3E{*OoZKJ7Pn8r4iR@K&a_)# z5uqUd&|eM2N%n)(>P{NO< z;wH~!vN>Mmit299v2AN){%*Aijkxjoro*tT6Ei-gsoePvO0t%!^=jFPo6Zzc*}NZ> zgI&S2E_xm8XIRH6++Dgrj`1_LMjf+r0amV^LW2Dp;^&(6g8s_%$WlZi8L$;|4QBYq)#3^4G)8jiRZ`@y^V>K##pvn@Vjtd?%=PCn3=K9({E+E_bcdV(ClzB zB4Xt{55JL#vOWgdtW0~xvT{J%TgUh4-+UvYdBE^)@=;H6PM&vi7DYN4M)NzMII@@z zj>5&fz4v*by)V9#te{*Q7W`UCBMqQ-l3j{wp|9r_=Q*64g7S#CS?4Q~pbHFaXTCD3 zc@8a(%HcQ6n-q1iceW?Y1hI2u@z|bL&n*UaH1^}v$~I%AiSVK9e&vxC$6A8WZCEg~ zr_6@MvwNP8EM9A;GQoUD7G&55=ZSNp5le0a^S8o@`N5Q(iziCg95%U?xd|_!oK&0) zgM2iiPtT{_CzWa7vpmO*bwLaE8{Mp)rC)(9Q-0m>r9Q*xHFQ4d{*{U6lg?#+lGUX7 zNK>ad!CGIF#1K2h*MiNV7QWl}YRDIRY$4XX{l+`&Rwl#{ahj1|5K+r{)~OR85^>t7 zqsuXQ7|W%xEK0Ck`V!WW7R4H}9%39>X4X*WL)5C3c&}mgnkvpvx0*53)v?_4nMga% zmMPy{$~QySaaPY!o|BBndWw0iz>wy^)8~xguuaWDCA9E#_x+xs+#VmLJ;Ritlpa3u zD2Z=Rsc9&u*H*#(pkBkKv01Yszf(Mwof|#HKGx8@oZ%zHKYZV>c|cc}Ub94l^Cwve zj3=Uo6}w~LJO3@~Tn}Gz_^UTZcXe?YuQ86vRg5F8p5dn3ft@0TOTWl?rq4rbpEI80 zi25|Wi*=;G&3Nhxao1oHs}HFMG^c=vYm8y~|FDMRm)O?|_7oVVf5Cc=Hn3%3^|%@D z8RW&g?>y>xl_?9k7ip(hPu(MoCnFVjJJ0I-)H7v$s#tyKy=+CU593e5exy2>=@dDeTbf88rb8hT~5qbF}Oj_K%KRz2{%8a=(n za2Z8_s0Ng}h;PS1tvdWw1JWecQ}a1`SH*hL|BO7R8BaPvUWDIo0VT>Iuczh`phcdn z)9A&kjHhNXdU^`btK~ePm7&hTyt|od_xKu=etN7&aZ~T-=r8&lR>b@_{nT^+sh`|* z^b`H#&_6EYZS)ssKeIr+v~Iw87_H|rp2?$#Vu0}^TZUi43t``rah5eq2cLo8^ym+l zh5mt(`aTy?&WFEo?7N%wL`xrNoL+-3=fSo3JM2*V0gRM|t^BY0QuZJF;;^DGS=1Nw zAq{j(CoXEh$h(L>0_Nk@=*LBHn+%9L&=)*UFTnT9fd3-s2|Cr`{b)1msZIoqW}@#e zpnsqd^{09kLmcPvsbkM`9CXY2oF$6r!Fk}?|BCzc7^nY%`@mU_EITj_ZUavRgJpwe!ctY!rH1rPR$Z)&?`2QACkocxq zkpc>RroRB_I+S;!4bh4CR2e%o`hAyKLyZqKQ^%*L`XNY}Hb@XpO#^sr4yb`XPQQ+4 z2XIiR;K4&U%sQ{gi!z1p>J?7?Z~8|P^xyZ7s6^Coq)|Uf`eEdf*BaI?Z6625=v032- z$Ufq}GL-mlxlfV$|6cZ4-v-yAA8CM_`UFn&Onwo4Iv*HQi_sUrTzwg1;t^FI*1Uv% z5IxZMx>0};v)Oc#f#=yh1qADB1q7j|4)TOJjih%daDpCqtcbr>r^k2$)vP2XR4Jzq zoB3Z!2EFb-QAZg|BEbQaD4A#^5}H z4Z4Bh=xNq-xQ+Fstpzn!DkF{HRQd$YF=QP@Ur2tO1`ZA@vydSR5#&g^9fu6SEaa(v z33YuNkZLo*SJy};{8xR_3-ubiH388!NgIOxs%S&Jqq&51A>f!!zJZ&Ft2haCI1Wz0 z%&AC$v?9o^0G_9>0f&Jz!1ac#E(J~wvl3{+82p!*v4sZdTZ{|v8pZ-aYw$x`AgbUy zNkZ@%sB%%E1}g%P~AFJX9{ZD`ErZ(BL&fFAgB>vR0D@G#jiz1>Y~-K@HxEn3b~R;^zcIkM&P8T)cCPSPg~ z=Z{W$^pJk|Z+LyuaQ>`u z%rYwP1Ly8@<)73wjLCJKr#oBe{?`3@dB)wj!@lx_suHqFcYsO`JA{_Tr<73(4|9XNh_qH3>%&6C%LXF1y!Po?>*HE7frAMI}e4 zJCK9+b$3f4{~u*<0~b}b^^fl}GiL^n*G2`pn8+9=x6GW9$8N!lG8{ooD&ND@PHFYY ztKOS=y-!@h;eZH;Iv}8!sQJe4R>oYLn_cBaV0=Y<*D}Q>CF|OtiHHgOzw4YCp>EIf zeExhshcoA#{l3@Ud+oKpYi*zXb(O;Y2Fo+_)zzGR+av3QrZ=F9c2X#1*0ye5_&8g9 z;~cPsaZRmrW~j){mGu63s?+h)63uW& z`>}Xna)y?S;dP|(kHs@~!b2m*bcRM8D0TfbPcwXZ`kz@!@Yjw7yBEeS*gbsog59mA zkgF?s#}NP7`-@iBDEcm(Exd_4L52q;zW+u)%$96UT?C}nVeKxNqd-mh~phj12>_PA3bg9pWj z$A`rG#&hwbVxNkIwo!HFc@Ex(Qr?26vFjlgl&CQL7#F{|&0Riwa!h7GEFU{6{;Bw( z@f36E`KQVeX86LnF`0|Lrq~mn@7d4F+JnFE*onPzHlaeCz-TBwZlI|kq=z5SJcKaW zPWmgSA0c1pH^P(OuQ8Zeem)P|NE&mU%W`s4VWNdmt0ZxF_~}rXr0jqFkZ&ESFhIWi$yI>3rD+ycTb0(21^iR z9sFS9nGaR&=Hso7$?z*I@z`6tO-)njf2)A&9XDI}utR{>f0nPXFIOyT@gW%zsB41q zc3*Bzi}J?ld9x<*(_9gLqm;MVFE|nr`_;|48As^Zm^d0#&TI@GCd))YWF7tR_XL?y;ThPwq)cgr+4OYz_Mj03&!ci^Mx zJ>Jd$mHW{<>KXU$;eGd-Vj!PepOA#v$Ah>WKV6|nHvIW;Z@jnBmO2^}3s_UKmm;HU zkw;uiW)5^99kHmv_3UB1#o@#n2G91k>>YQn7p!puucE?9ERQR#vpF}%iCT;fsZkYq z-$+N?&7010Kr_2%r_XaoHtR&5kM`CRCw1$4+K(;c%H7S~&HOQ?M$#*8C`5^N)%DIQ zw`unbMR)4#hD5|4a=>Dg+}ty!V%spk@X}DXY4reibNp3N&HKlq^&(~wzLNSMn1=mi z8zsW4d4xhaIW4kpEX14XX3g)ZEtxn+A$XE?M_sR6g8$HyixjtSBu2Y&2(?9H)e~yyj-6g-T8fCs0mhW2i=QeV*>g zDPv3h$m!v;K)>*g);=23~JmZ>$Yv4b;IdTc0OPjYQ^_2eGp8WgS;K{rugUYb` z5#IzQ#=hKqx2G(xZ+pVs+P%x&T7_#Fu6SJCJMoNb*-n~Ckn8pr4=TU9w<#&`0<|M@ zUEhN5%l;qY;p(nHJY36g#pCMU<>|>ce4o%unY-NO&BhQ<8A1e%#|+{JP_uvci?sc-Oj!TJjd?N&T)Oag52NT;x=?I`4`)HT*p(e2n7Tk#ZY~ zI$vexkY}(Sfc^$onuekj3rq_Q&j_voSD^u(x#)#UGtOtp9+?kUzjSfRm#?0+&)dT) zbNq5Q{$PWvX9K&5vob_RQuGNw?F8RlZ$^AHY#7ZtHBOxQ18{e3xuJ6MFu8=h-w7b*S zP5N!G6gFLoN(^m#%_0H8^Y?6I-OZ|90!~O*S)F&fM`n*Ggl$--elh$BXhWInr)|*WHLJu;P9=qak=ffU zHiRJQnjRsOqVf1{GdfOz)!zqWw$j3o%px_ zPBfe8+uH+dTBH$iPJ=Kn`)lofDQ07A3TO0BHyi!`ZL$S4DY;1~f!GdPV}vefQHgKJ zrBR71TOQKuhHJ!CEx~#|MHSbe+E6LvXyPQ*hG%wi<2Rx_!+FGjMMDbj+5}D$_;E3_ z#UCm7$@N*)f;;My)#5Lwp4H-aEyt)CY!)*Eg46nns(}7~L~4?TsIP4&)dzLgh;IR7 ztQ)RHKOw$JJ6W!|E2HHe)!dceau;89u5~SUtV40?lr9;kd%#{2>!r;%dl{Ex%pMAV z;W{?T9k(*6N)OzXY6Ip+ooWL=VNim@fz>YCnO>7PpuBgBx-whH!=Mf|xeYJPawuK; zuEe=nQ>1Ss%nV22*$Jo=imh9I$ie&0sZv{TN~0#3NgCCLsFnF&P&=tMjH-gSL$p@f zfJ)){ay~!}1e9t+X*o)QuW185-zoK>TIbkNZz?Cr}D&Lh*-nj+-yEH6A zNb9@5a6q1jGnbS$dLiGQKa{g)e`IzEt@jQilrMz}-(R}F(CFJ?+9DwS3SFaXLU{+J zz$I)ctp9Y2aQ!FBWwHa*fEGQc60hEYjU}ip_Z)ngpm%U$0a41{TzD-xZ;kO|dvo;{ z@0t6RBb3gy;#?O(>0Fs~XF7x`K6jQvQJ4_FIbYcNgrc`hT31#}m$-m>4%CoNZJExy z@?@&exK^~>AMgdWw#!OykX`}xCey*^8{xoq?zk)8|L*W0R16==Sd|uLip6)J1MUK8 z>;1N!zRg^;zn04cDlLCXghzjqo`0haYtBDCDRpEx2}wpfN*NzQWn1|GHB&DDHS@$GpfQ4h#s~&d zBLql|5W`@2h>dzN1SpPR@}~liH!HaWa8rLFjijnpe7#TwPGhMxvL*!hf)Fdh178pV zd_geq1;M}<1os1v1?_*Zn+=EdpHN5m9Xz`ae0o6BNWaVd9+&TtzcXfKnvBqciMJ0k z?Ad^@a0lbWMqv?XQKQ0Ks=mn>io#v(CgmLCC&VZrthCVY{myO0$&M1nbb)r zTR-v;wK5C)$$mD_^Gj0w^D8qm1bVh--Dbw@4xAH!X%*v7(mhcCFGIjPIJ>M)4Je~o z53Q!okbWDKOQFdp%tu|oKCEx)QaiuZOM0SUMKWIx(28-<#~zcS8${cc209ZYmiY4h43!J8(h^PHTXUIJ`b*o_N*4Wc20{3JtVIAW$2DKx}yM;nB6jGNJXCk)_~X zf}0|haK#9h9Y{PCW`jU4qJX|d)u}%e0%7sET^DHmFgsA&5dJMEBR-T+HsJky=egQj zy6p4nSblEXPg{tK4j%qH*TxU;M@bi|C>8Y%LSS;Rpg@gf>^|fign-94+4d0Fd_qHq zUsc|aw1}R456RC!6qEN6*=7a1*s=$<&}FcN4md`52BIU>4Q-#*;ASsQ!|n@jd@#z_ zO!W`;lb`VZCE~Bh#*yY6YFFCze*lD%UQ%P`crhiseot%v>yJJ2>ynT*|B(i&nJhhGA*q$Hc_H+M66?i;@T-e^#k!S35JBF-uZfQE}*T}WygyIS4dlz zO;e{bnW+BT;Th4*7CpVF%`t?fWQ4jNx_#f3o_YTYPE9HEi974iMKW5MOf0U+0bA<0 zliP&2gS&*d!ygG=KK+GDaYrZARAj17a|ymlj$PdBEmOsr9n6r0`P9<47iUhivr^YL z%$R+feO64iq1GKvoEwp(?kL#owyA5l@L2lK$^UOWPruK||2vt z>cjnHTDiwy8_@3_Rv(K>O6&~9>J#L;ap(SsoS00#wmO-!?8SUtJ^dTl8Pq3>D|e`B zbv4$}yy15@nK{GIce6%41xSS{85&wEM{8@fHOtM*Nrob=bGHWFUFx8IUc)D&pKtc7 z$i&QmaP*zufbVzq$=_{!uE`~IW?{+Klx9Bt#~jSA53Ee`_R2&03R6LWK(Bw;7kuH_bR97*>kUI z@H~6&RrQ`{&wZdL-X>4@fu8#&PxyhJ`zASjP6F1OI`NV9K1wRxp0CS1_ij(B%RKk) zIwjmP&%OJ=YnH~W9cKri$XWsC(SA99!%Y{|%ge!pm<`(?oKzp!4_l;^Y zcHUo7sO6K<>RadUkuFk}T(_YLyA?`n3 zNmdFn{pMixMJ@H(g@HhX=R#V0(o4@?q~EP1FHW8?e-Wd}SHZ~K40r12H9tfoX8a(> z=Phd?Yi>N@h<$6uvs{9$4;!!don8@;Z0Fxq&&b}MH6<%bYAgcP9Cm3Q{TWESz6sq+ ztH1?ZEYo1LMPZZ~_MgSri^8~z!niZU95!fbw5kTxLHG&;uNMx!`=El>=9>fK8r|&5 z`ymJEoq2ACC6+%JPwzJWcShnIaBgoBB|jXKX-(+IJ{p>1SrN8$D1F%?tq42ud#jM4 z%{lTX3q8Bppt-k%E4sMGIq>-#%=Ua|TLMlo(Ts0332(BEdElx0RY);8Qet%0im>Sq zVw2{>&CIXe61Eq|HRgrwRGk>)AG{(Aa;!I_3l&`J7KuvI8d4!uVC*Za@a7pYIglp? zDlNyac)mO%aS(E&kSReG(xAi@7`HX4{ikM4y-<*!Tj~=3dfme}*GsX5#>LPbIP{ut zG1G$z44?u7sK5X!Fn|i8(5i!>6H%KnN;hRI_ko`KrYz61=e|kuJbUh&GW$>2BB4B5 zD$PPIwN!=Fe~N_G8l-izIWPC0atkxaAnl5X+E@vcrDQ?fFl{}RK=`232ma5*_}GBVx7W|^E`OifqU*NtrPEQy(&+u z#e42mo>q(Z+^aGveC+Epp2e(X)oUhIe7;ZVWoaeGN7>25DCvbPl%ut(!7*>fvxG{H z$#e~9`(_$+WlVK4(P{zSALTl{j`#hjfc7-J?jvP~@X(>jpVU2?vm=P>b&Yp)kQZ( z!kfV;`+cz={}5Sd)Qvem#^9f!dXtf-(Cc_kwet=W|2rl=iE)A=dWSxBQY@uh^z{q>eQ5Y}i8Or&|)5`smQ=Vtf{gacPXV3kU6Q1W2eBwL7*f+H< z+aqghW&1ty8JBuovE{2TNIl-;5A;#Yk=_{;I9jw9S;q;oC6RuK<9=`ZIJ|{T%Y50U zCE!p_qFxsnEVg{6A~ZEt=zxziGc3dhLXXD=4XZRIR7WLn!rBDod>0B$Qd{481B1~m z_;)=Y3EMy79SI{Hlj+z4y>LR=1Xn?E*EAE!kRZ{h1c%k2W7w~P|K&9pkNqo6TN%9h zKR{1Y-bxxDXUci^wL1H{O1}#6rxulUNWH(LGeo!fXSl6H z_yGKVtj&K-i*<;Fe#f-=Z>+QDl$vZE9YNx2qtyC7nVORr+c@_Gvkb?5NnCjAtRG)k zZ}c5y&PYf#oh^p%Lnfwms6=0!BF$%Nl7aV*1|1Loo4BeEMtxsabObW?NtG$Tv`@3l zSi@z=d6#UbSm(;JT8UZ<)2=D9d6p*R~S%w}^JR>9K06{uUbs37X-79DI8 z;1&47s_XFn9#?H0lIc(9KG@b}bA-&boymq>|NK>WW-k_8hXvv!)3dd)B!$%J(6VIX zl5f>Eru9!-Wm^K7Gc@y{8nyT?Byo`24Ory>R}m$VSLF=s7A?@K47|1yHIT5L(_h*#u`^bKSAF3ME$r&?sOO!j_&E!jyFce(lln-5yXpA$fJ2pIyeowo zdsgw`cI>d!EEfA}jJSE?(st%D}%ZfD34jZ|j|^clO}G=?qGI zjFAuj=)>sG6!*f_qv@15x2YT}HTrnrYOI1vFH;{cUDTUDl_fUEiF!QpDeO-qNVuV? zZeF&NE4M8f$=3Ax-rW29cCMT}f{NWv){{bOuMo37KF^N=hU;$Ye%4^ zo?Ja5vEQ+pdE&e9>)jp8^~4{}_mp5(IdtXVG^2`ok2>Ou%S_@Mx7kaj;@?K`HS=(K z*OIt(_V>PJQS17xTDq#Rx~bZ|FnB~vj(cJGGWEIF*=mz)Nu_b{>^X2M3sdIwmbOI_ z>cCU$fu&qIc6tkk8({s`J3s}6^d#>RKL`EUY`W$^QFoi2`Bs(~3}+;}%nFB=&pmuK5N|`-EN;Px82sHR_~qhBm-{+Kf94RJI)gM!k$;oqdwH5H1sl%Z+#=!3 zg5l}&Fzewvdt26OV1J2o$S&CqSAXJ5cH-ITfK&I)I_PUr zJM1O@0{j0-L9d@s=}P)=f}nV<7PZiJVV{pv%U(i0n+7ZWnVSc zM@i#y9d<;Q29Zrn>u_iRYB+ICvC3*W!HM%fhgR|mC%$zL_nRE(qVt|g%$=upS6{vm zavlF0!>|5nGTO(5lv^)fRUe@S zKlz>ScDE`0>06V{;7d32?$#7P^%M?=&5Ayd#ULb|7gk?;p^5|FMy0Dd2JWu~S`O@n zj$gkuS;8)meg}1;Bu&pBlF*vq6_3*_TTx9MIpjyOZ{S8)8GX1Oz!i7Z3SjntZq)1636=N z%L8S7R3qr${h1jvvrS~J6?4h1lSua7O}q=dWU1E;raWoPOQ#O)lMs6l;-ZyzfuB{! zTtXV_=@(kRRJkwn+`CIW&z^gCvFEw?)?}oCHY)$~pv3XP8FK4Ad428VL4Bg8h$s2J zUt(3KJT`6JGCAf_MV>8N!s$Sghf^mk&GDlSluDV=cL(&0wTVZ#a{Xxw>>M?mdi)$! zjkO{_u7R^~6DkF9{SIH_y9u1WUjmz3Bx?M@z0X>|cIvJ~;$mopem+-!yFExg*C-)J zkS2)VwlG@&%|Cyn`Ddgg-^-u*k)-g$S>%t({4o1O4$VS;%+gCb%sLZm zY4+Rw-%(R;O;+mp$(K=+(!yzH6SbjekEr(7*mU>1^<_FvpX$$rTt!Z;-K*i*Wqevc zc+toZRsO2pA;N*{$VbVmR`rCjX$LUF^=C0YKc?SD!RJWl5%b4ela+6l z3)uDDa93BA_LHTRD8ZMg@BizW35Wa8Y($7686(yFB*c*3KTrCI@#Id0DhqBa_aM)` z;3v8%bA}vKD~2jDiDr9Zdvnf0Tm%4fdS zJE+vZh_n6wj#E*TA&7nVFtQ-$d1#)yKQ9<0*zSZf$(qw(b2{%*tEYuhug!12Q1xHa z^ZA>l@FDl6g9Q})*M&DHR}}sGoWeg4hgE?ysMNa>;H!f;ttquLs^L=_r=O?=U*==} zIEPDyw9~IODD9Qa$L)7om{zlYTO5}RzYjq+@GBFlTmzGp! z(Jmv`iM9r9=fh&IACr9R9g+s6LR`_uPZe_ft;xT23KQwl4C$G@$~)iT8n6WAee0$s z;eENZ#8-|a)I*}BW9j7iRla?!lYi(IOCRM7@RQ(Eolvc=*W!#hNo$5~iY%_Tz!qCU ziOo3w>e<&$&pr8e(;pj)lAbyI&V_|%p1$y3UmFJS@IK0`3^BN(c#UB&?vLXdjNj3? z55pCW-;d!QDc>~+3mG%6VYniBEu?>uv=3a?>{Az$lb;lR=>2IGk}q~8%Zqb_m^@Jp zEm9I`M_-WEC1{g+ymv&Uu1!_VyfuNeURLy*S_o&p$y;F04h>E=5GI{K7WQ=hyj3G}?0eG`v48B=Im>WqI)$p(4liNZVa+D%QkN@E3?vri7vJ>ovI` zCsAy>7L1)cc3rJO;--c`qFd~6Z`(92-L*Pj-Lva!tcwL;sGg1zNNH4<# z_WRRFHck1sB8qMihprZqs8%QVY|etpYBCZB7~mw9Zn-2^I@KHs3<0 z3I@2v6+4(dtG$zU@~#C3@9WPBSlbP{I<^&i2RcE}^=;dIqxM@^i`>D?m9KU6b=)6R z<+ASRN^{8N`FHX6y~@+K=zDLSsRV`rx7m$7a=7n`zv~q)xahm&{F)^3+fr7VRJ2bm z1h9R5Z8HUC!)mBs(h@koy@vJ|tpn>~R)k;4Ps-S5D}I>$2%oriKN@ots*LfRVCQdO z-`$TH`R`CV1KYzsE_3yd?Y0#~V5c*>!4iP=yXvhIBgPskDpZ`njma2m=fgO4BQzxa z^sJ)j*@9cEIv?qrDwcJr{!~oolW29Lb&}7YY-X!#!+&+Ut`xRkLtBHMzIftm^$#)jDdAEodN}iO1wW|^2S-V^j#%Q4>@I)) zM_YChX8$e42M?hBx*y~<#hCSPcqZx3Z0m-wEZrq}cCT2+>+HHas*rs{eeq3k(=YOGOdapa*IkQ9ajn!{qZun-*qr1V*nTuauq5Uu+HyjfzBrsE%ja2z zA8FN)naZZRa&+I=bx(7^!mtxMD(A&9t^!?iW43GK zg?rWnP?hCdX3zYG%9W{UwiUfA%PCQ+VDUEW$K~3BpZf64CRY$&XOjlA^*puyrmc^i zc4_%KL)2i-5UF7Xt%li_-W%x3^Q~3pBRfBeGipbgqomI8<;5?Q`czZcjHK|-sjjqZ z#drxSs{1A<< zV5_zszC3t_=cA5uGy~`w<4)2qLj=?f4XQfKz?r(NuoUr+*WtCKXs30`hupElTLgV} zC?mQO%kBg!UWamUk~2RpD`W_frdgYzx*8`}OOr z*4K8ymva@q-EF&*(^;!E&oe+&jQXJs;8#JX>lBw?Q-%MAjnCZiXU8W__-ukNX0%Gd zekhi+bu4AB4M1I?RJKqZS7VK9Ag?KC(FhHTt5YX`i}?e7ZhoHtuU1CC?^V{AOl?Mz zJzFrxHQ981g5wSX-Fh{NTRzp8AIsVQP|mIDW7NINy*no5mGLiAUsV-imYvFDRF<3e zIG(Lr?63_Oz_x6(mQCRJLlyF9nzcfltc2L*NQ2)NV_7z5Tq1G4En5Gy2qQ0ij@wghN#i@n`nDe*!%$w8GX(p z>?M<3;_>#JpIysylP(*5c(Yx*pV|5SCc`kD@4Ls}x$FwgZtJPvloi-5zSFyYC1&eR ziLFj5obXz)k#{nq)@d?kpEntGOVkbP)SpIr$R8uiRWZ6zbW-DF?&H?{5J zQG8!#w)?}fFz`pS{?%0`{olIcqdy?4K%@4W*>^1ByjQmyAAZbOd)CV)6##Q?B>CeAV59z~fK#&=QbD(w| z?C!n?|EAZ)FlaF}t{<;AsD*FYT0uSbHk&j)P-o0)VSzqI>5fTsHLz!;;1s*omm9rG zd>3>V7;RRA=8co<+4LIYtBp)V*tJ6b7_}imYd`B`ghDYyoKSW4uUKao06!N~4k_;* zp?9~|83vwEiQ4xbwyT$@Y~isi;|24$jpGK5xB2g$uJ;4xHGuWE1?+yp#%3=P2b@<^ zZf{(pab}!)j)`-wM!l1=W$N%SnuSGaD9PyX?|-HO8RoUJ-?`Hzca<(q26m1k5tO!i=mBlRhj^|1u4P2ZorpMs*IwIXJ$kKsF8<%?zV?A@-Fw}9AG_AdU8u5OUdD{G zmVukN%WX~nj z`RoI0L!d_85XfwS=qI$6eMNuhb#Tu*tF{HQ{`SDL>O1RffwLDGwP(=+pQ-Ez|EaQT zn@o1gXDZiUgIw0AOnCHM#%#+~KInySq5TWG>d>!?XZ__-8KB-AWDo4m*}A&ow|_wX zLAC~->PEWo6VeqwY~A(`XvEQbWfU8NPIYe$I?y$<3Mbp}^{RJMxUru}M);i_X|=D| z&W2@K8>vMCv|9tuc3T^-bsK`{eh0D6cDvS|@8W$bitO5X%oP^cx%3NFt>ue;(3SF* zGyhEMH>}9c?>5Z`Vw8RxC+~sYh%AF`zN90JKB@S>*Pcyos#pmPVW#cEP?nJpGEO}D zG}l`LKpy2SSV2_{Q90tDb6H5zNhz6d3(d1lw(JCM1UU4w#U)N7tPqmd<789lD~&Dn zjC7D*Y|fO!0l6_NKh6$u|55{J<0U>$vOq6X{s$_Tw-jrV#SNwGm!+UGpaeg`TTzl8 z`TFTzDh`9U#^kJb*s~4p=JZ&*?op0PA!!algAjF8+ZdBM%@i>vr$zQGiTDwwe+gH= z>O4c9zX-8@%#mt_XHxQf25)GmUonnshE;aQ`V*^8e}$*mW~SA(t%nEdufmefA5nuV zDjWx7x3;}IZDoHg=FXZEs|t@4PNa|z>+t+D`H_e3TXU>|&DMuOlBQNO{WKrWHm#i# zSIlE(ajD+8WF8ZLr|VCeuo7XF&&&oy zyos?omVO~W@3^Y=A)#jR`~r&eEPg`+&^n=jewCcUIWay=W8?31cZPk>8<&J~6X>j% zi3n5O+0Qt#n$0ixt9JUT)yLJ?^W$xEXTQDcN+uddHnI1#^9$g){rLHbo&8ZOHINVY zaT<+szEi90SNwPhoeFZ7yo&3pOU{+xWEq5i+0n27zQgI=`BNnVtSE)W1@u1$p30wX z=qHHtb-GyajhNF<`uRLtq8aCcPlRhbQ78 z_tOz3cok>l3k|1OvVV=iIg<^8*-`k4BmIn`fh2j1qHCtnU@}J^);30r|2R`$9LmI( zbu4v!N_E6|eep;Z>%&^@&w%#BZt?bZ9d``n<>d0}QQnaa5tAr4CHE6@?v!(cnewfK zY+<`JG7Fq)hi^ofG9+6c3Ht4^b`rkc@`n$G^pNklAFKEFuzBuyg+ zbj@M>MLBCG*F9T8|TB5S8O^{$4NVOxK zyzG5Hvh)gSY9i125#|hw+)|)bLUsUGGK9^>9*Vs=E(G4jL>{|-S+nPeRo>qpw+3F` zX6D~eY=d_n-w9oJ)A3xd%$RvB=H0v9pOCIw(U$@(n?(9jRjsN{1=Rm+lQ^eTLzcE= zWg9jP7~<;lLcf+k{&r~;DYmI{h<6Q-4OaKk;Kjw(9gQzT zkMoJJspsoT+`-K=-nwbi)s+yE+?rTdLed?K?DWa)v7uz05}N*Ot=d`4tPR<0P(qaM z!YZ|M2lng^#wU$N*l!>uiL0ZNtv|Jlg#}9FaF_3+?P-1I-}SY8belX5U~bk(4mEtS zoe*$#Dk~DoYRLaVSW?bBv|zgHyOyqq3DoLQbKAw9@YG5VRr~UCB)KJ^ok0!M~m7MGg&`UhaYP!|CbdZ28BWr40-TN`u;#!6)9#{81`19?yMrU@b5!Nnr;AAhma|jo4 zpwhAka|8IG2J%%78QK?+DdM`k7cwPWvv3W>b@}rVmWL9zSRybNpax@*y+LZCb!a_gOda?8S|So%E$0-<^R@X)oFRJT1KPu` zP^P^!$FFJ6`uju{FkZAR<@oV~=Ii@RP>sm^cqI_lzKN<48_E*GQeImTS7+A^G23;W zrnrW~S?{yq?3y$K_I#U8ljLcakb`qO?y)shQ9@b5-m=nyvbqsMM9SXch$b=OXEt{1 zpt(SIN2V`H9SdJT>hFtF52`CNnd>3Hd*X(rTyV{Az>oz?pSqC2imMMq9 z>eELYyIS)&1A5#v(Uu`RYQfGSmIy9?CUCV+$Rd;ECJ=wIpXQ{4CoM`lSi>d>+^zPofw(Ie2;CDDdd;7n`F6} zoRt^+7(7#7?n+*7&m3%qEsAalKNFg&uvFaw>qvTYUuPi+hrpG< z&m8**euv%V3$AWm{vmu4NSb%B!ady$J1gR$Oz`Q>B}*?R!e*f<^3@&<8)u;rvS?BC zspJzc9H;edL{0{FQ`MTWVcK(1XI?rs<;aXfuR33=cQ-Y^L+$7;k1qu_>5La&k*)*Y z^1O_gtDd+A*rf9AP4jO;g6nrvwMKxAk;>6>6w+yDi6KwNw&F76&{qknK z>MS=7K5lQ3R9Wx0@|5HIqwyoA<_KaKxG;pmw^q*b=uXJ7z5}Kjm%D{fHh9MMBrf+g z4&K{k9w`|-mA*}-#G8myiub0(Oj+T+H|hs5M#Z<~WN$3%uot za>5)Z2_1^{)ZF&2mAaF%jw{9I9T_QFm0u*lGny(xm|X6C*IlqtXmcFS@;+}WE){N8 zDd8_?es;9P`}n?WxIrJo-dm=?Gg4k7J9y1F8^GPM>Bq9A~3T4V&OGt0{C%cH8Ck{B=!a5 zfyuyju&wMIBP%d#;)`n1nizg}MKws+JWjM?OpeoM!lrgS5ELhXBEl7f>v$8MaZSV( z)U-t!3%iqrfvy1Qdgt$48~WTA)qP;axq4I#tb3V1Y`_*O_ejNu3!D9}yV`xeR&ZtN zzJc{utT$ZbA3fpc%f4P%^P*Y{{gMW$4z_&}>}ma3>-Gsrd-Pd{OO#fKFRl^t_w_t? zm(>gTy}oyUd`NE7&-Zv+XVa(0yse`;_TX*Rz7z7>6GF$H>5IrC2e>P;cb2U@$sK;4gcsoPx(?*CD>MdC(1;jS)dpiy-Eo8GxBBztHjm)+f6Tsa55E>U|h zG!kly?&k`eUC7+Y9Ujeg6{7V-f#@}QJx0wM9U(V6T+4rTCC%fi5C0% zj4a;r8?+e0$+Q@L1*d;)PL^pgS*FEtXpa-U+oQQpulBgXmE$A`pVB8pzc={Khh6La z?&Az{P~+}kh068}B^ui}l;~PgH$JIVjbx=GsUUhgZsoktSX(yC+;n-)qOr!6tA(2#LtQg1!-kYqcnGq z#TU39ZTk6%qzef7ffq`SEKe_;C+SL|#mC+)y<|*^neZXB9*TV(*!%F@G;^?-*G;P- z9gRyL+L=;Q<0ze1Q7k3a>Nr9CX*(M=Z*Q?J%gL3DHd`Uv`L8#+^A0Fh)lqdf=XrOS z;FBUFs`G`^YDu8o_SmC7O=Fv6?b={y*rGKo;voL34DkJ8cntR#T>cvD^I;u+Bv!}G zuE>lyqO?Il$(o~jZ5>BmdDbR49_36nY1^EB;5ZlTE?C#I|5&hl;8&pTfA8?2*0E&^ z`%7LSj+f*+v}+4@p$)zYe?6wqR~W7Ne4gh7-NJ|zeX+pAWF1yaQ*gx5h!m8<2fO+v z$VYrzb;O@XOcVdoq4JqDZBj%E_VSQ*wc)!21aw+{M?qXsAaCZqd*@1d_q^si56&x& z_Q^G{;w7}r%_`qS@sHb8`eL4Q=vvuHzB8ZN_eHDRhw6H{4=>~&JyPY{67avp`Ndd=(-oPn6mVhbUC zoF_1(Gxh4boqgwTD8V^DZ1&T$UbLK8_4MV!sR-4b)*ojgvchvu&$@|sB~vNX`(v*b zynoQ0(mdfsi#vr)nT-FD6P_DC+0vOe_$b~_3V%KML0ewOxQ;7y=uGP8EbyQ=4lw-e33RGlL_Vz&)x` zn>wdP9866hFZHQ)qTW|UvVeX!p`A3amMMk^-2gO#*?c%WN9=>-+;{7UA3FO!W#E} zMJ9IC$D^bxLw5;czuPRPVV41CZ3*Iv+bSi@x%)*2@LX~mcn-y$f}b;g^A`EH2RYul zsa~N$+O2s~t_l%=mxZVLeY@hM1+B{{4SgGH+x(xS`lb%2D5~j1$i+a~p|x)BV4yFY zA8+=Ydy$hMx;|79rs(p|rSrC6-oc!pFI47)Y^SzlOo;XQ-1+j^6N*fLN}^ z_0ppne(^w$t($&OTQp4cdz7>3b_a+7ZG>RC#%r!P^!#q%ayDJn^VI=uo~NpB^?XwR zo%9E)ZLPZNm6ya4r6f9Gp#v1(;&W^mdb8?Am}Qcgw-D-q^tosUplb?+yfOSdNlVhV zLg%nz(RPjHIZ4({dJvimV=_nGaA1y2n_6<@ys#AKX?n*h&H&+T{7nW+jMjl2X%`IJ zH7a1VnzK|&e~-efc^cTMy~Rpg{k%||!fD9MWZv0Np*_|sZAox(ZTHMoWQV!^@T-@o zjcA?7YCL?fvEgLh+1f9wU%NQ>%eT+}@ho{--5SKP%1m3Xupd^k)dAl~Nz}?H70`uf z5x1+)Gu>(+?p>iny18*7JJs9!sB;q4|8JaH?v22+S}sZN5B#-%bwGX+^s)EhjVnO! zx4UyqvNx4kKZw8M19J{q5m#IXV13d}ZflSk`23sbCG_cvJ6f?IONaG(>d*JL2x`2y zXU*g2G$HHuacaJgq%~B0rLt6s>!P{*M8nRnRBt)FsV}=q>7<9eHhAH`^OY5Lr`c`+x^P|-(4Y1LG1Z1$$MsaZ;N z`JL&aG{u$c)MD;u>TRbDJO7~0cgW@6IFkAdtz+2v3J~v`zDD?m&)k2@u{CHAcOCyX zb2U{|yXy{Dx~4VXLtF7Jl_ruk(=17}L49J=CG0;xRiP5h0D5>UgS@x`>tGLEY&sWm z%#bdx;ws>X%Xv%hzK1OYJa%m@xZPD#70W~3%v<&=BO0FD_Lqzv@I!2@W_IeBoZJkj z1eu+W%sp6#90n%ZgtM<{wY2U?VmY}RTU`BoyA0(T_DngIug4Au_@e#bpL`?Lj!~M~ zv3`y59S)bj?|nmg&I39m{Hdbxz=^VCJ$V3j3UbbCa@#KZcxD>!n>EgeF$UI#5kxvu znn_4s8Iw5&=Po`5ZHM-(s@7edqRAHw7#*oB?yybQ>T7u9CW|mVjv4tPO1)OVx(b~I zu-(D%uBIwIZo7lCN6+b?pBk;JrP-C4t)ww3tA;-vc?Pne@4b0_jNCFTuql)CN>2kv z@5!r3_+?Jq)wKfodFn|68kQkg=XE+JZoI}m&Nhcs!ap!(km06RyfX;Zjq;k47?Y{w zpcrcSB;cDWG#-7CUYlnP@+rNoMEc${4vLuiJc()?$Q+|}s|y)n}R{^yvZ zfb=EV8_l#N5r7SgkM`2Y2E=~{@dIwc^N6AUO`Kv{nV8&oaZGg6R{s<1aUaUxD_tPT z!vCBOds9gVJ=r^*lZJp_r=!Ryeyc9kVyUpE8oTFT^uJPnWi_EW&XBj`-^C@=ECh5<=>a{UGfF#5BX~%p8*!#1X$U5feb`)uazI4%yBA3O+94SSr2KboNUN z{hseA_&R_5F@^Uco;3d|@u8{Hhy%S^kb2(N0$Z!T5zqz%fSc4@RCEXnOvCk8GRXQ3 zGtTWcHBSFh!8_}tTw*?Hs!Y2dlK;cQh4)R9UVifk{crs}#T38IR&j|r7OWMf-9hsI z=qTBv=h_5{mqR?FDJ8gP-#|S)-8Y=THV{#>Ip#9jPDOC!Dv>o(l{@l zvlI-=w53j9`d7v?+gAzft>a|TYFpe1dE7`NH0D`sTRg>_$jGj?yelk4;|UT3!H zbxc2fFsEO9TRkUT|JQqJ*i)-vZKH;DliIcq{?w8lPz-=n0EW`Nq#C}R8mcnCHZ;F9>?akp65Ldg|=1G zd%UD5Y0x}Dyb)zUYPV_jLVB~> zpZ+iOp?p%*^nYO=%4fBT{_pl1h5t=lYU(J^Spw*c_K>tQSYT?E_lY!Gc)^B#*qYx$ zatc%P--u4u$P`ySpWc-JC0epgLO`nhn|I_CuOCeRg_d%&Wc5-?sSC+yw7a-LYXT%z;%S zRt^2^s%&2G^Ja!Py-7RGEH+=$1OlU1at_+}@_DReOj@_~G1#wNdW?y4&w&%_Z*C|$ z0bLpFZ+xsfeOQPVsPkd{yGfpKq3Y;?X=Ww9H@59uv?+fjVf!;0B%O@$e-Aco-`dFD!BwexDv$h&1KTOroeNM_xc%`Gla?{spjUoLSD5NHRBIt;-)Clqr5 zZp=HYOO88qY~k1W6f5r(>52)bK&RTLb^nuOAVFa@g-*lYLphvm$gMs_t6{8~?Kb>< z9&kSAj}uOadCq0$o$4Ke><5142E&#XzY<_+N}Oah*AtJpIBlbn%D&vT z?st$+_pMtdlD$%yXq+nN1=0>~StsQY3;$?H0TK?!VEF7C;@e$jD*XYJ)w=9wFZC$8 zz0{XGPc1L*sG4RWgn_aBs){5lBv+9V2DHc?G+N{DQkr!K6to7(O=5?VCqUnB>tOg( z{WqoC-A3FZPLfMHnV?8YQeVD-l&?cOsqlEifW@H_&ibj+qLgttJ9^-^OF8hSm-ke7 zJ#Q%$8h1i>O)?Q^kXo1h2&4_40{*z_OK=aSExL&6DA~Kluk*e91GQnLC3R}ed$oL9 zK~2W7g4A=ME}Y)}TP=0@yWcJY`J{Tap$GZ)($N_QU#qhw@=V`8lGz^Cakig<);t%@ zY+w3uVqPEBzFclxsdJSMD4z|$i@nl^%NL|1v2S|>&A%^5zx0<8HJ)Z)DQWSk0Kt|1 zeV6`RBGccAWdXVRzFJO?^s&~Z>t`VC(!FeEm+O(KKl>(g&Je8OmY<*+Qdu z05%fyU^#`^0J9u^Gqpj-T#u-`A}5k%ag=6eo_gwAOw8(|64lx8*X{aBa~n9-s@`)$ z(SxTM#W-IvZ&4n9KG2WKmG-a!n?uxj1+a68qZnc>G|rvNR-gJO5KJ`xP`RiDI`>IQ zu6)05xMcGlg{LGbh4ySkrm7(pV-M|77wgMRG-}`pIydJ?&zh_7l+e#|G?pSvYg*os zCF%qBT&PNY`RZ58i-}{Sc}v%=-kOb?sF}(N`9OyalqMaZ9S!u{y<{GQHZ1qE%+HElbK37yDIMV~tTLB&Tqy77Hor{Xmh)DI zn6Mi2xWz$IgR1uF9oA^SZoR)>cUht#>UC~fium1aZCN5A0g1LT`^STaY|0Qy67^Gt zF!4vHsxzy5Iw}vdnkbil2suRLY0)q`YkB2AlF%(ASJQW&Ht8JxH9}4quG>H)JHd=+K8g z%Iw;y+^ayL^L$Bdy(9JI3uxJ;y;|1kX<6^=vY>U~E-nQ7KN(*Nsn|b5>XqFv&9_?w z=uRVV{47%d5Q!#mX5^s}bJ5keI^Q8at+l(P5^K8cDj$iKbI?pp>rhXMRrcN~MpfW^am@ZB|Q-oOV?urFTLp|8{2==oOYFZA=Vr*ATj_WFqMHZd(6EK-=b5b{t}^0N88MU;}Zg&$2>tTEg}|9Dr6D)WAw0N7k`NYbsWj1Vp7u4ZpKJ#2;2_z*vhvY-ub($W zmi}WbXUf0Nl}yb@SWJ2VRDHV$Xu%;I z?R5NnAj@QZGhGwXLN+DB^T#3bp50-DjO6|0X>&s87US0&Gkpnt1#9k;6`7Q9@<3&_1$ zo?jX%timm_V1--!*F<~;EvFUe`|CId{721SRr3aHep+u7n5`EI2*avyXubP;9b%k6 zK0)SUNRp=4)OGoo-hqc8=&sv)kK#(f$3!y&&>yXrKYXK2ZXJ1k@R2>ZR$727xI<&N zqxamyytDeid&IH)I**{6z4Q2Wnm~trF#l$y1vy`>hpz*7t320K5ocSH=-9CUoRTfO zy(O)H_@$Bt$4GkLQBc-^zQ4LdLpW_Zr5oNCF7GW)AA{chVTY`lP;YZ~p&p+oIYvn} znBl1JBLw<|S^A&EM=CrdmvH@S@7#&`?$eu?>qdavi#kdi+9w;)_`sXbn0}To%o%d?Hr1`{ocziB2D<63|GP*wj-Sr7qrja28KZu4gl{RP@t8 zJ9s&+(8r{d`p|B`;zJPPBjV5S3El zMSIg_6m(lSRr=5|S(DJycU108nG#M!_Avq9&_JGlDepK*_WSl=-(e0(3nlKo1N~D5 zug1z+j}w_dY1aB747w1|8~h1<>tiB22Exx_)x~>-i>K7k>z!|O_?Y}HcIh9`!aaG2 zXrR6qjR~BW#x~uhwj{6HtoeV>JM=-`-4`kEY5zmsPu`)t$9wWV{>88J*7eGp_#@&r zyr}CJ8Ws7>Yjvo_YpLrp8%;JpiKCZTFa!g`ZDQnD{k@by)9{)l1Gd; zynpih$sJ^8@%=!!GJ963X>rxzEW!-Ec$4=# zTnHIZ5YDB4z_U3Y)P7kjd0Hbb5ZvZjf)tj_|8yVhex?I*9Ew5k`L^5)K4to5*}ZtkvD zZ}Vk`v!b)MNbq~s>D|>-CQ)C}$cqKPVCy%8vu^i=U4r-}?~^xi{;Ji-SCb`4$^`t< z_s?eHG_C5FGh-80?cd}c`jnjds7l}8!NloW6=-dtUPpX@JSvF~iG+p0ahkVNCT=9D zfxMQ&R^s>?hrWL(M=`|7TFgog^>xP+uqrQ^xD=&OBSt^hFII7CHCnsnRh;4l=w3u< z%0pSN*MZ0R<$8Uy*T~3z&_A=TdH0Kihwf*QEVL)oHY$EI^uC8^HmtA?@kOs^vh!oa zv~x^Krna2&D}4Ax!QOsb)%Fv@Z?0Gg{}+gpDyWBMGyCb=D&tgK(>ql5CI26F?;cQ9 zmHv(Iea_iupM%Jy4FU}Xg2BWzPPt2}x1n?7a`G~1rGiGG?G$UK%qg?xH;y1@p96@u zjtC^BS&H$Uu^IR1ae8M0m7C-(6G5}k5YQS0m8%K7pJ#6l7i+%n@Atlc{r-TnFKe&$ zthJu!S9`M%Mr#e>#RF*-b)IM<7dQCQ*DHH4N#qKxlz%P4iiwI{&_K(+lC_nAG2QNO% zC}AQqVHc87&3u?yuWD*yP0+jiyrw@gd>7(V>}Mh;)WDjf0k$KT;1%AZmLUw)msFdr zs=mQk_3JHzdF;$?a4Vu~l6ACahJmc;3bVXsBhI2ccI2tgbk?sfsB?Sj!K~o~WvC9= zG>p7s;FYOLV_qYlmJbMyu7PDkU%4Dz`sM3$7Q-UO&r=SPs_`M!BOOn+QEoln>%f~R z>AQUWdsGs*;(3mJM7xk)!fW@{X7(s#G-#64{Cs9y>*yNV{-M4?y6fw7hYs4HBg@qH zCQGQ5PPepN3dE6%<2&o0NL*d8@{2x{+<5$4eCF{dpkFZ_(|po49+)U=aSkWSuq3zU zv}$u>>kmDUQ++PJNIg3XSu~cTlbxrJ(7r4y+N+;Vz>DLFYZAA_SxU~HT>ZU?%<6)B zn*}ege#r<-vqa>4^vuSK`g;uwVXNJCOr9pM-XyK_V%RIcgLZlKCiXIM5X7iL+ze_3 zbtCVjcG@+1H<<|T@VCR7?+N)*MI6}!d$!V?NXE!yp$>h80Y1dQvfp0BsmCn8VctS~ z1vamN4>IFnTNan!w(b7dSH3_5lMFj^24~_F>-7mMaUeRyP&s}-MZ+()8ILVtCRVI2 z*q(^o4C!kTU%V5rX2NPH+%KncQX-oK%DSqJAIS`1S6Tn3EA%lktLd4DX6c-X=(o_4 zYI)?)KM?oS+@De&As5HH%;x^p1!FIyS|}z#v2Arh$brZRj1_uAF%-_lZ#1kfSXejQ zlZa{57dEl4n|j#nW)th+|A>{0*63(MKkN|zwFa~QAVD<8=kgJ0~Un&Xj5`p1!)ER7Qr+3%|Fe91gam;N5|;kVS#qWp#|c zQ0+=QEm5ujYKgwN=K{5qGW{X=6sk4b#y3q$Ott6Qp=amN$|PH< zY>E%H-iqH?J!^Uz^2_mu4Gq%5P?hEimF6gkby^ z%iR0q2*<1Pl#0m*aSD>e<-C&=@r3`;tmxn9g`fwSxPs95lz6Etnf^mNr~KfX}uR(%~a?4@V|=H z_b;pO&lXj><*8r%E9AvMgV`PO;#foHzlQf9hW=0s`IUHZo6~SRnfrWuBGICJz=O>p zmochPG{S^Igg=DMH1f2%k9{cKoUpA{Fm$nz&hG6pNAP4Mt;POvFbk_)oxaJY?M7&_T zZd+S1Z*9zxuh&jWoOtZ_NvYOv6VCzi;kne{Qn?tSnz<@F2i`{czO@>!I*RyL+bbMZ z6#eSSZzxM5#lMQFViS(mde*Kb%q~Ubm2|2 z=zN2fuCy4l<6(in25alHh&Pok-6&xEfBQ?!>{(d{pXwUhYo_4og2B&ER}ho)`|0B= zX%*A>UX1;&=2{sxh0HN|XRh@67Upd3q{P#X=N;gWz)UI`V<#-Vt71F2!ya3$Of{xV z*A+y_Kb^Ocoto&@=uYCz%v|sdoZD_&@Z{+&ihZ{AbkUq!2ig~v5hblGo40KHDaUED z{`OdVe^d2sMaw}o8zV;Ly;|A_V8!VNmgQnpawn^N5|-TkX7sQj{;haP&-)eHf^B14 zr8~VKDH4CW-DY^-^r#t|XBdBT{kcWJmm1rA$7yi0g=Y?zp^oWIi-SAds!wRTDNHb^&q$>zNHbe_gZKlq+jLeDrpP??!9%uA_$ zjhF6i&`NoDX}()}$8>kKCsjgi&9z9PA}5KAyc4NNClmvPlk?S zX?S=rN$w=g3iTXp=Q6xW`jHU7`yc7B0&nkI3z~FkmQ}&OIiNo4U0<{~CYy32LQ3|n zgZ(mMj?ZN+?m4jS#*R!dE>3mHi;}0vQ$LAajOUA33-SgSlMn}MQB9{R>rAwhZf$I| z8GP5lZ(I{v?&<#{gEmCuQ8CG$nK)!aw9WGKKO!4cv1M$=hsf1%ER4QiZwXW zb_lTq9ad;mm$q;Hf##kpLSj(Y9<46TK5JV>Kz+#!Qyh=ymwT2 zj#ji7y9qw`uQ9vrbOuQ}q^&o(3nt6`OnxGy)LxPYt?4U+w)4G+jh6}AoMN>_kSkk$4=I{PmSwf9cK|4EA^ z9pB!f_y19gv`=b?-)*OvptGY%RgJyK^`F1-lu4U>@Y;+eU{*W^h!3IvH(L&Vlo#T443cU~h(+Lz>C%RI(S0 z*j*BzqrG&*k+m1xr{On9e`KxYsQO+oIxe|5#t-p(ue61?C!|^@+FxUCJtIS6WB!+ZF=yj>If0u-8Z_W0WTFQy=wb6<9GdL})*hPhL;_@0^bGO#>;;ynszmo5+cm^we$B7f z9XvHZNsGECUF|Z_>_FerO0j%5#S^qHr?bB}ezha3Dv0^`vWxqx&%z`(^y|;9e`H%$ zRW$RDW;`=4Ofp$%Y^wFTtgI^J>Y$Qi&Xi?U#WL^FwZ0eEHb%bum&7k{mCUSdUYmFs zcG~4Wz-%2NcXH)pzAnRmH5b`$=t}=}+20b6mK{y(b8DIvqM_3#cjsm%Za-JsKs5C2 z5yvO#e zar%3_m}!m|oT1h?2q&IZ3==?KlagZADEv-F@vg9tZ2Os=%AE!Egj$s~b_H7r;hT5ogQ`r{i4IzGmbR~Q5$0&?CNzZoKVCVhY(Cb##tpOv zj#t;fv^Cl_^6XI^xuL4H09grWUKZDaI9q0d^lGO65 zCN4ras(ZK8zOWP4`KzP*T!sw40NE`V8k{hNq%sn~(1oS80M4f%|^wX!FKlZ{A^8JS-v1VWHqhv?)!=%K! zDsleBbQ-xtMA~jo`+=l~Ns0d{4uHEFu}ik|$c8fW(86B#7)BRT?jB=gF1$oGH+?f= zE4&v#qJKGd?6JqCA}8neJuDP?KkMs-6ds*wW;_3dErQTGW;rHr_)=M3? z7{r^?xsvBw9xH#^flNI4Z5!HovfzoFFoBb8f2=@;ux}pe%S6=phi6EpZs6pDtU2*- zZrM;-)|B_)0P;^>mu-*LtflwC-MXgL^z89#a7Lk1(QPYOH?+0-=&`U0%S3*nKh}`O z;OQ+-7kxnA{~*JM1=?CzZ(S=R8P@b zBZN#~<`!k$Ylc0L*{`S#_3`FRiIbU-aw(hiDccJoGgh#iVNqFR_)Bav1)~c=pE%^oRu_C7KQ6e>KG{E&JHO8JYq%^;7Lx zCAJ%xpT{EK0-`70KwRb`dA(?a$5!5qj@T6M z1yX8YZu2T9HPi0YGGz&-V|x`eum>W8k-hY_p|FcqvW`VSOk~d zQl`@wktdGb#JHbBEn#bU8XJ9y^9I(J87RMk^BtP4l!9)|Xa>X!eF4 zx>8o$!)`ndPZ@QUo;J#Ykf=r+vzPfacXBR8*(kLixVP!Ii~2nHqi_@00~rT0fk%W< zQ9SU7zp?gP543}_6mY4k-GzJx8Xkq;FXZ0?*+SLcnEm{$b$g)yl#aQXxz3Z0Cmm$< zRQ3gpOH2-N{~fRag!M0?5k(XP971Gh^;A?}VjCbikSO#syFa{hJh|i58T`n3gR2R( zNJW~jZwlhC+B)2Gz$qZprCI_Kkb8Mrw=OlI=uq$zg`WpM5qc=ABmsD;&CVnL_VfW+ z4iNdV>KaJ|+&0D7!emv$Q(`2ou-bb+pJ7@#KVG#i^QDaDIjydsXl6Gu_j3F^wT6wI2nNn((o|27iei`=>&ketCW4bwmcx>FJDF)GQw^%dGnK7I2J_Z@3{K{j5 zdG|8l>Hp6?`Zhnyz2?lO-+y$|%MgoskJ%Jz5nxf&l+)THbawk5G)&nW3J$hgfVq{o`{qi(B>tmZd_C&UUjn(=Ov396- zqC;zz`qVb+ss2M-w^oYQcgk`emrs^2;zOM{k3;@>o5XkGY>?yV4pV9R0_UM9sf9F^`~-ftWFWo`6QYJ zLuCh*B72#%oAew}=NOki(K|X!&HS(ds`I8J4(i z)RS@la?NL3gNPd}kJY?i`%=HdMwv(m^3swn+Dm#)CMvqgKiGJTP0T^Iy@BtLcXS6y zf@R-Bv)>H8(1=~*vSl=C5p_{tK6%_&KkbXBkM4#rub^}k!^Bxar zrdUL^MbkE2zJ=`DBjV3c+!>GbrPpak8}w$N;f4SqgUD~WPZDHR-TJ7X+*xOvQxu;O&*Kpr)AnhV5dSH?+XPP zcJsei_&kdQTMKc{CSBAf$k%_PwqtTPex6nGIfHdrr#L%w$dS3N7j{u;$Ny1=RqDj5 zeOf8b&{+>HwoZ?-*VMD1A4{MSswK6+S^QwPKv)b9k|Q=z-l1FCUUq5Tva>Z4*X)r= z&rh*kcAlizE+cgPIj~$pZZ+f`4~@mwb_fYnD16kM{Kzrh*I>Uu`YuR zIsC5f5DbW2RY=+u=|&For2Ua{*Bgfikm0;Wj2AVFmOH4!5R%Mkx0Z&TZe z0Ytciq*g9%Huz-OyqL_-34X*)>cFWq-|#syI$Gi?Tt8F~NSntPwqq~9!g`_n`AvPv zQ4WP$!a=b{gfc{+%bXTcsd%kn zTsI$OT%X>_&}#Jj+K4>Y+NzG6^zZWE>B#2%4y~}#dtMB@CUuY|S(i7XTkIgr_j|9%aO_?^zcYOXji0uTKz6Yd`m3 zUTOlxVthSj81qE0QcK&crA^|TQk_1=z{b2A`SS!85dRtYS4nmfXmbbp_vfhD`(_Qt zW*I(biIO+ZUbGN<&)rQ2R%Ca~qDtSvwiI>sK`vtVHwyDVL=I!GV zff(14?^L$vJj&2aI(*g(}ePD_)~e93>B^m+_Ce%jN3k$6#%8=0S!{Qn*bFEIB`p$??CuJu%Ahq`Vy?Yk3X%*4mf;oz@1= zK8s{%>_~JTAK8uRp$9ao=8>Tn`ptq5Y>{_-#6;>xk zr*FsPNM0XMfoMzmJ35a(D+KmO3J=Q@{#+)>2_2*!4AbK9i7NI^$jy)K&#NqPDRu$ zcrVfU9L~R0`xF04?b~zlU${N{JMuvB$lQEiCgR>gGmmcwrc}Tb%cKG(?XDA;GF+A< z)8gc)lUh{VQv0N;iO`$5@twVKQc}aSr8(mdQVc71g7<=kuk;^RkQZkyWw*AzA-kuMr)p=guWW%I6zZ#a);xIDO_T!obQ*k*#b4R-*dZ#h zKVER~hVg3_HKtet5)n7Qr{|Dce=r)8-LBvfq^dR*&%NEEy7{3`7%sgcZ=&f7-*r6=jJ;)DFa}|WS z%CbGgP|3{W^dwrHz0fKD+H%1CSbXo6O8oEK(&?rW!?Ua1xs$vX5bXP>j9;_7asQOJ zx9mT-f68+FU!9Sayod?5X3b56M%9gP3qLQMdC*8Xm{eaTn~JlD3`Fl5@QysOJa3|z zuhsTaZEQ2>8l^h7TtVcRh>HJ=QDaA86!#;HDtu-bqdr*t)A)4eHhlWOYq8<~phX(j z(0FRsSk=2F^bn+gGUSoR)6{2)V|lnLVK|*ba_O;{gOx#YQdYEaOz--p_v-s2WY1~0 zRvXQ7=ppP%E7h@9YbQO3kRHo4z(<|N^zAK$hlo;%Ht9?g-W@}2hFTDd8TL(~mUH+| zbw|mA5w=jKFka=VhZ^FSZD}~7tz%|>RnW~4{7b0&q|%d zr60|gzTasOv!QKBlv<74qyp(;i-Dj(7N@cD;=XY!m;WtGd}|j)l?HZ4P9*Nc`}{4l zbM0kB{D=&9`+#@*Jg|ECy36aITNfEo?L%4t^=tsO01BTwILd?xTYluVkDO3~@=l+B zCoH4_vDPsf#g+8xbJWtlq}=R(MPBslr- zO@}t}P4BltGa=|1gP8KA&SmNuur65{ET#lol}nWj@gynGWR%t{HjTxYi`kW|_*M_A z`0Tg18hj90CW!qsTXD=`gft^7U9aN)k?HEJ40}I6Gf8~$6GqxHjtyMDvFXjt2jyiq z*u+VyP0z;f#jF-qls;r4w=H61<3{d6S;m3pGBaB6M>NC#O)KqHdeBkTys}uI494x7 zG2qrQpShp$Ua+v6@WLN||G)1~#pwR9&=S$S8;|Kfvh~C`Ln>*98rHZcF~W(sOG%kF z(pO4LolK!slEKK4#WVGZ%Na!W$ee_83hKwCr0bTG3F4bw zx@#*UHm}TM*S(N1DW5d%RA0l)Q!|$pacf*HUK`dqw?7kK9#o8pBoqlK-4{NPl%K_PJiss*{+IjtVl(H(kV_~~c) zxm>9;!kA~2E1+N{EFzmWw5ruQe+p+JJbiS-x5eO zVtxsu_UudIS!|%^J{x^hYiTag_1OqkDj)ES_QjmFCX}C@%m#YypTG#I<^N6Pr7K#k zo1WopVi00s*}Ab;Aa8Pa60_jMT!H5XEzn%m-2>OwpF2%oXXvChd>2i<4zg&yUbKQd zdAW4>3akA>nTzmE9Z`l$548dV%S*Z5wJTQ$eD~uNpUT@)`uyn9p;m1i@!QJ#4b}Nm zrP@LdsHIFprT%?8bf_czzj@o;-AHfYWlQ~X!XJC5&3EL8M3%NZZH z8Mb*P42?|Z`pElewL%Rvq7J+-NgAx-x%H8yEuOCd+32t92ETOMbPLX6_71;w*s6LkwH+7xENP<*0z z_M*2}hG2GoC_dHZ$1J}WJNCwlsk3ulx;Ihjj%JnCST^+(o_!O7H;*@^&IlQPPWtDs z@51x43-o_0eAMq6dK-%94Y=VlUu%=@B;az6YV}D63OX2X`Q|c@j=NE(_e@kCEy9rPu`B z0vfHzhz_sN6i9OIs#kl18?&M>;e99%mdm`2eB-vY`UI!ImrnH(4Q{|&liL{1xGRr5 zuD&(J^5Nm&Gz%l|yJ#9~i=24T6d8WeD>CB2F%7d^UWY$6F9r^n8csCK1_XsPvN+f3 zZaB3c(E@^){a@`z?124Wq294{AGxd5o35doz}5a|v5VH;!7omG@*JK-mh#^CGj=?? zlBjrH$5+7rvCDzC>eqhoyF*mRRzK9_HF)h6xeYclehc3GAUy{$r#eisjl+q{O>hP8 z1wGXm{aH&p-7;$tjE6sly>JVMC%zr@{8t^MEx{SxWG+$0ujS#;R4yHy0Xu6@>ABEU z>Xl0MxCTEtN4+1`Dp5vraAv=ZnIkny^bAoMmYr=dR!3Au9h!FF*f%H7ojx101~Xl! zVlLq}KZ}#tZrGWX8!{80@N0W*L7J|-&CUQsA`P4jh|k)0~!_Y}+hj&2>bAfR@llus=&3GXI&P3@Yuc>d}6NzYCNWNntM z^2jzUBii`n19samM3%X-&Ad1>F;aI;C&(3rh;S%e)3v=;KAXk`6k`#bwI7GZkAKO$ zm?9>VeOD)TNG_BeEb$yc6S+Iu97|B;)P4-9+MJW6bjPxNKS2KV$*Qg>RI?wHtJx21 z0ZgFn%8#=jFu5}Hn;VYzA^QQKS#1-^2gdk;?nC1>9kn$G8|D({P-JUy73Xe-UIypk z%mYa?{0KhRWnNEZp;w9M1W=3} zeK+dPIqI%@)E#dc^&Rd=A|C+(G&dve5Kn0M&N=F?dej|1>O1GCJJJRX*TO^hGJIzn zb>|#)M_QWUl02+Ehwp5o?wq6Usz=>X&bblajk_$8)2;8+GR#bytnMSj?zC zy1I{aqovssv-UVAXPc|_(Y)FJkgfohB_%k!cJeR4&fx_*A%EAAjYOesR^ugh zo0bvLcE`{;BH_k}5hf|NJf6JTuwL{>WWA6;{vBjv;^`Ze$bfe&l^FQpKb0uAX|k{y z^}3fzkqo>OKI%WJYx;1>fv*2lQvacI6h>8#y0e*w;X_H>!S}4d$u4wC@orcWkPT2w z0cEe2`DQn)Cv2|GPWFOBs@#WsctI#ZwkD;pHIb1kt_~$UUsn%)tvC?*dP)pz#{v%3 zxmS*R!MM=j3PL0^r*sMg58QSIMKL0*6?VfSqc~n_ZAA=&rd8dy$V!DY6p)qkS(_y7 zMU7cID+jIxy6VS~C&mGxpo?vG$7Hcjur@YPimyir#mTW*yLd+7jcjpzRY7TiWba|b zy+JIp&71V>3w-3Z9%iA_-*li1Un1%}zC1)k)57Q{BFl63F66SVu}XFm zEABNR^O$04V!p-qCP44cU&g6RRP8?dr;dmtkHYRe2InndKTNWP9NrEdNvjilsS-YQ z(0PXzT~D+9e`Hxml9r1o#!lI+CgKFJ?B6b&l7_&C1i0~iQPTa`!GX^r9${8=4)V+u zCB@ZbMIUDAIr6)xRR6iMcE_E#t*_g zQH2?HKkch7q|W{z$;%N}6`GQZeQaD!Y6>!<9E__CP1ThHrX#7T1lQv&rFJS;tG1Tb z9GX(P>4T)Ws?-!OM=rh!P4$9DU|cOqlPuRnZ#|_~eH%JUEnS{Ei=M?D48(N>jp0879YjuVK0;)4L zWw6d!TAiV@sa)DOp(#0efV7+-RohP0%B7-hz&{JEt0l|6N*yeTzGyX4$s>SrmRha` zHP(ivP^|+Ep{awlddkj1S=d^J&c+utsIfLxEtz&&w0~qFJ2Y54MN9Jxx(|}*l#Wih z2TsInYMN^3A3bZs@3)>b=e^QHp8FJOqOqn)cxd1Y)uT;|T7oD5cG0}oQgqQHF_Ema z9kvIEg1Nx&*OP1tKY{HFC_LnExCZU=v~omXVKf^t;q4IElfy>Fgct;liH=f&r#dEQ zr;0CWm6Dg4$u(RHh=T1G*7OX>YvrD^2s(*)XxWq1yK|-;-Y3W8JSj&Ujr!bpe2;xH zsORxd*`pdxHo9+GUQRfhFm39mQ^x|b2*)wfl%Pa}W2bELgWUd)?Q%A#;OH9^vrzqjF{c2x*RR_ea^?BH* zTFnCrL6Z%*!~Uv%>F4<}?eBTG-hjLT=!@G*afqs-D%g1B-nIz=S?of)WILsEZ5_w- zg~?C4R(B0tdq#9V&%D5cM?cZcPfA#4L`L-8UH#iNZ@;@E8AVscWt+hUc2-Eqwo20)7%v_i-UkwAf4^^) zQ+A7{H*|t9ftl#iN9viV!bydCm9s9YpFy9=&d|!#E5&~Xk zLd{bQLQoDHS7FUq=yZ*v70N}neKke~vCPIrGiNuSn$mn)=D+1HI9VGkZ?Ue;FUX3j z9$;->wDbjS=07bE3V7D)49S~fu-aX);8zl6>$6SDZ)fYjHC(Xo#QdyUC*)6Hq_o%g zVpCi`q6*uT+&@^Q%QjBcUFmfLkNy$4i;p`7n=_vLOrlk{^0t zp|k0U6@4e=Y*T(7us;`Pu08r_bI;0venbjC3Hz-n23S@1ki`bxXIt$#ZqZn5L66XH zFC$jVq|fr>Hor1t5kJ|U<$%qcou~v6o}v@Ha=~#{7id1%Bx92-1t}`jb5$7yY1VC6 z(C`d)tp=RX;^Y~>_4r-U{X+w3>*%fL=`-q6XrCxAdRERj_*h1q60&pp$@`P?qYH1n zp_=KLEgk)zXYW(Da zO?n@8r+gAB2(j_)4=l^<#bHgv{_bd*prAFg-NMkx~BPkrN*X zi~RY*u*j%oVR#!B8L^T6!Xsmz3X7chx4W|JJX1WTG;jBsNozippLUo+Cg(j`^@3TL zmt%FAdk1pOpA|)JGhfADd)tEYlu5Ry9oc4uv$1Up&L@LwhagVYIVp_u0rxc{F5Fk8 zxtTV}kBbq!5_GVH2|;A_cHeI}Tj^Rn4`}{5vN@XR+3|Cyol@xD=vv3qc#;h(>47a- zcTHf>(!~#KuADyhy|K#CKAm#-W4-kH|76dub#2Z84-m$(>^}Kr8F>oYKRJnPcl^KD zOdFzMZgul|Xw28~(jU8Zi181d1Uz;M?q$9!fZydhDZS4)+3}tHwEAV+DVzu)`|O^i zr}6A%!1KwuX|S2!VAAf=_R_U?h$(oQlh&Z^j+f!tm0-yB0;Qk2>vHT~l>)NbX3hL4 z)0S8&I(|TgUn3;yNT!-uTZZ`A1J{C-IhUBjYx53?fi;X3>yKY>i)q>@p{SihZl2oW~p+ zg1xTnvPYgIZ+8INgL%OdakT-@!w!0Td9KqAyo@^h z%q@s~g4RxKcPw_a$nZ3Pl|5U#S z$qS}l9siu3YIT==IU>@SczLHb!b*B3y1-c?|yy~!EgDBGG` zUKg{%4}|MMD_Ik);re^o@T_|egy~~4!?I#PIlo}TvVL*kZvB0kcW2#ay<7iF_U^1- z9=Iz`2HlOvZiP26o5l!Of0Py7I)yvJJdZf)_TQv4TeF6ViuY7lt!D*$Wjo|FXB;|H%>aVOkGV z%W|>Jl6HgL224XnuEv{KKk%1^zcBnY_Ts+R-HM)+IL$e0q|Lm~0mLJ4dXp`=m%$~= zzuum|LA7P4+T_V?mQ`0hb<2-Hw{|5Kk~8gjDCZ(9nXQng%!eOh z`>Sh@kDuW}WM~ob-fCq*p7vOq2ii2eiFL`4mG zV|uKrX}z|NVRo$|Boeuj1Rr5@iLms`fQ`JkSOjV;BKm62s z#L}7y_$*JY4?Z0H8(jGfMm|O?Nb17r@s%z_J z({&I|`P%3Tzm4>}e0|E9fah?=wJzZ6fag?=b&JuDu3at0@WEdT{ZffjHazt^RjvNA z+HVwds+z_gryuZt)aC)_Lx4toirMr$C0#gO6AeZk+~b5D3b;Zo{Lx3L{(d{&x2Qv-aDEDU5a z3*|Q8P1+fRwtu7Do1A_vNIG9_!ak*94^GYrhNy$^Wi}-K1=1mD%>H7m%2#2a`KFVO zzHuW@9y-fzDL50#>8@%3jIQEGzRkB;r@!44cjb=+-XVAU>J!p>ReDdD$Z()G@~7It+5|6DI?bHU|bx} zP#LivHYal`8704y5f|-cmbP#0zx_Mc;CD*kUeq!8T@Zak-(ug;yyGXoQ`@WWw4y!4 zco=HWa(jCUEOf+Z_}W)+j95~_NG4==X4wHqnTTh)$|cBy-x|@TvyKsCcR~Z$jq^o6 zMml0-B#RrqEzOMdyPbH(FiRPRm8zPVraRsJO>b59OWC99TL-v?`j56PYMazH!7!@r zvNa>xwkWaaud~jAwk<<#mpAJu>#Fp-%Hg(?+&IZ-M%z1YYr70oH{3SOo5=0eDFtqw zklbk{-|pdl4`k8&xbR#^?y@STN}aU9ZIpuR86~h1YlKOiKSkcD!+7XiPSmx3r%pO$ z#BP0;MVb$sa8_EBy_g?kgGJ2V2fS!y6gTEMn`d2^m!@_655w)X-BM7GbVofb$0~Ko zKD5D`80i%1aa5r`)XPJ|`S2y&qb`Ths&L(m=x#>+IP0bQ9Q9pGu|7++oQ~#2Y1s$g zE}m(6-`LaCz;!Hzk5^M6*CX)l1BzT?X?mxnr|AfHeQA4RHgt(_F-I|tro>uZ*fsQqj2U|-+S;^GI0jA%}$)s^DHC1*$EnJ z_f^~_*q6mJu{akXnt&JbcOrb7^@%jco$6eHZdu?b+w^MlEm#7u=wF|}G3q-BUf(Vb zeE|L{fKlmmYxTEx8npV|YW?n=*B(dqRmSD0`c9GSV8z3sJmz7r4MFCR@scAt*MXLQ z09V)AyjVBbX4owi?mvu%o66I;D9Ny8!}&D4^uAM^C8(cA-6a;n#Uc1#_Q2nGOIpnt zs1ItL*GI!TR43r2^AdO?0p?C7t6GKGBFZId-_?G@z8>@W!%!RF4z=;asPTSlG~7Qm z-Y#c1GPT_{=D+jQ7uF{k2ge$4j~eTKPu<#BQ{6PyG?$8uxdhx)w>sW~u%qvz;coG? zlXfdMdCnYHav;7>o}+XlHdd@C3OxRCofc(9Gb7BohY^=IGc?XZolTuXcaX0y+GrP- zW6XG#g?)@4%IkzVGD~ydMx6rcgtgEdtQGjC*&@^j(vE>4zVAl$E+_u20NiT*pm)B6 z5j%l1b@wm|eid#n@ZQG62KxE}=K)`5yHJ;iy7t0fuvLYL#_y-vcO`SISP5KDmKmjb z5bi|OjrL-fGgu!M6#@S(!ty|MZebV5Nau(KK&KCD^rvvVRnWH&Naw&)jOC!qa`2E7 z79sw|fa2(~2qy3XC-|fZ^so+lm3NFWg!hE=QdcEbdeGflUEVGq(A{Up7}xu8jFNns z#kasM@SSz_g!5SU>a9{9@V5Yce!h+sgS!~<>QzR8y{0hN#40O}>0E&()`ci)uG2WR zc^>x#JZ!@2!RIUWF5ZWc`dh&7jHs`FK)M8r%dQsi`Ky4_i1u16Vt19!RfswoP~Yh) zoe+fYmjtn(P4H-}O}F+liYb^CD45;n2V*Gq)y|R$>!n%CG8-CYy z-Q`2PA?$`U4&z|*W5kq8IhUICAa(Gpz-OS(#EZ2)yRdJdxuo%vHW|G|CubFW z{M3Gq?4z=x8ZoJ>hx;ivgMYz?xPRwhKf4F}xfA_t9qi}M|NDMo9dL0NPcJ=ipu5ce{?x;YCcr17UrQRWhV`&6xpjb^iKZT_^429pqs6#kY=L{) z_pQLSbv~d8$OM0?XGOjq_|b#!5s~ptqPI%}>NAXCEHeKpt>6jVz<|=@W`qWe_j0V` z7-y8RD(m(`yRl#AI_<+M*)=*P8#Lk=2bgN$8Hx;>rc11F8f8tOx5d1^>2CgLENEWf z!F!4RHly$TR~a#|5;S<4B^qjat?n%GX3)*&bPxKcd1=5H4)Gsa{}sr{gmW$v_|MtV z{72|9kWMo$5Jwg@c;4?-Essz62S>??doe-#Jg*m{bdK%{%6>r7X7WALfOMk#K zKAn*k9 zeltJncd(C1kr!E9=;u%$PXpfWI-ODnz8Hk-^lDm%bkZN(pf^uHwQGfQgWuGtJc{~B z-%wd05Z7uy-6Q&`T`NvEubu5iN&4n-r<3INkojNyH zKVw{&2U-IJ;G?(#&mF@sN`JswFa)1=EgI`B;tI&z@B3(UH+QGjCkN!_MfI$7vl8RF z2=joy4((c#SHs$xuGY20()x9)#US{$`--uR;A4;*cSCOcvIY2a>^o6^h}F;3GcMv2 zzHOkpt5)fKAK1ep^W)2?kFT@Tg(;RZTh}7<@Se^#E^NTYXuj4S(_?@Hstr zY8mQk1byBBPiDlSev9N3SGJK6 z^xzYljXx)Ok@&nSqY%Bkb=unndQtXOfoDx-l$6t`JBXzm?~1V=G(<9Yy+!iIeF5s8 zTgQmO;3duIr_ijecilU%Mqxa`JBgl@I^2VP)VbvM=>)(b^>={|F-A^W=SW8Bg8YPa zPL)x*EJ`=h!cw~`FkVP8wVoHPhowAPCyMn;0sjXJfG|3{Wj7PKtS>zIA5t8vBi$K0( zh?kI@=f;{XreDQ+-Vc7lvo7KnZ-HJ&9`OMm$u{X-bHV%dhlsC0rdZ67TtYakWH+d? zh+-PYN-aV9rgwvmy9fD-0y-mEMEp}fWRbn93_!Hf^vAlh0%R5Ni6eB6v7>o8>++5L_C-Knl&)sT5ZJSj4A@eo$q+YzheQ3* zt`)>}r?SKY)c)WbRfZUnm581^{n4&986xb)kPPu{&5#VC6fPlMDP#z3%!NA8`I{wJ zLvjBqWC*~huAhWQ$=FK_!iPPAPP$2R=oxSATEyN_c@uOF9Hq5QgbbnL63GzFRf94_ zAjTVistgf`HI#H-kRiUSyA(SpL(m>rbbq7K_lM9|G_(Lu4t=L&FM(WU8ZD3BeVYs+ z*A2=LJ4VP5Tbtl5td_81`*Ll4vLnT92Xmt%qtIOv%1v6$eaurNN{Z!hBgV zJ5cY+#~eaFQx-v1a1zbq8oDo+lW4vU-viH`pm{u_wrKw$N;e=^VE^&f4VAai+DCGP zDnmGXAVWZo0Ns-up=5)Xs4@iXib#ggH)%3NRyyPUk1_;gyZ7;Ty9}XkvW%7?7FjeI z0^^ljJt#v|(*FKvEcW&S{6CeqAb(-6=)yQcABzmYiQrEdi`F2liAk&w{4laIZN$0U zc-Hks_bOLU&nf})5joKxmMEF9#(01g&UAv-yC7GC-v&O!2;(M0HVm*z0cY-$o@e}} z4JL!KxSEmH8DDd87`F|aPBc~`I>k=VK`Z`B=zM^28T?3p&O>flCHXbzT!!{lOPTU; z^?voKaPlt})4}s0Z$bvpOSSvp@6*moNA?*76RjotEy_61X$tuLIHFPP>n4{oB4|}i z#@b-q$%uS616?!Z*lx8=*Z@O+%irm;2Y~0HUHipUv@_sB?kA-SZOsW}NT1|_{jS)& zgAtoc7_#Yw-XzH7;QF!0(jHH@cyjSq+Qh!_WYhB+9J zbS57~F0@GR8+1xb2{H&9pLWq2U2KG&qEa0j+Lz-Dg?RW??Cn=c?{L@$^D6A9<0_3! zQ+7i?jg8U@c(LBQIE>A)I-`rj*p$~{9j38?9{w5VFM!WtAaJ-DyaWCa)F*$)v)ZXG|D@!xoZNXrGJrEyFl$ z;naCy8cwNrS~ZBLHUDq%w9+C{ojCIWo~rfIxHQe;+hYwGh!ol}Aa*$6mBpdI8htda zK6P~@ePAAX{=ehr*3tNBGWm$vz|VIK1_g5pefwm!@9%TKmz@@ZO`J?)Uu_X`XspuO zAwR5=0+y(HJ#9RQhMBQ6=1q?M{ceu%)UDF6U;>_6_M3p$tTbi6f$&V!D;Dwjy^L6x z4!H(6x}=6x@f3JQIH6b^N|@a>`xHC#nq zBpU(V(YPuTt~RTKZDqK6V&~iwrBoQtvi>C7+v?)zc#Jr{tEa`DQ49F&_k?fZ?%Yq zzeCox)47;QF?+^;GTv$9FX;>>fio~|=Z{|&czFQ&TF`&1$))O}@qNHWMyc;*#EVWw z%)iV?2?bsvUtn?Zz;)uI2fK{mQ|eiaIJc8g#$Ci5G~+C-N*lLk%yn`H=tv#AYOxt! zQ{%WE)UQ2b$^!-2OzmI52|t}pbPEQ#Pu!HF(jWLiufPZO3(yyf$rsTk%~3V|8c6@8 zj5~!nsvDdm@L5fE?RA3>&|X@xU&Pr(2j*>SnPe}MnH>SM9CqTh?aV^9aq+`vD8V^kM-Ni6m##FJnv zkfHJ=tP?_a$0{MnhNwaHz-^qhz>=JNkztR;!XArt1@_`yDq$f|7P3{lOgz? z?8d$q@cGKvk9PyUi;!=>$G8+Q;@0n3!FZyacpm2dsvwU+-+ce9!5F5&xCt=&5{z5> z)OK{fI$`}7j3?0m!58*D(JSE#>H2a1opw*}3BE9#AIxT@4ew5tUcLB`Yx7O$-oXch zI#}1)JHabj7$M)zxMr`%oPERy&x6-B)IzT2RGp5HYyf_*2fozmUF%KIEeU$py9UUD z$*iV#03ELGm2K());pAge1Ibl3=)y*mtgQNY*}$SV3EWZ@0di_WV$ zMc1eoeG3?&9{K>j6|!~#qpUuONG3ch`lc~%9rSgpuMa41Cae2u<;FAEH@(S7OD=+5 zeBpU;k&~|18?aA<-2win4+iis`vCM-;Q0ZvPWl$MAd4@u(%tK!V+Ai5QPyQ|8=&%v zqaJ+xqE&I%8prk)oC zpp1PVBP#>(8c!QD7^5ET! zwsv&Tm{CTf^Q)xV)?gv+ag;fQy<;mY)IA71f|omZxwyQJt}}!c*y|8)2VVyt*MX1g z=$*Kz8T%XT1=1^tmm``W98&KEpO498VQ0(2&X$FpEo4#N!{7D9-)XNk$h$umkUQ07 zN5pqu1Lgs=3ObZBTKxpjtF*e+N7aM9+uE+tENGjtm<6MkO5<*<6GZO<)=rJS({3U1 zKje*O^esc*R8<073#{c8CD;=|hgAUDO8x}8UFgBFHi-{2_{IFz0iU{8Kpx?BLO15$ zXu}H^>N?f6jrONfC}{TT67WLUZUx{x z*my~`6Oe+jhiR!+pEm_#zk~Np0sKJIJ3akP8?FvWxphoaD1S?AUZTn->U^Rv>MyOa z9$4xD3)WHSMKl-y*ANUoSXT+B2#z}&Smo+2$do>a2X}q|GQ2?=SC41dvlRODOLv$| zV)HI|tp+mExc|l8d%#6?b?d`thADsu=pdk?P82&LGKvP74`+oQL=M0PI?0xpxW$m{1 z+UuMnXY-~plu0xeQha{{ItO>T4%xmyrpCRDh){#I3f5|9cT%oQUJqagCanO!KNLPP z`=D9$T3i?y_P#LiWTlp^hczEa|BdngL!mi^Yx1t}!Rzdl*JBo8PcGie2x={jVl z1U*h>n(@Y%^eUXpv=n0zaW+EAc zWF{>yGjVRZj+hU!62hVgXbHIn~DX^E|L(vn*0q#5C9o%mAd4rTBQ!2X_@ zj;5p(I{&94?Qf7zO0PhloGVgzOGIgrIU?5n13JVs!=cy%ZmOfwYY+Y4HR#qbr|Shn z-YC}5#9kB8JWG4R+EIFK*%YbQ3e?o-~87YSKnYBFN0liIdr0nIDK+b z5p)rr;xx$`tkLI-(-P1Ib96;%lEv8T0snPW7ze=d1j2Z+>D#EAkWhLr|^VqD}x*{ zD%MG_}FD6p1ApTL(^uqOijyMp8e*L3WwL0-W7SxH_{nSuYg>DUuS z-9gvN+IC~kS9$LFYk8rHUkSXtfHp123*Zan14{cT`cnnSJikBcKI42Te4+le z_f@(;R!=Ug1%Hg`GCAgcy#G$>kYpN4@`vp1g3ByiB22pCK7dBYrsi zZ|TXOuPH%)snU~^?4g1E8Bn5{iG0*UdPS#MojB>~73{eDB|Uj72TfyqWuXY`$OM_& zpXHlPhNZH|fb`^*KHHVyTQRqp_X@ZKM~qmBJaa0+sAE#%aj! z?4HTyDm{6jr~LLO`YdWUc*_{>d9I>%rY~!wML!aB;0nyakQx8B4xHC@Ueyf$r~@yY zEz7OecGaKjz`3@o=5*kaYn%@J6yF9j|85&Rt^T48e1!bspX$I3ubmg#J&haxe!I*6 zg8m!ruC5-Z|Bm}}{WrH)u;vf?Z=T=(WBPAue_YxaTmPy4TS{#Z`tM~@-75XJG2}zi zf6xA?|K`$bl3ti3-S=%i&W zDjj&n8t9t;jt;zKEtR~b!@sKoCtWbw*rw__aMq7eb2{*hH7_`s^S@UIuF`wR>%g0= z5p>0hSv0RVSuME1vsJ`HnlmxaR_Va2#%|q*|5^v$_~93I;53#9GR`MD@bOp+{gn=U zNy)#~f%E&C3OyQA^Q&~7A*&S%6YO$ub(;w+4@&$+cd=^02b1iL3zw;(I%na0M8 zHQuNqi9(j`pc!5Sy*FeHJh4o=E7A$D`>-;b-ejY%pm|pfTQ_;$QPyT_2y{sIF^9!r z4;;@WusQ^(jRWa#R97~moNJ(e;B^ap`U)B32q6#BYIzubA8RAzdl{}v3mmY1snq1$ z|3e-iqhRibPNpgkxojRjPn&b|Y4gv(VGWFTO)rG5M5@o~zCBTPPbuW_R5iOU%V=^E zdV2JqROtIQsWoRd%e3-cn5#D9`Vf)IYy-PzM0)wo;H5%_ef9DzI*+5eAh$Nf8Eqqr zC>Dy3eB+Frp5Q*4lQjkVv8q%QnIoToq4au6+ zCeSu25w4Og1D@xj{A5$*qJVTGG)?|E|XIkf~Og2>QXK?Kt?WLMdkj+zZ zG4dlJIiAg{u4kmVkJ zmT~D}p`qk`)qSu_N4taG5N($Ba%nv zHlm!wXYY5^4(Xh2L$D*MvJc^HN61d38TP)KHH9uk=?h!xy|8zXH)h)u#xHiSiGNmy zEsNeRHC;=a^+v5tz;}@6>FKk3iy2K;D)iCb^$U8_mt-l=nv9{fsm)PcXmVVj|4tQa zF1qMxCA+Y$AC7%PM~5^|tRAs|7D>6WuX7%+bCQA?A{*NPu46z zzUjHR60LOjhcpwcr&!*tDc8ze=ebY^tUh@06?~0w z1J>`Is69N=>dpR;R==Z&E2H-t8n5XbZ!6+;Lror_eg0`XVcW-S*yWIZjoJrzph?0Q z1pOw;|Bh@Q6len~eS5AAWV+O1+dv|K35P#Z|3e$DRR(poa@KKf`D`Y5d_%kdoHXLT>EF;OPA&Yxw> ze}O#G9(buX@f+-c3-t}TlPT4ll5p9|GSIO)go@ET$ zp5~7+4t!wixvGp*&s0X#bMh>#mXDa8z<|4L?LOsX)*Xmip*E8{%>RG!K^^EyT z!Paw=CyH6KKB$&kR@JkDuV)478RPFGtWDVGifKPLZTx0-F2R1ZNQ-$y@l6c&USdS5 z@mQlzd}Bmkb)e_2X}l)AJw4M(&nKkGu>ZSwkGW<ZSuJh-1wIJ zbE882vlXzvl#uPTLbgk!@yf-$tUlq5g7!CtU>=g?s#Rur&{;vpT6~|%_!@RwGL@`3 z?A`Rl&{?u`9NC`IdJX-(Ov|Qq1$Br03r0=$ZAj}1Y_=E)Co3SW+)P|&(|V8j3%a^Y zb=nooiA#|tJu_2GV{empTC5WlrA0<~7mynk!g6 zm#(~N)jp3n4>Gt5=@-7zB*>M8hVrM>Khe%Hw-7(nN|ryfGaFO9#5>lu3btLEVWtPXF4{A!kaJU@$8b%`6D3RV5=_n{ZiW@w}*M3o6can)n$D!7#x@K^; zMBqRA4ZdUiWu7BXYDypccmrE9j`!x^J;pGSCp6~Zy}TUr2FbLl92db;p>LBPf)#qCU)=7$(`$ohEjRn&ELCzG`1urnC6CY6~gF>17L0S^> znc~IfrO*-2p~uN8w6Lc~zKaV})z3<|3U)NN zc|P7|+a|tSNp-~DL;VSMGgbXbc3+16^s!x`kFmBg=J#nHN83@eWoP?4+8*^~>Te3O z7*S_wTpY$yPM(8(h^llmqg`Br`Qkq0iX{y8P&wI-m+2^d@aQc&Kal(Y*+J_W1O0Ry zYlqqlW3P7Bo60H~12ToSq{K)u8)NgEt&HLu$Vo{O*gc_-&nVH?F8`X^wj}K##=r!V z*X$fLWD@pWFg9`fE=HT7mBPS~KvTv-l# zB_plAk||8mE7R)RpzPjd)Q+_JG#;!e)#yvmFJae`G3a}`pY}T-bd2FB$p%n12PyQ3+`OZ2mpjy@A5p*i&WGqH&Kw`$HPYGo^z*g1&~n5l!ok zxHvk;dIRke^S;@5?2X*RS_pOrkg){0E$7vvN9v+V2xB|h!^RxX$`@APH8Q}Gh+HOnF9OXL0Bu(8$I#n^$I*^FT**~ zkV`ZM(Bqh3ec+ZS))?TqAgpUCEFttzn2Y#5?%X1@d1(b*D}0jmzHm(0$F(!^&HC%g zXb=2dp<&+ZLR0zM!kO~7=wEODYk5|(asH?BTs0oT7N2bANPc41RW$x#{Zcg^Vtgcd zN=xHm31o5_4|VmpaZU0@pZ25K@$eq{kzW1RB&#W|d_Ep}a{JH*{CKGQ#KPJ&cKq zOR#52d&*79p}#Ux(3qGYDO0dxViW8=AfN1*=>2g_+|}d|-T&#BxaQ-S$OvQNnrdTW zehH0zig@&oJc&pH6if9vdtWe0y z^L{CSjLWX z%c_rakU@n#LFks)IjH*h=8Ex6R>Y5Qr&zh-Z;fx42#F)v;ykxseeII^RYY*!0imNdqVGTlS4t5?0vAAr!@)mnNnIOoJO6KTmU^6?V%3ILS9Z|O#-AfNzi>bb zZuw8vBv{jw(V7Huv>D|~!{jQf)*({%IfM6_Vc@&Du7uVlh5BfBB=^^?whnQVzy0Gn zB+i6*O8hO1+xME~=jGE?>yWBzGxn7UJO`g)C-r4Mv+@AaC;ri##`1d^_#G$L{quDQ zo@=UFhpf57twa8d@Bd;Ql1O~VI;1i9z5sk*hWS%Qwk)*Hj1z%}RcjEuO1!#TbIH`i0A|9x;)#awqx~D+fSE(fiXi$*%c@|9nm2jqe+NVNJsElwXsqxkdFw zd1d=k^)-q9|Kgg2UAN`uP(C16(lZIHe5ERfj57q|3dvLSRZ8eHs7|$|rTG5T6;6(7 zAZN#ElF2oTvF7Q-?JsnOzK`THt(@IoFv8p^PeXhpr{R4s60I~_PxJPEwf%)n?6{`7 zpM`$wrl+}CjCePf(K8ybt*zQm(8_)ERFG9wLuf4cxSya!T9l?1eMMVd&ZSodS#K!D zH_98{_eJs@)-`(Id8H=0oJ~)Gv{d&q8O^YAl$p}w##aT>p>;OthiSYef{enxJ5Sg* z&_Z7Zox3rs=ly)|VAmkb{RMjLUIF6LsLL@|#W5N$@Kg%hF05&*%f*V)awG6Pj+JZc zL9WF*faU-dbYrY;4tq@G$IHmw zIae;v&Zq+SWCpPYXxrI{RbZGMLPu_%)X=T~96x3GU{`-3!^qvg1Z(OFmj!k74yP0RH`PT~#KHu-a*h>8*DGTlQ zG`n{}V?Ff)x`*2GpXT>%rbL1DjK)+dK^bakiZUgiq>DZvq)p{P`j@e0t7?azr_1&m zqzO3;&-FZq49%~1{z5-a`zXAQ+=T60q$8*2b*@X<=mvN7C1z|CLr!Ut`-9bSrG1TN3@pK8I(U zs`WWmU;bC?QdW>$P_!O#1s z%6~84SFt{kyRrG!$`2ynB{WWAT@D=w*5TClNteL(RXO!l^a-gGWbq;VJ_a}MK=)Eh z6;sL(KNOzq-UatO5A|1ekKg+lyY3R6cm8ZYi>-qMd0n9nu&)bVV~-*gx(Db!wJfhK zIbNSxioH?dbxYXQLT_$jS;gz>>weN@X%`c(Y5b%9ytsOQ{vwZ&M{eIC6}GDEzQY>m ztH9gq#M=Yac-Ukcx6c56+jDznDp?B$j_3IsRQ}tj|FC(~$`AZE@YRy%EBFDPYS}Rm z&rG3@(0oMmgrJ9`ag6qw*)~V}1Bqtrc)-dyVyO(zRCLh}?Z_xhazug+0_hlW9!Ii2 z=3m(2Ik9#I7`NlniZPG4z`x4&0DH*P57C}hZT!D^_ z(VW-}d5Yi9mJeZVpy@eEg?vF5&c>Mb?`RLYgdgA6RIuZ@KH4nu+L@jmM1IqXi;*tb zDqY~VC-Mw5 z>TLAc1r?f8Wp&X<5pMx|pGtZ~jd@3eJ$Tp_wmOpreH^P}!?WRg(+40(UR??IH&81-I3&*gSXWuNoc z(z}TQPa|Hsmj5;_2s%SkJO>8d9?40p{Eqh^(mMe#Khpl^2jUO;3-X+n)(@nson7>0 z9rH58Dd?CnP731_$x2moAl7l(lvvdLX1oic6nVxT&HZ$C94Fl!SLSkzCu;0lWI>OJ z{ST~@C@+*xvaw*t{xaw-U`K@gZLIt1A>XDngK(685T1i)6cwne#%8d+ zHH3{fo-OM_?|ms|(&Vsz)-{A|^$NDt=GZHOowh=O=R0)YYw-Lu*`s3Lh~{4C8PE=} z&ZKz&@7aKx_IkW4G-~YeWTM?CA-t6G2bs)3Cf1_;XeL1yH!OqApEd<~9J7zrec}C5 z6o;Cgqt)huuU?dY8LK1H&cIwqd-bgTOpG$7sx?=kBVzae^WPA1VVb<5Ye8{hJQIhu za1JsYzDxM*`I>U!UJ6?{Oj<$Vo;`0;rh=QoTPIC-I&~(C&3JwyIZLm{5*?>{Oru%&#=s{&wc(@aB-Q=s zzinxJGTKC@oEce<`_?Rd9q!Y+6fsiq=YDm*5cfnrhEMMv`G=5-m>9j!<8$~!sIUIu zQ+w7FJ_VA=cBar1Mj|J@Es4_jtkO!UbiGk&MPW)7z7$Psnl>pKlhf?C@Zw#hOyS)0 z3aRu%`dk;y^DMkCYA-Vv->#bLV&bsOL9?`o8E0BYx=>p9FslOJtuQHK?@N>4XQcA9 zr2BYZs+@_>EUPSx&#R#Cm(PGUXCq=z$xk!WixDTDhuW5`iMX#HpDAS$<%!bu^YbbS zAJJEVn*A8WG~03*`%?&30y06h1~??iH8Kh||2-- zY+gm3yWpnmqQi9?(G0o)Z%z7F0UZC|-AZWb=2wJZL1g#eXLF+|8(0T?4 z;%Z-;lE_@a7i*-VD|3C*wJ9wbF7~7u#c@e*Q{s-BHJaZer7-&B>y7kvuv0Bg;0u-s z&*F~dS&VFxu=TO8)3dnzJl&gheox0YBJH7LT?b_sG z8;j%VW}!vke6tb9(~B_zCTBghIK9KAnQ18_#kUa6&yF~2F@oN-pYRL5|H~|Lr1#NN zs51I*0g5Ae+z$oXpWFVt59GMRW5?qT#%%vS(GgH!q@HG6X#lsey4By z^~0A#d-dJjm%foK?k~l>;65w#n5gfS^liyH7%Q|%W{lort^|ql_4A7>V&2V&+n0PL zoq7z7M+>twT579O>4jqpkJA@BRTz^#c+{RVu{b?>+BB?U%8eZsJETS8=_XAXb97PK zT|Y*%G}1t0o-1>6$oc%rvPgYR!(556(_*L3?pcT{jdR6rPC1`n`5{tQQzut!+;?%` z&+gGi>JFCvDlIh1EmN4uVBdnhFbl{eLvfx58BJQQ*2a_?EqsV}9Dh8%%6$j(%XsK( zXq}HRGvaidF|J`ulu8q&8bvM>@Kz2YbHF?SyRyysKmQ0+O}l3N$2CxJsrW#veE4xT?`zD6R~(Lq}Anf34% z^5#slxGbh#=K8oiX4Q#i(~BAD$@SCa;JGj^{+dqjD(6OPu7tF<&@-|U^E8RNz3cmKperq zqA_>L-DYtZd8O%U(H3e^0ly{6?;NvE+}f(?66(LyFEx1jr5Q>$#WYba#g|j1nTal% zT4iEIay`a6CEmFlbK=3|^+s1JreBoG3(bovnlVzQPU_C&M7d5@d1WZdlDT znS3io?;3|T1G*_2iJk?V!J=@qKv&1#*@yvq2@ z;>!4}tjg(lDmtqYJ+w$6%>yc=<(13tDx}3Yr=H&?S(}urm*^Ca-np<4Z9fUKkF$)S zUcQg*qs^Fd%)O`6JL7GPA{T}3RXu5MjY$?W-DP?z&C4_+rzOcn@tHDa?rhECK=v+n zu7*z<-jx`C2KyneyFiaQ8vRiwUNV1qp;UgQf<_Lmm+C#6V*0^LqnFE6@2R3Bis@!Dorkr07IOLF6(mk zC2>vfzHYDj7(03-Qm%B)lvko3$m9Fq?F-9brGY2Unkn&0RfH_8XI}ZR!r}zAWRgU_ z-ZHBQty#DOZNAX_YDJ+$w}NCrW9F(X3%p`QLMuKnfRYN{`Wv3P%> zCs9X9?sv9~dq&LB5&72~H5{nnKn(|KI8eiZ8V=NOpoRlA9H`;I z{|yfOnEm1t8Q%XQ=iURn3HknYH5uP$!>3{YZp+Wu>$_kRqVbuO0@%P9VC=+Bjmr=I>?F0>*hwGrJpk<&| z^U)SS`#^0LFlsd@7BmcbUkBQ<68Ek`9IF}iCeTw*>KfElD#{Of0J2)ks3So8Ko>z* zL6g@ZzV&c#VAKhlP_E73D`*dB_7>!8E8503sMJK6=v;761Tv>$XHQ~)9yTQ%DK zGj%=uSAx(Bj5(;R1mZBqL0(F7{3j1Qea8@e;ZT0Tug0r}12r6|;Xn-sYB*5Cff^3f zaG-_*H5{nnKn(|KIPhQMfC!6Y`bl&Rj1{K!Et)j7Y}wk%n#tDji6iCFWgc^Q%+>L+ zf%jp&Pap$Cc!tNTJQe_-gBZL8$rz*r*?`m_3hxH=0Y!k~Knp;rpdUdQpd8QxkPgxz zsyaksu?`Lie@H(&@Ji#qJmmlI(ESe|TQWrI!^cGGGa$mn)!cNAi2UgK;%bzQ^MWjn zBxgkG9GnxK!nxq4bMhm1Hc%k)e{fr*w#*l)Z9s%8c_cSoBO*U?Gu5aI&Pxh8GQTHM zKfyWCWSk3bIwwDJKL83u{)|#MTG1gmKH^N{PY#W`^KgID3op zsDNm1&1l~+Wk6(Pc;r{g=KlIjaQEi^R)LWL;|Mjr5#CYJ0TIG^z=UWzjSUa+)`a^9 zut7t7gF3hLLY;00m+N? z7n}@ZYin<7XK!OiKF$GtN@ZuIt&MF5rlZQggKa(b?9{J7V<2$na2mW%DR- zi6woeSAV4@Fi063r5rfK)s=NS4sfss+ibc_uu_J_gxa$e_x*83ZJNcXn}V!B9YH-n zeaL+l=b(WgAJ9~gO{&Pp5i|lc8MG2~7<3c#9%QjrbdOJIKczQd# zI(YQqg0g-eoopE4ULi6{JJdHg3`sKqQ4uQJ(YEb~aW)-ozHZmawq1~~zn@J&M-|PJ zP9ARU+y@P?Zyu%3cmzZ!m9`v@d&LBY__MwY6B!jvjGLfr)jX=Tm0x&xH7B)w58v1T zf2CV*p1b75IEIf83kmo2S5k0gD0)nk(my!L*DoZ1?Js@9Vtqq`{n;zZ!0!zo$!wPu#fg6L;T%p6)|D z`VJb%MI+qb+ieKv!KYK*P4`#1d%2^b4I1Lf-%k0W>vS8NFFyUM@E$|loZP+HAe3#! z#kH?z?>-;HJ2?;WaN;AQ_DoIJyLX?yZr<)r9!{QY8}H}o;8NX><%zct6B~?S!*I7S z-!H$=vs+k9NJtNcvFTu|>e$JybC<8HpZof0`~w21&Ocsv=+)cN$(j5-f`h_*qp3CZ z9vz?=t914aW?LQgi^wQn?}(@<>KcsD27^O=gV6Fq!Zl;9lp5c#meI=CfXLv$iPq>7 zeH_}^cCu4O1&2n21Sm)QMvX?*her5D21kX5DFfN45zg5+Dq1<-cWl5%FJ@pkZWFS? zMz2Il!5XFC#At*Ij|uZv`bJj^gO(kQuF#6R#CEwb^d35CZLRFfW|KU;Y}uOv{Cl$P z8|g$x#$dAY{}>m#Gvmefu<9LaY`{dWoKf~DzY+t0vIEGL zLmWfAdI<<) z2On#tJL~pWRxyL^@DVYQ5#dn*N+(YbZ>~}IclyTLZHT+uAT)3fr`|){o!9}^+p({U zlZPia?PG#hbK(m%y#LT)VxeSAluG9N%iMdD769ozK>u!b=$%Uf(H^BHJS;Fc2!mv` zfgSVDP&d|XJAo>kMqx}7=r`1TFvQ1l^D6Z<8vg?#*{;So29rp_4eyZw=$xoz%AYW{ zjt-!(_G}BYMJxMA`d{j&=!0k+nDYIVtwMb#05KH^{h8zfWw5`s(rH2j5=Cpm^c#r; zfY!=hn2@-fvGqPaG8{ub-NJUJ>b>QQ4GVex(=bsn8cjfeKh1EOP=94eKo~1>QEEI3 zt>8zeEboN;eqsEfSrelQ=H7rHYSz^8x=d)tfifI93-OKM`XjuXM+oBP429Op-XA+HMPoZb8O8N(&PDx@AM5@wzS-+DAMb|Dz_XR=&%rM|G8&U6CF&4O zf+o3?(cxTG`-V*%?>o`jnk`EJy7NT7C=|YVl)VzbP-Y0tcfROp0kQq*cVs+V2MzTG4uTBj;pxtzBOxDdP~SnEKal(x z<}2e~N{vl|dZSyWPjQ6q^wtaetsVRG_s4hqdhyP)7ai&vi=%Aao9=aA+^ak?*Y9hs zdHi>2!`C1AZRN?zSGNoOEPHoUN<=0_{#nr*91}gqZ0x_cRifUKr}rtu%*8QZ#Z_^4#z4}?apzf=tmu)-sGI1a8=N0*A?=Ks-ESZ%URyydu)s@<(?{++C znQAg!5*Y2`Z|Ny@ys`Oh`ts!cOTCMymN&}kmiJqWmv#$fyG(}$#>Uoj?&#%uE%dD6 zoAwXSEPps__JQqN9ft+Y>q?u;($TTS_8#EqVh8^3!q=jw_>+kZF|)6a8w z=P{;}Ug&2xNNcmm-ui>l?;*DaT-bJG&W;DG&dzNySsvm)!pU`Aw|J`pi{l1Op7p34 zd1-R~ik}W1yEgyz8nZCFsY3=vkJ4K2?(wVP^TrG_t4`f!D{L*DcMP=)I2PUK`{S#I z|Mc6@kaPEMOnq4Xdb+W$NULhlbfcG*OL|NX|FbLAb8j4T-}(D>|6eNK#6A#zHOIzS zyj;;D=%?6@jz@;{+i~*nuzA0(342`pcJi6hYw;cQl?&^d>uerx9k|!Co6|2xdi{89 zwcGq>?*bovxEg&{(rd1VsqdNyrDSV8+m?syTrZx^AN70Q`_VJ+ET6Rf)xkt}gWgNW zHTGF+(n^}v*}lbv+m4s=KX^TPxXfqPyF-!NWSaSrChAp#n>OFx(MEQ_Y~Zu3iV^3p z+#0jBaQ}qaFIFT+8Tu`8vv647sg32&rd{NhDxII+y6Ji0@d3XrZ+?iFqnj{&NrTPW zeO4zn{?_A8`g67J+4}BnZ`k_}{M|b?v~u#S#Z2Og^tzjNT(&%U?1f#yaq~WUzjYnn z=KiRVLFH4XhUjmM-(#M%aH)0S=9k?v_Ws(d^)FrA^shAx41YE?+V#W8IeWz$mZume z|MaTG-6Po@kDvUyU#njm469WlK_o z!N=fXqsaE}dd$t0WUVPRy|;CNa{8e(+jXahyY|nUIBN7Ai_x`T^_*mFSe#sDacaqx zHfz`K>N4YJt@GGRlRW#}`o^!_<8Bd#Z<@?6mldtbF*&{c=ccI#7TLsSeK&B-m0=_L z7Iq(F^`h|vBN|828y%N~b)BJitwrzJH)AD=v13o0?H-WSKnLZEsUO@ZJL`q zyS?u({oDGlFzEDK(uEHCsq?xWIWnkA#Em+xS(({=8W(7twtjGT_;E))?}oc_zCDq$ z)GKC=m-`vJ`eUZGy&ATu_6kiMP8dSkGwf$(syejE(DH>F4)&>+0gBGSI(Qe zcH!3xe3o>}XgO!jt)ltv?>5f3U*w-O?Ax|SpE*A|Xy>yvefpHqX$kGx?@-x1-TKIM z$A*!$LQ)rm+UB&3c$Hn@wd+>j{^PE>HnhunCo4bMRJrHklI}6*TE*GFT(jz3ne(Cj z?_O-0SXolm<4*6#mG^(RaQH#H>?u#iM+_5pjfMvL-1N}ctQe5fZg}6?wdy+_ zG`*@`nz`{uY>_X-_7`Klv ztNk?j)yS>O9o3^(tqN?rpv`xW78f_#Q{cwL+?&k* zveD1>9cq~;+En!0)wqqf!&muVA9JDEsax51GbCkeFQh&8IXiW3k0WOnR30$icX-d{ z?NfHGduPA1UeUX4=QH+i{_fVq^_f0)E5=PJU$f=gJ&T$+$D}kcwVk=6)~oNM+wGcu z(q>%Z@&&U;TF>qOP5E|RPxZdDZcat>2EKeZs9)P#1}-ZzF7*Ct%8c()e0onC&$67>6I*OOeX;9kynwy!`Bdi7 znT>8ca_bHVx%|u6_W6@zpWZnB%i6-&T%Y2fo;Q1B{`=jhjgD-5zAe?iBr2)pn^P-_ zKInbeKkI10#JNG4_Ho%a-X&a_bNC0plqstZ?dqX5*ipIkXX9Nz$!d?=p5NAX(`dU_ z>p}zf9KQZt%zmAbc6;}z%YUZ+pJF2)Z{=(F^x$B<<@Ha6%IBAiiRiRZ^KktV|JAlL zZy0Xae{*8vhgS+_Uc0=st?NF$Ba?rgDsQ*HcwwVs3;d1K8@*KS8q;UofmgR3jwVdW zx!&OMy<4G!_vVyjCH@xgwJb!Dv1P3Pq&I#ao}3MsJ!pi;w+wzRhH+%w9s zuA_{DUGF*gT!|bPwC>k?I^A4yB>g`m*1kM;ul~ljTlRJeS+=`Z?%6{()Nc;|SQv8E zHfBV=)1}(EH^1rr>-HaQuC=gdZV!$doOj05H~ZM$l09EFJC)|Oe96H}MjMapU%g-4 zN_VEzd-pYiOv{J0eomeo-oB3O=waI%`5y1yE^yxhhnumoaW_PVm6w;bF~0I_R^rd& zn(W;t+j#HT8dc8z2kXwtCv<$n7|q+Fmtwxm@Xn#yW2Uw19;&-E#DAe^gr=xu@Yu0_ zz9AM@Z2}SpGJY?AUm^?nZlkE-@euX3&o8{XW;D+DRPmH_}mgyXtQ{JGu6)ZsVkG+Z@C#jg4y^O;Q@1ZN7K((6q#G zrCv_pfi?GhFB-nNJ!;w6Ypt6u%igtTOJ0^)_q1=O*WP2@b;ObM9U%uZl=1t2-aikt)(eU=<2_?$C%LCTZWIBRO^!Ay;YTZ z+Lk*R{hwFMr#Nbjo?l+Cn>_lZsBy&!S@6iAe&xRe1;mZB3#nf$8ygneFsGuR?QgS& zPr7b=zTd5&@caXB-aI=xulLb(vn%s<`8-&kn>$te>)KN%u6A*MnLp@7(4k+0h92H@ zOSZRXf4kj%uD7jy)wQAiPi6gd?0hCk98Ny-$sdv*wB^~nunrTC20MSB=KD*7_`t)d zm&2Re-5u?|WW2$79hX{%4w#CYwr?RFaV?Y#Z%t`q(%TD;UeS-E~pjJ`Hhyj7;RvZtNly-sFPm(dpl|I8b(H z{I2lvF6rh)!*ypyj4`S_*HsocqL!#m!8`q4|5iEH*XdG->4dxbsZTH0&hw0y z3_Ovh^R;h_pv~o`KG_3Yg8SYWAJ(Jam|u6^9G-hEuvWhMdDp9*J$4@6dV2Mt+tV)X zc6nI2*T&-Ikt4HD96V>EP4n2aevhTpF8iQXmUp4`(A%EJg03~Qo)nn2zn||Zal_Fg z7q<;>)A?wvJ!|I~oNSmc9X|J&xE&)m)U#+!4201%; zdJG>~Q2g}a`*$x(ujc3edg|o43k#O6UjF@@8Hrnd+O&30+QB1P8D}rvxOwGrfyiz=U($nPc(_VOM! zpkHst`i;$urQ%u!U$to8s=K|aVcM8be@&0CZ8|q?Zq-&M(lu(( z$V9PoYwG6Rdk-HvL_p{h-@Fc6ZL(*wG<- zoyzlcdJB&eyS^I!%YjxS&mV1HFivMtajay?(`mI=KAfPx;(ch7dGE%U&w8n;6IbeQ zntZiy*KPR&yY0wz>9pZjwe9*-Lt5@T>8||w+_$awUl?J1Y=J21?owIw{nbWOo-Eg$ z^!WQm;T3ZljD9mi;rl$%B(QwT*Zr^m)Wh}Grp`_|Yi)Y{wx{{f%(SL%#}Bss=FAbR zQI~pkgFQOPvpaPDJzyu_A9m`%Eg*}YockQmUyVH+2hL4l?(*kiC)kUFwt&c=sID`I zmw|O%un*J+&lL29Ej&mFBjBlioZoER_qG?K&PG0r;r9q>x`GNornnZ#$1U9VC7gh; zr$7m~pXN2%SE0QgeDaAQLAMErlta@%l|%?oi2#)dP>BGQ2vCUtl?Wi%qtpCGa}>=p zG*{4gPh&QXyEJyv_(x+HjYBk+(0D+7n))TBPy0fY2W-*d9qn9R@U0}KHmDA$KIkhD z)RBw>$QLvnbR0w*L(@SbL?S{YB19sRfv}$_G5}$7P-G5Lf}qnBsX;!>pB{*cI&)&@&IW-QJ{FxdeBKwA&B3e!x{EX>(pg*<$5xGX)TF?PHnNF zh+XQi*Z%CEz#jnxJ_)FU8>fzAmk6ND{2LIxy{SOa@ zsjDzCsaMYwhZzof=7Ns;{L$dEqv2w{lvex4Zq5G1zmMhw z|FyHv%v1iiohY|hq$84uq#~I}F47h0;ir#ZE&L4dtIhumMcmIw#Qls#+^>%4(_dZD zr$2@0)1Qgx(_cN&U;j)+fBiEP{q@gW^w+=oqJQ>lAo^#&hN6G=vk?80Un3d@*tRb; z`OlmBziQS0w88$RG1mXW#eZn-^?&|$Oz5zclS+xzR2ad0jphV8gn2>0&!&f3|6+PD z_*c_|;Xgc#{^7wJf&Isz&VTq2>)?Ai^etPRT8z0|r1q>v+11X;-%bD1>tAw{-(L~M zGeS?KzNyQF+X6S+2Bk8&uAY7^gW85hke3uD^-Rso>o;g<(Wr3~IRfn?55xAu%a==B(LszMng9{(^;zw2POdEM2zz zhZQSVtzMJ5cHR078#isW&e8lx11}vc~`Gpzj5={?fil}cMI>`FDicU@X_NZzdwEU{Kd;xC8cHM zuiw0V_x?jg<^Su4AcNK5|DzmG`dM9So!XpHTGk(2Cr8)MYC-pkuRC<~v&wHOHSb|? zsddHIsdlY9TxxwynQA(#R%-JO9b0$kVU^l^L8Fl-zWU5(_gmJ_Z+cC+ppj+$(l(Q{xu zk=hE>2c!md0W}5LH-#U_3-tagk-9O^7&IC*0h9o;2HnK9MZnddNzFv+nV@B$Euh1o z%b?JxAn%CCa1B{Ei+W`o!}zdn{KI-TWURM;WGrueVl}S1!@s&i6J=A~Ir@`}<0GnFqvbnuqAzT` zL5BTA>Ve;i)Q+GoAS;k5NDP7%jCWuNtiND2930^t6c7drF%2-p21N*u`RtQ=`>Op30j1A?pX_a*m%M~jnjO#cCDSbo8AZQ{?%)q#a z0RN`A2X?vwx4QT%mC?bWU|<*j7LQ>iA+9kQoz;k<8>rXY86x%6c#%2+bRFmO zfIon!T||Yz*w$OHPUU!Nr3{P-(~$WaXHVlB1p`&q8m?*csHVI@qP;Q@R**{au~LQv zhfzyt9z|xq|Ko?uJOg?}?)Y5d5EAdu>hhkS&yF>*dwqMk5SCE5Ue~yC#s~e%5@zPw z-j9{XCYLR+*=4w8u6dn46C1A`|0e3n1cxZU(AI^$oeH)!q`9e(Z7%j(X{U(Lpr4nEd-w0hq!7e{p% zJ5+VCt?6o`$^9M|&s#CALB-u(g@gM0TyEK;+r_SByFAYCk~IoAoU|-<$dSis#ajDq zS36}6e~Ek!2^$**3u&f#yDqSx;%&l|Xus9mRIM&Ckuk~v0sg_!oNc5NJ?dbu>H$erUd!PrPC!pt`63}bVdk}-PB_Lgp0p$Z^0x}0#fRrFh zP%DrXs3WKw$Pwh$n_=7?pqq6A??IkK7>qoj)b=DBTbz5~+yUr72tNlXbsai_I)U({ zgF|P8p|J4xfWHU)J>c&_{#`(@gZAiP1M0wdB8(@(cp{7^!VK{6bnqPF!3^l_0HbWU zJ-r-U!E4xzyE=I}(J5>sqhM3Z4i-up`(Y!i424~O2y1rx*>zYm;&PyGOb9!#^$iIL z2=Wbqd2m%6OfL+EV{};?WP~kalE;O6B|Vb&sm+?y%vH#N!Ho9(F)g*y_Au=T4pzY;p8;X6PC|3z2b=hl#T2~8K%7-J#Z1#KG;97y(Tg| z3bvWyA?*gbw6|t2w1>I5CRSzJ4$pJ63kV5p9~G%-9~Lk^B-l>?oNC%fMf;OiB<4GA zZuq!f{quz=@q%IEu;U{f&*?l4f75s$oYV0f?zl?soOM?k^A4R!?u=-%NYt>ln0;0Y z+cAv#tPv9@;R5_sxMdfNm|=e-+?ijEn2vuVT+S6E#`tf9>$1s^$@m-LbPYd^NU0j1DbPR960CM2&DNjf5Z; zY#U+Y9ZLT+_{Zpq^vQ~YVJtypCm~okz#v2&2Ui@hx?P3^{KO1t9XJ65@{xK07X|$A zObbZN^ud4b`fR)p)C8{8JnjbK@kr)5kYtnBJTgZaH9gxW99B3HGrM4x!o_2c>viGh z3LJ<N4}H-KL*km7&DV+GIlmZGr9aX0QQ1=1Q5$FW*(4uaTiGW ztN;!Jdf~Zn;_m|BXy9ug3dJ-&!||sd&>3khz_a2M?i>(HGn{Z}2c-K}1F76wfT$d1 z504o@D)A}aoeiY)p8(qcO@HC8HwMyuZGf$S?!0>xk7Ix&b58;i-xl+@6G-I~4vJgM z=#3EgQh@8jC}aG=wFg72t+;yVlFQ}07tkGH76UDT`+=0+86ee1F3=u)Fun@AHMm;< ztEbD?FZ7yRyu)yv>NSK9KLbeiS2KYW;(Hz!@VFRA=?KSSoQRoP6NLEI;X2iC29U~l zlXt%bQhh0}F={o?2T0+j0;yh#fK>eFKx)6r>s@!df8kh(6EU;mv=G1fLvGyi0#dk1K&p>a zU^n1RAhl=7BQ78IKq^xpkivb><8Gie+yy`{pxtAxj2$ zIo<;dw{UdCiI{nfHM4~EdVuTHZp(nwFAQFD!-9X|&5swWdcn=TU!oig%sfQ4s z;BSc&F=NqF@VD|s|3W^!{5XCI;i%1snc@9~aPD515A`r#d2{9a9(V>}JbmzvX5ek$ zK;dTKc@W;Z@{Mr6PYb-q2JObGH8;Pl1_q-1lJ>B{Mc8}5qj0b51lwO!O@ck%{|x^w zUAcY{2gL2n4B$Fr$OEoucW|!*Qd_G4;xE;&l35k>#caS;?V|3 z?WPCs?ghl{Og|oR${rj)t}YhJ(+~W%z?DGYI-sspq&^3{3|xSO{9rS2ubQ^p64%6x zcC&E5b6pWT&$t6=JQ9w{I1w{5w+P`z;CdkZP5={t&I%FRkHdh}KTiQyqkMkYn|ukk zr>RIC4Lk#+esCK|d2e8by*Hpca18J;kox^yAdLgUaTq6JX7f8CeM56DTt{F5u9?&q zvGPe0@E+V_8gT7#Cy@H>O(3OX(on>NYm<@~rx><1Tc^x0 z1I3L*>JVTU&<5pO-Iy!Kb>LO_?{0$h;9sB=sbv^{goElt%=p-d`Tkwh4DnLK;Sb8Q znEA#O2m%eEr3d-@7$Wp*9;)_{~REV zH{IIc-Bv(PU@PEcAeDb6kjA|eKw{R zfwPhBFl#O!V}R5SGJw_F5%E&YlnfKfc@Ed9Z8^8+!npzK!tDp7d{0y+ZQ*l^`>2U@{B6-edT&*MvAAGqy1h}8Xn2|z06K_KPt6z_fuq;d<#9+XMU zm~9f$wYBB))elJH+9V*wdjhxt7^p&h;GRt#Me0pJS38kB6(lj1p0)IOo&1cRIB6S$tdw?`YW1paqcHR|1gI$pKP5Fpk_f5eTI6PUhWrdG~AJ1Nav>ao5X$)Q;j@ICl#09IpHH z;oPx6>Pw4&mcV^L;(rD36i_(M;{@&HicoK~=idf?wC~>(NPGX(pRIs1fIET2Z{7ab z7X%susr~c=Qu*9~)c#KZ#{jKdVMhTx3cQW{t{lkKO9_zp)@u+~Z}WhwDZCrn1Mo5s zlQvT@7<>ZScyRR}2vp*F63_=&1oQ$5M>m{^nbGZZ`0=BgCzt=>K+3NlP#+iqGyqNj zQo9lkstYmW+*P=LC$1A8vVp`u^C4V(LiiFke1pM4cspEI!!H&{@y`G{0yBZVfVy7X zxMTpN_UR970h|pS4SWeC{`n8(Fc%mCcdub0^^d@(K;m-=kmcVuJpX{P@Rtnd(lrKB z|Lg-K{$B^u{Yl?quN~+(f(z#cRKgtrB)&}I{gZ%(a4!a~1lo-Jbey3!EoR0}5X#*L z*Nx#f3`phn2fCu(c8%iVhZlQ9<3HrynZkY9xIPblqr5pjtpnDDdk>K6@;RXx?ZS_1 z-(|oY_@C48*_y`^+@tDBlJRr5ZQ^484fum9X;Mcxj zE+1!r)+l$`SnwaXC=7NJ2sbL68z*qe9-jCwX6l_2%0;#o)IQDu+W^V#g33d-7ldSg zVFgqJsb7x*QoBqAQh9{~f;8eCdP9hp>@=)#k!&)kJ&~;j-A}d~t$<{|K}fb6HbAo9 zp!mq1gZQcjQr++2-I+jYUpYW(F9pCb;J_%3Z^M9eJrKAJXdKPC8v~odtp=)raX^ZH z5ik-ciQzC7I1uhrKq_|*&<$uA%e6;GAjK013wm}97um$n z{m#H1zyu)iSvY>giI}O>m+<4;I$S3{?c(t$P#5k@9xnoI>E_8?d7A<$KV5({FN^>> z1J?nmJePr#uJIJ^dPkr&+Hy_}XJv!pQnAwkQM+xf= z#Ptn0)1Stb(*n3a47qJO?D5d%gu?U9y zD|j?W;QSl#*osFx9vyjf=h25pM8zJKY=00<7SapDbt+LLA1;o^c|5MSvUHP#q|;d%0t5(q5)cA{Mr3tG zKnS}lAfV%dfQX8S3JSPIK|n;uZCp_iP|-ohT~u^%29;4<#&I96*U|6yJEu-}$1wMs zx&Qm!@A*Fu{XAXu?&m#AojP^uJ*TSNb8q)N*gYTTo}1kBO!qwBJuh?5H@fFd?)hPy zhr<7#UEH}`wT~|Dc@)mgE;eg zE4o5m7xg%^ZOnA>YjEZ`Vi(R0IQy5X{*m!V4+Cd>&-18*Ez8t>?JJx|fZqQqv_sIx zFGqdg+;la@`>d;LmH*W^^ZM-Vo*QsxyPbeD+sizhdqe*26&M#~JckSe&tq)gsq-;& zmAbwcj`(M=xu6pt8NK2&(65EvK$8?<-pFnl;MqJvi@%y+t>w`{YkJFVjjmtLy6p$Ln5~ zm*0e#x>o$ZgfzeD=9c#drN6gG^UnvL;|={&{A7F0f8db(nLRZBz#;jM4bc4AlhyoJ zOZ%@MtNAw`lK=V1n!f{lUa$J6{5yGy=I;cbH2qWj?`LZMzC+qybD`!ZZc+D-mik9u zuKA7NpP-pIEBgmmYJT$}_3ye>^LHLnf9zeFU(npLe^mDEM>M}5_!JL==4H)a0)C@b##!lidsp*c0)I>^{@?d&e&uayoTf$c0eFnbUu(XmE4v$h()1P3 z~e~KZ;2%B!XUt$TE<=PJz~b1v4)x6=Ro2F>3)AA1A0@^8!r z&5vBH=H<1BO8>e0G=JV9`E#Gp{5{|=(aNd(Z+l+z$1iC4K26zQ{D$UZ@8O0;t@5{f zzvj=s1MRjI|2Kcv{M~oqKGlkUeRh`H{`~jhKG2FEEY|#0@NY*e{vuR~A}$A?<2C(L z{+HEie!+uSi_oh4w;iGR-#w0bJr4NYpVI$ku;%aHAsUuzCeDg~;nAAk^t74>)FO&+ z4AuO>&m4+>`7q6|dKTl_jCpW3{o^(N;I2d6Hx8Vr`H>gkf2;gmHcs=udhJlxe`tc{ z_j~-c-+(T14e<^$g8l2mWr&OxeHV zbj_c)8~rM8@a|9P-+Y$lH@}VYZPhO?o~8MV_Tc%qRr`5!j^=OO3x3A9McKdRJk3A& z=a&7h;{R~I=1<+H##b%<8+(!F7kqFi{Z-l7oy>TR{YV|Ykt4K9;$uzT&?+A!C%@c{i|=#{K0?2{ihZGt(!Fe z#;@?))GGbO&6>aJYkX6pmHyPVnqT$pq3UN@ia!ke*5%vb9<9F>{D)hmKQhHXDXiYt zY7td_w>_fu2j{8x^)2}ew`=~WL-Lzm(EQoosrinU`Ul?7{3fJdrI|RZ^shjdsv2E= zCEowFx;`KOO!FU%8S*(vn^5{S-)sJPNdFbhOxZsm{I31M->c_bEu!={do=%~L-J2E zHUBj5GrD)z|0+xKXM)e?2>ny`52X0Z!Oz!BoZa-jT7TW4)AwoqgWz)>NB@+5RhH(z z2tMZp^iT0~u+B@B?^lPk|9Xn=`QcFIvoc%j=Y!um{m}u<|0!3!Uu>EFlzh!!ddT+o zV2S2mcgXfJy1nMdEAU*<>iSvGTl1^oUqUC2v&#Q)+|yP5hk?)eK>btvFOSju>EJhN zCeDh#`FPF05Bx`4@qJS@f9l`WbG#N&`UmG|{(azAYG%s*P4hMX4e&R&;%`s!e?t4e zuT}qk+bXSpcM-;~t@wF&Ykq&|&ueA>;YT(936%e!R{90M*Zd0)9_qQ}$=5ai=Kna< z_`LfcHUGoVq0%3d;(rPK!L9teey`T={v-O&R{ZTBYyR`#CtC5VzS8`U!Easv8~#J{ zjsL{;+p2xNkmARGQu9nY301#?%xt%Pm4iQ7GjUe@7lN9<1pM+={6TFre-rqeZ`41f z|6)S(w}9VUGjUe@mpW?xm*Ah!ihpBI%^&m+HJ_+OlzzAVn!gDA(=;<>|Ds0CKLCE0 zR{WnwYkutKmhXR*{S%MZ{IkGst-oiy=HCoH=VtUz=?|H%`Okyj`uh3PEY1H6{MPk* z#RZyg{i5cnTH3$hQq4aO{MP;3f#sTi2KaLR)-|B~yKIf-H-qoj#&K5s;5yCU2!8AO zzx*!Ee;)kS_3L>^^M3-rsg?bnPig*m+@F`UYQJ+{)%<<=h&yb>Z}>p-#~YqQl>f7z zY5r31Ti?HK`cCtk!Eb$kJmq`MUk^UZME_Lz6#k(3+YHYk>hIkYe;E3YHCh>GrQcr! z-0QDrnbEMf6~9eL^CRVmPszwX^Wrh46luOzRd)T@tzX?Y_81;H-`bMDth?r)6i2*T z#<+!J0EKcEH2p)!kAbCehFHW_;4yfuTjENHMhv52oozH64az3`mDE%Re1ms%OZ){# zXC*r4Z4gfY;qN%)z+-v2u+6lx_98LU?;QjIGh%Ic7HWTif@hj&!>h^^zK4(>Q}}m6w@>kXW|`yYY1E}=8P@m`N-OlzKkD^TIq z^=*=%`z-4Y^K}4O@4$?8r!$c7xr8_8k#6`;#Nh+{v!z2uz;CV3_QJd^!u!^3j^%v|Ja0^T=zSliedUFnU?6C9!!d*@Lc@#q&4#z4Z7B%h z-hd0dJ^jr<>?K&1||72b zX$+KzV>cqV-a!(H*j^$>N+jRTqu5}H6xi>OGejcA_EF>XwS(Lkj4jmt04h)g|0BGKmB!))o&jEEANHSlgMtC&RTkaj}XV{r4 z$8ouY4ZDhF#`~B_%PwJRr)Iwaj^7?nWJ2OoAWKnRH0S>i2mW2VLF)jJyr9MM3V(n^ z{N4-wZJ=mRI}X|xU?WVynvYuhYs8~!|8r}^O2}LGOo^E(I=KKv#MC_lCb?+Tgr@(&WY9M#! zeh1HrjeKS=`U*1qmG=VSCovZL83GpzDQ?8tgXCQ->|vNiv0{A`mQTzdJDn*m7I9)u ztb)b1MEF^5k=PAP^Ky}msYW9|HkEoymCb@!A4)D$SaIz8Pk~(}Vh`g+lV~&XY~=fD zk^2O&%2;PgUMm8B09F<24`;nAm0ophKCx8_tBHMyoO)NQ^m@k5p=URUJPhQF+Sq7f zH;TwR!1~2rq~1+RvLV)+yk=n^0B>-Njl#Q5e-H}}WrfDJ!kKXfCI7fa4Y>Xr5>L|!Us22y2T%rbs8 zxC2PFJ>dx;uVudnq$V=)+{uRbO_@$lAgGw#(&v6a&?4WGi8k01na-XZ&Jzx{dAsz! zoAVV;M@J@}1p|AffkyjXJZO0TEOkcNlkNtxFK`vw$_e%?dhm(E7iD8?50Otp>_f-f z|6oaeCi{V@M!^P1vpp5Eofa}*g%VAIj$)n!7VZU4fSFG?XtAuN*2VEVp(J)LQJ zXtvYW5N;CcMiU!O-zI6_mLM12$%^NXT}4l)hkuf_Eddx$BY zp)L<}H^j~qvcj#{YO0^5Fei2%O`ol>{21Pv7~Yx6NOA0a>djJ4RK~LC(rhJJ73;_r zd5*$rVm}a@qp;c-?`__>3TucxO>CaR8Vx_2&HeCEmO_>hDu8OxA|+_Cbc)y!$yx_t zha?{da?qmHBK9G=oqQ>o@5|#45NR7{&R!Me?A+USA@Z7wG%;VVyU1tER&TR_P25`v z*{quUb5J+l*l;wjk`g)0u&iA>(boOe=4a8fJO@!LyLSXn4TgOsjAi$6F679}DB`KG z3*n$ewwJQmwdM(c^B3VzJd1?-Hn#!}T6iunO0q1bk$psH8?g9wC;=mW3Z#VL{Rf=O zZZJ21;m11~<2?YfsM;I(F9I&Ulmg3(NG}}#9c3$!@CER;I)1jaH4R5$l&*ok%TD_E zMZtK5WY0vNJw{>!Qyl2i3#&x)T8NZwq3*y0VgAax9#6b8y8=30UbGGI-VXLyhCqcF z>p4GBA;y{Cim?@9yl5~gxekkb@IW00rq`)iXErG|O5hGCCfj`qd!nDi0?;eGMDx#J zwa3@X!0AK>rbq|6QnEj@cP;Qr`g;-J?<7nc~WBA88lY zEHXyBeWcw_XqRqiyEVVITeT6zF4{`FVk69Tc=Goobod+@=qO!o+m|kPkY?MCpu3$e zVF{OnSZKS&F73Ul*DfXo{A4YXB>XcK(jdfoN@R$ z^PC|cAn+m}^#H-A3jF{Ho=yAaKHgW2&LN$tcU6=OSAN$gmOjWaqi4ZSUfXbxlGUOg40JrM3p z-Xc6v72&!>())o*W(N%HjV=?wq5OY>3@^QA?MCb*m|WnJC8?1lqwA|EbN;iR^%@`H zqc4{62Rt&l&jweZNcn7VK8*6W2-}Suel|G#Y=HK1_}Sp_v%%qKgTv1Tho21&KN}o= zHpu7L@n3imF%M$;MZ`kDcoD&qei1>oei3mB;QY&Q&@Up^0}fg%aZJC6cox_pUqoyM zLq13R8GwEff#9Ija|G$7uW`tHszWP!e>6;4W4M~Q5cGD0j=_MkjIV6Osoj~$OM#aM z0Eo$QpngB_iuq3)4S&Sou~NP~7+cAg2gWmIQ>7U1#r%HvN_tN1B;pqhae}WA3XI4R z&85Rh87Y0xd$x(@UKqG0&Ii2a4kU)Rdqx6}5F<|@RtK!?1!<#+DNG}G z&SbF9CwnE?`y~64zQCU%F0(W8CW`+FcsqJ?5KOr5b(~%FTfQ2B`+Pl7DNe;{e5IIx z)2WqWB2E)3#Uz}X=uSQCxDP0$^-OB0%uNBTVlEwdq;2MAXji%v!1$WE89InqZ(_*J z&=ZMG2BvZ|bQ0aWhFs=m=mlgyLALaM=;dU847?pnE#-aWU-iC8bW>TFhzA%%ts0_R z9@~N5Ur#g_qe9EJOOAY0%EhRUx#%{Gt{g)Qx#%{L*tx`zi*9p>-2+VJqT2$x`4PFy zMYlC%7vV8S)k(Lttdr5iWv;qCMscihaGO}IY+{cBuQGP1CiWB_YuL=LSmdZ$LiLRI z-~pw|aV7qglJG;qb1B4?K!Gdpvl8%J0nRwjV$H9pbot7>Mdk&XX_Wq!B@vf3y9t7P z@Dt6Cp^R82@fv3A1vttwi62QU1O=6?_(*1J2yk`fRLX22)Yqum>!!KNy?QRt*}_FM z9=;nDpQXL>UtnBnlvga0t|`AEVI(KgwV3a6NG7CP$%CW>d}BeWmXr?q6%a1zeI7pM zRYAmk%&UfXe9YScQT~Qi;4#mQAj=2O>{L(-vPVUec~mr+M@5t2agfnurW;MxL^%~r z=278k9={AK!*|sfx(41}+%7ySX3dPjx>b-zA5Ff}wQBNDkQU@?T#tH+R#b4H&OUdGgCR!EB3cldo~TwI-K_1oq-!^EIxwzRiCC&bAKV=E0;5nxQ2&DXZx?`3~3@i7bP-9VeWV!<0R0ZX%Rr(O%Ys z&`S^w%SoBAoRkU6Ntv*mlnKj8nXsIc3Cl^Du$+_$%SoAtnv{vCNtuY6l!>TGnTVQ{ ziKt1Lh&w5hgMeH^6vUV@ui1oW`rN+)6vYv*`4c8&a%PYpmyUYPW>E6ZBc&!l*B?aJ zfd+wwoL@_7C*S52g#m5R(zGi~NnLsTeiYyst|jXHr$Y(3Dz-5Io^w}2oDfO5@Ru3b>dXxx=Cif@KM+9*Sd49AVN zdKDMHgYmz zEuG9*OD8kd(#edq%u%tH+o7J11SjI0&8^E`#b0I!>75Lh7;AYPs?f=dwRAFLEgeqh z=~zoAGuG0{jJ0&U>=WErOD8kd(#edqbXvq(=B8pTZ=er+gN|5B!iM9t0FOU~S;V=alL zV=amOvslaX(Q*B2v6hUBOvhR>E;1c!$tb3OE!L9hrDH8Qwn@iYG7>T!Ye~s;tfdzn zRyx*_4Iv$C$$C!5T6RQk)3KJ!dpg!K2UgOtmQ3Lbw37!}3p&sfn|{pvQ|+1VTiLVG7=$4#n6SU?UbP^izqDvZH~3& z?SOfgy#aPp=5<}7arEsv*0K$9kdC#S0*O?tC6Rv?Ybmcgq{TKEvS>IRYstZSD%O%n zI@Xd{I@WR#Sm{{H+kr)lY!aV`nCo~t)-s5TCKYQbZ#4fT){?w*tR>YP_(*Cx)^aP2 z=~zqFT{_m16`qc@l(*1StR=DZJ5U<=XR(%)OvhRhOUGIgOUGIgOUGIgYc#UigkFMq zSqfQ3n6Z{2io?Ch>o>n8gh`HRggCw$yvw3pd6_q`0^SMOgH#a4vJLprB{vGBOHk{_>uvX4o8j% zzT~t7T;!<`OTp+I*>cp5;LF8;t^07$a~^*H9I~FkG5cXy!0IJcDD4gFb&9!Bm86&K zv;rNn%P^dEdSa{>=oz9isU3puRtLBQiwyC37D z|Dcs4%x@rPkx`mukrfyaS_CXH1P3E=DuhI0D~_H-mV=xmW`Yjwf8Z1tVjhoE$xRJNz#>IA^Y&5mk`Rk$k(F0VFBVH|iG_X9LH&dR zbY-Gpeh55psks~^i*)VeWuZJMCboiYBo2Tf4D%G~Ej16~RIWl$X~a(W`cqVfpe9rZ zYPkwQmF%RCc}&O<)PxE_brW$Cp(SLkgFz!P0-#9j#nF>^6-U!BqhL5mllqZ+0q=3z zN4@~!@DahO3J^A&2T1845#caA)9EPfTF$L#K~AU8w-E3U0j} z0ojG#R=ymTWka^EQTBS2koZDXb`=_jdjn{si^;DXRIoLP8W9v5AW%7laC-^PCRleD zsL9O`1ahoI*erlF-49N?w~;x~UF7m9xjh=3=pkf_t7Aiu}-oa_Ek~8T87Z>YoH&U`Z1Y($Fbpcmg)zjc9$A3#iv2)cKIE{l0OT64Y=z= zICMsld?QQ8==!XSfA8XNy7Kd-G~?dJ|^QdUs~~-bUuS19ZB{g1&bOOXN)8-DMW<{SEm~k}tD)@0HBv zKY;g;<@uD%lDTs8+#a&lcFJzXT)FPN9M)ZTScJxRs;Dt)A9TfzY$&nCR&yx!)CfxTVnL zErh;uh2Cu`bg2|-P?qWsLg)kJF`Yk_I?A%=qo^Tr$FpFc^NJi4BPRnH-`(qV0Iv|( z3E%@3tQPJ2IVcg-X5WJVZ2W7jokqi7k;X)<)l8?8E=Qv_;!0eSlDGhM;7JvsQ5$z9 zHl!rxQzBJ*Ms2k#@mxw`Ataa^l$^((FluXEiTz5#vl4|c4)d0>WR3d4E*ma-Rt_f1 zEl(6cKVIu6K;R%t<0Wrt9`ZgHv`)xiuNeT2AutZW3;;(^tj|JV=E`03`dlS}rStmS zAb|sO`)>dcdro~L;!Kom-_0O!GS=wN>$nyy6qs>2SzAE(PO^AOU+8MxPS!3EvhX+h z^XhJPwYHMA8-)I3)lPNu^*+e5_;;a1I8&?3B>=sHNbaB(I3NZ5zhGnq7OSo>*VSD* zuchuu5a89*LksMp0I!~@;PC1h+k#`Rqy^Lm%3fYQb6l}YekDd9SZ%Htv(0vTYb!CM z_6gUA$6D~{!!FnOpIUHQ`S7+Y=0&Zl5@IIIl`Va!|C8%OrpPW{EB(5ndd@>JM=)X( zyS=&S3wt$zHX0Ss>v#Zj2s8q?p1=_R9tLm(<@=ru>@#3}E(E~#GT?FmRbagZfBIel zMf+M29k#!%c$LgbS=!!J@zZ-cg-{Ece+*2CcSvJ%oFQJPK6t_i(Kya zEi^Gr4hhj<)Gud_U>Vw?Mk%vWP_WpboY`f|py>-Na8r7?PjY})8Ce z5zT+(E#uzKW&xqWa_T;bGGhR5%{1vyt&W!Y=afsFQx~_ zMKLb=-6jyHm&!qU&RNrD0;#S>8W`FhP5J3P`asO0Z1xNs=HoAK#n`C#EWkZZrqqmF z(#@3*EF3tJMRK+rBH=Tf#=ysL?-VohIdXU(_>c)mz8DF71ce5S3TDf@{#Rht&jU-< zoLgs}B@i5pJj)WP9qaPL$USR!jx0B`;I^*^s7unQUG9o>QzBT~^tRc=Hn12ifo-RD zohxyIk}%I-#OCL@47SEwmkYeZ9Q>l2pmEgo%*=ow2e4Z)OXzunz2Mz>`>`q41m$?+}#IXS)s zfBu?r!MN{j+!r?3G=Q&ftot7YXOG-tK)>Hn)8k$}JG64zB)1|sgAC&5?#A_x_pkc+&S_q!M5BvatXV0;*^?i@MQ9LsX&$myo#&XJD<2W!-El=~4_osko7 zMcX4mNbN_k1Bl*_fUw?=fC;AdBOsF6kAO&OKLR3pKLYN=%l!zZx1VmE%5fDl3M?fUC9|4g>#(o61(Fb>q zoN#JC0wRm_egw<`LW>Za&IJF-E6Ho0&z%{L@ z{Ro1n4(>-lbAC>k^Y7XXTAUHYegrJ9)P4kgLDTyY5Kiq!AQOQpHlx&j1P?>P-H$*D zyZaGHS$97I!hXFU!9_q)`wZJA~C_s*}AHhHfr02*HP?ZrS~IXdg(dx@1d8TBmYle={a&rrsv2V+&I#6dXBssa+{tbXWr9u zhXK6mn`m0xo%W_ajJG?$#{k!jhHyl!V>N-IkqEx!Wb;R_>0RjLLml z>bRA=Ggnrw-j9F{KeZnL7v87#BiI2XwI2cYP)+Yg@H3FqegsS>wI2a}PVGlPr&Ie8 zSSX3qegyeIQu`6mKx#h%>ZJA~xF1MrKZ3DvG_@ZA`_R;W1k}NP1i#0LWm?Gm6*6Ci z5+xhO%-L@DHG4i`wL^i_dZeY6L|v`rVC9n#w7A5&;7QnGS!5(aQlTr()dU5ESwv|W zXnzKRyd5y_vNynf1iY@fp26)+y?Ty3jvS=t$j^X8YL1*pdXAh)rDFl*b%(Ur27?w2 zr{~C@q7l6x0g?0^IkEH{`C_orbL2^2*pGn3mm%glo}MGm$3>HxBbPUt)Ev3;P47oQ zUV4t4YTS>2)bt$rvoxmX$XR#kIdWEbdXAh}dOreU={a&5NzakfiS&L1luXZ&6HCvL z6HCvL6KhEAM?ehw5wO|33G=cPQu`5*f&~{Sog#KbverS^FUjYD9JF}HEMgy`+et3q zpe5w72!g3Oa(3>iIdX~UIdX~UIdV2}i-9bdBR>sU%s&pWGY&*+o37*fh|#AXFHU_Gr)x?XEk9=Z}(ycfpfMtmcl?nHbnvgL^{ z=0GjJ07FhI{s~}j{I&wL;dm?`nU33dj`hcj@{mA$Glu$sI5r+d_{yJ4=|{;4XXo4fdS^~bQ1Q&P$34+@!>Lw2#kyPbR^_4tn=WsJw;BD2MX+I*%w33 z-Ulb`=^_nIRF&ZoC`FX%g|&nwYb_8!7Nvmdk9jr184&HoB{7_WRxys!R5G)nivbE%D%f0$PF@`YWrp`qG0naptUZo)>zDVs-6;KMN#dP5EFXVSG?= zAHSOMmyJ;GeOgy+!Q(pEdGpidlL8} z{yg1|-wtDDyaOnBoV^bv>Z~>Y0MS6Lb9?p*HlHYp&siU1iLzk<*$`usuDZ;z*%V_lh}i5coI7JIw|x6DifxY3&jP!M!gs~CgHvn|r0L(r=x2?+ zmOA&u*t7IBtj6JbMz}(Czn>u_VRV zcDcxw_|zk>Yca8X4ym6hvzNb zeyhm(E7_vCDv5%_6roJGBc!XOG^@W;KcFw8Sd41E@(~M_P&{R_vw>V= zg@}$f(TPzC+xcS3iBp-{(Tc1;@eL;)WXtKI$odQ4qWN@CyS~9f?&9gnDw~BIwtoyB z3e1_ZY*<;HeuDYW>2E;$Th$lsL}aOge+_I-@L|Iu*i-7+O8tJSzwN3U9cS@M`a#I* z(%&IR!5t4N@mC>BXmdI%Uy{6Ek@Z*1MRUz47Q@TJ;qXU)V)HOa zdsdF`F(0ml+M-?at<3nIn896QoNtu(3&HH&*7;LN?5eAQ)9oFhf_U5`6Imt=$7{ zp*`R6h$}^in_fLb?N_P2OcD6TrQI$nU!@4XiPu{bu1B=^EVhgbmBkgXSTFrqoU%Ay z$^VeDc(Eenu&$-W1&YuS1fz=c#v-X|M}MMTG><|%R+W(y-B}sOLAdJ#TsV*&%>n2d z666cqq?pc*XAGR}dIcMKQp}}O*MiXQ0K`Ol5u`!9HETDXEviZcn}C}uA70pN3Njr) zHfm9W;tb(sL+w2e#OI;j=MtAYiri0~-t4Q%z?+aE0E?h_8d+xw?@3UsJqbjkZssnd zp&RP+T##htH?T@;Q1N`3S9c@W0)kh%Y=qQxY6k6W_*S}gSLe{(0YXu!G2)iQ=9Fy zpHb%rpAPkL`Sg|rMsItxbD6LWPu0MKMJop$r3#;|aoec6pBG$#2(agj!#AEq^A1Sx zN<-)Z3GbqSyBDBXJ7A?qTT#sVH&L-Yx3}T>h52 z{0$_^3+amjUiK!Nld|!}5ZW*r?nmatCyLAFq`03Pp}5Se_&{;jrnny{?!b{~*Wxwl z-ATxuy3~Rw_(9UO*SgWQf$(gQbo;g8cvha(eH}*GgHf9A$iiI1 zvX~8nc@R$(X3(N^{c2XxmMATYZs03_w+xj2)^qb=v08S>f~}&jjB8olptzgZ1D`H? zTEX_AxTn`h?hq6C6BB*opI0A17tLEBaum@@6x3QEgV6{k<*^`lARXiAMc|x+ zk3k#9V}CPEjaCT_E}PDdJC2gPG9qS{bdhbx3Jl-02x zZ${%%qXEP7V|ju5e&lg&4+F*;ab@trF?V7`1uhJ)xkUoFl0U*XcbS7Chz*h!egg}` zNU8=&-nK_OJ*ogd2O6z7M(1v*iJ>gHYd}9is=WoZ-c2C!0d_cfkAlZ50cH6#y&_YL z>GU4REY?nY0Wck-$HRbrZJo9DA?WHJ`wguR0x1U#(HP1q{~63NGU*N&)%30e=~ysF zkQYO<@RPSCDj640%NWW_Y6V!QNwr_7mJ8C=;Es#~cpkv0jsS+UQ162zrV|YD)1Y%G z%JO`dhDP)HcmmulCnrNWp8VY=G8~eYm#&99puRFbTrd`9-IT@eC_*EC;kO2 zb|-NZJs8Q<9sG~$gTvd9N7rwRtOZhvKYl$nftcCkkLO)3hA|2zQP5;gNWVQhaRIJN z{)26OCw4)x@E`2voWM6~XX76-PV5c){0DyPJ27+f3{D_nhz(`;rCKFwfG^by%n$K5 z{%ADRjCCWPe{ofnXJla$)c?&@Ri;{1;?46qm1f#Gm*l~v!yKyBF8-#`hL0gT}vnh&hK;q^&Y zXB@q4ad2mSy(e$ViNHR`k#Y-7aJy@OArJ9D@2e2 zx$jct3Xw-72VKY&B2H-|$m7i*N*@qEdnRf^%y4ag?Ao3o%C+s&)3(pZw0%a}_8G42 za9i3M>e}j#>ZPAU)3%1CZ4J+~H9T!=xVH5VW}vfcYk_O4b2`sm)3y+rn9g%e+E$IW zl|{cIuB{hcTamP_+_bH{Oj~(rTY0Xnyb-kZt*VL$rlaza#cyRzL{Ssp%ZiAiB7TrQ z#biDFAgdvYYWP9bLf)&)-P_8_Nv@T*Q&#q*th}3H<=vE(cU>zv^yP77rP;Oec*@F? zDJxqutZYqL+3H#uOe@XG%7?C%=9HD&QdZVxSXrC0vevaSk5(2cD^+OuESH6{6|r0{ zNm*H(VP$d3%3{~bBwCrQtju(+OiuYSHDzU5hLve4E7M#nV`ycFvhuKNWk|}Gqf=HI zGpsbGtTZYsZP<~Cw!VGn495fjHh+MdK!F@zx9vb!j4k+<_1L!8ow%sPxWXA&1tdy> zTngh^Ii{$NZj|QB^`>Ks_E9tu`k9L3+I|JAxv=^G&|(x&d5BkVfAq>FJ5UFO*i@+^ zM;V$LznF$9b9hPe*|e0eU#6pfC_cjwJ#wjdHM{c!OY9pM-UADwUF05!lr02pC(V*r zekHIEfmPtK1wM|dU>LDy<<#=KaBhT$u)^B=>Lmn`(MtQsH?+c)_s?O)HzE zc4NiweBKZE8Q8pN~OTaE6v3w-3yMa}V1wdb>$@8f4 zIXFi+NHh|>X{>q^;}=@#8YxGME;|TXJ=i5AmYWcs0<0qBS}Am`w8QxYWrg>op}R5G zp_Q7P(`e-$(7vS=63ZV0R$K}zn7Nd`ye!Y7%HP9zF&LN=>klygmLb1RCA#I5jRJlT zSV>JR9|y{ITA2=jIXXw4N0l$YIhmjpoIP(F4IKgS(yWu0=Ewxd5s=X<$P2Hpyzmx) zjGt|N0*BklyDP7Ed3UuzUL%>ja*fOIT!qLY3~1d!kc9@v+F;lQf3Yd>sO7TTT97TZ z;?`0tZmnO16iJDUkrURVV}y?+WJr;vR@_=@#VyvEAC2_%di2%G_&dnB>4p?-CaLA> z+r=R1)wdGPSbf_nvS>JjTSgYq85vnbM@{vm6TYU@kwr<6e-&AzSKq40BE9;S-s;u2 zzlto4jeebv-I{$8D5q18H$Re_F4as%1?w3yfg~%dT>tBs5 za>Zq25#d8e7V$ckkwxqc5LrZAMi!~w^xuyxVp9LZkwq85WID2lw?sr1ktidJl;i(W zWRddi|L4deI`KarS;SKK??o2TA2h~XObPv;Mi%MSx07H|Mi%MSw^xE-x{*cAgx$y@ zdTpsG9_v@1LHQRVi}Xs||2ndWY2Y&`oO*2$S!5nEvWU`$jw~W4@c&69-DoL_%0fpLEqu)`QF8>O6M z6!%M=2#D|-&*7I-N6zlw-;dMiIc3_${o`okB;e)c5a%+l^fz0uCD~Y93eVAv8D2KS zw=tZr7c|)klFH-^`EKoMnv`orW*kG_`^2LduZtO{a2C3AIq)x~rCHsO2a8b0Dw;){tfYO5*~f+&`-r zQUYIo8ISj@7a&r)Y!~EMv>jdo@D!3;uM}v}=&;AN@=Thj4PcFz(eVdYiG@l9qk{(& z7W0=%L)5xonK8=xfg@8I0f4?2Kn#j_KS!DKcL@6KPZ(vhU8`jmx+>@xx`epqM12T&1qaRUlN#q^OaQ_132&n@9(cJKO^{^U8=I7Sj2P zkW2k3Ar@hmE!tw&J7}?Uek};_49@q2QdJq9>*|JU7&Q-5sGV;YgusPRH%`HexQ}-5 zY6%pk*M$P}DbZce*xN>TJu`0`J=()8|4xn1;4Fh>#Bpi452Adrzz5MWUKqfy?hM?U zTRu~=&@n&#JE$IVnTmdm7L)tSnB-`}#Qh z0b@+aQ#K#DjeteA?6G~d<~G3gXE?}7d0%~-EL`;g>jx>wuMhd-IApH}ZUpN9axt4b zOK+1Eu!i7h_rSrOrMEfNAZO`)%Zn%;ejlai+beQ{WGqLs%u@TIIouB|OYMgi83iGc z=jEK8*Ie-pHX%!3UPuh~twMjLYM5_(a^I%h;3CS2v3cK1tP^u~VkNi_NPGZsG2X}- zNOXX21x%oR&?L%HnR&-ZYMesnK`H-k6Ys0E$UtwDGiNt|5o6LLq1XluR`!ub&Lz~X z_bu1r>sSO!i9kayPRrw73%%QX>7l(bs{$ON&fqTuX~J%w{j&(v(FD!UdRK=~c)~ z{s^_a{1udGcM=MKUm7i#GzZh5y}Gkn`T@`X6I4~EjSM3vLjU8wvp|SR z`B@<6w}Ie%EuYM8TbY3uCus$$pD?MYZw%z}r7CM8zX!M^QAiYd+Y-=t@j#_oav4(f z3~Fn#q~okm&!8h%p+?C>B1g0}StfB-jOU2Hit{)*wQWu2rSx=w{aCq=WA@odz}*0`W!Hne{i^FRFTaql>m~TsN|%WZ+-Sa z;Br#Tw=s)m)TEg2F7M}nv9k1UD0$!ACe<9(J!X}Z(5IH~EaeoLzr65V$OWy7aFmPh zQW5mGFd28pnN5K4aKls1eFTFR*?OG22yiavVDn}nZG7(U1;9az@2T^%EGCU{?q|TF z*Li?M)#v{7IG6kF_;bMU;V(1V-pKtyS||Y}*T%u^OLJp@^W6PvC?0do-{1+21KMWf zu`vG_QWViYVm8_neGD_(X7sB{mW;RPY9w&0$LvBY?05r_2rq>^cD#WcnKjp8dwl3l zNJV8tZ&XI~MrA~AR7LcfjOeu|nTsH#Ri=cv3u9D9^hRYwZ&XF}nvCeRXP6IV2%jDj zXgX0D(HoT!y-^j>YcitOo@wsO5S|^XqOgqUjjD)VlM%i4T$79Qv;*gcxUq17is&s+ z5xoT}qPJi$JEIQ@bwqEWj_57a5xs?}h+dNsz4ii={h2nsDD(h5kP*F68POY65xpiO zdhI3VwHd;fhq$maDkFNMGNL!S5y^WDlM%i4GIJ}~fqd)*+7s*WMUom8ghb`;HhZQ$_UJ zn__GRDx%lEGsbdL5xw^282wZcz4l$PdZec!dhOrF=%phdrsH4ZUxK)5$}cM6Q!lpAME4jclN%+gzQ*KA4Cj)P zI4D>IrUj1B0y)FcSLDc^(Bw)CXK~3fQgoyifX7u;L$XLrdXu&q{N zIBx~XP%AN0n+65YWLS`>1xiD19b#lWIx zRzf*?Q-XJbdvWwcpT^OOzJ;SddJ^smB6|?)`VI55a@ae{tj#buEwqsa zH$lLNZpKXon}EFtBzT&6B^cpblNfXcSNSi&J;Z*u42(57R{=Kc==>TB~oc0$sBBu9#q+UWg6TV}1RZET-Q|IN%T7n>`r@?6%K>cwc@yz(yJO zPY&Ln+Z_l7NDol=0kc1_T*~H+W0^fzvk-95Vm;<{ZwK(9l9iIe&FI|b6*?+ZiAkks ze-x|{eFEhsq7xGECt8i8H#!6jBP%);O~N1D46E7EsgMjrcR|vQ?gQ*ZKSCP{Mw4(l z9OctWB>Fnwoaoo!=0>jqoELo)y7|!@z*txUI2Qc}EVqe%4@!Yy_68|5-n=2hu?e9~ zbWHA;9hEy~N9B&$QGv_Fie7@FKPq?3j^2gqGZE!A+YpsIW*6KIt|1E6@Z>2_J7yQC z9kUD6j@bn!YbjCS?wD<^q6cebnY#-(8cG6+TH~+`)mjwL*x=eChYB;jw=1Hl@mOTrOd?gF|?{kC{~OS;MDh zbGfA2!67^$aSjmf;6QVJ_BtfEc7qlRN^RW`zR65gGXr?pXQBsnlDlY!)Q@P;!~Vij&`e z3hXKoOJdBBXgBd}IrfK?^?v&vU0z3SwAVyhHZll+p^yjrE# zGkFd@yFug)f?jQMG_e~+q!C!Z{GxSoE%L**NHr~fX3t_l)PQ! zvVw;tZ)XY{MPvbTyC=Dj*d3}|_9qLdw@I{_1}g`W+o*S^N`YH9l%PJ<)(zn&{M=Ga zR_>D-mAf^ga-Yhq+-;eayFIgVcVt%X)0vgKQ&q0qx*@zPz!tBzZV10v@+neRTQ`JX zDhVPdYU_sZtHEwSs%>s>9DXhPSRgfJ+}=3+rc9?N5LC==>2p6IXpwKpMAZw{@SYsL z@KIYggx}4X1mx&4Zf_jkD-Ecv8^V8$cwgZ6Xt`?ZhVUoObGTsD)(zoLLwp`r zTQ`J1lO4cRBmQSdvpwaoovHzQ{Ju2zf)))|a(cKRJXrVxctl7x(Z~>yOTB+$t=1wTS-0CtyO$Xh*F=9Pru#g+d`7Mz|#Ux_koUO$6spk=L z=!)?RR%r17g-k`*t_Uxu2(?BBnNT468_=>|$82YAB#RDb&4-EHyr4`JpWOgbU{W#f z3lvpuQ3(~y^O18gTaK|h_JAwmoNV5^z2+*s4(NCg=J3(i03L+A=8ZqTJfPE}TJfC7 zo&rKrAiLsuEHngSRF}c1_`L|sBUYoD6k+9eS4Fr?6BhanZ%34x*d@$*5IbK+KVB3? zzXjqozq|A60SFNRoXd4~T|Q(|yFG#XV7va$dgaVkbng#aCckLiW7hI1UXq%G@fdI^u*=N zRgWaRW4a#5VhwVBPmT2AC>cL&T!mvUJ(3sGX#jc~eLA3dh(|oRoR>_ziuy?l@H)|?VM>?wEURI;T&TD+FD&T6z+t9y6ylT0#H8~zzzU!K&LNWA_R;? zU%a-&3{JnXV7&~MOU8n@cUZg|JdWVvoBnd8)do)&x;Y>OO2elK@bAL*`2z?2iFJ3c zCl_wucf`9a!5V13K~3psji-u^Dl;{n2AUbPl||p(6JYP5Z1nJi)`K%(6BLh>3H0)K zf5dwQUOS?B@St*(4?M*)g(1MI^8k@~B=tRJwip023oDPL+&tBjZ46-GxbpfEpaX~C z4fge(d=@QMsTm1a{7yLZMVyPNQ03}(qDR_QEL0|YKwq$xcX)fa9^Rp@wRaBymEM6> zcQ+8}9jWvV4*^QC$`jn%Qt>mb2v*&GAk0J^sY=l}`s=Ha$}z&rmKxcMkY1Cieu~5! zZ}ehe7Jy@JhZ2@`mhd@iEDG(I<*db1MT}2`XM>=Y%uNuv%vK}E_5*O$4sFLv_Zm@2 zYq(Nz?aH!#2Fb|WEE9#tvf1qeVGoqVb)qnV_aDQ)0a1!pz3+-{@?;PH1=Q{!gpkNN zg~&%wAlwPGuD1qiHBhgCej4bnfd&^ahO@B;6DR@QOSADJ$K-<$aMuE2T(>MD*=3@cpfYxtz&*z^7X@9 zMHAVDF~qHJf@1wlka?BH6d6g@tpn*;v{1EPZ9Om-w=Ib^AnFeCr-5R)00}pE8Q4Ktyfo(2e4Cm!!{Ye=# zaB2J$sfpn+lyBwWB4&MRv$FnY*6ChHo3JVArQG%!j7Cum@d2F7ck z$pwtzyf$wJ#?spagCm{;!ETS@Uk@tFc`>N6_<0*K`aJSLt(9FV&~bc`m;T-7gkrDtjKS(L834rDg0`ey(f z0kx|XU-UHUUj%6=NL)(+|3IpH1EfoE$LqHj08>eq8)|43E@5^`_3HsJXM1>jUjS zAFp{Rjob#{d&QGi1UmzHMeG4^G9;qtG?Z!d7e?J)kmYUWLbu#|X?~^5#bS_Y*cdei z&P|4N7a&;g7u^QIo|-UXI=FFE{RmDvb^}m19kNrPSw9oNEC4H{WnAZ|Y+iYDK)(p| ze%Ao_FPcRkcJ{Knx(?1@>}iObMNWMjT30~*L*+0m)|Z2HKhpm}k!15|2ilM5AOrX# z-=x)@0NV9X9eE85R=5oIA51`&RweHHbm>UN^qNa#Y1Du$OQSn$3B_!@1%cz_P49N$ zZNhB~I6C;%I7ydhf+Ra*uQMUyo?#NuX6#z@FegynywMF5HY#gooTOVv)xGQzgY8^D8B5V$6G58F7Wjg6Red#Vc}feRtWEfU_A?$&aKy48)>X= zFUalTyn1WT`jpS61&9FvJT?LivDVjsETSc$HH`aDlz>?66JzgSm0#;ifQ8!*SYs!m zS&5~-uW+T+NXq!rU_+ei`&eI*%^cvL%ISP@ZaGI*2+o}FB9iwUU(5+3lLOa@cy{od zXcIS@R-#|=9NpHO#4+*$*f~vFz7c*+-Vc)RM;_OX_!`IUXh_3<2Cxir98&FswYud% zOpHY9uF=2>4P2*zRT@~Mfg4@G7|v1b6ToONie&4y0_jJC+cdC41J7t+rv{$az%Ca+ z8wJz@d9H#nG!yosw}HgFWIsiccgc;Q4FzpvTI@cMcw3w7l5h`u5F~a2bz1;5uob@H z>Rpi%>bDmp-f)o`O&e2qwe?2D$!@ZFDmM(`KkrT7v?R)p|GZ-1oAw!Q@cid55dLYu zg+c!F7YhH>5NcokU-eD>1VsMr&%IM0fi(X%=oy;>q@0>H<_Z|Is|(G;Y1bf1ZGfAG-Y8+eG$M4kq}wAM;J+#yG4M8zVXX5R^7rgQ&Zne5 z!}-6mokHeL3SR3`xYRN-Nd<0VH-*>XqYT`{ZVG#)zqrdG`)ddXEVA`(3XcM|Kg2=r zrtpgt`4Y!qLZCG8*KwL$E*P+?akPtY&~chcz~0!3sb zP$VM~$UDhAB12_LXeCu-Bv3>~0!1<+fxI)!*%`v8hqh5zMgm1-Bv2$H639E#yfs63 zcIYn@mXSb_j7T8wT=T^Yv2#P556MxHKshQBC`UyC<)}!YTpbCNt0RGObtF)3%Sa&a z0`uz((~Cm<$W=r}0!3sbP$VM~$h*WG2DUD{%R@I)SVjUxWF$}|BNE8F%)9{XynOHS z?5_c2ac@8G)gi)07B@ceULz4Ji+lTdua$^Di+lTdSA>?ay0f^sn|EbYrh{rFQAPrJ zuQNBnj`rlHP>l&sWF$~TMgm1-Bv3>~0!1<+fxK%?6QX&w-rKWx0m$Ose%|#lIm492 zz5To!Vr&vt7Wek^Zj7-?{8_w62!S=`&tdr$0Kh`EtK-h0h{VC6Fs$csoI`sTiS^>e{| zHXE=JEyUPKlxKS_NSRCVt>S=n0NiLN(kop0a?oSZi%6=>u92cEq$rovN2lPD6iJtU zBj{~@CS|0^rq`H%1gT&#Nhd1Of&KcvQ1~IqqlE8IDbh_aS+oqf202LsxPiB2Kaa7l zVE!(I=v301e}ri9^s_P9Rxb*8ZQ30WA{3v5iNSs%xE?Z|mBUKqY}^rQD~`bsNbG`v z+q{^|?nNVG~n%Es-rSx6yC&KR|wyrlp*?4G#dwyOIgBVY|%_5)l;J5 zjP`dEA1BLT#6F|pJ5-ZsJ~Ioq`R+_F71bbemqe3-R&9)eaoBU4gHbcn7M=n8CE|0Y;nUaCW%^q%2CU}C`owg(Xuf|pOh145fzhzrCu`T^Pa2(n z0RD->y(^m+t`bJ)!5zSfafZxYzCf{<*L*eo$mwQM&sujUA_R$h=@*-Hr{h3 zbn-tk8v1G(BvTB0gu-<)-9eh5MG{8W(}2548nSpkeGjVgE{+m;k(Liqz~f9Q+-`^ZrUpeaZLsKo9XBtd=9) zI)4Clj#?dJlRXq{Rf10iFZc>>0T=PiypgZr-P4|4U&O(C(t_x zbSR?0Gf?h&2AIq!p304$^nNJ_{iVT_rzs-BN)$s z0!!iuG`{sNZuH~@cS7nyrA#d^Ib5Q3ec(3#-W=hVACf|e?;gnz*_Hr z;BPQr1VetXTm&#*Luq`l{A&>9msR}Bi%2i^o7wT~QGjx08rh{mLPlbmk)2TA{uX&R zV~ChtCK*da-pRzuB@gRL<@b*#L8Xl57b3FXOMZpP9rr9UTt5Se&`rSN>u@mQ@+;kO z`IYW?##g!nNplYP>MPxW_7Q;x8Tpm&KvjUS`bu}8gGAIhAnGgKfzF{SAT7VrO|~o+e0O~gtW!eb?pM0`9OZsYQhud7(8c6;t;=`uL12UL z8;rL%LrpZV!&F1X_mY~FFb3-t|B!euJTDq!iSLm35aKI|%O$=WPTmCFUBD~lx2o?5 zGEro$Y(V+<(#=F(F;9$dpj(Fj7DUSTy zY=^U4DQ+N<)~90-6Fpt2d60S)w)jQXOsNAG8=aPc_eb!MEWQwXF}$yigY+>-)ztvL z0f4rxzC+H>YRk6847qh6@s~7SYIOd9B|5;zmT@x-jKZx{H1|P_T}2FyPz>n6y0{Fv zuXsXA9z%R9@!v`O6qfzBz`Oj0@&j{g;lU!&a(L`FpsP(aW@MFn+mLqtSHM8$OwH*gzt9CbhuXIvO{RMc^q zQHN1<{=eUItCG&V&iUT|cfNDJoKu}=yU$(gRy}p^^IUFQz0wz;9=(oZ2Alg9c*%LR z2Zl@F>>zWw1hAy8Sp+`EN1w|9aP+>W1dX|!qxU9oIC{V9#zEmk$5?M%u7?!ICC}vG zxK!y`g&H;vhhD$;0pz2oEQqSEr=;8)iiaZcKu&XpGga3H-NA8D9MQLcTra1y7Y`8l zoYUY-Uwkl!L4yP~DL#q=ZSWo@C`-=3&>mdRK30=$Ber_=igOZgYDDJ@mdXZhGU7i)ao+_;U(JRYA_a&_0csn8OCh3Ch{?cvI_*q(91Hbp z;}& zYKpb;TlTb}zs4_AEEskzfc{_(zXiZt2&}{Bz+r2EoCIpy1^`zf2Q;}h>~0|U^Y+vF zq(I}4c^1+#hwNS8j~N~wul4Bx0S-DIN8Tl1%w1$~Sk-Gay&zBl4Sj|II0!&Fq}i>U z%`o{;AvYHG)u$SBmm(GJ&c6DzKyaGYXA+X|ei*HiSQ2_2sVrkWZVVYz2jL4Hq=qnu zQvn4jJ4hP_)QXboGB%RHxNk3aKNI9^>ymfSlb}P^IPqz*7PjgW2vMzl&3- z+Wq5qomRWuKYrI479QcRnS~*ar9ECwo!x#vdYYFr&~E2PV_v~$tr1-zOWJ3H&C4yz zX=hALUXhI5J^}xEMS8pK*Wo{}NFTfXHT>rl>F2hefd9NA6}FbZ~1{>(V>??A{|i0Jvdd6lvxxy!%^f5iQ^y)_XYUmWqO6smPj^3O`_}$eMv3 z(1OEy&!?OUKVYe_ot6r!X{(P|;JuCKLVza*n|lhbrMQYn5J=(HvI_G?f)rpB0;?{0 z2H+eXA#5TF0c8UpK7!@${?StiUyEWQ3W2~q(Ta#dupIOtqYxA#lhB(;i6{imgBY4a zctalPn#0;u0}4~8p}CAgFdlg1RH|H`Lp54t4w1X9?*Jo!!VBDGfmw1ezVUitq9y;+_c`o4GwfK>619+``60l)1 z0DNIVH2 zwop@e9+Jb0+AP94LG%TcA`DW%ZTo5xdhnzM+f{|O9 zN4p?yWGreK8X-tL!exZeNI{a3Jc^AHq%iU(IR^_;5*ba-XhF)g{H4$x)I)~{k7OD0 z*%%WY!dm1l{Dh7O5m}VtKG)DuQUgs-(T6QGNig`ZIme=HPlA}#%lBambp+RgrrL3G zE@3TFO*K<&R?>`=f)qMFv=RS;ktsx`mT$+uWoR#|bGG7#m#5b-w*e_IOtzPDWed#< zehDNp{Ya#qpCGJ7LU`c}El`<2700!5Wecqd&OlQn;mQ`eHCKd__%Ie)t9mvGSGLe? z0tX}0MnTEC&?F>wBSE&=?Se#;bY%;zPy7yf#Ulq$_0S!XrZBSeN+5UTzKlx3mF-&y z6utuZs}Nk-NKDg}Ed*CK>EtwB*+Ot-i(qCl({yD6mLwKT)0GWa88J6aSGEvb*<@s; z>B@%f1ffBgu##!IvW4KvMqXi>u52N=vJopu)0Hg*SGGBrMaqll$`*nv8x6L~G+o(3 zaAjkJjOsL9*+Ot-W4f9&UD-l#Wg}LXrYl)+tP!{gDczJ;EhVtl`RBUHV%Zb=|?CDS2p(Z`1Ebe0j_MXAl;tyLSk@b zW8FVY)0Hg*SGGr><&!jB*+Ot-V-BCAbI$}WbLvfIp-!k$>EgYJ0B~ZB}0-g zb24Qp&$j52K@PtLK^{b`q}=uag>Uz9JYnd{7J@6=P879JT-ic!Wy`^6Nz0@SS2iMA z`es%Uu58T8Ow*Mu1Xnh>!H^dRn_*IMp}4Yz;L6rPCDYhUaAhN+rRmBRf-4&_J55)% z5M0@g2g^-|DG67$OMt~Shs4t%<`uk9T-ic!WqW{X>B<&@E1Nt~(sX4D!Ie#wjjn7V zxU!KKOkcs0!j+B5T$GX2!WWU(#1LHBrr}0NKg68j%EnH@yh04FZ0uPxO;@%MT-k`Z z>GP->u584TX}Yq7;L1iNCFysV4z6r0L}i+;Y$3R^QL;MSmqQP(Y{cr)-w}f=8?mM| zUD-l#Wh2&>rYl>Ubd+Cy%EaxzOx*s#Mezf9cz%UY{YpE7a#FB7-_GI9Ga6Sw~|ar-aRdSGF=Ox*s{BaDI-v$M;@?Y~Ui{>yYw%rf3;!Lr_L+p@dS5ang!_FwiL;6<5@ zOr>X(+kZy6{bxP{OABU{+keJDQms7Wx%~$|t40aVGB%+E0fqo@Z%yzqTt2c76dh#$ zfDX2dwb&j~ehVr6J<4sMRHR7RZh!NM9~f~7O5Wp~>DUdhy@DyR+*|Q4WS~E6e+VJi zM=%dJK&Yn#xqG;jgAqcN+(f9~Z@=CtRLPBZ`g(f{DA?nNWL4a+r(c=hAIWEfI##GW zWwzIQ%mT-Rg7OS(wq7+X*9!M0;CqR`PX0>a|3til{2K)?83My(Gt>nmxDmJyvs$?~ zXcZ?@>LR-w%!!iMYUI`DLZQ~P6tzg(ho8svi^edo$-w)bd^Q%^e=WN8j^300Q}YGL zM107!e#@xof*5-{4l&g@RotPd&yvCU6AUn#V*2WLn6ot5tln(0>yVRH#eIr;qjbm) zhz=G})}xPX)NUNa5&jBAYnqW4uSmV4z1|n&NLvNWGm8ER0+-xx2tpKptv6#VcuVfe zS}~L*V<u*lNhnh9Fm?-jxw1HWinYbnasn} zu)#1RspD;2HWZm<68(w+%@Yi zx1BI89&1A$=~|Elvyg+F#mBg7*1Aw1;1YMuTA#zLRNOV|Zfh4{L>HsQV{J5;%rz}q z5_U>TYtdxP>5)DhoQQc0ekIbHMFYd`Sv(R16(qy14{ie@!5!?ud4#n%3=F$bGE_k_ z?8Y#2S3xrD#v~CHB*ShLV?_=lu$#g!AUT6%oQnTJdS~p$B^5$`Vqn;Le zfngsWT*ETZz_2GegjJ9X`-l*cMY%LE?4umEvP*Q%c7VFdPV0;^aVu&`$! zv5J*p-!6!XS8uORR^W z0viU#Y(6DYG%$cAi3L+MFo2a2b5k@hY#10!rw${qVPGtTOfp3S!-j!DUZEUDV8g&5 zrVb;pVPNdRG*Mna1H*=a@h-5+6b%d;2F91b)XKXJ1B2<*%DW8%gP1yuz=nar{M5?3 z4Fls_q-#piz_4Lp`~a*qMFYczfkDZ(6b%d;28N4yW>kuU!d|QAaUhIM(ZH}_V6dOZ zr)XfKxY9WUa*iQ=Vb?#Hyo%?il=WfgH-0hOa>)hv5=Sr*$dxyh;uVQ7`FO{xD?kZM> z{c`CxASzad{c7YxASzad{aT2T_Uqy_Fzj8DPdyNH%|T+8s9Rjxr4Fe6c%h*d3>%wNkV@Y}g${ zv=r?Q8+Hdrw>pf#hTS3e9Yz$#AR^r1H(%@y8+ON&R6@JMhTTC#OVRGIVRsO-Q?xs5 z*d2Ugs+D&ecE@U9*@qFRf~&&_Y}g%1+%zfL9X9L^dC;V2ci6ByRM}{E*swdu3#Mpy z*swd8j3G2g%@@1FhTZWjmC^37VR!KMz;r_lb_YA$OwsPJVRsO7Q?xs5*d4@@DcT)2 z><%g^Nzv}GVRx_)>M#Nub_XS^Q?xs5*d4^`Qk=VO*d4^0QnWj4*d4^$QnWj4*d4?W zLW5^m?1Flk%sWG9kP+8~+y)Etj)6uwjKE?**RWt2FV zg!A!+6P%E|9R!QtQbVPs@;aryr5f2s6gY$9FCdA8Zgm>nKLSQ2_%BUWs07&-zoj}& z#yx$Znq0xK?3+)oRHFF%Kbj|t^^>EsZ?;#eXMKJ&p z(z-aJpaO8|5(+FYBHhyyE{~o@J+g$JktOtuETL!A61v4)!d1oy{EOX-pFQE;@jsGQ z{49Q|9l~08GhTqheFV|NkN*xxU(suZZ$Z(*{i1sy77RadHISOTPk@XKmoUvi(fvSn z;1x8m3!NKeV~{Pyj;VW^5`r&Od@jceZfMqUD(P>`fk_P_`jZE&&6S2#V&vl}uJBQmprmZxShMr3S; zQ3{5N5gEHKn2%*%i4hrFmB;{AF(PBvC+dNy7?H6X1W_>}V>d?l5~^ZE#%>lw#fXfp zjvR_KDn?}Nmc%JQRE)^jt&w>^RE)^jT0vBd$k=Uys2Gv4+oc35Mr3S#gcF2{5gEH9 zas?Eq7?H6%B~uk6GIp2yFgQ(GaujM+#Sw-WM9i5W>)=l@Re+0Fz%*N0ejwWHi?XyL z>dQ~0Jd53pdOE2rOPb9K1&aU|qN6nyqf0akq7DeI#6OEMB4Zm9Y(a}LB4hUm>;z-? zhPdD^w@vK6<_Loy=Z;ur4n~_3Xz|#)ynPR9YpJ z0Di4SeWAzg+X^_@4?l^+YBX(|8Se<*2Q2*CgTS8bO%ziG0h!`W6amP^k5>~#I6`Eq zH&HAlazf-Q*!yO$Kj61AH-tMnewN&po6Ow9`vaRD(XdXt8Rf2E5h8t`W)YZa;ud6z z^XcXW_pt~(h9Z7J1!DzkD(SokmzUwGYE7fwXwCObO5xZH<{e)g?15~cCWseDM?$do&EVb9(b3#{KY*#r2F=l|4_NUsgL=xBneh`ta{$G;<{v+) zj8lr1doM*!&gYaAguUG!|7GMxX8V30&}XF8JO(r{+K~&7<#OZ>ln9YeZ z1W9TZV>Tyd8gro9V$9~mtQ50JzD2^m6bKio`-Ksk6AMcNkdK%_{Ptt9^8nP~dnW}K zm1cxlh2KIl>j9|y+2W0!SX|2QQ4w>rFK~h{kf!mXUa2fbY))KUdWMMp$``%7Q~ zi854kVoB*L5nb(zKGI#3Gm&NuL#o8m((NMpJ707+MVYr|F;sKnlG67@;1gfq00pQ) z)x)VzEDP;Mt`e#_ahZ4P@{Uhj?%letu`RCfZrv})S?=As<03$=l$KYaniE$EqCzz% zu1Bi4_HGS{14}u~HBfsyT5@lI^NOH7Bl3vJF+J=EQaRY^CyWej)PtP3lu< zQ=ys@t5R$f6{`V&cIhioZ7|awwbttm|qs7UL z0vyhKj$aqs9*``z&KL>VB=!5b4UF;x)y$hntz~v1ot~+Z+#<-?$XpMmnc0M2EAuA| z20ODIa8717euJ6M@EgjUkA`tFf5Bi5YZecx${lVz(3M5r=;&=AW@J?$BdY=#Sry3C zlvAy&3S?weAS0^+8Cey`?5JSzWmO;}s{$EW70Ae{Kt@&tGO{X=kyU|=tO{ggRUjj) z0vTBq$f#8TD}~uBIi>1e6a{B4;5WMeAW$9xbkKA_dNN=;pZlMse*(GxJ$MX&%!mS7 zuo>T`li*+52P2~uz^woVNRR<-U?nDT{ja*qm-E4&!4VHB^wlHKVEtFt2x~l%aZobo zwYeaCs%MS`A+WNoel-fF|4o<2#LX0tqqx4%3)nHn$|n{M`iv4E>&Y`E#rOtnAp55- zJIKtH<9oV;8#f?J$Y?zv(6kS&s%wGJgP(fgZB|?7Ydz!k`xpV)NkMeGt3F>FaycsX z3KF6oqNJ9{Js@he_aT$Zp`-R;AK2;x+kD^!A9&dZc6xx;{2`#-{W zeh%WZRF6*K(=@mV1BWf+Jr9w2{|A;2-Ka?H3OCLo-ss$gy-XP%}y^p*x7%Mj~Y+X)u?|Kv*<=xyLI$uT6 z{(;QU&)BZTQsY3M0czu7bF(Lqhb$?uav}t<3kO}q23V@gOOyoyM#s@4 zU8l<@C?N$0$#6bKzvn$96O!5Z8j4?svhv{jL7%cD=jp}jsI}b}4!Q@%r+&UqSa#9S zpCJB`Y8K0warf85RjXm&m=@HuSx_>Z+gH^9zY%30I`?l{+u70!7&RYWh#_)mdTA3X3jSj?MbZ9o&4#xq~ev9g`(^Fvn9fkV{#pvu) zz0U8_USRuOD&1|Z9B=n@J+``i`a(u-AE>P*qHdo{QRMm1T6>ibtnz_1K5(ZG+~)(2 zdVn^p5RFq&>{oX^;`l%{8XKcVRrfEfPj-*7y4^dB6!U*JiQM&*{9;3O?U6v(;wdK_A%a1JC%tOCF%rz5?h+6uWjefDq=F<}U!`19$`_;azqyemVaP zz|QU^5c~#wnnJbJUt$j}0Im52+?_)Jy)Q|ybc+;*v&qz&U9>gF{sG15RHoIIfx|nx zxj%q|k(jX@arf|MWwybU-VIVa5CTU)pt%{q@c<6-C6`?UNq8zWPXgyOaHe)~wC1TG za`|#z7ZKtz8PuKx-eT$;hT2>S;1&_$o?5S-&4+=*0&Z2wEyLZ|IqlRQ3FeJRR(mRd zC(+$_6ip5Bmo^KcL*ua&F~8-*iDb?c@^H#%$-e>~I1Xv`Mm@!uyf4~ujg03wEa^6x zV;l7jA_ooiXYxjU7H9H#B*=8ysNcrv^Z^oNYH!rHaBBYqgof#7W9#@3y@=}dj`{%{ zhV5#mZ@?q3aUQY+OIwAHIh;60sEPApJ`Nji0uz?6_8ypg_8+R4`msZw0Ef>?PI7!? zO%Bf0eyx=)(R#42E|I3Y0KZcMmm+=h6o|704?q!;SjH3BC@sDEu{QJuk132w%;;>e zt!S|JjV$fy(lk3DbP>KWAe<6!8RYCDan3(FyVUYn z$Sx8I;}7AR-%HSiT2O5*VKpxy?p@p2&{|vX1Fb$V$_K{#z|lT1#RIg)w!f>l(?*o~ zU<|?^Qk+AZ+we1N1}4#5d^7UiTJ^|YOox-eL3QS8J&(0_B2jkRn4orR8WK!-g8ki} zRy93R`vs6Y(WJGcvL4MYUNs*AGaNY(4Kp_L%{k8`;RaQ3S=RcW+~fmydVtpWIv{)=(`r#Y-k2G6?@eI68~20Br{O1^b+6K`x6$O)Ao^Xo z0nF@?!j5vY2bceJ{00f7-=L)VDkl6Q;(3g)=I6p8X`}l3l32typeqY zeJmzx^hs?UWaJSs7yus;GkxLB3n+|7L>oAKM6B$_k!fs-ucvt;g!uZtQG~qra(%4U zd^Q*?#H)U4DTJ50O_iegA}@Ryg@II82Xuwp`Nc7V6fc;&hL>) zKjDZc9t2=$EI<@O@c1wrCz*ewE%poXkG?@ zUBYirxVczSFPDuThgNiV&Qo6E3Bt)P{!TB=Ier>>JLs&Rr}-O5v2Zu~QeB1PAVv zb4>*vA8M{?ZUu>b)+!_ng+**_^r_ao1uQoAQA*k}Hqbq<`8klk$0OuiMV1lTnQjTP ztH)i*?1qj4z;2Ks)~Oc{;lIM(ZQlxxUL_CV(GWaI=L|Cs#1Sl_UNwf#skxYzM(~5R zUNxCdvipHEK6!mSAJ}WaMkV+>YL!Rizlg76>UP1oH*BOl(tG!$8E>uJw6JIS$Y+?M zx+n88KpD0Ov;CXB{b$!WYZ9g!|Iny2aIsh+r#t$EOn zF7c-6I(q_m-AavVx_hb5SEXLzmwK|*yxc4GNF?@3O}3h(TaoLBEcGZK81Dl|`@j?* zIK>BMdH{kHqx_tT?-k{^8#gV)(C9Q{o6iNGU%0j_KB9$b&Fekd?yfXi^G1*OnNP$w zo96u>a<~R?VQ^bUD_{AVgUFubv`?NQ;8Ap}8@+(5)eDA(+ zojuNX3=G$Y$CcrBGp)b0pOKe zqub;B*qwRTMaT6(X?VGZM8*xpea$P}W^0SlxF#0#@vHw8W8Pf=@Tq{N(ZQ8}+aJb2 z_l$205x7t0@M}reJx!Efw{*c_< zYV|B;w5hn90B6+)p9kV{LzFc*kFb`&=2pww-0ISM&hj?5x;38>QJY&`de2$j=GFwf z=d7mi?~y!-49~#-P%D1^j7utn{A6>h)f$|N?sVxrXL*}jU3$-1-sV=9-gB0>xz)Xu zd3c*!-LWPRZ*!|l?>Woc-0ISM&hj?5y7Zp2yv?mHz2_`{b8A;vsoPlwZf>O&w&y)s%{Hn&Q_FMlZyDN)>Ox^4yga>8GXW$SHQ8SAzo1e(*QmPGEDZbAMn!sgaFIT*UKxfNKFnA+S5tc;l2+-h~(+-hNSE4RL>&8=3q&8=3q&8-$Tx4siZ z?PYVTh0U!W08^V=Eo^T62H5{DtQ7O>3M=(J(y7g@7B;tPn2prtRtuY3DXBKMTG-s0 z08edhwbo)&EILnZZndzvmHn(Xw_4cTIvBN8n_DexZe`uo=2i=vTT7uuZEm%&xs^G5 zj&Z`xu5pIroMCMZo(iIL?&DdV>uqk8&h<98s?L2XyK|q;?%ZwJox5EIM4{^3=Tzsq z^q#YJI2`z$VWn0f_ez)EbJokH&jYD;FXV84HL?##jZ5!2>$Q-9TGb`Exz*Yw`P2i! zfP7ub+zJFE(%anX(tFO@lL#TrC>Kuy&3Y@51~MkW&8^nkqF}5`?>Woc-0ISM&f4qX zv7jC8(tFPO*gXLSJ=Uf7oV72?IdqEqBU;Yt+}!#yq}irvj?*;jl@_!LbTsqjV0oKc zZNgELZC%JzTf3(c)Jw(fzBUO_b2Y`cL7Z)ol?h2|**t3go-$0zChC$w>My~O#{ugu zvq3=NeS92u5I474*xbsU;A(TLh0U#JK|(gSTG-r5L~U-hx@~T?u(?(4JLJVN7&WO_ zZEm%&x%C+;;pSEgn_G#f&8-$Tw-QsETPbAMn!sb>!gw*C%3!7V+%taYVRhwHaY;N5_W!&6qVRI|{PHk?r zu(_2Tt~R$?*xV|QP}$sSVRI`nwYk;8=2j|En_I1Jn_DexZl$E!+-hNSD>1dX)xs(l zF}1nX!sb?DYICcF&8@`7!lf5Q;wF1(g&ZwLr@E*~O4MZQ6mcSwUI$^HkmrLOHTlFW z;vC|SlLEj|)0W>11dHiZXJKca;P`f^lBiRmM)zgF zC_4Y8xqym7lPz0XLrun=fbE_5k*HIl=7KK)N6mNf8`{Ql;~i5PtG8xu}XXvLrKsxuWhFD{=r3wiBbRx7zPSV<=M7EKy5#vB8pF@2~ zT{iXxR!*xtmUu5c!qIg;1S-o&=&cBsgHTls&UeVNvWA=9U3piTUM6eRbO0jw> z)=OmddK3ja7py_JdduQLZw5|b1$xUDyk5_E62Hin!18%-eq5r=0Im9M$jpLmK@At+ z7vJaPo@3MZp?Rb4v~$11%7zYb^|A<^0MDHZY8hMLQ6jFz-zYPj@REPx*GDEiAw{$DedzXacQ4Df=5T9qU(@7i^#31D5iC(c7fJ| zC0)vzaQ&>;Mu_|d>_#PmFEr#|3eIa@;wg%gGna{bj_pc*F;;}Wfza$I&L>ksazah@ z0Z(UV+af>Sm{&olf7F}-q)(JpyU)J-Tdi#waDBA_EvkX;%dml3P=S6@;rr^?KxeZ; zn<35$?NixV?xM}cG?WPWPS&bF^ti05+om|uDSc=Q>UY>vAb@<48#kQxoi+V@P)nKH zwb0)8teJ>+ea8Uuo@Q>dJ$=W4&{Y@qH9mUn(W)1K&&n$vYxoWO{?7i$;Wu^(xNVZz zG62jLRA;Y-Q+?D)<4SrO{cmG*3`e<4ErO37o)Ml4 zkVg0xF!=ZRQ!v8+>-iKW7aDLF;2%u>6MNbmN0Kt64SI|Q4o{yhBr&7|$~86MIgTpx z-dv~z-o`CyUO`xSt{N$n!YItE0m(nJVk%(UH2AXV$!QYdOIX`jEt_Sf zha64?*LvE9QS3SoDPw_u;~_;X!72~Qr|RoHq><&n!9#)+yU|1TQ^8Fhaxv4~>>)=} zY_*5n%}j6ckN}Z29`akNzSTqKvW?ez$Uq|NJj7wOZ`Y;SV#l)C?(nL80JBrhT^3wOHhIW=w%ct1)$lfv+dZUQGF3?A8g#`HOc*kv zVw!ml;Mf4>w;@nWM(hL@c%woh983@T;u+0cM~SU0(Y=8ZGGfOvtIY}#?filw+8xdO zBPAxYaUTj4lM&%iF!07H5{72}gAx_2$fJQ=GGf)t|HXhBH0^B4mpo(!#ddnNx{GDr zLD*u>?04^LnLY>IO)XpGfkm~OlO*6 z4;ewE+E6WC!!&(7GKCRjM;eNQ-?z?E^gI zS4=k0L$0ORAP<>Cv3d_#!k%vM5S?u@*h8)((&!<*h%|Y~i%c`bLvCQ(H+u+UOy;zB z$UHVftA~WyD?>eG29aSNvVfHx?NxRYwTPm;}h^AoqOUrTFycGmj{r)L&Z-A9AM-N`6N14kjqd@3^rq?f5gwH`p zH6sByQp$0v}$Gsfw zg|~zUFw1m*Q}SMt0xFb7_ZK6qM4UG3T)am~^g(l?UVwN%c$N7SZ;X0jm@qyn4*`-E z#I*iV0i;Nfpf$A&NU+A0O9wtkNxtXBzAW8Ft>y#%SVP9@S?ka}w_wN(q!WCe!;=_5$1HHF$n z3DRag!h8-EWR&$aRgV^Atn~oJ#t1SVZ+|(#1G&)gC`7>(X1nJD9dw z!4Hz&N5Oxkp1um6%C!9y{378R1z*Ip2Pyb1!u=IInQ3bk{4nL~6#NzS4^Z%C$_x}Z zd5@REBEUqh^m-&Y%2dp@60zJmlboNM47)e791-uewC%@QU52y<7iST9=s3b&{6VO%`Vn zdFW-pre=7NhnOs48eZff)<@3#LF6IYi~o7%kKMDF=7w6FMdYE!n2AKI7@S8~7H1K8 zXfgAU#aToiA`+CvSwtQp;>zMIA`cOXb8!}tho08)ctwUM;D4wNKd<7F3PHw?Jai%Hk{{4-s)?aTbw>h{R=a7LkXDBxP|Hk%x#B z%Hk{{4-qMm#aVl_Am#pvxq!IjEl4U z{C*e2q+b5wEFur>qfTkZ$+?8p;w&N$u_UG}&LZ;Am*A+ySwtSPQ35W`QeEiZ_~GU0 zjhYs?Se#{hsl{1D9;ydT7H1K8h_G6mMdTsL1gbcU)Z#2658Vq1uHPZ@kO*^e7LkWU zmg{$jJVaP6&LZ-V7|^mfi^xMn)Z#2654q5!7H1K8h-uXN9U>3$0F)BVYKA~pWG~3#EFuqefGC~&cvj~=k=40RW_RvW*`51z zcIR%(?%eI!o%@{XTv?n&}URREx8SJjAANlf_v?9{Le!)Z#264@J-{YH=2khp0d;&LZ*<(@d1b zSwtS%07Na$BJ$8tD5zSTwf99ihpNR{L>^)qL>}6Pe{9pN(|ZIZ8_kTfu=x~Wz-Wsw zwzuF{Qpq7d|8eGzmx{q=Eb^n~3W`4rU2Kc2Oh`(5;!jhCFq^1L2B|*)K^_OJyUYey zoaKF8>f@NV{K!KExYN2K4>62tXXGIwU6F^FRafL8x$lq{$6(Z?;;zU;k5UO2XBl~j zNLS<`VqKAk_)P7JJTwm&7H3I(0b*XkyCM%U$ZBWgA$ibrMjldS;~Fa?50Tdud5Fol zI7@0*(3M|I)IZ4&4S=zIP+$ z&>FzjOZf3)4t)$bYVO7_oVS-DDPj%<@pjiO=8*9tYJiwSe}kAD3seaSY1iJGl?3d^ z93tJ*gP228sAnyHw4aGNWN-^GVh%OnpIW;`%%SIi$l5Jp4iQ#sw}?4JM6KN-<`DI& zwOhm-`aKY}c8i!pe+Ht~ZV_|nGax%Ki%86&5F3MRDK^$_*|wAr9Ba4a|KQ_>Cdc+5 z=Fkj~;(pAbNnw=8i#fzT#ISx8KLa8}bk~bHL?n>#Vh%}HyI#y8=79};IZzYdi&yEm z+ZfzPonK#qpC(bGxep8jG9+?87`nUa8X(Q;&?I+PJCK$L{grI@5{k7-nwVxy22GB+ zAyevv8H<@S!js@Z1CaN+J<=Ne6%zfw4De%o+5_*=qm3G<@D)yv-av)f0e%by_=(IgE(9ZfOBJ4C zk?VqUumb76RRPAT#6rNDdt^C~>l4=jG2MY>KyDBu=-y4S8zX$zbKP??KyDT!?mpcU z$m+;Oq)EC@kaJ7oIUt4ZQ84Nvw?_U1q{J&e{GSl@D z-i`3wr`+*X$DPRX?1{gj-$+$6p$HEGs*)T*2f95v@LXM(JQe?MOWxQGQz zv!&$+qBr@XEUk$8@|!8oVt1pyL@LXYX7fV9UcmA+WHGu#vmok#;Me$PFu+e_V}dPc zFu+gb9)ZKb$i1OSP#~iwa$m9tu$EwepUC~Wy@0@GVt}8>W@8{Qi?R~nC-Pw3Ie?=k z`%wb?L>?-=L?|cW*BcGd6QY}d{Y(rOgE3s9CmW1e6fTTT55;3B#oiQ%r+R~&F2dLTAU$bq6m{EWcQ?D{h7z_x9X`V=QVVv0ph?4StRi$iM!7ribbPe$AxSm&oi-pn1!h*_F(53xbU5@-ugi8X`{#ZYxK z(?A?t!a5_4-;F>T1#zX9Voib+CeE3TMPz|1-8$Trv1UQ)r2k_rg0v=P&(>nC0*`f% zV{St;Ec?-#kz@-FGyVk3V!oxLNw~JxFL}F|lki)`4|j;?d^_L-zYxYF3Bp<)zYxZw ziHC`l=kW_+JeGK#*k1LFC#M%*-tdJ`9{OY|!qbYt&_asPgslwB$O-)bT997|3vr5 zU!aeQoZm-9&hMil=l3!2s;-sy@gnDYMb4WNrI$*E^N5zY9QVDRDZ+paWP0MJ!yDhV zAmyECuxNgglcPoX5WWZVke+!K{6OYU7?cpUaGT}*()d@F@M+O86rK)_miZntP9ReZ z{Sf{KdOdHJ(F<%}^X%v>3NPfdHxod^2Jp%WB<~#Ks4THL(HDXBIUEI8RMlr0U~OEV znY__g^%;dMw7*o}htg}$=vwu7W(=o*>f^}>=4jOykQHa`Zea;7GUjEeUKITfSmr1S zXLtacp4oz?K{<{%YwR|^t!4`D_tqI^wt-N&eCWj^zXy6&b^gsHl_HCtk;aObAjD!JP%g!Mpo`MJ&$EG=Hj(cuaKv^ zSXh^WD0hvcS?2-n`xB-U{fr{gE#vchzaHN2X3T+z*_5PhWH{)PntK$bfiroHoOkd~ zeGHL<_yVT?OP6`N__a19{9ccdC9Y=pUriPb!JlZ!obh zz08haW)D&LD_!DG*0iy7U+J~nyj!!CoUc93Cd}nPgrn7NrkZ#3$a1XB9*tb|)t^9D z-D8+hL9XPtn-dQPVf^z#XeRec5C-gp;zxlD#4f$PdUP?;J_h=r=b)%}U$iZK20uiz zAhg0pkM=s`h5k0^^|B|iLmRv|JB4@xVzhBXYvWkVta?g!Y5#tH0PzVd7VvBIOq1*r zEz~2l5P1ga5D6WT*2`!i87se8FhpWU6zM4%cgD&C3x@1u#f$X{T4u(|OyQV@f;(TqbTzw$|8;FZ;4?V&?gF>oql28|=dXf!pKx&9ZJzKJ5 zf&=!Wksd2T9*?sZTXZ>M(jJ4Ip{M_-wGBcqw9Eo9oWQvN#sg?r3ZS`K(|(DB=nS?M zx(a&bwfZUd&s25$MDCk!2vZ&fcmQk@hHP z8cxr|T=CjZ*j)jxzDmz!V4=1rKztGWw)+8m%*153zsPxIEPxLH^d#^lfFlVU05Ai< zh}{52>V5I?LD$;?Y|I0?(*&iXe8R!G;6jMAkqaS{LV6%L3qqqug4i|~KbJyTTOR;7 z5-0(%34k_eEK+oKq$c;W)_@~w+Ll4<4NxKD2L}K*{0T%#-mi!_YjYF2z2PU1{DMz@ zo8&>&(90p%HTjOz2DDiJ4e~)oYH^u<1VK5k*kYbi% za4MLLWEvt5DF(lcLX|$iXN&@43sT(dshSJn4$wFRo>MeMo$CBQBP)?N)@ z1A%$~?+|DM(0C|{@*s4vC_|wKxmd;)8I3P_O!Z83q2I!EfmR@CksiQvqP~wj98JR-+|=!SF4BhA05e%jt5d7@uOCm)p>};51go;1aM#gT-6>!fclJR2ZPO916DFDn|oI zL&aKOPE`p*X%;vv@^2N#GGNfnhPN|)hJ(RsWep+9)RGmmZ$q1X#li*p4DcwxVxyGx(RgmI@ zl!K=a#ut++zSgiBEH-nQVp+yaPRD8A! zrRVtkwZh*G@-S57koN&BSG+)Qht|ST&Izx9Gd4@J$xpaR5;kE%W2d$Z12B%gI|{(D z0A5#u=E~0(*jme2P^W`BXc7SGkz4j<>cER2UtkaYco=RbUA+kQ!i(Sw8t~P8>lldW zC5A4Gm{%SOTZ|v}byK}<1@VX+vjXCni?wI*9l3TN#-AS1tsa=GakD_j5|HJdtpmv+ z3G9}>K;)%@RMxR&6ac>NXf4-4;c%pCxxoik`@mWsSnmTHd|;CYsLb{Plg#4CtUr)n zN%H`>2tX9|LL10DYzCK(spPoCqwshOnBg6avJ#Bwf#_#536GT?~3RQB6PUC zw(n{am|ti0UB~bxdE!OwfZvd>P7{A%g53&!i}0HY-aHiW9)U5oxa@Mo0+MzlreK`i zgianP#o!}&f+*iHh{}IJF^-hPFG=Fw;}FQ_WPEqif1k_m%z>3Nj+7VuKZr#)8tjHm z(8d|)W$5DbVdV_Y$OtXV?!>F~X7FXw+X7$}`e$FKpf+e56NAQt7qAHeti=Nnos<0G zTq@EZ7{pi0iSq9MkeDbF7q@}_u!6bxr9UFDcJx$Ma+YoWfRHd!!Ty+jCWwhNtCjF^ zDDi~J%wyK{df+RFPZNALd+2w-kK6$x9#Qd_?I*;!N~X_~EE3~^OHr;8{Al7*oT~-D zh`1DKh2RKAqqUTvIP3ZWs045yfQG>UIHG?IgCxx!=41#=RZ zTcM&}F=Zm=>zmea5;!k_bM$|3IGHZN?XlETJI`19KVJ*3(HicA6kn^Z&DO%3@IH^R zsT%`Nh)2QTYt{3Lp`lkHGJE#(mMpM7TciGR9Vu4s`VoebCE1D@GsF zN_Z=JWdfHM^)chw%dHcD%Xf=0Q;5Gx{5cM?F{g1?`kCD6*)(@C%=aR@JgPnI~|W=8sZgw-tNc>nAFi5vn-gT>x50!@f(1!~E^*>9uwv$ppJ z{_FPMz<=G|3n$Q-Q1!pq-kZIL+H?K1Rw1eElrbukqX{!~f#L0xc}Vn{JD!7jc=?|SsKkKISv(_%9e-ouc z`OPQyZMN5Y4x4@!l#arGef1fgO5ZCX=Uj-YlD;<}yQJ?8>r(m`QTnJT4YQ;>MQI(B z;%CWL@N?#YHjMSjz2B`D}hs^I`%nTN#`548j`Y)7_b1Fnt zNnhxu^o6XF?hvILs5Hg6ar!1vIu%M+i&CX%3G({? z&q`AZABdp~jM4j0v#Zg`mW@DITQ(h2eW0HvSf-oD4iNtf^1z|RY8Ad3H z45#CNh%@yYxTLzsPrM+^*5I)Lq#lAFb67}KnO+d)a6yz8gxMyD@`5ni1yNoQ<_JNQ z7lb)d5ak77juJ$9L6`>%qP!r?(Snp?aTU1+b@TAxEi41QAk2vlVdVv39uXq4D7lRV zI?7=UG(E`>b><|&=mn7i^v5!AHx4!ctM!A=8AAGydccAs%LZI1!3MMu=0XHNW?)@C|(fe?Se#e8KTZy zpI|UOc195OvbY1-(%N6Cvt&Dy&(+ z^Ou1oi3JNz;~N7))Dd$Fdb0HqqE1Fu!S!fv6CvujuQ*x2^OsG8s3WhipplXYQAez# z;M;w`5Tb5p5VbGl`O79k)G;hnWdYA$HW8wZ(V(gehM}+~&R=G_nt}zyaQ-r}x`Hpz z+$PRnW`6YrzhcSY1@R@)H5KsuWfLLlcp7tS0ncAH5u%QgZ3TnLLx?&ClNwdPL1C^% zI%peP@CYRlqK^GMzTh_IfDm>4P}@BP3yC2_9qayK0ncAH5uz>^T0SXYNIDZC>X^gl z=-e&96XFG7ZVhtJvvls`S)KcY)WVd`eNterbDzrY+^4fUcUyMnZkIG(=RT)8SG*w1 z9S#S+@`5m5D&r&=c zAQ+KvNT$jQ!rYVi32BrUg!xt?ie?#;%Mf+u+oC{uL74AJ8s!CH?sZn6@01sW`LWB_ zKIH{r?u&AURbCM0r!o(mqNO)Lnr&LdaazQB6$#1_fM(`)eBTR#aLi;|OR9&vrxMgl zb%jW-q9h;QY=$iTBo%p*+bBbrt&(aR>H(=jWv;Atj9bUL}^kQawv%%tMfu}D^EB0Ak~ zsbm_JzyX4YR=}f|O+=?7W*6}2WfRfq@NCAN8m1(UUY-OD4iF^%4q{%xQ+H!%$4x}1 zi{gGM;L*$GG+jMo3MQ~@h)$=<##T1r0Kw-^uz*J|n}|-wWG>1`YD$h?HW8ifNh+fQ zgo)^M>^96a#1Ng1eQg%-=w%bp>Ezj3a2{17IvufO0gqlb5uJ`oN($a#Iz*>qAu0=U zSR_QJqhxhKU*4C9PDiY+;5%Z7PDiY%fTn?o=yb%|3bqqNbUI>ifM8wz0QJ%eIa<6B zNn<7{F_W!R%sEJU9R!{ZA2WFxcFg3%vY69{KTcf0G4lrz;W5-Dj7|qXi5{HSOZpQ* zbUHyeKutJ62to%46Vd57x=X(sfoIr!i&dO-lJA*M_k%K?Myby)B>X;J2Q#0DWF_B% z41870$cNGSjpSDn=Vo<%{wVTC0xvuBM68=HaOs^e3wZeqsQ(9$3anz_`)7rG2Ay1i z&!7V;@Kt-|%nE$fUOA&eKLPBitXfahIA-!yrgRT8FPCE0oQN|fK+{+M4)1%anB^H3 zgI^X^G0Xe07+Z2;m{~_Eh3#-na zjuS(%5I92U{moOoouaq7-%dqi#zaVbfRb3XEE&Xz@)}bW*f>~0Y4D3 z*lL1XnzSez%ENmNWa4eB~u$X z6u-)*`8ULA(_k)6003|wS&_K;DE2Tcn>}-ha4?({7 z^)hf`=2iF=yCWgrhk}FS_kkiVQ^7{}F~E3(;lI311Y;)I@_i`SWLyhaX8t6<4+WbG z-UcCN{vN-fAMx{dTv9EB2zy^xp#W0+6QK9(HUl6e`F$w3yoln7o+I&M5Xui821Y(j z=};<6SaWM@p|&7A6-Ye)v{@Lh&Md%%T8Kp>S@JRzPL|*>2iAgrk&h48#24L3$sjRk zZaF=R7cg%zx19RmSCADm!5N%KSj&gGe)s(^yO-o)2@& zX$te9M00Bu{)bowdR0rgke`@aPHXTo(8SzwhJ~0|Ih{Mh1ySaf(Ax14rCl)2@M z5JZ_<&PYL&x#f%!M44O8!Gb7r%NZ?5xt3DqmUDRU6_$bKmNU^ItjsOvh!BxQ1vIyu zqa4;i(+g;BIg%xncx7&F;k%G`411XDnOn}9 z;D?aNhq>k4nk&NjFt?nws%P_IZaKFJtlr3-b)ivIDCU-PyCBhgnp@8L#7JmT=9Y7Z zq)~6=&Rw}<@t`lkiwOkMVs1Gww@56ax#hszl1?t7x#hszx(x3PW)aOTU`b-ZBAQ#k z%80oVwe6n$s(Ft4$Lj`3X5oNIWV_~l@!t3a$s(KjhVc>nC6xP zbL*eLDvM}tIWV`lrL($-=9U9Onp+OcElRc((cE%iZdHLds)**619OW5VQdl2EeGZn`+0oPZOj4Y)}g5F zo+6rC4$Ljq{lg-fTMo>v0nqYE(NjzZbBj69+}a1OGPj(q!IdCN=RTg*xlc$fOzGSw z1@=1ksqD^uI=geXWq0m&N#k|ybEMNtLCE1e}nk}vZfWhl?K=#oJWbWaHJhGiw? zw)ecthx#~XP#RYbjH|;?)U+5^4vecMkSL;Y<-oWiq7~7&a$sCBE3=5kl>_5SZZPD< z!4@;AI4#DN1LJBpmC(3yU|bQ=ifCLpFs_K%MKrD)7+2%Ka*JqOIWVry0S4oW#E&56 z6+A7*l>_7IAlz|9G_D*NSMo$DqH*QGxKd@KLE^x;A}?5U1xpI!ipgkPk(w6c%7Jn9 zHkHx1a$sDslQ6FkgK@>4HH&CmIWVr|Eux6Vl>_67Sh9%5l>_67N=k}oTsbhVScu9Z z8dnaCD@s-u(YSJ8ToJ1);&aS_aYd}Dh{lxzkKf2jNE{Uk!51raMe;icf~7RB92i%e#Y<^iIWVpSp>gHF zxDtfMl>_67V>$U$C03x$h_a!K;*ofIl@=GFgk?>Haa8yutt|-M`sy!{Pewl8?=B;( zca-BTL*HHZEszUfDO8+@9V@wfqq>RMNx<@n9l)z$1?;Rng~Xnj3=G>*_7oGlghpLV zUc+K0*SC7)GT+tq(bKSe4xYaH&v?b|>9i9pJp*;xc>*RC*;T)~mAue2bj}P^NnaCP zj1=R5S77Ps)+D8u0;^g9We?+>`Xq?=l0BwXH-NMR1z#W}njv7&Kt+^cPyUM}O9GroH?Gt!)R&tgrqp z-t1MaX7*&Q?nSxFrL|`cCGTtEVh7F~$6C%k5w(P&HY>ztd>&YzPmqj$&8++adDj06 zYb9j|xKfKYt?yw!n=)o% zd06Y=ux`iO9Z)k6xW4**q|Zo?9bdt^=^a|lJ0tMF+Txw{E|g(A1_W0l*PdbwR~IY; zrT0m|#Tc&cN8VAuRU=flZvcKdaWRIg54{igcHjp|Mtzx40qG?mN|h!mO+-Zj1x4i|DxfqAqN1XpqN1Xr;#!*=Nq>2(EhW#M5rmD7F29)P}#IuxDV; zbci!PcrrB_x_H3k_cQp_u7opGQj;b~`iF#BG0<2yK?-}?aC>TK4fLj}$BGugqg;~F zB6yTTIS+TlkYjuR$LL47Z~DliTxJ|u@o(RcSnca0oMK>GU*9JWVh#s;Tkb!$<$`1N zki~NyC9NL<T`H=-=i(d)h!j zN~j~f%kv&fpZ64kA-7)Pyk`pwQ5%JAYm!#CUg5ll1t!jW2omQ#1c~z=0(I*Z&U+q2 zcHVkbg}>2y_}Gj8szQ(n&U?C8$gR(Nm{}e`aNa|ZIPW1yoc9nU&U*+F=RE|8^B#i4 zc@IJ2yoVq!xb+I>J$w=g&U;8F&U*;t)+?O%um**uW;V; zK6NTT4o@eYIPYQMiSwQ#NJ*Uc{0P8Xuc$8i4LrDy$0DxPs=r6hT3glMy>lq_$(!g&wr#Cgw5Dh$qh2;|l) zocH`nBh*h4;k<`=66ZaCU|zs^Ph%7%w_fqQhfH!&?2{9@w|s6@Ybt) z;AFY=3gMhk0=8)kFA0pJuUsS*%xPnSj++0|6dM zCPLCd>(B#f;=Ct>5nV34;(1RWNT>_1c-})G7hdtahegSSS3K`gT@Gcj`Qd6ke9DDa zJny-iN`mtq0=e*t=RHJn;T6w&u(m@_4bFRR0>UE+nL8k+4VMeAc;0iGYJ>A0HOHt6 zuXx@gwgu-sOp^<*c;3Toyzq)#x$uhTJ@=t&s0*)n-ovnAq=6@R-oseSg;zZ9QM0G| zH6ot(5XpsCJnx|rx$uhTJv2ftyyAHeCFQ~^p7#*Rg;zZ9A(9KPc-}))9uLlYi10|l z7PAZLl@}5hUXha$qIc?W3{p`C<0Zu&0(MG>lVu$aA3;0$Q6(N%pT9#yU3kUw9**nk z!YiKlC=i_YC=i_Yuyv<|+T(#EyB?oR+{r2QmsQmp)7q)p*Q3_%6@5XUFl(zuHV~rj zQY;_M&&@c82zNOaSmqaICPV97#^jpJ@TD2&GR3)uoNkmksX4cib9f*)Uz^GFE50yJ zQFEVV@;NZKq8C8!Jw0GY?$PduSMG7p5yS1@6$yu})PF(>zsrSB)kpXMm&FG%>B?1PP6!F);HCz83HPeUq+Xu*|CN&x-9N@1FB(X((R;T zpuEET^C+5b*Q)?*P-x^hYS+;`ZkfGM|ALtV@Z?f32%ifJmLOP*a%b{^Aa@wG^jHv~)0VjcFt>XShQIoQ>!UC;cRK&%F2iTd+!onr)%E!e3@knyY)CeL zv!eUy@|$Sx87qmv$iJN}D6pbS^vf;%>7bAr9MI*j3&qi#x zv-?2g0=wqJ(3TQ<9G{t6QRbT<{<{?iejjSP>B(@#^gR0gOSl()HyYtjZWcak)~{ax z<$3jg!Jj{KbNLNOyZ*Hhw$9o=!gdEhNBv4==VLvwk9y=ksphaNZLeb{&| zx7E5j6u*J}Zl3LN9Ers57L>tkN%4d9?G?5ft~273I8I$Dl9}-q)On>HXTI$CVdlHi zZcLOHA0d+Mi5kSKD0!8gTne3jd^k(L%FZEb7O%rMgFCZEbKTpt9qA~G%S%(Go6-3qXKP7D$(WLk>mcGzV zV|b^;e`Adn*{K{)XT)D;Z5NB@XUCT_(pTGFSJZZ1{6gAtwVh2gKYogJUt*^+-izap zu)J&Rn!S*=G#=>>v{Xi}W%0{=?X^uw77^2u5rl^9( z{0}ybQgVOd;vZ(GS$|>BFk#@Vo0>id7;6g+_rqQ=f2D2jfqSD1k$MWLsvNwuegbsk zDC_&Xo5=*nKJq+%d5$&6u5nf_33TIn45AaR%>>Bp({kqlO7W)Qlu)pW&iBH#nF7I= z@C$ES=)|l9>qVV+F(i~NiwtK5vp&!ta`nTtnc&zXP)6f5Y-N7HI`Z82UHp*QA{_lY zMB?EEk5|(}1}@qOatMyPR}wM7mM9o6T=i zxCUjSo1ms3NK7-FbkL3a(hH};aV9u+`7u;pwL{{oF*VZ~@uM6KUX7)* zRfOVvN!)xbrpAUyd^Icjdd%Yho@BU9nRqZ}cYu~A*E3&ZFU*IB-rUwjesletn%MID zg!VP|Ie8 z5OX&1VlCeWqd7FT+z+CH#FHQ{Bym58NhIz8aTSR*AZ{XYJ&27UiUM85nRs)@Xw?v( zty+kS;MxdUCisv8ni{- zV%`9fZB)%--cSWpy<*;E)~ij^5~Xed`)HfrME451xZP=1KiSK?8)Y^~t8%?&d4}KAguZeJ7WhSMHtS@L5{I0O)uuy?CdKS= zM`Nnx7NOJ>3a#J4QkB-Du@=<&9!phvkH)&_QeU7|M`MFj`y3&~9F2`r#f)sM{QjvF zW38THbm&JT-;AX(xOK5Z+h#Wd{AR43YBy^C{mobfbGPXwqE)PKDYo1X#WIcltr31C(3*_){14eS<5`nN`2bA z#V-78Y&4f4ZTiw>&&FocfHum1&&IB&Y0|d##iVUj(t>@l2Gnmfxtz`JshFph_lW>L zjbc0EQ0A#vOSZ?K;7FrM4bHr~Vkw-5@qVQA>Ghv$(Ot1l6jk3YX!1Op#YPd$z7RtT zOfuI$SX;Dij5VcbX*J@dYOpbO9&1odhN{KJ*f7>&H5sZV8)H*hlh?o~n*oKZu#H{~ zb)C#%p?N>tXLaH!PA9xs7BljUvIwlB#El|>i#+)AmbchvrOGX%bEcMp4lVKba3H~V z&x|HV*;v*~H9{yg6DFAJ+v5+Nvp&|A)%co5o}q8n$IfGjk|u!hfMmUpac)k=@vcf@ z8rL6HV04Z{AyuJxzFUZr@n<;dfY%B;@iwDQ<|uyf)k2(#HOb=qSuMs`eR0u7gbFXf z0}YL-mPpNGQOcO=m>S#OCu1dtlj>MMHu@G5!BBm(IyRn8UO~nXHj3)l97=pehBCK0 zwu(3NK}D1L*gP3sgt2{B8W`nth^XRb8w(-2gq{p zc2nD91mt(Az$4|}eyBf^%v!PV%sQBtZUS=@l3QL4Vhf4cApT9_Vh{yWKnw#hm_$Di zYe7^{MI~>bIS5p_4TLup#N!~kkaz*aLK1I*_=Lm}5Lwee{1ZeaiJw3`KmyNMMszxy zkp!Z$Ha^AzRn`abF$k!v15xY+l=IF%GdC7pN6TA-dEpEYJ_vjj7jkc+uIU4e@@HsGwY>iR@nkRVIVTzKjK)$6F@PKoMeP)I>9>+y}-0 zq;*ajh#sGyuG_u=XJmdqvEM6YRU%cs;5IXQGLFsTGnWgj8-L* z@_&zKo!e>&a60T4tHpu2Ss`wlgI(r&c36%K{bCgyraHjlqMk@a z4xW9iCG!gvH)4;#8BMlqDGjDYHD(d_&swO^@{%Q+VA4W^5s_?OHNc=deo}LP0 z{S|1|5ZMaVuyG`+p0e5(cHpRZESk)9QsIcc3e-_x9MvC-Hc{ZVUJ9s(+g=<53SXek z6VX(a{Mva6j8;Hh=l8izIZZph&|n?Gm(kjMB5GfXWzaX#bUvow0vL8_a()tysQ)=y zgBsfxD*b;%Yo68rrvT(+Q)bSTnCNO>3eRrEN~K1}{cc4N7Mf8Rkn-wYOI~tC(~RPQFI(S2#oLfi4a;)U_wtmF{jkr?YZE8fzsh}{2j;;~CNP#Q?mn!f(!&W1Dr2@lg zPP*1M3x|->Ubr->87*X#N-rbXT#@79m5gW-t5`Z7Udf0ySJh1kQCatE>6_~!N%Z@s zHb(jJ5b*jt>q`^AE>c7fT!E%66W4W-c9h%+MxVda`O6}zR{tTRGYwl7Q4O)tY%p%? z1I7&z^~eNQ8-3dK2IIzvdTP2J40f005w&UaDATK`a(N`iGJYl_nciL@8uI2~g6E1Z zJr5~-3)fs1aafB%Na>;0jGA!?7)Iau?Jy{Us60nLhw=-~kynh>l&_kRif<<*WbcaD zl--<=)r_B%>^8`@%SW+zh}afU9Wg!^Iu3yUXhO$!v9AOvVxMLV0>kKwJ?!#kAdV;G z?~i1$%-IQf%~(eHs*}*2f-_`XO-N{*-GSgd^`oeA#)tXP&Pe_uqk;TIC> zGz0S#^=*UT=mIoOIC6hP4NN`o)U`j7PF)2Ms@ew;7a~%h{om`HI5{JNHLcQf}`#a*FX0<&3`FI^c>F5VuqDGaM>DjHuD-H>7tS zhg2Eohhri+fo1auPC-T&_M|awu|`1b%uSK(Z;`#_ZZMNE9khH1L_UbJc@XK-$S~eU zaxmE~1n*@Ce14X9{9Ga3eppFjiZj|!N(BTh$1D#ay%;+|CeGDMi636izq&IiGx zVvUV5Y{a9iC?`3^ihL*bSFH(P9+V{(YBcNA1LA~f@^qkxeHZF+BoX3(mx-N*c zQ=_ZLL1ICqQav_x-^UT6zle@$gnL9S;PtElr`-OL4$LzVHS41uUk1wXa|;} zR_q0%iZ|o)0lLSmE2iQ}SQ^(46m8WDq9Y<140zg=V5o6;q)45{#F@Lu$m&yC&V1}d05Q{ z6Boc%ZZLcVTL-Ahe;-yOt~pQ*d`m}MxdlnpwjMo(zr)Qo>}8QWqwE$4 z+**ijOc)@I`s_k34~x2yW*0v56&sy5Xvwou#iHaKA)|kBH&o}oaPkRAKkKk+OQ4-q zyD!|H4R9Td?{hw9^(|pFd%aD@F)qZmgyS40@)v?Jpub`?B4a!l^v0I3+O=QB^ckGp zwuCF$$PSTlgD^&r@ozF3^->aQfl<5|jDJd@iz#t68D(5(Yzf~&#!Fx{o=Y8D!$~yR zUVZ4w#w&$!p)gi0=rgoRN!-PCK#i*rhM@?<;Koq4iWT1-PGQO_q!?9;k+g(KDnf5d zgx*DxG`({eM%7x#?nubKBeJIwvYJtA3H9!T>_-XNcSW`hl0>g&T&QFZK-TpG8$JlP zV_oMYWHsYqC3_6AtrD__!!0QLRzg-Yep9jr#^gIFI~YyeJQ7y3c%5rtT^>^ACbS$4 zt5wFONVz~YP0cW;85R8@DShgba4nWqsw6bP0NkWV+UE06ced5ZmdZJ8v&bmxpe4Wh zi{yW|PYB)!K~6Slg`#pMdxH$xk$-3Fsi$n6mMRme=xSpLUKzzNu|pVFm~!K$6=hMY zvIil{eVvga8=7~^LDj=(rWI*qbe>o&wK!V?<~6&r+q6^rDS8i6b;Dvr7%yS>|Ed@K zIzF6yH=cqfs($oYGwDa;!)5G8D^YmUm28gV!(G`+{!YeJw!-n@fn?NP3dZNc7)!?a zWPHn>HaAwCj%C6T)dU#$J7JP~)r5 zQ;gm}D#oGdRr4?iE(U1)Eqm~kaE9Gnb*7PxPYa{9W=!mJF>RX?z90h``Q|1lSIC>vbTY=fcXZAU>mD=Rvd=Ed&h!EomNFQc)&bl57snTRa0o zU1r1LZq2YOnW8FI@g*y^5=`qx5KBPNLlsP}Tnm&3cI9Re^GG}jViSqyK(t#9;vk3# zBt8VO8wAS80~u>>l>01WPS`0zm|FG(^ElF5b_8Lp0MPp(r>_J<4YP~G`5Z5bz%V+WLJ!gIO;YYf_l)hTl_mFz3aGwVSc5}CWw<6wDs*U2Wmvt*Q#fb40=X)sRc{3v5*R(lvIDjZ zXR;Xc#TGEQD?41va9et_%^h78=+ERfcMF(AP?*m}Xfb*l#0tNm;l<%x1uhk!-t}RP zi^Ii=-;O2~hf7#WVJlXnSo(S4ZdRi>tQ7ZRA1dUos@W>sj7DJV<6#!oHXMJKY2D8U zXctcYh~Qo-Z6}SPeJS=II)rP}KKxT}tT0D#9E;z`ggSL%{T0|M%zqk9eA;`&Rj;i7 zQ5BpQJl_%nquQZ9;;Ivki&tXnRqaq8al3N=8D~T4RN#m^iLYDXY)G969B~(LyV}%e zLr2_I^t3r@K(p`h=Mz^gaE!vY1_6EQ#`)6KfJf|9$4Oxo;4>4ZH z+`$U9FH{@$U$}BGvy!g(!fng6!sY0(=9g|dUroXj%F|4H&s9fWn^3J0V4CaK7NJ^d zTm3z^3GG~lYBg0yUhlabsb?1%>UioscaS=sB10Wdz2{D#gn1Jf>UrTkSIrp(U^G@0 z`amiaTD|!GMSYY(AGl3vP*;d_J_$2kFIMA&lE8q6LxT~R`a-LJ*}e#~pPVp^l0TzE ztIv=-CW1=~qQBND$w#$9Yzj}g>P)Qx^kG?tYEi2g{ghioqsP)lW%N^S1&v-whB{Sy z${oz`?IlCi;wiV9A^H&vsl}diYB4~ar0sDV&{_H@Y>(TDsLu-w+a9+o_46l02ITiu zj6r1J83R*t#gmoT=4(#~`Lr`K>0lknQv zGnjKcHd1>GErCPOW+#PlSke(U!m{zMx7%awfU83{JFQ6$LQzfMVprJgbmvyraxzqV z-|UQ_!`>jnXMfx5%vKvmtH78{+c!Hmkx@m4I-=R^Y-Se!Rxp0=rzG~X^Nj_(D7O)24t%k-Gw0gUf(L$u~W>Up{SzVP> zIWxY_j1M{)Llx@~SmM(iP8vOMY$AhMb~>t` zk0vAO0>x<684}lS2IFT&;1Nf?GVvT4vsmXxoDB`pqK<+wXbIOpn_P2#8Gdi1s0Mzt zpf#2{*!$h@sC9Lx?U1bMiG;&C;T1=1ZB0}OW03H@PB`FHaDcs8C6uRQNGuUm2OTv^ z?p6sykx;<|%tG%tX*A>?Na!3d4>oCr;cHpw%j&2EjdBC8hUq&4$(KU*24=;B>eo(9 zwh{AwK+FnXJ8HA58DQtzA<8FGED7u-$Lew&6g-UL>Axn{G1P%7o^smI;IEMhjSUHJ zBH;pT+MagQD_Q37if!Oh^t3adq8SfB)To+=T4%L`JM-zz-w*+CTOqB_a$#We5D!6Q z9AE@~b4o^{`D_P+#{TZ8J@{7%u^9f{QCl6gAB1?yc@Y2Ism;QgkfA2_-<<+729a?A zOZeSUdmp!hA?xGcos#h=0Y99xu<;)Dq2HaZvlL_R!m6Dx_meirs}?_wtM>f2BQMw9 zj;mHW;fIjEq8D;HZUYw9lMJ;Ma$NPCHW7@9Lr~QN_o{^5F4Yja89eyoB)B8nA_cyy z<*FyGhmcYgNykf_;P?5p5fs;Qm0P~0;>{e#z+g$Ub|5EwtlbSp4!tyKI_H-z@2|B?cQ+LH%Rc2@KYfcn7p> zsg`@=zva@;$}J8VWgEIlQ~g1gw`3pNt7@rg7`+cIwliLK(wmM!D~z(#)krK*QrphF9;Q=~GL4N)Ij0f>EWWL?Ls ze++<|Te~%wHF;-{wY8hetQBAwRcUD9uTi#bFUXE?RZClpqzYfR{SgxXTPcoRA#l04 z5wk|QYTdgxp&Jb9Zu5wkrQsq#Y;hs06f;JO*#>sSJYCEfDP|8vSqBQE99HfwSB*s{ zm{j!(60TqZ8rxm2+Kowm6ngk>ln76y1#Q8DbY>0g(NcQGY|Ktu-CCTCMkB4yT6VRq zZZSuo4PdZmZgW#PAiqk;Q>txlIp+q-kz!hg z(-X8@jIZ3zF0YdCr4BmbngFL77xtpPXKZ&d=4?C?Vb0!$)Mgk<&)6AijXBI{(x49# zez0-%2c9n=h|vpzMIA7?t7~R|u(O%;3F_NXdGrUnm>zAk3sbZ5=nr-$dZZf|jcagn zIc3)=M}Eg%ib=Q6D^+0qBro|dhD^mT$lU|qlK#bR#f_~);Gy!I-I+^O20zbC3!1#y z3we)=aZ9n4O;L0GyGUyK8Y_3)&Y^MNf-lA$w>vO3?eW04Zs3jP!#sK2ti z;sOjmm3Y*z4J+|)`CQYmdYwPWuxh2X1-9v#kp9B%2?$&9I09z4@>O2fj64k=;m;%Z zApNjxSb^v6= z22fjXRh>GqCtCvaQ5Iy!mNHMD6q=J4>q)Vy$g{}PAodDD-^jZFC9!4{J71-Ai~W-+ z{nQmngJO3Q^pEi3hU(bU6dRzbFe%oDV4zBw663YU)&;828L@55Gbq{^d1l8d2rg7& z^YDFXRwacWv^=#J2+K&Bjz6?2!1N>yQ`nSGBjqb_`2R25ok#V>$8_pVSD{J99f9z!u|TLD;$mBSZn?5ik;H)ag8dlC~Mci{Uj@q^@Sveo6o z<6>s{i7@bb6T?XDOK~1@udTjz{62<}%mwhFd7mB4Lt^ohV6erQn{Cxft^p%!9%eIJ zx&IkLyl1=3jctZ`(aZ3E=zf zSPV|P9k|Y+WX!uT`WFm1<}-Gb7Xj5h4(1m~%_g_rzkxzegZLdp0SWF-R+Fd&VhM=? z5Koh64&nrfQV=}g4j;tMiB3jxE+M? z42Vr2nt-VD0*L!za$aqiTwsM>c3|>RFnc1k?jaBhL1Z&I=PRI`pZQ^@;v*Fw_4sqP zA5dds5aXT&(Hg`a5?w%KJO`o=h{+^|fY?o9Jc!Uf5Ys^nAi-ao-9Ul|*Y%$VaT|zl zK;&!!QSV`V40{3A<9A*?vwRQWM=&){y?Pqi6jtnK@|K#cPqPT<5F0_w_Pn1RX+kECbQt7ZCPpTrKIKF)xD| zyU<&6VgU7O;bZOr5P2YOBheJZE)s1)yhDONiu(hJDiF@AAcla*Bry&|ClE$M-siCa zs=t8hdb0uMFntk-_ek(&kNU5HxD7-*5Jsb8aA0WlHU^k4C(^yJ5h;f1+jSzrz^Crr zA;gf!2{1XtaVFlDcJ+k0Se}YRt=BP#%$k59^-oL9A8pCN%JEMtnX|zhz{Z1F zh9Sey7fhdyH~mc0j$lkNHXZ~6+YXitb3YPd6==yY=e_}m$8pP6qukYm>bTId(>gIX z7(NFvTL!T@DOe$Gan16>9KeRz(VL@aXl=nf2FbcjK>P@zFc(BNW$IOe8uTWJDiF7m z7z|=Ni7_CKfXJ^CHOr>}1mPHt)(&qQO~&Ct=499`KLud+x1)1nDC9;kzeTpX3qf>! z3#H8h(KL{&cRSE4VAtCKV%Q-N_k&nUVi$-nNIVC^c^ky*AnKF&07M0ee}I@w;u{bf zN&F1rClVHHtoS>IjFgBNTmgF$M)TY_-4b9^uW1nyu*X$YPK?(y?~^b|3^}Z(X0tvcKrWN;`^S>o<`aq|BtleNUP(W zTP0PR%J**=-}e8JHVyF`_`lO~@tY{BauXBjMs8g5mLzx_aj&r2HZYoXL)zAJ`QatT zH8>eIQEfN&r+E$T?}juCYP$B( z2i}xU=U1bBziFvy--q~HTA~_HiHD@u8O;w-b1SWxv$)dST5DDdjS@>OG+JQM&_*=3 zzHvq62QPS)yh;PzG^kq5yWH?kyT*=R+{p!YY5c`SdE6;WAGflcBdyhs7*N3=8wc+`rp4>9ATRuWgaKE}Go zBqI)+`0F9&r=}XIO}^ow!gkD51GKMxzxp!_={E9>n}RLA6Q&x6{b}P+=m}FQJ#8G^ zcEVJ11KZ6BGp_8yOMxfMEJa=d15TLPiXM;4BmwdifNMTCB|s4Q+>EN2OdzSwpZswU z{=!sayFUriUz#bj)1L(KFL9lZqEY@yGvx`=)tBLiZvJVe>;=GlbgBB}5<5Ax1)r^- zU|6S_uE_;Z3-#;J)1`(js<~X9q08!9+}bc_naRxL_r-JnEVEGP64Kp-ZbN#sqURPF z=4>;(j`DM{Z!p{Rght-kW~$K8Ioqr$H1y0iYYPoMv(36f2=#<(pKcIc>J($oGe8=i8v7-K0Sf{8P2=Pg#VjkR=t$ zdk+j$$dU@RCS-*ysnBSJQ6XC@w15~DvZX?g5TZi1ROn;Cf`%9|*cX*x^ds*4r5n+B+C@fW8RReWLbd^`tnx*43So*43 zt#lke1+{oJgUUNjn}b&@Usc_c@5#NULf3Hy^1bFUOdV&Ct0LBM5-Rt)nio3Gz}G@w zS0jm0x`nphEw*xkR<_=Aj;$Ncv2|m@*87Bl`pr@(28zuwF4t7?Thw@Cv^kI3uL-*t ze0sxO*(!9qP>c%QQdLa)`+Ri)nyytky91WZM17Y~x2{fNY0Q83Z^YJ>+!==}rnw(w$(EBPTTc3(@c(%?`2YM-q!4e@wsPuKL-}7X z(sq7j)smf=NEw)}e`k6yc{2a9o0Ha#zJlrDlL0)K^^2qJ$;>d=yQ1A z#*KO$HMDn}46JEGO*6+T*14W?uFXM8`z-F)X|Fl2v;eDb=1pYDmYh=nouPhN8x>1! z&slQ$o-?NjQohJ)h7^Yv@i{G0n9<=ye9mm4^&RPy!5-gc+r*R{{s1bStw|MNhUbvp zR+D@qG8P{-K&g4fHewNHQ`yYne%e7*Nu#NN5zX11h|!;ARb zxU$yaMSS6ctl>yW#(hWFHAII@uRS4w`L3s__ zvd9Eb?xzj4=#2g`(uVgTKHLFOg2n0kXwU^Q*1#~+ zcY@~*RtOjIMJm938Z1?>TqAV=%3I+Mi<|*Z{5U+FwBh+wGs2~ZLS8+VHZp4APsAHR zFe)z#f0n^tR2NAH;D4<*Ig|-dGdVNE=?X1Yo`t!dQcs zx)dpS?%k1n_?tF*hT-0mu7uNY5udw3BAbSb_}q<(j(B6bLCL1*BxFwVBJ|n43Z$g* zCUEz@8oAWuok7*z%_>i(_xF_mThkk$lG#Q^UkJ!Wd@e5HBU4?(=i(wh)?Y5-b8!*h z<#@Q4i}-*th~y$Zpd2E(h|k4Ee5z%|c@wyci};qqD!GWy#YKEf%TyQfxwwdrNG{@Y zaS`9Ac(Rv^_*`7X_c@SU#OLB7zMp{PB0d)v@iCuV#OLB7J|ek@&&5T2EKe@tb8!*h z8RV0T_*`7XXJK5Ci}+kz#79ZFh|k4Ed^M3K7xB3pkPpF=i}+kz#K$87xA&~auJ`4i}-S(MK0oVaS8cfSPJ`y0%555(B;^SsB_0=!o5E|lKDyNKXmy;lHy zZvmV8TghJoH1kG14R9#Rd)|uDcoVq$jw+`F01fh8Wpfz-TI74G&~k4y%Q;-bL!NG4 zIn=lx)~E~6BaJtKyGN9Qp5BK~Amvk)r@uG$et=^!Y>yg)yy>*y%cO}gbf{+${4<4P z=m_sW@SOXV8V7I@9~N!~eVWB~n#Fo$DaaN8H?KyL{_%zk(#awETIG8FuelV|xz;Ml zdnx$})X)v*=qF1}7trNH-QX_n25$o68 z7x7&N33U;li;MUO-J9Rh)si=eTwPG&-J6ZjFNF5Fz zK|9F;jT0L6nGZpA5ub~T_&Bbsi}+kz#HYX*IuLh*EASPagS)}mx|7wFLvj&cWO54q z<;0;enpqR8G$UgQXy+)(2>NT-pFG|n<|4pP3c#+gRW(My4SjcXe@bFd7J6>1zea$M$bA~=+8 z_oo6EX`E!_yhB{9 zv1jCLnFicSnAWyBJ2SOftD};%MSd8fTyq#GN%prOME{VqFA>0wc=>M{$8%`zc7T5R87q z$aiqEQBoc)5hJ=LjOZSH0vk*@ua8Hj9y(Jl&Zf|DV?701XbE_!#)$RO=|M~Atub1{ zjr4RMjZukRl&{hlE#U!1uCK;u3Ak;S4eGHAYJ*VdO8+7%k|PTjQv^#FT^))1w<`#64`DGb9tfzbt+7GQl2{ZfE3X3O3=H zpNMA(4oM-?oINarB}pN35{1l*e$GO!W~M77Q(`o{QZUll#xHmH&9FRb5+(B!N)|=G zLQ+l++vs9#3EKE5_U5ZK&M|U4cB~~Dqs?DVcU_|~+I%tF>{5-<=J&GZ*J_M5|0vyk zoyKVM-?F^x1-odog>0kC1jjI%WE0<@<1A916T#r=!i(V#i*gG1`nx z`IQ=r6BarSHuLi6330;B2`AhVU4*2Z=4@!UN+t`HzJqOGjmD^CB^%~#8lzH+=!Dxf z4%*lqf+Gm`8cq>w1)IST{5Qd{f{|J6tfNu1OpLlSVbtAG-hY=fh(_F_3xQGJ(X$&g zhEXfV0B_V7Mr|Dqyh-E0sCxxxN}+c-so3GmW64tJ=0u^}qL&~k=RFSI+a(jOjmbI5 z)_=doFk;9!;0H8Db9jVCJ*aUo1U@8~8&jz1R%a;-Wyw`9F=gAJGgyjx?;U}-e+DUE~4;c3AR zdgIsZNPBcTdZR`Cdo@OzyO#DmqcPfCbB?pmYK%5#a9n>*W2y8b&K0Ox9&0X@em+s@ z{n5{AqSDW?ke75ORJx4#WsOm3gAM%^jp6AAG~$59@bn#Y+N&C);C`fZxyujUzqd55W#shZKyXN7Og=+d>9;jTNA6Gj zca1UmG^G4H8e{S);90cJrje{VZ z&^QRf=Nbn=_(J0#2w!R(1mUE{K@k3_aS(*BG!BCBwZ=gZzR@@c!oM^Qg79yRgCKmX zaS(*>G!BCBy~aThe$Y4w!jBpUK{%yx5QNi$br3#ru7RiX7zqi&&xs)X7X2e01mSnB zBnZM8je{WkN8=y}e`p*8;ZKe08U?B+7^Y^_F$z>yFat)GQK0&Q6)-Z50@WGpfKl5h zP`x1(Fycmm>JCo8sAUwW{@@0T45L7Gh;YEDX%wg)5eXRSMuF-Q(ST9IC{TSO7BJFa z7(0a*Fj9>I)hm($Mv76Ox7zJvCiU*2vjRG}9)eaaru#RI?X27Ut6sSQeD`4QjU5!$8 z0!9#=x&b2yPIkZuf>SSG1i{G(7(sAy14a;>ynqn|CqG~W!6^tBL2&8^j377-0!9#= zh5;i8PNRSk1gCMp2!i7Wj379L0V4=blYkKfr>SNzI1NLw4Aa?-0OT=55}oE}qf=x? z+vAX;;3Y1UiUUoE&IAsytpWz3^A<9}LSKy)tQR8$r)5S`087j+64 zh|Y8}ItL6yXCdwA5-<>*pQ)ofU?4h=(;pQ91JNnx1W_3<5S^i{T-Shs=!98Hw}8Ru zP{(-zBZy9S&Ct}3eUT4ITvLNR&FscL92u3|F zIwk}R1Vim3Ow^1JJbMXe;EMwZcy=ybJt<(ov%BcoO9BQw+lr-J8ZhA597;^qj9APl zFu7iyq8TCAD0q{MsX-RUC}>HqObZwxqu@Hu%+mvgZ4}(asdk2D*wSXln$8qdJddss zugpB_l{segetKmo>pWLy#3M_=BDUGfH3J6$1qUAiW1eQXqI$OJyh7E~FRHIRt9pSM zjbou%u$@LO)ETjIEjUeAED9Kiz%W*Halk+XHn5>ytr_*Ctof$X8tU>`pp#oSSOlQo7hi;)mZqSU7Xu8gH7Elw_iKgXRQ|weMBmGPc_Atj!tu|sgVeV}i z9)GkfmYc$FqJ+GKO99%4xd9dNUZ$72g}E`3Km!heUk^4T}FjbiSaW@fozFpP&)(dx`oB z8WVq&Xn>&V_?JWj1x<=iX00y}G$sB7(I7!H;>U?D6f`^Tav?le(7gDq>~li|&5z&1 zw4s6)#~&cNNYK*w3v6G*1TBlNK<$7-*Im<_L2v-lrPqDl^QUbt3*1AIz4TVRnX-@fSJtUn}{( ziL3Uy!VI(VerGgdvy8Br)j)}A+c?z-?cxBt(zMww>vm*&zR66dK;24$n+3!|UOYNB z4~w>Y5EZYstg%Ab*gKkSc$pgNhfgm{a1;y6I9%-2(Mz%v*_rk9POOQAWj!=xFI%T$ zVYviN$E&9?7M5=#3|@}Lc!XPsCw4DaV{9ALMTNaQjj?TT{&3)Yjj>hLp5^OJToYSW z!)bo7iHk?TQtA&jaq$S4H3qn$&W}gHTQDi>l+$r{2>2x@m zJH=jWjq&twjQUD6#?!-Ai~(L7jq&tg6SvhEPY;|NymlJn=^=y`<&|ozcbdKS8sq7q zH~PBQL1VqE<#iNn;c0<8%U+pIM^L%5>~+!@LFG=h*I8rF$h~}q;dRjvF-<}f^vX3x zOuuAxD>Oz-dtiw7DmB)-`CeDSVexr$=Q}tykB%3gpC>+VM1Q04_Kfx`fa5tkd%Ywl z_j?|}(B$qtP3rvEJSFE)<-K>UCjs2Mcyl=%W~_y&-~4DRhAIDGO!EQs_mA zLPtc~*GHk;NB2fbChmrEAKe?JF+#|FbZ@lAdb`aVBRGsgxo_@`6|4&#?hJzFJeDkl zj@LeBf$;If=&cQc#(lBmESY<_!F zbvha^H^04U8l&+(#U4FfV>I5091--EtQj<3y(Jq#&AGYl1zWOubK9Gx^XtuRZ??u5 zF}S(y&CytIZhLbz)|=bj@McQL`vruG;_=q7B>>y`Gx08IzkOXDo=}D#3Blw9?r`O(PSU zZb_JTTl656e84*0{$EP&_=}P?&X-g|O=8a95=z!b^BX}4??dtKl1!}Q*fGF&3ug4W z&FtNyu~>GeQ-+**)GSIjCX{ZD{zRqRJNLFoCT^B;@7&v}F@_a2jBL{whMdO7}T68lzIInN;f0M5UgH?m<${GvkoyNv#BxTFF9oYm7>rW+6{$j7r_jVM=eN znyAzm_Pby+6_w&~s26OeqEav8@xpsX=SQV}fy|fU8CUY43R2PCmYZD*S7=?~zoBW5y2+!Nqz`+hCJW+??2zD?Lo zf9Q#ywPo-WPj9_n1Y=Fc-f-H)2 zAfDWL=Hw-I1Yr#ioxH@3AfDWL>f|MM1ohsD7wib)@rE_eGMztII4zLE^UoIE$c#=$ zdnlO6_$IdSPWbnk3frJ8R8_W^_EQ;dYZZIM4)Z)aWuqGdR2;=7UUUF*Q-0Xu9aErV(cJ zA!^#f5RcRu+40q?VU%X%h^FDD^BOf#ooE_!R#TxB{h6BhnC~^QWatUDrM#w^5fV+l z5D)nPsnWT+i0Z+@6h1(|Bc%3B)dYBpQ#Sa~bLTr}o+fghhnC^?KNhD;3Im2v= zb3e{YF~gh&9*lEC&dW5z9G7>-xg+Nlm|+f-yW(TGz^E^~I=kaP6EzUDH=fO5s-+p` zsJ1VDlEXv?Gt5zCe|#*5_w&p!d-Z|%9UQLun_>2GtBmXBtC8$5MHQc8$K5QbP~`wvE@X3EbA~{knBZy)q=i>oAlQNLEptw z=$46sPQ}|X?P5W{#A~y>NrKM!LpUy9BFHfP%Lp$O7&85>gm@#9yIK*`pUnvauVfM? znf@U{ypu_oX8KQZT{cZ%hUx#v)ae23G+<<7$IKFBy3>% zKNI53OhVuE2eP5!)l9->rhhHr9Dzlqzk^|zE3m}$Z(-`?0!vMQ3d1>1V43OPMRM0lgXrKbNP;c|h?O#eDIjTHh{nEnQ)t`xY+^!GFM zCV^{A|0BYi1+Im!rU0%IxZd>p(TvpsH<-T1PJ4^M``~B7TLo@2{VjxR1U_i`pA+6D zaHr}2L3q2sT~Ngyd56H=razx>t-!soituj&_n{FIt`oT5^pCPl-YM_^+9ZdF^#TvV z?Syv;JY@RWY|nQKeAo0_6W$~6u<1`E+#v9X>A%3Xu~FbL)Bh(^Hwipp`WA=Xdj+0E zj0o=&_>JkGCfqFWJJU~LK(`1yW%~IX{I&}G1wE8-o4_-se=%Fmc7cZF&nCQIV94@U z5k4R=V)?t++8-2{WcfFo4|z$r*2d`aL8%m111Wr4FTKg8+v z6@l|C|3<YD=BSpGAFZwXv$`DvWk4+&fkx3ihOEpUV7pCSCa!22ve%DL_xf!i$qBf@tDJ_tW^ zKz>i)PRsunTiyEtcUgWuQ$G;6+wwOO9u~OQ^7jyaC~%+Uzeo6y!2M7~__4qPmcN&4 z@*@HdTK-(t=%~O$mfw`+ej@N)%O6MhsldaQe~j>$z$2Dl%#r^e0*_h#vmCyT3p`=@ zy_x!%z>}8$1mOvR-=J*}elGAkv<<>91fD|l3BMHhi{)2yNpJl&OZejwjW~K z_)1{N_G=J+EihvH`#2JQBQOc6jQ+m_rrCZW;lBlD*nUH<0lpQOY5T+3a=sIoZTsI) z_v;EhYdRkzS?SDY{lfV+&&*dokv%pf@Z_Re~ zi@-A5PvuzmtH5&GpTyMP1a`Ci^@P6*>}mTQScNkJt89M>;eQ17hcMwE0teatUcx^G z4z>Mj*i;NltrVJ39PpLHwkTllWcz?{TvcF#r9VcIs#|d{uqvR zuE5#0{}@xl0_WL&e|EZv!1=cSEW;fYxY+jJA&d!JYWufS*b}(S_M6dlNdi~c{$j#p zfvar44p#*!0@v97cBZBZTxGn*4du_iljm#3b&-ObL))Bbh_QMQH zU4aK|zY+Uyw!nk7zn{YO1Rk>e&j@n_zKgu42Mr5OzcerNl0nA%9-DcfH`*jV5%5bg@t!V2@z@QiIV z;!|HJpS`%HW%DU7<7a%-UBRiR$ciga#U4^DzQ` z4mC9JRiB)c>Q1<8XAlBvGutInBEbTp4>tK%UgiTC%06<_8zDJC{n#5fKsI`j;|%n12Z|KzJ9b5?IgLqP2+>A3`(i!j7pq6)`2r6VX=?w$zCSPD~4>f6zd`^>_!N=uy`st zUn5@5XXovI16W?89YD5sGlrn#o0EnB`-DQUdAYZN0Z)xSgH2}hSB6FYMcQm^KM2kllLa2BOc}6Myh_k zMlnD)uLV4j{IaS-PkbX6RgHy`$49537T!S`RNa&`h!8#FjHcR&_7KpS_2K-RL1gg* z0<-ZaIkY%PdN@eRB88MQkWUWX8Kl3JNGF99K5-?7_5jqOO9QnZlR>vChWbT1hqC^TQd_B{8Crp8CpgQ!qWV;B(Dy@O)PDsjR7KY-i404WSN;3mj zs3lTpwB%OxA%x)N6r_I`Gf|!&dx`PnT1#GJ<-JvW!4XkXV24&lhctfaAwq+cK%2p!=q7fo>18sZQsbcCJ z@ERkv_!1BuDAw*Hh?L4NRG0D=XWVyk^-Scr*ByuyEJ9%1O&F)eZ}*ncxW35Q{E?d} z)tjAYDKW=<>)zpPw3~@bJz{l1^~=Cw{bptTm%y#)*}*7cDDB%E{}lF>(6dIXlz#XY zHd1CVWsBpY^x{JBenYn6Y!E3QLagX>2rq+}s{U4|ImHa5<|DQEMDqm*6KghL_^z9rYvK9qI3L+*J&B z%|bi1*12_DrsN!nXBC3&7s<^rbt9UK2RPk0-#Vx?9 zid3Phcx(JU7RxF=#bQ+zk0Di6agB2(sNzASswy5+VvKqysN!u-eHfyu_#?$wMfYQB zyA#!MAr=F$Zg=>b7{%Mb%VKIr6|1w2o>45A2*DfO1F#?t5p(^Ai7MXMmQiemoKmF~ zs!Dxq_cGxY`VW+@}+iog1~*~lRfoUew4 zK}emg3>nlj@b!E(YF&ri();FDaBkU3ta{)4f%N@5#Lq9GrfT9-z+(79Wq7S4SQ*^F zL1>X0d{s|mafhR$W_c(bYM zZ4mcTuGJmrp|?ZKr`S>_k7DVNC6-ZUio#K@BLMokm zB~q1x*N~utw}Ma(4#X1LsVZDUC|1O9HG=z9Z=CDAMKOl! zQl@sk5ehyB3*oY^!RJU^9cFYn1uh5TUv1u_vmTyf2?ygoAGl9!LKt0NO&tQg{&EN(Z zOlYtQcZc|C2&l%e0pdoh{)o+2NIj5=EPb7ZeULg2yvLAQJQ>6*Bu0Vw7KBkW1Ys!1 zFv}YNSpB0HQ+^S6);~bZ1Q91Ofx!Y%5r|fxOlt>NTq2U-y92ngkXy_ei7!_z( z1fna&bnZzgpHo&(W%)}|{F%U*8w#T^;`-O!Jc7CK7+vCd=V|)BU ziLs%rhgcdL+EAwsqNy6%uN33BkbIol*lh2Im`|~boC=Du+2$ctHQN%3b*qbZ^(@4C zQf!!0TmsyKB0h*aL3CwGWjTKqJeE0G_ECm(Kyt? zvTCxX`=sl~%UOi*Iqz!A4Y zEJU&9&M1n7kvflJzaeoY#k%FA)Vm?JlV!DZipzj$VsT3l8z_PWIM?0nuO0`99Jf1! zIh^39u^=IS$Z1bMJO=6JwWuejTTwaMFR&W(&PSHT3goyu*%1!_yuhhbLf)=kNo*?4!1E5u4Jla&Njm^m|%txF3DAgET!3y<; zAkHGm>#a3%p+uI_I8;gPZB|kJaQdy7ea$@eYaxTL!H6(BLImfli0D|~mX6w%!8vom zSPDiCN?|Om&sZ8T-hC1n^TC*lkt&S&x|PRPtE?*Kpey+ZJ7P7>Ihe6IC5~1de^7Pg zpsQ5Ics@k;q<@b2OCH}gH%3gJ2Jl73=F^&#_@X!4)8oF07is*Bd}t53V#ODY?`cWyf8(gIaMmKUcEd68@qSM zQXwW!P$mb)9`kEmUF5lLLik5>eDiVgfQPI7h$FG0n~O3wpOK`i79FLA10KfBMI$)? zj1ld*h|I~@e991}IcjDaBl>e(PtMr9^_QH2;)L4I6PLU%}AH_$ozTC zksqS5ba+h(c&UFGCy2oL_xoYVJB`+mJsG;;X%uEqsc@bwM2sgDF3k)?w#^t);qpv1 z(&0~$4k1P-%h?Q@8EKz5foX=#j4YBg!)8V5sBk3l!x-cc5opqp+V1tjRETd9Bq-E{jZ zAVD|XehNs?O}D=S5_HoYpnwG3bdOR%f^ND46{rom>5f#va#hexca(?Y2-xs0zTDAK z0tve59_z6Nh6LSok5`C6H%|aH$>wEu1VK05@$NC8NjpwRGc7?k-H8!aQi5)}lcM90 zBSAOa$t4Q_7<7~3+}ZfzN6XC#%?CixO}3W=-E_}%uK`U3-E_}NF)cwi-KC-gqBwRW z=%#zEo5kp2Tt;_uS}`-|rhA?AEaNh|*Q>Ovf^NE7)X%3$&`tLS1tjREyEU~Kx+LhP zd!s5NaT(p4(`RDjAn4`|V344jE`n~7sDf^~2)d~{Iok@hxCpxWnuFHJb`_K%lAxQ& zYeFPJH(dnXWVxgYy6Gb5=0})|5_Ho=&`st^&`lRXH;E+Zrh9>z?T+a$K{s6l-K+$X zpqnm&ZlZ^E&`lRXH(5@CZn_A%NhCoxT?E~vJ_)+%BIxE=l#`&FE`n}O0+OJc80Csn zf^ND9x;YUZvws*LX3 zozl4~=%)KTyjjt%D(I&BV$qM#Es*=c?E+TKLc?Vq_gE=7zmdKkf zB5xMEC{_)*E+TIdNaRfykvEAX@}`T(o4htjo9;=1B=V+<$eR=*kvCmL-lP!{dDC4eoDzA{Jz0=M-gHk9 zB#}4WQw2%nO?Q!?!G_CWa|FbzR;Z18WN0? zMJjWe`d*5XD)Od_$eUc;Rpd<9lsNN4urt8f7c-5dRZG|ory?H0k*hMulnD~Fb?8)_tOiSF&BDXan^V7(;ir-5q z=5QXEXW1L;G0#ctBl8U87{$L~OWrDO4Ed1!V;ao!?Z@gdFHA&YVB;@Z8O2sZFdKFs zfY_<_SM}HyC#Ha{=|~u`qD9j+x!@kwbRMJ{o0<-Q3ge?@cfxw(DHD-Vs2H)an@wVd z>ln?>U=|{n8TK`_V40nUu%J0sB-Yb{W64~67DSrG529&c$7qy@t+G$5$Gkf62$?_6 zkojpSGK;sehWPbWv`1{MeHF63Ol(~=%}T7Ix(gFblV8{`US1ZMf1hBWZ9xPi+95F6jh%Iz^5(l*4wMWN<}k74-6PfT$237;_n^gd>zZYUaFbu>Vwne9W+kU4N_ z;e^ohBB!xsPKSu%zC+j~n+LH;J{X9~6@QF0ekk+6NEGT~4LliKrQ3%iG((%5S(bY; zEYEfTW6m54Z^J-hHVP3yS)x$(8bQs7-0Y2l+7iXHy+$d{3Zi6okD$Ipnd}Pcn_~?n z%F9LuD|8G|VfI{+GL5Jt`!b9H=ZQq6+0%w9w1mjdUL}^D^E1pW%O32Hyt!7xFMzsb zPd*0dM9aGfM)%D61AyjPnFxk*WsBR60>ZBWWr0dsw>XNdCs{=;0ZUsOEw9VTInIjS z!n*UQIA^RCCoo!U8UZxUia!igVz!8&?EpKxL>M*PTo}cyR&4rW+_^UcftiYcUxQSH zy#b*Qeg*hCN<6``+0bEcG{7_~mz8t*MQelWF^kdO08<$aRv4m*y8D&A;7!a?ARb$P z1i)MclCdc;K5?P~8N=QHwTXH5m0-8eN3|34vs7b$K{d-#d}gs)do-YRndzVn!QEE00zvAa|1%AzX8Fe6}C7BI*i8k-Nspx%kIi`FXE z4FT&dwX7CQmrJKTAL~luoTB>_>mvc{8;7&1MzVXOO%tn%_AA!U0@j0M<=vrSKZpe+ zac+?bzMPPQZ&iiHNT@1EJ-mvqVs*X3#Ou)kfU$*}k@ZH=AE+1JbEKj-bC{7AyPAdG zQdMnixNMj)pzGOVKMg5~x9x@?6)wOko_Mc>zm0<*NW^zrBi}R{#KPN`CFv?H3))k=b4>1ZE21aUr~4OXy~lDMg4hi-F_3+8EN3 z&MC-umg3f>LBkxS)Goq~QiD931q;8%eN2ObA{J;c|8H0(k}H$rc{%&{sj&4Nmp^)f z*I$q&C$)%~TUeV~Ar_Mrlh#y2RE`>f|FtsHjdCBIFcLTTM7;QN#`;>)K2{GdQ6_8e>a z&s^r<=7l*wDiDvo&YYhVNXGD+eMa)20$6|}%=+2NLUe;qSncF*$tS31AFcj9O=<8F zpf!IepgZf30&c7|&H0Z4aU5DBq}gnW`zvZRgWR527a*- z#;-FQ$;PI24&|K0hDjEg$#f&gIg2HW@zW@5&g}1O^b$d#?A#?l@DXR8n?1-u*-Q{> zKY_M2H?5Z_(+3D8TbRk7wK7|2nfT=b3iVB^7awBG}?4JDSPcSx#BqS!>9)gUn=wAe8%tLXR-5l`OXlz)j)@$3?L~dv%_P?el)H&F>S0~u&OFG$-o;V_#fYMZi?Xv<_XLFFacZA4XO&UB#C z7B>)8n+1FxC|!Xo9v3t+8o@N;acDW-i7s?(r3?ySe9a^3sEp)QE2Y>a8V zzTW|n+Zx55WkwPQjHx{DEu`}d_hDp{9NeE0GfQFI8?)m-3vi#{&NJO9(W?Nx{WdOk zM)7O7DKU#%;96}J=fGaO`0`u~m*U&;9WH(kogXQF5^1OSEquGhU*S7id>XF&Uhzk` zoroFj@)kqHMYhRpfxC;%%J!(OSyR*)FEAKb!;#gJpu=Y%B+pQUj?FHFX18D!yQ%6;v&&h%BURO=*_EtX_ZSP#u(P~N z?tTcv%$#XAr-1HDvGAC)?40ibdYm*JzkoU0Zge)ft%v%7+)N#7Z4=et0;5I-cKBtaEH}EwF^A1z zx>{q9A=MgYcdo0}FuOOa)vbzMINa_`HmS+ccB}CKy_A-Tws~h0vl5y(*mFX>u(un* zA!3XC`9)@Bxd~kJLs2k9Y*F+(x=n_NEy_B74uVn`vMZ=?E(je}^F{2=EPp)-s;-W$ zt}9Q2Q2rh3>)L9Y!<^G`Fx5xx2AmL|A|JkAre~-5(Dp0Yr=N-Zm>s_e`PRn4Nv(wqAD(BH`n9@;oMh{y(5BC9E#ihtSSB)zEwk6(1 zt7&T(AEN%%sEXOt4sS!TJ`aJo4D5aGK%xc-mEHFlpihDNzKTTh3lul{^@hNW5cnR- zaagZbL-l-oPlVk^sQ2KGFsszyt>%x`SIj%i1oEwgARI)YTe{whW!BthshMkzX%ck% zKC5G0x9_uh)^+6cw9inGD3d#uEA$q<9K^CDMqN(YZ7!YcrCWJEuXW@F7H6qwdfF|-F<9@yTyR@pf*zmTwQCx-Bu|px(&s}fV-^@tmq3Mh=O~q zW@JAILYFO&a4Y4)Rfg3o;|Sg=(nle$w~{`xB&gn2sb0ZXf%L6Xy`xBYlnuF6s<#jX zQFoKol;y7mp|S+yaljWq<}FsZ%Va1B19X`hBxVMQxj|xnkT@ksEYS(t%=@IHE~d?E z#pXSY@%EMhT$61Y*u2(i&K9|+*5XWo=wxHD?(J;~i_)D_O0%TG-pQ!sc47>t@_st3u7V zJ5B@diB@~X##?8Ap_~jN`6R352OxG=i{E^iezF9gVVSq1y`l4_JZk1Wd)L%b2*Y&~0X1&G! z5>YF4+797^cqfBb4|xl?AGcEctzt~|HaI9(gJeb?Et`UQI`|N;IWv4N-B%E+fjy%y z$MsI&AzyF`%}TJWy>Zp@AtSkX&B^0Pwl{vVY$$&l(45y@8#j5o$4A9Zlo~?pl|Edi375 z*kA$)MGSLwv`ZH0`?1V-A@M0D%8}q5snKN}#2te|T{Z-XOM}D}L82x|To)v^>V(nh z=VoF~o0h?%xWLTm@*AihQR<-}VKvv3NRaS?L?TF}b;9W6BZawWtb^2!6FAz>G_z%B z;%47LXc=-}hV}irAn`sDGr-0hmFN?=dC{~p>S$dCf_8xQ9*P7T0B@}$1$oA|wHnSA z4M$MJ800DqlaZi?=jx>Oo2hB<*U`Gn2Tf^Mg2X{;7+HvAZ8oZZ1;&v1eNnqsxc3?i z+F&T?(*udgOteR05fX~6?{Prq0ikX#n%JyBAEO-V#!-p~2D6+uSMG453-%OLr}k@u zL>!Dug)waJ-1F9BAvB&$(Mj{XFR|>o3mKgn3fz|@FJL=Ky1g#Tj zyEN?#brX0FZvxG7qu&l)WPiOP5!ALC-DdgH9jXW?0m^Vz8T|^t@ekCo^e;KufMX6g zhW`bJ+Bxf2K_lpS-%d23oyj`pl7BE zhaMRg){%azkTo8KSN+ez`_TiJg5ww5*KhtahtY2;(t+0yskt9}=jIJSB4VRQn0Ta3jHO)tnH|O9#1}JFTNzFd-_iWbMa) zvt}KZx4~<1(`2?TW=;(zj4aY^)gt{U@DQ~um#JkLj#Qh6stZIrb?F+a7V!3J0UxH8 z>kex9{gQIja$T;l_dW23w4h_+PUsl{EEkSW3EBW>6gA2Bz_LnS42C2Xk@c(0-a9f0B$hmgbJLOmO&Q)W-y>U>UAtsXOuZN|%16LmE=dHoop z8mvhxUQx#^UBS!>-X#xJ*ZmT8h;STs3!18?GLGMfF=Y*EY>(y4%jBE<^)&R={4%t| z&mdjF2C;EJ@D&qDB%1wz*Q<+=7}o}0g(t9JOBAeTQ{oOnF--)MDz=FU3fhf?;_1t> z&Oaf9<;Qo$SC?fdKOJ?&-&juY)xe)9Lmq91^2ByfBXoCTQF~xV4T}F&H#HaB3bD9m~~l zF31A_%$h#!p|1l-r$TU_o=7~%#1JGtL1OgrNK9sti%}%aBDl3x+2NmcftE~A#2_RF z27G;4ayBUAryV8GLtWpAYsEIBW!k0`?X7_)gJ;>9SVwM4orl`IY^deAS3i}d?@uQGXBY7&Msug;?6^_$3 zj^sbUqDErl-yo3LY9vkvQhQ7nA%PZNhqBxX#ot(7@2>^M{S<1sjgrm+=~Zw}T!RE! z_%i;RIB^UAO&a}o{2R9eU&+ZVyB%fK7{eoP9~OxH8zRWtgb9}I$OMHBKw@A}pf3f@ z0A)0Vjeh}Ow1;;2CxWOLY$e9z>{n~9H8)JD*wXo+lPnDU` z5oMyd5br@|pDYsI??^O9q6-qE%aIt@3txpNuwViOyP>7HOQx8{lAFa&XM%#ZBB6Nt zvg|WJqgj6ZP<(ZnjPk*<$IJA!*pBO|4EYBQNrUtyO7tm4qQf6Zlp!$ziP1+Qq2}ph zC=$%mQJltVQZFSl=jb&^3=DYG9DNKFnWImkXfQ{4C-5HdJ4!qE#ryOC=^vCc7zzIn z62~D?g~aHoNQ_>Ptn za!d@LZAX7EFes>*ZGF!&^HOjkcV5O;g{;`ZkHB44?Gtk*Y)!(C}&aN~HQI_3sJ&!LN-*jM4IvACr1lh~fF8V+WD65G;M{@*b8@JZa2t~z-M zPJ!@A+?}rS`a=~ysm772H2(9GDvDIK$A5lOg%RT*Ob!`OAA@i6Qw;2Qk7by2P+naG zguk}?4tHF#{+Hv@|8Q2aM&?(e`2WFKslJ1ftsRu;lw_A@#y~=?Qxa-xD5s=w`@{&Q z>68>+BxyP&g)eEe81zUee4~vEwV|An!Z*jaFil^L@V17e%X{Nt6BkM)6HZCtEz#D% z$|)(l)u9-1N($c+ejRD;loYP? z`JB*M_^xw4a+)`u1A;goITh|_0Lp2`>C%vC<$UCHRc49vk<&Fs8^!s^>6#%B=Od?U zV*=%T8v=y9>W`RMRj~qB3k*J)H95^4TPFBuG4xEoRIcN>#d<2vs66YhJ zCPdJK62oE#5{36a^QSKB+f?;oR1EK62oEL?q5f4xEpuPn?e&I3G1eIdML6;C$2+NSu!x zI3JNyoR1thA9X^WI3GFJnGHD*#QDg9^AY=5oR1thAB{zA#repA^AYPV&PNWMk9tFj zI3GE1KB5LXAMJxQaXxY$cFzM*b?zheI(LVvg>pV}9#v`Gx%Hioochj3&J*=J_eoVo zckWK(|pz|UqOxlH1lo93Y?Fa&Iz%tRjKz6 zFQuR^bvLpyB;dtJOd|9}NvKE-rLF za^QS405uTjBL~h$8^EEQj~qB35s34V1Lq^E66Yfa&PQtAK^MnhPKbiV`N)Cu(LX4J z&PNWMj|jy1$bs__kvJbYa6TG{EO9<^;CwV62(LMk_#@b~;o^Mc!1<^gsL5!kDenNosXjH3P{KM zYP{Ep!ucrI`#(7!Md5sO044FdJxh8M6GKq&|F`pzH^puSrl82Q#1aYC*4mSi?Pa`m(YKIL&PU#b38uyQ$Xl;~I3IZzDIm^A-iE|l zaEbGgw=tJ`=zK(?az64dwl4rJu;j`_E*|~=FV08aX8QmNdfmM1qj#W;az665WZ9zP zeB|Ab<&Y5PBX4V#T_Vm$-i=vyrZ^vYH)S~t#QDg(Im>nv=Ob@hb}fX7^O1K;b}w?o z`N+F1OFPB+$h$qul|VZmd3V@Nk)@oEJUAcGww%x|e2eo@?8F3DA6?;iRpK{f{gszU ze470(vc0_cjOb)MYbr01_{@ZweacHDK1%`d5{b`NK)giaa}*FSk@#E%#7hMJPZXfN zMB?-82t+F{k@);9)hI8K__7plE|r%^e0kA&&~rkU;=7a*`=k~lZo zA35SBl2{$%5Yk>EiSw*;DNXq>B;HNtrXYYm42k!(H2N?k_G)Q-&pz>i0^-Av_)r1u z!;si#y$)&m!kMTv6a69YuU_;{;6?AI$d?zr6L``46(IGZcLFbZtEr-1^iJSKZ)LN3 zsXBody@}+d>I7c&CX$z`6L`^^NM7`Y2e(4Q$1$ytg3L+E`hp-X1B+9zgasu$QUB$0qs2hltfdWpU$gfm3+LrL8)UEK#@o z_Qorgm#G8ErV5uLzf8R^(oEt0#Oi&L<_e#|^6LGOQZ=*fjWx^LsrN@(#96Ve`nayeM!70)c*b!@&ZS%hIsx_nJ?xuvpF(5JdDiW0Lq_2!pWkuz|~RSv?zaG)7sS0 zI=l>827Db}LxLU`M*DY=;xWjzwF+KS3c66iUSui-pCCa6r_~87|5DQ~sH1iG9yF!k zS0vg|K{T8ISe++hh4O5+A3sIf}Q{V$DO zjq)0B@$I=~TKXB#%U5|}5ni<@--B#Aom^Qzn`6T${{&eZkoEANvsjspl}7nL!Eg;2 z-v28G1I>6V7=HgNh6ETM07Da0mCd1yqjspUH*SRy1>o2TjwAofVU+vGdKFm{{+y)> z*Pw70aC``kzx_{+ZOe@gtHGff^ExEhm~N3r?cIoSO6u=(AYFCOxf zSOdV9?D$En1mKH){3Ol>;9G?JB+dcgJEi<2&II6_!~7)H0`PrleiG{d_&Co`;!=QM zlikB6yKy-hB4lhl4&Soz{fFN8{$6irke{O;^N|#+P zN*6Z7t065cA+bVw_nBd^LJ|h+@ZIOg2GmGLjtE7tJ{rzLpcqcs3akKztHNJ|yCe&d z6J_{|aMyS%UUUtQ|6+GC84odAJ%NV1*%Xq~4qpj|zX*44G!*H0=tz7w5KZA;i4%dG zi*b=LoD;xhg5hM4yruXOC%WY2NODIywFX?Rj2vdgLpR_%XCuD!PESq^(g{AqhSwF4 zJ*{=%A@(D{hK!)$s0bR4ilE`B2pWz=(8w@?Mi>vV_kvYh7nzvIg<+10py8+p8jgyf z;na(u5t(9tTd&BpL_Zc$53!DlpyAYupb?p6H$`?Je@(q;&5joX9s~+3p#1BBZ5jSgu6S$mQZ;e3T6$Xk>#38rezA zKm?8K;Sn?<%j_-nM6XCR;pU2ppy8+p8cw|k8j)4@AN815Cx($(J;XXHf`+pdT66@B z$XdG%vKwV0>!Mqbh%$mk&XBOBB;JsxEQjmXAa z>PcciY(i1>5F5GJ=2=D1%2y^n0&-LY4M#=La8v{h=XwaUoq7>8BAe}d!P=->rRy(1>iwvPF&Po4D7G+>qsv2t|LTiCeSm5;w{S8j%~b?96zS5i}w(iJj7ZRuO$D=mdhDC7n#Sy zdb8#cu$DA{USt(>j10joQ`4_V*kk3eL9LAonq2{YayG}s`D}c{scZp6-b9fPh{$-E zS=mpC^!U_&3|azNEeS4z$dVU?(2Y9Y2BEYW3KZdv5i%K$k_!*JteBT1^L7zB4tmiu zuyZAas@vq-tvt#|*${dL?Zoe)Z2?aw5{3z(Ck;OqgckRZaHpl-AX@}NvucQ>Fi|@m z3g@sEJ*@CblzACOtwjTwHHzqdu;X_#-;d<+57 z1?5%=+oTX@uq8`bfpV*yUC;}JW+5~oS!)}(bw@U^ZAI2X)G10-AM9tcac!$H1x-dd zXPDlgf?Wl7)7?@M!<9}_b6=fwjBXtWwR|HcfrFF8z}k&9xBLtD~Mn*%rYyw z2#I#&eUK*IU61{2a47b7K*YQ-%u=hcCSczU_V#-8i`6;6RVK%xm5ip86BPn{QxG9 zQGV@ZUt@aFgyYNdHp9;si2*b4R1?PI1|dW_;jl(|`I@N1jk1-W^U zTT)87o6Tl4=o4C~N?tD|8#`EGJXrV<#%}FMEWV2KakUxYTKp8mb)ii)+^OcwU1NI8 zfK^J=`66mCM0I!#%-?VtwB|jzd4?HT14?&Qoc&OuN}OSqu)P+eM6(*?7w93XnrAL` zFEk@dk%3hJdYLT+7n-eDa1&Ln)&-3tb`*lE%8ZyC>K&DaDzlJ`*#18gdE=yEdZI+0 zl6Wg6sxdImY(~bXAW>>FUTX6@2wnaK{R2?w3eKzvX1rY%SIGj`G}?Jckfp=X$o>~9 z++hq7Up7!WyS4&*FVXo%YqN5;(pdvxqO+ITlsd;ikm&3qIv0b`N$n9-nsKfv*Md++ zBff_eH3x^7Ipx60kbQw6|3sqMPhg=TvKC?%vDJPL$_+Ogk7GF>#7Go#_YiWzxO*|$ zP(I=pR4!yCk1-ou9LO&KpQ>m#Bsw$;D%vTiX#0;LBSjglhc!jnQZsTkD95PUa+lh_ z4zLIe+^B_JW`)uIDUg`g{xu}puyEI29J_J3K%2Ct;&13BGhwPXy^U@UF#n)hWXWIXL8ned>xef&N3!ylMKX{h7kEmODqYruReH9z zN|%+hN}mJwQdQcdsuWQ-Mw>gZQCQaK&4*%hZNyvvByG7?Njg%!U%ysKG5YW&E^}6R zB}#N^WmfXCW!8LNt9+K4Hm-;ERQD3II@6ebz&+1V6Ik6zEG7P61&S_I@s}?nev??d ztnLJ^d=cVNXZ7y9(VZ`nnZqMT4OUyx$GbR)~!h|1WDjCN%F0|}_&R2+zL*HekP4q^s=1rp-E7-h_xiah*N z^K%n&2L*(|WWzK*8Vu{%BK^7Ea1r#$Uc>8&T5Z}>6!Rt`uL<+8QooJdAzX`$4kW9E zXz0i2Q-0hscj%8Ru*HIp+dMLK68`h!HgJdTz<+++g2>Rb(LVfy--r&o8oLzs93r#YDM_lGlH}n#B_GsdUYKZMfm!X8BoE&y@sJVNyg0D}sG;nX zG?bl^hO$%APM^fQyhmoWQ<79WCCS5gN*+RXE_X^g;wCbpcS@KxB6_EUAQaI%B?NAS>koEH)^b=x z^iGM=g8@Neuv79`Jxi`kEJWF)+9^q@osy*5DM_lGlH}n#CH=vg%bgMz6Dy*3O4y=C zMDLVvNQ5GKr-WVNM)XbzJ2M{9J0)ruMD$Jx+bt8(J0-L;FQRu!x_lVL1j*skiTzxAq(|h< zBPkRfgpN?ZBY|CMG!rGiP09c3cO=xWMc`%Z&fp7QjW1hoMvq|n1<19_8dfu1N=4>EH=4@JkLd~R*U1T_wQ-GUmp@oKX zEAvY=ZfrQWz~)d3jSG-ZBU@^mZ#cWi-%8^=!}(w?u&;3=yiq<8xV6Sv!-=qb8^NKp z;oQYWXsh#6hO=`aaGAzQY`BrXoyH9eXDD%djnQZ)vwR1Qa}4LLlYq-LjvLPF#2qz` z8O}}ffjepJ8O|6sVrPxf=sS5qtq^RXkuz1mM`#>2ob$-vMQ~Uey(IiFTGnIBOQUzI zZS)>d_PjHDItulaLJ>4#6>%?(GpGb{Z;er@p2q?A5gZDPtQ3qpZRbb~)=*!;(8`|g z9_|B89xV|g`qvsUF#2u?M!Yl)g$C(D#fHNl%nc0|Y+)n}Vowjz`N2pSsxd~wTDJ5s zjZq2yPFQHT#uy2=vFAo;jFFIcJn+#Pb0nMsJW}IeB#aVlp%MDxi8VA@=QlK*mE(br z(HJA8f<1q%#uzEz&jKE!aWGPj)3|}*o;qiN5jtMuV0w)e9C2X}dvcu4M^BI7NIgO0 z2=@CqQpRhHo`0AldxFLxY^<|ACu(dP&KZ+{CuwXM&N(LoPu3Wnc8KMxG?q>~D$M<5 zk3A=yHl?=Hrbj1ZcsbKKy=F)u7mfNB@l1_T>E@xY{6lSoabrO9F0+l z=hz8zH5MbLh0lN{kCuoL^Jqp(u;)$@Y@%g;CO%a# zq;h!94}VA{)Fet4*D5(Z>PDbsB@3M)g=$yBGX*C^$Z6r`;Pfa-ge?(~h=6A5>=W2{Ge>apMCjW&R zOCu}`^XDHtwuCgoMYWA^adZnCp&bX>B~r*jr7!0gxKv|QvL6TLWg4SW%h?E@ zs)4W97)IU93;q_31EX#bj3*$DscXWWAlaj4QF>#o(rwXoRQe_t?^~phiQ#a7qyJWo zVZ_*}z_)3P;cyp?x?SU73A{sap(wpMd^43&vnc(0t)4<~I(%S2WHwoRM4z_GpZY&p1~4RgE!`M-jiKF)ltW z$p5;=xcHRww&D$qF-J0-BX4SqIb!hQ@Rr8t{ZC+v$}5Dz+GzZMd7!bchho$#^7K_~n}Fn7E$y)v!)necBd zBIPIHYmV3IEZ!u@P4@!7w$Uz=*4T8B!icMBkrNPd@EQTJWL`~-1_2>v#MR75YJ%>Sf8m81^a{Hs zM?LnWP3e{d9*NB8W4KDi)e4mj1Qi=`wL~=v2u)xe*QmUJP-Mi_B9$Ky3XQm0r3wN< z&^e6*LeM#d0U_v|qJR)|PLqHTbWU+V2s)=EAOxM$G#~_>(<~qaozpxZ1f5eF5Q5HW z5fFmTX&DfL&S@18g3j>+LeM#_147U_Z305jIc+t8ozox`%9!Ez(E%R2NP4GTUGJ2e zQJy};pW%&C$3PN#X9gG8P5}YE^9n~s=YW9TaoAlI0Rg@9BiGm?0s?yH0IzIa0s?wx zC|BvO0Rg@98}IqM1qAfY@Do8eG9aLLj#vOf_ke)jxty2d9svQpGl!R=o&f>9a~iKj zy#fMyX8{Sl0|I(y8SUs35YRinP)21yK=0hg_UIcB&^wj9K;XAvcA`;3CVFQaE7w0D zpm!W<84wWIJCt!$KnQwgpeE?v>0pM>KnHm2BI%vMb-gpyjGmH4?>tfoNz-&e+)~Dy z@D_46bT#g4s4bA0U>0>S91+o5D;u5ehn|R3pD{x zVjQzm%Qz(-z z&SL*`+DX%mP!o7?qDYECqC>?AHC$8tS>w==4mY6O6i-4!0~~IQ#8bx)0GR4JeffDatrxK^Y-nFa8x!yBk>=}8=<4NZqv@}B8S zxH_~q9bP{w(=U;6i0N>>8j$`E%^PZ}3Jy-M0ZmgiC>CMa=Cul|bHlh;*tx7+|@iku1n)HQSY$ga=m)=e^QP76;UZP2Y zE=^Cz&LDLOoxN_d!r$TWo9RaTm>}dw%~9zviEXKnli`l>V^xbcI&mx3PU5BlB*X?bs> zB!19$D$|UefgkiG-N^L8*E2{dgKQ(hAN2hKI5iXF89(StF-B@J!7brSkfCE|;0JwK zEI$-P#aIr$ASyI^Xe3Vo_$&08MHVB1Xpgj*!F;)Pi_>;VdiotXc6@v;x zsZq@68Y6I1WnU3w2;!*(s)wi;1VL1c)hM2U!j}C13#{6NgsKqq1yM2b^Po>h#b9A0 zrK4gHgi?z!G|cVr-{O)s7R=OdBbmVkSnUUPWkbM8&utIc{nq!Q_(N0Bg`*6qk7xU;Jpf z1)*I4#RVa@SK&uc;vy=>zX4J+jzQ_OQcN4EXa&GhQ36pMMun>&z64P*7Ui=y7cwe_ zV%AYHltDTw2Gee;dH{rMi4Fvar_|=!4GPFl@**n6>(G@<{f>niQ88F1FZJ4m05_-K zDS$#FY(iDZ%c$`8jEX^GI(rBVh>AgWBh8=WWmF8ldk{+VCwUnagUC(KVJ{&n22niS zoXv))7%Z1eUrwEfiqQw#DVg+imP1qwWkR|uIT00us4#u-3m`r706EqQ88GqEX{K;M#Ug1Pk+naMpO*yt4Ng1FT_OqJHN-DJ?6VyHh$hbtO%F-s8Y8N!@b=z>7trp}jP90>Q4LvjF_m-`E?kY!EbB@#I ztXFddX$G44C}in30K!ZcgxJ=q)Z)WSDX2>gSDa(Xc@`wH8S2R=sk!D{Ngk%zI(0nI zb0Y}qO2BHXg}@TLFTjS8J-{)7fEXXb_>v+tQ=9=YT44O7)$)UY7z9T8YE~KnF{mn( zew@V+5JOEl=;H7z2vKm!I5brr17e&`A=PX+1jHaP(&s$_gn$@Ck@Sf>fDjPl1Z2h2 ze9xT$F|ZQAu^>a@8n9`@OKw4bCK(Xp6^iAr@iHKWy2hkO&^83b5Zi))7|e6i7tm4! z#9*;FY$Ubh1?U>ZfEdd#HPS&q40an<8rp$?80_m%n!m=&fEYya^b(FE1jHc9q|1m9 z5Q9Pr(;u)L0%FjJ(zHX95Dw2U11PF+sKsD=yfEWq{0Wmnb3qlQx;ql&*zaJVsF~RnVggpF`X9)^y zJ{~vdjpPY2REPtxMR3{IQ1767`GTX^9m|dbdqM33r8-{r^l`F@-LWFvjeCVUAG>2` zH1@IctASf+e(YmkJOj9;#@NUHU?y-Yjj@k?;}&3FV+@HX;tGeS zqoKSKw4vI)^V$TvcV7GGqfOCh{$beL83wa6gUFr+g*B>n|8jWNhUrvnU-|tMr)Y z%~Z;RQtwzP6vkdR4@$i;8tc<(?>NB?P_sVl*y9D`eRk(=JZgGl1)HLDboePMrDjoj zLaow?(Zc3X%J%@gNm7WXxqJ`6o2)TLXQlrk1ZQ9*58J(!I$wnTE&LgUQnCm=r&j3dXh{nQN!jDb`FXb$4y0?vL`P8JtI_BL4v`1eLmwN*>f0l{!cz4{3}_ zUCSw=&w));s+vTsUBaP8LuTBRJ4qwp{1?-OC z@D<%NhO;X;d`0&-)xi4jHHk~{$GkuVhp)I4f6L+Uxt5QKb17T$fW}xcUtxECA=r^h zeGr}o%RSaiD)m)urM`_`!%9u%nEOr&@dEWBC&Kp{qooFO%;^(V-BRC#AEZ!97NI}Z z3jI0yF@^rYmiR?mhL+-sXWp-ZaVN%sbTIq}g;0_R`K?ySAJHLgAY>Yw>rkDLowW2n z8e>2F1u8L2A=o(l>B9O4$E1x#&F|qEkmXUA+Qjzk+U;<7`9+^WW}I)&c)`IZ&pP<} zjOS{}7LGRf{)`t52sl>a3p8GE@M+50A5E=#qDCdhZUM3&}%5ybAD{o+it03Q_1){uBo$>-R z`Z$&IZ5c$isBPmoUzhP}4>Ms6-NJ-z!zq`+QUqJ?BfN8nT1mGd^5}+l<;VQ zC~sP)yrmf(f$l`aZ20#AU1Y^byu9VB6H5KEj%Ivp}dleS|f)asbwz zKEj%tNT@x146F%GAGI~*X82cHLzBcB{I2d!SZX9fUQaVRr(Ix8?SW!oP3?hVU`_3T zVqi_}fns1y?SW!oO>m&7t?6NgS3{vklf;?KnScE z77zk!h6jYenh~0ytr=*BGwopwO%iKH)>(6$8SRTqbyDUXA4q~VYIPZ_30z*#=VQ$9 zWJ;nqk#s_xq={zq0!q4xT|7w_qz%_~zUP9b%q z<_&cC(CVgoS3}S!hfh=S)Bu9<4xe(8>afk5?(ktCqYm4=r4Anm^3-9Qx60v-Y@s@A z^VT`M0WC>Ya^<|l;f-Ty>L%VfUghux&`(uN2iW59My@RN250OI%A9g_Cg&Zpc!9ev z^#ZN_x5Eq5*0j2agiME5m~CkuC3*?d;bq|VG|v*fJk#O2ygkjsM6a3YaG|_6T|EP+ zxg1D6nEr*RRM3ueA(yERro&b3iSz+36WvXRtIE#w6fW;anGR?5^XbdET#Ygv&Z=GM zo5-n;`}U;oCep`!Z>VE5PapTalRoi8|H#}00`pA2hIeV$z$0^^ z>Ay~h9X!Gk)89{sEj+?f)BlAKdw7Jt=^ry45Sw^}Wu|{F;bMX1rhg~9VTr&B)4!Ox zrwQz4`t#VGrwi<9`qvPiA+XZ)f8#1~roaKFUs?@#mcYTLf8R{Nr2>bW{sF?j2^?km z5q9b_fn!X+A>nd?<4pf;!W9B1ntogM~wi0%x24zgUG;0_UOZ z96)_wy3q6o5U!ToMW#QQ@H~O1oBoy5yGGzr)4zm$f4;yKrhfzI3?zzwFqley~!UTXU95nd$l3bfTczzqUxOn)TJ*eLKi(~oh|UMz4c z+L`bYf!j>~Cc;Yv-fsGz5?&^7yXhYy+$8W`h~kXAT;PMIzm)I_fjeLo;gtfPz#t^N zO5je@|A1riYJtyVOmc~+5x5J@PI!&LJ*HpC@qDeoH%z}X;bwvFnEp({>jdsK{iirK zt{1r9^uJ*47J;9bzQtwt27w3AM}%7ier@^(32zkmz3C^|p*IQq$@H6Y@w-{zub82P z+XVh@`m;E4ZV_l${vyI#1%@nt1L17~UCY0hqy2V)am&Amv+NFmNy|TxdhZmNvHa5s z|1L1k^3UMJ*)Fiq^7n9T+$FHY@_!(_TVSc>dmJ102=py~GvU1g%PjwM!utf4TmDak z_Y17B{8A322LyJr{C5c-6xh@9b4~($NMNPq_ab~)-~h`XM~GiE@eYLxfKVoQV1oJ}I!;@;@MaO5k+M|B~=&fwL|D zd`jLaa2|3ApAopw@_!+GR^TGb5ApK)oWRp9e=Xtj0+(9;lf00=AaI4{e@6JCz*UyN zkIXL#Tx0oTc!Ag@a2?Fx;NLB9gXOPd?#lu%wfsj3UlDkP?d{^KTmj5Q`5n3PetlhRSpHDv{zKpa%fFxS6M7N^0Nbx2{I|ft zw%?sq_+8*|+drG|4}qh=On6A(7~9`L_#c7eZ2ue%6~j_X!9?5N#`W10SZ(`T*&3F> z>9+qep)GK>?ayR8hXl^E{R;`h0vFnTHP^a`z(uxy4|5%Xr`!H0PC8fMQrmxw-5nLU z!uDS$^aQT5{Y_+!30!0QWo){*z;(92f-pzm2HP*-T|q+NrM7lbPmXKQ~xUO^>wIz}fV zY4I31S}T4T9kO2B0rl1>ZVzu_QCgN$9Qp_;VsjzWDT!QzbXu$jk~pOT=&`q$lBLH^`x`)Q^e%|W zj1}QKy;CQ+#qnW#JBaNARKeVV`s4I8sk~Q|G11z-D8ykXsuh0^U+Kl;P#~jtC=@h{ zKf*IVP}~#wtl|xzr)cKoEnqU){2fekUV(bUoYR6${ZPJtvwZVn>k!srmEh_ujNJ(k zh_%@Sa8~RE04(ad65t%?Z2%|sH-ZbCZvfI`A6^BpLV(QJ>U97Y$D9VfQ{R3yz`9r| zKu&A}x+Z6XGaMihYfn3Fa!v&(h%LAXpw-?8P!!uqZa2hs0+hryqp3JIiDVVA8St%h zk4RP(%S4rP?suL?vbxwq=w6+NV&4GN$2P#3&Mqeie>B8yAnQG`t^kd(GFZZSMiik* zvj(E5DFJ7CXa-6VdyxvwC}x;;r)A73WINLwj&SE+Q5RPskk20^I1T@`4=nMbZt z8A8lAuygysCNKVJKb|4P>=nQF0Tj@r9@|$)pjibWpQ(`e0}zA;G^>nZZ9>dXUQ8E1 zh9NBQF6>dY*3MKTR?j%Ezkj?gbjb!2W)9`ZrLxri6q z(PuKDSafu(m@AluV(2iD1{ohEk%pz?{#ODe=d+R{;me3GphIOM@&WZH{3o*0yZ@6N z(NR#%OVF=Giu3qQI24GMg-!%9s{z$NTHdJ?Va=R`-YHsP_5?@?q!n6MBM=LquBLT~ zvGw8X#u9+80_ZV*C{8O9z=&~1EUlXW=st4NI)#2@?$_{8O6%N#RYXf)IDfX5mY>du zKx``c7Knvf!IEZ>oY=A%AQg9{V(GD&Xt!x4*(`QuY#~M%X{FKM5R--SaJjBn*c%z3 zmft}8GthX`%1kP4c0(7K-lh|yOYcU#*H@;q0G4_1_kZ>)8-F1vTP>RPmrCz!x)+hQ z{KF26>A4E(1|qsv!JbUt+C=y1&6VO9$*mKK3K=^PQuM8}SpoFP<(E|xUC7u$h%K$7 z+$%))rnhuIp6E(}W+JxxK;o+ez7<$2n@Petq10X|RYQ@jQwMrVt?NalMn^rR)*W}O zQtO(D7BN;RweGZIm0EWZW49t!Ds}0fl)6ly2N5fk+92@vz*>(tsMP9|N1;$yD6|?1 zRXirB#k43+_$V7mGn{R+_OA3b|IOF@>;`H+HBHwlv4liF`}i&mxR@8PYLTX&(~iA^ zv1xqu-;g!G373%~V-1e@*fhR|$B@Xve7(jhy)FXhzv{K* zFM9P@LUXjFd{dz}pg3@1w?UpxEj83>GGz*#TAJ7ittA#ZwM?K64-(he=Vl=FR=vB91lh6y{&@MR7gM420v%oBW>Tb0b;|F1Id`K!zz zWe!Rig&6clu>E3R=AbH;bC;4a#FsHc$(V+ef3@Y3zsM;2jxzd)dgmgxNXR+p%jqK; z>JgTW8(s81qM>%q01j6Xk7rpY0M`vh_A;0hVtJA-YBv7EgSKov-Bm0^e1vmz8ik0t zLp<{p_hC_1k!3wATk$YH0`CJZT}kE2L<=@HjiCq2y^>a)vS5LxSEaF?>JzJf2V?qk zBG~@5+*yAu_hKp)7fLNdUUbi}FFD9wGcJ0~cc4TiPFB|A$2|=lLv5hb2I`n~tWMdU zPTluW--L*(M%wQ4n6^-i{91@#Vtf}dEW7}?db83xU7GEGdkMt;xfb?Jp0eNTQt;xR zULVo+l%t2&DyQIA9+7t4Doq?6RF^=x@b9kZ|5rx`8FK5%pH2|E5gPr!oFHVqfP^XB zw1ORX$xSP`@RjcJE_@YXZd$>GuY3rm^1|10^!Gt-TCuh}Z-W@*rWIWHO1c(;FSULM zg$ofdHJcZ{P6u|lX$2R)l8xqY(+VzpjhYqXU1xfptA z;vl$`++4E#^P7s;*^=5h`yOOZ3-Ap3bna}4Jskk^U`_e~P#m5Q7p!&OLl~=r`Cl7a z02vr9&W8)unSV#v`Vc>vJRdIDtDRvm$=9HS@)6|1T~V;EniUjL<@mL7@#C!yFG4tT z1>^_Uw`cOU@|7zzB6=lI{NalsH2w{K_4w9HkS(6Mj)e=Yg|hLI_23r&6!esM#%kC* zJ|C1|{1C#S_yB~%@r8)BHFF(Flg)->L`;e9rHJ7f6pC9yRusC!sK)`wRQh+4_;00|Y)174wqC76P4xJz4&Wg0aKk(a5T=*5bAon>z zdI`T-w9uOfWXlV`Ld$d62GRnb;kP{_e?dT24RPUD=)&9-RE4wvmd(iog$RfQZRSCt zHljY88)4_rMY)wCX|0!Zgr8J|MAEdtSWr8Nd%r>}a;J+Nv%MS_{W*v5jkxzKv@-WH zk#wt<^d=^y3Yz&yJ4j!Zd#_0FpqJozCLjk{9J?yCCUg@jrjx?jur_idqOb#>?!80+ z-PunQt`op;zGTdL0Ziw3`ubAg>wxnqOM96BLFbGv02?xQ!ETPjcihm%cC>K1!*|@! zCIK=XzM_UUXVSb`&P0MOnKWgNvoQ-`Yuj-E38yW=fEf zLQaYEdKBQQ9NIwL`xUy{WPvjeq$8%a6AwyF3$VC$PUzLpH!L^r{R$n(<#oQAlSe_X zMHrFgT*FMSi=uYWLNtt#qFOpy&r@hhp*PGuNSZmXEy8al+9NtGz(ne$QEasf$Hj4P zVozN-zr&4iPE72n3s(iNMp}oPF~T)%7}j#8oQ_r6a<_xSJ#}HVr_SM?y0F?)=WtJ5 zSna9HnX(iMxovKN%Y^uT_&?MYKld_CA$UTb*i#p-4|Y$5JnpFr_Z6>Bn!`PH;eG-H z9PX(Lt37oN8HUxKI;RO%468kLjzysM)H&Q!7gl@foHrPw_S8AtQy2c9J$2y|gJ)5P zwlH^iM3`aCc@sb3ks$)Pr!G7?%o3XoBVNYF%HTz;D6XnX&V%$EpK0Gn_Jb4N` zHfJ!bIowkhR(tB4TuPf9dKoc6hkNS6Cnw$mSOa^JU5MQS35su8fQE{R&2-^q!AKAc zxtT6}PK;q3CQ$|8ZKi|GL5qpabm41*tC1oHo9V*WWr)N%xMDhdy>w{~u9yzrAi_bX zr4dZjW;%zP>B4F=UCxwgGqv!|u@9j{y7Mc_99Em@9B!ryZ_oHN1R0vu2BPxBW;%RF z4w9JQW;%QrmQU0~SNemS>CiR<33fq1nMA<^H`4)iBytk@w3oM;F2T)o_^uloX`@ml zxS0;$aRtw;1UJ*+yRASu32vstXWRG|bOmxV9X``$Tn$u^;AT2}mJQzlRFvRmI(&u| z`AQPpOo#8R0#ziqnGT;>g}kZ+H`C#>YMUL%SC`;sI($`4e+Z~P!Oe8|s47x6Bx)GP z&2)%sOt3cKJ7^o$fTjd}iqD`KbnvhQH`C!eXZq(T(ZK{a)8R9xu*=~DH`C!OXS-Ly zF|+LNcbETWF3qg6PxM6j|O`nyKwG5j&ZKqOedWCm?)8QuG&l|ovSv}N$2i9 z*13B`o-FCyz0$c3H`9fm!>R>#fZR+M-j_QL(hD4JrVC>;9YB%8&2(XGrUNK(xS1}D z&2#`2Ia3x-!-p{;rwRZS@_^8}9so7+H6gUY;byupHq#+bqtifpVly4Uken%Vz~F7c zpvmE8y0F?z=S;;=Abcnc*K1=OZl()=?DRm^@eViBg+GaMY&XgIjh6H_)3wKj3XS!t z4eP0VObVzTfJM+FEkOHKoLBt$R6t#bfcf?MaXFi_Yskl@z2 zFt^UJfk754TUvmO^TgJm1gW1z#pxZk-Eb>zsI$B)D~s>vw2|K!RK6uzp9x1ryvlhxI#|%;rEx z=ExIU=dd~_cs?3Jf?MaX{zkL|^eaTC>%y~v1h>v{^^F+ACzg=)T!}Ih+&YJ~H-bq{ zf?MZMiG>mc32vR^${Xe@N^t8O7v2z6B)D~s>u!kZ68Gbm%WjAo65Kk+RX0RUT8MRp z_q7Tuq-yCLQl|w-Nej?A8SHU{*FoTQqiKOkkkbNuCT6g+@aoAwMdU8=`x=sT=GHlU zitfx_yfe4X;X||pEi4zd&WRXqoeSeGY1U;mn77lSWf*|O^H##%@zHBI(*9!wN7`wD z7eKNdyHn`zNa1up4XCpiSZK~W4FLH9=sDA|D$g#6K7izg!}ou?P>rs>#<_6fptkYf9=afTfxI%whL1pC;Q$c6Dey+2*wX)#R|unltEXfLZ|@ zF^0421jx!+c#3BC6yXA=0z-GZmjD%FbZGY$pgw2*e9f*G;U;GSrS-|9?qf7FlNRi2 z<^Wlgn>m<-EnRL$I4y7$ewBxu{OCTQco;8B@DqM@&Aeb0ll(qW$hm^tY6U299z^YO z>V(h==QpzMDL|D|&zN2!S)Eg}7NED#px(Kapk8Ru;QXDe`v?shoqMQGUm>)~`H>p* z6Y31p3fOm~1!#{9s@{h71L0eQ3mC?+Gf*{y%8Mo?UoBLZp2jE^MMkl8wBZkO@v01y z=5`v)*TKgc1VZNPRDMA2G=$RvBk^1K36$155CtLM{m{uy{dol>aNYI;$_@)fl zBH*MVzAFPR7I1QrnCPFEvQEI0i}=2b*y{wGqPby~Xr`3A1afnP+?|xmw=zWaz7eDY zl*>0W5XO)IxqO8KoGaj@BEG5tt`=~z=8l7B^~sWR3pgV)?9rwTIRD%#qKc@*x8Piy zxn2Uvbx;>LU-};C73dn693HtZ3c(;|5Bh*+&s!j)UqoOP1c$_fvomhq9Xh- z$h#+O1#B(F?zg&AY}>Y;*!@-`#SQ~OirsIGqu3Q7^vET*S1nP#M?t8{9E=+$I%rz; zd<0%E(zKc23@huETFv<&?ad=>#-|JDW}J=R$-H(&a~o)>XQf_;pqF&#FTP&SO1*xj zUSH7O&sswn+avDj^{h3Cdd&r)=6!Ghi6>}~KOsbWy zA)C=k%tI6-a*wuzlA61D9pVSc_yYsIj~s`Qu<8h4CiMRiTR$gjU%yAK->NqDl6ij4e`7I#o#S##zDioWlWeB|5p8TwS$n=!tH*J94uw3x_ z!{_%@U;z28MfTzr41SPyIJ^C)d;!l$0l!heUEom8*7ytp6!1M5!J%k=TGb)YzM{~c zMdyLhT~cTks6&O&k(fQI$sPl~Di#TF;eCv{okC*wr9EX0;RNEJqW$&Iwn<>9UTQa zEUjyLE;0@cqsblWj>x~wdU2y9t}(ht%1T>>eCQT8*0W@OaoeK`9B zkP-<*7X>=^WuV`;pzeki_}6tGpDjUF;jFhtPqXs5wnu|YW;6yhqT>H+22oZ7z~2m z+E7QIFGq4#@e1*rT5fis$F%b87<}r}O`U@wy&H@(Ks5O2W=Dd`ADHzNGseV~q5;g5 z0FR3z6Zv0VjRZqf{@H&1A!cqe|8d9WAFA>Xe3o5WUsH4!tNW-cms;7Cl-&#{`;(DX&3aJN8JuMS zSuaEvGzrr?%UP}8lwuB}5VFH@Ph~T~4l;gMdAuj?GNi{_+n^`u&X-d}btO0g={=6D zL7Xe4ySVnK$7`%r#gfoOg3gLjA_+4|=tQZdlCY8l;f^vxe7d=Zg!xQSE(tG^u#|)f zN$8RT!VW$`DkWht3B`Ow_A=G|gL#&*3i{`o3Q1+Lq&ohORoK0;o6JP;UlbNzv`3S!cq2 zn*^JSH)!e3N3Ty7Gw8s~^ zXp6ts;G#nzfqi|kFyg_1MEsfo#+L%N`z$AEm^h?^dT%;C=X>5s(hf2r7A86$BBy| z4`a_GE7ZiQ6I8Kk#v?%U$nvpz2CI=}@j4`XQOY_4)pLoE#lf(Y^`bsdG-+Sfi~1kfB3F`5d}@n-rn&Uga!MG_P`&n;fB(tDLP%>kWqi$_w!5AID1YNsL~)9FZq%CH_?4yNPe3 z$vzYKS>or}20j<~ed6tm|3cvZ0++Rbd2KnAUWz~?0yUkbxzH6?uLNx*XcK%I>tYoL zPk6ph#;uvvmmtZ>NHW(?qE%m|c&?N*YpE9O*Iui>R!O+(n54IXb~>^@!qPP>tWI_dezqU-~WBo`(pA?e_8k@NBDlO>rgy%&K^2plg{>-AdoK9DHreMdkZy6{*=b!XeR4y6P9!iaDbu;`>Cd^T~efXVN zbPbn^QAeyZu;>~t6S#m_bPXE>t|k7O@;3@Rl=xKkR+|K#O#BPGmdygMApQ>@Gg}0H zf_MV)R)Iex{($&$fji{`7qaiYLf|35)lZ`McfwmAb`jpPOy{Mq`=Oo(F46k6M^!i0 z!ikduYXmyk;4H|Lz}W(|7ze z>!IRSh`2Q(u0X||sNyaXajQjKy^1?s#c{H$8M;7T*%>MhBdmMiy5r0HqnKx;JlP#@ zPr!OBCwqnoz@4KyDJIjda5Y5&5d;ZUv>N0H)o;N8a=v#K!?^$1h|>oRBgU*(yXf zzPQS46Y`ksEM`0FWTq;mN3H@MSviMTj4v?Zdi)5wb!bX=Fv${3F7}xWP0+1-nd!m? zrYa@IwZWq}9vp_w_I{D0tBWP>uY>d(WfsBUCgdASmgBrc{m8|@1+o3esVxKKR)m1ysNv0?L#wSA zrA!3STQ8@6E=ZG*W^^qATM+2OME4-kRp8FClZbhONtpI$1gh^>Bb^oCz$(WVgV+CO z^rMXzV_3ZHHR_ahb}^)#2#q>-1*=I2EMQ=(hra{zV9EL|_^MW40kM z<~ICHAj{2Qxr4f4$U2KmnR5lw30^ldK<>XHFp=`~X?>ZznSAw`f@^L!uqW5v2nf#A z4}mKuqsD?Gi*yl+lu&Q<3WIVzQgPVlQATlcjxYXLje|0lmO!2UAe}?LCm_(=j2~mu ztVvAxHWFeoLrgswUef!KbetE{%shBS7{hGUhmoGIGe?z9qUmwQuI4CWIAf-akF@uL z!k4Zb@Rd|FISAHj-a-sZ=A|9Q36&o}loP1$QxP5Fo~F)G1e!YtC1y=x!m_@q0bsi2 zAulN|zSqWiG0n_Fotdq=2I;Bu&41PdIyWHZ&pP9(5TWz_Kc|JxC5ZWx&YVda4B{oC zF10PiO7HhU(kJ#|%*}||&nkiWB1PAO2fSkeHhmsaYvX7 zlTsq40x{KHKxIEO7wKWL6nuRM{U-V^F+i-;dRM6wh~=PBjT|xEsErcy-kATMDMWru zk+)$cV=x#`V%!+S;nSIz72n4~Fjk*X)dD)-ytL{ng!lw`M~cTRX4NQ=Xbf!>XYV<^ zF4+$*V{HTJJhErpe#8m(nA`7$*olk<`?o=7v(~D2AVl`{h!y&4RWE@g+4I90KQ!$_ zO1+g2g3*N_?F9SL-4Xa1fie9M7&DAN6ZkU|Ka-g8OJrQYjQHl(mRXsjFYe71Jf7ktW^{0=1WFH)wbXlusdW4`vy4E)MP{P`Q?BL0J&p)3Af zH2{nF?|lf3?O;3BHdEdO90*vm&se0H^5R}ouD7>7G?5Og=0!qzIl7Sw^kO_9%#X6`7=8Fbl&maDhQ<~P;YBi>4`T$jv|}3F-g}FQCmW97 zgs8xFXE=zdiy6MH4e45t%2y*45(UG4^1zLu3BWd&?gws8B^%A=(*3~gmWhafW_%UE ze|MP7<^+t_5NE|jDU5f(I;C^=1&E0RR^d0wRry9K$X0%bg&?HWAe?1Y1&;#QTy165 zv|(7>H(}KZfdP92BWi6*587NCYt?2FI5rmuShXDp#C;Q1o&5u{XF}i=_&<0meo_oo zAjlgBc?DK|a4l#y*T!0XL$Xj@8*B9wAYgNCtkobuP%O5!`U~LLTpMc*5Fp*Q2nGs} zX>)C?)hIxg&9$-CAOUi0u8p+@3y{FlQSc7x)``KFs6$&CV?>x?&3+R<*2oaS@{HY7 zXf#%6fv9Kjz6oorKmlC~o&xH-APGn1X=x)NZ@o1!m;gIz$L0)%u~>*~CZ({D0Xvt{ zCWpG@7BD)~{!9T?}5~v4g6A92>X<~`2wJdl#Xf~I~TIa+V)@&}3 zwa%47z>3uq{)nPiL8YsvW&}$ zbBU~lC9*_0aW0Xyute5GZ;)um`z9`K=pG$-# zvP2beE|ImcM3(ZZ;#?wYVTo)4`Rd|aB5PrZY!{&VIG4y;SR%`m4RJ1!wXj6C7IBSn zRtoESK2ZGCy_~Xon zC9;(8Ih^|maGF>mYdsp=1fp>6KaO$kE>Q|`-vlmnWr>t?A3xT)PaNyq-N!n2kI18( zyH`5b<`P-!IUF?xyV_hLYwgS31L*}em&jT#=6(iHWOIqE^>PGfZEGbqm&jWCL)`%6 zeG}HJLXNy|!a5*ymiJ9quL+?IHkZg+2V>>P(`Yw9-ESe?I;#@RqVbLs6N}P*kEzE3Rj3_5= zGbI+y^2wO41xfq~$&})4#iCgYi)Q-;!HA1ytrlHAW8z#iYhlr>)QyW~Ei9Vl^CuYR zqFD=zW|_@_j-<8~i)Jk>n*EZ@xMhXb%`#%h;z}bg+;SOb@BW0YhlqW zQA2zW5f;r7HEBWCnBT!(SRqx5a?xxgKuQF+lwowvK1g^SgfxUBfg3=M1o*IQ&+fyk zCw)X@iTE9a{2jPx*21D$_Uj$W2(V~YfEJbui)IDjqFD=zW?8!hQUP?E2bF}&1TgILS^&xgFzq}015`x+jywUI2bF{?Gs!GycbWpwJ$gBSV^3`a z=pmA&+dQZwTpPUsc`|JtR1&Te+~TlED~OSRDEW@*i0NsXV9+r&Pzj~NW1@$E^29+U zdEd{(2q14xq0;o;;|;xSYyPHn$^NnmDK=d|L2p8|C9cCE`2iqd^PrOOCMP|@4w?s*gj?;N07W);frW2~O$I2j zc~D9CCXuYdo^c_-JtA3^&4Wt9_d5%atj>OD62L>TYXIu)4buR2IrjlH*gU8tyeGCF zpwZ?*CE;g85pd7e~C%jy{tK#nZ}94QBnAhGOV2kp{%+UPe0Ze2 z`!ZPdTdx3UiX8?B+Jn$JI74HHV))OVfHv!ljQx(7bkQiBaUv#DGzw>m$de@+g)>ut z9Gi=NomryMC+tp_0?Zbmz-}R!6YGc<*CP8M`ZF9ER0mLEucSH)M0ZeOuOV2J*B3EW z_CO{(D|RwKoqZM=EQ>7#s26R=SsrTzXt241(peeX4bUhWpR-ATCYviPovlKHVRki| zvU8<~8DVn=rE{IodW=2(a)9lkaO3TB2=0y@0=G$`V{jf2HfXU=LnC({iT#0?8Fn8E zeM~Tzr5V3%gk5uUPC@ZAY49`>684Efu12K!YRSF#sIxBmus2Axr&p@!piE?DxS8N6tFF;n}GSnM;f&jRwAtzBl?h_@( z?R$7}wG*L?bP%WAfuBwyMw1LX%Ve6d0Cu+XP3oG-wBZ7~Tj)k+>VOJim&NWwSW7?U z3~bY=6d+*t+<=&>*nY$W?QbIhwXshD9Q*N&0KFny2A^)<%w&C>LV!%WmU8;X8UeC| z0qw@v$pAU_Bdonc(iQ?FWD}!EF&0Dxrz)b|QJNee7DAzH{;>Xg(UdQvRfBzt;~6AsPX%QHCI_`G2tp>cO)||^y;`vsP5ouGiW$n7r_q0~Fd_!rW*}^w zz6pgq&di6rOmPuz-~-qV69R~g1Xyi4Id&gC^a^lXSiY|=Dy7y=n7*GL`vp;f_@%5U z4SK9C8?DrmO*Z=q{D2el3)Pug5VP5-BjzJ7CJi~W`2!+zMFJXt^%T9;UpHGp%IpA2 zhYp)SY19jQ0Ym~tB$aIjX^`HQ`NEk_yUBpQQg&am zq{{RAy%=_1GDi7_clU}sS!l;Hh9PicZyN~&07N`{CmFB0;Q|mMfsU+GwC8v~o*~4% z0%9c42q5B@`tgiF%nUDv-InD1m&eEXUK;jhGR%85B*wTIb8C^d)-rI;$Mqvx0dJ3w>&cwhvQmwFst&>b&Be5lo zp0K`xW%FryY4keZ=)FS|;xPKG8OT&GGvRin#1!H_3TL7a#C;V;q3ZDjiu98>;3?T4 zaY)w^J?9|4zr^e_;rU+HB1p=oCQ^xkz7m5&(JUzO0!HeQAu3azmf+cFktT@^)Py1Q z^l>WQs|iCDMoqYcmOfr#6oSX8MTRMin!tOvBEuC%O~@Jxe1gKP2@8NvRM@KtBP7PX zTZ#U&5I<7Ix6u;3cPlbVVbqi=dVaLRs3}KJ1sI8E!kaP~YcGFD-)d5x1e zB?x`!$?+;4p60z=kqHW?Xo=CRDH9cj=Xozzq*>vBmUxo(oTRX+CC;7n96ogTE9ZO`U!YFk9>Amr3w=g*?KRw#@*U&%VV zQeo8jT`c)3g;D44r@2=vj5_}nxxy$E@BE2ep|DrSu9P?kcW>n*;wp)CuM56f;xwt$ChHq2Ma`sA*Z4|Z z8ybc&c!JjfMXpmqpcHQdid?TSlv>{ce1pPJigy7;ZdBM)>L!U%iP+_BvrYx)d`gx= zZ}ElR7TQChyap(8yUe7cI`9^t$Q=qpiE((1kKCy+ssrx;irl5J*9G1!agG$a-Flls zDOn1=*B5$!=piIZ)KTaIiV1{b|CkopsW5~_+3!9maXR{?^P7PmQt^0#@f&O8VTJJo z8_9n45ry#tOQ({5SJ-lKtNpCy-t-s2Z~Z>V=i6#5AYd0J&cq3emCQ5c2RSka$V7?v)e63;0N zOJ7N&J+CktUMulFg;5=DAbvq%G`vh!mlqXA_2|XU`kxBpVeC-^&WO z)ei^FxrU5hr{a% z!^yYPsc$F@Cx=-6g9^jRpRyx)Q(-vyI5zyZB*xSbtNT;dSXerro{&y>+jqiyq1}0& z6AmdRo)g|z*mJ@M3VTlYkHVf44lC?A;X{QzCw!!^=Y)?H_MC7;Vb2MlDC{}mQ-wVz ze5SDHgwGZBobZLho)f-Q*mJ^H3VTjCs<7vTuNC&3@QuQr6TVg0bHaBDdrtUXV&#N) zt$)MP`SgTz!jHZaehH23HLiizihUlsP8@SDP(6Mk3NbHX1AchCw&OVD&hXs;ED zrhwbv#CwCDtrd#4V0eTqtxz-u(<8Lg3Po!Oc!aoCD4K)i5!z~nqCKQ|giNhaGzi=s zC#AH}3PpT=VEZjhk0Pmzy zN~1@hcgSOqNASEeSP_(W%601=I3S-clHO@bdS{v*+Fl6n{G$P!rmKt?QWkdP5ORjc z8qUb&pyL#e0B4AKgqeyEfMsX%34E%T0+wAuQ_u1Uu zy(oA-O(U(cAZeAwddTPktE^<1m#B<*WhuOXb@nVpz~Yg@7w-dMsUoCE){As254rQn zU$S17WPP3?nINoHgn;C}=>1*_bL`_-x*E7imr9i%)^=(n`0c@`a$G<&(TVzJ;A0iqf(fs%aL?=nKD4xQB@K}kK#<#G| zjg#oy_;rjMFVXV&okSBPS{Z+m^=qO;YvPx(vuT!SeS8PeB#Ac0-zJ(Y(bhOGGK^qf z-~`l&tK#pn*P0^Z4#v092`v)69p7><&_X?xJFV`f95SZa`_Sv%RmUaFg{mmPY~1h`DkV1f<< z2sTI%4n*Ujzq=T;T?em3+sV!qcRP1pxCqM?6jU#t(QJuB7+A((;%IxnFBUViQ8g2* zV_=z!iX6>R@fcWMgsKzGRTu-ySKx+dM}_eUcRt?Oqj?Hr+MvU1;Do}MHaG!qQ_)Te zW2&kr<*P|ttSe14Q~i7uk5|At^7kfj@d}vT0$ix#@d~*46yPoj;}!577$w?OVY~v~ zawBk&!f4GYfoNOn01TDC5jGS9->B;id~r1cSH+8&<*1s8<;?Oh_%K?bn5dWOXr;us zFI&tMN4u+d7@0H0(H;u7(-Mc!exp?iFB@V+ToNI_4FL4GOed!$FVG`?b^kr!C(cub9p+l_4D3p?= z&=Y;3qeAUUA(V5B(a|!Kh1W#RF-FHItR{A&CrOOOUx|Kn>{y9YAoPCp($R4e>r&`Q zt2;R7Q?e8~!52Cyw4Opag&v(OGjSr6Q|Qr?6^8dXg&v)vu$pO$wn&@`p`0?0PL)^* zZML>kC?!jw(|w^cL+_V)Rr*w!iSzcH@{Z0@Oi+b6O)ScXY0bN0sH2ck~Q}QDy(mc05mERN0yA2h>EY?p0Ye5gSCIIi(%-CSqZEPH9IM zs{Cq7JGw|=^b?%YjxJVMO=(A$D6FQmqh~3M>cc7R=u(AYR8DC}&sJD^@)YY=ST3KI zl}0_sH|qJJnsOMGQ`*rBWF{K*N#f-aXF^F%QAaOS@sjCz7I&NFle1*H!e_cVw2n+U zMIF6ZX7Z+}qiZC_nb~4WI=WWkfMmMLx|K}HSu$PcGrcUdpGO8ENpiq}m$Ri4)P~TI? z-xWrou4NNZv!^(9CDFnr=gpp?Q2hQG^=3~|sAup#5q(VMN1=Y65B#{o=mPkCH2Q?X z-cxM1#O-7u9<=hHX+BFL3-P31h<%~iEJPc2<1ffe7>*?V#^?Ks67$jd;auQrJlD|QV1nUA^UwH2SV>s2)_hJUz1Ge{?*j{b%kN6ZmbS(NF0QF3i!Y} zC~=C{`MfD{x)l1V^)rQ1vK0DnU+BA`2YNtgggw}MN(h9uBR-@sgic|dd|zR>=M}bV zZ^{yuXis-|QbIngnvwe zH)n@!qOuN@s4T1l@I#?)y+&=QlGLUwsZFIG8e9u)hMWXW{+u1OnMd3Bb9T_ClrKX5 zoE@~egB8%9vx7FblHkwTdD?h$c1oKH-I@-8`BX`2(=(|}y&gK?YvWJDdD{5XaGo~) zG@Pf6KMm(;<4?nR+IZ7&N}Jxg^)ZD~q&7qJ(6lC1lN}IvDbpZtCQzfa*iAilv(nEJq8_q99$9kNgjp$v*DFV9}_a+;)vejuk?>Eg*MBOAULHJq#n9VMq`-D=YloXAdcYDseHW`r6LDdwS~ zt|2=JZyqXItOx2=cr(aenAL)1i6v^bS-_HrUBT5`-pRCI7E z-&ccn-xjDoB9$*vj@?KwF_kYk>0*j1IwO@Y9+_f_Dtc}zUkI|q6jgL(DhIMTVu~ud zK2;1rZ61pi-IB_IV}X4uM~;6>`g+Q3Ne!veIS*iu_}87 z8SE4>b#_;FB2T4qNK{!2{IjJM~K_1mc&5L{*NXa@K^l@IDxdm$Nom&ym+_4f1B z`oF1sFx?y%50QYL$|uZiaZbQRqk1YI19!za0~gKGQ`s-?h;s@q+F4I!N4YcJ!U0CU zoW^-1{v%O=M7!cS;K#FX&lC3*A46Nq4;~4n2Ju5x*U#A zWf`VRBqyJuGbH*vuG3zpNOUwFrCDZ5^j*A`ai>c3Q@kDJ&64O>cO3iW*%E2GdnVy& z65{IH?S$C2!)dIb?k?g31N(Le9o^keh>bgh>AL&y1i&*S%+%d)89PtHEZuEo%f{Xv zCeG2_R|&CshcKbLhX}EIhp<3*e?M{-*r>Y&Y;5O9*rdA;^6lkZ35V(K5yJB% z9HF}@bn5vMj?vvVgcnFSUU%OhTrS}x-7TgkFO;xFcZU;RB;gF*ok+Ms!dbfeGmEfN z!a2x08&FL%&ez>W!qqZ%k?x*Mc(H^_b@yt@T_fSSy1RwGUn}8q-MyRe5(!u8?o)*8 zBwVArt64SHOSoQluV?I~5^mJpy^Os~!mYad7U2d7uY#>OmfR>|tL~miH8x3jz3$p< zw3{Wo8FnVzBH?Yidn@5q3GdR~4+$@qaEI>xPI!fcJHd)A@=6IG(cN;-LZ-u(%nxOd!vMhaWW*k-J2vl0v{3HEaB(6`#s?;5+2pvC>?sMgx~3I zCw6|@CHx63l<+nQf7RVnS#xfeP&3>`gm*|7Fx-uVcS;yE+?}lLcS-0N?gqB9yCqCF z+|w!d9tkrIcPZh$5@s3h*=#sFB+N0~{j3}JNtiI)uL!!6=N;Bg7Z817)kJ|W?F!~HwqZV4x$yo7rsY%$z-2%nU2 zhT(on_>_dR40kO#@0D;4VhNv?aK7RGNcfC|iwrlw$Lq5aE;Zas2%nSiT*KYN2kG+? zE;rnd2=__2(s18n;uj=bW4L4ZfOt{D^-zPA|DO_WG~D%!eM!QthWi-d%MxB?xaoYb z@0YL@W@j~fMZ)V1_gBJyNqDp2hWM;|Rl?g0_btK$65a(nvqOGO!X1YD1#8{w67DqI zPKWEEC;V8#pA2^fAE`$q{1ugfHRlrvHPa2SZhR_Xz;t7TpGg=r z-QDa7KbO!!EWQ7Qgz2W+jqpneGflUUV}P$D%rf0()|{gf=9up1O#HQk3CN}CzLBs1 zoC&{`u*h`(N&kK)VTtMPW9;`5R+#P^gg;1FWx9FnMSqmA&UAaQUi~Ctz3Ha0ulrfT z2GgCz*k2@UG~HIh|4P_oy1iJ0UnLx7x)%}tCgBJqCj4E(F{ZnV@DB;co9+r$70nPG z@+8x}js3GOVT{Dk#LdeKET*i z374Ag2sXN)gy)*><8*gO!sVv>Dq&c{m8N?I6WbE5G2IfH&XI7v=`JUXNVw5-+jCS9 zm2j)+-p<%G39mBUA$;PbOW10H*mV~=Zw=0#*mT zVf)RI@I}+z%fz`7?l;~45O$RC0P?cI=1F+abl>6gC?Vn7um)RMCkYRkZd5;Pfcq z3UNj8y+#`IUIs#?Hb!sgj>E-pgqK#j?J{J)Msi*a&ae(R&u;QKUn4m`>2bcs=#|w5 z_hpvDJnmns{^3$2UMD5bL_|VJ ze#@7<&ZuOW#({C!o&81H1`eq%BjFL6Z=G@CDY~Y;NT&8O^%fWIY+EjOO zc?l|8^-Y_QWU&-jf!G=$aMW>LQ5PHCDX<2)rNG5Tf3jOg!hICD*ci+0R!@>31THpC zWs09Ea3WZqDg=s~r+vAlpHOZ`DfiGwoOlME_12u@J-Ho?BFZf+_r!EGdQnUx38Lg3 zjpHe1E(t}L%-F+xt5|#LjJ8zwJrH_L z!{v;grfwJ>a>W`A{PH$T{O#ojnEsS!n1b_ z^E~^m-j$y129;z5dROnk8rwvI@a(&KBOQ4r3Bt4Q>SIax8wk>~|ItOueF}uyYi2{< zr@HVgCNZ_zyI3nRDBv#m5)v*Y;Va!Kgt{w0sINzbYY*@T)b6o}cKSw7XRNVlSmg*r zvY@MlnKnW1o;)}CTm))|uu2$423g-g*0aglGDPN`AXF_!?gk`HI%yT`ypc6rPf*2i(@_}3)NWAS$DGuTLqdU(cuQX2a> z5PIC%h!juj@{Eg3r}k)O<;MV<+cj~dVO0}E_JlCix%EC7_y9WQF@n}?ZW^D$f^9lg zt6YvKs*QsXwbG$fO;7@$D zZ;@&zsywyt`X9CNI_9Z;7epRCM(r1YskRLTpyM%WSAB`74w6jOE8DALpe<^B11!cC zJ%epdpN3TZ#FJ=?UMYYu_!fO64cXDiEZAMN+^?AXG&mpbmMJkV;nwYz}Oi zwG}PAbSxRPNMWrIh7lTy_kb^~MG9L>VLz=GX$R4%IICOG|`!X(Gk#Uh4=5 z^5HT{*QX6f3u-`zQvqFj7!-wr?^#jJO^;mAvjs5@Vk&TF06sj`!Gixq_JPYmuNCzx zp%>G$*>$?sxDey^3YdjeOz*5`4Z014!H5~uiogU0HX<;Gft3hcfWTlc!;qbzYzAe> zZUk;Yfd8rvLcv^UAWZ$p1zKf_u=_+D63ym}9!aa8gEW*m73t)I=p27fC6i$J_{fmBN0$sz!+3E~$J@&IEi|C4wGR%YdKp zqbpYnMWu=jC$sr{AnHd6gae@}4jJXuj}J;&KmHAMo5Wc0uz2A70$eo!$#aoVRr0FU zz$F5UhxN69y?t1DKOhRr=W|2)1_;?FWIlPk-f)_b`Is+rUomCQ?}<7&o6T}xZ#Lx( zz*2`7g$~aE7xSPI{VnnG#xdnv;I_k431iBr6e>ou$6dfj!u3Mx2&7veq+T=HE9v!O zl-!{gq;6-Mxqdj~MgdEyHwvi>frq|y5#r@HkWIwTG5xI_nf_kj0ay)jIFu|F$+PWRr!d#40x@NSzT7*S$89-GKI2f zB*0Taj=Oj>cwQsQI21|H0l=F-BfD(v*NE00>WwmPqYtj>N6WgvH8jceF+wh{vjbcF z*NlghUJ1UTO-Q{#@J&a;UV<-^OTHUidhB?g?}lFFdm6B`-6mnX%Ym!9Ap2-3hi>W9 z=*#8R2HNnEEWupyGGAy?$9RYJVX-(xJ#mrbF;kHwA2ESv(M0dh^Mu4S#?wZ?y136#8@o4Od=aEYSaZG8x^QM}X|0-9)yNGU%62 zfyYqGj>r;VmWl0!1qSzl1+F3Ak?A^h16PXGogR0160n!c-oz0*|4gl@~ z9(V{Q9Xg60I!<(;uS

ky0xdJ_&}dV8{`RWLR56hMyqq;KPUxB6_Ug+)FUQMW)&~ z4zBKjx(Gv=J{W!u8Uj+HFP;Ts5SWI*_+AK1V9IBZGMx<gLX>hu;%(WkZK0hJN z1!5Sh`gWa;!dFtF;X4Y(VZZ3g;ZZ3g;ZZ3g;ZZ3g; zZZ3g;ZZ3g;ZZ3g;ZZ5&G=jJY>4(i-ohBfcpTmt{xT$Vud&&?$Y;N098{=WptM7fSR zH}^&I6bDx}XE5xan@i#Txw-#BjDK$KCjdM*m+XQc;D>*TZzOO80O#h?UjDhc?chM~ z++2qJb903duwpgx&&}P46zbeukyxFZE7GcSa~TeL=jNgphn>~Axdi^XxnDsE|J+>W z@z2fu4jmoN&CP|V{21jq_Xz=%b9cv%aqb?G-#<53IM+KjmlZ$Zotrxs(*1LDTLJuY zb9V#y=jOfz;GdgIIsUo1)Y(5bmx?xc=jI+l9{=3jqX7Q7xn$sDL!Fz;a3nxmi(EWF_n2G)s$6{E z%p@TaSjgm8f){OZOmdR4Rq`8|hGCj0nFhI^0YN+tSa#7H;P70wYYkOI^`-&u@LZmv zoIE^tFjDx3=Mp3j&!wp3;klySK^E&EjxfV-^6=cN$;3N6mmqm~E>ZIE-06r)9-g}r z2#4pAcsr6Q#gm8U9wl4v@Lchr@ej|Hx_O7^GA?;|F0=9QTvC&V=U#{Q;UAt$-z5*v zrNfhl=Mp6k&m~G8o=Yal!*i)b^6*@yOdg&~lsr6_D0z4;QS$IyA{?H}YI85x3oH1C z=aLc$&^qne5ect@uv?HvfgB0&iP@fgh*wW|!fzz-j`;lnN&Lfe*}40N=L*mQp*%cS z0PpZz(S+5hxiple4#PbY#Wm#NwuU_1HtlKDr9h}AeIACL_FAM3)jG=%hDQ7^yBEWe z0HZCY4b_=r5YAkVpPYFl^lG;a;YeUTeuGzn!vhEi8+6q&Z(_0)76|Lxlb)Lz;8-VI z9}R^uWhLN`Rn!JCj`<;RD*S7v=$6BS5>=02cIrp;-l&F-(T9kQn%bGml{<$>H>LHPxg#J~CK*Cs||SY`>n z6?PiD1(eYf|Qbj?CcyA^E>X{xw~g|2*XHl8!8Xk~*tvH{fd#QItzw zh15=P)w=Cq&e9ZWG7VH(U2kRf{F1K`EDtm0L1fk3X%tmBT!29S*S97qJ@c-2DHHPfAzx`2>gYwHNxeC5a3_OcSA^g zW>as8!-2iGM80bKZ;3x5oV;Cy+5Ydht1LuJBycu<|8%>`sUY}oiH8Baw?u}$w?qo` z-x3M@w?qQ}Es?-`OZ*hs`IdMI{tq_e=NJ5m0zuw5Jk@x+%6aG}ythPV_TLf-{ttU^ z0$oLw^^aEFTerCPR@F^zaubq}zy%UWNC;s{A|M0^gUAdbGRq_);sl6_G6;fzXp~0K z2#AO{p-tO3;fMpRw%X!6^4Hc+(ROOJyKRT}`|VRhusfOw@PH%UnR0~f0bB(9DkMA830#_vUKbKfIpY7V^jga zDv|o~SBX=B^HzyW`>RB$1gvmp1*^o@LE)|vh4?>@u2Mrz$BeGhD*`=hsaYThR*6LV zt3-+xtP-!pn@+GwBowR?2?eV}mJ3#iH{qQlSS2#=*P^TZ4f9p7O8gN}uu4o|UJF)< zPJ`M z9O|zUSq7`bPw|gB&1d`a*{*y6nGH4HiYza>3e#{$jjNP;)Oe;w=yf1Peq$!2)qLvVsNTbAa6FDxZPO6+BoVcEvsDFA(J! z<1Y}EY~BKqdBFma#kfEuHdr9OPi9_p6?R*&KxAJB3q(S}0+CR#KqQl3fk+{O1tKYf z1tOtffk-G=AQB1|h=i~}_rRy0+ATUpmqv42T893!AMZB{s8S5d{`E6`tZg{ zXUR;<^*EIG7l@qK{RN@`-U3koZ-L0s?HK2yydPbK`Z_AQ%1Y$^JJD5A44Lw)Ay(Y5 zDvV`vjIb(8@OtZoRbhQ__z$B8!m1GP!>WiR*2UA1(@Aptuqv$D5353EeprXKRel8EhgE5Z zH*-I%$`Am4SQV1_VO2=xhgF#hzz?gk27n({Wh;O>FRaQ#0Q|5jYy!fnya7!}SQReQ zys#=vQ}5J_7gps1r1M^d@>`%_J})4^&5o;$t7P@`vhtZi&KhucjP_psL_eP?N2jZyG(jHg3F!DtP_L(A-#}u=@YAQ&>YS>{ygBnJ91=(@G ztbsM>bC82@7V-<&p^8Xah_-vh*}K0ejzT+u^}?#WjC6{NLO-lZ-wbs6Ke}QtS10*o z^uwy`&En8^!>T+7zz?f(Fv+3shE@3pIeu6b=J;V%SjG>lLckBJLWQKguqp)nuqtr- zjG^y_RY?Qz!>Vus@WZOKLyjL-Wgq}QtjaV1epr>20Q|5jy8-xNRS5WDRVaZUR)sl! zSQSd`hgD(Y{IDtqLFR{5p$`18D*uHXKdcHF1YuQ%LDzmnl~<{FH=;@l30=KBCSMJS(^#E76)*tOm0EikElYxkEn7V06(J2O91?cDt`muM^tfS$hZ+zDggKq zRR#j^BdSaUkXCmWYmxUqjBSb{w;XFzFNGx#$cw15&C6!}DqC9V7!Nat`uxhzk%9!l zmubg%9Y6sER7FV+?2jzUX^_$eO!M6dEgM+Lru-_~&FR9Nhf$D?ksNRvinJF|#RBKl zsX!ox2kucU3?Dpdg~kkAM(Sg;J6%{}R$7h86w^lGK9C zCkb+%_j3Nm9A1EADSY_E)sLvM5D9GKumcs<50yR9ObB7g0qGFE^r! z3@J9J4(d&QOZxUmjv>J(|aT8m3SKXA8&J;nhAx5bf~camo+{T?}OWus2-YL2&Y zb+8Q|Mq$18D7N{0z{Sg0vTwG;MW)(NO{l8$Gi2u?yDu`!c(SD`k2{{; zM4r|m1oq4U$TX=+pnk(TaoMw zOYR$Naavk9xUxIhlt>f1AXDq~JLK}`w9&0jqmauV+{9Yiu=bcPw5QMF!{I|zXGbC|*^F#7n<2C#w??AKaE-i?+rlj7s1Vv_uCzizXg6z5d=HX(&swE8q&Bd1 z|*F*?yLdwW%B7`>UQ$}7BA+$?SP8oSkgwUoXMj3fcgwQ6XGV+=Tq1_94 z%E)VOM>(iP8F@{F&}Kg?Bd>`N+NYwm%E)UXgf`o*jJzg7Xb%P#W#lyxLYp;whR*$* zy}->MbIb>#n}C$geXvRA?w3{=(zy>w+U?wjn|AIaO*{9|rk(qklyN)v3DvnaLui`^ z;~e;Dn<2E#XNtIArPyW&ZS%Pz?pZ0d8A989!AYSZ6*fa?n=i&H0aPWYE}X8Jhoqiv z05Bk57MXhiz=(WBDy_2_Lfd>j*$rjt?KR27?hkk4-DQG27_&e&^F(bG9zt< z&^8ap|BSvHYcqtl`Cs;x5OloF5ZdM^3C^LD>>r^y^N7p?F!KHYYU(tf<20Y`$`_C$ z0BU{!S+0>+(g}mQmQqKKE+wE_>M>*`jOR%CCD>36P52Wfj|`N+G8NRGV+=Tp?w`F#K>zRgf;&WRB82u|$b?2-6Ctz-C?l_l5ZZ*4k=H~BZ9Y(yk=H~BZ9W+@vBLxZegv5- zxH9sZ2%%jM3#Ax&&1t%N#)y&Egfkx{8;!gsLTK~(ql~;JLTIy?4H=15MqU#kwEs$G zH1e7Vq0MenMqcv_UHV!XdChqWQbu0$Oa&<;uZa-aWTK3`CPHXa2xa6o&sLPm$ZMXX zAZ6q=&sC5z@|x!l| z69yla1)M&-anesRY3fZFLm;pic};}S=DaROUK1g-1)!1F#4aEKXyi2!LYt#IVXQ%U zW#o;Xk)XcB$Q#Sco{d%;G=_?iH&&cl284vrj#XsibxxBI+OewCE)sG@DMsE{ZT9`l z9F@da?Uj0xX~xlx4NJYwG!4G-yyRZcd*;*bW+4^^t?Wy|M{o7&a&)qem#?Nlwyiv? zJhl&1HiK+i6%GZ{Y+8e@jsoa5gKS%s0)%W@gRM>igl(Q3wW<=7(Xbh0+v=Pmv#8A= z+g6vvesZ=MWZUX0WSKUDY+E&nT_}^X8D!h46>hoE8Lia`r5jpeNSz`$*eH8#-< zHp;XF*-n28HR@>zvYnP7+v$(+N^hhk$acC(kZo&n_<1nN6l<_GH=1WdBnH{G&PvMC z&}NWr>%8Pe$S`aM*|yG4UJn583)nZ#2ReP4i~X4e?@nkghW0sAn1XA z31gs_wb0ATX9_uwL(iDty!_wz`Ai{)<0N4$2T(wjdTehbf@&2+KB+*q7YLDnYE?NL zO~^Uu<$UMoFokD_>iR*I7KKAHD-I&oIx5^BZl3RkU$MrdIi~gzpQ~Z=X0ckkk;J-_NpS1W+se3 zdd1nrzbKAE9{?*R;ZTd#*$E74xMXLwmAC^DX`2&KmA!_*f>v9R)6I4xZ9fd4);^yME=;}-pqJc0 zh_w9!fI8caw4F|I{PPY(q-_F&?G4=lY!nHG+HRz6=8Uv&%SX;Ok$SA{M%rfM#@lYB z?K+T6lGy=~wyA?@wi{`iK|E&KZlrBC+cgP?iV7Rhe1i(llt|m55zzuzk!;$9Ln8}i zFxa#Uhej3cOH%t?(5TRulKlXp_Ok@WS{zcCeK2E%#>u$Iv>9nTbh5M~Wi!%tXuJS< ztvBEn37sMU?ZT~#$$f%?X&1Jlp>(V_g`izH)LL>h#juScQ+DA{+c0G{NNW{`%3{y6 z5beUD%H%spYe|NC4s{m5uo-DP)Ghe~a-#NM9RM}STr|VB8EHGz!|4ei)80w4;}Ni( zK0>_^2&$-PEq8(V{Pg^vIGJtyD-MT zm(BWBwtK^dSQGWx-OrJN1i_c-gi#2ffC8$bBnP%H5KH_$|_HqM=ef_6btCwd~&toNx!A<=zbw zTd0RFuha&JIl9c#@MsG4)WeUnq#Z(Z?#>vyVoMGoIyVQhvL%NQoqGZxWlIj#>B)tF zU`ysKMzVaVC1J3QNAZokOxk+Z*Zgg$}fi3w? za5Kml|bOF(i@@o`T0yC=Pd|=X&->p{JNjd4CFlF<#4J~od4yK^R7q3sZG)R z%hNA}EUBS~Ps0>y;FBj|wDa;gyD1*jpf}tH0&CuaQRmot4%K5mM4(E~sRz(TtjwQ* z#Lnc`;g7L@xrD}4{Ttol(AYRhuWN*M^u~{1 z=xry4>2LJz9KDlaifuOmHzjCCoeK^diMSsxbU>Ut3y5clh_SYB^vgK3LO8P5UM$q# z=^12S2}J4ll<;qQCcjXxAz}xa{#}oAx;WO?$?pF88TBy#(r+!29HS zl~(mSSzM}J+!T)^%37z7ka2ZWEY5Xz3QgAQcKArGQ!e0peHapesB}`K;q%&#`eYtNuU?6F0e&Yy4TV^&z|)Nkf(ucCuWx$et$qzh^xmvt zu~)+peHd%l!Wt-%TZ8_q75ssn_Mxg^5k48H3gYNCHOf9zO?c9);6v4fk66J9&>vL+ zboVbUD8X_>KddS^8xrvqT5mkfui&tLJX?@ek3rfC3q{Zl<1E(|i0*9iO-f06cj!pe z^Gcu|etpp2Qq1dp^*re_e@m%ns?Yo_eK?sfBlD2~^HB6y-2br|+@Dw6pF&&viRkB| zdZnA^^?HhahtK_aeJr`Z4up(%_>NTLeGb4bn*O5hj{kY;_WP5%{fq(d4)QK4U{l9} zy^IM;gwI6PY%bj+)E;puI965W96wV#ZZ$jdfS$$sSwDa>J!F*MSvLudh(;u0euMt?S+q4PwLINjM9$l&B49TWms9@G2Ey36o%)K$3FdpfZ;wk zwjo1~^nLmgYU21qoFw3?)Z>1?;@(SUpNCcRwUWM+{T8L@D%^tTKa7!$s8cEW7FA~( z=&84Sbh}+o$+yi=_rW0VpCdB^ZyD$&66QFD@*-h&8i!Z(*gMfJU zTp*?^#26szW^t~Vp%D7SvKM9poT=t#t(33t`Yc`E-){mnLa0(5HABLA(!{T1whnX2w+(e;>LmW zsQJ0`8X=?q5Z)G?=0w+8NjuioQZ+9VM3hu-ECv(R+bz}Ob1v#?Ck<$+*Hf|wfKalh zRfm2AMBk6w;`OvOHP+T^z?=>hV2ke2GQhNMCo@a+0=IRYYeg{ip|^9f0yuq%gmX}; zWDM`1d?lgbveFybOeJByUds+BJOL7hcpv5KWB3kqJP}{9dHMP*-epsO=*Kof1*ig= z>_3zJ6IZ-9oTAq)lGcCi^Ny>|T}oEcxpCadV6_hj)w#Cn-1^s1I*rn*hcZ+T{RL#5 zKSK_CXfblN0k5+)KgffsA2Nmlr#IfzQqu;?JoH0fwnZBP_Y^wE=?}veqbWTA50ZiM zle~y51>9D8<7e;Y8oUuL{T=v3!fWu7R5KUM+qB22e4sECBH`D8Wy9l|E;l`?aMMS^ z`;pK(FA^!e8!;FmG1~3PSM0T=nn76yT+LQ|EUoxvyyqILzLnRCkEIn`*$VND_3==- zKmAr5kyd=lR3y(3pvl^R{uJw= z>LxI~Lzwtv<5jpQD&X|e77%!fk{|qGiQ4p%a$>O+Ai}3*%ZS4-K zKH7k@sqVd^?pIG%?b9274+3>p?3IV}0kle~d+%_nI~&`^mAdy%rFzE`7Ip7Ehwv)E zO5OK}y7vO^^d;D@0Ap`}MIq$X0?PpFR0w!Skl(LXHNt&B(eu%O8z}5X5%#i)dfmes zz{Wz%d`j4j-FOSXMPX!YY^bC+x;i6s{*>5q9GY!pi|GVK<4ezXzFhd^0JHEbC`oD~YWqjPM#>44tSL2DT?^4idHJ_s( zN5`#ger0qRcve3rncnDF0TueAV-3bY1xP+nBwlA@Xw>!snuCT4Uxn+$XoGe+>?UUy za`0eSX|;P%JKrxz!Z9T-!3I1}H7^r2&qSx;F%C69?5la1yk8AM%LdLmo0LPS#%lp9 zHLegfz74q3Vidm!1y!Fb{+%uZa-EOVI$aI;dV$qI*ai6ZAip2SB^Wdv2$yo^nI{r{ zJ4PwFfT&Eqa;kRMjxqlN&`M#U?pKU zz{7(4e$>*@5}r7K5{?rI*Fr)*PxZ$4QASBPt_O$e0bio=B2o4zNOT>@@A8?uI@=B8 zBR*2=^c3J10=OTwaI^#i`f*kosCp5(?L>l7Sn!kt1Em+?byPcn#!`LYiF~~36NjEY zQ_}~_NY|%m10LjDS1DXLPrC}I|`e3b76>@Ko9K4Q<*J^sX)DIq$dN^{Q4X8U$0<5|ZQ^YF1SF{&- zqre*?FPF%w)$K*zXW44mO4eRpsq~53abM!~C^TA6@p&2Ui~_Pe0j4(rSV`8yjyQ~K zt7^Qo*9l)Phq^WZ^%)p;-HHUFD#IZu5|u~{=Q?@By||!NHKS3CD!2-T{zV0y=gLaJ zowBI}Z5Y=`T*1~$U3{hJ`aV#7S;Y@XOh;lQ7hmT0yl#W-oHdOdkt6@dk4WRcK4H`s z$c)x(b*s++pMR}>pIg1WrAqaqyFwxSCCbdv=jUQaA$}RHV`IJxqrLcLYGa5x6F(U1 zDrlqC)-J$RZKyjJ!|#^m@R5a{;-9mIF0dk}&tIU0i87QsEJOLhGL#>z2shD%+)Z?b z@`GjaQ*^jIZ#E05O>~CZL}#dtbB5Y1XSzPIU@|9j`ouESra03*?R*h(OxGutq`48! zxTZP9X=WHVhu=p+Ho_UV*aMkf2yu+v*~Dux3h*_4@;=6maK?^UE^3jDaK_GN(ooq5 zXWSZj6oiImx<0X33>#!!pIDU8d^3}qu+Ip5ozDcP zo!?F`p` zO-?(r?ZIj12xg_=v@>hqMz~$<1=$D}c_2C*Na@@Mn{@8}CY}3G)6RXkY3DxDv~wSA z+PRN4?c66+=gLO7$iX-VzS;;Ed8X(R)UGzdMV>3V6M)(X7kRz!bRQ|25KW*? z#~aaiY9n0aziirf)JC|-Ckf7>Y9n0ah|B}n2zL*tsndLp(|oooUqFrksQFxE;aTti z9`9kM69#oHrFI-$NN1;`2$kubQgD{nV=Q5Q`rAA{#uyd%#RS`Zw0J{c7Lk!J$Ik!MyF9C?=e4s~%1CJZtTjy&H+Cfp4d z!EQJL!I5V|!I5V?j@{jG5$uM;!yJ$57?BTv%oRL1@~q>=@Q*ypgT_DdtYq_!JTosi z^2}n~4M%KnR$5_p(QY(Nk zbB96SMMYQw>1&YKy2m3XT{C{oqZVZi1FD85yrmedH|;hVAz9i129K`sO*J_pDutcJ5l0u1<15d zbwGB804dG93f0Evg|orhyd0mj;`4J^jVIg%iLHQI_CP&a%hPbxH8adgmxM26kxwYi zB}qQX%|GF#KEAX_?aMld+*WMZA^g&s*^-3Iirxd1Fh0aJkD1@#r}S#}VCBn;H2ENG z;wl8KkPrejZ*kN@W~e8=qNrR*JA0%=LSItpK|HB2}_ZfROz;bJhzGwohaiT_Ig$*hkpf4FW{%`RxE)Dcc^^9>Mrk&8cCv zM=;(XKuUHf#jj3Ly?L@jDSl0gsw}jx$^(OqIimoi?HmHX$-NC^#r6lY0c^^pQc7iq zQv6z}r^0@fU9-86I;hgjJgiRQTf%H`;mb@nw*EatOc-pgRTw`M`;6_TAvpeW(fQ!5 z*{xX7D-JXA?CV+RRcUGqEk?!s0K7Ycng^)=*TN41Rd`ko(r>0yP)EWbQJV&=g!Fb< z96S0;K)2m1h(R2sZTGBW<~a63+e23{J)c9NSRDShyIAn|3jJ!9EjbR0IlVOX2GbQ^ zAzhYB#_jsfM|yXteaU4cu6H<;O1N)LAE46T5_r9}up%v!RuZTV1+X2R4C`>74q$LlGgD>WEY@y$kwY=<^+{Fu|l5$>!w!u1jTG_ zj>nfZ=ofNy%3>odli%9VQNY}Q3aUu(4aO(}Vu0aHK(J#XlejMBKuv}`U22fHi;4b7 z~B~ZhipvPt_v=If1wKmWuY{pO~-PZT02N6%)_Lzx8b0!wM39ZK_ z2y!u0*kd;m?ByOWA<>pZ-y=b4{Pi4(DU?5}((L7#1#GS7^vhwKz%TwtR?nyLpTGF; zvwE&t57RJy@T8~xxey~vJ8(Y7*@xg|kHrh3*bCYVZ!Ll2MWMU);h}Q$0lZ_Ky*tWm z5O&>XyJmwk!S3j@cTLaRg@@&BAVHJ!cHt5EHwsEj2u;t`g+CH6CvvXNs7$b+oU1by zsI+TNs0ChJZ0i_p$8w%VymFb7L@L&qwJ8_d-2orddD?rR37n^~Sl~SEM&!x4I+zpa z@CzwF^R(vxc+S(9{(s>-?Ijea^R#pEKiVIc_wkbkp+3)?FpDF^H78Iv z{}ayBZlesYIe}^4c^ZLbS&v3=n~jOH1%dN4LNF&p`{MrtAd_}Aah~=AdAjBVrjPAB zErjqj5cb>+2eCKJD`Pk0WGEt`9;`d{i6Vd>D z=V@ecZ0BhYqVIg?X|o}y?>voj=r5h89Rf9Vn$Py-vt9WDas)ul4aoAGr!fuB6S(HF z6hFc@DJ7s=YBRD@L^uXrROLMla_XW9IZ>Wxtd~f`qEt~pgVNt2C(7p(+b*+#>p`u` zgP|GEoX`O+2+RqKK;fGc2n6N?Ruz~NphhS#Cy+^CPM{EhIf0acIe}1MP9PMR69@(71VZqj#$odw*ozi?4{F3X z2DMYbiAZ`Kh%W`b0%*tJ6SIJGh&N7JA`LIXa%~4f-<-h7-8Ux);F%Ky@XQGu;*K#B z<$Vuo)K^mvYI2q?T9Lg18j!Pe(W(@ULvma$IxKY;(=M>l6R*V#`2zzeMFI{PI+Dbf~AF=IRZp29{zGp7r?f- zD0k)xkZIB2<(wfvN(<58<;)AeOyOwoa^~l~DgsoIl#gpIL=%>? zstA(~2>N*h<48absvYre&YD;iG-1(%3Cme4fNs%*<*XARWYL7>tQR0` zok%&a5TzRyO<2wb0iqU7Sk9FxI;vAn51p%;Q?<(Jq0=Bh%Hjr6=jxO=q_cR)&bcN< z9Tr+NVL2OfsHL<;6PELv+zN#*krvD-cY#-!)5!(eZw1g*0c|rAqx9Gmh%4u_5~KB!{{mZe zJ}WUsFQNU$$h`r#Rbs4OqJuD+TYz>aPJ;IzK(-cnnEb}+;T8Z}SOn(ltrr7u3^LB+ zn7RT9Wy3Enfh>CaO!`ZUguCHz3!Hx;U3?Gf&`UE;$5@DjtALM3^~%Uw$g(bGyDK9_ z&>QY|1+)cVXc-xRQhJ9>=2`C|UoV$&gfrBvry^DhoMFwul%sbPAZn#?_v@8K_kuNF zeprQLkU{9TkY4W;CMKgEX+!TE9ZAj~F{5)-B+!cc3DkuL^&;U~h+2FtFS6tVHxoLr2)(1+{N=Ke&qH~_>5U7C6h5T!gA2}C9pf&GzMdxJ$r=s85( zPsHreK#WAdWC-v95M_DoVZuZGr3f+#j|wDg0ViP{UW9Z&YwgcuBj)S5EOD0jswcSKysa&(O^~(HY+XJ4r-NU^Z;`5B6z>-jS_&4OO(0O^_Kn z4U*d5Da1FV$Z~~%DXC*El-~ZgyMWEnvpHa%B6d8nGL&<5haK@}VB4>%0a<~bLyZ(q zLbTlK*$@+h@1M|DC)thKNj4Z(^+v|+=na6_>dL>)_pwVeZF_&KreQ+Q( zQv>Ni@X@;6kq2ugDnASYM9z);0HW^i0Qm;8yZ;G^?8!**@XjzM?nh!Z5|vX>=zGlE zU!wpU+AxzXYnamsmR6jPAsy`2<(Ih~sg<*qFM-u+k`(qU^O+fX-4bc@1!!~a>DWv6 zO*WHz!N2Sv1ezpxP5--${1<_)>IW|Oi5juVeCP{b^N?*{A@*BzB~bxEo)JMt;6dNz zFYB1onj>>Mcy^I3iu=0|zJ;)iiv1%wDn288C2z<5vskw6RKOX$bN8=43Gf8Kwdy!e z25V{nTr5-6Q!*jxr}TWAay%{2UC5Poo`Ir~unp;pUtlLa6F(ameSFzfX!W1)4pEEo z^St!NrzoS9pNkf}h*nqbLxRnZfgZyF`~1O#eG@&15utc?;{N}6R86mkL0;&RHcT?R z6l;}l0<{RJehQ6FoZdJG zg}S^$4!t^)TWlI);y#7!(a3PeK-KGj-!7DCRj=ZJS&Xs+7O+&cxdWMeOzMr-qsYJ) zIpV9!_`;)482G9{1NfSQt+0bQb?`IX2BGK7HkhcNfZB|~fmVD8+zCGdM|j9jNYp{1 z6QV%h4a|u#B=i~Ob*PljF#MH&iPDlD#CdiKa_WWsDFv8iIj2qm2bpEpGQoNG_ec!o z>}h__>$dXwF2C|cNXQd#iHBM1CbVI^alQo9D+C!DS!MUtKpiI6Ymn%DDiYg}Sjfcf zNE~9~UL@kvv1#`J62sr+=oY))Q#P|}~gU<$)r<36&(b-jw&ql4Lx_kesb80Z&ADyeC9+X>(!9eEiO z?AilNunRR zA%V9H?SwH%EM_~#B5?w?g~lAqp(ydnZCo3q;=)ro6defom<~n1L=4lYik~zH^~r}%I22uk8R&o7q3DB@fge8MP?Tx4j~Wg|38;P4a450>(-%|?#zP?SNUxR09bVr>EN=kiS$ zWdN{`n)>n`ijD`)b12I6fA3KAPoQueiVE?6?ogBwtd8wav^z!}9Ewf>LEuo7$X{_N zdIjwJfkRP3fkRP3zvfVs@oWD*hoax&^FZKGlwTMEhoUxSgn!SWDC-Lxie{l);82tw zCIW||qzoL2mLV^2D9V8lI22_+2M$GtqqTuUQMNsBDB2xd0*9ikf%~XmWiNORMY)sN zbtoEi?tkP^v`Odw!l9^iuIEsc1K)Qjx(BuU4n^Mq;5!uM?qA=bXbS+oLs8b_I~1kN z$95>%8fAQkqMZTw4n@h}*bYUX!>!;u6g?k;`VK`ohyK!`=$}DNo#wNB`D|CdfX4$5 zHFGnx8(Ub?34^-MV<~>FY*I=@PuCgenU-XcFB4U1Am0S!tw z146utvh6Y(xL!s3dNAfK&#P!pv>@;*x*8O|S5X4L=2cYgJJiK72q#sz23|$qBolu4 zq*qY_fmcyNfmhLG$O^oQ-U$f%sEIrRGFR}xt7vE3h`v`*dC>fdS5f8#UPW1q`>2Tx zyow$sGk*A_S5fwz`tV7wqU`X%tEfCeWgj)YiV_OEijv8%c@-sP;8m1R;8m1R;8m1R z;8m0m_EB>P@q4Cd!QV$sOv0dc3OEr-uLHqd6$#@Spc4k4m<60eym8V=GF!^E2IYOP zqMY1)uc89*!zaCp3cwGa^eW0Bo-h`oyzf<%`U-PvwdYlor3R&khncV3h|JMBk0O0^aALLZI$oXm6^h8d>v)a*1JY;`|K*bvgkg4= z->BlXVY=EkLUH#SRlG;@R!GC68LqL{A!m0aM2YP+ql9GqBo$v@Kzx|KORc=*HQ)g& zdL4s6(~2 z+TNH$Evc>5_HS~z16ysawm0QcDQauAeXZ1^wpQDl3#o%DEzIvy_LeXkEZ?Q<#@2sF zI$^N6R-t_;)(PLDWNWqkauJ7z+FEVD;xI#Pt+rp4rebR~71IZJcTx@WyOjM}_$RXG zcPabL^vTFh7$kCU1*cbH2cZ9OCqkGz5uAbH$xRr}O8kKgo9;vib0>l`C%gw4F^-K7 zk#HxyOdekDjlWPA88Aq(fJf*QZ{3FJ2xaFxQ+5`#_)EwIV}Jb+IeKKU4XQmOW;NUitYYv(M=*j zsm&PP&Q6EZQiXjH$!>Nkz@W=D-*_p5F?LCw!xd& zoMnKvmMIIpRf`4Id zL~w3X(+oEvIJZmMiaK}3t_6WO<8=068l-!8m+#NoT5NTy2g0r`Z zA21UJ`%yL`IKL};N-#I!8vg5cWH!%yT`=$Bn)fv>{N-1m3c28YN;%mj+8v!BWpCq7eATLd?U&WVR;1Nce1GIqJ-A!{IJyD4Ysb+aL>-uN>fneERz7as~og~~Zzw#~+O!+XeYRH#}O z+eFBxj!~ihr1%>UW#WElLMVgW+Mb3_o@btVHte*a6dB^Ie)$tY+dG<{4cw{k0hciZA~4p_n_7lo&?d2+R&c70$Gz$AwNJgOwua%pwJN%`c@T^4-}K=53A}PxIaQH0-ngabp7-+P1}(j~0CgEFRJ=mP=G>-_X0 zu0JZ@MGocu;;0;IMzuVFmg|^Xs?tbwY>h-Q5(!``E08Eaq8P=GVp>&&oED(%R*%F0 z)T?zL$HAEs%4Z{=I8Cox3#8t737&vTV>zKd)W-p|Uui5SG>#hkUqC30<%Fh_;%84| z&6UQAPRAJ(trU+I@G2ir54HuNBpHVr4qsA}hnxyILsS?_vHW1rm%(9Pt58eIG7(^9 z=^VG?RZCcq`ca>$R^S0r1p;cxZ>A#Q5W?SayV9yrueV3-`Js3})ZXJ>Am@X74Y55R z1GF3v6o^4kmjYO&fh$#78AqZWG`Rrf{3_h)Is7t_PkpM_i4CBV2lY~|-Hn(q^!2*j znctlOpQRzHm7g<|7T4>o+3209S>2iI^$OmZ4m=4dwXWBXBgF_HWFTIv%Rt-)xYt<= z@!>Wjq+d5rudBH2MzG$kC&+x#8Mq7YBH~s(aW}e25Irc&UAo+-XOUtt5qB%ZO+<9L z35ee+#A8GZB9DCv@g5O6i`=Uaeo0`;$ejtM8w@J@`yq#CF1(i zfp|>Kn-2nU{B+1)i$ z!$|c5hnGRmuKG%;f%R5Chdk=NQStKhE}xJm>D{!d&p;rue~$!Ze@0QN`L5YY)Lq!t zU`tn^Qq7aL`abA)JQT(XwNRFc&tRfVQMVqFW$IhhT``JKf|ekrPB=sOI#~&x16@^A zjzxkJ3|ExVOEnx=Tce@-eR|3;$&*1IVLzSWKEkfjbLA<}3&Y5OHuTMUC2R%X$=@M3r29b2wRwSguoTW{jqA!MbRhYp?&7hoa4jo%hw9-4U`v|6dR;VknxlvtW^qtJHc^xk{E zHxE@}iUGw2AY>luq2?hxpR|hmS)!LNF94FH%T!W1<-nGmxmA4cZ}4JC%GvlOcpLtW}OjCP&U% zFad$pfY+5mZ|>lMM|TFPVvW+B^N?V7YSkk#kXK?|SJC!NNHSSZ@MZ8KR9SsCa?V3e z`6|B4o!Vr^XrOYZt2t#0NGm?!d^AHZWUWW&A-$KnFTtKKbvu=0@;WOU(5gyNkGx?l10UYsRaYY+5^h35-rlw% z!MC^f|E2T}GJlbcS1k+xf|9-U~2g!>La_G%Jh-Usgv{3 zW%_j5_Aq_ij(>em<*jvC-ct5KY78vQ4huou@4Q)f`8{05TmM~jM}P5M`hGFkJ*xQrv2z*l*AYAVeuG(jzuN}7)lw`>B@74k>h7dI5%2zM)N*_1Bkbl&WW{_5n5$vQw$;lX z(Mx0zcR3iU0d|@`2uc+u}!8YWj#MN2YIjqL(Y-c5p#BGw2v9J zl!BdMuEZLEs?Zx}qPo#3t|!kJ%!N9<(2qH|9sg$)&~kC1PdMssGMi?e?PIpFXjucX zT}jKL8i^*f_&u^_`-BNG7mOOn=AL8@1s;!X)U9I(*02+lg zPz^*oC+S^zFRq5EU@W(W=p&;X`TD4yly{K%C7L->7%vC2$~-W735h}YsZkG3k?_VB zu}iSB)XkjfW!jS2$jp;^yO}5z3D3mvk-VME(?-p>5ta2b-$iAr!}fv2NvwN5#;X*e zVFN|ft}*(?9{1V~6gs|$jz?bxrBZ#us6$gu&R||`>OP-gTeQCZ#i7JjGu`4sjDUZj z?RxEr{7l#j@JY{r`~t7Sc@Pa1s&N48AUb2zL@K4LNjg;>Z}8Eg?XH#oP(3~DI*iEB z@K&5f!}F0pr2lV;8EK;tY1JD~!;a$4{V6}iWa7-X-Cs26PQ#ScU#d7c++cwXQa4MR(!Vs}T< z^qnwt+=RV+Wo!}*Ll0v|Qj>i}q4K<1ppV{H6kde~P3XA%(adoJ7&qBh6dI8~k2%T@ zqql)cxnqRCMtXsCH$8<55swvg%F*~Dv6wyX%LnDE3Qw#bfH zU%=vp0nv?@BVV%?!u*No#-Ab`Y(`=++X(ZVq*+wN@<)Fp^tLA9l@ObjF2YrOGN|Kh z(dx|Wfsx~E(HeUf()et{f5|;eItH`l+hMdeybS5AJ8;Q9%Ye{5n*RZ5#B#?qdIXpE z@RJs_*Ro!atnYBm`ZF%>=l!fNkj~~O#pwD1lBb#(6gf6EQ5wScW;xlGBPZK()X6sa zj2N2{Ziei5UTjuuJrZ)VEjBwLGRn!e*l7Z&lWnm%0;rR1vC{=mC);9k1yCp3VrK~8 zenyPV3wHx+`HUEwpUZ0G3u5e&BqJO<#y(tgKLPdEs*btu}h1lNQs$ViHnaeAu5yaiLsSMmka5Y9_dz+QUvuqF}AAcHX*p%BY1)Y z(ttopXz=7eJkJi(MgIpw79)HVB~3 zxy7zb-3z^`b8fM#np4B-oLj6x0CmnSc6EyC&69I(v1?LPr8?&p+n6&NfI8wRdbW3ajL!q}nMU)XNG zp~hY=+6><6oLlS_hZ*XeTkKV7D$co4F+Tz?cSlH*?}@S3!ux^B=J&+do9P_f6ple6 z_nwINN^nz1j+|`H*^I+Fq>*;jG_>9ZawrEPM0+7`L0%Pk>A- zLZH6@DJz>~^#bHsuQ6wU0EN~-<_r`dtre{V@2GB#h;oCG`1Y|z#+g>WeXLP20?S%H z%0`cgvjv*olHFsC69`*eqr-Hl2xQVO&$o{?Am{z`htVt#tX;?*2w>3FN zCkx8Ak2NK|004dakX@A35aIH53@S=F^|3CD?m&(>^|3BWGOe8YSW6Ul@ZeiX#!6I@ zwzfuF;B~kVK7y@nSwdV0AHfKgEs_+%N3eCHq@&ifdT`ni!%IJUG)iUNBtW8Y>h#%~ zwKI7k>QYX9ted4wp7qidAiE`Nsf9YUtlc1J^*j{zrFDTGB{H4+69_KWgQRcBnZ6c!wl33SAK4gG>6t9IM)Ax`*N}3p zf(p~$egbHno?D7H{&ef9XQJI#=vkG3iqjoQd8Hoj1E@6Jo1M_0%2lM75Zb7qs`TgV z=HICLx~0#dWY_B115mCuJ&Mp~J@Z6Bz0%LH+!jSym#$`Bqi#(?UVVBL<=n1ka|8@d z|DKdL>RIgIq3Ii0!%jVOIa>RAdMTlsm0tdw&SSYQx{IxtV2>yHvs6Emqq4Y05Bq7kxJ{V zsZ_=5$+0M-ocdUABxeE`R5*1W7`!bElv5w;Jt;HNI`uY`IUIi)V?{ajvHr_Gh#OWp z^|3xl@ReLS^|6k~1Ta&}e-G3gPf3nb^#Ug#M;z457hXp~Aqyp2*MyR<#_D~~F}?)4yLpW?QB3 zUkr-0%+?+BBmpgbJqJs<8pcNY5f-aZ!zzlpIM^J6j9ZPzy^v?s>rp3xVtfW#*u+Xe zORs(q&_D&5=`;2N8l-1&sb;4wQol5P1{AfBeH zM@f1ZWjocAjoy2#=_)UpUPno1=qVQC0d_uoTKxfajkHeFquIC-(%i&~SiLd_U|u1F zO|0x$BmEl|pQj)@y@;%_iIsV&bOoXLib-Mm9hN&w2~nKpo4j?lqAX2!;LtlqK~?GR z2%W2-+Vo!Vvd&XbUHUOX*w4Zm;Jt@qr7dI>E%@Ghh`}Lzv?!A^j`TVZ-30xVbOoP@ znVc-VaWY*pN6B?AO15dqmc5|2;Vj;!lE8~Dz)h?cHnB<$H?dmS#LBVUw)%KHsz#gJ z&-P4xkAq+FZh%Z^C5?5+?`KW{q90(r@h9f52bjR(zTIXd3Xq_mg!Xi!sg;sdd!V$o zx9>!OTC)xatg=zIFJ7|C#sVxwg5;gs%Q5ZZalmy$nGURn{1h*(twR zNcWJmWDH4j%x6H>K{$R*vMzIpEo1sH$sB|BfsSXBI8*pOfdbGzM5r9v8?!ln@h8nr z#h~CXes##~^c)iW#oyA+PP6JXjlcLqx~Wyzf;EBIcSfqO9 zjiU`Id^R83kV4zVu?;EbG3UQCq#SKQ=?Zesf-;QhV%#IJpqz%ZZ$T+xhHF8Y# zLi&F!D0ql-GvxmdEGTk+{@+_rNcO+gf+7sZD+|hG%(Pn0yjw7J)3_p8vl2TZzhYeB zqCTSlWm54AqQ#i;t*p-=-GyQ`(X4+WCw`Fty0vsSfF%Nitd#^V79eb;Zw7FQYcCtc zGD}^1Sv%$|6Tr4kX3lZ}GPSHdta=dGMC0qDQ&=@0bnuYQ2c2f|iz_^&??BqHR^JNX zN&!qQs|>`xJ*QhU5WmqH`J0lxk@oF5V*vQ}90LD_J?C_g`SzSk0r>WuEdYFb4gueu zL%_G^P=aIIb8bVgSw z5ZH6R0+dBs&z{o-X}mN7?b&nq(g-JKxO(;+KH`sQ&)E+m&z{4yXU|!Kq;Jn5;M;Qu z`1TwEo;~OBC^{eYPRIY~5L{luFIEBy3^&i7a}w6Jo;_y`b1a5_f<1?TZ_gp%+j9u` z_8bDfJ%@mA&mrL3a|rnM90E=4IsC@w*>jlo?KuQ|dk$L=*mDSZ_MF>5Chcls&-siz zWu-MSi)r7U!^(Yo&ezEC?KwQEMSBj}i9Lr1m#dWqf;%gC#BOIn^Kt>^VgG_8gK2 z_MG8Zss#2NLV-PpP+-qtxxk*orD$N!5fOZQ4xzxFvk!}rz@D?83l`s=Ls$2KJ%{B2 zdk&$%p2PYAd(I)03+y>>01E6mqzvpiN01lTb2tJ5dk#A|u;zCGu00KPrvZ2-PKhxPdO9Lnt5b11ZL&v_qZe0$E<0DOB68Tj@b zmN~XPXI%8x>^Uss+HR0SJY+VydvFEsy%Sc1x4IABrhA8!h z>KHpoLwf2Wpg}zcfr#>kWh3Q&hc{+fw_z-}^QCXkq2JQLp2M&fzCDLPV9#MyfjviV zFx17t<`^Md1AET(Wa8O#2n6;VLV-PpE5^W{vm6lYIYizLGFR}xp7S-?diET7l=$`> zC7Wl@VP0U*VKLfshz;yHH{wR{?K$kE|HPg{CV@SNLi}&F=lmAzMGL+?hZuZKLW?pv z<4CUqL7R$Wj0M^;_)N^?WZ{jIFD3Imx&9p_zCDMtxNpx9z_aHF;MsFHmfL=M3m#P& zo%jwA3EzReFU7T}M=#EegkQ$in_{|o*4vdu!Y=|U`3H;+`X#zK;e5TW7+TRAH^Y+A z?$zCbZoda88@mbG{q<%+)DzJW2(5izV&?0SHNbqc$UApL(@nb_yCka}iHEcFCuBEY zm(r_<2vf-U`gBtK7KqX$xxuzZ#5+V>sSquRu$KU_RUs;g=m~^YvX4yW=;m{%y%boz zaV%@!#meUBBKuqrw!4zz%u%(kW6Aagtp zT8sQpE_Sc&Lc)vL!}>e#qf&m9v1lOgTw!uMm~;_~-;ZgwcM5nY=YBtSBD@E1*Ed_E z;<^fhx{6(bL54hVMC>}vUPm1>e^C*|Aw_i$e1lcaBR{b9P z;sf(xj1P5J%tpZ)(ZdI2tWlrPWmYk1Y6-oG`n2lPIH=z;H~EFG_Y1uxcam4=t!ftf zrxa?=(fN|O47H=T(dmz}5Eq#GOBGygVjxzJB+-**9f<0L=tC08R=X#AF%2Sk6g2U6 zbuY)lLuN~ms(YgLeu{OUnF&ln3Rgc*b~l)_&(rH}6HGS@C&liDeoPBHF2Ad77T#=* z2dOGNAK6`G9B(dVD+-t41|TO_tvD^VkX?9b1pSRZaq^LBe3kEk!3}`fwS{b;w&Fg?|F6YV+`73RjIuVebT?P6OxyM&P@$FEw>z!m%mqj-5OEC+MMh0$2YnAr5k`?&1_#1Mx>Q_isYTgH# zD*@|`pF(DJ6PC(t@7+(Oy~wH*thC-7QI%-D>J|=*KHma$0y1UR?1DV$){9Nan9EXH zUw&)gFTNM6#s#Ry&~~rERedjb?{@XQpspOW_=~^x|JCmWRD{V(vk&nVfqO4Y0Q@^& z4x-$9*&NEiZY#X@++sh0g0Y26@6IM(i}R(rJyMqN)NJm(JQ1)nI|8bmvgpwqckku5 zAP)9kvRK03d&%<0{&K)MF~eAeYvz0~P0|;OfxVYEvzp5>BVq65-AKb`!++UqDhe>$ z+k3ed>Bv4@QtsZ%Lr7;BkK-Eu2A5CplNPi`_!`O5LMZV$lJ4Hi$Ul%yxqB~3o}(<6 z_;Sz%q`9*9GFSFq<{rKGGKp-PdoMR3;V`OzxA)RvQ~_`ArNgKK-rh@xQ3brcm(GUn z0NlNo&Z%6{{BrMQZ?N|EUa}f*?-%D#^y(fx79$1$!^6g|wGPdXi5nDIv`;CIZ{S z+j}`jO3e34tUkJgbgQ@b@){xC;*stqDMj%2Ufv@F4|oL6lYkslb8POt+>LSM(3gw1 z_tIgE0dMc6!x#hJ-b;ru2E4tO4r2^>doLZv81VL9I`c7?VejQ*(3|aCcP)Ucnp4A> z&WHRy&>%p{p&te8y`*~c9QVrsRaxj)UY0arI4jXWhO+lE_vpQsi;$7@_FldRz-hYo(&6LE z+k5FW-FxXAwf8a^#oaeDzA{>g`NZK%e|%N*8^BF-l9=e@m&qe5>P!MzT)k)5&V~OM zW8VQMMUnmAz0+x?yJu&1XJ-=wJM1obVZj9!SYQbPl0{S`35W`)h=>^x1Qiu?_AsCr z&@*Gs;nefY+55?vPsMPYdV1%1`u~1kRnM&VzhBtTXL{@V>eZ`Pud1u7tEyjNM3&f? zWRg_)7qXo$pc&K4NI3#@F`H|oqph8#cr1o`DWDo*Bb)(aBrZw!1+YRomq}bIzzerg z^~*xu!$C;rGKt>^NQIBq18fdC-JS{QTqbcvdOko^Nar$%tHMNlDWROs5 zWk9K6fmsH1f0bHY5H6#F0*3K?M`3aQ&v=ne8%$jCj$gQ21fHjmU>_O!W8#%SLb0dOQI2~og)=mO1 z)LT0Vf>3YmBuM4d*3K(DXaG%yATRR!{LcO(f96%82t(^qPoZi~`5tK-U zKcURn+Q~Fkq2Aj0nGXXSb{bjL6}EPgn2)x0lHJHhTRVH=kznPct(`<(KHAzz6y&3= zolKX?U&1`GwUejjX7bV2PEjErZS5rLl#jM{o`(lwUDs%9C%rE<U$#Es2ITRYhTCgksC zJ#R6~SizI?TTsK?+PM?y-p)r`J6ZOR^U>DMS0LrHe6+QbIedxAJsn0)i`!Cc?d%Vt zRPKXi#md!70aCeoDL_@OUJ6i^tCs>)0x^BU`S=zJTRZOsXwK=aoy?~NK(=;L=QaS@+DX&5 zhk9%0!$>nWwJ!ys0L%p^06$qFa9!?ED4e04|R#-yt zd6Fakx#7Q913RVDSZvgM4sP1CoaIyFLxEHSX6AUh)S`WblgC1B+m{c zVxc?mkQDLoJS=%G&=y4=G!Tx#)| zSjNsGYA1h?$Oq*58d&P1t)1+}>!Yom0-~h=0Xu09Z0%%QZkTp6Mzkr}eqhHoaPoiX zHc--XHc=Tvh<*q+?jT!vigY`+3u_3C{cZv!qbXmKau#_iH03i;y4901 zLQUmvI3b#-`XhvNUqMYqn7wXAZfh}X(c@dnYgco-TR`Y3=X;D&geS=%6PBaRDyILC z6CI`2qe$KDUpFFUi^^pja=~^=Ot0*Z+4Jr)2i{`tM&N9Kvnq~t!8@AS4j_TUVh|RP zFdu{-&tOn$4pP~kPJ+iIgB4*j2)zzM9=+is<5*)vBbDG_yIUir7VWU9kBPHr=?kUpe_HAJS>&z@u_mESP@+zxEV21Xr?tT|B!`Ge6@n-w? zlGjI=;BFS{y*_|hod@P-zE7C1kD}m*iL-r)_xTRIp943nXSv?2<*Q8WytOCwA4&eV z<^7}LR7|kVV*Go8jsC9^d>~*rBK!YBJwK2k_H^Q>h(D6}<-}i-|09V%oA_PEe z5|1GMRPc+$Tgm^q;BSbZApSyd_B7y^$gd{YhZ3JlWxtmAS;S`w&aki>fOk7);c$LgLTUa|ixt>f$uiz2 zuXNjwGusy+-rRg8<_(4{ItmBZ+}E3>tKNvJ{3oq*-!R4v1@6BWQ$8T2TTFZ(;~%IZ z|H;I1{?-GsXmkhxlQ^8Q?+BL!CcjngW_qX6re_5x-t$ zbw559N0)$RZay7Toy|Gc!}>hA1|Vg#G~x9Fh+ih=$xr5bxuO3-oTDb|XE44JlV?Mg zA9Wb8tj(_Q+@>TGv zLaGV$6`P_$PL+H7GGZy@)R|Q7USL(osRt6*pA{8y>XF2%kZSUM6yj7Nr*|mi^bUpG zQ;cym_*5Zh2!0c|?fqU+As0%a5@$z+JV5XWV00zi&2H}Q{EX#e)~~twBK%Vp952FF zlCR$_w9YW+PhhJPwr9aM^gyBZTZSfV&K|m%W*)YOpgG3y4+#f3&m)QIT}SYY6tlmy z@B2VS<3)ZWd5ntLN2q4&QYPvm4QmZpnuTQ$?w#h7B}SIA?uSZ4%UR)FhKbGQ811{D z&#g$2kQAf1*Pp+{P}3RxJ%)>4;ujdBxIW5X;>wc5C@!(`m$D+8!Kyh%iQ+{3jna8*z)#GE;50#_*kwk@yT3pEK3= z&`KNi9Jjs$CFq7=Eq)=h>TV=_i5h@wq7D~5Q=RCIu+N!lds7YBldi=C&Lq07GD_#b zfJW)#xSFMFVaSrwt_a6Uf56o$-5pokh~0z;XGX~w5i7oMQ)e>8=T4tBX8TY`FgM?d z$n*=iQ_atF7n3sENDW(y|L;3HPmI25;Y7P)dcRA=)C0oJcbw{D#7Hj=IK9J0MlY0o(u!PZTrO(?KEmnYjE!Zv#i*q(3} z71$0hustD~ogi#G)`RUqrv+?%McVZRwg>Ad?G~_=FJ5^xxOO9cPm*zJz})VnkgP$H zahhG}y1jvH#<|q>ay)0u8=O~HN8_t+z^2S|Lp|AO!y{f^8gAZoZssC(s%vNr8?7TiL~e`!d;M!0C~KM`G;_?q<{XGpm!P2%49X zq2anDc|QPe=05VCEO_d9rcrSWJCyZ;;rl1m{dBakM5Cq6^aoSf zTf#Gdcgg! zm8h#i^DwCzKTt$;_Gn7qpxEBXBRc% zo5s?rnu zQr? zJ3Ya$+KBG%87Ej<#@T0guLMhg+k&&t?mmJnI2PCs)K@{0azz`_-Pv9S;*=fdlrgL} zqPra(3%K**HHc9g(cSrV{Q={sr7Cy|=-U!X&hNRhclSFbVBy{{ksYLc3esb&#R9EV~{33%J_9K#G&l?$-2R zO7b}g?RNAp;NDQy23vJ9G6#Y|ot@>vzW|AHc9t9Y7szrF+J%3C3$Y@i&dvhL5UI1X zfI1VYv$NdDzd)9g&@LvSuf^S@&dzcp{{mS~Lc5WFfh;GXUHBLH3H_@&JIjTCfs#0y zU6zy3F8m9W1F5sK+{nK`b~RLYBmV+fPC~ozFTniN*;y|93sfVWIy=jSe}OJQ>g+5R z{sqXX&dze-Uw~@{>g+7{YO|aTL7koDViKD5tj^AIF$ujlN~_M!a^YWqWmjisx$rO0 z1}W<7EEoO-m;?8t^R8C=(cK5UQ$Uo;eXv92YX1UKxgGrrxE=iqxZ1yfs@%sqR_^1{ zAk=qI3`_bKw{sr9k6R)8e zEB^xSrvY{rYX1W6=SlXV%D;dc`4_1A0^GD|HQQ-5%T+CK9q2IgHbm)RbB5v2qOB#> zJHJjPP^Y3toD2z}^&r{bgDl#jLnb6uYxbSwVVEW=@*s5*1aULKvP*A(ZR&UvHzq_F z4^z%fyO^6EjS{G{vs}0xI2#;tc9x5|X##b2mK(Vp$Z~Glh1&tS?~oVUU}#aWIy=jS z+kp=#gmcp_+zt?^v$I^d9UxL?XSr}YFb+}b>@2tFc7Q~FDWw%xXJ@%^JHU<6a(0%x zz*G+!IXlaZ+zw?{{<2bhf8)JaumXSr}Y@F|6HZrX+00oEP58zRh2 zv%=NcSuWmYatht}mFhZdihHS9y8 zb}~pJ8|69z>E-M!7j6gGxy#vEF5C_X;M}wew*vw=H|=6>noV2|nTl7X@$zoOR%3vZ z$mH0dVrNf6xH>nE;VkL@$=hA0bMca-e9Bc@&TG&lcRwgbuFqOL9u4L7&L5Qe8ZqMa z&L15717Q?||Eh0bFtivg@3Veuj6yQM;L@4zv;NS^PM8V^EiO!X@1Ya}5D?RKH!@uj z?#vfge^U+VU6d;RB_+uffOXSQhTOf4P$lf{ZnG_tE=HrtCES_9^I1+VLiDEe;-@XvIUJLDHqdExYWo`B<`y*jCKUm_tQ8u@^2mn+^lh67Z@I{RQ)ww{((MsF<` zeOUYz8hy!PBx+NM;I=)#Kk;ylGbjY{2#ryww!MKzDr`kcwksSrjr@>95kE>{+^Vek zp*EfE)Ke3s#F&B-KEM+cE^6F(>Q7g(-kg(5k@UR{GK|#+{mw+4Ln0* zw3HUs{9YQPrR+Kwc&5ftOW9lFQlsmUOAj}KeKd}4uYDDEJm|xkoTcMY(^J?|_tV%h z@_VtR%+?q+{{UO|9E~j_{{-zhSL2wGKW-lIJdI0?{Q4t+=WC2g`kK}RU!{YeUtbgjZx_OLx2y~LUDU+XZ#X{ZM2+csnk-9 zQHW<)3ClEAN*rK!Lr(S7M75kl3rZXwUxBFnRcxLsRH9U5=_3@zqHum2Yi^~&CM@$k z@sSE!DwE~*naqSasZ5S4WO8i$Zf3HMiH=i=3cca+3PUxv@nh_lDTI=gkkthtC&eE~ zK}ct|(Y0C=wDI}8o7ZXF*~t66u};<)ZT^_Uf!Aw{Hs7CZc7w)f^AEA)r)Z2ee<#g- zs>W#Ze_?*7DeR!l_GBB~sBi+kNhjjdH9y+i{%mt+C~Tw6jGhI2rjAFOso;&hNn^B` z82QiASQ%lB{RT=}PfI8xoKrBu`SEF3$;&sfp zgo`zf+Snxud#LUU`G~kwVKeH2FH;y=ux8G)mm%kRYNnL>O+l$E<4;kknN;E`oe7lM zMay2TF_hZ00C%U23D6#J%;F~o@bGU;_{Z`|s3%o^PJkMFu8|;~oT+f_UrneO`y))jo9GSK< z)4Q|~WZJqEc)P~PG|7JVZiQ3mm)5YP_vm;$!T2dtaIeOAg6+wE^*)X91WQrL`!$Xp z4i6}7<8J(dH`0ST9(Q92!s~$6aV~wLq_(bEV68@}lR0*GI996<+8b_7zxyDf??9@1_gfBFXD&b3wqe}Qn z4w#$T+AD&e16NK^?wX&hC;zch|2;b)DbO87HSQ;YNgVqfzb%FCvr~ zjdDxGBSP9}lzSo(5mHc$H-#S&N{vRjD}soSG#cf$2qQvhG|GLEj0l0zC^trFMDUG9 zxieClpljtH_D-0-o>kLL#!+Ras+R6}B{JiORAYma^ibJIP#2?7x~R&C&>7mXkE)6Y zIeg;Eo3uJ2bTS&Hm#T>fQRUP|gs5^lMTDqwauFe_oX!y;s+=wnA*vi~=utHuRZc!4 zM3vJuB1Dx_9}%L;X^03>io3r>R&w&1O7ai`w}e2TJ`TNvNFz*})Eo2&kQxSQ$9EM_C26L6{*^pP^_Ir zX1oi=J&g~xL(%~{A%>KVosR%vaU>d*k>jA_z=(j#ka>iIG{J&pm+}dGaKr)29!*m( zi3qUlc3O66M1W-nFqdT!0haAdjzcsdkuVxfj+YPB1j{iRUnJqMD2Z(}_M=snM+D1g zJe5!8!y`h>XuN`t+7+4*Q*CykX}6)^^)!vL%F3cuj>1{7w8{pS`DmRGuPluxvCST% z3D`y7`1~Cp9IFYA61~c_FQI74SE7$EiartUODTFAm0Y6}V&vNRH=5$4h=3ZH&4R9t z2&jRp*-+PMLQdti+O#ppW7IQ4mDl=WUZV%zOq4Q~w(>1|Tl1?@4 zDU?KUO46BHQsTQHQ}%opECU>H*kU8-?DCv;<&7-pl9b!VU$X%chq#=8^8BZ1rLit2 zMgo7IvA8aBIYE)~ALk8xn9CR6jK72Z^-w9@r1UpRXBooSHUUA_qP@mpC}Pq-YQH~Url0_<=(aBcBFJ{aKdE(cJp z*?IE-%1xI~^0w>+bAkGrE}tLm**}nR57T9TH8%ST)thKa0VibF?E^GPp~=}7h$bsE zJ^K#P6oqDHzag5c(5&nVYBEisx!G%prYp1{`+K526`zo|LdllnmDYQ0wGtqtuZOA^s_5}|Y%x`1% zEOs_?6xx)%ooKE?=Vsp}!r6A@yfC{M4J4RvCSO5|xHS7G_FDU^xVN)cuo4z1^ltWo z+klQVUG^~VXD2NNI>B^#XMLRA$rrN?rpue*v+R@X`cF~mzRXH{-DJ9Kyt|B^Y?dDL z{s1}3bZx0&Z)XR4mKkHatR2Sod^Xk%2u2f}qd>w6tHW>VFld{y9W%c*H56m{8(`RK4u_yeMp5t_7+$OwHkj*QSx$$Oxk~j*KuyjUyw> z(l|20ei}zcn5}VSggF{VMwqK{WQ2JdM@E>hab$%3HI9t1Kw)i!J>#8F(t27#8DWvW z9a3SXy&s}dD;FMPguVQ4aKjiW9GV&q_j#LGsRNfUG{WgVn~Rq^;Lw#ucz{o{1+?I@ z__eg))$BkHQKLpKv+(I09;!!?u+VM1p$}8I1QvOM@yiviQ8(;T`w?nLU6h6^qF2rE z$aqyFGC7aE&?+qy)x;V7@F32rEorA$HJZV*bz zO6X+;p_|k9B1$Ie!Yi~8m~#$=Ua2ukHiDh*RSG+3rJRcouU5Delf9c+r&}~XCVT%* ze2vCfU|3GeT&pn_7;Yinsxc<+?xJO`(-;$X9EXM1D{Lvt{3d*rg%mq5uGtga^%jzNiKRPsrM<0_L!!aO9^GbfeF?+Tf` zkeM7(!mB@;2nU@sSx6Je5K@>tsO2{h(A+M*;1-0vu2OesKZ>U6E{*#;iO@;N% z{#tl5g;0_b^0pSz5}p>H-xCAszp;4di{oCy|C!+OQr-)e{~@b(N&aC&#yI(?D!XjwH-eVzeUdVw3xEvUkjD-UAn0kl#;IFZz>UQkacVp z-)o`K4f2D+<*J!{8%{vVdP-J8|4|V7Q~EOsUBr_9OAA3sxdssatT9S@GE4f4!st30 zrR%^~T{j>D3w=l9zBG-g30UlJyorR8h~OHH7cq-iM8M1Ccy>=#M8K;qm!?Bo6KtjW zKSQfGRHy#(+7`N|(!IMCCd~9`L^f__R=!Rb$D8?l+Bt|Mf_7 zpQ0&Wi7qXQE;G|FQ?zs(Wp`r>@XS)SWiQ)_C}oziaRk}JS&&+@l=Yd)ih&x;Qra_xEc7G>h-V-p^U%&?a zzJLk-4+I|wnC$16=0gF~{hkCL37F|0#e6;%Fw39Im`?=EtvviFj1F5(pEa-`d&ELS z4NzQ3`F({y;QZq5HBk76Xk@=pm!`?ImHh?CXB8;GoA5vDp0eGW_xI{pkzk?Negv-HhyI)RgoZxa$I@ag=dAM5GCit8f z2~QL-+2_1SxJJNqpVK1YNdjj2oD~Vz3Yg_{QY2g_V6M+Ok?>>z3w%zAgzE(?_BkUG zZV<4<=Y&Xjihx72=ix~hjy2s_GrXi3J=uIbj`oT5jzEuhM0pY0U$J&~H)FI;AGNtF zIX5{T9J%vSFjDS}kej<|O1ZgQCcfrv43KW52X3;B@zZ5cPq$JTaWUXgs3%qIn8E-44I5gQ4RJTi7m z2ezY<_5I=1a~c#_+t{?R0^F0D4uw?X;-<04!uX)?tb~4Y7WRjtp^X@0%5u1zXL?*c@{yGBw24;6wl3~L?AIc}s7GU}3LPGK!0iM4HGdeeU z4!8pUehNCTg88KIBqT9*3gw(1I~}x0lgpCj1E9kbqV__>o4Kc{c8)t22I&nmx$CE1q!BVs!FqbU03EcI;muVR|tX4iqO#fVKf z7U-5(7ev+G1XYtSo8{Ckw4TGYUuV9ll^&Ah?o+)dF*Uu!40l6`$8|>en)a#3G^v?8 zod0qgaV^jF#p5T@GzE7nN*<-UtHjxpsSdAWs!tJ#R0i&(x?DA`(=AK{ObQx5Htk;ou(3AxDr8L)uxj3t- zR~~$+sHW2UC-0yJ;;$|z{_1ia{MDroh*5Z=Dt%zQq6HQ5K58_rdMZQC3Qnt@N}Uy) zRy~zED>%JWx(0PtaC(^lbyjft5CQtE;Pj!fhmnW)t4lA>G8^$%mtK?RR}tceB0S>xJR;h~b)uLG1x&y(>p` z>63G}3hVZW^@RfKQ>c8kIafT?rPt@)5!Ux2*1!Lnl><#fJk+H( ztvuAFPsue3L+^-TBpE0{l_SxT-WabQgc_iSy7cKGTQs~$lmeU~K%EYpK2v}?9XP#7 zfI1yGeU=zqoerEnTYx$pIDJlL2sBrx1E9kr}S&_B`h~R)TLj~7g$DM#ubl~(` zvB4m9riZ%pAM4IVIJC$#z^KNDeZKuX!l^~romdv888*ru#eGzkOz$A5D_clZn*N&T zeU%4ecH0R2OBY38q#``32)`5vt>{&lQ6ke_C|!Ocy1eprsWkxpKaWJuu--eFBV#{28eoF})BgtjR{1IMvk_C` zzfW+gFK;_W?2_YvPAh4nw3iXK%HK&nPifW(i1;rp?eWzB?`mm(I|^WjfD+$iK7SH` zM`imep!Z77fB@Z-vC)Tyo5 zx_>S6m|&*lR>>|n251k3tnAs$WTHY|Hp>D`QYgqSXS&G>rLt{AQxwW%OPJkMvx@3e zWxG-FX)3!;=r`r#WxMzBpiVbqE|k#EtjzpmY6w)Xby?y)$QpdV=fl`D$z1Xv264JXF*C ztr`C(L=2e%;=70)8pRCT50tk1$8_KwWDnT^ybEkYUO~XS0D-3w=!5|NhSNdX>yW&w z36gIy<5wfg5m^w2)Z@}Z_GScTAuy6W?ZbhN1{yUHf!KK$o-}G-34FJveK7)8B5K$X z2(+)kMbBgEPB z>*Jz1cdtj-s2fS1_I?O&g1m7DA+Q}O#nKb(`A9kBB+$w)f+dbbpc?{h8)3l$SF=6j zx4^=2H3CD)dJzIs5x|F1WSl)2U!a(??Z9X+Sunwz3)ks&h#UPED0(9lFi^7gT>u9m z%@|hqLrC>3)n8Ec36)@NABV`1BuY*1!J00x>6$)^nX{&^V}Lb%KLX6a9Sa8{5NZLK zizBMnzDz?4FGFAtTDZWaEi4>Y zBVr9%Y2ot`fQ89;Vn;1e2sTX=!-RNa^b2TFMnA)tI2@Y12yhb;PNJFTBWWFC%qz?~ zvGK!*8A(df#swa2<5!qHZTvX{wDG?X;NRqlu-EC(Wa453E<)gVzTK;myrj%9{P~uHCCR$K$3*sMC@g>Kyeo9v2IyZLScWaD^tOr)m zt2!TPV8+DbLB18_Z~wb=XMo{BFx24AgMR-mc!D{Pj&>$q47O*%*79#`#`vv>c>^*3 zU*bzoLb~_SrLbHpRl0vK*W^DVo^~24kvYl?684W`yHvRM7~svdzpu05!!O8ajXpAoQ1cHOCEA(_1%f|mXZMe5zF4+|xN;nJLX`&wZqYEYKAWxV zZJwdv-O{`-Ox~xnrH$;?M>LR(2I|s1!ck4%(A-qu>f4iC`w3UyVH9D^dI3c(`D-S2 z9kp3<48ko8qN#Gf%B*d$c*&QU*i%vTmnwSJA*iF0XEL#!lzs@ZDtV?^!mQGgXNEE- z2;m&pEc!euc{~%#!dQy;@j*r2$J>Q>)<7nFFcWJla6Q;s7TGk27@up0Sk2RI!O&z#y(p-;|YfUD`2fLJgO@A@N(#6MuK17Vg{k$b>#w%l$ zq3TMGL!qMt$2Aud94D<@46j4ZPa%Ek&Vs3Bd(l{={SKS3OWSoQAkWfa}ntQyR! z<7jdYqK8H?#ZEP%M4js4V3SVuGzQqI{)Te(W7$GaEj83=hG$YThjMq3la_cE0kK4Z zO-{JM zP*;2?^o>N`XK$g%%RoDe(PP@cI25t7sLlQMvy9yvwCgBk4+QQPHr|!vz_x;HPujJ6 zXuVz`8{6Zb5s+7l0+-fHIH=c;WTjro--uo}Bh~asuLtZQ6nP(L-55P)5g6wpb|W)< z&|bjU6F?h**dd1_FoSGjujP@DhwZx}y_S)UdYz1b*sH*$^%4&1MGn#HVoFpZkB3Ny zRq&|ouzq;!-5QB}A`)5P(jtX}BHxTe?ktMLiB0Nue%#(K5?QiYYneqrv@CFGk-|Zd zy~s-IjX(gSdsctN6lr8?#zWqKHeV@kKxVssQ(p|Ot7*Zn<8_memT&4q_@=%O#ql+L zIRYceA}{J2fW)SqF^2bOfC;vXgkpfpnT9sK9Rbm{z@@bn4r==pS*h*Y2tZph>KAo+ zABx`6$8gZN5lX&HCBKR|r8u;sV^mbujH8Ad4?g`o(W3a_Ix|pA^|d z|1ue*As`v(=y-egmrCHX9B+{&r=Vw?0giFtDAycFG#jM7K3mH{kqJ{3_>|&SLr+h}@`y|8QuX=#9=oQH4uX?y++~%Wo7&l&kt8$W= zy%+7{9>ZAB4>g3pgG*wV3U%&6Q-QmiJNU1}enI}Z*TjGjT0iWdXkRYiYnc6}|}(rSNfc8ll1aoJ^WP0yhu@yBLgCux++F8hWuI&OkLw$s6&{IS{a$3~*~W3%Cp zO)6RZvDxs)c9#olWO*nEP=-kPV*~0;r2Mhj@W&=COZ>6f@W=KH?kwex&4xcV##MjF z_aP~TC6)WIgmvXU(y?+M?O3^wb*$XSC5^7!r&Q&NKQ{Z>1RK8c$7Vm5qvJ8#s7f1YH2s{FCpJEb33 zY*fWSqfM*XPODk2YJp231!jH$QIS73hLwjlN%gN^rxK`By)K;eCROzV#Lx^KlS#hATF?<&YPfUuaRVa>ZuD6`O$}r?_IX;fjqwxni^7ij7FQVzc3j zjSouYip_>AwnacVF`UE{*tFux6`KuLZ2M9yj|s8iicOv|;)>0ND>kJYU9s74#l|@0 zip_>AHYTGhHd2)AHrBOr#b(158fUh*oc%XHXE+kh?FZf8?M-h;EIhc zCJXUmg@P+KQbLQ?sbL=^wGKjeA>S`m!G~oHyN{@y>@AUFyF)nQH$HFY!r%EdOX6O*U$SsMEchfG{-MO82hjY`n%-9 z7-Jw%d|~EHpxAF2KB(dnhCgQb%(B-Q{sbeS_!VVeFuaQNEu674Vg^Pe@$1SSWcVxc zY%6<);XdSfxa>WKdy?mg@*`oeP7i~gxID|8JN*;Fs32#6{My75d^);w*X}PB-wfk=;VJ3wf#N<8vM7& z)|7q&Y<>K4g1!Om-Ryry&>W}IEr!Pe4@Xd!FSir1X2M(w@{L%3YGA21Uk`@PD^{&U zOf75k6b$7$AG8>d4hxLy0lUcbdr-O*>c`I8ep21-NX>M4b2bm)&11drTXRmHt7_XZ zYVUeEGU6{dCosB|vA$2g2v;>^uf0zV*;nWx`y&>H>>Ny%bgk}>9AnmCTrHk}YMH~l z836VQ0JANeS_)v4825wgqMG>#JC?n4`6^5yBe&Swl}CW&DrfetXOBi}cT?82PvW0? zCvep}fvesL+!A>waMe2j(!GV&;(G3@_*b$DnOHrzq1^DSd%A&g0w{LhDpZRR{{;H- zO@JAeaKsO9$=5Kgq~ilqTv`zd zDKlmy=`DFKu+2^w-jXTCusKqPw`2zqmQnH-^waQ`%w(lj$wXMzd9_sX)}E8MAx%jW zvVn`_Mue?F2v@;H@@JIHBcI?RnPC}{!$mT4vFz!L80-^xHV^27i)4bp<^g?hkxU>% za=1wT8p*Na&7v=Re8FxQKjSB*fG8P~!$tBs)P>C6WE|LjSwoNcbK*r_)eQ=S?m@1pD$KfKGpp(r5`rsm&pfDtdi{z)N z1Bc{rk<2h2{yE|OaiS9FoghEQ~o%z7@mNap^lqKjmf zz33vj9a4%el9|JosN4@A&60Ea;3D~S5VecsV&y)hZd>glnI+Pd`$)&ieY9icKGv~v zAMaSXPpQhac}^c(B(vey**vEYE|Tv@?hQ82>4S^p&j5PZJf{yXk^>Z^kIi%X;3Byj zK*2>a8&SbUGIcJvNT#CgHizVJk=zGq#@ZZ`!$oo%K*2>a1x&DcPM`apC_3FTRb|Amz9PU#0QB>xfIv}rZlX*J7LEs$!!%(pOW z(|Z8-T!!J8MO#a%9luT`P^a3Cs0;})>rt|Q4Oz5BhfGMS*6d%Chhdti$b-~nAjmU- zWtZNdMB&L1#$zXPkvtA1D7r{K9~=c2$pl3g$;?WP%jqIn?mOhgHW;%gxacDJ6AD>C z>tS3@P;`+@RCJO28$=adB;O8{G6E9+1~#pD(M57wG%lx$WO>jOTqG;qI4-A)WX2U; zBr_TI|5>CKT_k@&VH}s!MKbHI=pvaFUUZR6RCJL{RCJL{Aw?I-R6>o*=^~k&MHk6L zMHk6LMHk6LMHk6L6O4e(=ARHRR&b3P9^V(UNQqgrPAxkksdW$ngk#o~Ajd2|F>Bd} zMD1j#MD~>HXe!L(`{*K>oqH!9-$xh80yr+Gi(~Tz7Y4X*P1*Y0Hcf1;ENwpz6~)YJCUV5I>j~>UvbpiFWeU(upeWZ=J05Ml>KL>=`Rn=jQu*n0G}tYSJ|tWW;g#ffKK*9 zl-5%EIzXN6Q@}v~9{>&Z?-(;EkcWZ&GX)G50e$R05wwbcX8S&-8RFN6=(cQ*V*R21 zXn zv7aW}1ObQIZ;@>e0V`~uV4{Fk_Gx6BB)6joem8F>El! zm}(t;F{62F{Js#)5E8zGe|4)4I}*XW$wcYj7MLW&;vxEcB#&8tjF_rW;TU@)k%E#pFSW%gcy#uQhShH3j zN_cn=bl{T!z3051OlHV?NeNk z`e~`j-$(4EDt6%%JLvZKd*Q!4;^ZCj?}D|=Z^2XBpYcUIN{APuYb9c07UMfN^KM&I zKS3xzLY0yjDA;aBJJmmo8`Io9I~ZX*b~_GZt^X@2<22>BJh1g^+{xyI@#JY}Wb7U) zd@AKkRN>8}Pf}qIvnu9f72cO=rwo_0Lvcf!Q&spd@=sIY_2ii@;l@4;Z!#Bbh)!_o zoWejy-rYC#VQoBv$%O995#2*g9AFF1Yt-XZb4DS}j6#}IyE4sZOhb`{G(8tE&03Q- z7+XkpMj_qWeoPm?66q+mnC?`T;dn_msF3c7Lb~G{nXVVpQEVYyV}j*cW%ekf`M!{5 zm6U4|(@6MObv0Tb^DAQ16G0pF&-x3q9s`Lq1^9yN~^rUWQF%3l) z(@bMsEOLHcAEi0JkY-T>)7;856j@Aj1$CR}>?)*rx{zjGU*1eFF%3l)(@dsrvm6|x zt9ARakY-jR)9hjziY%n*bq&+ZaGnP-3r)<;z3->CGx}36b9V2q1nn(o4i0zdblRqUF)$|9Bb(s7qdAo8fNS2!XvDD;`r6zwYHTh$y z$sbEi{#a`A$5N9&C0r23AzK@j3{C`DdLpO+F*r91OXh}53fVnsZ$;QHP6|1Ft2nN5 zI4M+uNg*mClR|Fa=v7B@x zz5thcgc6h)Gkg#4>*Ij~P71kOU5YURP71l(?7t$cCxzUbVoVmQNg?;uQqhBxLS9x1 zDKl>IuGPnZD~WAmm_Xu;o6Hq?^|gnAkdnC~uf^L55OA)@8&uA)k;ZXa-eAex3OHBf z4fd&t7jUk~8=N5s0?rkAgKG&=X)ND*t^O_~&mcpbx`*js%EAy?3I`sUEAraB^`Hfu zEAmFfnHaAZ%wwbgE8tv_*Dk;dI9KG25)cHOEAmDQNCliL^2P|r1e`1K#tNtkI9KHD zE}&Duxgu|zfI6d0E#G?6yl1Hc=Zd`P35MZM85eKQIKkTT$EeU=2`PbD&f~PaeFR~y zD83iU^)^USt}aGO=8C-89uLY=cAQhjun};s$eZi1kXFFCB5z*2j{kzWyw0y1jDH(p zFN%xv^eq0g+@wtAWs(-{m6Ew4?|AP(Fa(?{@=i!IYy_Mu@>Z)%AZh_;;@F@~(*=Oo0LCio9zDB-1=j%iEeB4oRut zCluYgPSR8boGbEfDC2oPos5b@z>s|r;awh~)E0a~qK38QFvIsWkZ-yc{e$+ ze9L;CT*>u#56ic6P};XEPa?wdEzACKWfjw5`F1pwUOITO#BONRE(TYI1up!`Fk@tL#M?>`pI9KGo6edxSJ^|;7yqDuW0GiW0PRn~u@@WA;#k?*$w*jC< zz9E^m2b?SN-cI*Lny~@rioAEyBLK#yd7PH_t_YYAaIVOEPtr^eI9KGopLhXvH#6W| zk@qPchj`BlI9KF-o@9SIH{e{6w^RCo#YXif;HFLGFsd4st41JO0L*+FqVPE3Tu}wX zNsG3YR9v0ykV>FVbq}H{NJv_blbt;ZZP9_9Bzd-hXBT;xlqM?jASMHXJQ`Sb=?zL0 zo*H31jXq;T!5Z!alro!xtiZz>?uFo}l)fBmxCBP!Z&-4y;W8_$@=+$kT#?*&$ct?- zX;E-?79>@9Si}94LKe_^m@6VMDo?|++QS+ykyCldLqJ%=U5==r5~q3?9@cQr0ZJKh z5`O@jRy?~6m74OfhRd^{D!GR1VXjCXG?i1R+rmgU&J}r>D`K2ic_uZ*8ZMIs(2>;a z?~&JZ4{NwzQ5ffnJj@lb?$F&3VGWlRZdG2yc1uKb<|Yq&(Mm3QLmVGWn4z4CD)tl<((Fyd@B z|AKh2f@_p=t|)1dlC)@@T6RQI>mVc%PFh!koWuhjk?cdFcEW@8l2&iIj-|q!EAlW` z#Livjiag8}3E*6jhq)pFoGbFMhRd#4=86)Hm3u=unJY^4D&vqLC38iILEb|UA8@WH zF*vaiVVnVi`xnkFRs-m{BL9%`jfj!CB4>1pZ6^K+a(oXgIiuor{FAw&Ak#pS%oPO{ z71Hk1dD50TPdfEGl)wrHr5Y2+=yZq(2M5gvqvZTob1{QSi_scdujjJfZ#Y?euccWrIvaLt4!%a1$r(~uo*~?px_wax-RmnctjR+e7XR4A- z;WYqOz?rIK-{3v~FW^j7vS0WXlLVZpN;Zez1Ed1ZR3-Zdd{k!w&Qv7__$j_12b`%& z?uPj-R7}8`s$@&)On|z8GgZlf{&4^e0cWa`g93RJ1)Ql$4i*7@0?t$=;XDUy%>ies zl0*D!0a^miR3(S{PXM$AoT*9<3*QB33pi7iZ1evL&>nE6DmmPzSC+8>XR4ATf^Gm4 z0?t$=NBSJzPYyU!m2CGH156J%Q1I|<>rwH5HfHPIesRA|xoT*CA@ef0qjR9w>l5_p@05%1jsY=cZ?g2PA z;7nC=zL@vIfHPIe{RLpAiuVErRH(*kcKWP#)$_Kh7I!uXwXFYN^~X0x{A>)xm>Qkv zktmwYqbM$l-oa?z1Z*QJnhy!+@lzDT`Yy)Q=;$n{)x0tHC`2=agwya(W~!3bKr&JK zkp(6Rv3TIT5XqC)?1<^o0+T$r2oZfH{>hFAyeUMSY-ma)3a`nE z48nH^OTpOaBchG45Qme<_Nj&=0>_YcFfK^_tkmQl5j&}hT{y)Kx;<_eemb8L!MsEM zU9gsUB%*5XV0_Vz65_?^dI@5Z7UN~6D!HisS)m+{KDGWK1Wmt_9ebBEQ-?!4Gnuku zZxc-*x~tZXZNTT;_1uJHZU@>*w20_#pv6E9ygkhaoEJ}x<{idi?xhjCRUW9LEz(z+ zMz?nn**%(3YT(^%-r_x0NO7!Aaf_rFz!Vf$NYR5mh4~wswRLA9)wf91a|T8==5M+( zr@fG_=Q85W6|CGNp3z_-E`H1I`)3jwdJqV4WsE>uD1(p_zl>5eTj-x#svCQ)&>#c>XPf15vpI^_c-zsE%L6%wnJ<9sRN@iVsH8dOaR|vW&%LXwNSX8-K zn#LT!ZYxELB}{+fw?Zv z#;}@77$b>$(~!>-XU-)a!T9tR;AWa{-E`u8fcv}(ag`ACKWSz(eFLsjYK6;=wV+Wb zW6o2?oUM#G2gc;n$XuQH1leC-Q2hbOXM0(lXOXT)wv7j2chl+~)bbg^#Ye6J-i?<1 zj9SVE#;Zs2W{G2;XEzr5f7HPg8jF{jtgVzQy^ z^mY+TnOBWxnbX%IXO`lB$(ch0bA>eB)rFjUW>n5AI?>t#AgbqFR{DxQtn|Hz7mg(! zL{(N1OQBbcBEE=Ovl#zN)*Pyshf3DV3t1nfvpzJ(tnYy+G54Vjl>8PYQ_WvX#$bzM zAajYcpdjZVEoX_y`8(wt2o4cby%l1Z<-d#R!Eu$jSX7!(5LH*9tg%?EF%*d#S1d*2 zTP!}{<`5sb6m9?(_o0rfDV%!zTDa~r(7rj4GZ#o6V+(ogqw`qMnZ>?>GN^!-fm9p| znsZ$???HuB*XUGpCDkLM$?;(8-3UeAqY&osYegW7gG_UlXwah|%gU-!&Ju$e*J;Dg z5{u;td4tUw#390Hz;0CI*P@GM=#Y`32Z8~`|s5YsP4H){9a<-j4k zIazY}88h#=$sm3<2ooqs?##KjyZ7@fJw+KW77(0sX%$BjCVA(F?1k_R`!4v{?W zrc5gIYnf1(FMH-dxub3>2n(u}!ULtZe-nv&E`g!VfxTK${XY;(Cp)l}xavj-rzXD^ zUR0QGmu7#-V{;*o6*`apV&Nf>(I`82`}bn4%?4I^^dH1LPGBBX@W08Ufv>Y>lXG@K z{{32hlibOh3-X(~QU1e}M`eC34+h~&ve{FVU0VL~{KQ$e|&Vvt`bj5+_i zu)d#CSfjJDAgIT&Y(;qye>}!9z2tUU0rASh`3jb{Zd+9Pd_D2L!2K=+J4aL9IJi>7 z28@sZQf;wnPR4mB7v$#hlzTtrE{o(+pZ`zpFv_ix#>T}? z%unFQq6M>50)uoRTsH1pypAsg{uvTQyTa*GK>}DhTM$k4E_mpR|o0O`O}g@N!(u z>oKJlOne017aqpj^#CY_zt2-xkyER1F}3m*Q!8&Vz4G=6=0IXt66*tI`$(j=dRERx zIHs25>#)V z5yT~pP@Dyb;qyuRn)pCq`Fzse>QapQeA3=#^TPw2&(2NR_DwM+3oM&!ZcbLTwRb?Y z+qHTQVnS;nuJXyG&HdRY4M&1kWc-bLFEj~{%mKkWT-xwbO!s(U41g? z49*a!PbQtgve#SoXFIJvx3lw;$(8u;jltzZ{G>q0PuAR=Ht#@KRz8_@M#NR2xaQ`J z6rettblL@|PbQsF0@Npy&S(MZlSyZc0QJeFGgg55WYXDPfcj+887H7F`ef3X=G{ac zxaQ_ePcW=LnRNDy6R7>!&Rz+YK=03X_7P;^lgUw_J^(f;SM3CzH832D;ZfJ3DFFu*1z0@a@&hg%O(BzXz z=Y%xF>XS)lwaNsd*o@RClg^diW8mNxUgxSZVdnm9=W126+`{W@k+Axz4j%!mMPl{I zq;stRwLjb0n(jhL^2wxgoupA;)j2nmHK4@UpUvrWwLjaznj49-Kik2Y8_TcuXFFJP zTaCF|wLcpuL!|a+19c`+`?DRaxiOvEpY34HjmsWtf3|})H^!+?CLOG~5vl#z4%Xa0 z#>}+ZpY34HZ6}c0pY34HjXNaO{%i+pZcL~4XFFJPBU1ab9jv)AKea#G!J3XS+5x!e`VU41g?JfC|WKz%alycBXVNqsWu zyc|!URBC^=^P1$N_Gde-?-cF~GW~_WN>AaJ!15o?3op(im`ef31 zPtvGQCY|>ac)ICNCY?`%gP^GTWYYOO$v#wlGU@D;egONk`OOz?TFrJ^&2m)>WD9_q z&qGv9@6To!cNMOZN>NvhhP z?O@IAB?{x3n}ans)}7j)?O@G~6|VMYJ6LlgQv0(Vtho`X{n-xI+$cot&vvlpMkUn# zYzJ#@ zBB^x{b_w}pkVA`4%o_F~Q9J33aEN0|c3Es4sVJhIg($D8d?CV_WeD2|M%IKR{0^QKxoA7O)d5uTle{}#Jl-H&QB8>gfj{u1k$WOi2opme;4h zL(obsH_RI(*pM1;m^Y>^eB?JawFq8zg}TAdViaiJ9`piztC6{bitY(TYz@&>K34G3p$$EDNZBn+*50pZYk2v_;&^CJYL z4Rkj$uaS*wfx)I4(mj@e<<^Zva3;c~Mok04)rAYhGC^pOCHKPrWA8oSt18m>@pJAu zH@P>tCFSOFfiyw_goF?vB%z0*qKk@(iV~`zAc#n@B1J(_L_u6DC@S{G3U) zs;jQ9Ws7CqUAzD1d1vM%D6-(P``i7051$V=^StxUJ2UT;^Uj<(@1RD3-<44N@L7tj z%EF6Cxi+9lQ(pY6U(p(?3}j)0+G8vi2*9o??`Aoe~Iu4e03C_?xa5bh`k zq0;Sm6;ycy2xW)D#<#273<|slgmwob(03_(_+W)%k931G@n)+1sUW_9*!IUE@CgHB z5ZL!t+v-5R^0R@C0qS@W0w*FhmR459uK@zf8Y>rp5bgwbb#TeLtg#cE&DO9{C95%r z`;b|Ua)ZA!SzQ59lGS|-Fsm1s75OBq_e@qxf1K4dJI<==R%q^K$oU#sbixaSGgbvy znuYizZ@rF+BU++11gxqpn%L10=L!D;JX*UVi$o{kh4&*!v8(yG5~tjl%F!Vb)PK?a z=nr-Q8hwoo!osEh;4rc}O*2-Si|0#b9VxoXF#+aKw>N8J;VbM3no zkeTMDje-KP(T391{;?c?esIznKq?ec+v~|yJA%-~X+@=7Ou}uQK3ml(U)zV zVR(CX-ON)gyWZe=r`Jt_{2qpX!<@QFkl)kbd2`E>9GJbF91h*Ccc4JnjOuODuR6VM z24Sfx&W6*=r0M!NGN+#e_Og*|y1t5V8wmB&Cm_i@N5=8fv0M0%;!K!Rb65oQj6w&QJLEv@<-bLUQ2DTyaHv~E`L3tRPPi=mKO`IeGlNe}= zz}XB`BXAu9eGqsKfu8#zP>fV-P>%8g0djcQrsoKR>Op>-i>fCiU+dm4O}SAB}ek?pZCM`;5=Y@XoAxX{n?gl(vIr@4sVqmZf>+YBl>b!~UZ(|40`Dz)tmE=CPv`tfDH6 zl8%O}8mi?!;V~**Y^SuQN;Yb_pD6YpX++9QsmE%m`RKUp>ulPeQ(WatFyDo7BTCcN z5~ZYD}Vv7?{~x zrI(T_egBC-@J$XZ_WkRbkbVC?2H5vMM4<9K@NVBron;$Tcj6!2PcPM6X((9pO0X{5 zb-dM@v9n=hHJgT$C$e%)Q@-2ljtNw*R=Z5->}4=c>k7R*>4aBOFLfZcxEpooh(H|! z1qd9CKnL=b4+6RtsQe%Vov6gUL}2J5JN6D0y9Y80Y4Z}w49YTm?S5;-&m&OqAfnqk!T z43wZ4_^e1ro1NteN8>=Rii7j;ND-8Ufxn^%j&ZdhnZDH&tlD*?WIjrm3pMk*M(8Rf zRLb>J_DZnR4$r{LE9nFqWFVcq38+!>kanx;3BDpIyN%+*L4+GW>t|I>)yelY$>+^Q z70g`2tX1+;!N>X4tJ{y*+4~!1Iv*+Z zxF3A%7Q+;u=@v4m*g%zAz@Q(dYVI~uxUfo#TSb@Ank#UkHf@T|Uv(4Ij{7*(;*6%i z=|>Z$O9q<6E>Z?g8>~}{9kE+WXt0!MgT*T9zaCtl1fn*d(4F5@s4cCm&Ye3W>eE0O z?a0oP81q@6h_+8>u?{~Ew4rs_C7&^W4Tx3LMa--(G&ufg#QZHFn^;{IvDkkPWOGT_ zMqVQQBOumXF)b4o%GHG`>GD-O@a8yqzh-GsZ&g(z zItbm}r=zD!G=Ccd{2gh7sjp^wYdaZ~)QoAAW^!7qjCLq#ie~DdnN(?hBAYAVTlH^!^58G4NO*!VXxAr6LE5y`t;1 z2SILYNBg4ptrOBa1*Z44wWaqh^Lk%fTYBFUUhgZlV`L938?1U?nJvBV3--QYkjR-j z2MjExEar7FYptp=I=YLFUN%^2kwV9^5j_RbRMlbIrIuwea%1NN)1{i}w4E`n*G#K+ z#`HXxs88PM*3^7z6<%vq{sqxy-J z=_LVK#I~8mU>(=9ZEzH2Nnk$)yBx$-@cDu4gW1+a7Z9C_DT_;$>RI4BH6VLiD!0=D zvah9bn;ocNZfY7nT}{JQ(d8`t2`D{HLRI<`0`*e*oS}%C9_Y)`tGRAQpq5?D>iQmM z{C=O70*qfA5&T&kg0;ZLL0w*(wbgJwDlIEPZY2XeaWyvI?B0Rk`)y#v_5*P-*xPqS;3fvj5coXSjfO)1a4>GQUu;+;5r0y9>A`o3!{~#7|K#40=-(X z6m38pjM(;h2po+-2S%570$Ko6UWdT#3=BkI3j+OyB0w?IDCYgb_QwJL0}<`VB9QSQ zZE#9B1*ias|9akuGAsi13}jip7T{3Cly5*_A_6_1M&L$74`uWgfU}se>WTC1hD$L$ zOa>XvNgZ(d;0EG{I*P5l5RpQ)s=h|KxOK5|`xLau1|S7zs)tpS*kB{vQ|_H(%>T+o zngcRD18@xtz!A8eicdo1i=59z7VLe@S!Ri5J&!gZxr&xN0NrF@5WRuQs6mtwsFFb> z-8oYMH7Fy28W~Z4J_?DVfle|gU!a7T>O*a41lVy6Fs8EtITYOGmO)_3RwK8Im{y5^ zyr$@KK4yG7PZ=^@3fcFQ8i>)=LZvC`vX@Do` zV}Q{9m8s9Rx_-@s-@rjACQVF@7*AA+8c*NYGTU8-MpOg-TU%zlk4TUK|D7UaJY>ex z_li&ff*Mah*fJHK2140yn3tuByaI%(d_7Yy|M_-smrc3Iwi;@{$tMiE4}348G1VVV z6eH1G?sT$QUFTBWbM4&5^Kb$Q1bam`EQbCvdC#?_BweWRlf=;fS+>}oB@Y8mCX{zV!vWi| zKsTazA7YEZUTjD2E5-2TMZ&KmwtasDK4+ji0vQ_+=!ifG14RhbBG7>;%Z~tB1XMmA zfmI0Lm?=enGpe;Is(>~8G+ z_Q*0B7kjC;*@Dz;o4r-r{1LF`Wn{*6Poa#H!L|$_dkpR>SiaN<$h+DC+cFW4Tjw@Ck?hQg0QEVTxygo^;J z!L!+gzQ}Fm>4uNVedJZs7oFI7>?8M;*FazFt$NNrBJqpEDZ*~t5Ayyd;vS{AU)@Pv zzteJWM)FBHM6~=)AEw>^QHdPZACU(j-Mcb19N7AO@cv$fi#cN6SL@GTJ<3VxWtjnN z?l>t~FL!T}_3{uS>lKw|ueX?HiwuY_aZ(X8HU2 z+QOe=J#&DhegUc5F9YdhM7Cdvz-k6=M&Nk_%I`toGX#1uS;=C|OiTv5b~zK0KWnq* zZ^r;d^+2G;@E$@5cXtL-s}BkYW58&7WiWGYdbxC~rFCeazZmh43n- zkYP+_4(A)}&#{S{l3W~?hKsj?L#@<5J zY~;X!aYIK{A+=EF_I4v*V^p1`V$VZso!w58B^OFBs_53$p zP2=#0kW(!;#{^x6r)k`Rf@#P$pia{S)M=WurE}2SE+c|&+GhMozYi4jfO#06@Cs>% z!XE*L58ePAj(mZzl_7VUW@Mg=uxn+K7GW5BHsp1-@j;g9P+IJ3{3J2C#F+(r-{fpS zTr@8Yq@eRQt}@O38@cP#KEKFp=IoESoQ*UqWo-O_$EZguKNr%3^MIbs0KkcpHpCl?5)S!(YeWyk+f^a5Jbp_9BMfTXzw6^y9 zXp8uSX-8Q&qS+rrD?WX!l~yKUH$DR=vfD{G6h8*x_7aZ7XCmA|!ddZ|)mB=$gcEV> zhT}XZ<)q>>yIMHS$#8yr26!qZTpXVPo=y@jjgJMrO2QrDV?pmM;mY_}q^*{4b$o0$ zE3J!!YvN;TthBBYu8)uHZl!gTaPRooS}Uza!VU4Ubyiw;2@i_TfSg(h501}(oH_{) ziO+zXdI=AW&w!jB5*`+x0XaP-JUl)Fa(YR)F+QW-O6x7*G4UBath7E79*?@90(}Kc z1V9b?378U}iQF0_JS{#Gx%HRu%sAddqz#bp$?=)UZJ>l_r!QWNLy&_6%uBzd9AGa2 z3)1Ir0N7i=qV%H(_7QNNYVjcoL?l_98*ceG;6DK$%`7hqKaWAvDuA5!K^HMCxD!R)Kmhsrv$a0%~E; zi|q!UH!tG->|3BOSW5ZLX`4VR!ejLe6sy?MF%Lk7q*%igg$FlJaFGbHTHb;Bj6ww7 z;9_4OoC0k1Abz?&XBz0UdPQcahG~=srPgo<}S`FGBL65$i$Ro1s5VLM0Ot` zwzYznBV2mc22`stYO@*3FdNy8<(vfDu?p>Zq}CoCmc1$*?}HNA@CZg) zBSvox5dKXW=sn9Eemv$>r0PN5;bni$<5ghTKXn8dnqB;dXWSGa$%P*Q^~G91eK!Vw zki1YNIA1ZmfvLse9hIs#OSOh)lSH z#OFZ=1B*LI+z~P#@yZ<}?g-&?4>#@TJ3^Q&>c(c(Tj_ZPloKBVN^DlQu2yPkxnNEENxp~0YXkK!YO!+q%$kyF_K{` zS9y$_kD%umB*@BD9wT{WQ34sRw^9EK@KXhX)F1g7kCDG&e%fOs6MG&b z2|SOH1fIu80?%V4f#)%j!1EYM;CYNB@H|Em6k7?;VCi^Xc#I?pr6yru(PJc0B-NJM$Jc92mzBE22Ex~CuYf0!G9DwP2r1(+k|;lA zJVsVyycf4L9wTdkN>j#TWz zse_2{_1Ymoy;Dz73cg+=XG5x%ark;|JmLnWjK@fJgu$u1$ceAl*v>;zSEE7cG4dSL z_SKZ}7|FW7mogqBr$Nexsr5{Uuh*EvpU}A3XwMwuG4ehTrEwp~X=>aDrB1Fi?n4sx zJVrKa+=s)>8h1l>v&MZy(s&*trE!hNNOpYBW8_E3-SZfkLfJi!k-Y&tkCBG~ROf1s zk<6zCKs-jW%)J4`Vv@c1n(6pknFqTpHHJd)^%{YdG9Dv| z(o)7_RVNQ-R4LZLJVs8TSmQBL9yF=_*}uoCapvcx`0{bU)fz{v!k37$(o5oQ3CRmpl zH3|oyol(o8fi1!f7Fthb=i=$D^h9XHPvs<20-A5cZTKHAc(d&z?O( zW7jI&NPRYH>{x}Tj07I3aR7c&PXHdJF&gcArXQ`bYP7wA&!T0D*>bAU#(Ir5K3pF| zqmAeAnxGPepwyR%kJcEKZaW$H7%ddTV;$osDvT>M3!h-2CTWaHJkCZqR%2C&qk@MZ zr(%{w6=I54h~vX6S%|CHJ*TNeSw_<*D2yjg;Z1D0=?dG>%-@M;DD0|CrUvh2Cd^4? zGRw>44NlM6UPsrTx2XP1~WFMWUOM*T=ilceH z#)Vd4CI{9T8l%sjM0K61G5UNL_Spp*qt8FcnlIECeg00W`z(#o=RaY7XDghBK3mQ{ zx=7&+%qIE7=V*TPxzX%%=PDdTpBXS5c(IO0pULCEK2Kxx8HfB!G*(KO6AWNyznGd( zO1QvN!iC}4h$`&Fj<#GS3ZT-Lun%0MF)BHL9rM>3qf&FJgo`ycee4p2Lul@c_=vbv zVcSf>mnjUTvt^bAFJYlrGF7N6yh2?W{)~kh#zI`BGeMy~rDj)Yj6$6^2KZ`?QK%b6 z0AHiADb%$Jr&OjZgOO}x%A8fE*Lj)V7(Ne3j`9!THRTIjcCXhcrf?>%@6>y~gNs7U%VcHCC1WP4Gn2te7=dm43vl^rrCJxv2ER%w)4p zgi7}&eoSLj+G0n4Tw`dO?{qSr&={J&gi3o-V+_0%#7}9A?r=5n(;8#oai=I_i^k|4 zJ*NUcqcI*ff9Jq|R%1MDzGnA(PUAeQ@IX!k&uff_&u~`y1&uL~hZ4W2F&;i;bvQ1-*5sMFpmo-Ks-^50JMPoEF_tG<7)fkQZF(;DOG)5!u%Ypy8 z!g!=}j6E9s2AVErOQ=S8!)t`!g(u{hMtEBbF^%w!#- zG{PS=HjVIs#-IUL$-R{stTGY9xH4g_uV8 zR%6o$-)U?b;d_luBmAIoYpX;?0uF6Hj9x$syhMhAZ3r!`5*Z5tLr7UAG8h~~XknGe zXu#I7l99AZWHC`9QvN2Ls*z$%eRs-+?1!*4TZp;m@q z8mF}(n8wLB1k*SLhF}_}&=5@H6d8hPoMJ;Tjnl>uOyiUof@z$#hF}_})DTSLlo^6) zoOXs_8mGM>n8xW~2&Qq$4Z$={M?)};Q=tiLoH92fVF&L*0~E7~RO@tVYMp93T#J|Z zC7Wp|bup6AIukg-b~OaF&U2hGyBPvnC!NhzV+d%SzjBW4ZU|_d5BX%PH3YQIe(aES zhJe=jnl^vEA)s}JOa`HcA)s}-(>UsB2xy&4_&Dxm2xy&2d=&LI1hmdcd=~XF1hmfa zB=j`|w9Xusqn{z5b^bva4TgZ$xr_SfZwP3e20kDL7y?>nI4d{M5YRg5%w>=vuyrV7 zFGDb`v$rPb*6C~q4?zPIvx!ve3~p+jadvn}YqZV-4Ulw{P6(5-r0@g~#v9RSi~<@R z6AS^3A^QkNYk~{SPT~{z7{dY0o=8%OQ#DE} z)0?z1%MRZ_tt?=jPt*yqWGR`;K6{cTVCTMM%Wpt9SrgKf=$UqK6GcIw36AlD|Z6FdZ(h2jSp$n;yb2PzKlFqV&r&1EdDM^d9q|7fe5;@LEQcKsTbHULeQb>iYN#{bK zGE&dB+L%rQy*iRQ9N^7#8m={w_qdJlWjYP0`qW5v(p)>8Px9WW<&8j9b~>LQ4XLNe zxUZeg`D#$=2NrKXTPip>HJ|IoUnw*s^$gJvg@&eHBidh~VX4oF4p3-#Y8p#&phAtQ zYl(&`G$!>V(LoB0PklgiutF14lUeIS6q=H{n`oFq(^Bse9jegGR2mK8!xTC>wVY$_ zaD`^4u43G9h32JhAv!{#1*whfUq>pmD7A!>%?O3gORXVlRA_1H4Wf|>U6dM+u9q>& zj(v|FacSx;&RU~Y+^eaTY=kiiy^&ge2ha>Voiohasb7r;I?Yb!$a*jJF&AbF>~s!> z4^xkF>R+hR{V65=^*lSBo%d5K&TbiIH;Wa4YY75zD{UPo*d?~Zep%3q{rP-5hYSS+ z2rf_{N6uJf)@BVwj9izKSr-|BFnSsPw0@YuESJ%8#wxSk>5g!4EPmSYj8$gO7IP5J za*xArI2XIH7a<^}z!|FrWaIIe%=222p6N#Vgdap8a_mO@^a=MVW(GOWZ{SeqmPJ@d zXUCD6#B3YpUIa#QJ;zCRjj@F=?q=Xxg}H@LLs4}K+X1U+!tqDLm6yg?&V7S9DAGe? zj8c9E9_g7k9(lR#2jVw`;78T|+MF-}1ueb~@nD+_iu2kA#P)NT zB+ES({LTwictxJdUJIT~H`X#by$$NI|2i~Dt5y$#=yL5nfVj2Bu!Gal{IPtEVFwSs z9k@Va*ui^2T&z%IEJoI^0WQ)Qi;-JU$XKz)Sd5%U+(u(8MvfTaB?8 zS#~FIsm550v><<(#?bp8D6gHydTS@vUSUieP**G!UV@qyFMtx-aQ7GjjpUt^<$0U8@64Aj^tVUWf~ z343X5l(4tPMhW|9Y?LrqW21z9H8x7vPh+EmUukTVFhpacg#8uPO6VKD1T`(DCX^D? zJ~x$caCCmDQNkfwh*82Yjg1lx)z~QEFpZ584%gTyVYtRd2}fvblyIcRMhPP{HcDvJ z*eGG7#zqOFG&V{Yt+7$U7=^VG4hpY8O^c}srG#;MIAq0I1Ybi`?)0%IS+S0poFA-Q zTyB61wKz=N+zC_1TCt&->@K0)qoz!^Vn=0CZ4qkl*l^o2XmAxLkjZKd%Qsgvcw$rZ znid+mg9G|Fg#*yYM#fK77>{fY*h#^@kW|dFs1i;ytM}N9@TJUT8E2uHS}2-{FG*sv zG)6NG;4E^Y#wY|0wb)4-qYyNEV<#(&2NN@$9$d>znX}6DR4>zWvJ2WF(+F#JF2BuG zQ{_P{#A1z+>8Q29=V^>gFXz;>L}O$+k?GIZ7=5F58t?@Q<8jJDEQ;16r(%{w6=In* z9o2hL_H-74F9u`3R*CrB`J9+D3p?w(91lbE3)aCNA^BrE42`) za|DH6sWEESmy_;Q3a6o$^7Te+mBMlCpRZt>Uak4@@cWYZ8jbPJW-2vvt;Tp~a~tt$ zjjVzryLNrguhrBj;k4Ocm-uuTT$XpT$DeP<g##$$!ECOL3Ogvou`J}H3WrrD>!VjQ6Xv8c+3aQVO!m{vq%DO!s}i|p$ULX8 z9x_{^f1nUbQbJzvglx^uD#u~e855>hv27|5->Ax9e_3HY*k6iPfU}sAl#o}okeb-p z;kOVK`5UWuVVq;oihNISd7NXxjl9byzbVc>9Exnb1K>At_Jv4fK2`KkoNbsD5q&%s zr|uGw%gCm-xKoi;l&1E#^CKNuW3{-&7(FkooKuf7e3I0QrZ)xvHD|HOgMLkE1WNdcu97HUt2}wvU!)2v*l%JdxQ@#=%ZxWqjXAi~0 zs6-}?T%8azM~Tc72_qWYJTg_}83J}mWUfdW0#qZDMGHfKYWQ9Jq{Tb zvq-8mt(rrFSml*(M_*%J z%uwakwkfX)J3Flt@_L!AQ>hbT=8!$6SSL;3)BzoKw4-goTugCFQs*W~_-1-2B0I?J z(M>1B^id+yM~x=1-$POt)Sr?lPD!fOk}_*ze+XApVLJGLJ?Qf|ho%+zjNt1yhlHEz z#vTx|g7rTHA59XI4rSRBFem&qQi}s!Q+Frc$?2n|hNrKXm}5 z=pEYP)Lcr@+q0#qml>z`W;>*&5mn>UD3rZ2wT_*y4*3CLGT9J2D|m8eSYVT;TCvwN zIZIj*n`8F3Vwu!Lq6F&oQhnqtmgr51=^c55?fsU3hRDZ^`JI44kumJhZwnY4`3J!} z0)|8inC4vpLnGw`zZWnpGK=}VCt!G_kumQJXl!}>ELey2b|zb3OzMQOi0Yv>oGwb; zK-5#AOH(t)0rgU7Me2E?-U_Ws-GeQSSRaK}r~b;gz6#x#T0zULpF+2$ULtBxXie&E zqW%i4OZ|grfI|1C4jvCQP@xB{@-=~2GG}TvG+6rxBF3lVGbVtoGXN&Y?of5)LZ=mG7|;#j=aeRJt3XOZbKxO+BhwpM(Lmkw>)CAg>7(zdrh&^1q_LB zt0^`|z|aVHnqqSW42y81DK<~Q@Cf&rV)F$wM!3xsJ43*j2zQxcX9^e};U-gTfq;n- z?lHv{3Yd~whR0%Tkez-eYB$Y_v-^m(Pb}LVI2OqfvAhYV{h6)1m+eqH9n;+<&`Y2( z_Bc?*S@cw_8qCRvt+^cCkunUGg-1}fUd zu=jwk0zit7bzW+gY+(+jzx522m@!U?cN)ovP`cIW6h`4_faR=Y3FbIwHxoTC=5$5g zhmg7AG>Eh-?uBYlj)RZ_m!-VhjQOlsHJLw1koi$$WLKOij7k2v52=T9%Hd9u4X+e%0a<57rcNmewA|>STpP6SBFP+Ll${ZU;LUR zHEKn+v9+&FvP-y;FImLZNj6C+@;$+INj7FAQp7aZC)o|MBHh_QHzcXIL}Ve^ZcMVA zsYol<^rHPtP72us0yCVsC6gI+cgD#goLYIG%qh7U4Iyq6$x}j7qv~LCsC7 zwShFZ2C0rOW~vVmiBuK_UvWiC{N`4+Edl?$$}jQfhq)CUz~EFa1arXlWZV--8weSd z1CYQPQ~3mTWVg(&ybMKztgXm9QW*pIAzsnD2zgg_Yy-Y5(^5I3W8+zZ{ZUP;A}gCM zbu^TLK64^ELC#SQg=eO6CWN0rAo4a^G)GNtR%H1V0BUk`BZF@SP?K9Iat?ZG&Lo*l zB9ZgE0~{+LD>4>p&zUSBVL3~YZO#;D8bmwipmlPlCYg=%5wn?-&5tsi7bt6P!Iz+C zx!>crnk5cHXcx;VB;&k-JfJMMHGW$$vLga&JJ;z+sq+hJg`u}$IMgtxBj{{*6bALq zIimnykwVrnhIO9DdJ-B~oeg%T=7ROig7bv+Lc@B?_N+8sEvGMZnzNwb9$|gRux=qM zkH1^az38Gj3kzNqhPMpE=VYJ+RgcV?oJHX+wP=B~1lZ4svPWByGV11B0e0kh>SD2g zK;$osIZuES`4yGEM3nAEK4vw~7Z8d}MX$-ZAn_+CEfTr>5`d*GsM@T^`K4ZZ$nyX_NDNGDGmpQC(yR8hbX!9N_n&q;(nfW;{gbJpN>H3PmMETmHPPED55{y`0{lafA}~@B9#(`qJwiQZ6=swXeg(A9 z3)rT~%}U>w;n^6|xw%ov)G5I1k(+Xuu-%_9VdSrz{QqWlgj@k$B1f@E2HW)#bB}?2Fc*RCQnGaqK1H^Ppp_xEXCneV7#NDcLFDgs3{oBqezc)w*9Jc%|4h&( zF}61|yr(ZdNrj(@Q}9bKUX6Xk-QS2laL!oGhUA-`+B5G$`u0-Kd8p@Xspl7_p6#Wc zvmvuSZ*MY6J#Pe7^=v z_wQ>VD=Y0*e7?ICY3voR_kuvSVpe;$qJ3n8ToRlgUxZw(9#=wdWd0J%byHRV(b*qE@r{TB5<>?oq`bV5NoI=TS0Is*_MI!5ZTT`;03bv znuRLGz_uUjn+V=Rw(~)Ik8Eck@TIVIMuMqe%O_il;9F$d2ehm$VC#)QDFRln41~@F z8|E`Oga`&v&z>cq)sd|Q0>2Wr_aS!`*f5`2cB^0|*}em96xlvUV7jnvKV`< zO`-;MVANL$hhuRsCi<$YipXQcI|+xKT_WDm5wS-R@!N#Mic7?Ab;LDHu`b~}jEKD_ zV@w9tb(8R+>lp4cA4S2C<-%dm*DUPngu}t2cvsgn@viPGyn}j>Yh}XWxKvy#y9?I{ zmSN>yCl-S)(pMg+Qq(cxl7z#lNTs->ncPdX+#P=#H z!Ndpj`vjA|HE1Tmz6poJL74V!#&-PJN*K|_~hFy6z4$cFg>j8Klu*1!9L+_Acy&K zAK}9w8_(hAH=uUGZdrtxe7PU2N!)@6zTD5`%l%+?jYC!@U+xEM6~@c`OupO?)+vma z`w_m}57ujJTbX>hAMBwq9=LqDAMBZTI`VR3jra{&ahHY4a)Z5sBxm#Gez13vMaaR+ z{a~Ns^$3FPa{S86{a`=O^8c<2&J@~K!#A1#8*LN_UGbP z8#>lsp(xiHcN6=@lVFX!vI+LWW~^^6SCj0RgU~mWD+1hiOIHM@d9|AY<$yqUpB=hA z*uKlS?>opIZV2$OwB%M?rz$p{;pIUnYNiU)4S};NkRE~C*TXEgK;wIM0 zkbg0ZpC#63Q)J=x`PC$TXEgJ1gKka-Ms}ATiMF5 zfO}wQD$9_E0=Yvo7*@C9x(9^`=H<|@fO|*=Yhc+q^ef;VCJ257LP1dHfF$)Yx8k}- zhBknv^f)4iVRb96+n7cTsatW~k>SS>qi)4@M-{&bz*})CF7z^f_+QJ7x^DpBR$S^! z-HPj;8p=eOf5iC5Y6mxIl$O>Q-DAeg&jwB`<-xUHBC^5Ti-m zitFN5T*j$eab4VsOQdeab#W{1jd)3+ZpC$REAH(;>Q-DAx8gnwq;AD^;a7m^)UCKK zZp9^1x8l0E6_@#`TX9|Z71)e)>Q-DAeg&QeQn%u|@GC%0bt|q5zXER{PTh*@uCjC4 z5!9`?F8m6xoz<4th>4u*Tt>4A3}<{71xDd0p`G4anFI0)vdVh z{h=-(O5;AztZ^TdTF9-q?n4sRjk~^i<38NHaW^z?+(#shZrn|(aphKA_lXR4e03|X z`&7YLWNMyx8l0+D?p%b#dUEjF0)d%;<~sMSH>OkVjqmU6s&H=b#W{15(=ST0T+G+ z2-K~(E^fsoQn%u|xD|IKqSURpE^fsw1H!GiB(4OTF1WfC*Tt>4?@=uM3b!i8S}K7`b*xGrwRWisB1ORBmR*Tt>4%P~IWR$Lc;1=x1#R$QDylm=I~ z;<~sMm(8zk#dYCVfJohn>*7{i3Q@P>y0{gW3R1V?y6`JNPIW7;3%>$H>Q-Fb_%2A@ zitEC!0OQoHxGrwRCBm(^>^9dzylBC@6_=E#OYOAcL?o>a!a5=E4RRD?ACa6xOh0*7 zB43c-kHI3h;<~sMmy^5PitEC!fB^axaN$=#0R0NM@GHQM65_qVox(Cvm*7u9+k4TD ziBggZTHlXwULLC-b%%l?y^^jCT6#Z-ITnP%0&ZrfPmWRJ1*dO<$Jp;86kD)+v=!Rdrcr$(jR>8ht%4}b_1knXc5ss9#lD4=Hf+Afc z9Lz%w(bJL~_=%Un7#sk`=)5>J7wpgQd{y&n$haVm?Gf0u+E1jj0Sww*WFX5q4{`&= z&K3BR_bg&U(LdW6N5F1wG3EG^EPz%YAO|a%7l)`n+eJjK)g~1E!VaGXwvriE^zU|V z6@yczSkZsj89y+AJBH=>(sn2-LC(;-psz$g+Uo}^u>|4Pe?+yT-`Yt=w4TT`fq;Ov zXQD`UgH371T(?)0;u4dF9MbG(;n{x{;DGE!NLz;etAP^2S~0>hj<^NC+nfC-!|cb# zptbKX-|Y9ze&6hemFS!OzS(cNzS-}a{dhvdKJv}}B;ASmX1{Ot!^r%fH2V{OMahG^ zXZr^`bE&X8$|Xdi8|>+(#lZ1EyRaBo1~$DI7{s7n47dn4Ee0qnK~7l=tVO^q2ChZe zTMRJ5TMQ7iEkp5evy@G7#)?;~fs5>163e+9z_m~p+3i_;yRjYD2AA2{R|2&kcbsKk zZnx@(@CjgShsDAbb|wqbVFlI%36!zCfmy7!6I@(e04DrX3yGz-{bV7rMlU4p#@4m} z{s8l3kba5%_Xqy_1M~v_{ejvt^xq%&?+>uY$ZblqW$V8`@ZTT!?+^U<2QV@J2i_n2 z|8XHPm{$H8wU97Yyjn=CQ45J1^g?3Ib_CZP3Tee$BywGeR@uFHt90x|e zk$6cjBqCQdey;e>&H63W0fMY+qaG>dIu;~L$JsI5L z*A0}FAg3H?x(NYupy@J%y#q~*@D4N)w4K7`Lsih`hZDwj$MRt;iSm8JwR-tb70l;} zq_oE6?#ShCyRkUcR2|Ibjg9TbA>2iU@r8!04BT};Ss7faR|a>C^;ZV|D+d1+ga3-b zf5qUxV(`Cp_P=$8so;O>?0@V0fAL%A|KgRwEUpattCfMV-POvVe=wIzfv5G#pntI7 z$18(@%~l43%*tRQ)(S4Jh4{(JU;|bLF5VeDJ02?o<^IS~-mM(v{>V}8j~wki%MSep z>`ox~jQmNz250`^HfbODEf<)kXK_c+H zAQ5<8kO(|4NCci2Bm&P15`pIhiC~Yf3|OyS@q)z6cgG8olDnH;kR%hlJ!UuhXI_wm zSAWI8u;&Gd9v3_>NCZ3fg2Xht;RT88zr+g?(`EgP7bGb{vMvbC!V417FY$uJbWL9| z5dH6aL1Hb87bJ!~FG$TA_u+7}#{H2OB&PX~dqHBRyXyssX?E8O64UHtWx!~RA%4Z+ z*rEIJ6xbCnNIKQ7dO_0c;suG}9eY9II2JERoDJXwiCDZKso8Y*y&y5GJ?sTZoTeo+ zgAfcaNRyEPydaS%UXWD5cgYKqD%<~KFGwuJp7(-8E&MVsNGuOJ64qXjB&@w4NmzS9qUB_~Ad%kW1&Ny6u@@x91oxm9B+C02y&#E* zJ>mt417Ex#Im*M46A}+cPRP9x4ul-#;mA=Qj%1U*70h9A_XZb483=ou^o;N}=?U7* zr73<|$To(uy`p5?gkwlb@@%GkWXXi7<1Kr3C@ydW+?FDlYrT38ez$i$v<91l~?KfwvP*u=Aa8 z|2_aJvVg9X{QCg>`v8(xc{(S)ceE{62_U{Au zzkDA+GvA-Vt6@J!7ba<`@4_7bvO_M`IcF2>kpC0w{1RH{mM!MFF{14iJe^(w^W3s? zX_5DbMNa!XU}q3cqJi!nWi^m(djtJ8P+aT92k^W7_IWYBiR}RH>yPud&v)NIXXASY zI)P`P6Lnf< zsEU77C5YMopIq4GZ=d_y=l|@&E>0)@Q577N{iPRn?Qr`%L6i8G?4j4eRyKR+?Gg6& z&>7+Fp%b*ZiB|d$G1848ZLe637#itAWDosn8097KRx_kE%kx`pu^$lUT>|MZz+i8H z1IJ5Xt|QxNL8!2Xe&7%I)*VfS~~&6QR%9r+)F!aIF(3aV5dIFkzr!B13huyXnVH4;`@v2vx^WYBmtERCnS1tQ z(B=o!{}Vgx57A(sE(W_Xq?-)(>9WKAoHp2}%MN?^MP;zhlpXf&K&21v#9)8&5saVh zkHl=!JM5cJ^mo{I-(Y8-^9*(Z&tNC;40eK@8|?lLI~D2gutN)H*#4Py|I9j8Qd@KU zGwXPh!O7Djw4E7Y*OHtpKPw{uyci&*=c9UnY6L)n9i>LgvaSQ=tJ?Z;d5uAdw-}4h*_gy{5~MYuky10ptybU-7Q+f zGXp^kxQ}FWv@!ELj=qoOjowa<#IVOf&Az)ue}{cf9f{#&{>uz@-5LK=20OF!-7RkR zw#QRx^Z$h-F>LmK;|{wq-nlN2yIyzI56o_yVSj-J`=w&A8$-IuV82v$*uT>T`=zqO zUjCBWVZS_!UeXT*Dy`q4!Tv@Bld<(Ebp0cPy*Jp4@#5;0+5Qgu?i=jvbDqIY;2G=$ zp21GAbAz3|3Wmmxj>IsrcO-_u^N&v8`9~-4{G$_i{?Q3M|L6pse{=%RKRUr4_m9qc z?TXJvX72B>w}+kS@333e5Pyf=-(iPoB>vGkHTXO1{ti2B<-KtdDe7Jid!^MIIL6nK zeFKF5l)=vI{2g{N*kybCUo+T6#2(&ZAArL)(Rpz;l=+*;%*Co#BJ6$Z$_VdUSAw>`gjApcl9o0(Yc>$_XlT0@;?sKuZ@X{e`bYKI#ko;9_~n|r;y3UXZQ)5r0<{RyH* zWZD7Tv(NBfNbLUlhC3AA`i8(;-w=4~8-ks$Zz{p@GwT~B_SQE9-ui~XTi+0P>l*@Z zeM8`_ZwS2g4S~15A=u;V8`f)A);G+2ch)ybuJ2Tbdh_ppa{U()`(%xtGR|_}kZ%(P zXTEkf#?$ZQ&CBk7qsuPkzmV{K(xU_Y=DtsQ%P!swO$4lh zeX&%@Y+twpHvBL0N&lZX^8Y>;8f)c+gfXP;6&J(Src<4@@BvQ4D+6Mv0fg%n(i*xetd4^!>ZO8y)QWw&bxav+L`- z(b=^#L%dEi;$6{76Bk#sk|>Xdx%AU3-uV|$_|B(MDG|{(+iEa$(CKG*&9P*#3P4s8wSpN!|=$m$EqHmO4^pBs$ zvuAq~eGAx!L)|AX@^{g9-$dt>>zU{To{3K2ndmYzXN^ADa_ciM#=|ZFJFymjL+SY8 zJ5O;0^D`zo6MH5)foGxx)fgR>5^e>#a$DoeIHR)+_eI<6}P&%Z%-4%8w-|!Dg9)x#^?kYQX1AJ`^PTs{sF=UL3H~m6qO=oC--6b-f-@~IkMo9qtbg-=@v;8?*m{r7PtrWt)l>ZK zU>X}w^ht!h(>aXrPUjG``HB{KAYii}7{l3KQG%m4fq-n8Z=yXuF$gXQ;IC$)6~BK z*7v64pY`|8`omuG&-z=*{W&L&Rrf~t-gMIajdp*d9hOy>R$N^L^I%p-PfIp=)7gcy z{=0A+Y}3*HBVfGm!qNWIz^0G(S24K5qy3bXAg3JdUx|P@+P?&0Z}GqgZ}C9TwgoNx z?0`)p$=K`m3Lfjv4&?B>|532=o;Qk?mz=kqF3Ue}}Q- z$1}DCW49uWP-?PRG@5O7G%d>LtEsi6sqMV1s z_DhZPF8Fu6D8O|AElQDX@V&e6(y}UcD8tKPRR(6Na9eC029~!d06onOT<74N z%&LJKBF8d3i{Tq{Nw-1`_`xd43R9+IWrPCPgg-+t^Jt1(olY@U<}8Anf>$8yTES1S z?Gw1!VX}xD+=e(O*|HHR_$DXsl9nx?nW$TU-=-yo)3$Xc2=Q95q@0@2A^l2 zcc=|baeCNy`i51du3*9Y2~aNzoCX2vMS;^_fO=8j3=p7R6gUF~s22s!AOY${fwPwY z^`gMpTY&eXz&S8=22`v&8?8bCw<62Rw=7c&1yVWTujJYKl6c={~zc6P&tUwxDPaI+y|RA?nBKRcYX85eYkn!ZfM@P zk2G)GO{#G-FJlp($Y94W&Rlybz*7ZBAotSDBM7z>ECT3|c{*F;x#+C`m6@Zk{pdU& zehi>GYxJyfmh+P2Qv-kwxmC*C8vs3Wn`El4#ByHE-hwoPG8^#gyq5h2{;1>j&Kn{? z9k+LWCu!7id*|(plTfx{na8sPA4E#fO_l#2=c5?sQ04!}`B>%w9Jjv!H0rb^`)Nzo ztEE8pIH-AlW^IS=M`VKGs7qZ-s?)bmB~YgthNuJyQFk=i&x9=MqFE*+wbbnAlZRod zsEG%u?*u^}2duly1_6ctWH3h1hwLb&cB?<&Z(ac+B2EW8)D;6L$!!j&qn%BlUKBWZ zQNXNRc~RitMS+YvsQVn&Eu|tb7K9Xx$#$(m+z;r`2*_H-(lfP#2DGEiBCsOor z3MG=2M0im^A^FKSneKR12zA`vnWi{9Bs;R_!^1v1k@B$bz{5U~^04pBP^cmK2&cxG z3JtbG>^4_GylBBYZcj?orFL3zB9c}I;Z`B{1v%>SiP?&Ci0LPje!yX0>Xa6uWrnOvIGIZpB31iZ2J+-U}NcQA(1$C^#eh@Pbgu;ULr7&hD$2eLFPTvF@CM$j#BBHKP9zksSw<`8N#(o!}Sh>SC z{X4N63f#v?&lmbtFP0TiJ;?2Cw!w3{iS4}|XE4%>|Og$ofa$L%xAT1i{nhjL|h zk+3W=BBv!AkT~%y7IrtfS5GA&za9DIVPgNpjek`YMhblP6gKdoDTcHQLt1*4 z??}`CZq@&8RXrZQz%bG07sZfvVMzbQHHNecL%JshkQmY~3~2)Y#0_+y3~3jJG#{wS zkoHg9r1>Xqf;41lNN23iYKO2kq-n7Hi-+Px#2)d>L%UFUzSn#8d@LHjJj`ZS4D5GN zxvnsi&FPyG+SGqU#iKB=8R2c96SOIQ92v_<|X`YZ>_%pYn`_1e!uol*6hBu z&Ys|(tkK)v?qL}`@6T=TApY{8v%ESo+ur`k8mv6kwzrFI?+;-^$hNnOZEtoYwe9VD z(KOrMF1EdGSW{}-+r_pwS1M}T8=mx9e28r>we7vTUS?$2`k%1w*zG-)vlA~f(o>b& z`+(l|=I5+Ymsbp=E??uxJ`zLF#w)_`P*8E}zniF88@4_jYv%#iM+4N*^ho@{PD?v^JNUR0-S z0VmqwClA@g~DPC7gigBQ}mm@TqFb@R$dltf7>l18) z|7c0kaFyLK6b$!W>c0Tk{Urq#n% zfa4@h2~UskB#r+9Ajf|Ju;Uj1U1{6Dt6l&YBU-%xcvrmuSPsiuy#RPmzW{iiF976B z{2!FHz78zyo)ZdKf`@+vL9_h;URE@NB&Qk^pDp|L?ve=*5M^C+a1EvE9{6 zf=|>-f_AX@<+AM1 zgbvkYk@pCi@(x(kdjw7R0R;Y=Brg)Wy^hE2_REehvFsQIhRd$)4;l{`s>>>`1?4*}-)Fiv<5gg8w1`pX3h4VDP^rkWX^`7YUY& zPjVMv#+6TUU3`)&fS=^L_#{^VKgo6RNiOH-kpCh%H=D5~r~Kcz@PG3(kn(@y!vD>Gm!o_cw*H3z{)YfR`fOMF#h!JP@9*)u z@PFg)@$u#WsiTNqdo*Uxr=2_a>U!_4~T1ba#!M( z{Id9f*SR)O8}Z?{ezG>$g0(?47;d`W--zG+wE_1*y|n>>cm9XKJO4wl^YcHP27c!J z4-KwNiWXo?AZH{|jCE{ChXz z$IvjJr#9k^;jA{|=Q(-Yh`&UP?Th8q%eLSB#MllUWi{Li#XWVCZ*2ROcj1WsFhu=->|F_bRmJt5n|B|1NnS$M z_manw2uVmnfDodhq6SISoY9#PMm`BpDXp2`^2U0a`K{2*KShMy|D4v$)0%l&Gf!*g+1!1m zuZVJSMHELEeMOXuE24luWaYvznR2@torMe+Km z->+UzGrx9{YQD!+YQ6;;Zu(X%4E`vNO%z5y^MVK8azve)8Vg(jq{8D z!v8YDf0O?*;rfmQ;h~J_X7ZTJj7a7)_|JWdA-H;qN3htdrzVj$S5FCTuAbs6DpyZE z0m5EAbrNZF^%VIk!e!)D_>-OO=ISX-6}_vcn2mS!)FROS)l*F7Up++=hP`^K8X4re z_4rLv&=X*IS5IBSLU`|=yG;>kd-W6x^!!u^JUW$KONi&Eq6-{`UU3IWi07xm5YJDA!1Gff@cdK= zf(kkdvFFr~_Rgsx@Xo2>6Zk&tL_EwsivQ0-GmB_z(idFMB zjE+LB^c}9a&QVuE?r?Q+hbv?1J6v7d;d(PZX8I0S7k9Yc2BhzBb#aI5G9X_;XF6X& zC-N0^mgk$!pFld_hy58K--n$s^&PG*?r>d=Fnx!sJKrgyAm}?>c}@-cS>NHx!|Wq? zTK_P6KD&RI{U^x9Kg^yb@DA5GXk>kdt9y5(KbX?FO9GvHkFCUw$Pg3x`lP4#mbnoQJO8~r+Czk+tCr>^P;GH~4A@WY1q(JIBT;1oT zQ19f)SCGa#dGZ4Q@8n5lpzm;X|1N3t9j@-{*}uV)>N{NBccOh!QO}2+W2k33XM@0W zekJ~6o0d^d%lKSn0vU{ErpJjr%${_v%eIzO=O(8TXi^=Fpkgv|-KmUzA@X8d1PUR` z9%g?9<1i_k$d7~64}c+`13tTq2Jlnid;P7&c!TI3#;d2k!2kLVS6)3e5JKc#Jw@PO zJ;kE*9j^EuWQY4FPZIej zPZIf8PcajHhpUS_Tv-WyhpUS_Tp3f};YtOa$XC#bd(B>+*}4;22`%3b?tb8iR2~VU%=>L9W`ooIJ6v-rI`73S^c}8}MYj%jF^dh{;hNK<>s$oO z9j@?Um%cDQ?4;!m*W6QLeDRB4MZ~Z%omYVozWNb7=G@W_P|q_Wp`{P;Khe@Nw3eP> zwDk9oQ0|;!g>b2B+jmZhZZi>iN@GL3&POrM!pywAz}spu!EKq&H^|d!*iOrCQ5uv`T_8@$o@L<9Q!n{`jClPK(xGiA!i3q+UGmH2H;)4)=M`kYZTnQIk zKzxgYOZ*bz6~s8}{*KHt!jB0tNw_1kGhwgS994PjA;&4_&de-Ux@z(vs`*yDHq|%q zQ69_8W#va98pr#LXEX8tKH#|OlDF`ieEQ6U!&P%VVw`;k<`iZ|l%7*S6nmjTah+{? zP66d4J*QCa0{N1r=M;)Ye|}Zda|*VCXY`i|V|q@Jo>MHrcLVM?={W_B{+u_Y=M?EV zgm*WPW;$&3S%5MQwVGHml?)gP?2-zl@@b`@#D=YmQoSNoFal^tcLBh z(6Ddj6zib3&x3|;<`jetfA{7Tgv$x_oPuz|>;9aA_-)`yGp8U9UGUZEl@s-xLgSfd zR34<~6dKPy!^|lNzh!oMPC;1n2B4i&u+qc9sG4_#YMvVo%q#c+Cn3b2SLB1^ss-twuUxmr{@*vwTkpw1->ciwTkpw1xCg6 zS_Q1+>9q<-LVB$NjgY)n@f7D3-|Dprt6{_42UD}G(9Suh_*Sn|d{2l;z_)sx z;_x^1oZ?%(PVr~J?vFCd@AN{2vl@(*nvu`7hONQit-If4#tF|L#H``F%mkrY11PhG zf9aKo;b363ROSS~e{a1x!RYC#c~&OYN0z168q#wDcZm2rrRN0cIYHWgNu1Nt{!3~9 zC3v;q(~$OGioFWMW7>Zy?Y{&)^FP{u>EFKA@S2$u&}?rtY;R6LnyA-$O)q&G8!^k#;T-pqh=*0`A=q&G8!GGsFYHbHPR1Jb>SvO+1F z8E9&?n;GcEX*V+nZ8kG-X-GCRJPg8aW}xS%-ONC~K4tBB5Tdx6%?#YulyfKstI)Nw z7t-6za18?d%?wQDZ)TVTWH&REqt3Z*6@HU8GZca0ZD!yB3wASu9M6zH{z&C+D+PL+ z8Tb(1W(ERpGXsI$%y2QX;%0_z@P8x|KYzrZJP^v;4^B^&?tn-woqo2%4>mI}vA3Cl zAbsejZm)8*;wrQeHZ!ojyv+sX2A|_BN;umzR(qVNoBU2vH;a%?v-obASe6 z%R=tVj%=0WoyS{bxA8kv_1|;k93ZPWL)D*7W-*WUnHEsCcliikkz{B8{L@r3RnOy| zrU72|{BD^I#GAKs_+eCK!^$>yh={VyJszzn+tlmZrEDLGcw0i*7M~4!)hvOhY!i6O zHbL9UHXmpM$~F^w$~J+gY!m!=JBO!I;V*$I>W;`J?d=>U@OBP!y5R2|CUUWJIE?>K zM>N@86WBStlzEz+!=zi^IlK%Z-p*le6z0xhW*2z@Km0TKZlba+jmJR`1#e8*mbja? zbC|oBTi-dn@e}S@+~!<0%XI$EVGg?O+c~@tyX^d(!#4r>JBO2%ZI-a1ox}gFhi>|v zdv9f5_JQ3aD?Hry1;O!i~6~Nm$%;Vd= zox?20+d0hHU+X)EpFOzk` zh?>8MO!h*q#~Wq){O8h^?X+b(=;pFTlx>a|?NPQl74?qkX@|0{^W8*cTMEILI1Ght zOxc#W=@ahL=V*>U2=@ptEl5(fDI7n!vdu!hV|v=DY%`5_Oiw$NZKg?|aF1hpnxWaz z%_VKw_S{@38@}s1mF6v>Y;!Q*JY}2pK@a^@$~KEL%C@{ETS(bvURK!_I&Im`P+fL` zhKgf)&VxR@F=d+{^x_u~F&waLhd1MDDLJi&;<(Y%dbawGig$*-TFNTXP`u%Wo)Idd zmHRFz-q@{rymH)778#Wzw!twtg-n+n3h}Dfml36U{CGIV8^))itgE3>YU^b@t}9tv zUkPn}7OMBoi)qvNrfci$SkDiIAZ;2?o5mp$DTivNP2;qx`iE-LtmPl7xs=A-*lk>d z!J(R50`U*kq^9H_s!9FHKUDKw4?&NOXk>kLLS)2^8|jYDKNa_T*O2K@V|sEe6HHRV1kZPWJ;)m#Gs z_YTz*hsO;Zs>v|_P)#QLN$#U!=Wls!ovpBW+PV?OpGsS2acR@|!{{xSef9${f0Zn{ zb+`p;Ya54Zwntm%8d;LI&W^I$I*SQ!n#sK6Nz4=?xgR;%`@_l|pK|nx3Lrt1Tg6H` zLI^%`%86XHRU~(g!GmebEa;#VjNA4ou2-?P~XSSG%{n+P&S??(MF2Zx8Ro zc-qI^)jsa7_HjpI`nY3*5D)C{U=QqPzM(bn$O`q&n@ZXo*e`Uz$34>xT^D)*5h9r8 zsL=J%Uz0Wm_LHx&SoGWY%a%Mce~jOx`KaTKaqc6Kaqc6Khybc zH$08nce{})cn9_q`3Lsj1-;yNyW#q_?{>2S$Um^3>3p{vBL8qrmggVX{{qta2ljLR z;2+q}nEu@2BZT>L3krfiw_rc}bBjVetv|Qmv-@+4uaS#Cw_ph$qH`}pBjOU$ArU7hpPfX|Qu22zKs6x^ttKqT25AYzlrw^sn;( z9_w-}O0SIWPw+&S1pqbC)4~8xvkbxvrWq=r)7MuGJ(tz&3q_}b|QBp zFibknWm}gr6`f@QsRWu-M!sO6ZvtF`f)JibHHbp z(I7+PFhs>`U+-?Z`1N&K&e_+47cPNW8nCCKM-^cw*W?~QQ zC-4vKC-M*MKMX;z_glq166yWKDo-|dE#@aGmx=dT11`EEBv zzS|9v?{-5pOl47Q=uIQ7kf}PBLbUV5zb4OR>m)c3Nw0(bFz7sYKd|#$elZgqL#&*9 zE`gk3ig#c?2Y2tlegSL;_i3k_0DE9RMLeqoAv?jgkAb=${_E2HPV{4OC0X{s zem;JlI}sd_%IP4=ydQ*|0*2?~&XTN;`&ll^K_B-l zX7(=>AuZ|qxPJ^*Xw*aC*TqC*G6(i|%VuqA@LQUVpKb9ckD)?cmLc*s9mgV}J+ME9 zP1N+A^3w>a}WYMj|gUn*X2liiyV7n3^ePIslCmkw5eQ{tv zKj>l6_4UnDZbZ)KclDX^u0BiC)#vkPiM|c}SQ_hl748JuQ|x;ZSXUc@t%{aIzZn^E z*hyAnr=WLtJFby<2jXqs#WFxP)DAF)a87U}7?o3?eOCZf9gLKt zBAv#9cE(p7jC7+SJp{oPk>`?9dlW)aRnr&vb*7;bp7YMS`A+jpNbCczdCLLjjxFmj zznNEUd7knzH8U#vBvi$2OBLFv?3}W-V_Pbxec~z4JX`UUXEr~nr#uVvmIDa9xx(J1qQ1 zcixdgFma<8ZOnN`;u_~2((O18KVUJwE|Y1D#rXO{>JGSLs~|~bC(~2e8QoXeY4-M2 zb|PP8C-PNxrt?*Hn#6sTU8>-z>_ooG-hNMcrt?*HB41@^dA`cdud1)IKMv%p?EhKI z0elL3#};YRx$X9pXPTdUIe>+3>T&?nZ0d3V)3mW1z~D_^4lt?O>nU%dQ@JlCy%A4& zj-EkJc|DqLx~Dvg@>O-2ZR?;&p#_h9lRah^#0PoAyCEJu{3bDX!Ei(usz9Emj;+uF=NWo zzzrZ|OEH!PE(Pt)AQ<4yAPBmT;0)p^*WoIF)!m(zm-FymVmaU`w~ztzIX^gouruLu zz$zSs^Rz2YM4u9J@!%OZhgInO9`Ff>{;bA>iBD9{bFQpsj03D@0SybB=Gohz_*dP` z9vL0s_>Yj9eqf5WABY1>#;32Z6}^ z0K`-fRU}RZu?LCYfS5tz0uUF2sJjA0{SEk8h|)faqKKOSo@bmTAPPRjbiUW4pysl+ z=;EDn5$8!TDiPH46%gB!co)Q25?_Egi9|-eQkRhE2x2LT&LCa`q3U-o01E|v$IO}m zq8}lAHxT6@>PLfEiQq*HJ^)|>gO31lCW#Y4{E@^g5D$^K0K}Ult_0ELV-SA=F$9F_ zeHWeafvrZUcAFxE28y&y6_1@Rb&o+Mrbu?vYcAPyt( z8HhO~{srPD5UPGSsL?2J2{YRh;0cD01Mznfhl2=x2I2$|TaoxRh@DBy0dX>kD?r=? zLiLW~(Ppqg3P8Nhu&y9JXBhtV*`II3KSNFqL^-r89=c&Fah$jTYhM2hbrbT~X{38I zM&GH3@^z?SE~511y4W{{KK57~AsdpnqVJ>z<*d^yYJDeRioGtB$Ju`0slqSRwD4n^ z#>9JFC?WJQi1VFEdko@yXVT)p+J71LK}V6!mFOqpZF|I(>NHYz`^mCgZ`YMjS&}nA zHL@@Jb>}m0ufzLw4T2+s;Lsq*e>9LLCjk16ACJ12+*Bj`PFG+^umT3CMhc6rz<4*p z3hD}2AQiAcDqw+Bzyhg&0lESPs7Cg;E?`pd2`!KUERX^$kOC}_0u0av7@!*KS%5V0 z*}*3?KsEAhM-nWz{=t=%QPtG

iWZb#{mqtLt8xkaQK`L^oHE)KSa1yWfHq_P%B zWi61(8lWp{fNJakdF?lV9r+hiz`!6F5(K*jL9Za#HVA5hpfLbc!hwiOjoV^Cw`MHN~d1uG>^vIHupWQ3Y+WNla65cp%x{6x$Qw`)P=T$MTvR- zPg#`sK>v#tB|cYswu4ax+!TwF&UX{HgGnKHBlcud+eP3F9CRje(-tL1Ok-(_Qu1~% z3P;+av?&gzY%#ofKaxd>qe0N3q({^LK#LM*w?PL}UGbm0MTxDjc@CyVtkM=GbI=)E z(q9A)9(2Z#uvr8yfGV8p#_?PFHI`DVL1>#;*en7M2iGnFhY@NQff>^*0yDoK=wK>Y z{5TG#lnZN7k|z&1m|BaHSabEFaa)(V|6~>=)^p<)r4mjB-_aH&tGhcbJuwZXMd=-F zQ7ZU{wkW-$ElS$~(xUX9wkS;`q($j{Z9zJZm=>iEG`@`(bKDQLMd_%|VNqfMH)5(V z2QzzTt()CrZ!oSyNRMG4{sy9EM-a6PuNx1l?nwTeh@YOn#?SP%Fa-P_#PcLB2eI`R zAg%}TClY@Jk@F>p`$5!_cpStq5-)<7OyW%tmxHML7)1Ry_*sb3KBHCXdw`c2CyMEA z=%2KbBtYf=(P^HBW)-VaIT$en^{fX`3!-j25Iu+BXLqvq1~Gxe1Q4f_I0{4y2vvUy zsHG_EK$?tZ0^H5;^FXX*c&~M!zCvNgqp+J9$H7GNOUB6qk@XdbP9S=br~%PTVrvk4 zlNbczR1$lFxD14I}-25!$KAdVoh9K`t~o(FLwi8nz!M&c6?pOaVzqQ|$a zWHx4~4an>ZX4VnlaIkxJ25~BhS`Z6JYy;v}62AcP2#FCOUM6t>2ppQC`WykmnV@>j z!2c~bIL*a)uzZL}&(pxDpqpmzb3iRd5TCi{xd8ph=D&s{6IBa>`uZlSzP^d7uQ5?E zMq|K4)fg~QH3m#njR6x?W57h!7%)*aPW4SxjZ=LSRb#+J)fg~QHTov1#(;^cF<_$V z#}}a~XrgLNGEw!TY&Qi>R82t>Rg>66jJc^vY$6r}O;k-m6BP;wn5gXncsvqA2U0GvP(v`J9Dr|o|=*k+P`thY`3Yw^zf+nh_Apr|h)2=}fG*LALO;k-m6ID}^iK-vpGyUk+M76bs z>zSxZ5z|#?f3u#6>N&ioO)ybC^?BOqY18*WQx!@(Jt?Qq>{H0ZFrRchDD}V}!$hU? zO`E7FfN7^E_j)I5Q}#g1Yb*B0d&LBoc6tgN56Z?#J3Vcw6N}PLPwsL008)RSLhA9L z9L&=us)sS(`>vR8UzfDg)25wRv?m(vXX5nKl_sj{u()_w-Q8)q7W4W_Or)#B#axjd zg6Vc8Cezj7a>9QBRxt__41*cKsR?ISKLN(Y-@*L!0EpX3+zw)of6?rOI5jJQYS!@Q zQ~cDf!%v6r9aS5_Tz>(HVi0jG4b)bEIGaR0h$aU_e-I-{3i2fuV1#u3E7eHJ|Vl{}TK%n|-@gQFz%Xe76uL0g$DpWE(2M zjJ3CK8|v-bhI$*@5M%TS*oOK9Y(sqlwxK=&+fbi?ZKzMcHq<9z8|o9V4fP4whWZ3- zLw$VPP@jNps87H))Iizo8?+7eNwN(!urK=tZ9{#7wxPaaj4wKy0QkShR;|)&^FXJXdCJ~Bw!BeyK4{xZ9{#7wxPa3+fd&m z+fakcw#Qs;0EO-087 zRx<_D55rX5=^D=NQ3uBF5YnR@#4RLf`$=TOio-ay+W^%L;?ExVsT+fz3lUg%D2S&? z91Eg42gKQ{<7Wa&TNXtTF95vA zIIBT?0YcS(25JgwJq>MD1oKGUmtaJ45hsLMVkZ!_`5@}L;AdyDxqWCPiETklBQY4n z`5;u!k)URvuzt*FKY$wNqf~oWcC>|+YVp~!-s%4gW>i2fSS8l`{zVq*s0qej4K$_>o8CcA!r0v za_eZ*TFj)!gLn``&zT^WBIg-Qbr!&f489OVUOtGcKs1uL5yS`*+!QpG#4-?JAuZNXaaE|h~5K1I1^O; zp7{Uuzi6+dcbM-!U|fe7s@FlF)*=Yar0Na^xRY%DOWrtl9D>^3IL8?O$s6bRDzvq6 zj?(?3Zk(eux3zJOug{OVagJ}mkGgS=uTWbX=lCAAcjFx2gCBL{9AAo`ZsQ!^v-WMA zI~ro(swLm!H+kdSTpZ}M6qcv!Gu^c1iKnNgEl>EC^YqlI7_!rs7W4E}PB_w*C*{s{ zq$$#tCkjN`^0X-%=h$MHw6}NToQW<+F_GTLQB2x^6WJ3n)0Y-MijUX`_b?~I`-Z*K zQ|YwlpPu?PfPZ=_QTo#2bI?M)uwx8o=5@n=_ViS;?CGf##kA!qZFy?*mWIteim82; zr=aJC)!m(zDNyg}m1It!c^uPidL@}tXpSp{<;l2mFs5^0b-8Eco!~KmvYl#C69)%^u{uwm~68nxG4+`|ps(AyrI^gh8 zQ;J)uzlp*M7IgZkh#`}p{HQ^-SP1RX=Z0t1!sokO;cqY^a@sPLay0jaR@3pp4;y26I>D~US{aqD4F z(UmnW9#s$Fq|?lf=(voWJo1UjA3BtN*Km5V5pkOXoXi< z0ckPgXEIC2#l?e$aW&)C-TEsfwkCScAuHbr zLE=X{8r8fqkh)_!CaMNPVmB(oZy8m zIl&8Ca*{4=DVT-4x17m=&($7h7yVr3!j@&MLe4neA8}yCs{pgnL8p`X0)F@>Mhyz~BrEjI!A7q;9F)V>Q_{##Ff z7HKmZp-6kqE}XPRbL2Lj`?Co0^3zwh!ysK2#_(9i?$&o?XlECE40vHnF&$rWU0%Fd zdI{R>EJowm<~o%?wld>m~<&4%VPB84Yk&53!gW^k};2XZ5hCEqwa( zC}inh*m5Kg&gvmkE`wx6+v)70>-KMUc3~y9yt4~iVe_0_SRaVhPvz{w;*80G3(0>Bja&dDMfc7`{{Sj1M&3?Uh<%^vlA(%T z^|2}*I39-;Rfm{K$-wc)S^5Y>1U|&#Xjf#^p9!l&e?Z*)a^Npm9gSyHWT@gn%&Uja zYY_9&bf_Eh8pOObJ_)#RN9NT-@(Onc9^~VaO5`-mDY@{#ANYc=*02InWSDiPsP*@IOy8r_A=ZN;EspN zT>5{^u6Jl91g`WEO|Shc=qEH?LHb_i*E{sYtxj{{Z#AFo-KS@Uip@tx)W=I?(%)O^ z8L0;&wgMqvri65okUJ5QkHUj#dNZV~21Q`Ht9qw|4wQ87BHgf*kbM}EPy>>4JB(Zv zD+T*zybYxtb**RKhNo%PPt$Tc=rYY;PJTa4e|QJzyEL8p#Fru4*bHR)WJ)bA>4oxQ za}e@wO2{IHl#NDVe69|tOz^4imCzL?v@#`hh2**%x$cw_vRcy3KvkLRxRg+*H_KdV zLQhT!Etb%gCUjm(=pcqB7NX3;p}G;+)%%jGVy}aJ3SN-H`3&kKZ`~pUbs7L>{2MlG zACc<#>jAo}j?A|(et@R=mc@_r=}w)%C>9awBO;_a^-AS*P6}6LuR~UN9@7{^)NQJh z-p9IjnzE7P3AH1tut-;v!yLyQh16k(&JVM(WSO+;SszSzx5T0y*1}`UcP{zX27- zNX-D-7EVhQnoEz=#*a1%mJyqHKaFL?CjLFJ9kH3duph7)v5Bt&wj(y<_iYj^qc-vB z8q26n9NHS`&8W@vXAzrGoA|bEFv`oQ&8CT!?udiQAhCATW=E>nXmBqEw{Q&Gx<15= z58D=u*ffOP=*909((z}5OACsQ-%H|OF7f9hwR3; zANYJ9??OD?$5#>$^l>(hbAMx9f`$=tMOQ3vEgcb60w+YHC_&kK@;sT5jD}nm(KZX z3Hb^kr=)~Lcj6PwxmS z+lT`#`!=wO)u0`gc;mco+4w+&lr;)Sw8=ye~F#Q3Cdq$L@K9K4N}G{*mzn-!@tN-@kSq40%Lqio&+`2VyN?tyuoHSheKM#GDIDYQ+IDut8Lp#EsM7--X_@Li<(aiy?vaGO#% z3{tbc6i(Z0DV&ocg=0~CPzp~5UQY@qT=%3N3u_*9npZ#*dSIY0g{^&u z-S!z7|NG{#bI=fG9&6jeY1s?S<c}Smv?Bj|1CzEYpwL1=x&` z#D4>}^H|2;Ww>CO#}Xf}vCLzMUjw%DSf)Q}S70-bB|c`iq*>j+4y(|YtRL_JvG>Y=>j#_gGxYbC2DXeYoL5#naG$=`}hpT zEK>uMV?CY{>ovwwWu=VvKEHpMuYysxSB5HUAoDbxBPD(pFbk`Ed^quLKK?E7_CCIW zxJYA4;q$=wSK9E1o+OrHs%IyO43CaPc%lwmJKZB!B?hE&Vk1zq?GctV-+dU-?0lEi zweww}&3spAGv8(AcD_qGacycjiQ7{--qcfSrb;I)*N?Iq5rdCXE|2m>YVt%T%1M5> zvh_GUQ#mPxcAkdzV<)vW=k3A@%H$J6$3Gl?YY)oxzO|Dv266uT6{=r~oF3S7i+pQ? zX5urDtu+(>M=j{x$?;b&=-J12THZkm>CfvN)VmSAS15DYst`j!<9p=M_!eopNM;XJ zAzXQ?ie&Df=|WjatJY~{CC#H{0?a&%#1>nv)5`Zt(}kEX^pKUaVpb2eQ7af-W(>7@ zovef*QG^u9N1^rbs2XIdcD9~ z#yyiV5Lg^o1l+1pmAZ`k4I*0go?#d4jf?`zxM%JIY$lpqaC(1VU!jt`0?WA5_d{NR zW!w%hL0DyqX)h!;$`tXR_xF`4$t$po+j|W13M}J33~UuCS@;?UY!oTtD-J|n5Jt0% zJ8fWV%eZsEr4>dm6WC?kmEZ=Kan)lOX3R2f=f^>tW!z!pn`PYP5X#^(?t%%>eJTd6 zzl?kSM3fgBfsijj=)qJk@Gg*${s>83#=VsxWg}2D?X0QGxQ|G>$w)U0gJm$sml=|n ziI5=oBXU)29@xQU+*wcHY3wrY-$0vX+$YF4%ebFD3EC{$bs6_$$+bUnOrH>pLN>12F5erR6D#y5`O_78Eo1+K{K5I>WQ3W5c5u3hN!m7r({eIei=XFi z#WX^nf<7q3K;5k?QHOCCxd&Y27Rgv$sZF(dpf&)rTllq9g_wz+`D$7Z(we>oS!!Eg zRp?iU_aw3Tq7%OXtY^K|Iv*LNH651$TGN@QsqF7z>Mj+VV726>?SYzJ%Y68S7mIWm zpOEiZIf~FW={jwFPRxb?VTCr?Qr(GL8?=SFUO#9j4EQOWBU3q@lTxH=3D}?oL42ja z6T}mZAP#uiX`YF?oiNE4#3Vb6JLn;Z^)M%wx@fBB*97pwdoVzIe!299%h=V49Zz1; zMa))f9E*@k@t4Uca0B}-{n+`t6el@hpt3AQUGa03&J zXZGE|s*#&@16zdLtaHKbpjG}W6wB@oe3_JO7^em2IBBi1hzT+efmjAK25)VI?W644 z2-8^m3u&`9Vl@V`evgc-VY(ym5@Mq<5WfUWvvQA|!;o>}P|PG3LR?wZj0U+w(V`od1g5c)K>B>70+ty9@$JBNkql?Ut2c>_7!a$& zAQmD9tP57RmO=;~MSv9oSqm)_u?TdxN_>SbD$?jZ|FVL!7u3t{=R5lJ)^7+F$ALlW|W%#6~cg}-x;ZUtUWZ2Fz}JLZLt zVUKKu7n@tD&Ll^B)EDNPDj39h0g zu@b*c<)kEmZq7T2T(zHEk7q<&8DQJOX_=4a5^*iv8|=A|3@fe-vEoX44Z^Ir5`P73 z#r1mN*x|mo67LGE#g!$N3`57A$7ohuCxcycJj0 z#fq!YMqGt9;>!A1aV4GD7C%<@$WV!0QaPUNNw`WJks2Yv^@XHNQj$Pi=izy*xU#P) zKS|;mMINsDd)yP(ozY7a*ZC0F=MeudQ#bIvb+2BAfqNGxm$H}o@tpu(Pz^KRTXzA| z?B>MijbhG~Ur!C=hjCNYFs2F0uHb;|3J%Dw;3U}%4z=s6VOvvnwHjs{#%ZChBE~yW z!#<_FZBz|o8vF4jJrCV#Kfc6&1GXRE2yhpu)%N2{yaTXSP4%gV$0pWfA49vEO7#%XyQ&BL** zdkF{cj48?TFdVp5Lmrbs4VUjS=`#`0s^!G~oh(}`oi&zf^vbB^P7(m@T}t?<9uf&=58;J~;iIBDE#`wWPLvY-?8@N?DXEH12r2m14R?dk#9PP{b>%h&#M$U;> z0BbpCbz;NNtINQ)avog?IiC!sm2*~Z$TZ0LOfYe&caofci~v=}G^uhPhlnQ5La3E< z*3HVf&_>RMHgeATSve=2fW5_&b23!ogj9|v=Mt{ERG>1H^J@^%$~l92@|{WCwvptJ z^LcnqE9d%SpCaeGhbZTBJ9~0|1-h3X`PU;iWdh2)nVtMJs> zZfJPu1rRy&P^r*fdc#~iOX&@DBQ=H#qux-rx7|>Oy^bFtfg2i{xelqdC1scFIiU4y zXzegz5?2;Sfu85A972~ zLuNs1{*EUhXBE2>>^^w-;HIoY5!A_U$YRUb4Ov3V>)am&uU&M`?yZajd*DPg*q7x@4ryb z0tH{FMp(vMeW94iNCa9%nfO$V#acl;S7Ujp{t6sB#eb<7K3ijGRXsw)%QZ%NjX%{` zUM!~n1!hzB#bW%6G)DRwN&lS2NU!lPPLufZaxwi1VsF`UXE@=OdYK?8P^)UC9V=k+-*(iSbX8_>-9vP~qY1iQXYr<9vh^zTo2< ziRb(H1>&=O{4MbkA9uwY9-oPf?QR-oIsi<&n}+y6;v->*GliZ>e5jA-6Pw*MjDH`o z*-b;-c_!M*>{BA128`#Qk7EA-7z^wsDUF$(Bz)|c*-0X_@vIU0YyFNgFASLr|Bk5& zh*(>%E;h{HCANel2d+EIv z_Pgkg)YyI(-M#Hz4EtSlhh`#Be;3_d0(&v`4KGBlD*qqse7zULKDyJgKUzm#W7&&w zCHhBRW7&)G0FZr+WrISidoh@UeSb-JFk2{$!BJSJ+wB?h7EeGdXM){=A?eMBQ6ihY z9Om07tW)i-40($sebT;*5@?AZKf4 z2IVaCSM8BA=3wQFbRAMz<%`(J9ath{9dWp%HT&djc{RWgwhxw!qwR z^Y%@oP9#_30XBaknPoqip(R+yx(^&Lg;w2g*eNBkz_dOf&MepUK-UU=L2lCYn5whRb z)d)}}OTirjuGM>)*=vZdN>(C-<`^BnS4hYI6x`o=@q2|B|8vHVm#)?t+D_mU{*$kK zZ>dUTHrhF#y`yno;L^x0h-9`fu)d=h$vDgtA5Lr>=7}#MHZJ?bw-E<64lE}Qxb43} z9N0YYF>%0g-uW%6tV(K7jo%=zU5WUwUA0BtRco=QC9_Sx>(tj1)%gLhXWMq3Gxh696Ni0V zr{zJkh(9eYMxR(eYlc`qYePfUt3sr)+z2_Z3OxpTTc$Do)e_J6R~uU1Pf0UUD;i8Q z9BGQ^DIw;l1AvN~AqR^QR3dZ2T4P!n4Q`3dR(fhqYL9Bm-78q6GClf=>CtuQQF=sBxTJCbsMHiaEmf==+BwctO(grMdcWEpGEz>@Fz6`7=w?>y6u-py* zJ<p_=i@{yraZFer)4l&hr^}z zd!2|*;LD}`US|R6m&^FM>gm7rfHh99%t3o^RD}#J!zyXKeKM@>3i^8Fre|Z-I-YTG zWjy^hX})z=l(|@Sh)JFCGPa6GYm9Y|qTAlX*s5QNy3m`zs&p|#;d_s3W@u#v$Ux7< zj7Mu(_w_hir*aZWDN@Ji&ryi0KCJab>H;HDEvVZxRAuX%e343CI{&FXT2sHrpQ3hF zT|OSPYwb&+k=kR`+LuCmTMt%iU&6Wze4V^?mqkcz)#ckktNb_h=)FB?+YnC6yGSD6 zV{x6h+Y>1>K3j_twPlKt4Ax9zHDl8L%w9geWEEX3{A6=FHjhrNJiRaL14G2mExX&Vk^^~pENb0H+dV1adwdwZg`%d#D#J_3r2D*J? zi^rbt@?lbH<|>qw;xt3e>siP49; zr@6*#pWSJpXNvT+c&NUE77TuwTlZCF8r##PvoFD?(-;nk8#R`0{yXp~#L~?y`+lI3 zchSv%LXe(Q)P?xmDt<3HfeuxrgV9Npva$g8Rb;SUH`Czgs!!^@Zr**R{$NZ)4wx0I zn{U}bH+!zBEGM&Jhcm!g~|5S@&AFXK(>r(+OeyXx%To^ai5gljJ9{}obCyL|(~l`2nrBXZCI#givK zca1pDkx3wu;MobdhrHTohbPs@Q@)$WuDrNfO#f5-Z1lW%H3uXCp;2oTW<9hbY}uJsLbIDtk!}QRkxKi;=}n zIKQA(6Wvel%h}ctC7+#u0wTE0&r;h8NJq2+hN$h)0Jb5VmN(E=z5?D_iWSORC2_Zi=u5cO{NL#z;sv^x_A5cU_)1^vAa2xH zx_mF-BZ)n&<0_z74Z4z!9#-pE_c64NVPIOVV>-%vh%qOC$tkMUI9QVp5ui$EFuM6j zklXDlC@Bf^onSo@<~t#@`A!IJz7wn)|8;6Y>C`w9ZD|~wU%Tq+CQq>H(4@3~4E_Wz zk*MLc2iq2`R9WIH8-~fgJ+efRI~RYM6Y_IeCWF5X`XVSx=L5GYOH5{EiS#l=v>Gh&%NmO;afPI4zLg~w zKNKi72Xa6+1S?DXddIoY6uU4F-$_5qd3Qkh(2)@eyl61+MPgO965`e$q5ANHe$of%mE_GWuOX(ZuG!WT*6dgGpf?wJ&qaIw=5Y>s(vz)z zP1`x>rN}IYyWil?4tFPjmJKbCS@NySvU6m(dliKJbWQ}lX~SK}3Jg}SFF|T+j=Ki5 z-aHdL_BSZ3QdWg8tbzl=DmWmlf;T9vtVgo2e#c&`bXY0d;!ex6=oAWTWsC_fLvLzf ztq#d&@ESYRYHU8+Jwi;ThgwbVfrxsj)p!c9-Zj%B^fKb!LoB-qH12#Y~ak8-5QJRGp}Fb1<=bee3Yd?u?EO2*Rbum^=wugEduU6;OfD+QJ&~6L@(9O z$c^$8+8Not?R&F47P1Ahk^ zLEjGH&dkfBd=Gj{tVbV&7W;t-X4GkjlKr&z@wfW`?9mC~L3o}FeIcejpxS7U`a(>j zFeblx-c6Y7)9{+xlnV9EqjA*UgekPS36t+ZJ8r_<6VaZ>Ul#KW@rItOv%UtI!xQR4 z*JjFCmouH3PCV`tX9l^K>lOSSm!X${=n=lFT?M;{j#r7slf>L`E zCP8O=6DC20+QK(s^10e`6DA9HbGqR1-2<|g;qf+d6Q<606K}$lLU8pI#i-*flvUwg z8R7r=w7D$t>a0h{<(}!}G-u-f*tQxK z6GdW&caX5IMA2Ax%JD2G!bi%FUBWVd<7Dxw!r~ZCQBm$}oo8umTgLpIMxA3{ya%*N zH(|1b`q-(cx;t0r(h&QY^7jW_UQ_HC*6b3e=-~)XC5Y`sG|$O@9B4r7F{Zmz$83&m z!>|@7XBEN*$8aVbTG}aEirj|9Zez>^PT}c5yTza`DEC??-@((ajGaMroo<&ku~Me{ zqZ5A@xx5>@kLj-0C47j^{Vj0EZxCg&dv}DlGfL+!33To~fzG`**tz!wJNN!z=PnI) z?gPQjeMon1&ZVs4@@(E1S&{SCc>s@fnTXOWbM_~AqRSkBnw-b2PyYiDW?el0{NWOc>n+;@_8w=IcGe}Sy}KL(hSaN#;^NQ!5aKGG=KaQ zWUxvy7?$%AR^r^hOPUcm6JacOU(cqpyid;2tie0cI#hIYP6okyc^pH><$TAMd|yVD zN%~Gpx%$$-(^4Si0nNee_Bp5__L=Y!Wd1q3Q~IiI|z zmhLTl6XpTP-@gg73MgMi$dsEfIgCNE;FK!gJ-~^qVcmLuhT2SUisqn;R80JUCfd5q z!c({h>99!b96sQ|PBD{3(WXpM@+cl{gnO71xd`t^?5}*#BlPQm;fCl)M>^b%{ej7+ zXcUc|z^sqbs5n+nG*xHPIrb{k9jz;|uuaF|09}rG5cHD5FhaXL!G!naGiLcJ(3vjt z%PH;fD{v}m!BG{*q9CW@Ec|9vRDctz$U$yy#W$eCs>{vDE~ldNaAvU(kxUldI^4o6 zc9bmo;n%5n7{3{+%PxqN)1&Ko2<|cmbhIkbi}kt-8AbaFEf=KZo)Y7WuW!PnTSe~7 zj%<}M&jG`&nDXRTqbj+xI&KfXndW8a8#3+OPv4N4p>N16c@jw@xgR;%`{zKxpK|nx zFfBO=xw0}=(h*sGP>RW6qWl=C;NLu!K=)AeC33g zS21JC1)RK_UIwo3Rq=VCy$d)Q;9bB;(EUy5>Q1f0+^o9pv{X(9uaLa(A2U?d2|%5R z%prBv(-GdYU^dcMpMb!6O`fQnUOB8okEP7CclPHv%A7(UmJF^SRnZssJ0Vzk+lm~lw#O=1Xsgh|W}P)hts43R&H zA^PEym}{WmRK&+01zq_(r|<@#${26Wbbs$;-wjj~<9-460HJB|GN27j zVqQd8`zA5#piB9a7(Tl{iCK+Yw(uk-(7E?#1v+;NOk&Q#lX#Pun*qE@%%cFCI*EA- zX}n1c?`Qk(nZyLD~!v)T)l#fG%~LBAjgJh#g@YJyp*if24A^ z6`RWzu?bh9r_$-{8as$IznUbZNBwakj;ZmNRE8oKJvW>3L;4TVj| zAJcvr4yLN`(f{i5O5J$%_ckGzkbF`nQ zt3C2v?P85gUW5tEH8%qo56=^jedr>5-$Tde32hcf`Rx`DPuz{7GG9bdq3fgYmGu@! z$ybqy_;~|=S*)g69Hmc{_3&gi%6fR-3>pV58V^q;dvTR=v5RG?pB74`mpd| z)0`4zFJ!EFcK+l>-;CXlwcpjbv*2D8^BrisRgYbWZCc|6s zCl3^`=50--h#N56oy30Zd3fpqjfbZ$@G5krJ5Zu|9-dO5_3$L{JUj_J4^INm!;>JW z?48Uyl%S2=5!s|w&P(`l_sSxeS-3O|uy;0}KskkrS=Uj5Tt`I;!2KOq@?3$%(I>#O z${uM?*<<0Jhvzd0@jN`=1DK8WVs?=?@xwopZ?5|;0IYdzFVC76N1d%TkF>JZJShZO zO$5(d9G!z0#=}!08xK#3Ydkzjdmf&X0ldXg0&j8j6I8r$pr_0ar8DIe{qz{ zn*QP_)A@^|M81b7%kw=vxkBMDjy?nAFOD*%@8QX1O@DEeg5Z02vY&kq&j_B@UmWGL z`-`KWAQyjelqJx^lLrQS9-cdbX*@jr&b=p-Phpik(x!9o%bE;eI`@77rgN7T1UmNt zNpCv$p+f0g>)}bk_dGn0Lg}7|=OqB%;^-0pZ*lZ_0B>=W<#-;Rth49g$%=X&p06N{ zw>bI%fVVix3_K4{rtv&H&jIi}Jh4H`SN1rDdLEuk0}sz@@E_Z>jL%ob=PDD(V7@~L za*c;4>0Fm>EvdM!8Av72q?#--k7G>klwdOiVv<#6VqU>Gq}e)t9F+3_81g0HW6MB* z#nFj~`K`qm*6rdbU44D$PA;%{i=zbo;wX#qojc`~Ls=BRT$dU9i=%UyiCr8e@E1pk z{Ke6u5#%q9&H}>XD4EwHnyI+IIQjvzwTq+jjq#j2b=|CUC&PT_PA22xD7n6K=Vf>` zyv0#=oA2DozV@9viG1fyBHy`_nfQyNtc35}$(S{?%PjFU&y5c`toSdIF}_*rw0 z)2KQ20MYRp4MTUKN{f)aw1T%dN=~lJ)=6*-l3oX6iLiGEJJ)5d2@W4tPTrHimGb); zqIip=9M`?YQ2`TBC>KWs*u_zKdz=1_erw3IdXdv|3RI^qIN_>mE(L!$G_bDy;TGp~ zjdMllNNQv!K#5{B-+Ct|H=6KZbUQJo6#p`}%2Jn$9(Fc9_+}+_XB0<6+k}ov&LzM7 zwX~rvZD21Yr+X22x>qJ-)7QO-sC)5c2m`uT+R*0fUi>_Gx))z* zU-zP4jIVo%myEZ&hRD~wn9kR|=vm?GUJTpN?wYir&FWrkB~SNCucW3|Qr&tdC+(Pq zjWs_T$F%H7hwfPep&{jLPbI8M9HdnKv4OTm$C>hzBdHiKD&sO#gFdNS_#<|^wHa`zT*p}Egzydwf7=dRRBk)XP1lBZmF*FyN#yB^P zP@SPGq&!f-G#1?a%*38)jKJIcOyF&PCh$yS1m5On0?#x?;F-nhsc&0Jw zTx%NRyu>q&(E#9?#(wbTXBO(2#@f00nQ1)J*ckwxX>7xrpP8nO&Cd+RJH(Z&P1yWw zQnh#UvxzR7pGmjA`I+yrY<}h_1N#`UY|W;625(m zd**%n7?E!uBl7KIM818D2=+0G5T}VUn0xjya&ld^PJ#oG-8^usu!n$cHV^Osg)-I$ zj4iSGIsCqhejAj}evWXH&vsPARB>)IB1~TaK07A3Y>Fo%2G4#8rPW3S9VxhUuIqSR5LUW&U*7rIN_c>=@78}S? zxX(HJaw$>vIj=+!(r9L%bM}>SahJ<<_y*)`?Zg|f6}0?-*MZ89#;;TU4SqAq55jM# zyz&i5dBxy8_fg^Ud#R6>j|L~Rd=cnK`30b}uqPh>yF!4|3x3nR_uJ zsPg^r>y%%Klo{pw>D=+_mUjd{T;2q_L-|?w%`6`VPNe(_#LOx`2XuD%Z9`B*`R)jf zDz_P|oDoiF5b`c&0k*u6PW&sDSB`k9d@_EW^55Y%qkKF3hRRFv>z3bve8c6};I~8h ziO4Fmd?@%4Y(`+dhszx) zf=RAMQMmsliuY68Gr#S`vG6h!QNtqFm9oV50c(#vMqW_<$J~OzHD70=`GgvycyB zJALse;H#=n5fH^pq|cWiSi6Nf2J&N+8A?^<;R#C-r9K9NnV7U_##+|sFo&gZ)-ulF zGqSbxGalBNRUL_{$}>)uXZ$T-EuQ#@PTcaalxV7Qj;vxPuMy$tr&MxHW*tz&L_Cjk zlzjOUf67pOe}i%!Lf``^rQsrUqjRR5TrmQH4b86u|0a44!VhNTCOlLjz^@p&9w%5h zS7foAa}lT-Z%0-a%k!}LD&hOup!#6(r@0bOyT}Vr{c6aQHm;&Ns-gG)zpMN<^I&S>|#wq@}JB5mxPQL>I_;df^lc{mDw8O?1SEA-4Sq@5{3 zDHFhYL=I_Zija1u2x(`EkaniPKJ}q!p^$c_2>*ghi3f_F$(mdSrWNGADTsh zatp?vsN4mzg6_>51D4-w^p@m;@dq8M+-nQoVzTa$_w})mCMdS9+ET+qk+e5Rci517~p;=Oe__kr>g+sH5I>+sy zS)3_Wl-m8~RLUyjcE362e>HKt-<;{{hdm#gD-+56$8+S^eXC5#i9R zr-25L=@9JhyNQ4og3Z$sno&@A@zZgG2PRwkZyW!xT`#b;j=w})nZ zj9lK0+e5Qh!iSKP-y@%VduZ0SU`ppMDfBznxKv2z-W%-P`=mcTmkRcDp6=YG!Ol%_ zsgTZXb>7Hxp}ct`=RlrI#oYj&O9khE4F%@VEDBK*fE=2|Iu8JlL$lcQ-n{W;r14xT z-Uk?3U=Gb<2CchPoPi9yd1C|K)YcEpVmXsk8Na1$Q#o=f!TE4PAcN7&T&KrZfQM$4 zkj``2){=@!cOaEOljwJm#gHcI5j-?YoR_>qvp5}$+e5PmRNNk##iHCe4kcH#?aOiEvYXDYK{QkG7!){tXx978*7{Y*hbC?h&C+$V z^G1e6;`Y!iCX1qu?b!n~1U!;>zg6*5)FQe>3p zl9T7Mbvkn(l3oXc8_@G`pfG>=#q7*6#LCIL63A`ndG4o((#38%=iuI@H~SNt&IMS% z3IW!yg0FD+_`A?=HJxb64W9x!vv+9?baI(bW)8|{|94&W3HT3%*$huWeQLn}PRm1x zRZexhPp8K~{uydw`JqQaA#Et9JJCzP6)k_OuRTOsLFX0Rk+EKI#7j6NFA8GT&4(Ro%u8!Ze%4; zN}`N)>LHMI>Lhg<2K@i*T?w2N#ntcL>F$}?>7AK9nO*i6b{ANX`xX%wL?s#(j~Jtf z2#TnP3V6gjiUu)?y6fsd_Orpjk9>IvlDBdP9Y7&p{|9@3o)r-5h z7{2%&yT9M`*1zi2UETfqy;rYvn;PP6YK+>{a-V66?Ds;8Xe@#z;onU1toROa2E_T) z0hd3AU2pg$-*tWGW_%HNPW$H!+Zm$WWIJh!@*vuL%&Y$&*v_sPP8#c$dBS$a8O|Q< z$d{);W(IHL@fiZ6s30(k3W7~5D#%B7qo`nJqo^P-iV6aws30(k3Ie03ATWvw0;8xP zFp3I-Ev~3wzj~smVC9>ms8Ho@=8k-+1atibRQ5@V3Zd=FhWFzPXI?X$F$D*j<(?BzvlrswlgBgw(PQHPyA@3%UIr40H&?M zshWs?^;BAz7U;e<>aA}530lP4bXBBxN>)5pE{(i0B+?c!=#ETK=(_n zkg#u?XCdy~{__2@Z6(nYAnbpr<4&&QlP&yVi8Em0-`)0skaaJ0215S-We~}B2$rKB z%naeap^~G_V@vuS&6=B}jr=5-!)iKKAw{*ZNj!lKM&T`olCs$6CrH}`SlZYeYhz2N zHnvC`7l4p$Y?U^y1Zw*YYDt_wGhjPS3t4EbZX7Fj?!eD;4&KFlx4enkPs48-x=5`+ zBlhTRSp%zcQ0gi8`A)D1|4NipB{&1&Z^`U5~9~*6LsS5W}@EI9eqn@+3nrWs-rKl{Z-Qbs4?+{mi>`^Q2oQUf43La zLMwSkb$R#qKCAZch?bO8OZ%h7sP?ND-SAlZPncoG|A)H$RcJqNlo|i{tlEDy+g~H? zj~b)eKSb8g3~7HB5?jxC*S5d*CAHD+{R*djI@-SnlvuqU;C=8#y)H|YMt&jg+un_K z)W{FP{jmv+e3t@J=GhDZDaoyXw0EOjq>-l!ZtLWL<6@m0aIdpY zfHXF_JwC>YdT67O{}F)E$oG1Hca$iV`uWJSH+7l49^moP{)7{(dOg5X#2^6jcrE~LoVO>^+sl}K6L67k zNtv;qa$?#~DYg44r8Wev9&36{Y9bf5qtwJxqf|}(q@>48P0dnMEo|RZO)ZkX18{Q& zCAs~>{wQHNa0~p^s||wJ0<}&;J6NpKzXEjp1+S+ZbtX`1FT>F;Mgm}gbz;Ae9MeK^M7k`e&P#+Vg%cdNHKhLfRq$Aj z_GI;gy$w6{kY=YYK$bQTJojNQJJrih^|DiNI=Sg{;(OVt?ko^{*{NQ3iW_CRvOwh5 zNiRFqd&J^Dune@9g#S706g*iCig~iyDn-6Yd$JlL04|sAC!00&^@8<~wY50y^{_VG z8M{b&V5pI3PC(nbd+pvR6Y5g>aWBy)Wvd;?@bONk@%~|oU>yj=fqdf0KF2aj?Q#z2 zGCl#9@r+B1hLNM!n4QA#^$a(wFg?S2!&G>CO1WU7xrOOlb&~VVk#P&dIBx;t_i=1$kee6Ut7s| zWp%tKLZ#AXCzJA4rH=y+=dsAEk}Spvk0rRyFCsyEnD?$vFk6|I7|3nqzfCJET54;we|ZX)nzDP=zoJ5j zxi#8fp=Or5XZ@8DPKC3lp^#PLZXpa)9J4Ex*Cp9K>t9vA0CnZV_tAC#YROXwANe}K zH5JF8ll6{&83>feQ~%3uijm^+)IY@)a;1p%&u}yMBrzH_+!_s3MWkG60W}gSms&oK z7Lt`!!>!T&*>3ttv`TqA^_QtK)lL;3Tcb&-cB=U2x-~=6Ffx>*xP2VOJqk#<)beo@ z_x3=_rIwGQxS3DwRPirTNb!mO#i~B#Qp<Ht(-MJ`9WUHt%C=H0N1)oAB%B31cmLt^o&aiVwEw8o zqqau-k4c-=)@c86skA*jko7!SzAy4j3u!CrKUF>-Ky8io*GU1>!>8~Z_MeqJGs1(e z2UuUq2l3wFQEb6W;Z11hzF`T$%UM28XNDhOBiRBWgbNyK;-y&rSC2|;Il#Hs?lyyidFwD`hG^l4XBE))} z-IfPIiNYsD7%y(xe*4%JP34)|q~f=^sWqSwZ}a|Ox12zEoA<2R4 zaJ5OrKfq1RXR+KB?ay}AJ4U?C`%uJk7`z&8Qt{`gG_^^^pX*jJ8+S$Xt)#ro`-i%z zK4}!jUD5vG>dsK!=6&pn=3Fap^Zo*bl(%{RNQIQQc^@86S%~sB?;oWap*E@b*cHuE zls7FOyP}DdH!UCD=82RyEg#M#1cgW=z)O=+yBUB(si) z2@?H)Oa)(-b$on8>tvoJenGAakyE_Q`#6f5&vo%O?_*cA0Pc$R;cZ?3cSZX+ikquD z@l)I_$-xyT4N( zf#Gv2USRmo;DFNKt$3f|C5&HLv6f*697+1>ir+B&I%%$}c#`2Eq`9-=Erth?=I515 zF<=RL`zoE9=Q@;4G?^o^ycg@aoh4L$w`4m@_?_y*kXPOVXP4^X)!SLZ%ljOMsC<9q znN-#{wND0leSort(o!Ti;ll)trGG_dOTqxvmo=3RLy8yvk}1W^M1WLyCPBZ_8i3L; zBxo*e1_;9@=4p}Avf*;3w3dE|((>VCg29zH0#t=rl5HiRKKvWHUp7QQYxo4ohL*nw zvLRt5!LX3?Fd}@LU__dY9^<4r1@jP;<%9lllTbFFTZE{rCnIxrD}wK<8gt z$W+fwLfH?5JFDj=q3j3s63w6LRoZyVjxd;O+!d*z6VNkR4xY&> zP`1wsqWZAm=YH1L1UjctJd-spN4TU>Jd-sR5cV3yGg+f}CTlz%MI{?|LVU^z#PsF0bGxbMTSlKaH?>CdyV{-Ar4H%@|T+Ww!6(ah{KA+thc?Xyk8Q3@-t*au;CPV#Vx;e_8Kj3A6P6D@ZxOy$l~|D}ddO1#o*c zK&l%c)jf@`y8*0nU>{al4*qi>(4Y#wC#M6oiF2;O^5{Mkcu*-=PXHJ!0xBWDngJH@3kF!^a|nzg@o1JZnq}bD-3^T>O3P-lMBK7FfYaeGGs;bkeFgV2 zfBEynv6taLfBA2Q&acyauU1Wln&O~kwTv-amjCrXj^FvG^57lHBT#U41upBEARdGTPGZ-Pwv6@9egJlx;0 zO!1|&e+9!``}2ANDaN1I8vy)hWpSyOaN$pvoAq7?z(*^`%lPxE2lE~I^J4g8{=5!C zobl&%F(|Y@FCqRUe_r#E+4zAb&@P{@Du0`e=+d7Tb{5c|7bQ>DpBE#$@#jUiHP)XO zk@e?A)SW*svSmH<=S2@*)}I%hk=Vd2%6aKvB+sV~O zq(%O`Vw1a(KQEcw$e&lIBhnV3cH_^BzNw7$@LB+4J^VC)@#n>Qj6W~7xodx3>yc+# zrX5%Bsd9b<8h>6aplkOE=c04QpVv0HLybQ#xSlurr@-_4u;v%g0BwPUzGx>pdgacR*4fx$@$3y?z*`pRT+F za2$9`I$G6z_>*qSOOJH>;^DsP`=JI+F4zr~BVkx;O^e{&xewSx?e zI}?5SE$S#^BU+sA;tHRv`x|y{ThNl7`#jjWI@Dc~-XiQ=a1hG!dVb>VNg$6-yp?dw zNo&$eT%Gtm2t*&DPrMa^?#^aM8mlyFXoq$UM`iR7;bSXw!^bv`xgu7Duh{Sb1 zMQ--QTV{hkLc3=@gZZDqgyY29p0aZyJNL#_evF+H9Yo|UOLP$4cyWcHbP(S7zMO5* zLBKt0oSjQY?3{E6G;wxLbP&;rw;^>9-ga_|nbJYPV;hTAI*91RThT#yQzb>|AiV7b zC>?}1O@PutcsmGCItXt^0Y(P__pIdFL2kYg=R^nLom4I_anV6|C#y%n~1TNWP__S7||b>}Th*g4Tbc+f!zJ699AXBBp?rjvWtnv>CV4>|~z zX>CJ*%*DH4iW!bP%LeItZN2nGtrbCUVaz>|D()q=XJa*twc$GnlY* zHC%BXbP(*j-3%t|TutPjl{I{7c1}(1n)u}26`$O-idR>YtJygHf z(m{9+GzdECIv1L=zX?40Nzyk}*) zln%mMUwR(qPU#@LmqKCZLO2nAUQg*0Nu<0%fIkV&?+O z&PguvZ?RkgbuP=!6*^G<+Rl`W5*7~kDA_r2@xsxur6GmvoV*Fh&dGxSItbp<Tc6M1Hhvvc;uTXJIN#9L0A(m~KOE9cst zcuQnYyd|Tc)5$YyP2`!Cl=egqB733-kv-9a$e!py1RX@g&dDfr!Oqq386>lg zN!Xa3tK;J%S|=N`bLPZbGHvF>TLB!0h@I;jXXomNf;$QtwYA z>q@d~;J>EId*mLV1~~2j6P1m&3cz2x?k3t z5A6IDVbA$!reV-7dRZ}O^T41@2SF1&`u_itw?(`eT@gjR*;ZIC@WY3z*b$3;2t;jk zaGD#32`+eJQZyEcL~RVi+VluGFWoFrTVA=&Uxn;Ea&0R9r^v$7y|8?8puUJV8;h6G zXCrDW7Z>$(oqr&Q1&6@%{b4>KE#842#3*1(PWd<^Fz*ZJEbQYLqGY;v`zP4?Vv<15Fc(M1(x9HZ5h0>Bc3U0JjliC^Mr2Q06H!}DAzycyH16H{gj(MHBv-t02m8iqIHv{~Ma!Y<335n0}h$ns_^MA?UUun*x}SSO~W zw7eOS<;{pJZ$@N!Ga`uExMHqH@iGd=i78{sVDbq;8lOQj>xft_(YqqL%;U?lj*pLM zoxCiGPs;T#AThidpX-J<6AOLPK59+IYKzI`9O_}K|4jBGdBwa?NoskKSk<6NZr2TCS?7BK%`C+I3JKb zLrPPbN6y6AFONBLuAOB#xB0KZmC~z@a|1XxXj7f1$~MKh`P+iDWV$Q&kEiU2J!K*6 z(?Yle7Q&QndFmV_+{Qn_ZPKNPEjW{O$|4ze!y_2}#G@;5*-$6)F>Omss>lXd!rBIy zi$-jK-$Wp?0p5?{W6=)S05jf6FT~{|{Df7f%nk3^7E~440L#-OvH|`r2(1k;vz2+- z;cS>T{{1GRBI94UaC34Vw$C|vx~Y$hf60863v&nKUs~!$#=i_Z6=3dQ{L5O6@h^cf z{v|NRzXbUTW&C?DvR9$PL-0S%N9^PH>F>qzFQUt>F#g>a^Bo!gGP5IsHyHmC7~@|8 zWBf~CjDHD?@h^cf{v|NRzXZnkm!RlWD&`Kxzu#pW$lSsBmtkZ4OK^G>nL8N&vImY^ z#hr*S{v`r)m*!a0&876K$tkCdMJW88*hhQVELUS}K=wkzo9L6DTTZA9_WF5LYPU zU!ko~#=i_3<6qjK8{=PsYz5ua!}zxXB^l#i<}t>q8-(!$Z=}~F? zdpwZRqtf`7luD0EI5mAct%9VzYS=-(xcM&_h3+n9+k$w1WJ!e<6kyV z9f?HaU%BN_7nfhoW5G&~O5@*KSqPas8vha~Jt~cViIg6d#=kVeQhHPx|9%Syf;UF~ z5@fpJN{>q8-z@kO(WBD%SKcwAN2T$vYFlLd%QU4&rSUJbg=iyVl^&JGzjv~*$oQAj zru3*Z{^eXNJt~cVq8Um~SPrSUJ3 z(xcM&mq_VRY5YqB!5jPXTNE#&kaQ{wxak+T$s1FAE`@J`l}X;5;X#v5xFf+WnOOkq z!<%0LxHa>2fEU6Bf}fSLVH?6Sg4;9f>uX^jg4Go?JbkNb6gZvaotX=fr_HT;h-gjb zN}$1R)%hg6OVG|PMv-mGd7PiVd74FIcMhPf{e`KD~0_wxNNj646F>ECmE1)$jeH~z2iqqN_W(md%7!>}U z1xyeyIDCV7wid8e=(3)P0)~WFlWZFSL&HZ1CJ7i8en_%y1q=^AU;&c_j0jhfY&!uX z!+(;jUBIaDFHD&tV08Ej^Gp>mCVY@7+Y1=$l#fKFRC4Rof(%CSQY0m}$?_TxF&bh89A=Wom55{*W`2oDH+$~=LCc@uF0JR zvPM%W2ku}G4~3m6d=Fy_ekg z)bryo$D&V{l=b0(1YZ&GLd7AA4sw!b2-pw~WXhQWUJG|%X-fsX6;5KxSpwb;XR^|> z1-$13SBJP$xp>$Md9Gy?W}^fL3f~)H*J&KhA}(v<@RZ+&vh&G~R3#owVG}F5T*`LB zXV`=*1bAVADJuk|!c&-kr2trd{|?18u4dHrEi6SIvl9_e)yuU>eHQPFSoK!rqor;; zOi3N%@bsbaf6ikzdH;UZP)bPN=0jrS%$oBK29;FD2dh+suK+#{Zi;Y|)ASA=h+&g_ z97JEKZpR+@kS!i`kmD9=DPYH;adYMXj9HInoP_V*e)xheY{wdJ0cr+eQ64&P5`nUx z^nTc_a6Wg)LTEagCDonPdgS6G9Ji(HL6no|U-vqS9_X&c$8qxllrbvJdOwd`&0w3{ z(YY@I-U~QjFe%4K@-DZ*ru#l*2~qo5IoOgffg#Lb;eBQy%^A2}C$5STMBJ(H%pt=$Z#k~c z8<;iEd1SVcE)2)0P`Yq1vhNInu<}17UD!ylKw&~+Se8wV40t3QGvEnmzylj2bILM> z3DGIbjCWECad`tjku4?EDa#dDe3^NC7i$Ba%&`R5`FDWO8t^b%XbgBbSdo%w0tzVe zCga*kNi+lzMoDxXD-q?!xJriq4JFZ!key1R-SIzF#DyH7bO`l{90BJmPsPlB)=HwU zvJF~E#IR8k5f~*AdtjABL{t(r;{UfnCjE*jiJoGaT1muk*Gi&ikz$lY?*LFq#NtE_ z!Ou=zZkb1s1C&G@FQX)CO`u$EB8CAE!yi);aTysU(RV?il|(}PNlGI5)XZ=bF${PJ zvXPSLeKewLB@sLYK#ou~7*$y%5hJ@X;Mp4-t5p&asZGQlxTrEe4lti(~)pCRkcZhrURLJB;N+K@& zVuqWDVZd`DYBx%vs{o9W=zajBBzhjeD2Z5)Q4+DuT`P$;AdgWJ@l)FXl8CWZNpuaqXN{7G(`J=KoNKEjBC<*%BC8}~A>Ap7NNJTsL{>>e zWR*ljR!KwzB@tK5ttehbA?cJCuxJ;!!Hp?Cmok(i1UF|sC_}q5lp_SUWX5M9N61i) z5Zs!X2k=6Ma)dz35i*n`1h;3{*Vi)q$_`dnJb}XAs^BMKaA$`50NdOO$`OJ!nUjGA zyA_lp1a}F79HGo(o60=SPaU6vvhEPEGs0!weuyp;flVDBV9`oFK@ty@>xUpQYAU{2 zjG9US07YmmRbfnoz3v&UYD*dVn}6-O*5VuSSHR6_Z_~pCgc*L`rbh_KXDBvEj}%aqq1YfjNF`pFf>E4L3)yaVHt`I(%T9co}t(vJz2nr48;cN?F5X>P;8KH7ceSAu|ax@fYBL> z4boEujLA@JkltRvSSKf9gJA2_4jGIh#RkDPIX;~rHbJIfk^m3J97u1V*dUl%ByCQ_ z2Enw{z!0eWdq%z952Ga$kWL$&K2?%9egPjHBWn6<@1XRhm2A>yDkZ}!m z6;LnZ8tf*ZDB~LJE}&J$HJBlwO~y6YLx39BU{3)fWL$&21dNe!4fYl=!KvbA>;{Sr zfp6LO~_Wp;*QgW$^oPR>wl5S%FGUy`BNAUH`tM}}g9 z;A8P>y|_E?1;9E7sE)T4L(rQ5qzrFW}J?^YG(Ee{&=-mNMgo*mGb_ik0ecS5-~ zhkTn~x&UGh$&FT>cOLg{Rq5TT0v^GB>Gp0_fvhpM^Voc6(k$A1X9|eEGX+H7nX-%U zZE{~z+!~B*#2|Irs#3$PD!JA1ttumc;#*br0FG}}`8Mz-wyHFPZz^%-A4~@AHt5VB z0bh3Fdv5#tXbCkF`@Mk{o&JYDctScS3)QN1kV(u(^abmog{*PfZ$Jl^*KUf9+k$41 zU9)p%q8Fc~;-bv^=>W8VW{_S@?Q*u}8H@_{A5X?qX1!^+c5){(3K7Pg40R5X`hwwq z!=216$WC`MU%>y=09G3pD7W9d$Y#igjN;7^yE_5K9_cQPC= z<4%TJf=GSA@J8y3te8QX{l`~=Lc5a@;!koX6O(Xj^@Z{{a#eW=O6ppDK_M#K$&3Jj zbtl8fZrsTn2q~C#Cqrc2$q;qtPKFc_cQQ2k>6tqj)@R+x&>f+5 zC$j*^x|1QLGK1v)W7-T^cQRZE)}0LJ*}9V{qPNza4Et`~$((~ytUDRj!2QS9au%XJ zE;A6R-O1R=-Gn=t*yL*UMdVH*q4w0on?xzqT zIt%t)o(5WnQ5j)8+oO#x*bor&Df1;z7@sl(-T9P}`wn$+4Q4$SY<H6cj9ZYW&8^frjC+9wyOmmp zK?EH})?=Hp9_OboABD2+5TX369)jqs$9HyLKEjpN>Zja-VGUE=KZXMf5y}gh;k4t^gJ>B%h%Q4()hsS59Ueq!npms?fm8e(X+1D2g4Kxx3TQw1muSay2> zW1W1Y0i%*4(tz=OW;9>~o>R?H7Q6jKFBX2#f}dz-Yh-j0TKgf>V73d#E*F>{LF|fc=y` z)EY3-8VwkM(SQ+PJ%0tnVmJ#87&GQ04cLt^EG*X=uv-y!GFk&hU^HOA1TY#f0;2(A z`9=dqU^HL^Mg#T)@)!*mQ;Y_T^%xBpQ;Y_T;DvIn0V6OPFao0iBQP2;0;2&Vc+aW+ zCHk9Um8lYg6RHE9#(UquxBB=z356n64zo^4Jk4o*mWkWs z-$i0R{U#{#h14VvWZD7pwb_@@SSK@!pib0eo|FGNP?)bz9Yea$F{z=PVJGtfL1VzT zo|kzWMdzC&Qwlw(0)?0IuKfl6dEWhaZ?-%Da^E9$`GFEJ z=a;mcg_IO6bnZl;*{Qw}{~B9vgROW~E2A3w-i~m!ylwNxA=7Le?0R_x8bsg9l|PqF zDNg3RfdIcy+hj5qfvoZ#0jbQb!vXFU5N7Cqx$-^%`SL}FEO9D-DWEE|543ER_sg&s zGQkS~zY&sy=fpo4;lSyCIbL0`R%LVztbj2iauDMm!AC!GkbL?glr(rY6o` zck0N;KsFa-O;tkbjvS5?(2?MbdIc#*BW2`=2%L<-R7HZ)KvQx8hN`CEv@at`BLXaC zwvea-M*bL)i5kZ_d!u~A;jH@%lyN}GxyZT!R2L!ZDn;cd?)d#*wgZVf)*1O&tx8)H zrQM^`Mmr-*Fc!@Bbd+|#P8;WpoQkv+NXuaGRR5({>rZ9XC$MTiF#x?9?#|+1JELYJ zgLGs*0_?~j$*DRrY#AbdfXJQ{#Rt_NFp2V9g>F3;)bCg$Z<>qT zESvNJF>i7AV%4NUYZ0;F5Zo2ta&vrg?~I5xoN$lbtt|Tpz+ro$0v63-ex(G=osXZQVvk1EF?bmu%jGzmRltCwTNgtWYHqWovnKEEF#7qbu1nS zUvb@~D0vhwkFe6L$G66WQ*VWZ3Vz-Xb6an-8hZxttJ>D}CzRp?jX!^M*@Qu8AAkAQ zaKaG8@#jw}n?S!-{8cxkCzRod&R^vV?u4I#mcPnp+^t{5Q=dO?a-wqU$1!^R!G7JJ zum>pk%eREiF_Yvfvk9+=zpeof9YHJ(A=d! zO;O@&4DZ!vIm0~pOpErky~e z<^5U6`wvAK)hsCWSJdzj0y2V-_uqxE$osR9_cI|i2bXsv3M0pVj&zjwXCd!ra_V+m zny~1lBtw@*jL7@5koPlL$@_DIQ^%L#2BSDO7nk?v;`07nT;89H%lmV2d4Dc0@6W~M z{kgcjKNpwx=i>7ITwLCti_80Sae03(F7MC9<^8$1ygwJ0_vhmB{#;z%pNq@;bL}E& zQu6*>T;89H%lmU5llN2Fy(xJ=M>*Q@LRus5r-1waguI`}$VEF|*eN6Lrx?4(^8O1z z9PM~vMkDY4Mb66m??>3k`w5J^|49HN?r~IizXmOgXH-K>7@rm4 zz7fgq32EGCDw1adj7WYCfDy^}N6U>!ei2f-63H`%45SvxlTNS}$)6G7z-gtx%3UDB z#h>Um^j^q7KLpMEY9#|bi(*-K1Rho+Q2GEg_eErA z`yxwzTN>DoEF&i(ks{MClUxf=d=mqNsIb zU6&>C&in?ZKI{E0l3R12)t$^K=p?rukBF>CHAU-%Z0JatUdj|h7qEk!Q`0-L$m!h+ zT~O0Ist>1kIk8OG=+rXQ`XaDQ_n0*6ns#3_-DA^i#Yw=Nun96AHv*{j zp*A&Odx#W0_e%`eJghY%sxMh8Lvc2)GGIgVn3&y6wt1onnZRr}bdgPT1svy*%^y!q zobU_G+2}}QTh)+uz6(Ceb7mcGgswlp7+tX5aVA5sy#&;UjI=^mFS!mwmQWsL6Uw8k z7kQK&0^)@7D4S3oWfSVqrbJ0{6{NQb&)*66Q$jhDO(T!{qF@!#}N!1W1c3q55z z?Q7HNV-V+S)9L=`aTXq;wdu4!6!qeGfLcTt)9G&kM5faW{~M;$^y5s^=}GvXD#PUm z_(``=Ut~Hx9OL*|n@%rb8?@;(!^U))z?e?62iA0&h^Es%{?iq$^ec9B6K)n`I?Zs` zrqlEnZ%n8E1VGbi@oc*efInSs)_WcRrqdiRV>(@q35-mq8UC2*G#8UGon8(KZ8|N) zpJX~c6Pb-{mB7eWd5}TZrqgd=B|^5^2US_qX-0NqI?YpMtm!n7HJv8v&UE?HLZpE5T^B^Z{I!#I|TYVmB)^wT+!J1BUo~`M0 z61}yi)9kx7o#v@6)^wUR&~*Bn7-VBQJsy$TblOhtCQPSelY3V>Ho0rdW0Sj)>9kC4 zWID}-Z#=&oirS6oG~K2e*(%-18q?{=0F3E0>oKO&Y;)J9(>&0~m`=X}U`(f3K-Z?z zr(v<0lQ>79p~iHYPtuJ%zsO0M9Md}Xua5ny6WAZL7-ssM$6MfbBvvz=^*Gj&i*90L zxdiH5bCA@R5#YQ@elE)5Sj5Q@6&a-RxGUk#IYgEQxz{2>UJC5HJPp9?@xK0NgmDK& zrqgl|hdGY39gE1AP7`!zIxY7d>f#!NeGm$^rqdU)kl8*efg4!@YdTG2O{eD~$sWfE z3k3)6Ul@5M$aKT4>GUfsHgf+WFPd&lrGknT*UNoh@|iLB`~ku{wrvZm8SFrDVIxemq4D46q`7?brlI`w=I$*d!S zr^{tM9;ub}_{OZ~GbCCkJj*HT@vyk8#|?rFk>N5Q?hV7RMtK~kfZ3>&&Q}CPhRa;y zJ`IH8+rjE#R0L3ynozLxyc-T@i=I&N>;C+=!No6`_nVgPU zCZ}VT$?2G7a_MC?WQW8uxl~IkSul^_l!4Kf$)%U~xe-yY<>e~RKvG#(ibst|DnF%V zvPaA03?!9wvRKXHqS7I$T+Y(BtYxxC%j66sl|xW=H7khfgQW6#)+dt6;{5gCC^o|~ z*`sB029nASmdk=t199;nW0Vnur1EXx23jU(AgN?R>f4AJ5>aG?4wjrXh-sjtG6P8^ zlT&YkZtsuLO(q>JlQWQ1GP#)>K$7bs*veRq_o?+%=Bwi8}@CF;AQM18!J=(8+5|FDHi zn8ptq??;gNmps`AAJb?+}PSR!(JDf2=Ux zNe#gTy>rqmQ-7@R1sZ*0-5N5KNd7Lmykl*AfX6z8^i#}7vV%Ve4 z6lQiZ-(elwr3t*uu}H=VvjnNk6|7^5fG{)N1DGlxpYaK{7f_X{B-u0p#sq`~)JG;D z1VtPGfwEIu>=ZNhE9RiG+f&R`zZ$S8al&j5PBByEZssXwQVHgo%g8vW?vkM_Jmp1XB|}j?>WVcy--Kg z-5H%bsF35k=Y)X7>TY7YZZg6f-`-N*wE;aucVRskSXe_q;i7 zCEq{RZO4D?6f-tr%b#M#QTTMHn6W)r4O`+AvjWT77K~!8xuE3j5usd021jIhCwL{` zo!s4WgOJczKsfkLuutA;{~qo*x8wWJfHuK}`Yl;L1O5eeuL-j3pQevM+56uQbjV`I zy;b0SgmaGse|lS****X+9*w-K<zQ|{W53&7at(V4a790;5qhG1XT;5p5=l74ORC+KwI z{L@csX(9fF+j{g-7>qq#cNK=S{|mT)b#)#^K}B%%zw)O5C4P%x?tgGOln+4sdSKeq zB}}W4wB<-+zD!1?ZIFC}B<&uZHc+SiRnjI&T4{yKx4lmLXM$z!E@=~W+H9l^Kz#{U zGR|S*zz5OLbQYT)kk}@M?rqT8oQd$vl5=o90G|!cpg)3&yE;k1H0pJnfuqo%uR?A6 zJDqX@Q~VR0Gn{5*PoCk7Y(0U&14_MCW+id5L1%#MI8Aac5@n;vKW?J*g?!N>#)AI`4;_>SlT@@4ytMj!QKUY_#BP_)oe{+=WsS+XX0USqNGH1pN-jFrAxg?=iwO0YS?P6PGO7K zTZzTfW(LYhEyAk48(HM7mUMp}@nra_4)Kw) zOdcu2e#xxoq~sPHKAPZAH?dNeacDVLFNH}Wgc&|(d-#NNv8q09lR;V z)FA3u++$;k2&`maFakekUfvpcg09GRM1R6&V%4Z>#e-k;QA0lO60JmezBY>A6ZOl3Z9%A4{1cHYVcng7j z5ZHz{eDF_Rub9N_JL4IG#g1@i_JckZ@K-G({bFKxpT+ zD-amD0)de$5JYkXil}+;1sVHP5|{7cCp$i3a)m)yl9612nT=e5z{nK{j9h`h$Q1~T zT!FyI6$p%6fxyTW2;y>ug=~XXe==;;p9H5zr=zn6j$83##CiLa5=H9IQxPToipdq$ zA};bA#jsI-vT`q@ zN+l?Y0%RjsSPBX)R}f--@P*K7xdOvRt`O6ZU8yu=(ZLr~)Ec=0^BB1TzjAQ!1+`iB z;0s2YgD*&Kk3-;X}eDNogVh_Gx4Ltbb91OBK_+lg?^}!c*a_>m87m-|nVLiEPWInafNUJ}i zgD+x}d$;5_as`>(NUp#ybR$>b>(i(|sq{1I&mRF8_2;hu%)u9|#~ggYHk*Sl*ia)^ zcnEonT;W*&BUfMnMy|j-My}9F{W%y7HF5>&ql{dEc_3H#HvVx;YuUeA_N!JPlX(vz zsYJ^a7=~mPSIKo&=Uf7Hu9-qfwQ%8F6vJVNmCvYJO-WgNfnko0r9nNnAVM^q?6y1z zwC3~82xD^DXs^{3<(ZW$jK%sfas>h_S723Et{}G@>f-V%^H{Jw_+l9gi8P-C_TUR5 zd+^0vBw4uv-|brSc?rmL!>wH5Sr!{2T0_Oi|-(@#of=H?zEEr97F;7i4E8> z--0ij)NU=@@~gT`&i<@gV?^w;%(w4)TP?n zF717W?OlfUE(W2rX{xlB@%?T@F>LRI&S`H+doMyFOWy@Q-CojvyuDLD*4|~HllHd# zd@4Q)@C%MkwvE0RpAz^b2L*%T`Y~rQM#OUtUu0O+Q#Ffv8OCRCv~S-jy)0@ki`vVg zf}>gFcq?LD%t{IOvZ#)SGv4_q>t#_n3cW09FN^9{^s=ZP&UpX7#G*b<_U~`PqDH)t z+i^75r$%7`Yx^*q_#Ie293k9Sb{n)3L9taYXgm=3WlGVUX8gbeE+O0X*!I5jd=|n) zNI}=366=_LJos+U87oxcn115l)cHbhfH|ASVs`kqZInE!tF#O3KxlP|xJl#b{1qdl836ErJLajZQDdQN;sm8C-x~rx)X>;k{+rS~0&P9fy^-Ru0`&~E&J+TPGfx=fOAog?0^!AmXAY+-f2xGh>FXbu@ z9Lr2Nxm03RnkNqD=i#FTM;3GHo&2!`*ZF7)Ml7-jW47`xEy89Y#rF=zHCTw8kww^^ zh^QEc&%c51O$Tn!nEyGU!DO|ig(gdehujN?nRmvVXZuO552gxlFrYboN z|L;VU^sC9Khu zuBZ^=O2rm)G`z|Kk9Xh{h~ZRz_B6z-Qbt4h6h88CWHBv>vXuwUndf*{l{d5A{QDe& zt0hk%FQ?jGQ!x;otas8gK+xwwgykS7Miy#51obJ(Udt&A`K6yCsadl#$v#uScW%f9VaZa}^X zg*}Mi9FE&cCKVoFzDpHldm)nCeuT7X1uhD2g zVQO-cWr!f?~YIIJ!*3Em$HfXmvZ43^ZLl*i%@%O{!5o2(Dj~`JTvmzB5V!jZtwh2Y{5(6VQA>S`4WPcvwVim z%zwa>{nlbTmcwnKJI;w<13W6b*2=kDOU*PWu$xnL3TY> zCZoh+7Ny-o8s_4NSQ?~kK!iN~*;TpuOB8O7FkUzmol#oLb==47Q<)Enf;_qhyX6E< z;XCZ;R%$VOg}az-h+16m*Wq!=`5p`IvoA_2;5eAnY8DbnYYCjfSFy3#+tIBc3JOQu z0ko4_Ay#0842N}Rw^dnzB^mi^km-i^xejxf_YQDV6}S%yk+fFcD}`Ozwu7R!MbcWP zr3&Y=rE}dXW`oBPkFkAzg}P>Vhq|e|Sy<%apHqdW3)=x{E$7!OT+HkX6bcK+fxK zO;50CH9e;s41dJz#ntr8Y}E7wMomv()bs>KO;2Fd^aMstPhiya1V&9yu*GGd>{n0J z^sIby)by&{%~aD%B~H)O^g^rE^bBvV43v2`LrqU|tES%p&pWH8C$egKBCDonzV6iY z(gdTXC$eh#AL4Oo)$}(3SvCDVKvqr9d{#|Q)SV3U0pzo4`iFtKQ`0|(w4SNy1N7Fa z>DhOyrhgr!d^$Bfdl9MW8QxqqJ@fQH209P#3ZtgK7{I9Me+FRG^xWXq12sJ>HEMbu zaAefa3$)Gof|$jEL##mjhbudaXd6mDUS&j41OK z;3^7x4oHk#6!x0@JEUQl<78=&`z}O?!kz;l8x6I>{vQ#>G)F8T_vBfH{dQPMMqy82 z751#kD(vOvLtR{mWgZK*3i}IKNW=mXScN@N4;1#RK&BgR74|Q)*oXz}tgu&Yi&((U z3VUYzxWfJt+$8_D!k&d#g*_Xw#T52jHrJwf83m)TXH1#L(do;lQKYc{nMCh`Xr-|4 z%Lj>UV@JeGlK6YMz6la@#u7j4>xYrk#a3kj5jQ9x;s&`;8XCbC153G(GiwDuijr%#w|@IOtbMc>CyIs}@C z+ZqN|JJg~z)hR7nBk)2kS|dn>TC_$GhFY{nkPo$Jji4&jqBVj-827gwcH?h*G21{n zmN%o6VJCbF7l_sfj87Q$z%j>Z5_ztZF2(;dK_>l*`GkSDB|VP&S1{~^TC~Pyd7&1q zVVei~rA2G>`a+*DEH3>AT=>)FX1(VC;1h=9WqiWq(dJN#));m|En1UGxS1bu#wQGo z=(JB5A@0s6OsGX`2eH6Vi`EE?PnZpCM5sk;YMixb?RDJ9^^RYIs;p5YBaKlc$t}0l zj)#TiwumgZMbsU)wKtZVHHwrbbi-}&ab~%#8-Oggbr(?2xGmOajUws7!E#&l5M#M5 zQd*=uD8+JHtbsmZzJWnDK4B=!(>`JBD}&7FP1L}#QwhCI_kEn0g4!1#n=0ncfEm|9n zhVC0`(HftjGea#}V;*o@9i&FVwd`Ll`&BDYR%%wbEzM~8d}C%kjkz$ND-8iFhmm%VQB)9&0|5tWo4CKzS$4$nSzoH{9}A zFR<8%$C7u9F^c3ccr_7^#WZUa$!v57!&qw+c_D5M!((yUtWhNA+8Ra5+p{JTvk_UN zNEXr^k3~vr6iH-_B8jX~B#||WB%1D|xngLSEu&!E!7v8rCZk7nd-hMH)(Q0hSx-cE9$n)Yqewp2jZvh4h{qBT@mO;AK1v>|CB=b?m?F1h3HYW4 z@>%1nxrFC}v1-6xq6q<~V<}K0*sO^Kl3fkd1bN#wQwsLv{#j}->(LZK3c^LBq%k}#5D{W{;={Zlh&J>bngX~PP;yEz+H6mM2a z-s~U98acvXG5^sGE3B|r61IsAE4`91=;Xv^c+(qJWaZXGYERnBTi%Sw@@7Qc@n-xS z>ltsx$DrlSHnm}eE$f*i?0?UO6}fFi%z0;$;Z#N#?;dYhVV)jH!nW*&6;^5_VGm)Z zjU5bF#HJ{R``I4Z&)G5%@grvo#kJf z*s#K?to%!EIkfk`al?vgxaG|@v0+8EE#l2O%fJ3(8&=qeEhhgm8&)_9M*g)~8&=pJ z%+MCuu<~s%LqUIGx*~qa?N~tG3_H&U)^I`JM%D~F$J??*Pmwii2J1wkCU-xcJlG@$ z5blrX>I4+WU(gyjXF_M`IeVRKBx6?~fqWTr&p{Vv@6iLsD{+Y1heOo^cggZwWbXR-|P9FtJ+{DVeYQCkK?0`4{%#uqHkK>IBUmL`vo>|H&dH^RKOBy!sY; z5dmSYDJAn)i9klAWd2q1R8>+k|2qF>5Nauze|>`4w3IBUsWnovWOMBZFy8pa!_`X3 zf|kA%o+&9=FebGUK%`{BxJrgaN*0Wl3O$jM1>-a9gp!g41$(3kl$0#k ztCT&^QnFwlL6nl!AoiOelYT`~vS7ayl>2%d_pe}BNy&nlauX;iS#Uu538W|~Sum?e zV<$?)FX1&(|ASL5?DJfZSVyYhBMLZoDYK9x=c zDZw=r|G>8nq+~QMQc|+u%WjI1A|(r8fX3ybq+|gM(C8pkabiGKM2ZswY9vyeSO5bw z=2JS!00wCM4pf|200T6p6+}uFz$F=x(n$tzNyaZv#fb$lK;uR|B_#`BfJXV2l9B~5 zKx00|i3Kn~BT_oa00wBRPf5uF7@+Y}RY}PL7@*ObL`lg47@(0-Ny!3i9j1IsNy!2j zpm8B6DOmsmG|sbxpB|Q!P@xb-mOMfP3}Evaz#oO++WItucTzb0}YE% zd#gyvg5NZB04OP0@KD)W03{_09!@_EprmBMqf(EOk_C@Ro0XI-cw8!N7b#irWchmJ zQBtztsq(h~l$0!3Cj}@eS@5jnQBtyCeJO=dN=g>I6jDg9q-4R%S<1kalq`5fo&%7Q zT?=ZCX)V`jE&Ej~kShSgObK8lC1W`2ajYd51zfRQ0(CArY0G*ikdjikwVf#$6-hr< zk%qZAI<_?Az7G*16=S#ML7=5%c%?@VQsKk`7^8iJ#w#gV(B`HnX%Q(|0An-)B_#`B zjK-=IClQ~V#pRdvSg?|k1u#atl!Z`A7QksTfs&F1Fh(O%QnCQXXmgRIq+|h% z(X^C|k=KDtH(YUI0gTb;@mHi|!E9H(V?;_8z!*)njht8jmt=hZC@EP0V>D)?l#H=T zN*2Hv?F!r)A|(qBS9gYzk_9kE<6J8#SpZ`+BDHlmfH4}8l9B~5Mq?pLN*2Hvjg3&8 zSO8-*QYtA~0An;FB_#`Bj7FrSWC4uPh?JBpfH4{oq-0z%+z~9JV5DS>$$A`}IzEGB z))B!kysWn;qO%@fmUVo5MC*ihu36#7vfeu&5h+>lklW1Xx=6_aXd(r0`37*BEPzt7 zU|gcW)g3&(5<|LY^-^@PKK~Au*MJm>BWB6%*a!Sn!@-N;eJ5ANlz);hTf7K@v0Q(y z?-L&bXLjQTya~(YK?J_656W??WZ0fSYEh0h9^oDg2CU!Q`Hnj-#X;ERaagS7v4^0k zne=_iSko*-HVq^$RL%rG2e{wd5sq67ndfGK5a0C^_)CFMlQs){THt8M?Jw|kz?QjV z9Jfti%iOV!J6H$DIqnb%w$4E%b4d zQI_PIjzc)nc07Wzi+Ruy*yLPNUe0KU`b7SB-l>KS9fMBM5^gE#Y6d~eK9&vDUTr5J z+S871mGc^JBOkXyp*-n&%9F0AJn4GMldh*c>7tM)uv$FrLRaf)rM+5DE8&=)R%C&{ zL;aESnq3(_77Gb_TE;u6gK&8cKRKDF3#YieON=b=M+kdPqLWkHgx1sYagfk@+Krsz zCN{?@t~?ter?>>4Y!$Z(qeAC3Q}I7V4>`0Ol@7(M;>KdiBj+`$Q*k|QaVaWo`P1cYrc+$01VtT$%8c`x^U%XCoZ<>?S5|TJk=Z!KCFt5IF7q3! zxKDP9OLD8H?YUE2=Cf9DbV1fLSzynd;S_P?IK^e3y0nUmP3~QyQtR3& zF7q2%;D5>~E-N*%z&~K*jV!Qxr?|{xtm0^D)&r-w%mWVeO8n#eZtN77$-IY)U57Nzdip#33EKvMVqplQq znlg_CTRrVXh%=xICnRP9Dj%QUN} zWj5NvG1ls7FH0eNv>k%8X!W#oLuB=|MAmr?k=4_(knZ%fq_lckBCDq*vU*w~tEVM` z^BS(6>ruQ+myrcBrp)8$)Y0{otUN@lmgrp(UFPv+S@$O<>UFXuoZ{9G0b>*l6vMoT zH*z~fN83!=+FtLSe%o4i$(-N+jV|YB0n!t(n6Es(NwWY#%ZGXC9yuPIwukV5J zs=#ENy02xtdbc3pptK%&3Y1%P^O&t~VYz(VQ=rlp^lm}GgW!O44?G2Oyqa+HZI-7% znJr|ZxX&MKw^b;?)|(eb$}=?d0|< zUb)|t#w*5CAP47@w;=Q?UgeCmPw$3>Pq6q21igw^?=w@p#ythT4#p_Cw`@X)cq6xC zA=szJ#Y+}BZmOD!*W<`y{TQqh6Nd7kDjSLy7z)_enV)3LiG+ z48w=Lt@$vPF%C=Oxcw|2)++$R+m${*dIezkzS?4^Lh&=NR{+*40OLov<;nO3Yd0!T zDrz?>P|#^NDo_GpH!4srVK*wgiBjxF1=c|C%~Y@$@6FpHQhRUigLs7DPD86;yE2BG z4;tgWnV?qy)++$(6@bwn2w8P&3`arM{~ZCC=E?X7Y0%sg!x5k4cB~^$w(Gl)eFc5_ zFkeZYOn9_pABw?#3tSXmAZgJm{{y&RGoDXwX__Uq!m6nGez09E=t}(H2$?=UntzYD z4Zv%3+zCk8KXE=7yVmEC^!Io)GQdN!Bs%?L{yzrna62}r;unm9P0l-b&heLQN{bf~ z&-vm~!vP+ME>H#f2Fl(W6Z+Gc-~j($oeNs#)ne&t$8}kTyE-X!Tg2mBFkHnfFY*gF z5)o$e>J0$Vi5?7#SzhE9E|SyHqmfaH5*Sw@1kvWzn~|Mzy1nr~)gPC8@ROr~Kof0V z&2= zfila3UpV$ao8`eT98shc?EsndD>BRT_DlVdWr~xg{VNzYCwj1QqZEAsDMl&!F90e< zSzL;iZ~WS#sN>R#| ztx{B)U^cH3Syv%FSBf&9Rf-Z>S0SvgXG&30cE=NPAy}S}^ZaReLe@Z@@EXoSGP%)-9z2=LoanJRCxw=4zi?bcX7eiB zY&NfQ=r^GhE!TeGSb#avgL%4EicUvE&50g-!y7pr^Jt|gJ5bC1)v{l;9O7CgW0*Oz zqBs?$k);u+X^NoV_*_s+$s zEvy2ah$5{DbRVD|p9?B)6r%!FZHu-;Fzw?iP{wwn0_7zA`zla2VvBKreDjJ5^k9^# zjqu96ja8tWbxe3%19oWmu_40DODSCN1JZPzFrH|iUUe2w!1z)1p5ebb;tRoUGm|kA4mzV41 z<=l!*nX~osa`f)YuY!-6v;7a_FJfnta@XlqzZ zE^erBaeE=P30&N8;o>eK0v9(zxVQ(2z{QOeF0TL6_%3yJ#3lvLdHJh`G3)c5+U|Nf z7&Gb+=FI7=W=%ZVhib9z_Ze{Ot59tAK7&VBqTCI2%$(q!1MGS|j$!UOz^+#b$9BC2 z-1Yhl2xQLzcDcx74oIs#&<$UO(x^~w)F@jnvndd<)`9Cp3JEjETi_8ef> zE3@HX2ktq*uGdq5WX}P1y^co#WgdlWR^^IauiT2D4$Q@_*K1h`#X{Ki$}n^{M>x^0 zR}rs8yIwQ&4HxZt&CoYowCgnw-*DLV$}b~|*LK7I6c6iNgP%5)Rc3J5^*RM}DdM$g z*J~!e>s9s~M7v%y+;b4^dX+r~(XQ7FeZxh&UNiI!7wvk@&^KJP>ov0@Q=(n33O|PzwYUt>Dd=%g<+-{2ADyRMK+lML?i)0FbeKU0xl>TMPuA1 z>@Jvu_*aPwAdsN(XEZKB#h((9;EzQVOx)rU|KD$&{l3?)yJvbfxbyk+n_K6e?VeMo zPF0<%I?n5r-|oC#e}`I}*DG6~dhJFGvO02w*Xwp9%H-bRO|Ez3YP??6tT*CMZ7fYQm+}W*CJ!X z!RwX!Eah_muUEP}DfJq>UP(ihdd+#g(q)Td+Cx0;;dk{2$Zy9mQ}bqg4*1*>bF51& zMO~R!Nudi@BNhV^>ov?+xfyAYSEIj>hj&g+$sV$$gKN(ep&#F&3X^)d?9=YT0KF-NDDG)QJ0 z3I8I=&qs1g%+0cw(=X40OR#4fbn`IcGqjK*K06N{Zw-m z7K;CY;hA!~c=N%49I>|b5uZN_W@~QWKV#>c)kgRmfCn$8BSHtWZu~wpXfHb-PO|gm z1U7f}(916dFhD(VJV*!DF&Tpsn2|ShjrDR!ay!espKEN10A~%JcL;z@1TI0w;j6*J zwWEgrf%a{Xp0mBpe0L?@Me|0{?sdp8egf(lDvqoIJW62xMm$}Ce<;}!lk+hitHK2- zk5xVzk5xXSgsAvN-ex(;%fU(Vxb`tLvJ4qo{?u`jnd3y}IB`O93GmPy$nx19$P!Q- zBMxL6v4owMDj{-=l;z%lY_jkS$A|;jdswGFkma*IkmcTB4`egP36Q=lVjVB)V#qLO zq{l#F&Pb1@e$GgbCxqk}--?~W8tJV>qBhbiA|21Qjr2UP7#%02U2b8!XO`y`<8zGh zeJUKGIglmd+XGqp;@P_!t^r{0ZukcP_U;D8WSj2Y4PQqY>!q4StdkoYp2C<2!NKCm zBGx%CRjv$oL`x?b=cP)>d8ra|UaEhI^)-=~Dsws`Jwnb)m5}pNCFIn4gupQ#SP|QX<3XjaP^qBhvAkBC?PuO@hjlq{jGXPoC`QiqFE4VO zZRU#N>qWukQpKnAqPUKhp6M>u7+Y7d3ZgP%nz>Xm3JQ zSuB=#M+ZF+s&l!|`dBO{1zav67nhmPL~)sE_3X?JiJU4LU>rmPj1dixcm24y%#2X) zj;eXLm^-RwE$*nAkTW}Ed(P~Tmjk&wGZ@(3-I>9h&g_tPi%rcHr2}8l-me?@|5NI3w$hO_~A;%i8G zNi8i=ok=2Zxw0mS1e{4Cn{pI+@2x3jWtPBeKRJBeCJFOS&SM|raF_vTd+v>I4TP(nTX$|T<7>*LXO`h z+p;&531CbT1u!OwMAm_~fJMqLN{HBoOVT%#9o|Qw^*dn3Br40M9)|b)1wpWO zn?<_ncu*Z%ZxQzs-dA=Z_~bZx!CzVy?46ng`yf~_DoOwIB^e7g+`}_y1a`--JDSc| zuoIHkfR-CYBcH9Jk$_b+ilK3?;}b}O=LaF<`H_Xgvz{NBH*m;;W!}Ib-%YxAZ?R#b=NE66X)ceF;e30eP};c$Z=vvT%6B74m@Tmbj8k@iaI?*rEft>jM$t6rtEzlEz}U9~gqtlj4c5(;yUT7fTNJY0 zsji6J-4}9q!|fM@GJRK!+b=SG*En(Fd$Tfq7sf%WjYR*I>AU_9v~VZJxCbNCcMVTR z-}MyPt|g-HGF%e$U2?C*CQ*3dUW>uUahSVV^j$l^XboO~vCfSPy)0wQGR7=p%#=me^>Xf` zEVA^qWYyvnUx0;U;}jFHaf)Y-F=OmE$Cwdv2a$yKoH3hv{1bARQ#**vE`|7V6AjR< zxgD*it-0O%0N8`bI{;)_u!zIpjuw0T<42mk%kd+1gf0)XB=;gg*e{8QLifMyQi$~N zV|FQouwynN3VE|W|M;=bKYr}@W8!@ZOj6?+!kQUADYxsLV5L-?;)1Bfk{_xA$R=UO zHUk>`4VWrsE60D#jqkz(qZZ@d*dc_ms}j8U4m88R#xs-XXTqrMdXHt)zJwQK)L7MX zf#6qNmN9A>qn0sh8KZ`C0%tK61~U zWYUGMdn2Ii_AYHFc7PpM`iz?9o@ifT_@vyf2gsx$jO$*Ni$=B~ z?Z+CH$i;Q9LiMA5u;TfCu;Po5H;(RpujTm4zf&CF$*8D=qRA^WjxXc*GLA3f_%e=f zD`=%3J0%U;O+q9_+ACZDE~@Pvl-rq25RKl zhC~&24|p<~qzy}+{{W;Sr;G?k_q-p`e)|K$Zk_u+%WnO-X1DHve<%OVd9`D=vS1@w zu#qg-2)2-Fr=MOtikl1BEv=p#<~?B4oEs)pbIuKue)-M~GrOe~!(mT9vtT1p50x!F z3=d{lIBMqP^pm60!`LB`2dAI6BSC_T&@EH8Je+<jX38^uDvYSh&%mc ztay9+Nkr*?fGpNBxtaCFP(Q80c;$Az3oO$B!iWrY^Ip~~z(x&R2qsHB1-=Ss?j1Bo z8)@U)Sr0?0_EHpOA%?#w%dHM)mgNL=M>O;X{SFDd2`n1^_g_R2|MK&a=#9dhZT^5| z&i+d?XS+}eWHeg)+Kf392hE11n7fQQ%b2r_Ig8?JbK)>Dk!c#qzKfBOF=t>u#p7_W>uvyn001vH8#h>XE^E;7asX{m}aWvYve z!60rnGDgOn4GTYJOw%fvvxmr>y+)Wb!w=N2IsvwF`;lgS>`T~xeMHk)sb1D zVRd9yXkZc#mNUsyz!>G1i}Ka*MmlK5&}?G!^<=*oG-Fs_xy9(b>OAr;s>*N~*QlIM zJ`MPTU{8gVJg+)K^}I7&V& zw_^}zmPd&x|0rIS!FU}lrv~{qM9Cj}uaBZ-xV$QkUU8k}y}F@Aqtfg5sQ(36Vc-7? z$9rX#VcFqhcKC<|v%f6Ejtb&p5OQ%b2u&0hgSzgi1?c~Ka9A!t|EB_e>pnnJ3((K@ zoTBS1DCaE07+8BE%dj8eoeR)^4}?Q?acO*GuHy}W)WxN|hANM*bpiVM?Jht+qjS3e z{p`yDb`2GSkK4n?_X4nSF+K;tT88~Q02>{a*In5F{k++xdVv1#p^S|V`#1m_9hMbT z575t>3)RJ?@uSU)pog#l`Vmn{UtH?=Ee5IJn0kkU0+JoWvC5fv)ysr>b(KvQ6A)w@ zzau(0_vh<)q0uG5?{>hJci_ec-eg$u@5m1i*lS?9+bWt31Sn*0q||a{>Q*r z!_{rXHUpDvfPMlK1?ZQ>hqj1_Eio&00s7y~N=$%$0xm#5As3+kJiKy_mvotf<0TVs zLN?uTb%iMd^gqsOO@RKXA49TOgv8hqJ}NJHOGr!n6tdU= z{XA^60r~~-k0JX_gbX6ez~elI+$hJ8XGC@5NP>;nUqNv-7tGhr(Node^;ltpatL|W z@Vfv%pKv=5CC~2qAacG2aCs*RUk_kNS%|3^89Nvw1FN1ayU7Z zV*)v{ozgDb9O`G)iES59unJZW)Wfu(ah2QOv&BVx7oW8@vVlJNXlESrC% zE*b?#xS)-T=qN%jC)h#oDuDAZyY!+6H>oo7f~#3@CC2v94lJJNBR5!%@e6qKpHSQF z?2N|WhzwV~2^^!k%^ufT{eKv$dit8y)irz#&vkW;H(}iC;)Y{Dkm};b@1jUu(y)b4 z()cYvaolj>C71Et4*e z@|H$c6BRBeaBIVrco9bpPhoZ%K3>ma9dX0A@h;!pb3F1jJcz0rhkO1PZyMvc4p+io z!jiPc%g^ikFC=%Z#d9gYI=K{Y3%pM>zqXUl(QMpUm0u?f#s%J3m0wq6>q%h=#xB3E zi$HUsl?b`6k3jou+*p-gU%VW}yU^fl{9pWkXyi?JkPkxo>1b~R3o^m~g$;O--&A-Z z3P*(xv5n0F#0A!o9~U4gT+cR+5TLoR4PTqzB0zhgfxwXhbQL<8ZL0vK!gu-RC;|El zNAu0m0+gfVji@`xN*MSy*+>q zy3aavn;}KIf%T{`wBdJR4Vc=5J6lJNukhM)@1%IVrqgD=N830);jg5{}u; z0<_NN)t&iUX8jXtY%lyCpPv7)lqnUy^$q|Z?f4gbWPeouG&0QjH#|R`e|0WlVyXLo zk>T|@$sUy!pfC9=bHx&c?{?*ix8mK_5|JW*L#~sEu&u;t&4VH4JReuOku88B{vKL*pmYVH536x`q*P)# zMDV>GwLDh(0?U0=weTb+_X51_;`KxqLDc=;!GMVaz{qb)qvM5h*vN%rON8s^R z($JlSKX4?U5IXRpsP`2}A=b<2@zkEn?)cheTbjDSfO=Xx|_w8C^SpZ7Ll(pX2o;PKux9m)?9Kv zDxse@!+M^;9FGnHW@j16*7TWV* zg70LtWPqT0-a&RY`y8L6*Bzbz-E{$S%E9Z+#$)4QD{W>IV1xlJ2KTs_zOHY z#&eO}7;}FdAjL4q@elIyI{E!4WSKjcpY!$HFiH8`Wdy#V0dl_iZ)$*?Z+>lki3nXh z8?*XbQ~@sLDg4(m@3Yt^x<;7P(uZ|fm_7T2n5-6tCTY5;m8jqFG^#G1*2UG*Meb>R z^P=SPBJwt3&u?BLnu}f3VCU0`wQ|WwzA30+%(hv8m4)9j z+qeL$3P0zYBLq04@C3_j5ny%U-}vT80oFuaD^Vz^+mQTC5u^A4ysA5_jZ`8k2t&G2 zfHD7XA6-)|{1Z`W0L-dMLaxuO|)Ij(g_>w+BDx?@y98P~dP0wgl7b=w7KmT|2+ zR)BUH*ShBj&?Vzqcbotv8P~ew1?ZP?t$VHjWf|AH69gEMajiR1fH4`@x|0M@<63vJ z04ro%>z*gTY8ltMQv_I#3vu~{KfrL*oj;Es)ioa<)m-6OO>khFP%dWYqHey33M#Td)znvM)3C~es1V~c%N&!|B zN?0d#uWI`a-n^i2|C0b-Ex_vvKjGNEM(Tfm;SqM@wF2xa%qH+U0d6R~lG$G0_Ww}9 zErmY5d4s(9yF!`mTp{gzqR_^w|6JZYR5*vgUkLEX?DJoCZd7-r0FMo?r0%HjAiHqA0CAzjH#Z276kgBrHwpksQiqZ)cQEPW^H_^e zx{L6jnwQ@}wXwYwscK`BUG;UCl0K$^;LU5|FN?_*_*t7%p7@1*y!zN=XVJ#^y~ria zQD~Efz=o3?JYwL%Xz=3?f|z|Ke>6(m(-n=E@qcdDscm3cAbS6-d>*R)%p(xzC3ezN zT|4mRXMl(P1k7~qY2lxHevDX2-$3CJ2+Z>y!o!iXz~!i*m?J7E=1A_W`j_!$q{f&Z z*UuIP=YrF1`e$kT2HW-%y6s1Y+4fe{t=fKc9ov2_VAb}c<0Qr(;roj(g*5+I%ew%7 zlYRMw=?lMT!oG~&-VQG0zjJ4yCpT~uJ}W)B4rQ>tU=%LH`=OJuljnXQ)ACfZ=L@S@H+_qhm6Z=!ZI#D%(HK&0-nbYQ(ZWdM%ijqc5qan2H~in1EX(JJvlRq z<_};@a&OLYK5`ux#s$)WH%kW=NaJr_&&C%>!*7|xL0KS;zGWU89h1R$%PJ1WLQLUX z%dBPLx#wYs-X=osLOfm5#=MKRu(7wR)Jx9)(aG{=STQCQ-??r!#)5x^wwCBC$Q?)TxY=rt&cO?6kGMd{ zcYpTnnf55kv`3ltDAOK6EtqMKGVPJ51~ctZraj8EM^UCd%Ctw&c4XQkDDSA1%d|(C z_UORV9(@KfZPVx4j)x>Xw>wH{kM19$qGIR?qrv&MXi3fhth6NG5iQA8fQOf%@I4Ti z=WW8ngc_Srdvq+@zE9fz-`S>ZqdofCJhpwCZToBMsVMoeZTo9SP@&QO6ZB0KCjZv@ zF2IKY9&R;#;TKKV7hijH3VZT->B;ZW6KV*2?a@E=^LSw=>Q>sLe-`c0>j{ez=RO&i z>j;Y?=Zi8fcLScs51WqmXghiW?Gfk0*B(g+wDxF&r#&ip+M^K;h}Iq*!ofH|v`18z z^o#b02qM~}hcGnDsnW^q6ctbNlN0HVUW_-Q#t;%GBWuC(XgmoU<_9;cbp5{%X{FkykI56yY%GwbopdOWiphx&7W zS&ttE+V5^vB;>5e3GKP{_{}(EcGly!0&?DZp9i!%*5g^|sw{LB4aXVR$60yz2sny# zn9F9NtIoqXydO)r!e*Q?sCL6sZ@T(-gT5rpW7&F;+I*xJiLF+_5s>j+OZ~OtgnixG}3mt{-e!g${R1| z^T#@wuC6xy5gx>>us&)^>TfDAc3+XU%k{T3vYMz!+vWOO8~y>$aa2d!<@%4;vsiOn zN89DNyXWK;VZ4Hdx?>XsrI?ARdcZ4=w&cy)pR6j708Z}HkrKEvJqq9|S`4aP;< zF30PNY&|K`b~#?xMWDGz+vRv&AA$CEOi;YOcoT|u0e80G|D+Q?H1m=VLVIGn9B)k4 zU<8XBIEZ5489B&pN7W?OTT!5rV+vWHO0h)`nU5>X1&|akNa(tu!T}9e1$6Ey` z6=}O1A06@i{5db~(POZ~=fRM6F_(QjrG~@kcx4dOa+4G&Ngnmt)v2GqIbt%Q0-1nLX;J z?Q#s;<*8qC&2sJCv|Wy2yUeRjoHL(vp_{hLF>IF!^>@>DIfm`>)GxVaITuNk(28!- zmxDQK6~999+IPvg=*gY(O*$;EC-*)zx%=SmL^e8Jr0sJ2z^w0MrmZs{Z+o`Rd`}^R zb>?H46N|K6jvs2e27qHkep-FQE;UGe_?)&HB&le&`h-*iUx{|M>- z|MmL+lVGbW{`W}#O=tZ6|4#aUE-Yi?=#sy+<6l52n%N!K z8jb%o`hWcg(SNOx)$W$s2UAG`v5^Fb#-TT7ZA23fPVr)dB=BMs7B5Cf0`jaS0jh>Y z62L;UlE4vs){+3zl?(T`@gSjov?M_HU?T~z8Y>BKQ_^0HkOWw)S$Q!+68JMf;>8F_ zfGmGYJc{4x-zmTbtt3FeN&*C|BtXDO0)LH$C<$;YP8#t;|77_fPZC&&?c7KLEF2ZJ zBtXDQ0tBoiK)^}@1gs=Lz)AuHtRz6dN&*CYN#GLpVKyoMiA{Wtiu7WPPbv`j^A373 z#?Ncw7vK!x~A;D*S2KlbRs7<^W<1>?ckftQ69UXj*iu7WHzJ`rkN#IL( zVkOVkhRuZ6uY$O3bTS-6~K~K{$VmcISIn}UlLQDkNr3ISupS4GVwPWFBmq8KNx+-j zyZzg|?(rx0UVn1$>yXJck^m8ZFWo7?j#^3J>lk?}3Gn74D+v$_tt7xQRuZ@ZfRzLm zp`%t3APu#W0LwrUAY0D)^;E0^@-^2GUTKz~i_cy}k7|lpU1|!7S)G&eLy6CmT=+DK zEdGU0gfY3Clo)=DKg0jC#g8$DALAOZiZ+-B0T;}JO*u(G&O-1_zn3q23cpSgxSEyF zk1>WHBLNr8gU}R$d5B_Gb=(E>sG*oueKV54e!5eDop6!>F~&&(gq$Qm$Vmc(oFqU9 zk^nL0I&kko$E_s5l$MyI)62sl6U>8Jiw9>j~4ap;eh9gRl+eX?AY0W z%MYVC3sw#7ftEVh(odx&a$$cZEo}v(rdk^8U`tonmXsp+e%sQJv{ZZ=wium1MbGB7 zo`SM<*KV7K7;hs&qqgAXycYwKh;J_dG;%ihzT9Xtt9~C~#`~Br(~;XT{}S}#`KSXO zMm3O18tTWt`}55RMpBocfatH;hRoVX)WyCo;4SV?;t$jF?Pe^B==#66Oy*0`*t;LX z9x)V+gV&6XxNfGIWW$xd2(=p~^9Vj`b+bHcCX>=g1(Qk9CS)=>f5K$4&MHhMtCax3z+|$pWikm^CX;|=G6`5FlYnJ130NkRfMqfX zSSFLej5C@1uBkAYYR^)tO9|nFf=| z?2gGC$BK2Q|AgG>KOuMe&vFwnnbHNzWD;^r=Ep#r-Rb{rfZXZ--GJQbKg&5Llh8y= z<`+@U#g6+|KoiA|`vKlfEp}WEU+ZGW@!MVOxW`b-?!}JdR~ROf&z8ybCim`wH@PV$ zlVz;Bd5TOX!%W%Oai0cYW5@j)fGNa|W22VIydPyOllcgM>P#lfOqa=InHo$cUtzLnOATq_8WaU^z{uw8R{pUJ@e1 zX?|Lgk4CcQG)Y4Yo;)lszbU^@AdA&G%R#@?V^m@Vndb{2^&kSked3gbZ3P8W>={ z>*jnJNpl->Tmi*3xj8Gq{tce>5TLx{h4&rkA4MqyBGiGc6}RfhQZ>WIfvBK17fjSmm{t)`Jq@H#B7hWtn z5lwswFGeAXyc)R|UyX#jk#M<9L`Umhg*TtoZ{C@Hv*>BO`D!{fT4F4gWB8&keZyy< zsl;FW_iamhF`oR(e<;_mbm3Fz7XF$?nxk!~B#!z%VFjD}v|!VYL2J!Hq`fH^jjMC{MK?SaMf@v%wk^65QRU+3 zOqjH37s=i_WeIivM`lWfhnv$n?)9Tj~xv>{I>jO&T0=#=H3RzWE5D!v+J z#&QK66`fJ~7Uc>$DmtNKb5YX*wBComV${rz=tJe^GM*(WIy@x!x`9VMIk+P5t77e0 zuz}C|s7IdlQ4hP zS-@wBiVn{LHW(+`vw%R7XwL!y&58CbARtlE;aRW~#k0@=v}XZwv_yLr@EH--m1lu8f~tr{Dk^$>U2-f&jDfS^SsDmpz2m|aChkKtMHODs?o6&+9)Ar%!J&|E?)Dte5l=q#tAqSLd03tL4+j}aAJ zx*$=}=~+NXMMbA)!Bv1%RP-28(a!)4P*KriL`A<4kcx^PBPu$}si^2NqM{R0QPJsH z!1h#B^cYdmFGV>O6+K2&^veOMsOT}GqBEz8iVhp-;+yeKMMaNq$aNACR8(|IM4V?8 z6`j`v{Uge$sOT}GqVwBTRCL@DGKW#vRaEpCQPJ7LlbGBSFrO+adi?q1*O(@m+&jF< zy;HtIqN2xl$+Mo^FUWlA$-Ud3+bCO7#27r>VV@yiLLqQ_qu=tGxA z5=KRjzdFGCX2udmMUTJUav^{v38SLN-zZ!KKt)B5|6STqQPJc3rOzrVdi-r^bUe|X z1#d-}tqCoOpKMQFb(>{J*9~X3=fP9T%Cb`eY9AC-Fn|8dM0_vRHFY@saGW4E= zM}E4OlSzF#C+~mhm0yW5hxyv@L2P#*om+ zC^Vw`9Fl$#8<}b(oQ>yv{5u(c?uz}S69zdLG(8_Pn0h|G9wi5iM<)sRfH}?)z#QiY zV2*Q$#uDQkk`6~FW{mUXv@Z5e#W*i4N)~~SOc;W?utW`E!Wid;r2@nWW1JV336La= z#a&n~Ky$)a+=Ueav?q*lURWtWSHc+Qg;fHS62>?$93nt}!Wid;)dG|g#yBsm5nv=? zjPt_Ugd;YVFvfXdod63H#yBsm7hqAs80Uoz0xV8)Z0Aq`mL!aEUN}sEr3qu47d8s8 zEMbiE!r=lePyWCPHVLpIVT|*_W&u_vjB#EV7hqMw80Uo}1UMvNjPt@40ahoBab7r5 z058V*$wiE!j&V*(5G6XsIe|E8<|vyO=gezkoUd+1ULE6H71S}#rJ#%}Vw@95WLy#B zoItaTD`K1zXqRzCjB^5AGOmbmPM{>?iWuhv`ej@Z|NBE~s^F&S4x zsUo1p6*0~UtdMaUYw;WtGH6^V{p3H-DGt80T!~6N!#-&NmMwI>tEx8{?e7W66Ri z@wr#YM?IP780UQRbfRON6Zl1x+^HIsDh_5!W%!`6fwpjB^6bQS)a|(!@AtEkeP{kb+e6@{1VfB$Atu zsx~ayBQHf#AJagqcrJ_W5`g4v0r0EE<+;_rc|ZX89TfA|>PMY1?P>e8z$j!zcH2McC@ z#qpsH(bO#YMzM4!vgG4C=Pp8McP#l>&ROyiI`}R5_!Y*IkI&YUk7^@rrdi8fgk|=* zB_A7|?tvG}OxKc+WolUR@immCwB$1vz)rzkM3_RkWc-+;@CqxalyIk4x{D_@G!=0@ZH0bzFh<1>0(Q1`%` z7oij84prZ;!YJF1zB?~SM|dc(oho5`#E2sd<71TV zEY@t5?b`quW&7eBhi@f*#r()9+Xs;_X&4_iI8F1Tn^13M7$1HR+B3>_Ka7w1D6MQ) z4QgdOfxYKf@fu)=ao**#b>1alop%|C$eAAzqVw)7{Li>MGEtuS(N|fgR<`rmI`69Q z(#rNJgz@2cO*@Q_G=jP2>bHIs6NK@RywmfmpvK=i@3Or0tC&2D53@V-qvHZ@jF9uI zAT*I*1*1+l=UwT-1b!7XQ+9q8bd_^{74(RhnqLLmbI!Xw{&#*A^ssY&70fx_%_~T$ zY^O(r^Q#~tZ0o)qN_HySi8jY|--ur-+gtFp&aZ;s?))l#fm)nj1zUI$llxxO(uP|J;71Hd}( zP8`OEWom@+;cE;t1F;zA-6@3e(WMy1r;C2MUMwGug%|ZlV)^LoH{q4|Rd9%09+dtP z62y;!-!4=}`&D3DSFopjCpI__UfSkczX}2q`BlieLtDhbmY5YgzX~e-tzQKJ=T|{! z3Vs#T=If3-ZtQ7RYqal-%oBCsY zkOmkMXm{N!SlLg|gp8eYulPQa2AzAwkxigR;$Bg{^dW51<=^7BuKYs$)|bV-Vo2O8 z%Hm#8KI2DVxXR*QQC9914HqM+2=|I#qv9@BXKIIg#iv-ixL1@-ZgTulOSCWktz}cv^}F89}&L z4B*+iSMWu04|1Gpa#;6@&CF-qEBHDo;pg=g`TmsojC%!Nw-sQ8lr)!;&j2Wn18DAP zr9m4UItcU@F2ZvhwY`H-bAR$A^KBl(-b^Tfkq#awPyAEjjzeJWPY;j5Pa26*{}mqxi& z-N_zZOBlJ=lt{P_`vss2FMUOnTieG@{WsxPM!9t(HzRNVF99LO=(+`j8h!=nl8d9< zdI>N%58&u($RN25Ld}jOyis6r=Xev~`RBjvWl=7l%RM<5jW0NZz8z3=kG%Xcq+Z#@ z{qQ!HTFO#a6*v(2Ujsgp@HGN22R!x&O1}@^(uKkc#RzL5jIOQ$x#}-R>Qd$9ko9vecq?;muumqv}G|J0U`S1qrXwS>KFTJ93Abnx4Sx z@8I=c$?F|;e7%!iC}Y3E8+i3cw|Q-dIoMbe`ph?9u6Q$sH&5Zs!|6ARkHeeac&X|; zPD5|mdKdoq-O{>zX*BkE{cf56PQLydc*FL$$r~E3u`Kili+_eUXM3qTQDd~Y1FkWb zrBfFTBb9C2cI&RjB(=nJPiu*Z`b&<2jRF4}SLKqW^!?{w%V1&2PvJzvzs5DWWQlM6 zwsh&^SgiPK87M40z}eQLhGwXb!wwG+EuBq_6U9l0P4fp0sD zOgVMVtX%sX(36ps$Bt63AMrJDcU0ecXz{Ry4aM!9Kx_>b6_}rsD;Dt5+H}-&pbfWiuQ|&04 zsFt^Pvgjy!5^;(&SKsH`sNUz~Q%Enaj<}t&}03_qHn;neEywB@hwy;=NmXR-&t;^MMod z!-}_e230RW)pl@M^;kN4S%z$(-vtm0zZlkuKLEh~Wl_~{0e&w-r-KeGYlv2Mvf<^c z@c^1NpmUs2e17qCjMmB`zO(~Wc@;A-=OO0nAw{sIjXjsNs*#f=kfFO-KnDoA3*KW@ zmVGR#1GWyOaV@}%VIRjh@AG^dWWoq4bjXVeM;&I&_g2M%bUO;CVFT%kgPMoAg1!*n zNgHK_v+Ii;BLB5oq)QAUFAXu6G-H|R7lGv=&TasXgK%e9dw^kWhz%*SS@uzfs8~s& z17s)m8XN%Ldbl|{A+4OR3TRpm95xupohiW1F;g|sYhj39wUGNONtSLFL#Vx)j&8U)VK#x5rS2$eP=|Ym~flev@{B8aK1(e4KC2=r@=Ae%tG>Yi+qGq6)*OY8Elx3 z%HX|xM8=*JBHr?1j!S$+xK_M%#J4N`2Dms@`Asn45WiL~%+=vSU@dFRPPx{wcI$+- zL+=fTH@ z#GJgsbHb$BB!l$b5p*Nr$(nQ$o<^-q!kak>Z?+bP%fRVqh|6`@>}2!g0rJdMXR zkf9-5vWMEy$7&!)rAX*uK83@W+4F=@>&`Qxu0^3u5Cp(~k}8SSQqI&BJqKOwohmNC?@C z5zCLSr0dTOlMolzQ0fyEQ*=@|G5q$E4W*8v=cQ=hDQQA?YM3yY;8dHpRh&~^X`vd^ z+)KbHk$Wi^PPa*Mx<$hQHT#38SlkxFR<#G^CQOQ7ZQdj>wX2FjEI48(Nz_*D@D!Pc66aeF5d`W%)~{pG}PU?&(` z?!p0UOROCuTyUuqXB-RPHvb1QZ8@^I~HUHhAs4WhD8Rz zMo9cx5-z=f)5f<<)k7W;XYb(9Eha5FG&~Au~=v%zS`M z0S&s+v;zXaqBGrUn)L+D@pubT!vJ-9(wkpzFu5RwYHyU20CE}wZn}-oH`nhONTJ^b zRHMsmzqvCHQOW}$bl(E~(M-;9IO_Y6@);bOrEsW2p-!j&>1tE$s+7cM8%ey|dk139 zB{B!^5+1gc4By>j_-?b63E5Yb_bJUozhT=4fJ!h)wP!$sqyuGU;(1ai_@j;Cv}$8s zTD37^SCj7FsLmms;A)z$wFx$10aOxscX~8tR1yoJ((%$4g+s*^vsf!LbW=-$roiS= z5nx3JwaAv)MTSBZ`o&5XUL&(~mQAiim4Unh?wuryQ*ns51i`99C1AGiHHs}$J)L0?`q${J36*(g|n>xD2=W zqXpjFugg+pu;?C*kgq(-@3d19=pg9oVV4Y}u7(@mf2`jpj{kE!hDwV= z$0?!bctf1{ea|(#)d^~Fn08_~Jxn^u(8!akek`**FYLJ;2);WdppK`yI#PVVX|@h6 zf(5ml?h{Os@-y^DDo*bMy>L zhv4%W((rRDgsB(Gu%fo}Qj*S#DoOkKK@uiDivA=>LP9OZx3=)Zow^=b_SGiu(Ps=6 zaYQNh@e#8OeeN*yxii#3clo%k$TbBW%Rnju)~zTwmGvpoRdthpv3!I;Wu$goMn)sRJNwWeT5kjBsXW-m5+S80*!1t&68c7!6N zx0b0)6m&wSF^LDSjh3oFO~3!LNYde`w_jgA!HASWus?>|}SLI7JG&w8?NF z{;7;%QNVEpix6WB{wqwHU{!`no_ZsS#^!v|KO%JpB8{OOl!T|H1DIJpGn;r|;-hxvl#x%c%bI;oEheBxxH6G2Vs~%k@l-50Hm$jW%z25b z8ECq|EyFQybq02AMCZ!gF6@D~QmGmW%+IE>XE^nvIgOJscBgUDW3Xl+E(Y2c=w1vi zK0EC#*N92xfKROylFqHj7)AP z=T&x9NR1x0vQBe4uj)h(R_h_OjX)%qeZ}U$89g=vC(W;S;+*O5He;u{AuR)k!nt2E z)iHCR=58 z!LM3E0mL;cS+k#kbvJ7c42zgBk;EqyNvIcz9l2J^qzcy>Hku*=p>+|4OwKvX^6>gd z&NkS1Yp;MRx)6ouhAD(Bx33O@{W()xRy(zy%B6w+6_{R*A6*(abTZrI);dF0)!8&6 zM+Nd21&PHK9(HJjsXGUjk^w(vPCjh89*(oYvY?r8$bGL84!5H{amXV#Xf9N!CBMrI ze8|8jYJw0z)=dBQPBmQal*xa`1%~q`-y+o4j-|U7HWr$^`ddE@UM&K%w*ebQc{9a` zA*Cr~7Xrr@>16tgS|;vy+F_>(CcBYtP-B)^fU2XUnhrZa06VWx*7>M31xC_vfJ26v z8wUDC^GNbWeEcpJTZ+v^;>~EtQqDK5=7JDe#tbL9&O?inPnNCjWld+z@_4Vry42IYRK@22j96t z&xs;MNH{b|Ko<^kG;O0lC@GffaF6AZgBf8aapdFaE%cEIm`SC#fLW+|z~RrzPP%v< z87g4;d0Wjf7C1zzbdFXkS#5L09NSb6-?IhX->wFO$uP63HWJ3<%Ky&(JQ+ZfU3Ti! zrg^-cGsS*lSf1;%p9(!r@blorN4FqFaN6S+NY#F_pOy3eJS5naLwr0X>|L;(oT|QG ziz%lCMN!x3VZ*AgJms+s;EX5akL85N`FoM~m7^V-1a#ri&Yp1xl{D2VQ!r+n!f+oz zlM@?5_#>!jOBELgKNCk424gi)B(NOgtOT}WOz5!XtKkf-BRTggX`*v>(cb7J!jBGc` zNXPAIbTZtYtVrSZ(iR19@^*X!8IRdY&DU))6PQoTq&nVi1+1#1c^Dz2Oz3fHKAduK zSVi&2!qwD%6HYt}(5fZC6WX-|;`2l&T>dN*1!3*y)dUnY;*E?6agrupL0h4i6RvrZ zfw3@Ya`Xvt#^9qvs(r*-O&@)XJ{b#}^J$JuW#|;mnXR$FVwgf4Pg`XWN96#9l@x~c zq%n+o;{e0@(ijFi8p;Yp5W`vt_G#A2C;P#E5g0{r$}8RM(l{{fW1avxt-mO{8hDI4 z-a^aFdJ|h{Xq|5*7;JMe7u2L1BN>QHY$R~P;U|jCyxqQlwN+_ch?z#bqCUrA=f0(J zhNvB!9$;kE4QhI;#8)3{dg`l>5to1qM!%r~*{uUC80F%DNEOP(11T{3@=J^wwtv3i z^UZ0ZEDxf?m=>3H8+6;SZHUiT4Yt5&X;fvPsm1}!*1l9zXPdArWNXD+Lvg+<40j9D zE_H?{{`aCoR!4a_bq_nE7&sig`(1`thEQ#3QXMJU59&wonSk*J+fQ{fd^1cHhK|rL zgT&u{n>Fv^syf`$acxqJHaYT%SbVYU;-Rgu_uPGsu^yB+M2x&P99)z->Y9c;)U zGZB145{Dkr`re|V*c-7Ei$Y4ot}Herh;|d`2h)tfy&f&KfOu5q)fkwoI$I+dBGGBE zA{eMrja;!9LDkF%S1j~3`dzh+-OxEfEzZn3JykZroSf;>s_TI{1t_0iNL*bVA}Mb) zhgWE$DzD&HhT#*S-{!fGEsDctySl4=OJ0ws?RsO70Q^lREI-{&S!~Wuz|CGam54(V zF)%)XbLz)IpUk;rSWl5$1t;NPV{{#|UR-9{w0nz;tc`bGF$zVd2hLX~^t563M2s=N zW(u(jD@pevL%J86ch#Ui8Q8bZCao(d9ZX$ZOnCdVVH8^Wa%(0hAcuC$vd3$dfp3pFH_FsgF&akC-W z{Hk%qa=?t8tr&I(Ljrb3n4R!r;Z};$`k2TtJOQ;j#vg2V(k;YT(X;J(P&BbURu|CV zb3)>(iX4Yw^Qge_K9N;9p6ib^+)Di%!T1H5P0syEhLbv3jf&AElON z7;g_`k3J`)gLY|FS|IuOFN~m5o>ZDnD%+^Qa?;SBv~`i7ZYt0uv3bqRVY5;sW`t)#kW;%r0qt}G0W&VI=oC8T{_K{ z+@;wdq_ZXEk_(#AE#1a0JSWt^m?J{Tulhj4bW23}9lh${p>GJ-gcB*>sK@ARb#c<7 zxts>Gdj(rAG#i%wqd@SEIB((*NM*#BAw57U0d?CrtKcTQ4K)>IH7JE@0{<)4OBD#e z(AI11@YoHv5~P#Ct|3|x9e+x1pwRMyZi6pb5)xrn1^uoPV|4TZZX+7^HRp@qJ8rDh zK4Q%7q<3I2g3hA%hotx7z-XB3AkY-5O4p`0m4NdwTiApu5xdky8La15cE4bFf@nP) zX=6uhcj&|QqdxS|YNYs_(`Pq0Nd6(o%2%7>4mz*+gdQ0y?*u-F3>R8%{)j%za>9t z&LSsHm;6cs(gTvESYLXBT0|!n>9cYWB9GYYK98jB0mJbMELWU%hXIf5ce&((R_o~5 zfc~6RKG2#&XYQ+YTv@t9S*phX-+_jxEmRm)2Km;N$|Q1EFhRa$qM6XCbWB}lzfwAN zyyysYG>Jgdi*F=@ppxV6PY@*K*H1ZoI zo9+IvJ2rr6H-~k^?B6PGw~rkPv3FaYhJG!U^@GttI0)soV!}Yk2y-WOK_HM6pe$FS z(Whe5-|_h9V7gIN=f zKI)pmaJXJ^^-W-=#UO0EwM!`lyIGR0`8ScUO1`mW!<{^-#AWDpbh2DsIFqEa_HC1%ySV zSDETG7nMI~TxC=PX?;()hTL+YXRnV&q|z{S{kxD8^6fKPW0aK1x<35(wdA6 zta9Dw1r;2g<_?Wbu3?Q3MbQ;CzRThqY`Sgh12^W6i11>5S+jw&e_MU-*D#?+*&Q5T z<6(##`d6z-YnfbVS1D)O0Xc(a9C|Rl_fZc<#gYb9^gJq-Yy$Z^^SMHK?YFVdh~wfR zIA+E-3eeMNY4Qn1-wjogTd$nYlY(k6IZfq_W2)r;q{#%fBf3I+vgD6=LtV1Sp zOmTz@(XMyuxX7=HELt^PlD}n4pv2cGJ~bu2UEExID-~G;?e?~UkZfaFXze{mHYHMf zq=j!&eiZ>JM{Dat9X#erc?Hse!gUJ`YHF=iVH=&c%y+!4MlhkmH&mE2=V&$X!m*8d zxQ+U^_3Y}21&>)0L=(A0nhYJ4^+;j(mFTK9gO zwTf@0yK?XmF8*)c|0dN9Z=DW5_DKhs5gG3@t0__)@wP%RH(YUalj!TvhDLxCTeU zDbDR_6sNt%HG~L~BE!ZhUND8I8+eV-&NcKJ!Ah`RBVZpq#6cJ*A|@#~jjk=D!b%qz zhL@a!eZ$&yL??}ifkuTY`XG)IYua=4)J{^4xb7pT6r+ZC#@hP>g*f?&sRfrk1okRtUarkL%T);j1_A*#ET zopL{+R^2I<(_Z!>+6MFeEQ)aw zLt}o3=IO}$;cmRQ6srd}3DZa_sG>yjni1KIHrKm>CXFm=l?7WU$d+DZ(oRaf3Oc1_ zOS}b*q6xjbb_Qu~U1>(GGQ65!J$FPM9ubR-OL2*}Bd3@=tEEFbmWAYw>M@Wu-Ow?| zsUpCr!F|0vph#8p3zE1dWPBhg^>3FE$qP}iNDN%Yixs zGZs)XF2vfU3Q2j!fUR8ZvCF*$r8jmG{8YHz6j#k72DkB`AC)g3qpAyG@26-(d`vnL+rlR*~Ket^uV^;R%D^;>oPgwb0`lWNyrBhH7Y!&a%xLKdo(of1q+f#4fMM(R1Vh z4%_phvj4ZQKo3O92g4s}lzYW6)fh0jD335>ii$dtZj zZV0#$4I84x_?4b7PFfK0@tjEIE(i}eV~wfif^eZSTyWu`DH4phY;!C^3yzGT1*33R zIgk*LE>^nKvyK+wq9zg3s;HHo@<|)V!8%^8G@)5s8Tv3(%Ob{uuiBT&9#1-gXqVjV zeeuLwuDT@%Cu)^~BB=)&!t2i_i-4;rjY0wR$Ossf)JO&e)JQW%8k{_gr6pY)za#xg z1;I)aaD*rdDLR8#1~nYx&492xLZbKu?sm-zExV$H$C5^ZSh)%%Xpw2Kf+X0aePzUVm`%QlvOPQ?MGwQ{QDDsk+@$9X8Zwp#q{ou6WSONb zqIUB-AQD2_wP@;C0tN(8Z^#kKl|MYb+JBZUA(s+hkFRjAmQC;eR+mY#6=*XRo2ckB8C>m@VSVn1H!s3r? zr~wLBsx-sQ9vvlOR_Zr35tj{-d`jxZTHBbfLr7^5s<)^Yk7hA|rvb62lw=qTTV9xa z(_^PUFx!UG$Qmiht{4AA-?qVzT^m+xKZWnYxB>X?_2H_snYGcQ=|gHgIvXwNyV_&} zdwJhLEBHRm`Dq45#3^qpV;`LpUwRJ67FYnOT)_#_+~Lw ze#}in_P0R&5GopYfvk? zs^p+n30AbHwlLd}DuxBYC`L}cKt1M|O>(4Ef`((%NNsE@?HV->wl*O!TBcfs%Q|3{ zE0?v>wfKIv>O&}iz{jP=9vj5};2@bp57i%hZJ_bMnpMKd;S&;tP2n3uwDA2r1o0SI z5)AUXxb)6j-cW=vQ)mt{wL4g*w2xb(V0<7+$=>%q(GAi2q?Pm89!`j*r|b>*PPdr2 z>2w4Mm><|!hu9Ft_CXF4eA~`ocTfbC(jy_jsFK@rdeoz4&;nPKfWou4eU&p+)!1Q5 z6QiXAy@oOq$r>h-)%-LE40;8(UMpHU=vm)md^vSIT^3)ciB6Y&y6+C1_sCc>R15L4 z5>HFCQ0=lbmbA3hwQH^v)oW>q_dz;oseC`SpJnop2N|ZAwZaHtD}ndXDs;i~4L-!g zT3C&~c4&J+4HnYd~j}mgZ0+WQ*Pg^wi5MQh3TXos)&j zLP^PSWfk>8I4)LIsn7-ZF6fGlhE?K3JMAk=J5NAX!?Wn4!#0`e7`I_;^Y*^&%;~Db z5wOX}LaAFnp>=U|#3)&0xXg(6WXbCFkOm;SGSgV)W+OeCaA_5_tgH(pLIoaCw9Q(gjWVG zMh$LH2F^|txVRDts!nh?tKNllz(?PIwems?y<5X@qS0;K3FQ)A*;)wqY2G%$an)2f zecOcbjchT#{KgAY=NIoXutW#O1RJ-@n(?TIu%fE%u|{Glqn3mr`-iyy46AL;2snbD zq)35yvl+SF*)8&~($;$(tdNvcEC`kx*o6kzm*=@M=T`20gJHKL{od^X6Ink^CtSI&|8h5WV!=uRfDYTxA8}pMwK_Z_Zdd5qu=6M zMAPLIZHE=B`+R=PY9k=5;r_AKE-@JiyNsZx^~a4vY%E&rC^*k6Cm$TY^(9WQvE_lw|M!{2QhA~+CGPQ0+-oKAvE`G3vb1;&m@rzrx&%~aB1r1tQ1S*{WNj{3$!Pr4v;-zH{#)3( z%E#)rm5#Fhdm=;?M_J-2PL4&U#0T-TSQAM(Dz?fqjP2>uBa+y{>qFMjZ0_I(Wpf8{ ztfqhP<3#x!VP%x4G_O}Qhpx@)(6v^?YkzE%4tSO&6_wK&D$g)bRGvA(5M$d_tu(QS zN;EsAoCOysJ8TD{gFpMkud2+GW2I}1uRd@{>nH=4G)gObc-xOw#Nb2tscq>ANhv73 zMbGS^iV`E!kshi}f0n563{{jEq1nzh1>r7PJjU4yTdZlw><9#g)mocp(!jd=JyrxDV6d?LsGZG39@i@!9zGJ` z!F;aLeg~1}WD9b5hm9ztzm`~GUkcR@xW>cOYxL?>j=xt_B?eJ@{?t6R1JDvcblzk1 z4LPg5WlfJ(>;eT6D>+L-;!`U#%gAya>BZEUM)$6?GJ$v1SSmqfLbo>PuvK9zBW{>5 zKC-iMU7ApGHo*^LqNtnPO~b;*$6fL&l|c~9$05{H^Gj(O?D_x-X?%i&c94c15w-&^%4aDR8Di90J2#GXl8;t7 z;M4BfN%2aw6ZTKuP;6$1f&DOOl+-dsEXmqDf?a9o1ji@PD>s`Rje;tFW81^T!KE(?MfrdY=4M_a|m)^ZYz)9lt{w6G%Vd=NuLrE zUDDUcI>9#caCcFirfK&~<%^-kf-ssElP2NdtiCnv?d}{i!xOB)s==3GQL9sq$T@i6 z<0zXWE^V7sHn*MwJ?D(7@YnylU4SI ztYSr2VM?v?0SeAE2b#^~fxV{fOs3^ZDoV_3$_`7ZfR-m#mBEC-wX3GSCsR2n<#r}hF^0Sqnt^DGqVmF>%Onaezx+nm7lHrJ#`J)gFSzW2aMHZ0dvG? zS$}iHC<$VtMEQ;~BjPBk2>rYkP}>p8O*GDqFl`Eu77a5>kx`0_QtU@cVf6wTkMJxO z4bvNe(+ApZz<8qRZD2&19#wi!_+|*1b-}aBy1<`$Wsnkh+ZeNEjX?~YL(AQG)eKq4T zh8@X{g%6TrVNmsy)oJZ>!P->9Zv9m-qZUfgkubAQhws6D6bg4!eFTIEY(n;cXaq*e z84Wqm?b@vtVG1-PTl@$1ey~>;zhyBeQw?O&-u{>NW@=Sub9tc7B_cvkCJSZ@^}yHR zRbQwxFu55segLmr-)z?^QH|NIO<=${yX!)VH*SFR7ql|kWQ#n*gJ%{VPJd00y*20vk^3gZp1F&v%>>hHPrF<(ZWeK0 z+)e2nr^4+uxI=e_+Y1=TlVoc|tg@5%~SuAIOv5 z;$#}I{m(v5U$(V;*ksdNTRPCH3v(r0qq!0;(HJB;1QjR6Trwv~QPdQM3!i2%@HyDw z{b=I|1}@vVuAJ9jSOrDJ?Yt(!lD>1DmtSx=q%4;NFTb#*nNaoe3tObx#UjT0nqk3h zRk&QB$%3=M=JvR?*Q>S@+;hQ=sejKHk8D=9cXHl>3tw>M!$h;BKcwWs)qggA7St|t}N7Pz502YT1ghVDOAn^rX?U%Ts?hiKXQZ_x7=yNs#-BLC^ zT*uG4(+RAhaAmpkiA)0b6neX{URcEOO(AJ{jN)iA^7L#It^FaJbknBb<|ut2 zviV|yI`6@DJvnw~!|mb!loZ-_v-W2$%_H^tFS$lCw4Zoao)qm#V=$nu2CRb`$Dbar zI_-IQhAOOU$;g57p*Hh63AHyYsAF7(X`Ng<@eCFlYUznALRZsH7&;T2IBUG0oStNO z?48q-zyv4xX?g+zGa)^3oZ}v`k=aJ;5%AP>2wAB@;0-;gR7WWDKX5pt^;0sbc!n;B zTI9tN_DMI`ss{pw09B5@-e477&$d{O!+2?CW}>z@#ev7>ss=t#Mo)#ue1%;}Qxi2A@1M=fH1=xJG77$ycOvGy6S8okoB2hkm7&}Wm`iO)i%c_ zVXv)@*sU!a@{%~^ACKRQe>KYsKvw8tcNm$s!1>jFhl~b6gJ&!4X z=TTqlXlrM~p0GioZX>UK193i0j;k^BUP_F|NWplF)N&6Y{cmQF7iupZyWc)1L_CT{R%? zlA464W`1rk(ICyczt?4Jypz-jCEZ(X!k3Q%Zx$mGzCahrT{h+pcYbwG0)K~1Ye9IjoN$+u-Z0*wkwc# z{=tb0^g=$UH3I%B*3ts0;0%&HE5^@DZ*t~}29*OyWWvGPBAWbx@_FQOOp%oLP$HSe zwrDgz4g5Y6K&0~X6N{$l)euF6^jgT8hw`pSB_6j7{}%IcXOpx>WAhU{SXyJq8}=!`IWNB^g})!R(I4|I;|+J2L=KY#HFyx zK#7dN-=WxUu3E7~J3LhdSvTQqRSpPOi`15|QuGOny&b{V7A?~kE?5&}1P50k$0eS9 zKaTdHDnbe>go>%#oqc zwW%H%TC^lbFbEdGDv3lb>L)NqrNSuSDu5jG=7UwJwGT~eij@kjG2|hW&={m(q|zp1 z3{ngO={EcM#TZZ-gY4ZYPOJU8(`rBJ0Xf>cyAOqABc<=-=~FPbmFL6hxeX61FqK0y zI+fuZW(GapGVPyqD($M|BAlC^xxpEosJ*-96m@MgiuZP7hc(Nt7i?Tq74R_7el}Na zr{wUC3%i1KjU8&Xx^ru0H14&?D#x3%U{{zTw}Un3u^jB>Twg%~CYBA%!8?#M}u_#u# z{Q_fVY%2HeqBpC3uN<>k!U2j(JU@6h+G$xsPK%G)i!1fuI!E0ds$MA<(p*6728N7W zILzayc`*!H(l!PolDEZ|^MI(8C#QO?3tPaoj$88_d&mSzdX`^gf|2xW5nQ?BPL?UD z;ch*b0P_I7S)c$t5Md&qq_|~9LWFUECm-SlC<=Eg&08)m+63qW;zMfgcB@q>t%zI` z-ai${xNB9FI_Em{QGX@-xV}<;+z=$;TV{|9X6r=T8`N4S8matUt#XM}F|FYe8LqZO z=9wijQWK?UaUN`kRkb572Npn8?MT34EeaW^#TxzaaYR3}VgOEQy%=6guNk#oz=0{{ z%OL^gN}ZE!;La>F-ftS)gNwpX!BVCYfd?xQxC)K0iJi2I2rz2|_?NPUKuX{xA#~nR zRBaNWkY%AqiLD9`B;9rbl&@kJSrTBF(8i@f(xgb2I`I#6&6#QN)D_HA699spu+m5i zm>S>|^>2>AVRH^o^?+aV96f`$7;dJcP8c+32ozB_J1kK9wZgqI5BCaWM$snqiDIF&**-JFxPodk z9@STp40v`*PDJ5I?&eXAC4w5~f@KtFW=LWO4U&W^PP`d%D}ttvcBh`_EdU;i%L`C* zJZkQDe%OVe17zKURXSElgBJ!#LaA%<0vR&R(3OHd0p0UM5@HvoZCZkRYATiHrNJCx zW3F7>xXked`xn|P1J57MX zb35`4j_}Ph7+?tMP?}1cO9S9=KL1EynB$vKgqIbCIcxQf9 zjDdpFTxx^-1S?(KvU%lDGgxg$rM5h< zs)YnT0NL|o=+Vz8KEHT6c1tKRxsO8rR_0Z31~ly`;TcNHP;@qGe$7oyM#aM=Zma{r zbY{w%sf(NwB2TrY?@yOO9jn675<+ewQ~r!z??=Hdm?gU7YvI0z6@5U>vGHTY2T4<6 ziL*6|aobb-H=jW7o+KYET$1>J`9eaay4C1{$OKHJB&x)RX}ZOxGz1~G>}xWvSdM3? zwCTScC)MGGjcXA?5T3EA_N;}mez$bm?@1ikkM3E9l;gXn6N zd)wqO3)~)zY0LC1MVt(SaUjdf!)ZG@ayXqnb3R~$BI>1AVS`v1=Q7RRRB~ZHQc=*J zk}*yob&D!4)U#x&IK`{({m8ZxGPhN>*9z+_pK7P=N;2*E-d2@NQSSDRH(4SGC+(DC z(^Q0Iv%9ZmH(-x3QSED#FPyN$i`$hNsA+ezyubP&=e%VCKmVUDnpBA z>Ox!m&r-V3*3gW%&949wkul>%LECpsKLC#y{UMm|%Gk@=nk)#v%-veM;J^jJ)SygS}@6U9TB)h>jTc<@Bg+Dd6|U63@X zG?$?{Zd2fT08VmNcFP7mL-RdC^8jN-B~gnoXY$Vs$v^x2XfR}p) z>5a{xj^QeeqNXves0pIvQXLX%ZlI`XGVDu{1KO-qM9&m`jZxGXi$QPygYM=S31nT1 z*~nzGy}Wl=5)QpFBUh6CSK`Z2yY2S~g$vIIL~qFSl;d--QJp z`2U_gyAR!U;F?$HS^rJfuGzfihRL}LlXZ*h)+{W(gDT2>7rECjOcoZ`uKC;WckPJI zN{b)S&)-S>U0B?x^x8plEWCAB{QEhFELXx41;>Oc^tR0<+IY_ z!_CqEfAEiWcYItwcnrta?(x-nsHlCY@Eji(^R*sr^vqNESk7uB@KEXTp~ABonm?Cd zRxh{JLp~V!JXEbbRCpc?FOTNB52t*XYOKurkxQ8_tW^->qo+mv1YF2jk?7J;icpiW4 zIe5)(ma`5Xy7ksQw_S4wi(5A120KXl;(+0qWl>k2o;Mrq9@U8_rc;69;jas1={^@0F z)~;JSS;Kno^l3`3Q(EEFbh_REu9vk>U9VEmoR~EPRg0!%Z>;h~@)dVYPp%w6x?ik~ z<>6Q`HkVY~HrcnhN!-RNXK?!`F!AJOV!AmIiMSHTp9AvrBZ92?NrC)~8c6BV;yZ%_ zG9Yk4&;0U?40z^u{EVFPd3`TloWUM0y1^_oC+0uL#u%~b%GRS@{W6b&LON~cLl z?hnMXDKcf01DC7tRc@L6dN`Ep!djMWQOx!0#~jLNN&G=NlsVxp=QM{lYN37PjPAbW z=392{e#_yzKf6BZz@gppNxI?4Ug)WGlqcBCF|zHWej6J-({m~Z`;&)|@m5ECF_r%+ zOxUK}y=-IlvhW8oWkrL8rG|;WB5y(ss*4KyfO=TKDGHaEQ!z5zlun?z*d)mWN$Z8jEo_TAqOWTT zOZh!jTMFL3&i zy_Ww*d?rvjYlIN4roVK-Rvw=}myj@yRQOlivgQc?~{2qgojR z?r082x>UFesf6idL-4rO&Qjjv?NB9WvjIu2ceY4LpL1WA3S+v~=@r%T)T+iohikJQ zqV*X!jFC(NX-5vN&el%5TOw6Zi}njI{iE+WW0hdp#I!3$yX4es!7~~C)?jyyIx9-`u>ppwu-FF|pdEY)obt_G0$FtR8f-1G}5a&Yn@1nkj+a=-Q zdoiZ-+XraIcujPx%{JlwD>GgP)GMNNYgu?$mYhr&oBO!uLJt79ZtXPO+T;r345;WD zb1CD$l>GIRR|oibQk6%3M!n$sApFWEdcn&z@E=;5H#QX>|)ZvJ9c>ncks}G zz58!hdV@Y*xXcREzre7c)rKv@$6Kp&I&#?Tp<^235#vw|aMKfVU}BAk1_;UNb^ zno)d7`1zX8+0n-;&L?R4f}!aMHK-a9c#8o+A+blf#vX>seX0eos>9EhzB9W#b# zeDlu=^dq8hg&EB@4W6f}xZ;-6XW3jA{Lao%5KoVzjEfn&5I~u5d$*3)n7F3cj8D?? zs9#fB`NmCvq*}(ar1cqmBIWU{%F|N921-uL-$ju>5f(*_nbJgXx|MXb$@EzdF&~Z? zc#?JTzXeqbbrJeb&s{%xqob3_1^g0onOnl$&?H2Ni!WiytM(O<=`T!|A&m^;m(htn zqS!iFGS~FtHBx%g zJd(`xsm`k|KfP%3kKQ?NEtAv3$YK=^kAhdmCL_b0L`I~_Zwa{6<@EHygxvj3&w9}x z?N`G||Hl%hI?HtX9qyI!v)#Bg^39gc#>oI+>nSO`Wb1Xg(=fJ}>DD=3o(sYNf`g&pp*5(yI^d~F4? zF(bmwZBA~VmHb7)vXG!u`;t*H{d#Eroe|CDoUY2&AQ@cGO_#Y`J|6SYn*Rhz6#9#g zSLRsogeCl~HeY%Vgd@FwEi(KsBN=umO1O@O7AB{L-Z@!d{m1j<&9+u1Ie?Aq#fzPb zUaVC3(IZTZ>S=_sZi&7|;&p-SnaS6R)*>4VBS=&1HnR;8QnvA*;OiUJzu2fihHC1a zF|Rr|tZ3*ue+}f13$moVMQyO>Sd$C&A^N4Fk|4SB$#H)wNap}Nn?s*lIY(3Y=#**S z17)xN1yT0#@DUC$nv+=Vld!0_(e)xGLO<0HJNS4~O11Z$S@Z{T%UF!`12I(bPC_t` zK)dozE)j^`K=YG}($iNm{UL(FX}!u1uJfdN2=eLyrEJzbO%3Z`>Fw*_`TrYuw%&lf zLJcF@k-xEGE-c!_xoK+~R?d>e0_EHeM`maIclx?yF&8<83F!@!GeZa?OAb#r*u1d5 z8Ifw=Nu-XkCe9_ewNL@v;nhL2UE>Pg>Un`8d_;Mvkn=mD%iM09ywB75>Ew^s!~~%{ z<6O|FF62-;bdM3R5)IY}G)X+JQ=g$$IoBA7R07o9x9VNBaD8^!c@G8G>xR zMM+s@^h@-6jsQIVxsjlZ)@H1d*3#0vN49E9i$haIsf@HN?!1qP!hbkWxH6s5>qMtJ z{Z{#t5JvL8GQHhrI{Z%#ynM7e4stPx{t$xH^u9QFAsl@7z`@XG=;0cSW6YLpr8Oj6 z{a$Je-K!I#fM9?`O&Hn#^$76usglV*e`o9vtET4~Gs|=6MkTRF?6jnP~?N%A&^K*e9;C1FoOE$L6?o@)y>^ z6*-PgCtn&uDcQW+?XI$`uAh9R@m?`eMa*My^5yOu)5(2gur!6BB<+Fs09-%$!r*t} z6EPEdQc)4OB*Zu?)3QW5QKI}ZhOhgmjNvav#&C8u6zWEwvpKY_92@tuBv~@Hia0=t z-*}F?B-*u(SM%V914aUncgM`A8>T>_R~EJ@4E0bKol)>b^~XLcs=snFxQSUBm#12* zabA`?+u^OK9jFgig7{{rhDsrurE*h{JEHR5q%xM1M^vu)n5g`rpfVP_W|at$EFEK{ zv|hWz5a4`U#B%~B4@>4sWioPB>1vbo0lu?F9D%3xP$7~mWMi->dkXs+q>Up-Gwpup zjAYcx_{dE^3C@0LB!A(pAtaWs5jAyt*bhn~{wSK2b-*P>C>eSubxL=PpexJM&Yor&pQ1!Ov?U&0B51QjUPa_f8+@2V2ECJgB|uN9(dv-=O?;vQn^#=99$g zXo7id*1&uct$Jnoo6~<$RQ~pnWqTele=~xav4L5=UIFa;r}(cW_VNnR5k4=th-vur ziz1x|P9kl;^@>P)JhG4S>8KdCN1A*&t^ME8nh$`EC|j!aHv;?P0c%Z+U?YAW;e9i( zKO3+f#TxcCt?!r*jOyG^osW!YX%E2|GWNo@H}~o3dF5Yfo%0Mqqri*wi>7P3KTHkY zM@yd=s7p!LW~nU6YYyAwJJV_{)*iD?PVQneJF;yLr$4-FNBjklTG~VD9}A4(arP9EoB$kfT>jd?@>qD0O&|V>Uph zcZNmCk)*`kQ)-;5Nz|EN!zStMCl>eT3nDTS!#qUfu-932M7?mT9*T%|-HNw`R4RNk zIkm?_t=awq&QPKSA=d*;Y%h(|j;GvcYo_U0QYxWXR~yQA)kG>Zfy;>*GU{XpNoc1# z^o!0)uG>=@Cx{O!ND&rr;T|;Q;XyX{!mx|h_Q{i=3?raHX1Ws%wM1RyyJv0Fp1FjjB+~=PKzo78fyD>r&v{#n?+j@&pBL4qp`WX zBTQrkj5BqO$F-v2I!0R|NEu}t!AfQ!rrLCzK2}4)Krj@#OUd+j4CRMx4I@kWOj&+NHq{$n!3V=j4VS>wgmFVdNezcgWel|Sz45EX02`X#2y&XoKIhQ z*eLC)4QZ584^*>5jD)f5QhzNw=vZr}1&HESZY=~SU zl2Q8_UKCD3#cU7?_QE=^>2b~@=JzfP`*H=%l56!HL4=ZpmN!dQU-YW$x7;)gu;Y??12W_7`mf^Er2!_vVj`6nRueUDxd4gBOfvoDOe-ps8D*O|BgI9UA;YiS%q3l zjaOucoy6F$d?LPr?EKcgb=^3Z(*~1wVwEjxN zWdS)RSlaEuv4=Td5E<3Km-QAvTwf4rTk_=CLoE`p2vO-l%htO$9%th}wCv-%u5~n+ z_C}b^Tuk7cM{11twAboKk>YpGS;gW&xQECf5Wx{9*qh zMt}NNZ}*ooa4l}h+V7sYUgr-9?;XSRA%~)WI9d5V=#RVeHb+g7f5<3wy9tt9&@EuNH9MRVqFD;7{WQ^?}hqBEGaJ`D^Y%g8kcklTi9`d&Isuz z0Qt{DZR1SL8c*zp>R1{h$C+UWUg)ne^3*(_D0$kKtEKybNJh`vq|X^^_b-b-*%4 zQy$eo^6bIAH5*6Z2E{DuIJKXU{WD84=ZHqAX9#A3sJ2R-F%%SB4=Fo3$2Eaxg<;%o z?OJ2iMInvw(j%IlgH=hqv;#62ie(rcma$mz75K637X`Wnwt|I!WER{0z0Bf=M@Q

zg}LnU60q{x#9Y@VL$FCdq-{!DxF=c}i4~UYp9E#| ztk($ybw670(Hy<;q9O7JkNa@T-~P*PR(Cnic(l?jt#vt0-Ai-eIPSMu`8L)im)+>) zo4ESsz~Q@j1x~v1So9h!C9YcyRVyHh-f4aJU)ik2Bo7Yi+hq)K_c!%Ryvx*k;eJ=Q6pbQBUfPBajL5*4*F*M)>i>}eRl#u z23ezi@?Ic@Yc`gF_&OklTSbT$QO*4`txq%*+2l8eM}6}70)b=)df zq;u!q{d@0M5+rx*I%ZBEeT{Du?xwZBxJB^(}pPYx#CUj%0ngJlYbwKmcpjU(IZd`S4m z@>P*Qp`o{i=${7ncf_k89%O~Mu7&aV&LL@y!P6%QY2957&I~v5SnL+j`J3SS-eaLN zXBHnwN~g@X7bd^846VrFFTnqyUjyB-_`p!CuIx}}Kt^kUhCF;Unwc|-gX;|klbvKR72oE`Nl=cFK}_mns)jZLb= zZ??>oK)2*z#xGDa(Rfb$2pvSk#G4L;8Y_<+WgdO0Nc$jtu2OonW1O-)+|@mh&Mcr&T}m0 zK!M~Gt~W$9m(rW=b9wYx9Z1*dVnniivNPsyAk=c}$vluune$dvrDKgVJN-t3TQMOD z`09;0t{sxWpgEhojl*f*e@5fo`Ng=q+}!exOx&-7z9&p_@|WSUecIP%AN)+dH!L*A zG8pDjX!EiiLD$H$?Kg$>qr$o=5LlLZm|ak@A&^0bH`F)hNUhEt8l| zzQF_M%*)M8u6Q8?HQ`oxzS7k6i}*ZK&ZaZJp)^Zi%#0)^0JEghn4f-k+zh9e%@!yB zq3&$4dn`d1gU}lJQU2DjjIoN0KoWE>=Uj@;=>-KDIcSy`f#0(x|1s8%jY)q^K1H(8 z@PyPgYsJ)$l!g{3zrQZ}%~_M*&z-o*w~hOS$(?1@f;;-(?O4h@lba^Htpp7`r8It} zRgWEBY3-XWA|Lvl-@PULdunqKBaBClD3P;~J+y4Bs-six?op}&Wo=R|=G&1|MMvZ> zt3p&+BV4KQIB6K`B91=eE%H91dL49G8pe`s8X_zoVmu9h_BS0@g-juTb|HhD)<h)Wrl> zz<2w7#2zf8E#y?U-1O`2A!oc)PK#w;j*xg}L0IcEm(nm zYLE>V z9>SG&o1$CwVATV++M1oGX{T!c;(4lbeoihUG^d$9DSWmh&!~BdeqkMd0zh5Bc#1Sh ze)xk$7X(z(Ar8v|6#}E6ManV9eP8scopg%WNAfueBM%1BJTfO57d29D!#C^~$kjT~>cDi<-Ys|R+;}Uv zfB=Z>L9gC|7yejWN~Vs`iq7I#$k^u$t@DBZx!GKoY;hFN;Cb)jMIuBcHX!3FIyK5} z4UL{GIJSVdNQ4MT@LR2*lBIZz+qQ=e6|K>u)XFVE;+d24qIQMcNqL6{+v9oFzaqqKIJ>Z5sX0#qTVQ;lSyJeyaxziLMxA^#R6TuCJ z){UN-bg86vo1s@mm1{Iie;}SFIMAdAN3v(c#K<;ys$6}xxVwaIsA!R*mT=_=r&{v< z8J7sXEgs#Fn2MD$u6l4ZG4o2l>Hb!UKCaJ@)N@5*%fK~7H>g5)>UxwDk z(o&kGGv#KjpE8N2+;%$GM;Rd=~5pLa(O9NcyD-3K3*j|dO@#9ErIcJ5fC2OpKxcJ1tb zY=8Vk#+sk%3vf^D{uEpMz_0`2UfL5X^#f)VdLId2Aj_p3%8c~8)-48X-0B#Lt!)%HV)3$V9&rzZdw(StmsQZgKi?kF zgK4w|o#yoXMB2nEo$nBXBle+w#`Ze7k6qA2VA4Y_^$(*LV+fpY9^RHX%4Y#$WPtS6 zLan)FK<5A<4j@!iy5b@KTxcFn_)32fJlYaciy=45IwgKZNxt>$-9(nzVgMaOCoHcH zg*@EDx~AAynwowI+-V7ip? z=Ubn=Y0&yafc3(~a{81~Oc&!ffmdGUDc#mM{pmkYH{FUSi;f^MAq-iBV;^yLVl2hF zne4qB z7116ln#DM7L$!~H(XS*eqfk$hBtbi&C%_t{oK!BeJoOb&gXMQ{)DyOA>L7mIEGB{j zmI-q7ui~VFqU~y8;V(31=``P}0-ohg^DQ?Hul{9=Wozpj2Y2kiq4hFsu+_#W6CDtnKCuSssMr&bwRp+_vlRzC(RxPIl2}>9im{+=&P9q5JOM!}&F( zhl6$M?n9U)LQz`YRKu7?4Y zIcf9`db|(4^fIh!~I^EIciQ zOAZ?&jA`$|_rk$+YA#_5qG~o4JhfF&Ujs_?s##LI8`{5S2x+O~aB!>Y(l(nG&{@yb zQir_?1iakUCB1Z^98Vv6%;2kMVC7nIW6zt5C6NU!HV~`D#jlbSX<_hDmtGBsRv1`X z%I#Y#yci8(KMsH2HR5l^_GqEx4?i)p9a+J@qxSf%iIC{*v8dkz=0l?vW<$_m5+*dn zjxhgsYW>WSYKa(@KZB}XSoqSj@cyq-&wlvMazCoP_OT5(5B-2Q_~ZHEZMoJ4_y;|$ z7OKOaf74B?Yj-(0rDNZ-TOV7!`Ifux%FoV^KWyA%h5YE;Si<;GLk9EbJSeSX4nRr` z1B@PqK}F-pFsR7ec)G2l+2oFoLl2X3L(Ltut|Qy3dvL_b+-H{y_~&|kAaYPoifdW4&Ho=Q6( zSf-tU2hEGb|11yRn+L6;;MbQq9*#HT6F3mXz24qFjYLOXQ={biuPC=8MviYNV{$o_qK6ZQREgRh{dgE@sX zUjOL;l@)%1lgBAy<~JaqB|K94nhtSM??RqX(5llN~F6US#PG#Pi;6$d110y?|a zcxuFz7s0%kpk;?}3a)Ooi_;C(1cWbIKe;WICh9cNB~_=cM7|_B=9wDx+yPrJ8L%D% zpDKwdwHxohmjBWJ+6OoHV9n`;_uZaU6kehdp_|@JgiJ75Jk)McY80w@37&eSSBTmnl+0)&`1N6p8rqVk*Fh7zDO%HfXRKCBzm`o~)492_ z$-WXY+C2H6Uda*YH^y$!u&376(Y0$Aikg9&L?}G1X?-l@j>CB$lj;3aCWTqamRD0R zaVs4RyxOR$)Qza3z*vT_tuD1~4S|=Hv>+zL`*9nc$o$b*fwXwtyYyGU*`#fxc^poL zd*Mp6>bre4V~VSn&Mf>OouUlKVw$mFOhXy2+j5H>E8lC?@#zm&>%UMD zx;x6>LZ8<0uI*|3rrx`f zE$v#Xf1x@l&Cz?Gmg(#(bxs0f+eBZUyg2$zbaHh9xR~kVM_7~g+V7a>+KJ)QiS))N z(|GCC!;pP(6y#cZ~tsw)vz7r?%<;5LXET#*jCdS;CZ zSC-zip6k_+l^}u#%OJ-JyXG(*5sRR_fs?(23WdGv!1; zAD_Rq1Ht$&QBbAs8>g$KcW%Q z7&+F6{=(&s;))N(plOk%e+DVYwk9bDq^x!_sx<$0X!HkzBqai|@*OdohoSuQaXt+ZbAO+Ia= z`ILEBq;LuYcH(HYV|iFU;Duf)imPxnVW+Y3Lg%UX6N^c{E)jq1F`+0sy zo8uvIMuF1wi?{Dh&bX?5d16gGND4uPRvuf7G3|Mduvd8+xp6j-&UBF}04F zbxhKJnz`@smf$&5cL}9Or_o;Bl(vnC?^tRPPEEM<7jG5A2J+fA`2x&UnKGP9^>?!7 zDXZFoe{3`5;N4drxa-cH{2Mk$R=24!z(45C6mLh|vCA9iz3s8W7J6@cXbYsaJ(L_S zpc%G3ls#;FXz^#*_RteM61Uj_1y2FStp;ArV8cp1)sm7jBdMfU#9kQbLA^z?%CP7XQyeefsS6j770;45H9 z5;+IFz5~Paj-E}_{1JLi5GORj(hPVwF(>vcF4hLp%S=zG0=z;MP*YTTG304YrK-z4 zA(LF)^RRq+Nwefg$OpQTrzBKTc|FuGd*=p5L%X>>FBGVXT+v^#%j{OP06YrtvA}Fn z#0lPhEmkeRnihX(v@!j8I7YYh_Hc?=M?I^qFd?y`=UKFEQo=aYKnS>6d8%>ywk_>zek+&!-R+Erw`G%r3Rk=E-V#^qIhY3cm>=SM0tIkKye{I>04)`XXxq0P*hFH7r`Mq&xIR3q1xHW z2vqh92hCe|2`wzz7sS~;#DvL$M%0Ga8mR5sbCd{neW<0)t&Fufz*wat&kh%5Ei7bR zw_cw@4iM`oIoMGWtB)8(%WyI>(g@VGpjFP}g8wPo{Q6<(Og3u0vo{T6>3C9jqQzff zuCFpL=oy;E&oo)j(1L=)u3S(-BOC}{>=6roTd?#Z36>XoM#F_A{i5RTixT4#i=@e& zVe4NsIVFB;0vavSb-l1x(@)t8+i=n8BfUO)1P9XB`iyt1SZck^t~yr6(%QW!7xD@4 zc=aeU`>mOIw*$h;_jToKzb z9etd+p7m{q_Uu2n%i+|ay?5&Nyxp99oI9gJ0H7+k$=KuCE}3b;Z2oh>{LKK9 zoo~DfAzs+wH9UzyIKO2%8bE&|tA4rfx*XxnM=3P1j2yBdkUr)PTPRz36EU9{a% zJCI&?;ldhlOLvgUUEJ-%+VWFoOflaZVE?Yi%-!+A&T=sC=6&B?N>$(qfd z3;p)!eP-@{OLd(kd6vot&qOLWs`&WSFw?^i>^->qp4EAkWAlQK{wept`wp&-@xgA7 z75+g_m{)aLeL2P0?dBQ3u$%FL!#M{of7!Ef8CK7{i;@;Bb7NP*>O9wr|(L zJ2V`~)!sGxxTFX8Zr7zJ5QlSyyAI$>gl2RKv5y>TLbu!sz6;Ho3 zK1p`sY5ln`E^a=`T%A;^A**_!#bl`WD*#$S`AfY>*Lx2nZa~f@5vI z@W3d~vwq8x`t(hO*2AR--QZcHCX$QEmX7I0};1>d^*I34XJ*Dgwj(l}Y^FFPo zim#B6@RAhoJ}*E@O=O-^MD~^>Ddoj`0+n_|9_^}D=4O3kC(qc2(%IB3c6v*ehh2@| z)*MqO$q14?3}esTjLd5~^Ciz}>EhSQx(vU*2mQq;`8()=1N@+#veh~*J zjf#ftBRSt8pCBX^`LFv+^{xLZ>evs+~55-kX&;6dCNc()siV*CloAbhB?PY}80B6(>k3V$f5?>-lzr_ZjR-SLR6&4?1P}t_M%c(hsrlnE1tVraat3$B=RiL!Ky# z*AdoE{`v4a!esIi-T-RTzo_F*>YUZq}9!6kKcx$c^ufPK{TE zf-5Iy=JOr#eAVQv_&rBNP|kOp_!a(}18~u-xwWBv4tdb9{8Lr5ThZ#Ug~CUqL`ibG zWYw5%UWaB7d@WGqwL6yL#nMK-FL|Y~(jLcH;O{C`$5BH!`RaWh=z4X!DCEot{SL0Y z9v+kz-M#2iZ?P()I5I{?5p^D1_#4BsNj4V+x_0W}$VJZj$?x_e?svusht!gfkT-3k zBNVm06L;SUnn*TS(qE+HJMr4N%+!RXK70b1NQRrs$Hj zCtvf<#is}&juDuS;pV88@zg8#Dxc9^+2s1k$1--9{8MXZD>sEh?S{$kI%hihIY-Vq zwFD`BnM`U)BA@~MXyOVzlf)qklOQNU6D#xAD_lwHu} z5jfYY$>V8((;La6Bm|;tisRT|@Kb%SR`fOT{S~hao-+B78=$q60J8gGBeyd3sXmX48w1c(jH@5er3c6*9WDV@W%-N$hw-g!gTVOgJHX*FUvGiyh&*y z4e~=sgKu5b;ZcmW#j1w)gsDv#A}H!L`>-kD6N7D2!u#tHWp<_-5fR_xQvf#BF@_j? zH30R?LmOLB`#bEe|K&-9N91@>o_lawG(mn!Ld918qn(|z!d)(C5 zONztrnm*6B=+g%H1p8x)+b%VHCM}0D@+~)G#<>a2Qs?GF>pqt)VH&n#j*zaz<81x4 zI~@O&!sGSFudd}aOY$>5^v>iK8x4|lL}A{YVr#1zKOC6OEl5c=HaYhNrG;ig#>nBk)3wSMTBUfqmO0DJ0bTm>;M|A1>hnu+91RLk%WSLGXtk=TRWRpxmPyMJPQBPu zhq*zwBRNI<%(dZ~eEUitjkYvA(8e4!r6IK!lh;nfB*&%F{F2G;!e?ZpP?i?VrtMi3 zXQZu!^I<7$o>@GNZx6tQ}jsSC6z9(vU`%YM0nysiqO7^R4L;26bEO0vZWJR|4EH z`NNfku^~OqjMizVUC@SyM(Z=T?#0NSW?U9Pqs~u{lmdXc*0cto5p#b4bANs$<~%6P zXqt9P(=t!cAGP-$SH;zqjx>@>h%9q)?~M2tBVxUt?#R_}{0bshr`*agPpq#_$d-T3uCqRBZPV`2Rsb)I zgO45YL~FF)6KrO2%xYEQU`yuiITLqELP*ph(H%i}YJl>g z&XDM=pk2cC(jHrPFu3C6??qcaucHjg^(>d9=KzYz9a(?7%X7XtJo|r1;eMd$v z81)4zXcoy2JE@I}6-(tF3a6B}wspO1PmNO#FT1qffvgvk-c{BE7sm_2^YRc~mTQG@ zjC}4-8I5a}_T}o`nf2n3eAk<$J=oOZBEp{fN|J0jsgcj{J5*DxMT(A5srgPiAYkp{ z`9a_X5A|O(@!A-nr;|%dYp8iGAN~<*Zg>9gMWa&P{v$}!W=QAw@3`(zYb|#Msg_$A z^JVxkwsDT({nyy$A%S1=mTP_+Ag)fuf5#%8R8xItK?@;kmCqgP`W0cr--x<9N0mJJ zY#b_DqpG1mCDd7J9C_W%>ao8S29U8u4a(6zLw5%xtIYAR-2-OvF?{<5+C`)2FDl*( z6@N5Pp|LsX_1Ulu@)N3Ieh|WCMdd;+QJpR6u;jvrvH&2T-;K&gnz3pCit&202g;`O ztQ>N=uL01LGc*tf4&Q2e1|1GzVm1nF;HN>IbF$N`P2P$pQwOT*phpWF_H)vTKQB(4 z$r6=nc#UkkAU2ZWy84SV=#`OfvvU@7{Tf7^pp|=ZO;gmz^%>8-(ExbS?0{FLZlkd~ zPKdL7uY8lV^Q|MV9+slu5*_smU<H-i!O#!Y9T?MB2Qu^6L(Y=C4jm zo;@C?XkdV-x;xcEFld?TFVc?Q7ZQ=4X)F7I)H9rht#W=valFr`+SO5h8&zC3)|`sc z;Dq02de&xWo39s2+E#YFMv*=|4jR^e(Cors@SidYno)DFlwqK?_NlZ)EZTnI%a|zN z^4LWA);)@z_U_+%|8Y!xJGfGyH5**@p>dTs(0bD)vV)IrlU~}y+7O&GcDLSP-!Qo# zI>gEO0ptzpRI*ZmW2+bII0QzyD?8`K`3~yq^Lb&iFW|sJ7hTXf66&3-?oK^U%3!n` z)sgt!FgcrFy{$L2u}PK+>;|1nbej(OR%(-vk*E{+?MEz757D{T>%K`Mws`2jLfvW2 z=#^F@swLyayC{YKP+y2thNh(H6BxN%)f;2Gy4`vdL2AFv$tNb@Pp}qT&-&P73+~bl zB+}c;3%|Y+pPwCegCR_vDbrt5jyCH^SR9>In<6!m<_cak90V^xex$~nikP{)K@JLT zW=dzJRG2L#79xA_i}`M-uN?XokwV53$RH7{BGC=G)bczzO^zRFqt@9`{n2kNR` zpt-1ocxFOq5o}4+07Q0g*XhF#EK;Gf==dUS`cz=Cc5Eml=y84=4>;1;QSC-ukn}6s zXNk1P7{{6*ZHLn|enDc9oZygJIB)$*QYD*jM>fB!5A@W@&}R!2y}l!VrD#VR?@--q z0!PUVzRBemNn)AfXIkVL@|Kp1N*8o2`f_nbxcUW_&h+K_1v7HwmwbN72V?I!MxmG# zN|XL_9+U>#j!Z|*QMy;zm;`u#!C^Q~GZ8%OXaUP9iNkij4j;@$36ny=%-gT0g$$ZN*&PJNKu1}w+w#8uV8lSyD& z&#RngDFZ6wxF98kEsP9Rap)K#Vxc31Qgu80yF^F;eMbI1S>ogQX$2|GnEBA6+N+B} zZk${nkdw*F_*GNXYx@-uPYj`P3{^KyN+CX{a#6Mv8${^-mSi>JFc|8U4Em?qb0;7^ zh=(9g4{N3InchKNdOm>(Kv;8kV(I_J5XMc#8NP%nFU;T9=I{0S`zHM&)?4#8ZhOIA zcy9n{wiRCjN(9~E&XdRiIo)eP*Ko?lV88uBgVV32j~l6++|>Eo;2bMoD~xJ#FI+aFz8RYW_@OJE*98H9o4 z+v@yAAOWR)o*^|~*KpQ25r=Y-U<}fTwk39&a8jbaXXF6__OLjxGarBs94NmR7Ef^_ z5fBycaqkfjiXTle(^7ENeP&nH_aBITsTq@92)bO5WZ)oq?&;i()!NHR0P>p3DWBh3 z4r~wr7P?(w#jN2nbc=rODjYvAFagog{ngCexa114TN8ub#KxyZC+gzN-^G6XCa!B zQxmd<`7~u9pT3kV)-VCpAm-2ID#sUiVZxBuCLAZp$!T+wAWRZRgG2FBE8@Mp#QRJV z=<_mto0Ga-vZLxsdq%<$X&K$wL3+fog(W@=D<}}$GIF=!dI6$MN4x%f+d-o;vwKE0 zUYlv;7$I~ue#5xN3kE2)S<{6 z0_GLI8lF3>rU7sg3_Qwl=8!5Wi&&8?KcF;!gYjkm0vV;^U4pdws@oz2#Y{0LP1(qz zl{(To!S7)#-!&MEF1NGXYtb~90Bha+?3{7cb$dKtCSixU&_U%p?vI`{anzh6n^;57 z=O*?ymI3h652}5me$gsc!tYJcU8;U#J)qv_CPy@OXQru9`J`uVjBbOYoh-4-0B@UO zoR`V*I0~c_YDD#=R0YW^QMG>sszOF0&o=MBSOHuu>YZ$i_Nsi5B^(m05K02@=KRgC zma8_o)j7XSVt;GoyxkvJQxIaozA}F|Wsq`WZuM}3u(;5M6i#VFMk<@+AQ9|^szvK^ zdY;mDI1qyvReBIpupQxzxX!@=u^K_9#Fo?VdXs&e}V@4?frjm-#BklyUX3-Yo zvVZN&XBktN;wX!cq`N307m=mba$dEn)cH$lq%Ep0;VhgnF(eJSL@nKAG4gmoWN_If z_1TWoL?wmiXaARDj%QwqMViFpran3gLM6(n01KSmrD~lkeeX+SNfn6jy|jWCkQ>>Y zT?LhCf~8DSHa=3~NjqsS!5S>HSy$sBFAX%-r#2fh8euYnG;lRN*NPr)T&r_n7pitS zFb;i|1G|(oYAE3Y1b^>>m#TqQDjhWvh?uX18B1<0K^l=!`;Na5mJf%Kt=g6dn${|s z@<_R3rS=Q6Sg)i=B-xOpkPJ=nVu6)AV4qE40-FWJZ*T4;mCke3_J$NRGPJQd zWlZ#xp??f1Ai3m3P}7SMH-=E#Yc;=mM#e__0HD9;+JV9QudsHyzYZfR=#jPth7n68 zx6P&-p|aYI6Vcg*@)KL8Y~Qna#!6nwIx(qAjL)_MdVtZ-kiKmzWmS{QG-7L-2XIEuuiPzPbgm%fbJf!5XrBdw- zF2cXAQBVja3Q|CokASka<-pCzU3-1DLGAM@Xqh<76e1~m*}r{Df~wOuR9z|hhCNsY zYB7eBi_s9mR2qT`1`@jeM1YRGZ-8^EO?6@e>dx`u76GRdV%GMCuq1|eK(Sov_F{@4 zE(n9{3(7eG2(}jpPg%(uMrpR5$OncIp9{`F`6ZFIU5G|sZGfK+63eP~q?d_RZ%{n9 zxd23nT;m9T1*4{BWhxaaZ&`m+Z_%9~QPALq$%Xu;*&LxAjZP{RXtpLkq7C~8y1|Cr ziovK_KP=-T`TF5uo(P?u zeP33xe5MGe`OEUR_StSVLlxb5$qo`&WkgT67KXhfD0z2CiZV83A^(SKf$81Ihn#;D zFr+?|>YM)jOf?Ywd>zOYQ%2NXOgU!-qL>iUR`{rOlkf7z9i!ZWB!N$qX~j@$f|vbk z#aUgmW+E3KGl1-5D90F9mGS^V4e>KmgR#_kgjpU^n5hma8)(j6!z|JOg@@iM;VCr? zT{R4aUveOpkj69*In|Li26)NP2S~9biTH7edv>rhWz`B!nPm%y5vjw-3$s{N${Y-J z8IUcLfmV2S%LDhBitrt`;qoI;>p(`Bq~T@%9x*J5iBff3LhZChrH;_1j`TTvY6}fJ z6wm7?FNmIV`sB&cU#^57?7cU1YO}B%_hj-sJ4HzxV`ng-^R!bIZUUb(8@1dLAstS*SN>fq;|>#xrSXGLM?d5Feqq zLq?}J9{LJi>hFQS<|lg7G^a@rw|o2mr3D5HJ$+)1A%4PHknF~eCG}wK7jZFrUfMrl zea7acF~@+6v@6;0INy}bdNSn3)ixC_a5-8JH1C3M#P>|i?)m*1t{=n1y5wsRa~uaS z_U$dRqo*9e)CQgKjFPP8K-+!FCXKnhi?({R=AL?hFof169U9sV9jQCsqg!SiY8$mTsMy0$|GgfW=cX8Xl`*S#RSu!tetqQs9nwaT448HS`{!ayE_KB zBzuTX3|N56eJmb{ZO;HoHNAq<`##n0)h!&6U0yi()-p;_^ZR2JI_h8#(LRaZLS#2Q zDGOT`F6n#NYulR0&vbVKgV(#7H?{Bay+g{T=;ESCwfr_qDPNkbY1WrNmHn*^JoY7BpgftYEz`G8fG-AVVdHwThVnvKpC%V8;FTk1>Kbo)+diK zG2siw=v*B5s5P$yZ5Y7Ixe>57FN1UoLrRv0V0 z-_T0|x-oxiGiwKghFbKC5;S1Phel&PQqjBp`;}_DLwQyL@o4Z=CyzjZTeh>Ci*e-(b(tL|c06uQ%iH5VRTonnaY)SdO4Bo|`0IE*gc+ zbGsQ$L48dI2{8m^9IZCQvp=Dt$x-@8@Ss%3IemVnA?F>WLB&J(*?0oicUK*d{Xjhc z_pRfHch>``IV=P?mjMWJB*}Ln$-f#TIlLY?Nc+ox`R)_iA6d>T{`F=OtN)Pu`uxo$ zBk1_4O=9?Xkj{fuio5eVLEl_w(cPIcmVB&Q7>dZmku+dSdD6DjlSt z1#a3OPaqM zhDcft4I=&_SX#{GW<#=7054b619h;0s6xqd2yE?Mp!8|E=Z&jy0H>S0xgJ1xdh`-XQmj!hD;5*X;$h>(=&1qTAUJD>5)tne%0L=* z9`AK!D#XZyTbt4yY)Gena&Fi^QRQ^jIO7NU!k}==Hv-Bs-ewC(f1pK5H+HdpsX`kt z8BD_=bMuPQJ>QH4yg)Uug0!&tDc z2aQcWYK^%i5i=>KGsck<8f#N5IhlJYbG|5PHX9Zc4sdk6Cp9$Ya#eNk!J zE$4ROGB9YJ-GzdG`Y8RfQM&Sh-=%!SLmHSAYHZ@<{5C?UjX9_yAFWe3hTP}}v-A0S z=pOc#dVtY4@Q`i1dX#1jnSA8;&FC5Tj}j=Tp#VcoI~fkv#!3k!vo0HrTF8TW9z8`v zI?L+sEMPC{V_Q>M89FJm*JLIc^KnZxRgdJE3|tp95UyZRc*xv?OFAysmAq|JIo$q2J+x!@*ZISxrasU8sJje3YF zfidATtYdnpbw_H*TbjaYT2q7j9F{9cxdtiIO-il#+2#HV#Yzo&7ksS3HXl$c9TyA> zAI3?_t}7Qq1V~D4Pg&n#3!OB6tI|k|G&0#hIvK!q(BGp~NcaXUIJ&TR?vLJaX)1m8 zQ<9$$vRDgpSa7w#hfc+6k6F(%c50Nf1ZI#FBLRf=-53$Qsa$1h(SKFW!jCbL;#CN0 zos#SY0ewPV@!nklB8PAqY&Vvpk8)~Lc#qpbsHJ(@kI-?{)~xXlhB7!A(^SskT65#S zeRi=fI%8T=o>0+8N)pOajZ}T=agCsK*YYlld z3fNlGRsKY`@sB&oO-pCj?W2x#6k9zm>>y5<(>O;^Fe_2&^OYl8h-s@roO9D0VkQo- z5I)=dxyg$YV2-9`=~V46jvk^mqoySLw&-4q8dQ=P_c!`FQ@#{A4AG;m*Dqb{#L&riwxQ!-Y1N*aEZ zt0#C-rM*SGB7wZ?%-Kakf#FdlI!~gguPIzn99}FIM6jn5m(~MSn2+H$K+9A;pdk13 zEC{?+z{ACA1j7NkhN~%ydcB-QYZdXb7SR5dDOL_^!_A|An{b{e24pF|q-|!F7d9k0 zTGLMs&GW4b`R~sfmo5>ejl*>$xXDHxCzuqV_D&6)Sw>0 zGWshZLL7TPQrh;+JX%ov@q(a~3AnI?`bipxQh0Z7&t(vkd8$2=%0Nnaq+CiD_GZUy zpeLgd9C;Fo{?3m$xuz;8QWzP>3OlHV+VUJqW*DQFmw12++#5iYNG_FaV#u^WNFj#% z6O{CTgr|4~8Zf5ctZD~(_BvP@hzGzh?s$k!Sr00aM%7f2MDUMY#GxEOnf%23jRyk4 zp3KGY2jgu7dTlH2yfe-Is~SfU6^o?8Rf;`=BI4ceiqEJv7{QRj2rRo}HwUP2T~ZQ` z+89#9!T{oi^Pg?KAz~<^#QTaN?9^-{qZmPcQ&e>J^p|F^{7Mzkz^$N!0v?!pwmuK% zA)Ii%gm@PuwsN?y$mhfP`}eS8R2vH+=PLmuud`p7EGi?|pI)xtFcbZPn*AxPtG!4R zikdJRJ=BST5J5gbr0J~HLQ&tAO(mp7iy4pCfIG}|j*#-p&6-w&;I*Tc zV!@#3WI{z6GFeEdbmXHF`mkvH=Z-0*`Cm3kFDZSoIFCj9 zP0v;alIVe#!5v!OXo6k;E3n2A)bwDINuw_uk$n3o9p~+!1E4P&*M4?AP{LWL#vA04 z+nbdLA*_pBL>Ldy8*8VD-m9%{>Z4GK*5IKENZ(ntL1m~C6a4gu|7so-wEs-P-vQwA25gfK*2f%xra)*aJCn*Zg;^Xg9+F1tGdSp^J7^IV zytN(xqkrsB0nNrvWP{PE;sLO8^&m}os`3;+xScQHAu;3BD~(spbl$=>bo~=@OIr%{ z^;H#Ya&rolTr~NjxNrUHvB+Y+Dmxe?7rw+oq%T<^q;zjsh`gN*LS(s0$f-WR%Elzc z!XyO^s4SMo;Gg<2^DzwJrC^jf7tW@XRTPfd)a4}+WU6LS7XZ>Fo?LLlm%GNJQwI65 z!>0O()O;Qx#hCIP-bmIfG5^tH3a?Yc%0(s9v|QisA-)3Lq2?BNLIcqyA)Bd2cvw?LMP2f< zDgprHRpYv-o7JHKKBAWb8Cq2;{2K@%tSXwGrhMeQ}Ff#0#Upx*l0zQ zj|^&A)Y50|fjT)r#svvHZ?l56|Le0(any)PQ1N6nkfHc+H5jekmIYvd1%OBseUPSd zP!y2_({YBr4lD4i1s0@IS8Ii~yVH`SnEHb0;$k8ezJPst<*2qDN6T6{zF4Gl9+Unm zq_584LF#k~6cL}M(2w5>5jBacMl$!Zw$;^g)_`ZD>qUI!SUVknbqdiPH6-**#VE8ec`f|QzE{}-fSAAEd+WjHVOX{YQUclIz zF7|0TAw*rYc$0n^D(ks=@G$es!vnqk$TKw-CzqrZ$Ul0Y!V^dj2lST?E0~LMK9&|a zN(2+&I6Kl_KSsj8^;_n?-)=sFwPB=Br)GMw0YLwWzOn;i214_X3 zT|0=J+9{8ednzd!U|WPV{BrKQ($|wNeqX7FaD~)h)vab6w^RYu@6k}88p-f zJ~{WQK>V22+^HhGNFeCnBJX3ihOMErGl34TtZABQPW@M9*sVoFszlnIFR(`_1P}6v z-{O8nch}QrJg%PXC(F=p7x*X!11|48Bbprr#6#?EmuNY)mkTKIW(8@0SovI<4;h~~ z#`L;+K!357Vvc5(>|a(upvCk>yQvM*GbqON>#dw*(9!Zt8|KMM9dFWakJ`?k;WgN+ z_KGJ6v7}sMhNqbwq4Czk%6yo1%Z&qEV$jnC;-pl19C0d-E&h40CfC&Bs+XB^JTvBS zWl@eBLHdkr{1Rfq#f1QbTJ(z&v})qltr(GH*~Wdf9}IFi4_O~-NrQq(e&sXl!~|81 zsG)j|=Aswt#g3oY!itfHq3Tr3HE6!_#c18Rydk2$Ngh+;iW~^9yOk@ zU&GFC4(wPIDUfF+Gi4Ta6kp7piU3D=*1kk|esA=7hBym`HbZ4JUc!v;hL`GNJ2xH@ z);x$STPTOFsT|Q-De+P(F>SWqJ`)z765FP;EZnLcRzu~hOR*s%a$=~X#a@@`Xt-e% zPPv7vs@*qa&dB8Gf$MUS=9!W9^@5B{nwyxLQ~i+ij!U*KQ(^-T#6`g~024Jba;2)r zuUEQA!_8*c6A@@#YZil0om}T4QThq9Jo=1=z3Gb+AyQ#;Ip;X>E)vMee@7xG{k2fQ zgeAs1IvlyJTWQ;Uv2)H4{86;suo0$$@6zHtx*{}RTsaGQf6E1vH^pmEkU;-BGiMRf zU&KhtM!{`|wekph&JZ8~(t?lki$e<+ssz!f?O%woI8iB@whDJ-)!c`O3z|a;%7@mI zbkvpKQ}WH)bMr;ClXAL&7gf2?8p=NPCTRyOPf6^uKW`F;jRF}HAri`Q_rRZ$!A2r= z1z{EMELsVjv#v{YveR{0nna0FN0l?X9ZF9yVxKNj((wnmn4A; zOe9)ev;jnvkm%LMZnb0fuFc(&zV3+c)PZknx}>vn+-^{ti!GJ0{7`2#CL-8H-W=EgQ9zC5JH;VV=H1L~>&ZP}VH+ksEbu56ZH%S((< z@OMj>rzVNYaLHW8JSk$>o~dVTrOk^aA`IZ13}s~0Hr3W<*-CZ7kfyqBETaPQ__C@elYrFT_;?dJz@Tx9w25m&*{KrS zK+;y`dLwm^b?N%X#8x_g0RZ^Y_7Shm{uQmza1WfZYeCLUMac`-PtFhGUP2BOJU{{l z{%(^iz4%V3$>gu%^T5{n_^)m^uq8ZEwXvFzgAy5)v&sw7$4PJeme1LsolIKYEVs#T zDg2DInv0ooL2(!s5E~}{z()}@2HX?4Dg>>I$l7{>Zplt;YPwBF$y$Ih7iUmn3Uru=%=n|#1w_gh4K(44=*eOOb^A??ok_&|%Brg~O6}Q*2W6+}e z-GHva`kYjHPaK0r#1WnVtS?DWTr5@UnW-Is*N9?T<;xtDhj$6U!X4a^qum;JIHod~ zNwmg>=jB-tqbIH2sSNB@lK&+i{k%>u<5Ke6LLwXUmj_zFYTAQw%_Dk!Pp~d&!(!H> zg)Ut~Wmj@)3QdqpBF-Afz95zLQlUbKyHyje-mG7kxhgUJgX*_^|8k5K0#QXcXcrgc zf#S;INsu=8ZI#2!9_;NP)uVpSQk3+(4IL+bz)U4{^88Ww8LZPt2PAk4GVm*iAhduA zJCu!uhlHx-0Px-@ye#@aPzZ`lQD%B7Xm2KZzAKu)-YXv6w{T_oValX)^#bJM8 z=oy9nwOZh^aPF+E10=xm!jxM%m|6}t8I?u=m zGpv-1?(UV7-Kst0waS38N7RQx>BH_r5p76;aJhT$5j7LUD-tYxE;zs=+P#LgUY~o6?Xdir>9JQ%A@JyCO>0XJSm{(VH61LrIY_=Lz>T# zm(d|KpxbNKh{WWL0!iYJmvp_pm*>(VTtMz!Li6=TsD9>ssA)UWcA6dXuv`+}0>Rdy zZicScq^~8->GO6e!toXE+Kog^oMfY3KlwKIgEIFBYmk8m{ASa&G{opG5-JC_O}=(I zug%VLX3nh&a%mT-Aflzwn5twxya-%ye__e8{L-T-tT>h~!D^^f^8b1m>?rAC&7j~@ z3fvlorEuxKuw~^aphxnpQuU1`cTHYa-LFUWg~^}95|WVBD(|{iX*u&-PtyVQRLuq1 zU1UBsjLXwb>&hLTv2vmaQ6LHn*E!(&$HG<1s5fEb^u1aFzA4RO{0xUr&5-8BiTh>Q zlfJITPF^DhFuG6lvBca9G%*BG^5(LNYUJ~>(d!fGs{t6}=x~sE7$L>yB>*;vkeS^_ z1^6M+E{?Ny(b1>|+w?vO-XZuiRS&A`gww5wr%r24wCzE~%W@09ru)E~K;K~ZitI(F zWo-D0rf<-^S-OGlnfA=NG>+<(``TOMj%?-k#Dw9oA`i1#h zy1q1@Uz)$Smm0d!8!P8pfj~~-jz~J_OQm+u8AB{3msH)x*1hChih$`AxQ1!tIKN=7 zC_Fto=$Xe03g&eMQ+Py`!qZf)v>i6Btg`!yUM;)-(8%r^X4p-+449udGR#%L{NxCx zmSI@vK;|WDcGq|=S*yL+eUcc8rfb3VTO(YxbzeAC$2(s&&tSiKEv#dC>^jCnH0y`x z?j$XMNWC%WI49DkiG#AN+jm7nPj4FKzjTy-bEJ0!yl9G!Gx90VgpWU1nUBO?^S0z} z@+#AnbR127Z=PH++x{TOXVd;ypN{NYay!Y_^ zckJ1J`yGe(?tIRkgKs%>*WEk!9K8GL19#oIlYiG-vvcqM-TMyTx@YH}LkHKaIrQec zZ@=}L-9nMcJHWMOy0B)t_J!*f^ihR{g=rd0uH0(GvUfb8X1Wp!HYa=Yj92o>i>0)L z7JjfLI49Hg#L-y+j<8Jp#Eg!NjsD^a`188F>cYb?cpJ37YwbX5^zo!v^t?Tkdr|sp zzP*LVVcVLC>&cKshN2e_cy$_jM|G%_fnF20Q8bSyC68ND3L6!fLG@xT0*dN`7DA#P zb9`EqD95c%HA+H8%c5a9>aQj(=s2G>BS{)m0AZ#b^fivU0;JplU^LR}x;0a7DG-9A zfOfW_S?VarN%n<=MkT_%zF4J7Btlz3(;h-i3N2>U3K~rC5CcVi2(PdqRYqX$hJ^q@ z#5<@Z@ zS8r!!cT#?ajwy+gGUOWU?v!ACWOoN5qXvxDhb-gtD0yh??u7COT-~15YYT`CRVe}y zu+1C>EK#l>lxZz#;%{>*8`Z+=+e+X2BGDRsF!oh9H!tX;1`s91+!3ce+OCh;-tG=W zO&z=0V6Hc-)IzL2rM-&LmFyCmLwe%RU%2ZzWNCOqLbL^Uc+|7gK5upr4ME7&b1nAD z**ZpUlt%~SC{#|L{{KB)>SXP8#(%xVCq4U^!>M`9K}HZX@um*6 z)d0f6D9?2^=Y)Jd!^@I-l3?<$x4DloM^|!sZgr}-r6Y>Dx5BoNio0e0dW7R#ugZ0+ zPryz2pvn?>%`IYgsP9x-4Gg0Tct1<{)!k@~*$}^2+PL+HDu1nn3*O%L9WTkEUrF7H zZqqJ{P|1=(gA%6TWyb|sYc&g#zp*i?>X*H9@q9qj)YXV4W$7NN7fwlgZVdHWCiQnW zFA|sw{>+QtQ39D&BFvw5QO1r8u@)V_u^g#isuYzm=z_I78T+kF5jTq-3Rs4xMi0;J zdLjqV;$zC7Pbg0Rj8ZXB`{#T%6yR!c?1U44?h(oKIRn_V$Jj&F9ujdZa1*W-B76Q8 zu&fF8Rzv4BzH=r|irObkUJ?{7%G{t}M^0}0T6gYOrl4!KBWp@xL;|LzvLj^xSt|8j zOFKT6hbf^WQLX2jF=50Q)rNI=gjP9U9JUE6f-5~(&x~MtI2?>|va3r%H>LLUq-hHb zZ{bo4i)7~SzBCOX#g%kmSJitSxPL4+>WIR0o~yv6p5Y5SWF$?S8LO3%G9Tn*AGer> z8YPlxX175{-$hX4RYZ5CHr%L-2wJg`6aBe_!df3HYYJi?0Y*C~_o>;tGu2GMs1u?f z(S};PTjzE+v!^Mc4MwLE1Kvt6>}t-~`Q8AGMFzCaQcuw=hfp9>wAb67Xp8!k8*E~S zs%f8JkwKYk^U|?F=&47PctH)(-Gp^L(toFI1{d<660lGDl+m{+-wT= zdJ7ClkcNx^Z9eHHWJC$J*YcF1+E@05k6`|AiC2hf%l63ilYi@z&cO&x%t>s8-XqwQ zsUpsiP&&qxI_S)`4?$~OrO*GfR5Tfd~o5j`|CP4#O6Tjt7t2fn2#S3zD zE;vcleW+S(9gFyT!&$DI{Fr-FE2x`q2It0|hUGkajeM%-5VcELRzqaehr<)n=1)m7 z*Cln~(*S5+IukP+>)&t z11>b&qt8-UyPEEt5%|$?Ea}qH1@u>PdJCglXje9)6JXo8w~KJ1b>5bzX`cD5(=M&w zjt9yT)XFJVRk@b3H7@a1Bl=gfnp-w$R`Wgj&_peBjbnVzWYmxy6qlBwzeQbp%E4`g z13vpM8}TquFTL?4L6{MQwWITP3B_|1iK2zO8 z0{g~Tf;Kt%*RN5u#KI^MM9&I>6;YW?)Er3VUe9I%1rzcqmfWlZqiEhhARK?1JPL}jel!~E}i_K zJ#`I_0Rvb}Pu?Ua6DM=RoRC0(kc0pM znM9E!pJVrCL4|3F46d6c3 z$$K*y>`J(?&0p%mSQNd(_Y)I8QrK#6lsh1({m6+s%3NL+>i zFjkvQ^;ktS+ALC}#_Q0aWZnMQ+sF**=ocNm)I+Z#5GN|6>f|01PX2yBR={Zb6JTH^^YkY>k16UOb5#s`Rp zN>-76H9^78p)@=*r<|tLTD5STjx|(f_y>jq69F$mXz2;xbKCeMHyM*gw{J<3>_Bx{ zCRHF>?@H-krVZKKl4Y6;b4)a2D_6uy$v>t?HlKN^mJw<_~ z08XbAQWYU_w_;07|W8)#P_y6LY^Q~jD_-p~y+ zeQ;R}t7u5Kumw(S-9j$wg#Pha)7ZdXxcG1CmJqWtByg`Jj;mp|x6Ip9kXbyMsxNjy z#!fYil(*UX(8i^!HKA|p4xLwTY+mGcEHJJ6(dwBbV}kzmSd&(}6+Muib_${P@ia=p zGQ;y@N)_LfEE=P2xN(7%hkEOPy$v9?pU~}=M%At!_ey@-4v>p*L*z-g^DZtKd|Lc& zZ7PH4EZ6h?_4qj;3bkxV#AQlZ4T5q6Bh@Yva;25(%J;BQNfPeA^2BF>j%3L7r6sRj z)$6h)C34ZG)p+TWmp-|Yn#I1EqFblwbbL)tK&pxPAtZS+Aycvp=q)STn^Jp2PSx-c zVp5T{(_^=k)?D0D=$zz?mbEFrnUiW9b6vB6ERr4$SFxE8i@DLVlMC%@Rv(_wVi&6z zG-8mUQ%X48?PM;RzuUSeGr%RO8EDm*>y-Xo_)>u-iYo53YI^fTv!M*c63F!COdAqb zFoPTjUl`7DLcb>*U0Ri?&5z7WSAY8aN@tSJ6mSBLlkMEB#`hy6qMD!)6{wqOB_jAT z66UuvXJz2R`4OF6^W2$}vpaf?Oo-DfahAkjuu3dPr>9Gp#3L6mqeRLejSpdRU63V1 zE#e>(NFh-N6*VEXZ6`igk7Md4OvGSy^n#8o;Tdjxz}9(9s3VSGj2y3yykfK|{_v7l zb3h>k#CE0(0Vdkow!BRL(FXw3FDEfOqDuy4dULeB=bRy^102r~5u&}Ai6-`m2~vg# z#V-#?34na!+l*ATR9(M+L9@F2rUb>y?~G8~s$RXf3&_!gB%oCX4g7&Vv6c-Wsmoee z3Ka>~LcxL=?v|kgVsHj(d9s9zq5iOnl`!H46>>{O?k8Ldcb;{?@8$M@2E`!|Rde>V z5rC(anUF?DAkLvDMrql4Qy`|oI_Ye-$mK~bXPJyd@>W?E0X!{+qt8;SH@_ZzW;0=#;o{cNrIRm~A==LFM8Zl=PB>KzXoUQO=X{%wYnioul@^Rjn4~ zXZdLu4vj2HD)T?ceLWwL3_0>nW$e+o4>mJse5=8W43rNnZ0ZKdqi?zC#V+(DW3#w$el|xFS&Nw-sTYK3hG=g&gR$UG% zQO|N-Ki4;s0UAq)5)UfqXVh%wcv(|EBNa~C6ixdF@5}S`#hgq#!^^t2r`pqI9RkE?B{rv8a&q-Ais=(fqPQ!iR7(?oDlk&y<68KKeuN$s<7 zQO_BbNxZq#%eFv8NgQ079VYRBzs#~yzo-l3b++8fAu-3#fdGky;nO5_V_Ja(#b%ef zRzw5|qOBWC8)UGRSuJvU0bvTX5zzk&>|Jf9JR841?e^FyQ}*xMv2$#lZH*n? zyzjcbBV+5fm(8)4E*QAz$o%AMn)O)0bO8m*vCMD-X*1vvX|y=#H`BYtGns8g~kh?A&HM zhBt25c>3t+r=7Fz%yk=j3hdl*)%vT4hkMdh+IJZDHr#JV^6rrr5SpP7D6ikOWqA9J z-6KB*gt6_2Hnwkc|1hgSc==A0>a>y3Q8tPKGgLtMhBnQt6Z>~!`xF#9|Em2vcJ4cE$LT~O4iY|kB})r*Z*8q(1txkvn*9Qzy&A>TDuV~0wl1dqaCB==!&69Anbk*7kGm` zI(wb1W%CG2^xW>Y$BX<@yS^`4u{y{g>3Ja=Zvv!LI4mQEC9B(9;qQe?G_7(#Jzd2V zFtiK*JV!j3Hr38kT)GfkI94M7hf;K1#}Y8?%0cKT0h9oe@kng(FG(g-pe#cK1b}vr8u!2LB5KnZ zOxGexDpZ7_(E!qH+cxU`rTCq$=^C^|iu1A)qG;7E!D*)IAG(3kh5Fx8efTJ*gUbC~ zO%(E|d*FcbUsos~oLTm^d9AtP!1=`HYZ7C>5mT*G+X6qqf6cGi#si3)wGKov9upLf z#e9T>JEstCi?OOE+40sfF5#e>e#1%$9_J0Zgkr9HF*ET_v5I$eNTw#8HKfR_03wSEjV+vkjvv{4Qnigz>~P3dAwi^w1b65gMAjNxfWX;SGXU%G z9v3QcJ&%@7ciGjfsQi=QC`Xors_N+&Q*iL~(0V;#dXKo4=^Ztd(~p-?H7Qq zd*J*E9kGYdd_=?h{5W6cx8N@T9 z08<7JuI+n`TmZkid1peO-T*wc1TrdqM^H+by<1zZEI2^9@c1ezjXvU+RueolR%3W5 zlJ)c@kgR{VDv|@gk^zP9S4(SoAC;T6FB`3Z#a~-tG>&rEr2~M#crkbGpd^!h?+#Kg zVk!x8Dkv;X2Ss3XjKpq^g&C|8v9ELzC0`c=0YTps&32l<^JGgTdTn}Bh9=}S6>&lH z2hwy3&tnaB(*2DU&(VzNexae(Ci`Q}wzQ~@PK`r#JF`vFU>yE9ss4)M)Hb(DpX-tM zyFu$GSj+Vw-`Mx)LEELxH?#p`H{b98GF(Y=l-q+-qdoP31 zlD+rZz7)vBC*`xYxrbd{;`3$Ji}15FHj!;@if-!P2h5|=hdFX7`tYBtKKw*er9K-&FjVYy4;%URVi$BmpXE z8$cKq%3{(sw@BNl*@TpRRs>+^kz8ZGQ^o4{Dj#JFN8eBSyuIS+H+wnys^IA3h&O38 zy*b++`Dug83>mI`uuU6Q*;wUBLwL`&o+ZY#ktjrMWhHw6XcQ`#-A~MJt1$aYFJ`X` z%Czw)GXH?qGoecx03pf&r|abuuGtaQ^Uo zC@1K*j1F&)FpQ#BlZ)OQT%7CSAEKLdfUShdCP%1J-mWO*&5=J#HA^KaTgFTP<$nEC~JPs?FsboJUY*qqxwM( z83h}<&m_c?siBn#p3E~XjLsC#fGEzK&k%2@n+CVfCarYD#m6GMx-o1jD^9Kw(zLHlha6HYnT;+iBu zU5s)xwaA#p%PR2->s0@8hq$aJ$}~19=``=LX$88Qh0C<}xaKY$b6wv2xz?ALH23_f zwYI!@mr~|Cnnp6TuLiO4grWr0f#ZM#BgL8McKU%pm>XrfB_o2`n;8 z4mq7LE^0!=?U?L0mf>sygnq#&n}jS{4hi{BO}B{H!kQyy%{wP0Xu)58yaR%Al(k9; zWY^dbdb-sfZe&s7)IvKok@wC2??x6N|nbirbzf@R>yZ>%!!SkfyioK zREP9wS?fBdV#i5yYD}?C@k#e-{{IB8fUc-dtD|J5tm;Wwd4Lr1vt5QMr&YC#li5S` z4gCvV-ArD+r-xUy5LYrPAXH?nS9W|~0YA`TJiEL|aUVBwhz$!2Vu6#a15sy- z!@*tXC#Ecns*?COcuT=z$&RrdIqcxCb(M%bN^f`VI&WLM9yd&BU+)TE=j6o(Yyd2= z7!`O2j9Wr>Z_nPXvVo5u`mqjY$j(})+5qbG=4}R!^k5@{&8M`pGMrQd5tS3GtFh<7 zY#m9+%~>QN{HQum(!NiuEQc|)o z-FS4Z!@;gFLny_5B{GQV3g_)gcZs{-Q|MO^Pxc8Z9wFDgJAe#n02tVaDAIh$438r% z`;~##iK)*4M@W`LgXhB;<6ngfA|1vyMv)V8UQP3 zD~erz2YdQjbIvEU4?u{mw(Pp4=_(8Ft=et%mi_?+=f;9`Wqjm6(7bo#FSvp-T@uJ8 z7}h81_zw*WCjBi@e_IdgB1t9w{ZJ3~Xu@b~ijq#!ZhUk_Sp4=IklJRRGH_yWf~$6f zdZKF$SY!zj_~cI}qH?iVRY@-oOY4*dkw}yxxr>ehQ9j&5lnHq&+Yi=)3AU$<;E93^ z4O;V&Tlm@M-@qRmxp`GLFbJ}ttX3nb;Oub+8(0W=0AVna1U;W&3ElQwY_o28yWJ%s zj}rYNCqS$0sc~`^pL7U|-)U~w=A|w>5At!$ zTpOH@BV8+3q`%`xBoT0qol6c%`; zKy@3YBUKysvW-{ZcBOu^BJ~ECnQM-Vj~ z$O2U5RBnrAD#$S`v1fdr*&yzj0I(25Oa^qp-+UL7S#sjSH_iQZTni-N}& zvL^K#RL26BBNmY;Ko2|pl%qk%H+R#KT$R%UirD-IEvj|=GFJ|n%rV_?=!5rj^0<`~ z3vp^-wu``gv`)sO4dNI%l@5QI zRQg~2sU%mL!iG(a;y_3*PatSco{>$Ybm<^!$$qd#zh=p z&nFl}*Ir8N#S*2_bBnKVK=70&eG= z=-!zUS1i~|b+E74Fd4w!5))VKN#XwuF>`dYBXKNanTa(E=IE9wr$k#R`n@UjG`RA@ zfi(od+gcrP;szDK(;1X7GSEZSplSB?V3D{|vfX6gi>LP=0&1Vio@3U@5Ex}LmZu{m zHU}v1QlBp2A3e8f7}%)cIgN*iT*?5(waWprgTLU<6a?XKyzIp)P}J}o$0DQC3M}w=M#;yt9zKTIY}%1Y!$To*CgC)D}-(WH^tgAH)CakA-Er zyRuA@i|j|(Pa%cAlOJwRgt(_mE!aV<~>ej)KO|ATF$ zU7;tz99Ct9m7wbwqJU2vC@0RXnQPA~v5}!bHOz?!rU$B&Wq8dy;bW_zPK4x|iJ@Y| z@_y5XvuO4r>5w=F?A6?j5e&0DTsH?GzPEtGI$B8d)IN0x?6F(l+WtuAKOX_pwTR!N^F{a3E5>IOO>;p7`AD*q zJ)UTwR$-%atm(7S*r$#;>aWYkLF+f!wr5FAK?_^6?lRJQMlSNlJ+X7AH-Dj?Ek~f3 z1kZJS)RpDm;97<)`lP(2lNMOuzS3xml;e#$aL>M}Y_Fmag);7AVFxHB9*Mh{4U4i@IwZ!m?wDw}?41iX%EzM<9q`OWX<8l$nx zYb<90^1H@c%+g8o*m)+3cT+*sY?tY#LO+W4htoqTN3sXE&Z>wb!j#^XUWP2JDLRqJ zFpi~=Xt`M*vTEc=6(J2({apV)D9U!880J0P85>?GdKgSZ_6wawmcy>)FatM5PQpb2 z<%&pfQ@#?-5g6*KZxW$V#NN>hW5+0ws9{|MfK*Pm{bz zl6455Z?YQRPcyr%KtIj&G81a%AxQCZ@jh;MI7A4LaF_=8yvIYMn<<~P=R?_Dd2qWV zC%YAJec#QB534OiDW#LU6R=0=({BG1b{lI>}Qcbj$8)1uxO*Wuv628%^-+J=Y&VJM?B!Q?lOcrJZe_Vdis|YYt$W1c36|^ zNZi^^?}P#6cphy2k1a(g3mJv(q^Ia!Vv_BrHr;u6Gk9RVMAK-_Qf1@4U&6xHo6rO$ z4CA%!o{}t;5fW~i?sM~ue$K9c=zcl&)b~2OAW?C~);H&xw`T(#iGnHZ8?^@%4Xrgg z^^6v!I?D7L>4<;rQ}r9^y2~6EPY>M?oP!_1fsa$P##}SH^ajBcNqIUfaGK;Hq-$&` zbOz&O2wC}%ID_fpT@nsaID?nCGsyiBW8XI#*yWz0*qhRB58&mObe&+8 zZKIHy*HVmRww1;(Q+nL4a`j!50pc{du$Q~7M?Ap?6r7-Fi{hWLl_WF@h{JHKFJ)mo&jU|g*rUHa~yhl@z;CmiIc&N>6 zlFl`hN%CUK7$rPMlH1bXI>%ZKN0my=X8COp0M*XK&~}oWD-ogjbYR0O8F&{~nh#uGWZa9JwrF4Y;Zif5lD&vZ7tmuGPxU}f4alQ47z(8%?( zArOn!0K%*A(%OyLSw(tL3OOY}+jtH+IgvGVrn;+5ZmuRhz~>pHnCowzO@kmGNnq?S z%E?jHrXGqulITpMfG&%1Y2mjySlT|SmuZTyT6;`m0eL&oYo$nmGdDEM&K>iG;?|L` zCGMIu>QQQVe!KvP}{`q*TOPR9(uVh{_I(-#Q4%T*G86Y+X; zg%=b`0|x^VI#rp%LO5lr)<6}xtlv(fzq zBynAj5~MZ9$5y)lqPjg$b65gTrF9Wb;=uV@=Yiw2&~2EJ$w=p0VMv09F?cCzwr7+xT0E^ZQv5{IQ@=h-_rA%Yk?CChlPCH&^Gm6w#^KF~g9^{?zmnndZAM zjhq*m*EVBgk~L9tuSH|gSd$pL*^C(lfH3${}9u=CFX4oHqSPU7By?EWJZEe zLgC&)TmVm;k46pk;d%aktf4yCT;=b_dHxo@SGw@;B*Qz)aUUWs6U|W{9iVuzANIhy z#YWCqi@NWzE%>rLAiQ`M8@j?B%nt+vx6?Ah{%9mVsjf@e;*|pY&ud!v--Z=pl6B{} z)XuAS#j`}tzgD~4##EnMdkAZzr+07l>1^!AB4sJr>q6U%q^Gi*U6H}{ZU@9QIT zzF5sob%eW%F)lm~$j5#!ThfS)U<|KX2DOC48Z!tX7A4q|)7|H! zCFY&3mS)d(?V-8+p$C?%!+DI|gloky2t}j@f}_1QYnyvzlomCY8iP;A*H1{VQxvj* zLFL;S&0cF3UH(PM0Wyel1{XN=5pmcJ8O#)Nu3C}d6dx4#yCm_S^^SH37Ui zCa?+b$>O0Poa96$5MGT7=Bi#~kQcm(7a4O2$Il)lG%Oei(&0Avy9)o=0pv(z63QB%9(PWOvPiMouKYdepsrSMf)Qvl#>Ho>gL1yT z`&<>xzf>?jOjj$XjhB$lfbl%SxTk`Vj;T)TorEs1FB~SsWbM}G{Dr;e_laoZ%u{8- zz|$OPQXT@M_-i;_8sb?NVj+s5jA$4GhAWOcu{2=USThOTKZ1z%HRPa#L4Zs}*FMOu z-B-F+)+F67ij;3cz`U9ARO|%!|K-9*_hP{$H%d%qJz`4dOiX(2A{&PT}G^Z3G58jg4tYks^WV4rjBh!n7$W5vcU9rFGo14+xC9fcHf@ z&Oob_&OvYeIc{GZ6DuX4Rm|}gTk5#)Kzeu z6(HKB>p`@$NVIf8%>1}`pMoM!VUb6bBG4fz(=)>cvJD2K!uN0|UZvJoy^2EYq3vMc zL&D3H#8W0{6Og!yNIbeAk)2!%WJnf|NR|UWIc#t`;0@+hd7(B793k!uNuq@M{9Z7r znQ{@7_5bZ^y8eLQWq4Ta0qeK0JGmv#vRpd3^7W@ACbg#8@4F)TEed?~fggX^zGrOT z=B=YUt{EAfq-kq?LIU!Zd&02#k~imJnCZI>EcbhHgID*rCjhK`d!pVDmSFWkimq>H zU>ZkI)mJrIDg3I2eafOwkGE5!`t2CIo{GDK`k4ksbIGMJwHoL(|KdBiAx$LdIu;`IZ0n7u}&qi(mT?au@n}HJ`V3PU?UNHNuX`w zaD0GMC@a_c0wl?k#6WGuZs63YtifXgX@ZLfcghAJcR}G~f?6Ed!8DeQc=%z&gC@JbBh z2DV?#-Anv~@WlqXJ;e|iYorUmpaHC{?`8)i538_Xf00{?U$6H{%m)@u5(HBp(Y-KO#=mVlek$ z$Ua4#{j8A+h)W4kq!96JNIv$j1My{>(EH+}4WS?6onGZ5vXm|Oe-TIXlUFi@I;RLXW4VScuP zX;m2ch@f}Ch|w0RL?=(6gkB-+nxPM`e4PIez@awi&_tnhAIt3}v+H3(B3vF`DToykGeImg) z%cYeA0vNWe|Yh{Jxena4V9;^v#9 zJ#sgIYjxSNxp7jF6+{WN+gi~aFI_}O98@-#3lr!YU+Lh{E#(kWZ{5+MNQ5|}bEL`f zY8YE7bk9NZ3K39+eHS^^G6%6}Z_}|ZD>hjsBQ2Q{j&k~p9 z$szo<6bZf-B--%%mj!7xLh{;GQ#!nhhuSo?SYODNwt$`rLUNQ(9m-TlirnDj&tiqp zC#*eyZ@z+Oums_^z2!{E?fXq`6-fh@`daVVfJXy!49rB%n)n>CC+@yAaiPE&FNmgD z0ClW>CZp90v>&o+w5!XOQYMKZxsq#;>Y&Qj+raAWVbycL_NbK`%|21vDI)0G(~54P zBVC%!>6bV=2%53RiWma$PUNG>Vwg_!Yib9v?~^5TqTH;ElWjbcb|O|0KpmL2B~~-) zpk36|FG;20;UwH?Mj0FQudT0XhQ0PN#t+pNBWlArzxid=3p;Dlp>DP)U@G29>7kFz zz@*9;8CxY~LfV=q`>js0bKscuqw>R_xCwIo`kp-yHEx2Onj2H+Si4@Mn`U6&w1I^m ztrjowi&Wjuhu!4YG8qImY3-~D+cw92?pQ=XzA%=Sunw0msXVb}ns$*1r5CxaI2Nd}wMU0dxhVPoXfs+^i}I7g9d(7f zt*NsLqa|dQ;Yb^~90}|{67(<|_uVlAIO}=Zb=udFgs~#Ya1D)2ym41vOcIt*&v;fqw7CqdfV2NRm~8yAy_#3h$V0U zu~9ilx%+I8^6o-PR*?f(h3wSXRna_+8Ce#)5#vryzO&UBD#&*E7+fs@z1$j0K7fK# z1aTdO?$3%Ajz9;UJ-KaERH_{}FH!l+>?#_y4-^SFeu>hB716n^I~F&%e+y^{c4V-E zi7+41eY(VP;?^h^a;-od0fLbn-PofCLFF%#%AYNZiolBcnMN-+ey~fizk{9O4za{9 zGKiK5E+34jC|b4lBewPvYb}g7y#5%I&8y&x#FM}FTyCd2Ga4l}A&JDs5D02Th9My` zS1P*U9N_RL)eU9ZQUNTkF^e$Ak5qEH5~z94C4Q}*pUhIAJKO4_g0|+Z2&}ky2VDYr zgZ7sblh;){Nzt4&0eEBreM`Xg5e6?zgk83g1XC7yVaxGu%n1{kyo(hnaK!f9LgXnP z)+rJV+VBE%v~z!PYv4fB73*F_WdF3<>zN}4BkAn^A{i6RP^2?MP&z52yh*bOWNNq# zg~12eDOWGu{n^{8Yi$-WnNEF+o%&dR4$x?}IS`_ma*AGyMTf|h@jJlj&ty7q?xWCw z`-_nT3&>fp*bJc?1YcBkJuB*Ds!E~C(I_@3@FsKel=htedzHEv>TSf~HU0Ng^%4;T z!vqAs6vcz&yJKRZ?mohN-K2&214Q|c3(7zTWSi7)T8lkK>0@x(fCtt{DC?{f*Qmn4mM zl{^rd@e<(BX`p~#h>)HOl{VI6UhGI_2e_vYiY^Z!GQ6jMZ)%%h(H5Tdo6VI$9?0X; z0cK1$i*52snizgWw9Q3p1koVk+|byhIutijt5?ZehWOaXT$gAwKg1(L4vAR? z>VgAZWz=2Lb*f=1E-7eZr0pW$xRhn{Xw?QU-byCA&&PiwN93%CoES?DFBUP}9g3?? zlr^}dUDA1p_(gB;a;L2u5L>44sR#-&wSzC&6L2p0(CKHBfE%141-seKpcwY$*NihAS*w5w1*NucMkULoknI-2Vlw^W9-DAV6xiM4> zvk!-ab<{X3o`F`{dj_WI>mu-6b=&~`f2MH_aHMC{CbvkM%C&OX_FRYna0yxhmh3+? z$YjIW&VM`slJ2XyS?ojxI(S1I6S@K&c@Im@z|w63zV^Xcz}CP>Z8Pr|DMb5Vglj%N z!ov<-OgW@{#CJa)!vrFR98m?B*x=RGH$*BV^al=mEQV3AHat`Vd>Ml0eb!{(Tzv^> zQi6W-1rW>+l!?`31RWx!NpehDfJ|74Hxu5+0B~kO zc?5#mA8rLdSx*Wg^tQ){jNRlSB}b27@P8ON2^fB* zC{RT_V@5C?QDU0Zn1MhbhOJXJIFZT*LAB~%DsxDWf+J`SFe%lvc=XO~xF!r!UFB2E zna^^TZz@ksLJEG_hGJxzc=IGd=5)1amI*_u@;SW9$Z(v01^;NC}rTyHJp%0^ju zW@ST!o*6aZ19}96B^Lq0?FK?&VTPC8Xz+`#g& zlbCc+J)0C(Y~MsIKHBOB6;(S)tbJ039yYLNdwj)1+0p~Jp6>Q?nt3N8zj>o-Tz(f^ zc}*V0Ldq3%PYR5F$65y(L!(EqHKd6F_+w2lZsEM-i^u*S^xnnSbXVYK-{;?WLM;{gfqZB z&0q0j*1!)HT2v5XBsx8F^AH_b?gVG)I2e}RCKHHDk2$uYo+Do~qmHMd4hel3{*w__ zmmQoH+wzWYe%m9UXy3c~bsLoN4kbbL=<99l>&pkTuih16l3be=+A$( z{)j=jrcCIN#k7a%;xR?!3O=KepwBYGdwYQga*&ark1hmxlKgzE4F!F)ig3LAe6zwt zxwwEjg@Zoo(gXBfqg_XI;VUbQPnA{}50G z{Y3vRQ@licpLrlI>6%G6iRAhssoNT*brr7$6@Gx_(1Kx6^d*l)d;ekW&15qbC68v- zkH^=GJT3y@WEbE0KlCFbe|EGGnH+CzoB|aWx-kXCoNig&=?0pG1iqM<{OPQsp&~3O zEKiYJB&g#N{pGtbQ8d`!37E-dwp|b8Gff2v$=&1`^x=AAT6$CCnO2%q0;P#{J7cXN zG0^`s(f_ESpAMuDzc3^{RY!&)3;#4KQBMp%0X#MA^d1xAT>d-DNkUv%p9Vl|(ef2~b*&M3MYP0{ zERp>^KXPbXh$Bm&FO`^XV}HM1gkv(U|3v2Qg@pIr2ZMgAy6Cs6KmF31+En$qO+Q5w zK&2NPfPNPon11)Ozb~Ji%JtLI@81aTl?5J{4o&di96ID3(ov8^TyF!Dduvc+U3|uO z^t_KmY8!%o;}_)>9p<}BFu}GDNiYRdgOztQ==GhU~8zMbsG6U7(vqC++hWxp4Fg^FH;4~ z+cRci$|w4l0pCwj3i_GC+qY zqfYaE!G$5A=){r$c+mF@EC5Cj+*!q(7}RJw z*!O|vtS}u+GY3=<#=hO@H~>c&}KIR}{E*&-a`tQ6?jCzfUji=^^bsRrx`LcG1Vq8TEUu1YlteG(#))$d089dHVp8Y zj8Qk@AZ7@iIzYK+KYUKc;<4C^?n7z7%h#U3vp!#))LEa0{XysTyS5B(-?4j=r*--r zmG1wQkA62;_p3d*gVW^%&*aM22d(40^rQ}4mxg){u~$cwx9r`qZkV@P=gDb)W@GEf zwk`X2?yFA*=#DpUJU zM7KW5oA}Ojc-$q&_836q|6}}}ff7rPNl7m0CI%JG?y1rrVI_1+uI)A9GPKiCC=AWK3?d0O>9VmmAOr3`qE2RM#=;D*wK@r&#CzR1H1d}T;!HjbZZL2s5 z0#srhdtM0{6p=HQ^SLEn%4lVcyVIBh5L(jKz--&@_AB+mw6Q`oX8@s z#L|xujU=q_)51&Xltq=fI5KA#uMnR*^3c*hA0(!7}f;lG>R+58UrV zrI6aBB?nmGUb$>TEPHD?hE|Rv&}I;RTp{B&#NOHe?swxHGqSa%m0WPwScAS0B1)?J z=?YQbNw|cOd<@PMC-X95{09}rQMT&UQ&{E=rHo4~G(^$E>P{+;yn0C9sSP|7UV&?- zSq%hKW+Ylmza3@Yrv?7(xJ?{Lioxbi8CJlNx6fPe*i%TX!Y3&`Cc|WPwty5(S#nPZ z;~|7g=^!P;`6|204K5o%i<-K}-gnv)*GdI5+btW|kgYg^ioU(j)}!9)o2aMrPFz#| zxD$7%`CQ;+ii_Tb^}K^zxT|o17D{l|xB$3}d9NsGM1!g9Lc9YD%Rn)}h9FH<1w2u) zKnQzstHkH%2WpDHJtK=zn~kOBWeTv=cMVWm_kCq3d$wb07?GICa%&0jT+))ZQG+K} z*j&7~AuuP~&usuGBR{@nuUNK&+ojn25DMUbCHZTg2%6tN37V%~8z!J35bUNdC}DOH zBsJEdDL$%?_GEQX6YO#UPfCX`QR%ksknT@SigQg(Nq*9?n|^WSW9*)_UXV1|J`XK1 zA=*#+CQM6VyQy)2qIP>Jj_x)%NJj-7XqH;=1@(2=ej6egQy^;fzT(ga$f2Jc42Nn< z%TQANPCc={lLNgRq^1C6An$j0*;8FkJU31|d#R)ob6T3VI<$-nIi&Pz|L^ZEAci5H zp_H=v-1J&BR4}KlU7ZZ>7`euY|X_x@ysGS_D3=8ab5@nczkJ;U(B9 zl~O}HEoDMeE|8K7yT$zE7lg6qMFr)QexPizAl(3G&lzO(SzMyvO{Xz+Nv0EAWp zdO-9dVr7XeOsynm0VIqGbms{=-V?F5LZynb&YFs4;p7p9n6EgYHkKJ!J9?<{ZLD@r{Zcuw_jM~7De;>EO?cF&IYmH`bZB1eindZz9DW}etU zeZ$q$2+oOfN%d@SoPTPIy>HM^2I{bvw(Z3WdkfJ%XArllW;vXtUTe_qpL^j8S+i8hxKM z`tCzUBe~42Z^rYq9-ThoNo$p(N^9&myi~BgHWd{veln5@5;f6W#PiJG_`#N}Va@3s7e} zFm4ns9tmvg$}Ob8oBB|o)8*Nxm+3wW+UnMwcqev&gHS^6`g{87y{StKDLwiEaBfxW z*n-yNQd{^{7n39sfnCkmO&oC#?V&|x$=PBLq9=L}jLR92OvzS|(&fzt)IK^Xlbv-_ zhE5MYodQ(3tOlsIF=!(F-OiGg#t=8b^;(kJ+u39zQJk zLqYB3j}56@yvU(1NArbXKZWZUj~s!gT{Cd*_$O6k_%q(J%DA=}t!SH7#!v{uYzihN zZL9rBa{UW^xQ-fJ+~zEjt;ZcwYusUMSt_omyd|GNJL}) zI^>$3nz$rBNq|__H&SA z4p-diENkvL>Lp!WIu>l0LAe|=7_E)bbcH{&?K<5)KZzcebnm4ANp!3QAG++4f%tGu zXoL8GA!VLnfv)(d<2{MpLerxa{y9PlBAclZKMRZ zDZe>OOMcX@u?EOf1GB(fgEUDOBP=Q3X`V=mRJQfLr$WnKUrs02UI8ysJFHqpRY8xy zf_~8$P|mrX@?Cbo|CLXQQMYN{t?8UJQO6cS6G^xOYGT^B7|BirVyqeOOa181a^L*1 z6idRS-*SAv!stk@p@Q&*8iUaOEO~YPsMEY}*ioY*yi#`VSDL!vY0%VvF-_Iv6jny3$7g~F&g!la8gOL-Q=?+^ zB0`}ve4apO1R*gS^37W^TfOUi+lc3H+8NZYtJY>>d4dcDsD60TkIGgk4k%mo|7ODd zgX(N6`rjLuw*en@$+tS<$Ub(z+c=91hzRr-mZiVnZtBWm!)4^qW_DfcCKLM7M85y5 znQTs8retLRgWNDL8*^Y#qN3hcNxlC*3F?6uq}5@G6P!Y-h146_z!^ff47Y!p8;fIg zx_$4?u}NQ>mHT_)%xQVyCi_fHEeq=&v^V~f*5mrC9c+UH$wkKxV(&yV<$^~x=j^si zcpuu$IfwB|-p#|=X{vg031Y znthzl$E-yj{#yXUBYP&Zxj-AoGVV~;QB9(0BQib`Yv*Ns^I2?qHJi5S1>`$cKCfcV zY0MEiIfMbM=7Qna0-dO|la)4QC7ilK7K~8jU(5XSm_NUGN$lxvdyTz4_E~UwE!5fk zL=2kNc50m!@3nn^q<|aGJc&v&wR|V27@@46|7tq?vPX3IXQ9J~zQL~AAZJ_9uHO2f ztMBM2cil;S%LceZ-Xy0zc0zt+_sHlDUd4?smdG5ugGzD?mBido*S}QaaLR{#f5%KM z&(Z*xW9sEoIp!dl`|RmNK?U#^+IVl5io=DF|Ia4qJB5!FyX`n5r-KB|;=~0-ys_}X zff84D0m!B^UAc(VMAOTD0e!r%tB+nBuys&_S47Z7^cxo7hGeKyoiCcUmhwuNVpX!ghkMof|wqtuw8{M;OJ^y|-du)4D-?e9$n`G;as@Nx+ zduGApo;|a${JCcq!&mH?#iQ?;#Z&H?#m?BWXBHV{&n$-UUUQ&N5BXPy+M8sFR$Rlc z{j*o6{v&V8*x1M@H_vh}ZfumrbN5DB?(W+}4Z6c3qMEJ3Kxk)J+%Lvmeoz4@0_8tG zKXfc~lup4?KV`>{uu@Ut9SWm;V?DF4GK^otw!czEW23AO^~CQcmU(x7{2DVz3os_L zFN^;jJ zG4!L}FhKIT`n}WJhfKtPdl`=q!uy*apE>cYZk{VbscT>6yQX zKAl9%Do-f84Z+2Z9ezE14vVboGQRY}bmc*wVRxU2@A94GQ^osoq!X(dUJgCdp@uve zx7cOR=s`keUy&kPJ|p^i1S+$yJ-nUvZBUuk-`?28O-)r{g4OsdBBllCaGdQQ$N6z`Hd4O_ulPScUY>0x2Xe^liISnLSkYS+LAMeiBz)i1PBA1JIY~IemCi5n zmoLxG_iv3v&DMCT-7J(*Q@2C_+ZiSvDGd?BBa?{95x%*V?`(+gNUv!6UDEWQkQMyS zJ>B8wFwP-r%6*a6)zJ^O6z_+drg1_b;<^t7ZK)cQqb+GVK5e)D5@>s4wIlEm+M2i? z4%+?=Y5T51Tek&iS8ClK&lVuv#}HZsw?bWe>SC`ubAh+7yM@M2UOF{2Evi?F333ve zk5+ZOZ$d5aBZ(%N)b=tCUi=JD?c){Iy22PShR5a6rp+Xim2(U zl&HHs+YZwU_WG(7zPZgXho|p;x2ZcZ@@dz zwKW<(z+W?u3K)eG@-6b`ONBpWgf8bKzRxoMP|BcHj>kWRd zjU)MjlM++L<{sapZ#%p-lA|23@qk{hFL&`X(f@z1`Y+iOvB6sTYxMLWKR!2SA9&{M zc)`{X*4{tV8g0?O2GDgOZQOZ4kwK0Rhk;q~oo*p!uc&s>Wz?KwDH}Krl@)f7Kg4%R zcSi5|!W-?eCZG-hNiBlr3TODeab|>+Wi_r(#k@v)dX+way`j#-7uYG>wrsO%?q@LB zq}t`qHnxHyM2FqalC%))$sEzSlHqC30u^3cQ6b_WcDjX_#3wv_Un2Mv@;}77uP=37 zwlmflVVZWrZXU-?>Lt*d%YA&h;ag zA~T#!4-o?5Xcum&bSitCTAdPM^aR1YW`Fxgr0N~YQZvX}j38c@kcvMXVrqz=P(z)(^w=4>FQ z?^UW~^>gIl7YhePv)7tf7>rO=&90=2|d+>5wzH8WZVc>h9x%m z9F{v}31I;A2H)@;dVKSl^1;v=F!r`qqY@?d z7$1%R%M}!PnX$tE_xNd$I9;E5L={6|tMN_`PwyHO0}Bz; z5rG-eu7|Z=I!e*BcY9oyJO}*ye2I3YWvdqGp29M(wK5j_P&?ilc%_@W_}M*iSYwZW zhOc-G$)&_6^<;_Lf#hh87{$BTODyi|hiUQeuV{q75DQ{+(Z}%%x?p%Bo%Y46- zQD0#M|IX+KKjY2Dbf-kMBm?<_Fhu#z`svN5yb47BzZ&@JS653IksQZGUTfDgoG4P zB~y4(j1q|)T?r65mHpcA%i#1|jnig(P=!>> z+-NenmEBU_c5_tgA|tzpN3Ywv?=UUumX#Z<`Lw>EJW_AU$YmL=zHAxs%^KZHFN~i* zo`Pie%Sn#xBKu0vp27U3)IUiWw8jFe(AOACx3b8ISwsb46ey56$>+K!RSKqZaBvk& zjhtGjtKHPi^zYa(;~8j25TFG&zi9ASGfq_74(bzfJHSm7k%szg_<c2c<7DV zdrEVj2IlF_J3O%6d`V+lLPK-EW9Mz9gmN6bOR}9B>(l>QrbgV;I2%K?TQW`GLL-5U zY}{q|PoysJ{~WzpBR=g81a#w^hH3{6@!#F%seki>YOj^oxL<7?=G*ioT9wu9o8xoRsbOY(yP0q;QlKE;cpTjFl!(1UTV*oCd$2XwECVs$??yk*M9=E|Unu*w{O z(dpy-_66rkY!3(s3dH<1!fBxSbxT5i=+8T^g#H|x`ct+R$CQ$X#Rx8@(Mgyb?9u@V zQppXv6`K^ADR(?F06cs*1=T~x*xoZXZr^xl8v^%@)ywg_c5T^vn8uvkIe^L2IO7l8 zjA|cX8H%uZplmPTHh|bJpdCW_x|w%_*`}e~G=RqXjaK(kRXzq)sD>j=8jf=1kFX2h zsWb7;Pz1*WE=bY2qAoFiDeMr(rBh(V`2Pf-I3XgUU3O3{83|s(LVE-4yUun7nZb2O zO(r2j5)5n5fS%{A(6F-PlRW)bJl$MU7R)84Q`s(?nd`1_7!}l~!I+CN`^wFr!v98@ zLAmX;)3(dVTUml+w#G0_;>XTrn1{h|_BIx^`Q9p-J&7p}1F52?CdA8pi$3$&fdP%N zcn-7nMq*j^PnIr%qVj=P6w+D(8i>lbvGVza&#OyO9qbprF})4!5_I|kNQsaPshSkX zl3_8?1Gm*W2H^CjkMtcP^A*%~sY5{^$_a$ckswP`IX@?G?NX27Pm^krEeB^x1}Xm- z5BrjKtNob;Edt=QX8P0^%udvcWYMlACP`R@@k11|oR~mCBF-3Gi_D?sQVUoNG=D8d zq2qpO1SWZcX0#ytlWIdAOG1v_%BF(&g$m&pt;##oKq`8)exGd=N_c>CqN!ifKlCrg zvTOmwL70kU$pO~Nu%}s@SDUa%$ZuSA!VkW&;KDkn!GsJ&1Cv#(3Qm!SIR)L|A?Kq# z7<{(6S;7FvBf%p-q8dm%%~)xnW|A+o+2sS+$~MJS+s6O|%bi6X=L3xqyMYcm_h#CA zIxb;HPRq-AabAlx3T1I{iwSFR2@X4I(Hl2Y4pUz(uopFhUtaeqWKcn*;I?8^Br2qj zekJKBBWHX$B%ZAV*UExJreyetookg%?qyj_o~1z>0iR`0R)>0CP*zV zAZ5D|pci`TTyHH%fqf8DK=4bclU%FENnfigd;ENsqV1yKECFxp=zLNf=QjDUnnBgdu>AvBvn zDk94mBq1PQT6%5}AX37Rp(}Xg{dB;DU`X0r8L-l{p>ThlTMl_1=)@LUcf!*=npA@% zBqR%zHAFz5R_E2cj+-+r2M6vJZsMYs1$vPH(nupmADN?(#*5{kq2R#}$b-MBc%Z64 zN0i~Xf)1gwOJRV4k-#ID8-TSvS%>XO8p)HsAcz2-ju-1H$zAum3`E%@2$j49>J~87 zWQ7kDZ4xPNETVD}pxrAOGs0|&HSF#lfC0KOdo`GX-1|#3RUA)bb78pp$ut1=+;|eR zeKTN|unvn*M*5&sKn+)sXQ+}=rq;!KQ4MT*rR?my=_d{|-KH` z8gNr;KJWwd7=z_9UceW45hUV8$`Fasyk?4MOEEs417>|XA1v-4N2>Jqu3^Z|KNs1d z=4x1B$4o!0Dqf5gAq$MTlWWc>SH0*bi_-Na31WqkVOiF2?eQ(Ab&c4~=Gt(bSwQx- z0ZKF)>}|+DWlmv)Tu%?@2eKy%a4O1A#TbC$2;C2LxpXVK-1ka0b{XVibx;exsMF{7 zlkS%VEkO4_mHR(SVpF0=rz0VV!2hSCCnUn4FJ-LpFLQ@s||p3kg_8j{G|C&9=Udx0EDWDfjR7FiOn4sPygPc-Ak znV4vDBE&Y(FL`7+UIqT#nKMPnwb0v5?!^sENlVw! zQrNYc;!^Mo8(A4{221z&DQK0nrahxbIc;3Y)MUyAEeQXIXbVzlM~Z)m!#N-S$rFxf{2%YJV#+! za;@33)|Xw1QThS-bgS`6BkzXrZ{pi4vG;!i1e>kJQJ)Ro$~+i4wq~+cr~^1MBtL4zfCG6+3!C5Eu+KR*ZZ-i^`kq+ zhOg;eqIqO3t6IxC9EY0@B_!F)mVWFUC;VALg`4;69aAK8c<=trJ9i>Z_~4$0%7rwT z=n}oG&p`nN}&juw}MwlUYCE^=`g(A1J-Z@ETIGO?RF6Nw(IUL}_pX&}r zewsxuC`Hp2a)5*N1O@^13oLp^p;gu3cbHYjuG7^p@^R(?mTCawo;$aM zCsI6=Hnv^O!4#5|n2G(4{BIn_1M0JQdhnJ``Bi#S0qGjI({pFQ5(Oa*A!;8XZogM9 zxPr(aulcrC0;;JI(fuvO_|`Swvy((1-EXS_OQA@`O^O37OC)DE-+!SE@!_vTS11($z5M5Bh>0Q)?{# zimuBkq`K5~<&`8I!*MJdh%AMjNT&z>s&0M;9Nlgf8wiJz`j>A9^{ay{B(jJT&Zn1j?^Hgj1Ao**?W7^6rM`}@StRk7I_hqvg#Rd#HOSlWss#Jr+KyTNmZWL{G&>= zN=o`DIo7)C3)aItG!-_+&_NR@51ela_c4+Qz@Sqgr#IiVbl_{z0Puv5l2Ch6PkD1! zh6^~8z>B!gSzG4J@y(YJs94~lGauYB(efGBe80?$Avv()1(s>&{DYcjASWh$g0enV_k5%7o+G}a1_5M_7 z#4cH#;00S|goSb>V6wB3&I*v?=d-^~nq0q&?eXUT2C=80TSy4ctOuc&?a9elY($Ak zQ+yzCiH|B)L$*vzF9bmMYg~~eOh2UHOYxS7&l^y zKhT_PeHg-bsX=DI2;2DQJD{ES_1NvTAqO6as;ue9S>qjL8m?B0RJj?`))g%)iH z1QpRaQ&{nEDl}6xncDmp$qui7N|h!prZ#`Cxp;&p$P3e4Hj+p1I(d=(oZ|);A+v%IY!8c5DbhyXEk4&&k%~)X5i;GYxv(+C?!iJ zpk$*fN9kN?wG=j;qjcJ!EMqC+E=iRkLew>^l3I^x6ASqttccZz$y`|gI_Rm3eTN^k z%Av;WRG35t!ZU}T$-v8~_1Uf-r9c|brZ+2?+NU+9m4W0Fn%zu#Ao(-XvOoe`Ao+MW z1`?XCAOR4!qiY;s*c&kZYI{gQ>oga+>GMxd3^i}lj!e0vWoqz)=fjBpR@s$I^Qk`1 zbw?2jbBETx(=8cj-ls_NO!sKwlo;QArBQb=q>=&3_-65Tr?S|Qzv!FH;>TN5ZOMYu zmm-%A2n~Q4A(WJG*T3|Mr5}vbvTW;g1c{ptT0m(TDQ!-vhd8M)0$-CURIlh_zA?Uy~1kGF_X)CL8nP{I{f&^G{5yW z%8*@ACiH@3D*WuMv{enRz$%a#U1=p(LnRH1AxK+Vf94~4!8TZkTx8oIoD4886JaF` zBsSoKkjytz$cJ>J%&?}Ec5-z+wrE*CYKRl8r=ccR_`|U)<~Gc5+2)b0=CEc^DV1r? zk)l~)ZMM6d%)q78ib24IIu2m$HsTM~+clg>y?P?qGOswa(%KAamGx4RfGI!>oo%~X)#f9JSU?^uVs8&_>!w}>N7M23F-EL$EB^L3q<&$MZPt%ob6xub(zH!t>7 zmjhKj4HWT_=@kb#GX0>{r^DzFvByCmGQk8gdhefaAHWUwCOQ}pAifZ@kdrI-Ku-R; zl9Qikxvp|?ZnX2XhzCm8d=`m)Tbc#N4#D`qHk4D*9muH$-uM^mAHenk`gq-nC~dj)B?Tf;|@qVnMC!><4r6w!!*lL8P}%ocY~? zNG==xyY~3wHCD->EO9R(YUpmzk5Fxf(z+H|E1Go|i`Z?#(gKL1Mgng1rF^ESKPrrB zESVhR63>!U+oMo31)mA&H~BJ26%6`5o3&d@UHJ;|?uDsodr{Ob9X?>uMJ#H!5X&V* zXB5HV<*2}jItn}O$}8)`7xr^SV8FeAR!GjFm4<3!)G;p`T@0&q5u3B6FEy7SftpLtvc{pN6VLiqgenz{E}L;@tp+z=hZUV3=_gTKOly*vaD&= z5H+z<5f=K|Ujc*u*`Ql%q6!gJ57-7#4a^w=kTD)CxDs`X8?Zmb?3ZfMne7t73@;_v zk-_S2Yk_89_G)7G`PTXgEF>DoR2jcS3iD1udh#K(XT7M}`vBXkE>J@o4{Cc~WqThe zt34tyi9|oUrg=EdmHcw5Z~Ey32vUwqV-7B^o@_{Wc@`&U$taNdp9L9_x$~rob#)Uh z3lJGq6BSw45%Pbab-#YSEUQqoT%ILS5Kp_=rmB4rYu{tFYw<)$MOat)9EI^(lB_F! z>n%j;47?M|6y}^AafN}nw3dgMa7Kt&+z*o8-kQh>vhtf#5@ns|sNb3H-=vxjbtdFA z5=VI3#9?CW{P-s{Ae7`b(&z61&BFt2PX-jhL^{ge$+BOyvgs=srWL(E%`*Q~!84PA zscBW_K9+e&QB0mClNxeLNiOidJW;~D8RSMP`$tqs08T`$zy7`)JY;&9U?iJ11oY$@ z3TV%4btiQiIDG)K^73q6ohpQZ2bj@@v1xl?BY^#@L=u@nuFJ>J&EKuMnFAvkj@nh( zXRz$=S7lcO((Wsxe8AntvVU000vJ(DTXt}^lY|X|#js&JpZtaYXfTZtd_i0I1)ZU5 z3_7+WZ^$L7j7?56lxA?fT@D4h%T*;%h3t<=LNG3BgkOzxyQu<$Jm6_xaYd-1eIV5B zg;3%a;sTW{9?LR+QI)Y!q@gcuWS5DHQPssX3>Fzb?tm0TMSX%ZNx?(a_C;*_qgC5& z5@i4b5b#WyH9#OQr5v3%BP{s%1?eGyAtg5w_$MpiMnqyvsuEC5RRXN2+I_a-l?3*U z0t~GY5^$0mwhA~&U$xaQZVQWOt!!hY{_LzMyZK;P(P{fZpZ|D-KH_ulD0294%$%*J?t6T2%FX~%`$H@Wr8^^w7(RWTGz+*TIfkx zpq$t<(j1|3#$%CTovudGkB}bqU85RC%h>U07I<^zPUV2Bg=Z2Bs0Mk~@`2cPVt5iE zk*Xq97^r<-*MLX->PR$YUB-e&!b*%Zy5nBIbe-U4`7w@X;> z6NNr9W?|jfSXei};wWXLYMcITgz=dI!;Km$hBKn0E;L)DtuJ1|eo8VnQ55ma*0>}> zwE4{ad2aY%Y&3eXuJI=p)uaa1FAt%}1to6@=e%%d@Xor6@XmDRJ5?#I=dqsQ5N#Y> zev1Dh_?3h+pgAzw2x{L=O8rBNQnp-9euB7F$?vn|w^}91lt*aVL(^xy0F-*5MJb-w zH6==#{vlQ@nki2g*hGG~oF@J>R7rcrhukJ%!!7I7DP03?On8T6 zabR`A(!7Hxtt}{-Iv}?iJ8x%^(@T-uB0{KK(=5>LX3^^Q9)rdr#k75aMeGBJqCwjQ zM_0p3;MoOs6oEdSK1i1&MjANj(TxWP^`j{5q;&%Gh98tEe)E|CDwFQvI}9Dzu%t2L zOueYeX?js`pWA!52ZOMDU0cJ8p9QV@x9D16a!)rV!Uy9OA*69$1(3V~2rSg}IEgV7 z^X0gjXGI9aM$};sc&?fM0ZgM{n>@_Qfd*OXVXj`GmZ*y|LTafTnF23wyU5yunD7z* z3*uzy65v13OJes=CvzB%@*sz zqGnmp-%c$TC+wl;&;Yi!ldLQ7{SERVFqq@y2Ice-p`_d*|B^fJX92PC7n<~C%I|M< z&#YX2wWq9~{7S7JmhwA2q(9^rTa>ibBI0=SyX2Rfdm*xiNq%`*2nG5h_*np{uLO&knj}duT-tX#&`>iT*Y1oU)eBiwl0LVR> zecR5)7vIh%STr8fP?{OGNj_`_s}##OH^{AFgtrc{#!R0~K&jM_?GUsU!#V+mZ1h66 z(Kh5$;gKV>QG1ucH>=4kq-YkEhk6((_Z(Tho*c9EY&ti>C6u(-ei_I$hWryMSp)2_ zA&agD4?bPl5KT4h=!m*9sbA|_H~&U#2wII>xQzg?eDr+=t9Nt&J;l`1QrR8aNB)me zF`-PF=OMuuiL+Ih(|kt%TF*L2m@5(-&50B5=%p22;O~H$+p^q+Alnjh6^3OxLF8z& z$zeRzVXpM|MgHG+EMnnm!1pooe9E-ui(u`WAL|TTeY2fkp!R27ibaTc`4}wXZ@(6 zxTm>j5FWzhwBIsVB@Vl@M;Rdo&rv2v`BU|xZrk|p-DVS0VLmA%&$eeRT0hC2)km3F z`8)1A2)~V0<@jJid{e~q6O_S;gwTyyzY5)GN1}-HnL*QaPSaRhN?p&fm0wt3mm^re z&@Bl{$`ee_=?uUkrO00N4YdM`Gl|99T9aX7ku|MVvJ_0$pwIJnq)&Va`9#44Y!hze z1?)=+TOp<%4Mrulb6WJ4x19h($8)~>k4$Cb^*h^+cf*bej|n*EIn^Shex6&(D?R;b z_|FP_=l^*3^1vame=)JI7I}rS|GF8DR)b1mpU*_Agl?SR1KdZA5mgAu6(uc!taNfW zb%?94EE_gn6rK)Dn<$fxYovgGH%=WQtQk6cyN@cpOs%1J90@cNI zYwu20J&Wy0t0ap#E>BeT9#*}Bg4wDI$ujA59q}+|SdrXP&TAt%npz8#Y8<$e8prKD zbKy@j!%EOJ<&iwr%^W_o@kLqDH9HIx&6BEZ)szHdO*dep(J`HgLUhL_O=|5FV@$#cHPZdpPi`1ezpFQ zweB0Y7G;hrPW+r(%6Mv+VbSK(+8Y4x>j#8KE~m|E!^>X11Gf@2Q`VYKcPO5~_ANWt zkNC#}{A#qx?YVtqjpLzN;~3jBoD9PAp)+T4HH&AKt-@)VTwTi2LCH{`3;FCqw6UFA zt{K_9bEW#H%#`8?jPQ#4^LdZb=MX&S`zke8D$oW?%TR^$5nWS zzrJh7?j6^Aa`iC_mfF5$bY$!1tM+f(HZtnpTe^1N@Sa_pca2?*8bDxl-!L993|3^= z!VB%NO>kt}{;?6|x=Ra~?S-cuyZ51U`|&ZU?Nerlzq^fA=qAkmcnv8B*zgPW27{wf zjd2o;yZDCNN?!lZk=%9;a=_%?4OU$lg_%Hm7*0xlP!mVouAJW7rK#u}=anf!oEbhH3h}YBxeuI=A@S^3M8TzM}baVZM=w67#qqb46gzgcjzj zJqNIlpU%^x98=u;Ooacr3t^lkY9svL?9kD880(7CI`DK$pFR*RV52}xU|?Hr!IVz( z1>q3x4e(t*y?K+vaqsvEs4araU+Xllv06$7dLI=*BN`}zzF(1;4fyzU%`TihoXWr{ zJQ0$z)BL8v>f6Zye(VpWs$qZDiy(M++VHoCV4KfP4i(ZLqrARD2>05)9R;4nr2S~Z zy}t~r-enBHB2b)*ra+s2;Nb!8G_gRTPZZn>$am&(n39mz${aLwJxP%9qL9ttO^8C_;hvRA9TzNU|M$F+c2T zD|!K@f@I5_VfPqe(NS6)nKK0Ds;WfcOyuzY54*%xXT^L*SuU2C8ILvGTzui zBMgK7FW!1cVW)X%7*5)jcCZM-gtn50^)pFX@e}xXu0Bv}Stvj%PvPEp70zFlSM{^} zzbo$a<`yF(hP~fVBxxn~AW%#ogbE}$vz?BCIiz~m*V4U|{xdS&xNDFR69 zqZz)XDJraLew2CY&*{xg$_h&-2F2(`@qM0kFBNVBpwdvp3Ag#K3~3A6T1`4;-7G_8 zrENJZ%8HL@+DQ_P1kZA3Z?<#g7mCD9AkRc|usOx*q`sdB!c)&<;njjdNHEt;@GCDC z{f^J_$VR!10o<=vVqaoT_&mf}Za64F`E`Qj&`;un=ALX1i{USE`)F&G zI+dXvuwJ3O+GCa^74eWc#WIoa+YJfMNks?{Gl=(mCzYiO2{i8)$Mn_2by&M2QNhEd z&HdI6wz7-N;2avS+&DUf& zljmGDBnP=J?3}#Vct1YR$!&djp)O;0aCSm2`j?T%aG)|Ap`#2?fvf&B%+Z@EpL>Yb zt{zrbdGw8$ja@g%@JhehQ>N?~+p=%pb&8SnghN2&jDRpSa-ayv=6ySMja*}a1;j(_ zZEWudLl1bZDzg|8!OyXMTNqS8c7#-rsP(iz{tfsHvvQ#Zicb-T;~=G;;eJqD*%$8| z!zsL2)R&gzA^~$aXmH+1t1?Fm#1gBkfkHFoeTP@9`ts&sFH)0>*42?degT$oFyA-r zA+av$fh27iWjqR!glDY48sAf>P&{M+kCiClEo29e2t@5>RXid#HjK#G{;L@DO1Zh4 za#P>Fk)wwhXj+sUTEOTQCfTZhOmAQgtZm!Do!RNUw z^IPMVdB5#GIMrx=pf!hwy|O%5cS!Zy_R!aYPwGTTx3WrUhGA-pfv3_Te7$A=&V8wq zH2T!l-EO2)hfz3m7>bwWD?5(I5*n|x8R?L`n>Dn+`)a|4Rp$Rgz~lx`_M6-91gk+Q>rdjM)9a6XE>jz!89C*4pk zM3J|#$e9I~E|uGeBDb?h`AA4Nl*gjToh(wFb?Ab!2}M55B99)op`SyM`&s0}h>8Z^8m~I)%b88jWTmyf-;{Nzsw~lb0o`rYWyd_xq@ZBG=7I{mq@Ow#fIlu*{Fghw~hixs7FNyPtuO=U{3BR|&$;2^Dwk z(Q%sa`#|))>Ts?d=D@xdn}lH-10JEax~^e}FVd{miCqlT7Tm(v%rW;E;P?P>tjClH z`r5=8Si!Yp*`rW)&dn%$M6Wv7MQrQ=OQ{9-m>K&+X{{~kEQyMpw5SH4Y&-C0ok+ zIK!f!6ZNQWm_05HpNxjDXT!($Y53%>hWUQD8a@sUznKmHUgbkXm)#dR8fD(aGS!tD z-PZF2l=&dbyuE@G%Up2qEOzE{!?O3V?0XMb_Oz2ZRXFMq|7G{^&iz|Q*7u#|^z&be z7jkG*jQv0N*vD$7I=p}Mnvv5ux7@L9$M8Dr8km$TQ#l?n)qvwsxhb`;W36o`+^B}f zvaAocr{%GI!zIG2q+(9>wFM%#_+=$^08 zix46xzZ+^KpYC_fSs;+j9*yGGJpPkpeCK}#V)=h40t~j_ohgezaMp+&t&4OT0BIx+ zNA=yrvuEGFLL1I4jJ*o(&-d6SPJC&_2OY2_YsN*jjUK@_^}^zxY}%|_V9NyVdgQy6 z;6v;%bGt`B^%i3F&hCBuj?aY=aA72w0HXiI5APyouT+5wGmRQ(`8unZpB_5}IB|45 z0so2PV*j5w&WV1(=!>Koqx3DZ3hmh5S(YVUlt*ly{Z&&9IRot6$Jx0LKj@vq77wxF zRQzY>TAkuDLvN=tFmX_wqGvqwWt8`7Jq^dHB{fHbVARfYH6BB1?xNXZ%IoLbt-R~XcL4HU(Le`f7&kKp?8+(YaP~K&+)0)@a6XInOYv4$F zd8%s}y1~To0w9Hr5=xj}GKere3>bf1Z?MZ|10crb>_&``&Xx%{r*h8b%`} z0xT-#FXKpBcbnsvyG7Zu?{cw6A!oZbqeSAVGck+h>!w~MjMQ#kWJydG0|t2;8rWO1 zC&v~oSeF~Cyf^=sy?24r^Qy|lXXc$rnrqX08rpQyJEciVTd+Wd8UplS4s!DDX!>E{caL=Xut%*4q31 zE_2IFIzzwyns3&--@Vsfd+&AIYhPZ~9|?ZUS~7Gjr5QQR9C(j`BW{7yRYlFX+Z}@e zd}XA+&5?fRlJpe4pVUN*w9d+oVQe(gw%0#L+ERn_ASkkvt33Bglm_iSW~-cAIKCxy zz4s!;jx}_SB-5h5>M``HOgQU2MO>{EyDoXpQaBK~Boy4Z!l^(GDa(o*tJ4ieU?_~$ z?e-*33jB@Ak+SlzN+zx)^GE&${!?WOVx{E&N1VmQ6Lbx;;8Q=!ura*f{;I zoEqs9Tw8VVZ`Rgbf3&vU8ghiR$qF|+$mfPDdb|r)ht&7xgVngN&IZmMg)S_xwc>8) z*KB9uu}~hs(=m!AkIYD7Z;ch%uosUl+Og`{8XY!`PcLRqBri;VB#Lg$Gj%eDfeYQv zvC#ZGYU()_?D{CBk!8xXMyHRBNNlTp7ZzJgq(Miiue8|OA`RX7 zu&|u9+2$GLw>bz2!K^`!Al@HkddvK9RI2vimqs2Qj6SEkOqMG`Q+b9rd~%fnB2Hx( zbN&{|`2n^qAlRoqygvwGuPw(jtz$gLFbc&OHsxuzPu|cLPJY>gL6jnuV^TY(9=Hot zPA3#w&XAdO(KUYX3qaQk#yYwQ*^q-DrfMJVd!UOF5Bss({286e7BH19;*MYbtvZ8r zp=(b!v}oZr4zM~kf0?I*LXpfGmSe<;tLha#k|Rms$>Q&K6*jy4Qf*@j}+?QEH9VzNUGaO&FexleQnsOFftFy5m6S8*GixOoWOD;;*4cMpkT$uV4@L06fI1Mv&V1?y~@ z-A16lILRL9ZSw_bu}nm(5P6w)|x`)tUEH{jp-U@QpXfX({djkVnk-UfXT9$@>|lJ zVjOu6lBiVKfwdl0Ax-ys*Nv_>bT%jj8oR(?v4)qFK>ILAUuk@vT#wIqH9k)^Hn0-S zxDl#xd$PgVlNb}!Hu<=jj4)RSxyEfsx5(&)iE@RB*Ge?aIue8mspTF7(RlKUAR6`e z!NiZ)I2}7F#e2NMfMd*!lH{7W(qL`#`e#_eSn~zT>5|(#h81ZL^;Y91Pmd|HLS?UHRZ1uknXx=C#L7nF%rSno7 zGEhck-~lp_m6c0_);&ye%)T)XOR!{I#&HowjddW7DOQC6Qj^Z{FM`GGre~oRqBCRTood7u4hH##k)NAqf!xN&83xN*zHu@}T6?8dO!MV|9?iwW}Cp#{~L6ORV zPWzM5IOGv!xm*ZzHyfIW6hxo;M#f;L*wx7m&m4oxyd`IO?U&&%`-jhbANgV=B7AE; z1DY-_)$iB_+W)F>R9VB{B}3GU#w<5mr! z2|yjkAvQ{f{QEO|#|D{vkFLZ&;6?C`%jV}3^IcFljME~0?7SEWYH5&Y_+*2BvPyqs1=~ky(J1Dx%kmpOqu!kJ3v7@g z3cTzH*2+q99SWAH!eYDHJ(V5Ci?)qoREE~YO|jlcS3KKh7;}IT)lxpWaQ@bpK5>9Xo^H zMPa9(hKUQA=nPzRNb2~^zkH^W9|JS+?-_n}hI`)6#PeE-4ASkR5^@aGFF>n$S<4|Y zF0cseKI=tdWq%)2!kp5GIRWPFuPkADg9O6rxdw2j#7E!+I3$$$;NIX$+8H)*P4b}} zpr2%_)7No?I!_lrILj&~HrAYPrR>z?jLU8|I=~1bi2Tn6okvLp%vNegj_#zBKc0az zoi#o^N{8n`EF71(D}4>vj6HgkdmMC}gGq(mR_Mkqwe<85?P5c;h&mSQVmiSEQ~&ST z`)0?R=a@G4rXyoKa>PyS@QUIQYF;`0R~>Ik6wU>26^TKzm>0|0q6_H<0yFG!z9Cm2 zV*<^Fdq&NRit9v$g5Ip_9=kWWg?te1a&+Jd&`mt|cE1No!9R!t8aXDd0b~Cl!5i6p z##|yig7cv7`1_XV5>_^S#`?H1Mf2v_mHw1U|Jv+Ie_EwqKfBVO6+5RFXhYv^eaRu> zuhiq{NSv={AE#Nrzy*PB9AEIH8As>L(CW*Y)s~Q}b2b{xYSBIB9d{gk*WSro|7ymk zdHL+x{6+N`j`7V#iF`?=Upl+eUsmZ~nqBFyXtcoP0&KL%)#)oCWf{A;dG_pT_>SoN zh1r$HxTs61)NDv8N0oO6wE>>sTi9~}ylxB}P{f{csI#-k!SZEt=o1p8Gt(&(w}SLL@Eu{nu63OiSbH4OZ7ub!JtHsS*nv3mIc*_=%2+IlV<3xvu4pALq4s8IlYeb9LXa^WlQen zY2VXTm+`CLSaxXtw!PSkYwW#!|Dow$vQ@UxVn7dEci_-oo)6u)>%g{a?Y=DxO59PE zS6SJSpfOB6@8YoDHq7~p>0_HNxNiX+$8_+NL*Sm#5reld_o&hzOl|B%kU4m2-OGV_ zIk_K66>Fcu^e?Fduh=sg0-Iv(<1%5zEvW<;VbWRExU+*(2IpXlbQmdS$o*4PDtEM# zOB}xI5?@%r6D9=wwOsiNghD&TugNM7^Al?Zz>mUhIBsWc62qF=73wnvhalHTL|Dfn zS_IJ}G!qdCE#pZ7`U-rPNESt{-?FBMXx-$ZtJ{BYDlz)rj5ei>gkX-PrnIQ1ARQ;`GhXHE<2OdUaZ6=LlWfx$sZ# z9*MInv$}$_HnP*bK(i{dXU~qE6Nhu#XU9#EX4R|9BPYK@6OODd!UTgBuNHEh2ZaF_ z50_Sb=T19gjC4Pa1E_UVCJb|N6qX{JwGapYahkk!^Je=#O%(I{G*Je0={`*;xwuc0 z$<=+DeC%`H0hJjX%0zvof4w>^{o4C+0@EN9NJ5@kdPl>O)E zN+I{TmOCTmmYb8TXrppJ-g9qk=U(eQb-MciR+=ta1Qb;IvEC#1wbBuK*1JbL)%WZ1 z?g|h4z;b|6ZTj&$y~eVA=E#sQ)<>6F3OlGfB{|*lkkY^-YOeKmezBLR)Pf;Tx+Og0 zGO&m{WezouH_t?H<2byHnk_QZyF?7EOv+yh+`q;Bk zKy5}4nPo0JFlUvZ%>j?5paAhm4W1PuN$$sGR~Rti3DL-mHte`^m_;%_4g3+v>IZ1}kjD zhC!mbFE;P7waFS)jy;C*zR;X(y5)IsblcwvAC|BUz}uD08?3$P{Ef}$tIlUN?as$) z4Tct-k1KXLmQ!{9Uun7(U4_BDiL#B>+S;Jl>}O%~o1v|@?Xnj0(M8&HBT*4Bc=sx|}{V=Ak~_YhXF#6eRVun95MBJF-)68x)m zz8NCzT82cq!-|bN+1If%M_6x7^IK-h@{l~M&Ffsz?6JDX`t_^NA zF5HMOHEi6uXV>P51KT%Wy?y&;IK%iew0VZbh17mGZr{EUC^qiey%)Fl6KCGw-w&y$ zchc1P?09s$z}(=PaYNhvw7JZ$<^U7>YWu#uyLMl#;TZz<@;|%MZb8D|3!z1zPIFQP z4#;^Flx<9%0G68!s(Y1k(gQ9!w0Acib@5ucgzuVd6W1Kv#_tSpCPrS_xNrYKUaE%K z)9$?!dpCkm1Z(zM8s}cdHy0uU=#q|l@~dDh-w)>X9ndZc+VTL4q4S>?xd6vk4Y_|_ z_R@q7rVxz2+bqa{(Q84Tnb6Dudrm3F(^4(u=pQjgzk!T?I}WA9R{y;82aB|ot;^XS zZ=zH%(q{H~m)O`++9+~ATvnMWey5!Ycq3z;QwHGBhVI-q;kJQ!?bIM}(bAn2Hn|(e z@jjb2Qh3)P0BWy<>zObFqC2YCHH-zo{fv^o+xW(bZeTBmIu{jbp zvxJNm%Ceo(DQpq3q;;I0Wy{-grfJ#kHE<)l=7R$_a-qzZ_Fsj??YC9en=5o6Ck`PP ziA`(-KPS#wn4OQU_JOP&jlH6dq2hFt~K20i%CBW0m5cS5B!}0$1Yfo{UAA(U(SyB za7Qo<3!hqd!CH#eG}E)m0Gln2TDX{Bxni_y408vrm|(Z5CLFOgIS`3KaBHClxBh`5 z@hn`9Ix~^r=B8?03~b35`)~nXktJM&>;rc zj^f8UYJuPl2U81#-JLkF3xjab&IKzFuc1JEyAp_jUErrz`tS3YStN6?Lbo_p=srj> zctM#&=cacp1I&kA_>Vyxbl@m0Si7+HH4unbRswIy4k9puK^*S`U!$X&4Bs)9DEvhC<|pL&$G$=AFG%@b$&aRNedl;{8OgS{DZ?ngSh3w zjaz<<%>VN^mEC8F7b0N(n>@Onzwn0Yba+=NWbPHf)dUs$_j{(8sQev}dAlm&Gi1v! zY@c*!0FP>mwh+QC)-_$+Vg%8|Ke$zG2jI*Lqq4 zxI<9AQ@die&6UbM;-f6a4?1&>Be&}rjCj@B`>6vV83@UO6_U?WNdBS{61iEEJ6pwJ z@dby&5~{AbjD%`r*|?mfr&|oU+rcwu$*%0G#qALTaT|!+f)%&R{wKukiF# zNS~`YN?*&xTlV@`u3s96(m<3JtSG&NqV&y5l%`|3x~<3*7Hkehu&4zyZajvr8D^lQ2A4dB6SS3Do< zQeM)vuPemA)mnu4;{$Q5l_7QhZ3#2(mL2Tq?1*F!_DhsVIoRWFyh!z96y|5)+vp8G z4G%FMOY2ryv%J_xI{~XV9Tu_kjVpz;b|GBU7HRFCIS`P6wOg>(?x^iJHvj3>6cDp> zlwAfC-q&|}2bS#45YjeV&+E#sS-@i`J*=0uJT0mZku>cvIhr$1_yr@<_%zP z*a0i}PJI41mZ~-9)2&LdbGrM2p-KwXus(MI3v≻>=Il#oQcaDXj};x>M|<9mpf= zTmOO<)sGq^d|A3qk?GAk`GHVcQa`=g5D?a}JZ5r~ACJdD9h84;=Zt zM>W@QPbbLYoha0FJSdcuv4g_b(EBRqQiJ6JSw;`FB?fb1Dhy-UK2|jAzTh;3O8O}5 zzyqR+qO93oS2Zsf+QAm9jd*?-mlL-9jM92%5pFP~6p~B$mxrA6EU(bUhCSOV$sC;} zAx|dIK!BR`TRvU2m1gT<*k&~_TLZJTFwNGJcTd-B$v3pmF`L1nu1&S?hgSJay+f(E z7=O*&m}G@QwiK?GrMc-&F@uIYwNSZe^)_g}`X&X>BZ|~bW4>V?_%)Zz8oLY}n&$Ys z4BQ)lX?h0kw~%vY2JQ-!pn>DxFmQySei}>cHgFt-Zl%ul-;H@`;KtKPP;aJ@AiaGJ zT-q-5!OF-814qtE3}h#>g26#k7`SQn1q~dtwhi3kpxq1{iSKFP$onVC7?085@tI~T z()pL^Y%BYefBDQ2h-Vr^z1PZK=W}lZS=U5Ne1`Om5&*(tAk#TyG6#6MhhzB6(XXHJ z9!@e0>Gpvk9YjGFY!vi``(a3b&^7;CVjd{wBR3eZ6l(|+v|&HDzXZ<|0Dp$iK#@WW zl?p+Z>4HU+aYKqEBvRdHs0wboZ<7gMQR^WwF-YUVIt8p6uUsSQy zG3ke(qr-%12AN_lGpOm)D&dlYT7K`_`a-XI)N zaLW`p*qWHbu5*|zh-1Qp18Yh5In|U{S)w1-quiN8Pb+{jX-`M*vZteW*~%l?yOfYA zd)G2W@6rW~-lfY)xb&jnz)G%DulMNPo>+;gA6D;O)CM#AP;9Un%vT5V)rC1^ z5OW3$^7*@`vTt)__|TIA^g&N7K^6OW8dO0l;YR!mjw}z{h=CiiFx`mHKOJtwSF2BJ zuJcP3$4>K0`_{P;V~mZAzYa4H{^c{3#kvex*)vobnEs@}M!i9ZYQcu6);t4D|DB5I z&x*jwd0=MRmQfGYyP&kjUmAQ}r+ zG!9ZUe%?-OXiB4<12#8vcF6_!rAkL?kG!U)c2?y%fr8<)t&o zqfC^dDAT+q4%)&{waA#nB_I)?iAta z#@3xv7}O(ro1?|u_5Z037;V01xBc>i4~$x8&!EHA?$F0thA5b3+Rw{u94F~T^y@0i zGpg$#vUloHt^1{J^K^Qo&M!Q(?oC*$|Dz5N*MvEtjGSn;C>b{8D!bO?h(eg#Nk*G5 zDdvYhIMyN|66nc$EBP`wR}Sh??w=mx@x^#v5zjudl7*hVTysr5;)3gbtl@fW1kbdW zJMiO+GWrZjF8D#xjw6puLbYUl9C_3&+3o0CJ2659f(F8&SDzmbWI&0q(;=JtBHwzC zMzJ51Ilnr1jOSkAf05h9fr>;}wQ>0xFQcnS^5TdCn2b^EXgq;y8Y;*?jN98Z2$1;_dqJGeC-2-+1bho`b zMZGc8QXH{)@gvI_mtk+o zbD-r08>$8ysupH6^iywv2m7YwB^vsPXV5CwnzIKiEeluTHv}zd{`whaA>n42B$PmC z|CHvew$p;?-yjw_9jz>_B>gGfm?JibMOpwMBE+-k&CXaPnEVTxbd5H@s!zGiwHp}L zh<|4pR;-y}I*sl&vMN=l3$9bdcy$Wk`Edu2d{~jaUzRJ}DX+qc=%Ai1Tu;YA)xBSjRy`hd9;Cags=XF7bK8We`&VsJ`r-;D{^TH(I0z*!*ihn8Z-XQDs>%`5 zeB^JZ?~Y~kr@zZJgFiar`MLg`)$7z)H^?ZSqWGz>@eMA3&`lSS$TS;?MENN~4CLP{%4rKYJ1K)2W~OFCf=7tCUh|xTd0p>#~b4aL4sEyFbxGAD`0% zF!oJgiix=1MXLsJy}>TWO$&6F*B$W&1&A=^VA|olmT!63 zo@C$M{k*#e8U^op_dEpAZke-lI(&d;zT3ATl6FuDeb|Eh6B0;UDnAAguZU1SzbwMj z(D_|Z$p@bRZ}}Y;r4@+1qq1uf;`eHluMH_5)6j9i$E)?CKg$9%Uf^PedmB6OKELC9 zsd~9ycxWs_x20T|BH_faC?_}y3)djWD~k|?j=48qwg?;YqKRCXM#jV0LN`1mb{1()`Ps!61Rkp>H6d5omKZv; z%TD!uTbEFar?PutGwV8{x0ohP+=hhNH3(>7|0*9LT;VQ&;*<%}wauWvJUTsgc@a+=LoR^Wp|KT&qxPr;)FM~@QgUMXjOk+L@hBCue%?$= zx`U>%+!T>1DO)RaX(reY)22Td+%GeT!Y|k;{0lj4dPDiLac-9s^S)pW=lq`?A|wA` z^(y=h5Ay;4Z}u<$bq($&d$IYz?uqT!U3B5bofG>v?%cC$^TdJeo3Gx!ee<5(SMkrp zzFh}5?%F?em}oX_+Pr)3_C1Go>>L`}wqwVRT^DWIPVyW*W~+GEvG34Tdv*%mvv2R! z{HJ;B(Aei;dLG8(<(tP77^3ml~SwebS+)&(&iT4eypCW-8e2%c+{J&+*Q($VH02c*h>oQVSOOHc$G zCck&w}or=kOtK}QF`+_pj4sjN^d@;^rnF-_0Y_Eb3)Gm zq_>1fTQmABjz39iMxR?)!9Zo01gwgYD#y@O>^9<6h6;Q`IGD|-fhq>jv=ETBQ-j`K zsUxFjWy=T=mC`z)^PQ5BQ9^p#hBP`%V^1}szrt@uCKyy8^)SI#d%tt=G$v0k>U9C6j!jD9w(9+JON2>NCL|D^*Qx6%D!q0K;5(g}(-OBHQZhClF04l4d0 zLG^@zLiT5@g37QN{c@q<+XSI?koxaNyK>ycWYuw(B@6zR!NMn4)!bRK-&*MC1Xa#b z1^zj3LZDk1c+l>CE-2|d6?=a#tKJP3Pz0;DFIB09EdfnJW4WL~3F6_ZdCnmk*VU2CDcZppaSykvmCVA^QlcP!kNSQY%n+ zEram(&U>fRTZZ`aRo8uW543{>5dfNG{?P%|gVD`ej& zRTx;MR-o`&2I1|U_usrt&=dv=!~ZR*23D!PK{ft18eL`R1VzsCm_d0BR9*um0WU3P z`(+)VioLvGFmT+&^Ys=aQXSun(I7{t>9@wJ23mP55vbltKvh;{cz&t30$)*5Uu$)! z6|ZNqsupE}Z!ftGL~2V_rHiZ?6dX@T95aEaQbtBuf*m6W^kUi!m^Y`OVnkK>!oH}clGY0nKRO;STk-*SEA8HiuR!I> z`tWQ=M)_@5VX4!CmZ{SucFZS* z^n!dD2yY3gZ~H;QcUtCaL+Z!zthWtGQ!!2X$~gP?r9c58QP2-k+46Qn)>a@l0!6i& z^L2r7+>d6jXk4bh|+NnWXnM2>P<3Tl-pda@YNKVTRgEmy&%7(Y! z3g6+Tl{(a2yv0)u@sA=pzbb8AzC8tyN)XapLZYgjCh09DPR$a8goQFDEaY%OXXIN# zk}N{1<8UF>+s0DT3RG(AMOA0onMwWGElBv7rm-X>%mq4kNfx2nP?7tT#QPvoeMv~A zXAW&D2GT4-)DJWWK4PQbK&$tHgtVPhCSu6wD4% zZ7i$W3g#crItt{TG34PV@K$9Xn)wKoG*Q(~)5w()B|uC_EqZujxjdmq=37F-LP&KS zE+m@!Vd?d@q!md0M=VPF$%OtZAhoRxNeY;zb`;1a970oKMbGRE1I8>@^wKZSOsq&s9w7v^G^+_uC9DG z&jZR)qO^J54LQ&2Q&afQUAWL+H~1bU`sOI^^E^D@lVUe7JKsF0qd~R$g^=1?AcUiB z$0R%7_h1stoV}nuc&qm9N$;L%!tGG$L4J>0E^h4XKn-ZS=kJ18QUpJUO_HAIrx!Iy zm!gQE2e%+qTV$A!sJtTc5h`h&(4+8HZ6&0)ZAhdtO%zc6l~y#t&*fV}!qSFNM``y% zO6NU-pj6Bw6Uif)=p|4oq9hk*ap4ConBITfw#s~U9(NmTn#=tLJD;{=*M*z3-C)=L zjn{75e$DQ^+-87gOlSWAE>_q6gHOGGJ|_H=?lbTu%ra%?HQ5*&mnq$O=p(ElVhQkx zR#)PUNwD5e^2=hzWD>uAIU#1YsY=m@L{ZY`FL0$$4m8kfx7e~~R;A+L-35InW|1D`~N z@Jo@i>!%i($nBXck=y!#fyh-kwpCO?HS-w-9g>amJY8v; z{_w4gOFLg@S_#q@h*LP_t0!~TE2ynbGb*Q*CaT(HyX!D~#rVu}Sw@~wE(dy6A5WFdO?e8u}aOPGpQDB$W|7pQCiPlnd`-ve)yz2 z+HWO&OjEFGCU4c+Whg5wEBZi^624W5xr5a6{qRZK^m@B8DP0XnSO}?y2%TwqmXK(k zUr7DOItneFX$-z8tt}m*nQ7{0LZW$op+bvjZd0YSW0Ph-zXdBnNc7DFQrlQUnET-q zRWrd{XeniTLA~;ow0jza$lK~ zZT#xD;n~$`(aU`o40v!`tPr>8f-5#>?VIIAdzxzJTR_DUj%J`gzB<5n5uac8lhe;NG2AmmsGOAx`g<;P*e$WBwI3H%tPmp<(DrMW;ru6c*;#BBkOv*yX=AQ16QToa#f%m<<=9#C_&zANk zB>i6?`n#&Fc-Lz(jT^gEw!OtmCE6RTgqdjtD*0py+i#VxEE*9iX%59flabM%)rg^E zPK}OhM&II-I&6kFkfl07>-DZw)zz6dC^#!yPDr%$g3iZVwT+PSwITHZ)6|p4V5vpW zeKPIhgzlFRH#8|9p>gAghXE2kLaMC|mA9g*ynUvZZASlyEKAf55|4u{-kn-y0O&%8 zakzxwxki~SoX82>f<#rmh3^I4pP&dfP%YzpO7F{A)Hb9d{{{KfvMT_oEFrxmq_

zQs#RcAk4M>zyex=W%)SAx&!Z21D9b$-QG;w--5=i?YAIJ^%D|JZK%8zzUpn^@28Ol z)olAo)SEX0r3&3#dUIdtO#@Zxa?k1~RawfHmH6I4lGltr$F&x~7Zh$VP#Gox*%&XT zDthOA5%DTR1-`b_W}s?2eDHPNAa;yed#f=jI}zt(_*PZTHy8w92ROlVQGeMC-i%g< zJq;9575Eq45K#Te(pLs5uYnqazb$zUREAEl%B$h%%%Ebo!yLtN(c5Dp*NlGNx=}d3 zQwaKQ0splF9JeliHltW7W}qtR1gi|9t;$fH^0RYW8rJFv*I%+?4e-|r4gW?^$o{it z0n(%7Tg~ta{+?wKae`IN#|xI{mX>saDrczzZ!39UKv2jGR0adpYIJh+kb%n3308SU zac2e&gGLVn zug&P6m5c_e_#~i^S_UJ2-wNsB zgI~<5+Q&uzPgUXjOWO=o-IIW7re#nwC&?>h-zilXSfy5=@LC4p?Va~7Zxcq|Kwx9iXasRl#83xH0XUZ0?|P-?h;| zZgPa0{@k2e;LZsmP`#6Ys;tWJi>2NQe053vb*n?IcoUOVwI~z(Di49?Y?2hu8G~7W`4KXrJp#Q=+`s`oPz~VqBVdy%w&R! z0WlUl071Pihjfi$9AyBC)BDt>3$dgRmkG9h6pX^cfEtw0+S^Lc=17Dh%1 zDIXzFKue>luuhPmT8jL=R}6~Ivc&};6eFH!jQF>Uh7k|#otPyrzGwb;k-MO7;&ACx z1{fUjCH026ZazvHM~&E2e90oj$8B^}9=zlL7lX$p^j@*Sl6E=@i|+`DcS_nOQ2>O5 z^p;TJEYu7Yb*FL0-z*Z&*t2ij!3o?3ISVCq$tR(t&g`&O>Kgx*5|KKxF5`edoqY!r zXQz|Uo0VL;1wvx@V7y2jP{(-U_%42%p~d93?3kUNKlrIR6%hHb=s{@zCEN%a-5yLsr$+1p zW^;{4NP{;y#J%DwOGqX9L6Rz7L!x|bNLWhR*@>BuO7u(9+jEgmtaop3BKWZe6AyRC zlhvEiSBFPupe%%^66vHM+v6E1=p`?d3LkjB9rU0B?UgPv(~GM5DeDZsNF|G7WQW_& zMa4Mho-OMKsdvlUwh-&>Ilv<5z6o6f=u)eLkouXB^0m|Smh0~tg=%rS1{2Ty0ZHMM zt2hXWPY4NPFX$S)6%B-xuNSl@@exwKHY8e^CVcw7y!Gwn>aGK12KDO!Kr2`!L+MSUt@slI`jf^ydeRPle+H%q<)SD)r9_jtYDO2TFPWo}eVcK&5_+#o%e+ zS3~=Lf^0!E`Zp!@O9lKUK?a+f(Qg{Ds{fAxk2rq&{(_P_LDg!h0&Pp4^4dPU3RH$F z)%JfW!?W0$q9sAhcR@hx%X+c56?xR+S297Zvac~{>i9-Sg3|W+0iiZfb-#rflxiSS zIo3*fYqfLecS}YCRlIlV@0VIX+ySbXr5+Y&m-Bm?E-{M*PS%_9Xg=g>4(}bs-oT?6Pl%8nyB=*7CoKpzIKJrd*hOVp8i%GNIE>m zzr+&eqB#_XyV_^xF}~;X3({l60GMY8CcpxAx&8wz7SG@>zODR9F&&DE^~B%$1z(0X z7eq1a578`izNIkMX=NH%Alg6W3ron!eehqM7Tn)2P5j(`+l|?3h()A1K3?oDUjukJ;P%3BI!yOw$i_APo8HA;PGN7eHCr$!se$vk8XtHdHtrUo}RpqPa ztv0@>txk)%QYkTr7L|T%Lvkrf+L4JCi9>v40i)L|b}{u^aYH+w(n`dlL>&mJUP7AT zx6{ho0*xClPo8fj@TnhpZ-)4rREd^iCBFIkTbd|h!hl^f+r&<+08V1 z{wk&Z?TL-nt(btktYhI_^e1a|ocaS)6H?k`1uDD64wc2%RGx8NDAM*=zbKie+yBBCC7^e{*iPYVA7CjFIBzm|XOqTx!K&qRN=(*X`{3nFbPR zGx{IlPdG@louG+QSE@+p%o~KA1;W%QLL#;obUxmSlG_>DW07VQU|>IdFfKE~SX`e( z5fV{dP+=FlXiei0tAyP0g`(=w&K+OsyAPHOAH=Z7t}!IXuCWgzIdFWqG}S<1wj0R0 zz}V}A9{Li8O`T<+s{RC#F?t$(`lkfhf@bvZOX^n(XxFW2w+=UIX~$+W`X_*6*I2dD zs}oeMmMZZ3#4Ngh&;cq#mHOtwdCwsTE(jrMM*kgf>>7KSw-tHR;$LNgT4k5AQBa!E zw>lDlb_^BjTw|`AW~VOQhvvl)`kCFC8L2V-aGZ(%&TGs3fmueY8mH`RXd+P z#P}S6bqt2{)}JT#7;(6L+@ZMX^9U=3@0Qu9P=Z0Z9e5pRD`}n3e@6)k93j2!1@Xi360;{~2|_AS zAa2#uAP`cCNNYx)5bPTu6M>#?o2akr7-wY)@GmWiSJ>W`e9+0VRaudY5l9aVIzs>bVhW`D1^y=q3U^ zFXNiZ7{BoAb1KQwulk*IA^--iCjxemY(B2xI*Y>(jT*Jj_hHT1NfTVAz zQDo_SB2lIky&$##I)Q(no9bRe3j48Rk*vgyREIQY_kUJx9Nk>eyn)}uY0 zz$@JF8t-~73UTV7l0Jzrc{q*N(qVv&_fEsLbYLI7KsvJbNG}^#$GLG;oHs5$0U47( zBoNv82T{jqav4?SV!M)UR&$p3%q^3p!(*<_coFVkgK+&vMlr~)EC_)cFpQH!+yx^= zGx>fPz7>OvMK7k{x8)_7 zo|<{5L{{c7uK-(Hc9WRHx;O2dY%XUmYWRhKF1CRoL;?{J%C~j!C*D3V-x5*@Lb3|& zwDMNacI4CW5-Mq((A9XW;eAS$Af$W+x(R7&2O&{Fh;=lh&oA?zP7oQWE$|1WF#iDr zWw5yBKRad@!r1!FIkh=$bpUUL{fd#mFFJPeU+@|QSsXz~&q-zjZt_VJLJRNMBQAB==F`%{2;@LSm1 z6B2!A=UYaOrQSxktD1w6r4(;8J zuaM;N=Gp3j+y4c6p!3TU^Q#9mmiY@#0E}PX)r5UcV1!OxfDy_Pf-&NrBCTT_(vb%_ zsRocL{wUBW(!_7a3v zQ|UO!aylT9b2<}6MY+p@kZQ3n@*?m8B5b>j3Z0k52`T5~P%r7ZB(V_k`VJG)SoFfT z89gVxu{rA~&_j|ILZXEb@Uer`?4K%q^;4OPkY3vnTd|JFnC0zK8jUAp4TQuU?KDw2 ztIxUJ;3Ok5I2vHqcUBMRe58RcO>%x0imVxW>O82k?fdrb+I{ur1G^`-UpF*_vw%Bx zU$p6Gz<&5|Y~f zbI-1>XUDU7;>L-&!qp$oCN;^%u%c<=z;qo_*V&Dro0{1AF%goH)1x ztp^NNJhXQ=9+iG@_qDt@7pd25o4DrSHf9+EI!eLDeftj*{gR=f-FqkYZbUOD4sP3P zX*k!b-njB2_t(-BF?TXs56MZlB*s-2#g))sT7d^z< zuoUYv-JSJ}*-mb>B2z@|*s+mwnR^Coj+NyzwTmba`L+N{EGxYo$ZT|u<(n~YS)sx2 zjUr;h$Vr5njlBAt+P#7bzu^g*7;5Q%*e0lJsGH_fQ4Qfe5>^CxBXIL#5?iyOYetYoYhTvzj~)(Gd^KM@jBXwxfqJQJFkblZuUO_w{Mn8 zn6Y*;6?<^szC9D0iIMuRQ{P^)>B3DHOk2lNJBzN3SMNT!@d3Mb?A*5PqKjL!PRok8 z&Yl6jp`mS8P0T{E*4k8>?{P;D)f+m;P73*=I4_AyeZFLa`uf438UxPXpdQ>8AI6%A zx$GX*t;b0SxDo z);Px-jq_iaJpazT%JTty+~6Lrq_4VZ=Yf5*8fbPNU0C?H69@SqSUP+Ecj0)fA08W# ztEeH}VH-CFc9+IIXMvN?-ezNW=>g7sLes6GpG>>^X((deRsq%PUO(ja8GIZ&8vgkR zUx$;tI#f7P?q#k!d}6uoN0*=)UFVoCusD2mhA>^~r7Xo63nDRN$LT?N``|#O zFcI&zo00x;URB4A-TUt0nq$|lJ%=W)nH{I?=F}NuHKSQHCg0okpd7|^|G{ex?A*qA zHjqf;Jn&3#>sP=hu|8EzHe39g{1!aKDV$cBR%=zsR+;F5&=Vo+an%X)7<=YlOijh9 zIpJK6`vjQt*ycK8VdPkDMZ&0!oy1rxIGyEJ18$l>A2Rbd+?;Af&bP!@JagG< zpu6lwscbD~K-=vt0fpi3$DLYo*)XW|JCQvu+b-zBy)*mjbI zW?}yy2Tj8q)HL-oO4#(T)P|JMDMWx~sm{~A9*)gLfH?x@TSg0#UcjSZw$<8vuBWEr^Xq!Qrq!LBcI%fJdJg5%C(hZ zHJJhdKT*Rj`kK`yLmB27Zk}dzEoqK6DPDs3Fp_|5Nd`Q_*83o<^;B(^;Jpt_MyQuotwst; zBhiM91y1FIYO>BBLpd@h2PMarqk_J>!JEWwHd?db`l@g*R~kCzXfcT6$({rAe6H=YvK$ryhD2GfHF2^$&c~dYnv?+BT(r88b%6N`Qpe1iMrI>yg z4{tNen3aQcpN)m({wxFpBE_y zOl;rn(e*A4xTb>xLYau=SHUtZLYBX3&$hj;@Vgqkmkr)nMm#-!?sAfU%h?>%o_hU{jMm9q>_hz@<}j03%9tTs(5!-&`(cQQ40T zz5PVxTlWM}nb^N=`_4X`GV-tBlpl46>CpcDeRak0?11x&2u!Xk-fm%+!S0E9UYgr| zaGyK4n5RyEvtd1{)qLQtV-aboE;-XAu8AqC?eW861VW(Df*zZMgLJcL#h8!gq%wp5 z7CNQk%oIlYI59;W<~lPm8R|RUC!nqAY3|}MOq`OgW9^)&FaS=}z+{Ujny{29E67x| zA4T^?L$r+OQJ%~z7mv}HW@x~(^USk*=4v0;ZCp>T4vuJVX@)F39IP4a&VfGCuEP1< zDu9jnbF)|Ar5xMOK)PeEfCd+nRH>q)Jp^Wvs+NMu6jM`F6i0Ngz_r+s-3%SHIpZ9h zALtP)vMBjn#)>vyyKVb5yZ25Vf9l*j`lGeI^xADt-Fej^U&FW(#&p}EJqL5&J_a;R zEMoVWj;Uen=LhKf`2k(Y-TK$r{(^X#*uQhTb{NEA0KBo$L@L-OtukQW>u;&scvt{g zGv*AqiZn;{$SYgE{tU>@CukWFYcEeO_nI*U2AB}psKLKxSZMv+n z(#$(0y3M8S3h-41EX+Az$^*kW0KQRkFVY-<%BL{6lbiaz8N#w9*~zR4O9`#Z3Ns}*4T4gr-DgV-#=vvh2MZF3-yojL45^A*h= zuAj226pPPg?O0ysH;-8qIXV_iqlgV2v*b1fuE4T>TRta04gzxzHOu~n zd0j~x?CTu5cIUO*x9`7Ev*Xl+==;=!{Z2M@Z{|FoQ^^N|PoX!cpETL1ez}FmcPNCm zu?1Z4gHJiY;!;$}NMMf}jr&iIvcZ&o@Eog760ujO5LUk8zF zbd85250i_oAQ$}!^g(OQzMQNAi(Fu;Em#N3kA5$ht4FYm)N{>5_FaqAPe1_Xc-MeA zj>PPN%yI4hIZ-jY$Q%gmH_e*fDhBfhjBMFN6?TXwFkBYGs}x+|9x^#78Og8|Iux)_ z^0RDlo;hWG({j}*cKtG(uB*hF%|_E%%Y7SM?Ck<)+P0~(b&dW3>ERavX)FB{K6qNs zIqivBksF-58D3#C^cquf^D`as$%7xp?t28e&mrBrbqX=vdCv^i-RErgy*c<(PswIL z8V)BzzIvMQ&dJVnCO8v24~j-jUasUs#*Q^>QUf!B7vRC`w_mgEfWXX;o)=tWA_L+p7JTa|0LX)vT$7oq`OibQ7hSDe5Gf0`S${n*yV#jlIjf zr9qeXc^b_~Por5{Fwc3|Ntm+QxM6hY9!eXc=c>_RwqBzXTmyA%lU;d&UovBVzaynG z{RRTb!<1p2AIT8RJn6b?_g&|!c{B4gE5%mpGFZ~kWdKu`0Zv^8Sh{S-zd@J%SSQyh zkdj=tzMA?TQ^8OX#*UIRmo_u&t}jL`wh)HiTmt$bkV8$_yWXsV*3@#oW<2H^yx*2P zt{BXCx@J5ylm})vO>tAk;qRWBTu!Y-4Zqga)G-)bTBi0?h4w9`D&PgJv6&`iULM%N zXiHap+{W-A*lxaV9%#FF>=_vTav{Vg+0s*KhN*nx7kmnszjmU}f0d#Yy-+30wi&mB!a9%I$dtNu(O3CaBYG*WglvXz zE8V<}C>^yQ!Lx>)ma%xot=lQA^|ZMFAozsl!Tij08Zv}4G0c>oX*MrxnHH);BNYRZ&xz6BP zXY6?2M{p9fHg&Umi?p^7UV8Yxf??_amm3{JCGQoOUDrN@(CM(#c42RcaxMi9hW3Zy z%0f>pY2IdE?2Be8yij5l!y?GZVMU-rb0h+Jp9y+HBxTHExEZ&+h!*G&bUV<>(h*(H zDb`pXql`&car8mzrxa9e1>rOrJ$@DMRkTE>Pi?A&me4E$+tY07XBXL_^>%vBJtNQt z2qc(?50K~2&{=?(#&dB}$AJ+>(u-oy0HMvcsWC=A{V<*i_np6hcD@{+4Cy4Ndz@oapp3aX3edXZ0Zm z#TmT$rs_JTd8uYNaXQxq2c6^@bA=7*TFJvTQaWUOTyqLrICf0)K>NGWgHKDET)V+nAzP}Rq`z#I{Br%Y*~B7isW>swAZA1=gFl6qk@?0Qb)1z-rbNn5pTB& zz|FHhK%+P##nG1#(%iiiy^-r&^{t-G4)lQC zC$#~rP|OjQ`1*ir(d==}Pc%#PUadAr_c}P*cD?AI{Tx&GuSe}G8px)_8 zT&XpUKiPFl*ayDPgy*QUKX_m|4pQC6V3%&L?y_T2_<&tOsN}z_4=IWpX?u!B=qO-| z5kgPdeKyF(#wSj44h_yZ=pK?ej%PNV%Ucu+(61m!>TMep(zVnDCfmxDW4^c-dV@H) zWM&yj9D!U6H>qPvJ#OZGQ|zh{Gjx%{Xfy&ua=m4p>6kiML@O!v3YIn_Qgn`X$S4I@S+179i;&|e_-o)y&xOI zXB#6qE=a?i;g?r%{(u{W2lI!SU5Rtgn?GDRtBcpBHG_x^PGCdLv*hy6!DM1)^M~%p z+*{XS%5eXjF=%;^5~nS~KL+QWGBu26${3#|YxWF@q_@IUN+Q)8)n=%-BHECDY4>!! zkw@a1Dv!#Ar7bTjNyiF#H9JYe%Dk+RItKJXt?=#(mfq|-3hr{Xn}U0zw0k>tK_8E2 zwv5mGYjs!x5zxXQMGm4FJ0!BHrjAi5GjK8mEv5%q$4X1Xgs>5o33&*wWC2fiy{;GL zajXX8!<9xTPW+N$;t6+;YjormE?62kOK|2|Z@=vkO zfH_!eMwR}YVMY<)xO&-%D6+J%&pC{x3vmu|(TO_2od{S!naj+<)&lzqx>!Vo%4q|J z9aE3h2w*@T>zDi(-|3|@w+37INYya*%##b2$ukh&q5VG8OPj9`EgQ%CWF!#wnrALs zM-(y2?0R!Th?w_v;6X;;93S>3ct>MQhl>g6KqT)j!%U5DR=T{PqGPS<%wc^3VljrS zDMx6PchyOqeOD9xb2e1D6^#=Nwx7ENS!+x<_{{WpALGz`RUDlj&>FOJq*H z-8cR2ULh5)FFc!_9|Onvyl#Tw$2ZtzXjI-yY;aYNdg$3OGsi zb3)3NvC4>wkd8=a#a1|Y+5FNdt*L_)80gfBWjaxG#@uU4+^lCK(mBJ+_Oe@z-`I=5 zqm_)aqZYcb-k&ap%^9Y7awXIxo?V|Z4o&xRW)jGHG!VZTQ%(dibQYp{}$^eYsB_y7P)3ZzLlEAK7u4-}4kKb#!xa zbcN;=Nhuc(q{zgk$w<&w8fwl6yvyaG+b12^tnk2_f~f}`pF{4cwa2{^$e69vxcXyj+Bm>e$tRJskklM^0J9FEjAx#iaF0? zC&>bk%|zuG;v6h@hNYeM#y-MZz4+n6>GsgBH&1^ z;?)XEKe+$3Mb2H&%654X9x2Lxg%J3L3XN`VZa0@XPx2Whf<;qP zLK_&1^$Q(Irdu*W%h zQ-jo)oScv!Mqz)9!a2f)ObUP`pyH)X6|-X~w1nqStJG`4SxIFpW9xZJT65X7wu&o}ZdXd}9uyWjTK;q39=r_p@{%8`Pt-wHP44Uh|uKJ zJKg=qpil~G=GW9Sz2gD^|14))GL#cckabj=vosAQ)%+kAqCj0C9>!ZOa>m;4`?G|*_8o4^2IvmJF^GWzs9`!EmF|Z zJ7Cc;nkY3ycLDEd=)pU43Y}^8fMn+$xCE`uPkojAhK&XA`Zq_EP&an9Zxb zH(Pm7u5ED(v%Sza8a{shmF=bX!^9 z%$mX6V0+2u_f#SGY7HcP$Ca}?Raic?r@8y9{vGmtvL>#OH)oSv#jy!486ejr7|&*c zy`e0nS7|A1ntw1x<6 zt^)+V5p3*4Ff66RrW>?g(_DEGvGXTY@+uHP3E=)t{>8kZy&Rna!@vh6gSogHixz~w z9{&zEXPP?uueJ)kO80<>_0K;7j>UlW#rm_0jrv~oWbY4=y&uTIHICMA2AXtHJKb!~ zer#Fbop=I2q}ON17F9wi2)%v*q4)pXdVg@I(LCQoNon1;XLg?@?NsmU?*hM;&#C7& zX_@Qy!3;D*&opS%Uc$Lq9 z3*O3tO(!L{BgT0fE6qy!z5#Yn-Qzv|E!NG_@y$HuXb?5%VBuD8>th z3-=Mit1Buq;u!3JiLr@wS=HsGStA}XkL$ZlfQ^Yvb;LSAN3E;%okv;6@0z`maZb-`oYgA?mvRPwRIhCIae65nAXm2#=6l;0i1@49Xvnd<(4 z;;&6(M2A0C`M^08@ z9kr^)povAqXyIUuG)?;9z$6`sYZ)={d$!{e>e(!%cTSVOL6d~fsBm8>#<9n*Rve&4 z6z^S&EL<8p+RrAzZfRvbcemK`7dfn6coW;Chq&H1wH%KaDw)u|*E~=H9JZEJmi4lp zJcX?rBKMmbLl{Opo>U+O!91YOz4j->u0v#Hoyc*$F>!jHI4vYkc6}J*Ovzfg0PUsa zf=7)qoo^h7z!4LHo>wPUCmmxJh6$U`!T@z^%`N`{5x{rodWnFTKiRhSsg6Nx7=jST z`A!Dw(CgF1pFyoQI_gCX-)D@rwsuE&Mt_$x;JjX?y2?%n3Aw{O=~sTWl|)w|GG>7j!eZau>_jlZ|G zFDZlF=&#r@lFk$NDB(fld*Xj$e9!9~U+h%U_%NvkBxLPf}Pn1%=9?YBL+Fk(qPPp}b;9(b*a=Ea%ao7*jGwU+C3P-WAcDZYwK^?+om;{2Ql z1x6-1)tQEB%b3UiR`)0;^T(+)G7N&04!dReh&Y@YFp-RxEZRXkeE@Bvuza3fhDNi~ph)NXQN4Y# z<3nF&>sAbG-I20&RmktKY~5qPcFpOjgJkfuui6Y3XK}8NjM1o=@;Ddylbi>}(KJ68 z2dOYm_ZqOn5n_iq+cy1_p6rlX1NuOBfg}rHR&U>Im5wUs$d3U>kXLw=!18JAget1!L6=&F|^XL7F@6oX10nyopC%lZxTi>7sb)Nbah?CE z@?7n7dqaoRYmUS^jWV>$c*WNlAb9YH{RzGN~&5Q)GRPJy&y%a;u$is6xNk@tsbQt-Vk`u z&17iPK_fpR5fOQ}t2~k&^t4%d&Y^M-EoDBQe zaD-dK`3Op681B22a=O)Ic7BcsAsP)CnDMG}*~`&78zgKq_*H4Z7FKyS@%qrP23 zO3cWuwbCaZhYL8KGfX{Fo$hIAliE>A>Ef0#PJPBTGlJbwsAYw2_2LTCEoP8$el8@jfRnHubDF? z9#X6DWL%?{lJ7VFHpkmG5$qQcb*3RnZ*Fa~6cPp znY9pA>caFJK$mu*)+urvGKCjYvvl0ke41msZ^2rfouWUX?f6ouS!Zgp@n*lZgJbS` z@-a5}7&Kj$*=TPJyb9bnr@{GO+LM|+jJzLF*DY_}t&5mk%@&o4eTS(ak8bwH z&~@C&79KjN++f7yIs?1CcjwtClWV7w7Yxm;7^L=HacL%elylIKQ%i0zTy}FW95mT2 zywNlw)OomHj6rEvLAE$MEX`lCNt;dr;2@IO~O zE6R->hYlbsuJCyl1X8!fg^o`Z5T4_rv4i@MUea%BiSj|NgLANKAP zS2(eI^ufgt%-G&hVTHXLf&DWD*TXy=3iG5dFr?b8%+qQsJROrmM}ZYhC-3ac6ZLYJ zdBTv2N9WE6nJdv;WulOM($^F<>uDguEV!iL)acn}h}z}|@sa~~pE){#gm#-FKaeyX zb2QjFe57vKIkbPycMd;sXyoqMIZTt%wR8CUwzf2{XJc=i*uHJgo~h@-KjIVj8z&~N zI`Gt4oNlbY22xGmHTS-a+|+w(49!o!bJ3XI4-fw{Ch*PB2k|>!ABwTS!rTTx4({7F zv3<9HQZND+aLm;muVHtbpR4qoZ`d3JCJ~KXY0SRp8oX!U^*db+bv5|c*x)-b(v3Tj zxfZ|!df3V0u~mi{w2RyvA5Ci(X@4BrzrSyP{Bhs@IJ<9uKryO6UTbR@^Ls(WtYV{g z>-9!+J{>y*8J>k6%y=Y}*QM-{gBy46eJ~{7W&aA^1H7Rn`-%~*c9%H5#mr|5U%=Pr zUN1h=I7Zk+D#L%}mSu!4qH1t}wb?#5cpybFicA^CXZwhECA>`@;fX7p{iK|Br)hc4 zmXJ+U753w|RU$Mprn7QFt`G7ls zqZD$(2?enthqklv$Uq|CX~Fnhl;;w$^fr*oKK5i+7RBdzTDf>*5ppT8hej{gbV&W5 z)JZ}cjD0iorFmUt+_8J#lqTy(+gG{%szbYGC!o9cX~`j$5ui|Ov8`R1gS)Tw^$A;1 zKsk)+uIsKpu=^m>@gS3a@dk+X*(ufthr*PLTMEzEhY;~dGskZPfMLN^%mx7r{(?gU z&{w^mr_g56A4?)ggIN6m;43sAm0lHS0k}7Po)W5e49UxF82Jiju8f_#lW1LV;OK&+k}?^3-&6Y+alcNJww!Dhcj5G&N1*Ege0+_#w; z`0Ifh*nQQ^zCJ#qwZ`jl)BbEPatcLIOMj&lrc?xy{WYgU_HEOx78cV+#P z^f(k$Zbv{2V9K+PF@46s)ru*0Hy}CD0Ummh4eev+VrWa3wR+xE;^Ol*eVfS4Z|bT{ zfHeH)h7iA4(d`xF)(&6!g`$A0t-%M5o1yQ_uNUh6&00BZTFMtw@d zAC=n-pnI3>(kjC@D5FUgZopGOhfxXZN;ZiVqp&Dn57PLCSi_5Yudi)- zzZ0ePdo&;ESjs+~

H>7gXK~3O`k$5!P@0@0A$;5ROjgr{WoAVZRv%aIiVFEfzpi zMgKILYNMv6B2e`+MnWYYe{;*Saa6Ikd5m|8cymcJp2VW%C$s;%+KU!=+SDy)J1Vxe zraG??j=?eZVF#of#a4GzLC?}WO6SrIbV1pTXZTlqOGSHfF@Y?-+5sOvp*1wryt5T6#-8SPBPb)HhL1 zle<}q3ou zN<6aZy1Ul;LvZ#=QI3Xz$dl{siZP9^hlf)IYNxsx02VnLv~f#5>7)iRRn2a(iA?Zm zzTv#AHM65oLc&iV0)jx*N3Ic|I>xHWJ_6m+MRkhCI$MG~7Oq2g0PiGyq<&#Dq6aZV z@Co6k<6|a6Kg55{(D2iTSB=;+l7^oD-l5Bm_xF5$tv`?R0sp-N&s;#*vU<(dTZeBO z*}MFXEg#vkdT7fE;bfj~ArI-;NiCp zKbo(*a9@V^-^agqA@3WM_pz^B&Xzr|dFklO#%^Eo@};jh>X(;|9I%Gox#g2v{%Xso zwtRZaXSRHH%jdRQg`}4_p78#m%g)E&cz!OP$MMWGzJC**58&@(SC4OfUh}fCD{dQk z>FA?w9o~U1e57FpKKvKu*WNL78QT)i7j!&dj%SV)^AP_N@q7XPK5q3IwD;k6JiJGH ziR&xqvlk*S`zD^>jAzUg^7$Rrb0?pii+SUF@P3`==ksUq9DKv)uXQ~CC!X23OYx8I zSAJmVvJU{>vii}Fd0xZ*ZuRzU?Cq_e+;V5t+t%0PUjE}K|0F9fJ{);eVZ_IKp7Z}? z=(2aCuE(wZhn0I?zO)`x4(ThG|H_Kys^R5#Z2idAJGXvv>tAjC)YeaL{mj*1T_t(J7{;K+s8$ zM%^KGMnkmwC3mV_@%&Ld-yb;RdFZ2hrc99L`{P+{yX^8?hglEEVof6tueptEnmAsI zG9eel@n$>|f7J2&9nbH_^Jw+{gZ@6o|1a^(v7+vS&a(06GjV?%@6OY^t+$QbI{YLJ zc-Hm*D0>?qORqA&@9mzE7zue+yT%x63F*QL!Mh{TAEVKLwYWcLriY&Hrn_e}lE=Dp zyYKDpEA_|Kz1=gTiA*G-5J3o0NwY%BDnvz5TU*o?MN!n2;-V-)C`wDHErJz{F@+UM zA$Yx6D_F*Oqmcam&vVZEp7-tBLZ;C4J@UH(LTDS;abKl;KV@#x=k2djj`A*8uT{!lq%7Xmc&U77{__MPUZ(y$ zh#WsWdg}4MkM}=$;HiTLCT|qSh_*S-)4m$(8hwv{-)W$+R34|iz-RROX|aj(R{sZ_ z0ev{(RBf-(R{ZF;X8zH>(-<12i(@}eeO#y7zeriY%!K~mr~CnUbN28feUncfJgvFV z+>iFh4xj2G)aN||L?f7L%uIr5{*pRAOhsFbf!*7`MGN(=GSz@aSr9QD$3&cDb!jbq&l z)D^rvZ}unF{isJjwbht^P2GEnF~O(nq=8UB@Xxc+QLi_-xG0R9f-dI1NSi8Lar}=^ zx92hfJ#?!^=0ZSk(gXw&8t zpW$6>`st4!kVhIgM6k!PpQoMVG?rfqbH(y2mGWzpHHYfcwP=hN`0^e9%J(OehviEk zHZr2<3ejBk=creI*IyS*-eTQV>IywX$DrHP?>Xuu2didFXG?WIqE52rV_q!P9sCQ& zEp`ukzg4RH0Ch+5e(VC0`BteDEb~3)`{WzceVMx3>32Tqr}b(LFH?8U=L0ulwQ~tY ze4nCr$NqIT`jWMqzdy?OQ`ec+&CRuR*gzQf#=mraa2rNDwsDhhMaijNcm7Q_`dNc#aAB_-zrL^Dkq%e?7wP{I^v>kr7Y?3( zyk9PZq>Q(UlX+cLWwFnRf18ain_ON5S0+!^XV}zu2@M%jlz36)ncu)ye66q>Du0c# zZ1+H@{~l%SgYnPswUOLM`%XC`To0+wP5-WtJ(b@{d6YgbSMs|zzJ4P3-2;5DHWz3k z9-xi+E06Y>!86}Hw)q5Y9;Xd++r<6LhDO7}QW)pAe!<*^gTe7n-*Dph-!lKybpQ$q zrMMsMd-_oSH8UltV)|!L-H0DuySQ0)-5~hh{qM8UZ!yQI!vl=9^zj3oNBjDH`(PX3 zUif_WX7;W0gQX1LD*uAAd?~e8`KDj`UTYwfZ>7A>XKb0-ecwztp{sL9ezV`iKcbJ; zub9G9*Dbjwf3$B^7Son_+I5NAzD(Qk(3Tb8e;zi!PId4852-GZocX*1v{(Hp>fMKx zeiTDS9e>#PLv21oo8TLwVg(BND$rVdsy5%D&2gtuXyg0n{x6io!X}S>4*oyc=&$I` z8fT)p(f9{m%8Z=0*)mUM()6_E>3`kzrubLo_fQrMUFV^v!uNm4_Z_aej~{;SKtFMv z)D*@|w~YLOyHepxHr|szoD62Zr(As=!*pMN-{`Zlk#)B3ex3vv*GU=nu8j`}WL%tk-KXCf2?_3(TZY#@9P`j}M^5322t zX*+B4JkrNR)>sbHqkX0QRPN`dbP(8-NHcVcjWJR91b|6>|wNBux3J=&(dZUKAt@M-M8K!nb<>t+WS3oBNe}U;PvcA z>L*LqD@2f7+)b7R>%sSBqc1Zya}xFgEq`3-Tk)payh59=*_>axZbRJkAcJXgfa=kCZxe{#_90$znvXHrb5-(`}$3BpaeudAmeEjdb4;Rai zPzK$$H&*+PQvTe{;+04GPd#(v{jv(5zQG-N0WNe&)~{6Nw9skd(2IXG-mNp(X+A^G z(}$lpXK1?jMi>$N2K8zFrP_Xuwik-FAav4N#&!|rU(pU!WEc5Q{rb#`49gE<4d+R$HB9?Y@?HjEg{7<;>m-^qtVosw6 zy@1g7ZM!#)+M~V3p{$6l9^23CC5OKk|2o3;$N%sNtV_l@}<-J#E@vH2D(s7pPz5 zvup!is#f60(EhI)J^j98^Hk{j4f;OjeHWx93N?2+>TD0co93<#<_c~gjCJB~_Juvr zfW;V27wXOUO|Wj!M*EN0=bMy2i!7|$`OSfGJOb0x4KOL4pgzlgt8et@e3q{w_(XFy zw%>Ps4SA89TSMEWxA%?icw2bP!q@$-*lEQ7gjbFEBJHBzsPc~~-<8zg^0)g&h2J>t z0_FQD%h!qHp8oo&7f=0}j|+R-xL>86_H4-ZxO{Ha#yNjN-4W_kPU$H5y7JpucK99M z*Zrx&Ulblxf0X){`3xQqo+l4lK&UvAGGYvbwr~48eRj^YY%!e2`|nL?aWu5~7;RqR z^NGU)1Vtm|#X9q9orq3BXTfp*E$&O*XSP!s^n5g(rvKFDi?q3&u`e1PJcguotL{hC z3Ab@wZ~N^&^BLH$IvA(oaPrz+L&mMtRZ*+t5hVc=mVMA*@oJk%9&ldHA$is=lqxY6+Qh3fLg$Z>E#a5=% zXW!*Kt+PN;H>H#CulasRn;-D`JobCsw0U$lz{banX$lSM!{@mE@_!1Aft9$%>3F8} z)O82m*5~ANTr>7$nCs<%zEMujY5%1@BvZ=Y!T^Ql?*D3KMqgT(S2#`OMr-&I$o=Wx zg$_6+WO7w3hzsJ{>N_vhfaziI+o9ZTic8S9q!IDKOIW0b{j@>x~?CzLci`u~w_^%)Y!2)9U_awe^*izRoM&7I5my0Q zit~tnRsT`y7x>J$$cq97UN2gx{w3;UAXqfUC+O3$KH>qijF|sIG?#{2(=TfKI&E=}#V_Ei(1WVG=}4c& z4&u18lpnFS1HmuE%Ej=Us01Nqs8`=Vr|l<9_AXj{=hHX9^@Tg7Si1QvKa@cA)D^zN z7QQv!`P-d;BAl$k^t0;jr%pCoI`Z*;Ooe23BbQWzE7Ir%+V=8QqysLzJIlUJ{lk2| zm@@UX>n}#fi8;*1M>5#?XV5?rT+O3#PQ0&}N9B3SZ2R;2Wy+D4Qk`)tZC;`MRq8kR z4BefE$gu+0Y#5ovc}(qoN;|=xw9A=HO5pzcWC9~)t&(rt+9 zKSI6pa1KYl4;=_&JpTr5;(C5gn^QK=sL7orm8?h2=l+rA`@m4&=;{61f#5jjW3-dp zBJ`o9xp z*j(Q4v-9A@>C`_X(?{wuWyP5MV>?(ejP$Nx{G+3Nqkm-c#JwFd{P}!bjdS29SwWY$ z)|q2{qhDr>SpF5|HsygZ?$(`sqnG%MeAp3D8$UU2h-05uX!Ca3#PVNL77fLxf^G1) z`y!HK9oIw|SKTaiCv5y8Pa}`2yZSS`ueR4{E1ij9nl1Lv=7@%Xm)ivCHMRdM+Rxb7 z1E#B_E_3w}#+JOO?FZiP@}hG}(Rj(1X}U=DtJI&bjMaZU>LMR(G>r8%+TPM{JiMgS z$-;_WyZ-4z&)jIc)jhh=VLuYa_`%=r3$ftA0K0Y{Mdpn59%#+jR7E&+=Kk`FKC!&}8!%`}B`HZeyQ!PHGExd|1i@{3p2INqL>m(n)sK*iVk3 zHVOQ1fdACyG1?S(2Mjw#bH<5${}OGE&|dcU@qYFNqycCcy4x7pr0?;y4)^8J0Kr_P z{I^Ow>44bp;WyduC!ybHnD3XAf5vC|MUVGi^gy0i&{gKO>-$He&?V`49;%7-dU?uW zkxmyLenHuN7M-hrE<1U^@a_~tp_87#v78#;io->+!*%`i@C;|BO{=6A7K z(|wlDMLfV_BF291%9&nPo4=$D<`W*3UY^O%0aSPRw9C2HuksPfALX;?LXMor=5-*- z;ZfLyo5yN4i*~W!7wH#tHV5(Yt|SfB^W1xb8|HY?e1|^NXYoSGzsfgLmcMcuJ;RY$ z3D(opNj5}pwVkKze)0gY5{A~qq84%5XaSWkC5#S)KHs3v{d{)5i?ZSfi*1g~^o>4g zZ6x=|O26fum_W^halS^IAES%L4__Sr_<@G-Bm)q4g}HzHl@cT&r8kL7$2p&!&FzlQ z`LJ~~W{7QGqfMd1fXibu)<(Q0oQ%)qwh&s&0y#fP7peYJ)PI)GzW#aP3(8*2p;T+} zsM;Qx$JfZ)B1~W+Mqt(MuF&p#v^#9Lm?t<`_&jce`u|BjcsY5^_8OY!9O~bAAMr8zO6FtvyOgDG#3!nM$Jqi-;*F2?k!~V?Pwmt3gtM>E z{uu2?`AjUv^p*MlVJ9KetA1*CiFW!N`+b!1r1cvt`Yp@$DDm3ukNSO!cH`DgxaMdN z3y<{Y`=vPkp>rPV7@)2C-9*{_HSKTc)Nd|NjvKXU(B?g~7hYBV1m$%;qcef&(Y`{| z=0UJL4v+V#?ayf|9ph&yCIZngi4W8P_v5hnt~S@*Z?3&`nA(4z_8T_7Vy>88RxqA# zG{#Hup3%@}{CwZ&pIDzq`be4xG3#sBqs^W?D4}yBPl7?_V*7bm>4C^EJw| zHf9dTPDHpRi>pkrwg5!WhdLF#D%r7@n zKF%2AZNLZcrCD7Vh1iaaN2K8?+DS*__ZG1X&(GIHHc6c0hqM*G#Q$2y$Npj8=-2qH z)01(6(Qf3lN5eXP{D1y8vH%l^%X7$rIVJ#R z1EKsC%9=aotvatdk!M1iSJkFpFwO59Gv_?loP;zXz|IzvoKo?%U^ucIeat~Z;w(^} zOI)IDtV)PAUb8Zrh{;7#WNcJ+bbReg9lAF#K2t{cfQ7mw-b#b zUiE07e1ETxV}64SLshkN!|$&}kf zM*{4>pw9(9b7q8Gha=o%I}h2deU*PyzJRe@SS|c;mDelfk5CrU1vIREIH%bw;``x(l&@Y(mc zCq#z4?J9NY-0e#FYNh;GC`VX6MVTprZekB?5hv#x&HYX4KVkJ>>O(2UgHZNj_e+Tt z3S6-2Kl;qBV@uH$F0bd@Wta`Q${@k}yX|^~q1;BYyt0<@9QY z`Cg=ayUAjE{OLm%QZu6vOmr3xe6`P}jeC`-y~*!Jwluj1Fyfl_I_At5=lsP3=wP4o z{>c1MT#G6DznCmk35i;ZN&lqI#EHv&l*8u)k3HvNpCJ9;R-_&b8yb_faR` z5ScKY-WEe8eV?OV<0!VFzKT0)4b?S0%*OJ0+TKpxUHqr=Pbtff5dY#qk*@3(_US{& zhd8SL^d6ewh}ih*f8{}kTl1;>G-csFmcLdh|CI7zQvdc&p>NdxcFNLEs81Vjl=2Rr zJ#I7aJKTm?U=|13q8Z^*-1h`lKJQn;I1!F-QBLb$qO7_jVV;*MZ}C}tQi#3Ytjg9`{&+bGBRPB9+fmPRC!R{DlObn|I3f@1p$fq<)n0Xi|QJa*Bs1DR-#vjR%%K z{?-y6BK{8U{>Swb&uKlE=r_w}@tis3cR901e14O9@%lh${}SbSZy(}0SLk56Ca1}* zmkQrUb4*fBaj;5xl`-NR-=UoH(rcCadoO!TN$sn=zW#fh{ZJoyP313Aj`l<4=PAD} z%%}2qC=2HrPvsv|9!Sc+qWpHs!maAxcBOChyZU_iW^zNdYY`dFAI=CY@(o0Jv7vBd zAK$;2^n2w$vfn_M?<)_*eY>AuT7=R>z~$Lsy4pAT3)+v%w$k8`U0 zrAqm0ln;ges{d9fOUJ4F=ah%}DBGYMAP(|vF4biZ7d)l%yD5uif<@)yl(jdH)5UNBc%!H(%$8zIi`7@v)R((tl}>ahEhy;g)_mIEFp^uN;r;DX?kh=<9a7 z+Fs?OwEqt6BOO)#31z_+>tC&ue^n{p^jNw5EtT?nE9GOA@?@pFP$^$b%2hhO2E1F; zvo$byRqiD1Req#W{#2#>Y^D5#O8NOp`CFCpOO^6ZD&TlntejxOpr(Qmy_qQ$T3?rB!jBT#IK^yV2=J`BrB7dv=X7(T9Nbpj$oxW!@xc^)9 zxxw*VpAOyfww6Q~_KX3JfiU)kPofK~555)m^fzwQ(UroZk_?h#h5G6fgNc(Ka+?UU%HP9nUS+)3sTclye}Z z|7g*;x?aKXJZ+zSljFWZ+i$+fac}+*F_3577yNbb-bLHHXgdJ!_Or8!i|YmNI&Clf z4{r_+*J%3~ZDG~yN-=CtzIuVS-=Xb!+E(XP`DN;F{cMrrT;*FG`aVHDe|q*GpyEf= zH}Yt!~eV_i1Q2$HnMe|<$pQC=}InU|oRsRC@-=RM4k<$5( zFy_nDA6m)6`JC*mC0gk)OlQoKFP{1yE`YMS{N8KY|0w+j&fu%j|5ZMd|3?3d#U6t( z&TEVrA46uK*EoQXtuxN&8`gdgkyS z{Kg;t=7II=zrOV1{JvA{nPZYUj?8jbw9WlXTf^YwQ`Zrd-q0e7r*W_dH{V{_yKYHD@8?~lS|BVBG zViPR&1fHWMO|u97oA~Z8nde6jXSpAl(pvR5&5`f&kNtfRm8m`WfnfK>cI; z%)deXg^v{P%%tOse?Lk6JHFgE`Xlgg{_uc3mJ;qZ9C+tjgj6Tkerp_MjPEkWYyT7X zh6of-au)mX1MBj9;$3Ai+kt`WG*%gZc9~%xxNn8QUV5Q#^ppG4Pf~yJ>wdSW7v37w zPky6!yqol z-Lupm|6ZTn%_f3Jf{`3qWzUHdeD&3S1N3`|e%U|u^FjKdvrtr=?Lc#rj%pvxb!dUJ zHu}88XYO!WAL4nSTwSnkob^}x9jC35P~=4W?|zs`QrI7PVX^}FvfQoV0&C z^!?3?(Bwz-w|&5X@#4jJSc>et+Ao|G%RwFQp`Gw_o^gKpFZZ{*SEz5i?0d{AUR8dE z`gi>Az3T<%^VENb`kQh%pFC(;nkqu}CgIFbz(07Uh#{sr>AlP|K>h2~UvPW| zZO^+Aua?o-YYi9Zd;VYf`G2qahpB&-`Zn|Qs(+UHoBpD=?;)Q3D)nvZZ#90&<%9Gg zBT-LYAE4iB^t<-2`$m7s=UhG-)~jb9&Gp{1@aJFljed#GJ>-Mf$X@x7pL&sgcl}?k z1K4jM!#wu_(^S`cl(wIw?N@30xbuJI$sFEYsj?oHt~!q7=q1LP{5SYiz2wNWN6x@K z*DJce;~YHrD)Ci5JC1m>1?ZJeeF_2C&jtyeCHh|bzxzh7F@F_4m3OG0`L|`d_hrSK zwAZLV_Z!8#UgF8L{wvf^{>|deJC#o-jRX&%LtL@)*H+=P)pS4E#?5sBJjD|_6Xlyr0oZ8<=p~sp?kM}MxjvBY7&X?0mNr&|MY*x8w-3! z2Zk7lohVz(P7@hl(e5~JVF(6%1f6H;4e8ER=@VBhA*Hhhh zs1x51`#$yP4UgYwX@m)n#iEa0|0MNq+o%6|>Ysaq`L9s_W$NFtPyc7A|8~+}nSNk54f!LR7cr+)+oL5!i6mR z0`2u1z2uBc@_evVtlUrS9Hd?<&tmz!TEX$q|4)A#{xJ9lO+R}QlY?Il;CobCeXIBu z>@)v}a|7^wjL$kpeEh~oZ@Aw@#PF&59qK=5_2g~e`0=+sdIRqRhOFx9m?}R^yx)S0S}bEmA2{x;yN* z7a|YrCC?uG4=}zSN8Qn{vy1zST&HMbwB~EH z|IB|V$Ar@QuTcM2)C(tSpUS0Z`V#fSe~tgaXL!giRYayx+`8XPZ^_gczN%xXJW%7j zpRoq`+^c?+`kzw2pANW4{kvW-&RSDgHQpoCznl8yea3%|`p2k$caM7M%onKtBkF&P z&z^tK+YcC^{x50!JZ+snEw5k7P}%>cF{|rSpMi_unm$W>7VWgX@H;1lvYt3uqR;sM zTjVKJ*StghBh;@mW_3=LuTlRq>Tlnt{wvhK{a1b$q*wo!sNbM|zy7aL{~79!>@)t` z>d>6}UV2she3bgXpk6eOI!cGCy>ygpP=odd|G)hFjyukkNX|2p-kXscKGeAZt&gNSmi^?j213-}M?efTQRTk_xuUH{P7s{8EQ+_w-7 zRDO=~0G}fbqMeBKFYHs_3sz#p*~_$lCv&S_<=6jKF`vr6qP*XHs(%-{y;ps&`L59Z zLe}4t2Zf7gsDGS#`Im1b*Bbkqw0)Mg`}wl3Q2#mVg_mBi9Bk<4Ir@9*F!9)})Dv+D z`gD}zU%OJs!w^NnusB#_tL@9Q?e8(y5x#3vub(RZ2A^4%9b_wh%+Wgg_Iv|i0wH+S z{ui`=v$FPG+Uw^~{r+2Vx4qx*7t6ZY*i}53d^OoOWSl%1Z2o>nFPWa9{y1&*BWpiq zq4V5BkUaafOg|Yf@{kYwG&4WBr(q=&F#gs{&6S<)&h3lY`_{KNoA0~4dv(3JwYI+7 zdf#NT`@qh2`+d!B`?k*Z=KJ(ty|c3ZKKsSW?Bwj(fw9Gb;oC>u%OJHg0Rwcj~uov^HBi zzc*m*mRrBq+5onJ+t$_^%LBK~@oBC*aNBAG?zS%Y6Oepoy^}J-u552^Zf{YiU&&k9 zx$V;SMt!HX(Y$TBwX@o4ZZy=7cCD?A)>iYjIBGYmH8-0b5VZ18*4*jV>dkJg(dyQh zSxoKnN@r(#bGg>t0eLERt=tV?Y;13>4cI@sTiw>$Rsw>})kR81&MP0Aejd8mNn_VR0MHtyo&!GEi!( zTaco*%fd#6!9;Bpq&%Px!4FN>irF-V5dPN0FLtvuPc-cf~JiEA9Zr;%O=$$eLGHYAf~KE<4r-sq>f#>w7LxeWO^fE z#Ds$kjE=Cfxtyw!_8nbYWTUxJf2g+GHMSa`UIHw`fnYf^Hc?wzm_C`ET^tV|#ukBWh2Mb{z!cyfMv&Oc3^U#d-=o0?q; zHM4WI#hIz8d1#5@s^>#Nd!wSr;)B;3D1nvjwm7+lYTvB4vwXAwA|mG?o?jZ9K^u-u z`m9USXQmcvQ|ITW7pAiDCI519Y{5ThVLRKB*KBF-?8GVm))=CIN0McX6-Y9^y}e<} zPoZ07pgk+Gbws?3%@?DmJy}<_I2p0T+G^4gK7px0l{e9Qm9Lst+UYmZei_>Ger_R? zb|}82#pOCnTV;XW_4I4a)@pA{)mJ3DawTDDnh)XR-v{;Syvwt1&6^@nQAB-EF; zJ1}`NM=({Y3yR1z{&Dc7R-I>>0H4CX3iXS1EH!jh(9Cl_lU zn!2ZU3h{9Gx;4P)Jk;K)wd*3`P>HJN`CdpVNLpk#}u#$2ll&hC1> z<|~a&BPFG}rF)=bn7))Iw>3=o}N87HZwh0o18v5wYU_U zV%e8>yANfJZq3NvlIsR2L)kpSGBY)+!o)TXBpO=&&|0%wU1gxr;Si7v3md9+tYI|AB4Gg!ly(8P&+HoYR#*A24&DzeoVQOOOJoKnbz5sBzHavXP z%I?Y}%bg!v7(0XKg7R-Qa7o;^V;wEcBPXK1gKCDm+JO@xTc-&fo8|$k2gVz_*SO4g zaZM4Mtj*w&J+7S@J0GCI-zbJ@Z`4taLSR^XV2TQ1K=|bJ?8(^3rAz>34}gLUH|TP0 zWv8=|okjenu3)q0>z&q)FQ~aHTLumrH7pIb3@Xk~*G|lgEuN|^Of8o3I2vm^&CT|92jRe22*O4nT{K+_t?aO#^2&~}B zH`k55nrdocVGj>QXcJ^#?%+P)V43T1>?j|LC8kn)9zCW_6Wc)3WU0P-qjtlYi!BCy zVdc`9?%Ft_xo8o9>QaMBU%DIrHEM+3z{qQ;P0rmtTN|61*#}^2b9Ub3aB6X)HUZlv zcxL#uaH~?P5jQV!L%h>VE?1H|sK9 z-`!cz;8Kf|%}dD;;@J`%3k6WD*Z6BNbKN7<*g$Ts&d84~nIN1D$qM>wA9U=sID>Dx z<#56;O*3y26%)?jw-lmd=F?SWA>D!WPWGa$Pze*bA<1^Z)7ExwvJm-bstTl}oF;|X zZkP2!@0JC-;J8g|8?!ila+d8QI~Oy4`4+5DUiLlyIW7XOuNpMF-JHsE?FEaNxW$r( z$QSj-{I+{sK8%sMd8vh>&hE znq9VWIe)abFC!A$cvy0?YLeR;g4@1Zj%ry1Bt_=u|+P?6Og9>~3y8B%i0&-U$0v(^t99H$)JSYGRY~#Sf1R z%E56#>2#eVs9j9hO_a1HyWpU_b~*}Mgw3mo%s%{4=%Ld~V+4d|CyAgKlVoeFga&Fu z??29`8XwtthOJbn864JE7Jlo-*26>b)A2jwr=ug`6GIis2I#g4WUk@=i3N{+67E zo%O!~3F?*kXtob{5V&C~G5xzGX$+`&s5ahE4?u8ch3|ZgV!T;5+rE^IDtmvO8 z+YvY)qks>wE4L5m49j*Drp-fzfKI--Uu*c*OF~u00bk!n zmrKYeFK^8><~!Rf8NR+~M6}<#sdi#}YimNHZ-b2a3hOHbgSR^mcnorS_QXu>#Mt5z zM+dqA`)Gm=f-;d}Ffnc>L4B01JmuBiaE9>Vh+`gt*R)>JS z^eq-Ho1eQI&2e&OdWr3WLtf}r+YARX8^SwRtfR4rA#JxU-*+RI;Lh$=u$Jnp-9@tl zqL*D&aO@=JlHOA+SrJ1sO5Ke*{z~*?BkQy_wDE#Tw`<)8aD^SC2?p4g%q_4fSoPDN zrO7EMLr4YG5DA#RcPg8onzbO#!qSAOGckWQtTAr21xg3bHQ&d4H<<^8mb4j07;Ga| zLK!%1IHIjRA@Va*W3$z;uo(JEW4?jLUECXp3$PE+<9& zZ=5d)%JNS}rb!M%>_jB=4YC$c9*t3?fPe|uFBF5LtjZ|Gw`ayAii-7?RLFD>6=L62 zRET|7Q6cu-NbqUUh>eN4v$IS1k|nMpP(idVvQ<>vP9NMcw%rwKOTsv71NU)LljG1m z8t|>aUlKYO@l5Yhg{Cf}FETXvca0$7b4LuIw}=l(0Q^kBXk*GNm#LtF3n33=P+oxt zmEbaySrv_X&&aoRQ5Q+t?@;J~=&slGnnGKjDJ0#ktuGKM{Ux>=8X% zfDMIdVhjS#xo_^-BG|X>L=4np-B+If|I06#jH_rM%zoM*uumvLTa^1 z$Q#cgD27glBSylNrZ17*d{KnV7eAB*F3wSXS>~g$y=J=GC>$rubQX-$P?1i8mupph zxOmT*@wpiVp(~0qRt)V|F`VT{a4+2gwS^hqURl}Y*f9{>l|ivK(@W-e8{}+j8`{;f zI0=2Os|wFDV1>x%%uvv3klQg+CK4!gR|#H5vDx^>_p9-MLlXtKT!6|F?MFbF%gXl7 zIw~%;3twcSqtRJO;9&m zB`mZNoky~5-19Nz7tUWIIMcHrBdVytlTvcQAnb9EOj?3UE_fGJ(`@;c)MXuqB~4gGEIuRO?|D%M0N!Vx8@+GKN$mVpqmjVBYG&_u}Bvq~sT^4DI=5 zIMesJ=xn21ZNl>WCJ$MwtK6upQ*RK$#`G)C$pEv=pLB9t;6{_Zxq<8*t@A0_LJk~9 z2JakZ`9s;IX2-KmHrI9Dt!>i`+ceF;xwbka7gs4pch4>OnW-u;U-eqM3;xvkp^S!$ zN=s30O6;sd&GzoHf-B%b`&_s&?ji-+CYy*53cJ!~-E4Q3IT2(Nr75g?GJ_q)ck3L0 z6X56?n9auII9toj6%apl#?Eu~&*r=iXwBwpF=}N6vN$dktM$`fn@ao8=xiiY!%99>_b!RSfbS`xw<-u_jT;7Fp#{^ZgWGPk>!1KS`GHnVK8>Z zI{IaJlEOHm?(L=_yc^{807Eoqrg2K{c3}i_zgOzs_7yk^et1JTN}_EVE902%5^mW# zzLl1qhB2MCvhHhsk{320)}@BJ*`1o0$PbT$vQ@@Y^gKumB0ObWWlbk+uIe=TF?Fy2 zq6RMcmM4Vt0w|tq+kuV^U(;rme7HD7a{8!4pBP|WCE%= zqg%J31B>(k!NVLOB%Gg%CJiCEPbzw0&p6(eAb5{Gm{v5->U~C{WS)vZm;i@O%&x!1 z34bzC+Ktr*feVn63xjf@BkF(@JT@YWXD24678jj#fx!9kzbNB04*D3CU#t`X2;Uj@UVGH(G3Y`NBjVES1GfjT=`^~t4|bXACF`oIta zZM3Y;P$q-L5{%s>aFN{-G%NRsygr51>T4}r%0MuaUJ@O;EoC)^g}89rOjQ{QoCx(d zT6QoS`{W>T3IIsee!1-V{1(*95`-xSt;HJRSI$Q%`-w%^l;HbG8JL7quw+`Si%*C^ zOXm;+B%zYe;49`uEqAZjchFk7P5w2F?if;fY-p_jX=o+aJGAmSyvHUfy}@SD2jNps zr&KC`Ii$4e5KuIYVmZ3fwnPK9#E_n~b0s^!vn~hkG7OH>&N25^ zoumHzTQ*pvV6+;8d%qeAUu|ygB4uv>yx$6(vS!IcvN5%-%cNq)#=a?MLrDP0TVp3{ zS2i|Vq1aMrS7$*w?)MgrosDHeF>r6uLz^O+#TM>%X-jvx)xZQrKx{d&Ux<>}l1S=k z?CqRPxo|&+E&e@u4S;&rAI8reO(TSVI&!z29_We0rh&tyK-EGNjI98nj3Km z>uRw{PL2{|QKdNKo$QLy@C;EbldSTbWK@xy}xDA{}lWcm3peZc6K(h2!UK^v z65!(ua7cZVqY4F5iZ&}!Iy4MlRk$!mtJX}I+KgQ?AS{;-Xe;X~9n9MV#1qPoJYnCU zW0m(DK{HORcUG(18ko8?R()mYSop%0(|u?wqSczSLKIBC!USiQ(Q2C=hb_b%6WSSU z%GGgF>|tGBU7P&`8cDzgK%(%a6I)p&>daY<_{=MtNWbFCbykrC5LwsJLNC|7VsD%q!t zvYTi?=-<&LhLCwAC0mgoQq(tbbrI2Yo)B748uVBKeYY^paAL(ZVrfXzU zy_+ekW&FPf!WR*nsU!!m6IC9GRKwj~Zpyo~(=H#=v=e5smv)NFNjWvjL788|w-)Zx zZZZ)ZoXXnrTETFdu-+vDHNi(PG$p(ljyAS+vBDvZjS_-b8+Op7+@Use&auM{@5I_= z0@4+?M7WCnuz^-K>YICJOV^IMf&>XMOk<)c)`laDE=~B1PDPzRI3PKx5^;+7O;(g> zpyXRK2!(MBLmJRq_@-g06$>6{k}!g=(i6G8k9>l?SnsXMkiur$Zkwg^>mG{IuL?~Q z89vf2u{bs`k=QVR=?CBcMd37nQk>`P67Enr+)nt`Y8c2AW-1tkjHmj*22apxqwK6} zL#69cKD7BHWXpO2N&wA7TO#_CrV zwA|Y@t1T1A@Ch_jS~mRY`l98kwz&wTwif+Xl+J3Fx!SYCu7vwn0(FoxHtzGpt(6a) z6;l*LzVT#R&7I?e!$a)SdiE_Q-3t+GjHn7|^3@enms<21ztlitQ(3g?3ka=2g25gg ze6a~F$w6a~H-HapC*u~dCnJdvB|_U5KCsgQpmbF3hnfVV0yzSu_S9CWrq=2n_I9Fw zkEID0R#h;nPJyvq#RAJLqaJ~mdyZIPDZ_ovz3R-pDK0eNvBq;0Nrw=V$bqKZD=B-IGNP2C;;^7vvUu?G~?AGtZ zrW-}yT*kxz&T1^$5hHkb^W2(*F5Dv}*yRIFau23<=FHjJB8TuEM^st{`RSRG0ctA@ zy-~-L2$vdE=Ar{9cIco5l<66ww-egahDZqB7E|bpTAbKpCag%LsKTg9^UATK-0xA7 z<`v8g8>kAv#v>sj>c9(b!$eb4dHT4eRXbX0`lF??HgGlBxzx?mEp@-t6L90U^Qq7b4!e(EN$dw&Utg}JCXd~-gE#hXr@CDC6n6^?lyWvP#(;Jq|=Mz`~g^CAzejTE#+spzogtEYU z0&4C4T^&|bvBFq`Oh8J8^fBI?T~2Ud7Q>-zfCgEDb^x1Q;>^-#B?2R8v_K*~rr7N6 z``(E-cV-q{rMa8%^w~DYXKT9jUfX7iv%yYAB2^+5Jv=3t)sy-Y#KY(zKpZMNU6!k; zt$Jvaa=xUjDqeP4<3Z|`4U&?SrJ#EYz|W0ruDrUMAGEcKZ6aDC_E>U>#*E@3R^dIN z#v7)$L-vdkP6;05#$KB(jA67$nq1}J$IkE(UB3?GbrC2{A|U0qlNG(B)F$P*+BF92 zSnJkTo5mG+o&ihk>xdXwHF#)ssl;M~$JiafLp|YW+oh@UL|bt>4r$61%*C5W!2~FlfU-s~mQc6zyigf{t!1ot+%p@#SBNsgP1JJ^KlUQMQWvto{X#ekN- z$VU~8nfUI^NnpEh}8Ls4VECDZ_)!Hpv zjDaYc=^nh|!0-W)Z5kReh%Fne#(cHLLqrh>()sxcR&_qCTUjo2X>%%!3=z|^^<*}L zEktGXpf0oqZKwwg=;A4f3PrRR0a+RgXtkqd_tj`#(Wq2#rO^Rt zOt;ajkMvNdemS7SQ$758eQkDXii@D6Lr!t|b)Jilgm69LVt5w#S$mf6M3hJ?QC#tJ z7-?H)s5Us!P(_uUp~C2M9~!%dme^`2<#`0sFiv1E+nE$Lg`@J~WS?BP`MHIqsYy@U z(*eFEEWl(ANI)`xc)$i2wCJX-SwJ(L4QdH!*(UhW?f32jkx$mi=fT=TN55L2Fl|yAW?j5eqIF<`JjX{7DQn3MvdrEbdAFUt`>Nl!_q!TYIL@XlPYCUOaxWh)heQP z=q4T6CW~}N%28mFCmuG8R+*V)7b_r{CuN`@hlr5{TfFFMA?OImPnK&s#KauobFNa1 zP0ma$AmhTnu>^8wDgSk@Tz6Da6X6O% zwh+!)Kw`W&Cc?Egkw1ZXS&WRCT&qt z7N&KgwlEcO6)(X_7*HI90}B{PLjY-0nlMVH30bK01RCFM)w3XIUXfdQrYK+{ zH6%YUZcxkJ-IW#cNU(i~|E?viprhx4`ZQ6-t+kv963?!-)~=Eu=h$`{mK0^qpu9)=H;#X_<(BCXoHyET($%Z*uNBr`w^YBsT? zbjNv=0E%;?U+ZSynA@a;OQBF$tJy*D0Q32zQPEg}qoQA77()B)Mau< zSd`D8b1+a5XEK?7j4r>$I3O_pSzMn0OC(jWQkKi%3LgOjLdcu=JpYN&!w=bg)@>mIb0G^>3$v~ILRb|T}%*-xlHPuoaO^v)+((!XTtUb z(rJa#*5BfP+wvdwnWW0Vw?r_k%rj1=vrGAtn zhf22RDH2FdazA2{2LjSHs=1U)5R1U$K2(5zdIk(t?3*I_M#4^$Cn@|TBwU^L8MD@= zt;8rOiB0x^nR2|?y_#-Bw!&ntf1LsJ_>C*3lDL~Chw%{~_@4KJ4A;gou0*1gNDj?v zD%;Q8g(@dRi&O|jaEFZqrowqkgR^9ylOAV$cQ^L6ZEn;J%Q78!Ax@XNe6X^wWvt4G zK`$9o3-#tei-mKs&pn6eG}{5WOWUv2zx+g5;lcT}$kg00-+W+KX%)cDxweWe41yc; z;Gkpk!VbY;b&neoN5QvOqIi44@0a9kTG$(isDyT70c1BwZS(^z2eQ`XB{LTtU$3|< zvW1kAb_(p`u5e`AFmulPSGXvS#6m-n@2e~u_&|zEOe3+if#}XY2Cplnl(AEL0+W?V zS_bXkAykw$H(F!;(lWax^Kb+@z5?M6kckls{8#J;+%H@g8TPnqVT)4Y@Zf9J&P*?w z3t5);#E3+fOT6jmk+33kQX?|%SYbittC^J=FbCY!idNwO8|x`V%b|W*hpR>oVGv?< z0Ug7k6=);hQ{oMx4Y@(#LezA$!YFAh(?LQu%D};ak?=`T~DDEn{fWM!S#Sq zu3H_aa=~k|9l0qg2<@=6XP5>6wA67Nx_l3(x3~B*5Kn-?j>=k4OZkXpH5Mn3gHuRp zL1QVK3hsi%_0?zhBmVv{4^pI?>6tXNOjfqlfirkvlGCzm{GO$$Y~8+YY;vN-Hbp_3 z>@?}(yn-Y5(ByP^dx!V#vYq?eYYpu4>B$AXfT&w{kSv>-<0T%LQxeTsB5c?YH}Gze z6y7w@^um9(xw0D!vkjxGSJ_$q%^uv@fyvjcQD<$Lz{#X?g!!JBsb=K1-cbB7ED$G_ ztcW?uCh(Px+axwy7q7p`MKGL}(|Xs@A}|Oc_+GaL8t=rJB_EFugcE=~>t6Lnp?ZW> zX@ToaWou{CZQg=Z6+2{GhsU+LJ6o7{^meoMAR!?Zv3QD2t6He@#JRDF2`~#Ppo;4> zgH(75{c>NI&K7%;6GQ^r_9_;(qb$?i_An9MVezIyc!O+n74ICWotj%*B2QW`k&y9c z59yHz-7>X7=uk<5a6+aVTH+dBbpR+Xr4Uty+Ll*Y8yWKZmSk1tK}F@G5p@?e(KUQ8 z2J?6$*%1m2TR_j^o5euKjw+IGmG_+Y9;y@l>mH3*+5@uNFZ8NiFY(n}?sPlF2qVWl|ZuqNGKJO(}V91;&aY?l0$skvkKhM+TFcI}%jfk*soPIju-~4=tBkfjnOH z!zqEN_3Sd~3lKLi_o5bN-A*+U;L<0OL~aqZ0RD~y+@a;9F#P@m#*yO*kjD%ud$4XH za*F{*-oGNn!R;w2 zj+O3^2}?3kl`H)D1`e1MrS4o=ZLMzCF0bw?MT$o|^Ny)-r!qV=1mpTCho_q+6wrl@ zMu*o>*sl~L4K-N|xPigTYHFyNAa>-alf$rq?ly%d)mAqMW#p=2fZXe8CQGr*B)DA7 z4z0OsL(ZGhawSvZFujdtW3IZ=cyKor4)`ly`4D$_c-wTFOYJGyV3#TY(wdQl6cEgZ zct2`$vvEA1Jg*p99W+S?QVF_iEOdGPDH&vF73CKn#!yb3nQxIRUtLsf=}SnH1TwO? z$kuiN)X*wopvQyt#HWrD#FaW@ix1@yUpS*HRb0-Jyo^}tlY?l=QxB}+76^izU+6#V zte3BGxV{%ts!TM*uoQk&vBN0&H+71GPAjaDUT!t{HHJ}ACP4_}kzm#I1_1;RTV$&` z^D>J2aoCF9x0DNMeqvO;u-K~fL}QnU61H~BiCNQ=bv~@Np*TPJ8b*c_1{%g@xE(2J zabR#2UqZzQ2VD6u!>PF#UXIdU*l8DD-^tO7Z43X3Sc68axDpNp5K@(pB&`!li%~0@ zdjy+cwtY)O3{}=NoEnLtk(6R6_~;fWQ7u^j8h#Z)6Tb{Er{A+mv_^DQ%GhIr>=VBV;9q5 z4&=J$vcE?YiNAG(UvdM78Jd@xZ5373{@@VTtdx4hn>M+q z;`0R5L=B?rTv-F?@SRE`G2BQ+qU7%22LhKlusB>Cha(vQHys}CF6JBJ>E>ecCR~RO z;&_sOhtmoarJdMu-k)8zhmV@6XPk3~Y(0uPE*hpEHo4I$yVHhabu9y(k_TvdsQs3+qah-Ki)JXDD$d*ccWd>f(imE|)J z@eWd67)Isig`vTt<&8z&SrK}6rt6|N&$nQ}(_W^9*yvm;AqD@yK}kFto|!BZK?X{%V`&``48A*C&V%{84}=2#dS!rSYqzlt^^7!P;- zd~vyIDJ=Der{{uJA`2wxiSg*Q0O=m$+Bp;>$fAsabYb!Ba0z@ikOH5z7U*(`=b96J zrKC*i5usv?q2Uw-?D!SykmHqlHT<%J9>BvIxW2#>+FsR61%S9uMM0Yh42p-QlCNPX zJ!F%opEPPi7-67Z!QX5yY-^=#F5b)+XN@?lE8ROP z)(KZWvRimWy0j4Vwi#CNP^@T(?MPflf^-sX{ce7+6?v19qIH26g4cP2JByEry2N{k zEows}#gw&Sh?{U&Siog8Z_)v8eAR^0yr!U_a)nXx0`u?l2}e-=vVVJPa4Iw;c;p5G z|8*~OkX`g+uTXHDHnHyU=xyHYF zG4pTVpMR{4unUgg*M`!d!H^7+916X~PI4x`LU>3zWr87M1BLABDJz0t#ek(~!5sw% zwGk{$2n6gA>%w6w26C^va21{1Nt`RGZS0Z*Nyh?;5iC?O(wzyjqP z%e-b76G*m>%@C|kQkV3CeN9p4J1rEHc{*k0lzk}2pz`4YesEP~$y2owCPq98cC8KN zgds7`gChmlLqr`CkxMI*Wsj63J`Gh3YtNqha2TQ7fwpb+ZkrdQIs6O>pcXdjMXBID z6+`K<3k&DuVqPf2XnU*fV$mCasn;y#{{|ePB&u#DoLcQwj%dVnj@%hpJw#HpeRcQ< zpXca6(dD0q(xAss8WtPEvoX6ztR`)ru*@*V&-R(dnPJzE+Gjn}pYTC3%y6Q4$TKv~ zD|R-4@q*Mg2yWUBf0#Rh8VymEf&#KvzFlz*U@i#Sy|fujmYfKCD)_?~Q?vMrw<$^; zhe<;5?F$5+}yd-y8^my$-}-Xu#tU(FEFw!A>7)Gc;p zB1Z{6kbk%!BC^vV@ z9}%wv2{5A4emT$P7#+q|s;lCwzTvRbg>csfWT@kao#}2UyZ62}a9(DTfe;Q$JxiwMWBg416TDM?70wj5{*ODS)`W z!cKSyN%(YM@DoR=KuErOSm}F=)T(GUl$gem#CnlHZP9WunHYp%0n$_u7>`3-Y}-SN?3co_@*g;y za`{W4K&Xr0RE}Xpz?My=w(o9}G`uT!BfkP&!iwm|#v>UtJxCdmZ7|xFd1fSWQ)?rb z0qHM`KMaj%=U~B!%boJ?kYXaGAzE%2Gfv6J9L0u~OP*h98F`4&B16$gpAf`gpd z^L(|YNLQDt_>ok_j}Ry$oh^Gc-OS;W0rXg)~Ayj}@DzeEP5epq8-cByt!)#PW8i8)O=H}}hGi{%z` zZU6F2bJLzEv{`$OWk3~en3Az}H_p_r1UPg9;Oy7}KkIY%?98M;{;tP1P34_sF^lb% zzff#|CQa?#x_J^aZA2fAY#EK-U7LX;i@E3Z3t1DZYZ1iF?wUAI*IFuz^+}j^p}Dp| z0NTnE{8rca#sh}d6KIKJ;POsvDR}JpKW4exUV#@8 z3{9~Yggd{3!vM$=TRR}SL^m&-(n0g?h8MJA;cJ3NL^)(Mz;{;`f?GZe7sSsa&Joj- z);@q{AT3Y%tL)8&LB&0e6o~SwA!PyudQIY|_tHdN{RUFF#fIF29)9P^t$=b?d2FLR zGBg&l8Is-wm<0hN;`V2>Du!wWaPSBGws2*f!(yXIG43Ld;m5HPaoF7en_A18Iv>*o z-E2wegFa_qLgkT6>O5h0!#HQplAW!!=ym~-(V@+1U<6}`oL3f`JLC1;@T&KQemBJy zW7mVVnb&0)Wp(YYEOodow8*&V!f|`Kes=?j=HS_Sh@EXh1FIzZi`bkK(5DGhpe@K> zE(i#VzMAw@sNJqnY>QOnu81Z(WqDSt7($WKW{glM{_x&rySsz>fU%8#3mvk}Z-VsJ zNVyJhuyn^O{3=D4xrCL3Z^DnKU@Dj*(2*&H=iL<%+*DzEYl_If6KulrL>&F$jED3$S*?^vO>_BYP?$lIEuKfy*tp~Gna ze$GP5yDKc2C(ER5l6UeWx_c0;fH*Z$3uk%F($d5%%dWac)1AJ^QdNc1C0~W%8=pEk zJzGYXNuLWnZIdOsK``wQ`AB$itn6HYMY41D0H{&;OyiE+s)ar}9RV8W{)#K$Bjs+y z?uJYIG$IB;PT^zjRqeKA#zVK?qtxZdlHG_#PW+y%Sefus+z#Jr2;dT?3eF7cWBm}X z-r6wPEf1fdDRb3Q9;`4fd$5?!13L;p);9x#RhCdROhg5~LdojaK%2AMyk0oN9^X-_ z-e)$KS(m9eMfPCo%9yFH&1UQ%a@7r`{i>&SHD#n!owu@ya}^h-YzNCT8GmWFEhHB{ zz)<2H1sv1B_{838;I>`T7AVyep@SVNC(VOIIdPG}&76inS@Sg)58v`W*LYY|gB05B(bW zZF83G!oFTe&<_sVtN9MJl0tdlSyys!Fc8!1c))Hi z@FiS`V`S5FWah}xQgW0T62q^WVDI>4KjD%Mx_(0|L22G04wJPVj&@jh+Ykdq?Qend zsmYU51%dqs4)ji^z3yfhGF(-sPSmAC#`P; z$Zr~ggbmx%^%&kSHbDR$S|bvsG^Cuh_?0oi14DGNNBEv-krS1M($uYk$KohZv$vz_@wsijpW)3b#~% zV9Z;lmFe(htm!5+7lxPoW>jg!kjADM2J!y_6^d@9gKK7AZad^eZ}KzT74WDk(kAsP z8;EGG@cuNumtur=5oXf=);@ejNj;`oxvRlXV;Y;P`5JTi@{1=fa}_K=csRwz^+ue6 z@m8%dik{iPyv4M`((m&MCB5poo?w@toEuDYv(+OJWP6t%RLwNrREJ9+V<5dy6#fQm zm|B|xizn6gYzdtK1E-1PA^xvrIQWD>5K`&p^4k4%-hxXkJ7rlnFYGB=%Q}^rF$6Q3 zA=x|afg)^7ZCwN#LlhGo6|P@soV~Ccy)AHP*jJ6BVg>xjM zPGV)1g<2W0;4woF4*?i{^tP}&+}A2gy>$Idv62lWy^iZ}mJ z$OU`8$hig)(+#XB29eka*%s}Y_C0IE2;P*jb`TZ8;ha6kFW7U~U#zB(m;yhV zz;PC*%qgJ9Av!#iQVL;&#_6&um?}6@m=Y6#B#u?=FHbyI!y!RE2DumbhU=gu@D;iI z=5O)%vdBL2C8??T9D9Z|o-;`h^A;G7>iA|R7?P7X(lPwp6&dURD{Y^zk&Tx{&YDoE)UigmfVAft4SsQ931 zM1Qmrm0Y03b3z<35?zU~jT|&CDOM#uELLuOgb3Tu11NPCj<;VRcj$xS6DX#T?Y9-3 z!+R(aSAw2fT*7q0t$xa8ws#L3Dc#o2-`4Rxfa8sHhUp_c2(Aljw(#1}v8B18JF^~N z9ye6^4Kx?-yET{aH?5rELWG)I%iI$)>X?iN%oLdZFnwIPknW&xO z3bxf1U+e7S1ZmQ81MZxjJgUmCs^HOSX|jCS46#sw7e7aG%oN{B!{+v4uVvIClQHIU z-0p1}etc18B_56WZ?WpBAFK*L-6`Y!5Xsy;zoL|Pcf9TLUUU&;eRxzY&n0#|;&$kz zRQYZ$mBBT`wJ%n(Fm=+NXga$XY`ypGDsInPp0hm0Lnl zW|AM2AjLSZh|r|dvS}$QiWS)c-9LY*)#N}@OU#j&uSE!!D8{v^Z1_t@5-FgO<3^6J zTIFLUU}}z-KjL%S0^8ecb-{aZhLR3Ka4)<^Z%Lb#*vqay2fiqvGY%8M3!K#3E&Q-$ z(4wSx1AaeX^X~%!q^vLtIftZ1J)T%ICOBVN-`yf>##jw(V4C8~#qKD16jX=;VG4*A zAOoNACeCs4ZS)lLT6jj?g&v=hU59={%ckeEvA5I2v<1GJUt~pXa6{kFDt%B)ENn;e z2(!wbFVN;g6}-f;Ggo>{!}u?eCEGd!syy%>RQjGxbBIPMR$Q+cfc!XB5D|qGBH57@ zi-g$k=p_qC@fFaJ)E1cYrARjxFa~_sJv%vIEjEN#k;eeHSe$Do?lwArK~n80XP`5S zHfPI$Bvfx!A9Yie%YS6axErEM7abBzY8hE zC7?v6GJ1)dqMS!2Qrb__-lwzH_H?lS(y)HsRB`*HVUPh7AxkfK$ZV}PK{3YRFSiE| zu#v^L;&H3Fw$$EL=U@o*Gi8>(AbW>6+uJ(+*?VQJnjCn$Ztib(C(}f`9U>6<^uhJ? zuZ6+%i!k%$4$0I7#K;k$6OJ_mP4c}lklp+*+WL3=%x6bGf?iz#Bmu=GX^h$C``!gFK(qF&a8~Q#m09 zu(q*{hwTPGfg>Fuu*J|Zep^O2@e5feTx*&CmbT)r^Hp7sUQFoeFX6)Fo=J@r9coQi zMbTP{-Xd#08OF#NS~=C?&-i$0`rLb<(DEq)0 zJv;faw)D8%qJ8iP;WK*#HH13$L^6~JRqRCY+7)ZW4qJ|&!r>Awi4|YEf931R9nL&_ zNMy+*e2F|w?LKFw&rB~V?l|Q~)RP+e*Nzq<0NO21%}y-bGf$G*6tBz8@}w{Ci&|JN zYj3d6ve#Yg_b>NrJin+11PhdiKBn5-|8Ki@RMe9w-VQ1L`e;vXx$@J`E3YhPlAIy? zci1`7A3IA%*yY!q_&s^^h)y!ywBq}Ew0%k^HyYG`-5`aELoaOxeQO}aV?TTiBPM(1 zGiS!;Ym;M3V@XF1S902Hd_S3F7<^rOr>cOCA8+UmyMH8k;kL zN}i(?GC8`}PquH_b$Ua(rmrr+K+-dF<2j47^G|`y<^@#R?;aUq_E)`Z~oD{7{l!!e#3N z8Kpu}Pz+F8UIq9Vw~*S>j25o-K@BaP=Bkn&j4MhUx_3PSNt@q*`-s(SW1VN=%GXK^ z95vuoLuqbqMv#l3`2(@?h5BmLD507`Gpu#m6Qw2)uIC7{CGD!JNWvZ3m17I`&bzl3 zQ|em0Ay`=1WK&+e^(`)!k^)aTAKJx7e%+x!ZQPD1hmGGM3o#Y}r<@G`ePoqPH}i&G z73QQ2D2UoTDOHM2?*p3v(e40x9Q}S4FxzdI^80rGGBzk#P7dv~V2xHWBwpuhEJ- z5E}RL3J|>IDk)Pqx%_Tc0=f7xrR3hu+%DqhqupJwSIULcvZs(jqAgpp$dW_L8c5Lh z-g|(w-wr31N?Je0Q8X+;F7_#^?BbnrxoZfF zpsvjAET^bo(Wf+=UIaua%opk*z4~1^ds&_vclzB`{fulfRHCc*ek=9B*g2aKJ zuR6&n)_Wx%Us|N748H*~!%tt-7KND>zx@&FtK&`<;|4GU;0DS%jFP~4c1!8SwMotg z<1de#HMJ4jP7^VV6WK5A%yY|5ize}!+#GebG?sejp+Vay`oHmKUM52-MhOw+ab&H1 zp>u7w-O4|)i#yo(P_<|dNPvGn{EA0uc6+X-0EU-3d3Myf$VV@OQX7jwEU!)chcJt; zoD4D~K);f(!j%}3ulb2(eH9nYcUnLUiA9a=gPy?4;Pvn@pc5mokedlHImg@l3&O@G zPVw6O*`>LeIlY!Ww>Z5teQqispuF_jq@>*dDZ^&qM%V@&HispURm>8G6eTT9bH$l1 zV%;RqJE_`fg1@r1hEXX^Fq}?M!7oIz!FypMG!1Z+WTlq(E2Cp}>Lfb`&{4vEX@!fW zU-8*PU{S5aybjrfEB%1qoGauvD4vX$gOAtA5v9Hz4M)&cU(BbgfqK4fvTVV^=J0`utP@%sQI70Xq2EaoF7kQoQ$pqU1-Um6Zr2qQ|(PUqXC zMN|7Zy2W4Hm+|u=_&&Vlnh3$3&7mk?(NfFtwfl;t+gXDB+ONKkihj<mpOMw5XgZ;%|y>UoMl_ zCNZV1nFWijCCtZl9e!}Pw!{=?Y>M#x9GA%24@DW}#_8O`Jqd{CS{*xHGx!2*?p9!a zeeK~}ZP0KZEU|)}ul>~r!QI zOpJktW-~70yvGI#6S7<%sSMl9oI_k`O4eGFUrV#;a^O6NF)ZKqi-MvI?VC&2Ri6s@ zm;?jA%deTEmRpT0mMKsm85&s9dnP(5nCNg7M2mps@GASBAEy5Qd3zfutEw!|^F|OE zi6luoA+hy4<%W@psc3HM#TaJ@M+YW6zj%C}FL)(mF(-i5LlueuS|LuLxJ@*BeS!RXJ zV#j}lx#!+j{GQVs-Qi?Ubh8gS*lFCZjk-fto7fuDzobAf)~s&(Sa$0k z6RN#<*HxeEvR!y?ob8)ka)sXv)?-=SQ%Y(dK3KPL{mNWlKSyh}Li)kY7z&QBSlOjR z19HSJPI^>r-%H?|RNDCSVM$(ki(<7y~4 zHPO|_k%z1{q_|F3;5?;mh2oF@AYImcL*i8{R*IX}t-6WNcKIuXyluK+v#uR^!>!$< zZ<6r^{#Bt0!MyUbui&sfLmOHx;J7_#MN#QOAK)9MRwsT)O63S9RUT^!YoV^bS*Dep z*wt}z&Bj;w9UaZm&{>p)B?{*aq~LABlp(*vfjqP5O-`%8Ww~SJd z;x|}2a**}<4GoT9wZY>#^tt%a4=OR7Z_$ta=|D2?&D)!pUV>s3*jJ9MayTTP56iqi zomE;+$Em=!)#%q0Z!(Rg#&Ni@$12@-S?p39r-I@)VD+6p>p^|}_F7y+N7uxf&D)J# z&ZYsq6QrZ9>W>p zHs(E@)uO-Sl1ka9w1-l(r;Fl*?C(}TtA4NYYx6NH#9rEeA_}O%Q zZ?I9_ntJ8!xWXQ(zMJ4j4r21|_$iROJ}Dcev8;6>?J=D`#UA8f)Uju1(9QLlGd9Kb9Tzi4_`mNf!(!Q1^Ks__%r=suh{w|5$ zW+FlwfbEUxr`9)Y(GNUoD@t{zGE$lnkoHe)|$WDdPm2Z`d4+yj`ETj9^3NU z_2g&Ab+S994V&r%dg`6j`^dJg-x%4XF0Qb=x{Vu*EG?d3V~gz)>ad{=BN@}_HZOx| zE1d)=YsI=j2R1o_uYGbIa-E|%<*YbKtb>7+$5l1dB^ab?>TVu0dQ-9YHd(2wOX#Mz zu1cz}(Jv!!mPGTMozM3uyBzX;ES=BPe6mrKv8|}3Mzxv^{Z5x|NrtB6OBXA;?JI`) z^GL5gyT)otv+rS9wz?}Dnp~ew;-@HiEpt6zkJV4=XgMI4H8JpGsj#eV2eir;Yvqs= zx`t4pYx~qOBuC7a9p`LWgz?Ku`udC)$M3~>RO8=iq6~VkL+^(U^zZ}*L)@tib*)gc zqJyC>dk1)RGV?oBt50Y0qkDzEInt-Gq1>|0p_}knA}jS-S!Ty4C07BpeWl?Iw@xju zZ~W@Zr>nBz(b#%f{YQ5`&2Uj88-h~JI){3&no<44njrL(TL-kX+oaVqRT^~%yXWW; zLl3u(pW2~{xlze_l}7ElVigUpF~dVZp|pxUG4!Q8E9-XARLIX>NsU#kcGulF=Caac zPe0FUp&&miW9x~DejA#z$I*_y3c?S*g=}wI#mY`?+BL|?(txKYMfLT4oI`2s6&#Mt zhQZLNa4=jJ?P?-i(WOr+`i}_~hEBqxOfKaG*R;!TgJno|3||I=KRMA)RMB--TF=x? zr8;JJZ$Dj9haDIc>o)KkvMcnd5Ph=Am^pd6eqO12*$+y|t%n^7QYD`|kS5)BAYd$NAgoDu8i;-PQPQz)`Pv%gGqhxLi_6~R;+&2ns(!3*ftjY!;xAY=e3kK z7d4d!l=vo{)YHLHYmr>8How+dT)W)fj(?|HOwvc=gI3!t6142m?{8~{=Xc=j>oCfo zuCyQ_YFPY3bm}}DkoE=SFsDF`&q3!EH4do zE!$%Ui+UTo61}^%c5slLG`+#E`A(B%UVky6cd7xkl`emIde!82G&F|PBlRo8-S#uW zL~Ba+K271WAB@fFg8GJaM{~nUtEq%XkeFc;yEvM4f|L*8Yi}Y9KAoK50PR_x`S7sL z5>A_Pxz)!B!kIza6&c*PE*w+PRFi$(pw4u(-uBLZfIO#3tM*^PMwIuG(WA z*q}GN%sEYo1FQJF)~bQ;UN`?cJY3wsDnT7!0p~NW)%19q%^&t{g`TzARqeh_k6-mp zu?}^!xaUUKJ}Ie{>e5ZuZ}#sJX`!a$JTq=ewAm#O^?NrN&o3#yYEz4>}zbcmXm+x3+ z`Pj2-&LwgmY-?T5ztO);nNsNL5)X)n%()-2Dq`#J?s6=hPdV0a z&_T!ixED2~%t$z-)(hnwcp>&EZF z8X6uu+3`W{(?ep{^u$?@(}xMv4p|fFQlKVRz~1U1RM?3 zxen&n!>*01`t>EtTXps9y0u#u)jlq&8#MZ+XXj1V4obLbl@2GY(oekJ@dqnc_4KGb zH{W!FeWJuY>t+n-R{&K$jcd)M^KaQWpjknM?ADL%s_e-%*Xl*lMN6)jy+C)|oAjV$ zAd2Q^#mY;yR*NZXnan(Qpq_vUZ5`uTbg zl5zT`W^C2ZoU{95f2VhMPnQ!cC|2~J<)SZlF1O`O=3t^qV0|u+mfUciJE0G>g^rbX z7XP45oqgi$3Y4`2CDS`1>$GFHAusBJsRVN>59Zw3z|uIE@;ip zx=qLaq@pHQ54yrRQ|79u`w)IV*mTtg)~utW>$W@Re7M_lDUx=r-?ZK|;LyE!zWbuM zo*u*S5b!BgvBsX2> zgq6f9~S?fV!wRyrXJGg(whQbZ5?+V2e z>r!>XdY4*=^fURx`f%e){%}XX32qbIW@0xJyP48#CL=lEb-q!Y#%j;1Ig)-K&F|0p z?=(&2s}Yvx16t*CyEVN*diG4Fn`WHU&4_Jv#X@A9m4y;gu=?$F^$+ctZS11t>YF`% zSA6EdKV;hB+pN?3)?Mz_H2Y}LrL9-~%BclQ^wZwgeY?)jjL&8pgu_X`;kvZ0CnzY~ zym*L8p6aISzjFgAmuYQuO`UDQU@yjKziVTcV*0e1B~E2MTSvd}ymoL6CT1qrW`Eq+ zHS_25jQIMci?3OvUZ5kF=SZIUXRqt(n(OK}ExoBeM=LDt zO5UMzsyHTQ@Lf^QCYqqQ3{5L?QDWx_@`SR7+N!hE*59VH?x=m|=0!e|<}-8Yil>hS zhR$2Gt5vyQ&osV1C7nLc+$a{RQp5?D!s~@fk)&*G;LRQ0hJ`F{k zHC%adr_jf`)NdMWSZF33#%qsTQx3z_{Wj`yp=+c290J2-TnE{D`quMN23mdDce(!P zj=FcVJ~5yw%A$ucH{ErG46&XCwXLBY{`I|UR`E-p-U0Pe70&4A?1!l$?G9(XR*P9_ z7x1zXS@dtAs5})Rc387h`LYZ>0}qFq)i0C{SJ`OC9@=rZ3{oBX?MkaG_npwNn%B{k zh73Gx&7UvAX4yK89x-&qV|s<qeta`8jk5~MFIBVrl3YIP(i$U%?E=Q#Yt}KGReR{7HjFjr)`qX@bU_Rr zJ1dXvIyQ_x2YbWkwJuKUvnwMPDtP(rmn;hmQ}>S+htYSxmaQ*L-s`nrg8#&D5mIQl z3J^`&_^`?v)+^h3zp};JA6DzCjVy!VtPnk&DAYcoVXp7S47hYE3(eZsmzG_x$1_^f z3{!D*hF|CVRYlqSR|u;^X}5TwTPwQZo4BLJzyE;Xoa(AueJA*GZZlS0p+{V|+Y$Eq zhBfPEZ%*_~OwU52C}ZuY!|fL5cU0Op{d-pEP-iyC89nYL5B+L*SF*`+8_rC$h){9k zgN@nediLM=WW%0m_@>`<_SCgi^qI?D+>zJwfbQu7D+bn{wH@!rvDk?3zI^?L9^q%s zh~2-;%-Pm1*9JHfk{)R2(^NX4;>>VovSBT&?iB(ZlF?sf^y@U?FDZt+ryMd)DS*$M z!>`jK_Tm0vD+<;w?_vi?WiiyxCa?YVcAY-GuITVOfv?9Vda9#SjLUDCf5W$uZ(YA^ z$t~9=-(9xw`lU&qf8pL_iGC_$>1VFYPw#cB)?V)B<%BZ0X6d(*#oztzlH?|Rqg8X| zdjIa;V6yz0rMIAfSVt~+0es0Vdh;gv&NU_bZ07aJEjP?xwlFDQzx2C_v=%H)7T^4x zYvsPmqc5)LWVpVrWKYKJYY#H0T)ut75@~(r^87lTL!TQ<=6`q5B2}Nt#j&mIXy#4x zzpD?zsOWOi>q33@rX|;3Cq13y>Rab0y%f6UI==QI#(%G5$x_qlUfHcv`0MqkXVEp^ zQY62y$0siR+-Lo|h4t$eU2~HrHMOZKtloF~3jHjcA4*)lgx01GbG7=WzU)Zea1Kk_ z+08OAKd&4pne1EH>{AxhL{?%B*!Jrj&3}i+?)L3sgZgLA?^6bgS-U(dgbF!K^Gr0m zZsiJ@B?EEb`tDV~-fqh|W}7@4j9NBb{d!e$xJzM1hre?4p1>ei6rF^C8*Z=du%nqb zPT6RIqa%pJ+{9+oveAz}tXrvUY(x%sHfGeaS;v9LVK$8CnG0Wz;K zn%N#k%ewrm(Hq8khex*c*A5=*NJ)QBmtH{Nk<|LzSFYH=J3iX~tLtR1DJ!skK*v;c zoO&yHs-t;O;_Z>Pgzotv;a=%D&e!X9Jd-{#{)wk)TLjA}} ze|Mf#3#04oy&K)`nGu~xtYat`kuL8g)R*apadeu{&yFjN8_yEyw;S}U!UJn{Q-g8+ zxI6DF+@VC_v^zhc$B{hD>kTvg8hw}iv{`0N*M_yXTX{0&^+jL!&d#m86T6-d*bn%p z75Jr?QoV1D+tcT$_|>l7?q20#NZtMn3sADv3{AW@n+4z45DVzi@Z2Z_yavZjmT z>Wt;)8Nc4+gL5ohbz#!wgAJMK;ns+mO~*6V*5}Usy>D>HnYZ=U z-ySX>-F$maGJUa4zc;1vs-K3{$EJ0vR1>%q`}Bngdm&B(Xe~+m*vrxMq;a)5QP-WR zme+^Ju&ILi8*`e7G-dNjoznQ1KQQVB*7t1+uYnQEq2J7E{?mz?d^9!kb~lfy%?Epr zORv!B&a{WANw5FNas5bPPz^@(jmX|!EmQmsPRA}ZKpCpJ=lV*UiZYOd3bOLb6JD^@ zktxm=58I8GFG_{c^+G_BcwfUAh!=g|jpY_{TMsP$X4hp5*U z`1wLj>K$^6}$JUDFq)qVErldGIkQtNBOJ7|{zP}!i*7WvVq4yy5axhxz zGrZTqK}z2BF~;sLKkMZ7+2?$H3P?lNa;(#i{AA*qUOrS~XSDTYF#Tx6a1ChB>~gCD zRnTWG-KR|5*_x6U9A#9$r89ifX~A@z2@cyDo5SRI<7BNlV6~Q0Hw~9{4PEvY1>O3n zkh&R_lLug#Km-F>{O6OgGKd)~pzk25eZ+L@W!qt@NLkB^%3b5|o3+auPJdokH*8z$ zJM%ddVQoK~8<-b2T=s`_VHvk&lg{<)@rB;U=XZ!SH!DLj)LgX zptiX6>puGfl~0`z^6nt3Dm2eJdh7x_>^(zfy;j8xSEb6^tUH_2vhRDH+&?L<|8p5R zSoM!Lyq|~XvYoXj+~?tYxS|Yb z;-X&;&~Nk`%lbCYFtu{ArmXkq(<7gY^?Vc$FpQZlV21BXUnocz(!*axJ_PWc3;VF! z&+hSL->!l}?!$GH!EC!ru)|*rTLJM6tzq1v z4Oa-OdTL2W;&q3yf>$kd-PNZG^v>yu0o`9{kAaOwE*^UKz<<~$+qBTGrwMrl)pqRo z8jt(!t-RPa7cmnLY8&S^LVQi)7;Kpoy zv_U(@%x4?*DUM;QhtOU!s@7Vip9M+yD9LBe;Mcgr^AGC`U*F5@U9K(AiAl?^VGUE3-VE6uqB2dMPuk8GH6>->w~eg;SBYAZpEZ@!B>aDTR+rw+#H;*b0D^M!V>K=n8=A zR*SmP?vqk@$8^iU2O>8HhanXt)CjtNZK4VgbSr7ptrT^CYPwb6bz|#5NLDQ*tA=E+ zNa5Vc-c<~qRr9Jwx8P1th-E{eP`02D+xT#9p^70CMv}#a%~wp#vx!Re;N^Y)GHH8I zq`CqAOw^qGqzXPQYHSUZiD^nIMTO{QRA{ge3mO$ViWWL@7Z<5(E%#mt^yNJbZj(m< zJMsv)Kk^8G98`k-P{6&CZOvpmghS)2|4Y*L1Cc5K*e&ux!|nA5U|${)ER%AbDO7-v zvXa7~u4)RpD;4Y)eIfZlGJ9$Y>zP(VrmbqNilRb_nNqn{B)@=f8CwAsiW=Jm-K$*z zaNTNAx6)vDp6ONr*X=0k#@52_Ri@hkxNfbe8ygPYxu#nKT(@4-tu^>?rRmmzP@sB) z!W>iR1l-t)qOs0g_W~(gYPx0Ma$_q1E;UvZx>H>NaNTNAH&zt7Q%tuCxNb*LH&zt7 zlTEh+aNSx_H&zt7lT5b;xNg0u8!HOkiKbfzTz5rLH`W=$^+S<53^4Bn*dAcH$m;>F zY!UfPNU~p8vI-D%D{0itdoj8vO}7eo7Tv`xs)c0vOc=B1APY~{RZP}VNY)WXKulJP z$$E>)YK3IAvy;_hvi4%KdLdc;>|~wAdgv_ZcAl-f0^KF5(Gkg>rW7Vr;EF=R6(Qk? zy!fRcdRS@R@FoHN%Ge4pPA%@u1~=ZiK^dS|H1=zZ9PyOEDAVl%f{{uJN6NyiM6%Z` zSrs^GYzYX-s)b~Edy<9wSp`O$(QbfbOk~xr4&uvQKlE2JTiaRQj8t|^MW#E|TZ0oztdIdOO*1LgVPeWd*++H_;kwPuu z-%rd!6}a0hlmPc{_nAijG%e)zO3_|kebHVA_V${+E`W4+ugM~}&=oCoggz53)UbdX z8tTP5sue8sL<{*K*{5WuMNNs8lKu}-p_m?K@LONWocnvbcBaR&B@%n)s4@ph6Ft#b&=SudP2p;*sd7cRgCRaTD9XV z>r=RHvs4B!>Jg-T(>gC|aQ|MU-T~14GPTU?cu6LTnv;C_z=4vNeY%tI~@mI(ffMiJxhfR)WA2P%}I7}oDC&+hQ3VLPl{D(+3k2*o zOQ|`Tm4cHjT`6cH4rY%@^@OM?sRAw1{6ey|Nf!=SavG_%a_fai2#s{WBOa~NPCu&X>rQi;WE&+Q)Ba+Q6Da<~X2cs7#I8{VTfEQbI z`BDL{6*7pi^%$G?%h&!lRf*`lk zP~r#AmF6J{pA)qv^?O=s_q4nu{-=d-DA$dzByF7{6#&>_Y&)=1q}iz@h1n6X zJp$O4N5Jj$2mtpz^I{2V=3N!oZEOz^N>H^Dc)|0lD3!OybUT1u#&!cCSw|sRzUCUG z{KuI)c@<7lni(Rx7q~#A8V1Ou(7mGO9Mf#G=zPeX{$Eu#iI`ZxagEW-6}?&{gTPK> zyMWyyZ(+Fo9uew?WPK*80B#|l|AUA;2Nb={G)vJ=?p^g|&1a(4WOVXiQ)ddl(!(u; z;rl&2k}&)_5054czrn*}3Bzyp@cD${w|e*j!tgshJdrT`T^^oHIFt|hu7VtXkB6tC z2fxq5mlB50>`W`#X_kD9NYx8W5P6-3j7W5^D*y*`1-J(+q68euBj6shh%)f5v3Z3O zJn6B($0E-V?uR2dj68j);iNnvR2M!&~PGD%dtUeQPXsYrzdUNyD^ zoD_{n?r2G2tVe37$6d>ZC4FC1=+%!a_>_tAqP?tO!6pgJW+=cL61bK84hhj)B1RGD z(fQnaQdg%lcD0(Bf-P_0Lw<)g=CHPN{vDzk@V4kTb&=efOgYdr@)r|+(rs`_-f7;< zl$w)&n4z-(iehf;-Dia_)fi|zm}7L7>m+@8W* z>GH#Z*F>m;$4uN092bp9_H9pLK5%)+WoWW@EqZy>%>6m3m=7(s2DJQZ9Pbzfp032A&t0I?RhM54j9Y_KZb$M9sV}ysVg?T5Jt? z%N36bK5#ae42pPy=GzwC51?(Hz?^aU?pJm5EQ!5$fQ8NR9)8B2$Oi zr;C^R=$)JcQXzsV@egJLr1m+=^Pkc?|QiM7< zS0u-Qc_LGXX>)nVWoWW1ExIFW=8n%-%tDK;0VP+g2?m@ECW9iLpjo!)egJLr1ZI=V zPY6zlPzOi-ALckPMr7(R<6Itc8JcXQMR!Ea-0|^>nP9Os;4)X7DVXPMFc}o_1kGs{ z-4CE`p1`!Z{8hmb5$fRkE(T7BOdaNw%R??hlO4C{j;NVC{*hunw%8gl>IfCnF;+0u z*Q9|!h{OdV#w%R??hlkK+X zj;NVCen2q?Ew%2Gm@!N3g@$U@|D;37VZ2-4CE`p1^E%`A33}MW}=0 z?CRYQjJK<|uADFvTpn^6nry5^cSOzH@kxrg(PHyUKO&YEFUK5!*%E)GrhQ;V)e&DtxmQ;h5D%igG&7^I*NNYl1k%;HH;9}zk z`@vEs56Q+VJXxeQ1hJ~AI5oLg!8W*=1nPdtTz>U<4Mk*;rNLhG7@P-QV zj!1bM{GYJ(Cc!8vdKPe_Em;{DlSjajuTq4vVDAI7R{^G(y)Iz22z!+jZmUNCA)`tP z=l1g3GVI}vmbgHhu_YkbtC~HMYQHjC$XCSCLI)OVW}zDh7CH(Rx}$}B5JU^+!}(^R z1WYxy9YX`o0_#M2_VYrL!g)#CqumD23U%dnyDm_gt3+xM?5=edz}k7qA0~Gs6Gyg9 z%#ELy>`XQ%QzT8vYlkO@`Q>%ltQgNE-yFME)w{x)s|;*4wjJ0Z^5%!z?GeC%JR-Dt zG*ZFHe$j~Jhb<{g(2kqYnBSH(2 zY`%z%R&bF;m(eU|VzBCB00YI1`DJe>ZMTS&ac)$>_f1qf^zU^~A<{H4K|WKA!V``z z#q?Qh8CYd(K6FU?_B-tPj5zr5zy4-^`;7dAh^rfT()ihFr*t=nidzluD(-zz!Mj6J zc}!Fg^~u>ajb#{Aa9gA3)L$iSe=AZ#V60*r+o0<$t>8sc0FIh&2{O!tcaV^gUD?}_vP@ANhpl8;CRPj3r$LZVRj7&{^ga`>YnZ5kXCeB|uM zf-y41R)S!vvzH3KU0lV$D5ggkBXG|3Bj|O7(8s^((8gZj4cE2x-|H)<(Q@_kbK7Cw5j8gNE0X*>krD!LicC8gUVKztMx=P)USs=!heU1*?pm|acXqN0 z$qtG}BtL3OQGF}~V4m|pa|-i{NR*D2Ozr<$*wz6nBDK1 z3UJ8SI`FYeflpitw3-t=z!+moz-ulA-WJJnOA6yI_W+*+IsUuL`Bwinq}{a81CEN6uo-+$Br)JkxmEiF3V2i2fiWVifZlj@ zU}h!;=Za(npefOgO`JBzzi#~A?X>ha zL@L|@!6IYp4+>~&C7qncMz6<8tA}=;s?2bJDV`qmXvTxji)3PY3UgZ2l-vfK5upz* zutvRYkzl-Kej9xaU!)vdLOJ*(F&@!&h=U(Xj_O(~;u-z+6mGvr&sk}{ot8=W-GV7* zxf_^f>}slDolAkcTuOG{Ke|H}wEi&>*@Ewjba9|Lue1zGl;Uw`fhR@HI=cbV08*x# zdO1s>6ou;xIWUHc1*4dah6!iM`l9RnDQApax0-oE<`Cyxw z&!4}_-nlv@v)`!Xfsw&a!UsgHN$))^EAMG}NIbrVF#hf@gz@+BLikzn9~Z(5qM3BC z%pUD)9WDz$ukgEt_>Jz+6q@@Bt z5jDX8r{t}qz(*oI?b(*Xj8qPi1EWNeZ%<+HRC1j3Zrx5V^WoY~$D+!m@M&J`v#h(w zn$fS*H^2cAeu5`lOtttB=mMA{M`bPlgc%R#B|nsOA|iZpN4kJ*qGAfd zI|{PxN-cv0VA-lSj22e_hm?l<#S&+|zPK{3sPFgyCmcxa*#l_Iq03 z+Y0faeu5os7+~&Ak>*GMi@ItA!&1N|HlzStYiu1@DAEa}rW9te%g@fCgB-BOf~q5p zmOG;59xP+Qbdm2k#qU1+SryTuT z8cmmiY4zXW9Ck@Z4v(Jb|56H7Lw&7 zG3M4mviX**2MEbJ3d!dWa7BC zZ%>^va`O1|!RePaCF6fHC7M+KgR5LP`CLk&%qTu5QbPboMP99N&F@(R@V>EmRmEhL zVzNp~vcz;NfG5jOq{U>_VzR0wJENo;jDRQ0Z%3Yy=&(o!qY^S88b17cPqGstjbGr? z-42Q^$q)ZSbBgXMQA@H#Avn)BZ=x3EGurZ+nSzrUY&Q^e z<5m*7Ev8Tfo;9`|2)c1s3Ekf^g%03(W4nN$8($JhBz@QvmWGN!RB+2<^FDRDv49?% zcl@iBcA=Romjo4O`vmKp-6{A(XG4Cw6}(GCLx2y8&eJUgd;AZ!rUVZaM1Rtn5+vh- zRxoyN7Nss4L|cz*1tZdW?_R+(&W6~X3hp&gmDoRXHpK2$@NN^e$F%vJ@`PfZw%B|! zo~+;!7Xkgowgc-#jqQ)_VpFI9ea4o6)gtxVqfIa&VeAZ_sF1CuT?R&r+%nu4j{wHz z5urSEfYTyPB*4caPYHL%BLH$}bavDSI-4R=N?@*trzPM#;|Ke}QYHt>nLK2E<^QYa z{vw$Gb{N|Z+$Hkt;98YVYbao(v1I@U8eQsC}Dzh#mnIZ|BoIziR1+^ z-Pj7SROC6pEwhL+usn|lMZw6$rceQHG`0i;Bb5}6l!fOv)W|-O@&@h|d4_N=cm&Y$ zU(hK5Q$?-=cbP{7H=@02(Oxyh-t%U!3b?(lqP=Pw?d7vqv{x(ItC_vOGKigPWaC}eA|`iJk#v2r;`Mmx2FmY(2!DRPbjW3t&_?eTVN1@ifm8 zYoao+MdWPe=9{Pj3>w=D1iO_K&XeU=Z+uv0x>X?PR!w)8 zM*yBIpUX&AvDgkEBeB^lY5%l?`gWHHAGw{VM(OHxJj_p*fMaZu@&HHW4nOYjBS5g@UF3C;6EB$S*MIQ ziPVXK9~fIXBzVN7z@NJGF~Lz|+dmYXF}4i+H)AWo!?CAyc@)XR#{{oB8)7NcYRkPH z*UmUg4IDHx?GFmbt1w(ns18X-Yk`SHmqHX&RjO`+e z^DT?KzEPZDu^m9L6c@D1BrW86+;n@ebb(pQZyU-IJz=r!z>^|+Jov7QNi@z9=T z^_fqs-;{x7DQZ+Ur7)vKjYYxqL6KYn{?ynCa8z`*?g3W-ju_hw1l`!0k4pNa$U3#~ z1(A9g@RCSV!}b*Br!Eh5Fz>(V4nd>`CI2P;M9jKRvcMx^-U4{T zH#N1@M1`x#OHx{Av0a-4uGnRY%_!z0`voatwK-Xsg09(z=AfDE18SBizXFX{-sG>Z@e-56pBKz>XGnA8ZZr`&AMDLNqe@$uG7ZX!_=a z^teLQQ#U+Lh4K9+FUC``9{2SHpE_*$5vu&etnOzC1OjKwggl~)`~E0Gq0Cr zxhQ{%PDM@>Y5K>PZ#f&Bh_RIzn>*2(r>(}={3?1Q_;kdyh zi8@7kvKO*PYn+MlDd2t?e$;wi88~e0D&VL~fp=XBd~ED(n`PzIM&no_R-3`Q?o5M% zhk^s|WIEOpvHrm;7Y+od=pVm8Fz`^aarl zCH%43sNXF(U~Ku2;D2)I(}HJQ8XU%Q(VdeDYlg#}eXhA*aIdrX37&BFDZ#VOJ}>a9 z%GZzc&uGU)Bukxw_0Db(Y;$(M;2vj#C(R0ua}h8_j9m7%c-6L>>WmnMVNg@(8%a9s%qzwjH=z5a7?5H2oOA| zq{f+%N{b+PP)Xq~_6Q(&P)VZ)6+GB!Iwc@@P)Xs=cmzO`e=*s-W5!Pl_757y16&^6daZz8#kDSEa6* z9SHe$Siaxz2q5I!QOLK0d?_Y*#ajUKqQysQb=JD2rFBY5h-^o*Fl@EOp`fs`d6ZHt;<4D~swBCUyL%T+6@`FUL`=#^`8sv-eu!1184j)&m zXrQ{g^p=nWo~Fu^gm#NbLU#&D=uOmHMg{D@|Qe&$`p$|qA zp&z1Ro}W>cG}D(d!QvaH#=E4~75R=xqw%ERl(V6pK2nh6Bvl0-f+&W4-b;mnK& z+eBYT=5Ev7Andgk{06~db|E!*rASLNwB50K(0p%1Q``F@xec5W`HTaXSh8}fV4SlT z2yjj6!2*h>MR*F1wdgv4wml(>$?}Y!lrPq9cPaT@U@UJiZ6-C z7<}8J>j2u8aZHwHJfOHiQ!N8qM4mC+9*?+7aKE!p2=KL#F^W4xWDGuP(KP^V9aY?( z#$@>#d8Xp#m}(iAC-RKpZuE#Hg4NFU3-Gm&F^boU$QUeJbPYh;GLFgej6c>5N3*Gx zfw9g4<3xJ&nM_XMCVRvT0lpS8CfP_48H3X-x(1+a8OLOK#@y-X9t%srL1*t1Jm&1< zf)|{9NpQs2+UtT7ECw zN3d^uFh)GWLj6Wjm6%Ny+YRgzQR-?6hZ|Z|o^7dvWLrf|NgoiBbrh22PXS_XHIi+! zWVZq#S*?)l*0Xb~lWfqEbpat+y^t*5KUgk>F4HXotBozi(&VepXBG2;h>-%mENaz* z3LVr);a?STWtq$osdp4OE<*Wy)yf1>t1dby!%q>J@*PqxmY_$8v_$?z3ggbS<4l_p zm>lL>k+v=Xs@&wk$kOFHXjii41Il%8pxEpBrLbSrl&k_CFt!dH5?!F9!h4cSb|e$@ zcXu-7A16~r@2UKgODCqpPPv72b>LFbMW3ep`{$oO^{c;g;pB_HwnODZb&jV5=8CS; zqTtTtl5NR^t;r>yl4CS7MOOY;j(qRr4@XT*N&mc?dr9z9XI~X8w{q93f-YzK1Rpqi zN^siQGlC86R+KG*9nS6&oN>0fti_i|WgRWp&u0 zk&2IGuPYo7+;8ma2L)rQSXh05V3M&lV6temI+kkYkCIFF$^w$RT;XoPL1*t5jPAff zZGvEmv3(Z{4mx{C@QAT>;4#scbwFbB*5qrddo^x~XkyKZahc#MV{d5_Jn8Inf)|ag z122iboNP1`KS(aQT_zAsQ72PXg)X>3J*C-Nr4tx!Yz-JIy1IziI5+FIzgLBVEY z>%dmgXf=Q;-`aLcisY0ld?YyI>?eZF-flYudyK8_6@21si|TxoNT*fC2o5-Vzu=Iw zz(b-hC$}e)e~^4_V{*w|YAZzJt*xpP1ye<1)y@9l`RD)6g_Ea#^&)kPI2+N5Z;SN8 z1n{1*9l&wX1<4MzqslR1M{>!gWXg|{DHs0LU;m>&X-av;B{x; z5-hex>R2i$Ia?LH>g*eWW5!mG3zk@ORF?_L&Q=AlI{T*J9b-F=3d+_p9bJNz&H}4N zUsgR$-j;lAcXG)tRWG7BW^2)o76G$;VXu=Wd`8ritOQ;*whFu=q6vSLT(UixpuZZ*do&OqT{!ov6H{Vu zw05fkOGK;wE>pei{K~mp!+mIe^YW_&lR-*$WzW4PIOgp8f)AZNE!bvVrMgS7*V(%S zW2{qD&lgN^c9P&;XYUsra`s`tBhIfkDg1OGl6Flzh zGlJ)ht-m0cVV$CWrC^@-kE;cbI{TF1Ib&D9AedvVzq(DZz}OnFQ1oTZ5|ei)U(*=l z3V`T&*LX?rQ)dqg=37UoEfsVbdo$1{G84BaU(;N(O(qZ>agDbH?;2YJj)}gk4TZ_u zO?jh~5qW3I*SpI))h|U_Hv+F1+XcKX@})1_J01}(1|-{Oq6+Y$u_fT&8e0Z}g-RMN z~xSSwSQGa@f1+%lOg>=Iz(J&~5p#D3x|Fv%3VrwA@HwgSu(wI;i@CY+eUU++=C z;zAVsQqh-^A8PT)``;I~r3lEL!}i%r;i0;5B<&9*tH4?S}&Ai&~P+dUqYp z{VM@prhL!#ZY6usjI|#Yconq+Znqb^m?(UgGRBsP9bvI$0L50F=qfIGX}0%V1vqVN zJHTB)~ySDS7HSSxDQcmRWPyzRm8Op(@10LGj36*(|V*iuYb%`2UR#Hfag z3US}KMUlT{3S|KOMn9uMrKk{nLt(U8r~)YIEy&O;3DILMx&!dM>P1u0nda}vlt}dl zj2F2xaF2Kd@Nymjchn<*X3MAqkZ)s2u{Z8e0L}bZ;B45!V7}N7IT8+7&&o2hUGR zZR}E7s=F-kM(f6<)@3FgDH!eSJOL&O6KhP~9+S7no)_beKE|IA`CFZ3Nfboi};$a)rq^bY7@coPjPl%e56~HNDtAJN% zXK0V{a(jtLB?p#^um$$Gn0h*71?zZ7;AQNfjMQFMW0XZ~EJ+6?aVI;5I_chYL~rsR zrkSC@2x2u=1CI zk|-vj&b&tQE7E0))ik1}O-%x%_*-C=3#yK}{ST)isAH!bsg7$3>g_D9QkRrkxrUNe_pp6LK+ zHYJ_7@tm{4QGzsnYjSGFU{jLNDw{Ui-y>-aKVm+3wA6#)Q+a~ z;ELFgT5L#InDav!G%RA86)}ws7Vi%$iut^0Rj~%33UtMv7}CQ>18YL2h>I3{*pxyl zEsA5JQb<%dIxt$Fee zI{q_90c_@il?q@v7lhh4D4}Q9AG7O^Rge#gP=@ik6XpfT(Z7=!G~oxqM${ZIgPzmvYgCO(_DhDCh-~4SK;YUcWBl3AggozK|S8@P?pfRm11nZi!fd>T>UlOlkT9U&1ZgMvrA}<&6jvFwiIJ?%j=YOi-?Co z9EF1?r>|%UKk64v6SUE8-($|Z#0Eufvjjh|1n?yIO(mFn(a7x+MpR$;n{N(DG+GY( zVlAH}D8nOGj*f+z4wi^mItaM1>Wt^%1mZCeivH7(t#+HbE*JAUcKB(ZM zqE_`TiVBbUuV{>(v#1X#@(D|@)e^vy;5U`vQ;Yhf%Jim{tNww2r9`2bi9K$jQjE<# zJYNfq!lG@eg0^Ub*=386YFNJ&F8rionWE|o)f7d!?Ez_Q7KMg}$L6Ot^q?ZQS%R#g zvjo4ip{IRaTW=!G-M~R(OTYu7#{037Bs)wYUsfObJ$<6{N=pvRxC*ue%oBNXxLqC* ziW`$vNOt4zldK0=XKV$y($e$*!I+Mi<;L>8lX7mM_X8!HYsq?}V*b(@iua3}l5XIH zNFNp4mXhit%eNbNa&9Jvc~vC+;5a5eG!yNlYPP%@YGa#XSx19+nP!=CVHj~RbgjY* zM4U&Lk;~i=POo-$onV`@02Qc5xHDUK7PcIZsP;Q8k2-nak-F|FffpwqXQ!m-xpgg5 ztmoE6ZZ}#MU0bs(3R{d-DZVPw8T-w-+d(+n(Pd<#MVZU6V?<}Ud`y`h zH)nLeDQvMcb2u#q+iJlp2$I9{7#lpt0GVml3mSz95R)fFU(i&&@S+s!imz#SJROqT|pyi`R#wg?Ee88Gxgi*wBVUzVaj$!?RdnQ5N6me5zn3c!ca} zQC6|A&xp>dSiIRQk~in@Aoxlj2+_sq2q539`a{#*3;kX1C&q zLH3s-T@3)A{PHVO=fzqSTw<}n`68d;;kb|}StvcaFN?4aekf97qB+Ji^Tp78ih09g z>%`6#X%Yjj7U}feohgi`st5beNc5seU1;5U^1K6NPZFg==R-YCTjAT26WYS*V!BqTfh%J#y)+sjT;# z4>a3=N4#1zNg2$Vs)f4CFC3~DGOA|!I@1(HJ0-eHG%kB_ed>s|ztBpqRfio?oHN`3CsxvserF2eV&0%+T>|a$l8M18PXO< zBswaJZ4n$J#v47q(!ZW{q%S2~j=Y{^6&dv3&LRs_e9PtP86x#d;CW+9z>6a9yKu)m zB3QaW!HFV9Jvd1;N_}NZGI7+n%O|FUrxawrDH-8u1sQsC6uxqZjPO+j8EFa6FUUx{ zSm7l@WQ3O$WTYirE67N@QsLD@WP}F_GSU*JUW#QS{KHJ9<6~CdV!cpC4bM3OTo#L` zcp#RHNh~&`p=!TA6HyshJ{z_KY!!JEz_B7MOiouxccDnHUro{%v&5A|n&g0*u~lIA zERzCzMJ>tBf7F~}Z^Imm2yUReQq-I*PQgQ#t{Zq*q-9`}CEKN>nx=pQW+7ks{Zwl2 zTdEFVo;38K`KI(Ksht*CAY}KXvUt<7o0)>WmaucA65VJy)W~6(<?;Da>Ax>;rcj+YTIbDe$1kvVwWomtjeJ(;3+z;6&D3V?U9!F6NPj;m1dVnm$ar7<}OiTsL(U$x~d>LRI81M4&W+d ztH2_WRS?V;lXn2#Me>U(!;X$;hc&GyTA9j}r(|pepkL}8xk%K)A2>()_Z5Faq~^FYg*heC zAO_~iag#r#gxU0PXPz@D-SQlpKfGvj@_6QnsiNQ3#>a@Ze;IaXSmqz;YFy@{>ZYzp znMmAJT$$2++N_(@0ea0>)ZkhYj9S+;(QSpU6e0#gMC@4gQ0v&6Ci;zJ`|)YBY;QEI zXo3nG2k-i75V-3yYNZ$WSmaYa+($Dk0%%cp^@yU8<7T7+Y&IiZKro^g)N&(TMI-S^ zH=cZ8MykM3GtvzNBYLGwA+j$tJjs4$$vS`!ELk5AlIe}GJXyXRBiUP)tOi_Z$!-Ng zvYI7ZFpb=91)dO5?pg|W+#`TzriTc)x2&da1wu{56ZYpTgQ=ER4VW#mmk40ohuV!| zYa)gZ*d@{|1FROQqi#=Oys0`uQ|UrD;dga1L!@bHgWTFDVnq)=EYd6hJR;KD65CT4 zN+S7t0!qRx2%a|atw5`aq_1RePhlvZYJ;*J^I`(tH!7i7c+}Z(rI#0)d?o1}KQyyJxC!_a8qZBt;=Y)tROs?l?wWk!t(?d@vi)Ssj`dxVz z9c1A}E(d#B>tN3Fg8L`}&6fUj9h zFr=7YW=Bnf4HAltiSql_Wy-iO%N*P#Qt!i`7E4qGMv3gPE(|_OCAiv@EGLTzB1&+j z(6d`kc2A3>0lXy|k!;$Y!gw9!KQBlPVvxG;$ZJ6hWK3Tr(g*|Gaw!%hf23Qq&}SCL zdNP12)sT+HO3_#)8q0g(5xMieh@arKyH^5K#27t9m_3ynOuwr|hToEJFUmukgi2~j zw(i($&DmzIQ~?U(5z&Qw+~ey6kqrdlm7>CmnY8;%)J|0n83Ttk$-FKiF?h@-o!S{e zs|Kg$LZE7F4d@ctEDE#JyjV{AU*gjfxx!^_g3;Gy8jrLupONL>oJT4e1H zv&`isL7%fgzepgOIVPosSqau5KG~`)W?c)>{sTt4<*BLeQO5$?-qzFy$ z1(Doj4nJe{Rr^HXYnZ&TxLCPj2Z|n>H~ig-#gzOB7DpyKv(2!eA0?rZK3SBsCEp=g z8Q`>7aATFCv3P6}-M37) z1IUb>ZZ!6|Db#@APFzMEm-GWuD1R(C<81I{s)AJ)0UM320OZ_QFm&g+0)UbVCSQu` zagmDpLQ}5-cN<#*?iFELU&<6mMui;`lGRMq0R%VVMHq!0BDzgT?|y_rZBp!hkyQjG7mU3`ai2yDlkwV7e9Hw6Q%vNTwfUQ?l_QUBm#lkZ*60 zv0JDDBc-8NMh|R*A*FsG=)g9ZaU#tY047YS=>0*@OPGZ$`3|`?nQSdiFIS zcwIBEw^)`n;B{kH0jEVYR4s*j=?`$L2E1bID&VL~fw@!GxfFQcrN9Z70zGZ!1F+iI z8nE;llL9M^tpRVl6gcTp;Nxpe7f7yytpR7|n-my#y-9&}#;yW3xfD3$Qs5bv0^=5# z1z^0fHQ=yIfp=XBjQf`B3NA3V2DB|SDX`qw8c@B#q`;uDHQ*(e0&lq#7<;4X0^^OX z0lQoZ>~SgZoJ)Z>Tndc+wp$QfY-|nacPX&brNCa70ta0R(6zl=7W?)d8x?gR8x;qO zqvBw3R2)3VsOT(?iq68Q=wwucq0m_v3Y}pn;7n&4M?+^A4IU8(L}wTf9udbxXBZP6 z5r;)*7#1E8M@DBD86FV_M`suu9udb!XBZzI5r;@;7$P1KM@eTGB_0t6N@o}-9udb% zXBaCU5r<1>7%mn9^Fm;B(#~3o%zjcxOmwXD%Xwykp*BFAuP7H3O^F* z+RA{rKo zTw|-iViC%qUpd=>*F?I^1Fsv~4ls3~48Cet#&+O{NOw>pQAihWaLQ)y_KyT}R6->L=2~H85XM(3`HjU?6~zmC+t9*#v2Gh$EHA)qLkm!{ zYu;_ZI%AguU3N*k4d^#^IpCMS+kjmz1>Ui8+y)#ow%V+6xWD-q0x!+|?HlT^H%=eD z(OvHw>UxjWecu7W6UHtFo)WbtoAheo*HU<2{Pe}f>MNEt&hUM4PVd{MrrIH*Ipd7p zM+?3#8jGAh?wVTf7w7N3hotbZwfFArDa<1xC1l|EVy7?8-FNWk)CnKdAsj1i60l4w=l1WlqqmnMB(CW-glLT z;Uk-=!?pf6PhW3k1Vba z7^$w=lI+$q+HvB>i<+eg&K0TnfG@r(0K-yJV1tM^Soypcd`UBuq5vi?c?Ue^Qs7CE zs%m=*^OOg+r7%y27?|foN(^vukjeK2ABbo%7GZvc=!@5czIYYr3oEN>`OsQDbZGf_ zT0L|;F)s8uj^glOF7qLqfBbTCZnyi~cDv7Qw|l5vI-H(y(9JxH{KWT_UoU=?o6 zHY=!enZW(VmY5$#n&UkH*C^eS0@GXy%ogc9a8nB7r7r<(BAEl2;*}8SbSc2BAt`Xw zr2vzLq`(4WdjM95SP(1|S$;5n8&v{&M9L5FJE{^eC^BsrrW;uSo-notU@a*r@Vv;h zVVHR&2WA@E1NdB20&WzUHjLknmEs)L6IPtE!F07lB>w=vGb;giiOdEJQuoS1l9rs`aWzz9GV=MSH!gq*+djQ_ociD_Y!mgyJKMrGQ7_}m2URWH)~XzF9N9L}Wf}*P z0@IAG0CQamEHidF;A5^gj=36R?k-d41@0DEJHs#tWf|}RSOa{_^~S|cVXLW^vE>7* z7Vd>*A&#N^k;5U4l7~flr~qV}OZ$qOOZ$qOOZ)Q8rB|i?iKVUh9hp}q%I9lsrE6U_?yw<~bHF+Gdbw(^h(&TY$*2CB|c^sYfFgi^h$7el^ zPm{+HS`V90CXZvZ&V`=AY4SKq>tU3dJdV?PxQ?4Vj?{V>sV0wOwI0T*$>V6PhtX>C zI9}`FI&AVdGV5Vvy1p))e$A}|3`(OI`kr(MR>W#ag(bCG0VntmLibw+5S@nLe9 zR*||lz>qb09J}@Lk}(iX9!F$7j7XC+CLb1kk$&5%$E5@w6Ui{Z*fhmBNb6ycdWIU1 zem$%Mj8Butfm#m()#P!g*29L4$-~v{ghs+Ck@i?_%&$$=rCFbsG$>A!Xr@S_l>&Od z*mZ&p&IZMM6}-P5>8+ zRE7uh8RTvW{)xu}4~BS{w_F}f-J8X8dq?yk(Rtdz*qKZm*`^OqD)?|gbj`$+;FATB zvZj=|RMPqDFV$_3Qp0ra(kmBo2yA=13h{gdQ7d0hofagp+D}7h^zKem= zq7lg-Z%<+T7Gq7w4L{uJwL$c#wA|9n6ntCMl=P$Zrg@#e5k6G&CDW`P7QE>!K>Ft7 zt`-cuD}oPsQOBNrZWPfJQ=6HBmx|PqGX%?>WyicMX>V>>O$nE#!Z-MDs-|`WAs( zsvHuF2~|_HRQ^DclP0YKZYi&ur4lXo*mneEE2HlTJonuB`SPG@UQ|{J9&r}Pb}8c~ zV}4d}v0|5+Vink9Z23vS(=G)(c{wJ}&q}Ob=o^%BC=`5}L^DMaEfx6vLA5Nl=F*^e zK*9S>)DJu)Ds<)}3T7MnQ?(koN<^O(EEIWXUL?*p0s8L~`?yHC0?&zbqE4L|j+ITp z!;l+;L%Ez5sXb;(34>yz-Q|ZQdDx^KfLqF&=1C=e+LBiX6w7i-`D_wwaW<6ogo39V zMHeVI(M4|v-g5RG!Mo0ew2Rx+L?T&!O+A(+k=VBcN1Y9dv$Y^vBvJ{s3H;urvRka* z|L1PENHo$Et5XENrm9{hc7{uX#iz1c4ISEG1@(Z%R)BXzx^8YxVNSaIBY|%qtUB93 zF9w(s0Z`>u*E-4CZ-{eksh8qG0!Myge+doeO!x?2hEqYz{AGYfu~&x zyzElo4P&doTP_9MvwTiJlH0FF`&H~eE^1XL<4fdEh^H!aC=qZQ`Iv|{R$ybKRl^FZ zVXR2+dOh)5DV!(Ezr!MDDsc@!)>*Yek~=1+a}UA3D}WGget<$GE=Ak zD5#GVW9OTw3V1FYz6!bU(;8L%vz*3QW2v_rn)q-`#*0%_Lsi!3= ztTf#YfE@L^0r|-|UUa`(q>=*U&g1EF{uCO8M@^vuJYj4na7r{H(b-#=k(Na#fQ>?B zVBmZcRVU@Kd2xfy)?|nJ<-{}?9_eBAQmnTsVbBPbykGJsMd}~GGsf0|S6m9b=2GBI zmjXv!3LJMSaKfd47a^W;l;{zQE#t4}S_WPawdz1Q9ri`>r$jn@1YBulE(4gO$;)jQ z<@I{6R3@0p3aVwY$a^iE=b!glK1Vr2q(%bxnq^}n@x{x9t^n}W%tnQ-QB7^niDUto z_a)d8uw3N2a95AB2%yc_GH|WPb>J3QM1G(d2t|2Uj z<#HTD9EW(lMDPE%cRe4c0NYINtXpgC_1|aj|NeNM^PG?OydNbsgk>L4d{D%}@$SvX zyEh;2-n`)6c;M|*~3KG#?|KUl=pGpW)zC+zeL`*d2hQOQc!tK z%|hA1^!Me%ystJ)_9nZB_%q+%BH?2?;5v!E4)y4@`u|7@l^U2&$n=avdlon%;kz%l+*G|L z^*zb8jbCpJJM&`rx?rsFr22VEqGSL=zoxO1|9MWQZ=}r&Qm<75gWgzKW}mN>AwX|j z2eQ;aJSyUg5}mLBk6A&?S+@ez(@(?`{YyOLpz9c>j#!zN)xkD$-g7W3hQZvlTI z(L4YzOSGt;*o<<@?Z6ocKZY+)$LGfL+OopLJdJ96F0+Q_Pph!^_EmbDWQD(aRQ!t) z4Ji=MM`8=&DDN@?NnzLPWWt_@se$Z^hfm<@O9n?9 zkXL+?K31l+5hp%SmG%~xJFKU#CT6@79WT!Y^R7tV_(s=4Rq!fz0uNikUf^NPf!#Nt z5UFo|gdtPykmc+F7KpB%H&!TQ)SgO-2S~intOekS@9nKp;&@B8Q`z=g;ub)1jj#be z>-t8JjC#Isk6??bJpjo+rvEN;Z$qDbVdIft=#_zuwLrM&|fD~9?#-8Ml=r$psw=CG+Nfe}ieWE(*rd_0tnD#J^btOUl1 zt%)2@u346#mt4=Ax*8bF)t_?3hkY+7!E2VQ7a)fk+h>hUwhY}QJ7((Lz+kd_z_B*U zc!zsj8Q!pD-2ll(lB{FXX_ga-j$5JZZTr-i_IR z9ZYMWMF9q=9S@NFQ(C?qx|RR+#)R3ErH<#e9tXSS2XSsXtWwc!TNTc;5-m(%ur2kZ z)+Sagp2w}N9)LL;%>kxk%MA@((m&$HPs^?KVhFY3(X4XFpo zp*ZO;N_5G3S8&NyG7~Fnh|8{NLt7eY%;nb)7SspF2rAtg3cVIn_NSEbj)?2o3cH2r z1D=y~G`8wF!A;e??{Dkum4t2d2PB`6fBh%zM+wqvu8>C)ylr#Hq#M(1n>*^c_#aj` zRVkPLS=yCyardcQ2R4UWGusGbq8beCuHeu19A571{J(++f^UVpJKqZVCXUv$N!l8} z1UxPo*7z;`9<-Dv-F{BMjOe2-2Lwk<{UzXSiP(CvF6AA!hs4b1aclH$`gqZD-3^?Q zu(UwW`}0l3GQpTZ&lOKkGnL>K%hf}!;ksYdH9J(A9lgDH-?u(`gLi)Pw(!1Z-gtsv zDpQX{msy}+(xC_N?5L2SsW$gX^g!%c1)s76@kD&9Je$nh{e-}$tef%lOZbs0TP`EE zjIS`Pk?35e=MWRtzpgW9bmG`9(a8W{60XP#UCmLkwN`g^s=GSW9o6{F=jw%5DB%xe zg>USPrE%RO(dibT^i`Olc)JQOw&HgHJ(6LKZ?sh?J_C0=tSqb+{ZcN#%#CRLmcAp; z|I=ZM^)oV9^bQ-_>~`7K8%wrO?~-=Q^;WMNm|$wj()DU(7`NVvW0o1hC$hoDL}^hj zWigOJZ>s?8W%UZQB=%ku$~xcJR6QictNlE1SfbGLg7-}A1{x}CUw%eu_l->z$_U@s zT%lYi(QE@_B^^5J>z{^I=(F6#alt6`(Xew36sAn|fWu~A*H)ptjUvdt0Pf!M(2EwEdbx$;RJSK;_r z0T8O62YIJ~0+qn@wcu2w%n9i$&xz2T6T0K*5}_w2q^~?LRNvs6cSORnT&YPuv>@`cu)QNM4guCDQK3mBYKV6LglfkhJgB{~$c zeoQ~mVqc?3vmbA-&Z`^D*$=DCQ;|MNd*hahT}M&$epOs)#e0Aq5?1^}Lf=t6yOoSx zqFo7`l-Of16!wko|H3X3CF~wq!}uuOZ{_seF(FGOf6R4OwuZL=ykTk=GybkbV_wF5Y7wmQwI3VGl0P{BD6Vjh^7r?v+S16Nmt|aHX zwue>%q#xGU*;Y|tO4vY|B^jY7iOh3*#n!^i(pItc!Xe4`nI9VR@ z+B^%%sCfqFNNk=_$SHeM&?A8kZZq>8zz&HnVw)?J-*NlH0_sCgeJo3Jb4O|^?y#XX z)>y8kDQ&zPm?6)632)5uL#pTtBs|BqQ&hzkt$$Ltr?!jTJRp;&T?Kfzcc-@EHGk;z zup9N3bl8KJ;!^lU_LO_$cmEnP`9ir9??j7@&n4NM}Mjc3H<9#Q@Ip*zNEa-7Hj)Qr}HIuSh*3vE6%K%9|2>PCj(qfO}Y?IZesq zoTf}IyqApFdSB3P!)Of`bhsK)62nlKWbhe@j+~S|y{$Kd={@(Kl$oAMKz?QnJruZ2 zzEYx@2Kr202K2iXU|zF}Gck+IQ~--5`fShFE0i9$10=EkPjKU~k6#*BvFVB8YmHEx zhEnxbVCH=;(d&%c?PW&`SZXgj^qYYwrNq}n7!~j0FOXghc6pYsU`F@V2ZMB_Gqdc)_IUKT^G?jY|?m0HYKUeW6LRo^wtxu}Lmn zw1ereHvi07073QcA-rOQ0tkfE{SjGD8ethgmUjJ*&Ab2`9s=FQXs z=%79h2*Zs~0D+LkaYlsej8IF8IU5I?mn8W(f-M^dB|5xXSl-DL^TQZjFZqIU|6g7b zu&()-Qx(!2kA(Orh8WCQn{2*frpUToo4@ZYfS~#eLD*=70(jokE+BBzWWn8Ogc1mZ zbhM;u-FdaNSX&Bv&N9RWP7LO39Bi(tv)Ej1rg*RCTeG69Y+J zk?8UdylMG*0rHK|$a?JKZESgCy+BivoNW1Q_J-L^&NTeqF#Kbxv2`oRB%^Vb2b&iQ1fR>C)Re*s@iG+gDM@6N0ilVHdP#|KJN-w&>V3 z^*kXc%dze{8Ore? zv|!65NZK?OuZ9$P~x@Fo_9wW za0)93+il+dM2yb_60wB1!-&m9j8~71^6WD2asUSBu=2)XGj6I9KfZ2-mWWONM z)de7@_HLfK$Wj-i{)d)f*_@axt~rutIQm zfuoJtm6&m|p8B8KI=?H?EC6S22tyC!O@tyRr2DBvC?UM647zCoLbBBLELm@r@Z;&7 zH~sjyYK}HaN%m^^QEfgZp?B~}iQb#uSfM=S8(*(bPWr~ic(|?pA$^EaqQL-1B)%Wf zCQL8~@UW?I4pLZ=hZR){D^gf|sFlLXJgm&Z$`ls&O-QPz6(g$Px8LInQ%>SN5@rCT zU44{h?ASQa*W!43L(m+N`fXhCH9oQX2J=vrC~}7Ak&SOQHV*HwkDZ4!Tb1HIiT=Un z4ITO(c*Vvp%Uc4wC49q)$35uZaaRZ@_3IKnTD>4>m^a@1;5}#FuL2OmqwTR3{P$`W zw%*SyKUf<-8T6R$ud0wrYbe!>H}at-15eClp_-1}P{w|qoO<4MJV?)t*JVqhRRvs> z_^Lu{7hjGr{=l`J8`$>MnHxt`fp5+b@uZR*lPC%Bvc$8aopc94W_RR~&lsTqPMF#R zLXx6FBQm>eQ1DqZm4MeS^4g_^{h!7ufKWRf$f0W+N{9{P44s=Z^d6j{`(4WWpp|F= zB&-h)!UIMqfX7X30)d;(K_Qt{4C#heT&&P;%hCewle9PPUj-81-dG#Io1UmeMqQCn z}9 zjia5{7j?2?gk7+(0w^tPIRKHcG#t3^7`FtD8MhAzCCVz5h)>^Vh;UM(pLXB2xk7XL zT5X{nn;3j($0a&V0oPjx1fhM}8gBvK8ji59UJ(7PMaDDCNTt3`5S=jaDao+Lh|UV-Rf$ebq&g;n1HLQ~=Y|U9^q>Qz(e}o?*k)do-cCsL zZ6InMvD5>=a}r*3fn>GWf`2SgGr*Wn z`@&Dp8;{BQoKy5V0Jjt@RfXNa+SD-C+ z2hfTRv_5wL+oK~SC8b9ed1O%$*(=dKIzVJLs1#P_VWowA-MA$X3Z|=GYW2TA^6%7Y zD%i?fZCR@yIyWKGu81KvToJ>}nlsF8aE94s_y=q@TEG#B?=ZA$$JwF)MoWe@wymg8 zR+>HDS*ILDortZSE^@2M9 z4~vKQQJMa~X@E>0aXJFk=AD?EC7Qc66$%~JP8a8t`7Mctc2O`~{_G8OylHa8jOSplM zPE>nj^<*DH_|Ou&mElACePEDaD>e*i=sASWjz}~!z;hBGHQI~r08U3om<}S38=(LK zA*oGeLXoLx6=m;qMrbHtE-jetT(5|za=N2$VQs1E;nPBxp zj-mC*JH^WYQ)3yl8SVgPM+e#tcL2X3(MLB{R45OdJ)WLPKFv%8;OV;abVWtFKIZ^r z(Xktn)u)_%^rf>DFw@i~5ZWs(-y-J#-cdX)Up4HuD|5eB_k?}a?yowdB>9Ll8gke^ z4HFsmX~<*FY~QSj`=)mKPt#q5>6Sk|1WNwiaMWO0CD9JJN3hM++`Ga|1pqN!AK-7Q zS=ic|S<=~+GGwr`Ye=QDYpNN~u7S$gH8GckYC5}yGIn;Qo_8J3uB?!Q5*>lSlM+AB z(4KP#a5Or?cp*G*g!o2aGR137GR1fLhGZs3{n!o!+mjTB5_WSaPeU(A)Hv{xq@E=Z zEK8sa&B6nw>--@TFh=58&}O;=;GtnXJ(0HLebOE<-`+Q@emulKLc(#JL4G7F1$=_5oKaPA7h4p&qDD-fHB*i6KD zrMOrhAjy4zAmb$fMA3+nKXUiV?>2Q@~{&^`mh}egza$juT{(r ziQWr=@`S6wJ4u^UC7c#PpPOZ{e8S`DZSV64?70?o6o)mE6-N0jxF(c?|d?b=*zrg%{rNo@(Uzf~@e zh;QuVZfLhzbU(0A!Xq(ov^vP%7~CV~Ompi$9Si4}KCc4%CA>Hq{5v4(lUDz8)l0%x zBs!SS30`;gZNWuX8;Tun@vUnG*SR`QFu~QE1yfz6Zp+nBYd~364rUs(9TwwdW5uKC zHEsGVMAOP?dM++eW58pkb^!<6dPwlBTY)1IowhdX-{ids2qde+% z-~|cvFgBeRL$>L1`J4=pY==ZoqJe#qVGaGyE0p7IPYL4JJVJtw#<0ev?|!ig^}=>2 zbm>Qx&elo`U`^GRLLwA7AuWZS%J85>3mJIE)aDBULbK~6#D8w40(eY9siH!I%k`qr zPbh}o9+&MYiSDVNi^f-F_;ZQM1>PBLzV5s~k30--x$$%~Vz@YzIbDX^B+3ZTW_=10 zp~wko3Ic)CAdDW#$Mt0teWqf(zM-^gFl%NCt%u0L+DpaMi~;1(`%Ni2o5=y4X7906 zZ9IR!J4Gcex&@4s_#n`3a0fua?1@=Jn;zB!ae{e!fN7Fz8pAIAKi~agX!f{j{CkOB z*1Rlu-Bp0I}gwS3`#o-;r=8 z0RL8^tUyCd-jD4NjoUt2)vgM zA$TX>+}7DEQLn%}rS};?n{WNZBNXnh8@B)gx2O^~z8;-5NYI(;oEBf~e~j!mS&kM! z%KD5$m|%ng2!wQ)&iG*+-4b;SyeRPuXeZnOoQ#ez))ZOfkwr!1OBPuGAu`q6BkN-l zz6Ue%gYU~evMl34b8NcYLB#062zO7+KC8@qz&bx?1JA^BHX2u14KQ>Lx0JBDKq#E1 zz+;1UkTC2aZkjsyoJ6SrCZImsPw4zJ+zG%KQ@emk66c~#aR)%odXnu*^0=MIT7c!` ztQp&2LeE)-0$>-DA{KahNQkLAT*3n0uY8ZHvV$l6Zj{azXu2j((gqKmle znc4>gZhG}X-k&!@H?UQr>+nJlvOX8JFpT}}>AG>1O)CMIVQLc~NxfaT?M5hoTTJZ& z0ynh_ceoKsV5X^kK;Wi!;eOHx-M}mf?Shc=cApXT1&P`P-ZZrdSi#!K7w$156u?`i zb^(E#+TA4UE+e#nr%Y`EWT{UB-204B0EbNN0s=SXT_S6b5n8|oQ=0%;>UpQg(rJVi zuqYDH7P|u==jD-ej8FhSZR#>0Bq=I1BD3$%P|&$$&Mh-;e1Lvl=i`fZPHq8{EK?I8 zOT8Vq?-;iLCL6a42;4M5Tv~P*w*{OrwF!`=o)_*;BNV_{Q@en`O?jV`^@I_Y0p}!I zQ@4YVwWe+lhrn~%&ZwscsYBhP^rrPE8Xt_~bIzZw2!N^o^>h2)cI@{r-P``zc)i)P zKr2I{g$g_^Y1f%4{H@dWZg&H)+Z&tPg1cASzwB;ct;DAS?N{9akfuIIDYD2Tiz-DH zd1RWgEkD!NdA~#*1A8Q%8tu2;0Xz^Lq1zN${B8xooN;S(ovdkjOJTjd#F8;L6 zTl1}3V5_N3V7J5@N29mwl?7p+GHwBEGqno{VMUd~;uFUdRuZ<|!uo&^R%T)GF~~R( zrW&^g-eFhI3*L5hyt9gMmXpHw#qyLP zJ%Tx>-8n&Q{bL43>bokQK=HDdJM=>WAKx<0YHZH7L&o3_!@MvUH-aA^7{}YEBws2? zmX@|w)hr=f;tb6fc8F)%JeZqIrDY11kSU+~&{Ljcr24z%ChsuxliRM8=WUJcT}g-T zG#MFsyQ&j6Fh`!Pk1lDvl35+cG4Zdx#$R0h1)vx?`zLSQ+)Ap zKAPeO0Fo(wGGd!pJsJ@I6-T>~@jsF_!_++_Rw=W7kP!$0`u98p>~{|kV&%zWTXJ2a zAF3X#@Nn7;tcO*hX?X^K5HMKbA@=|wHmgAFV!5u-2g?U5>`t4Z!Xsi0Sf0CRdY`Mo z`@EjSo|b4?0q;nB^`L!Bp>hE1+xoI1@-HNMumXfg{hW!mF1iBa_s+s&@+EX(JTCvl4xdxUE77?9|4 z68+Z|=iE5FVw;X-+iY>Ng*}_n$7>;`mn8alRbbtx&4Xs@d0Oy{tDzsg;-C@ANDVQZ z{{O%(0WIJazZwANB|gz;T)eWge+nxIJ7(T403u;&9UYX#OAO^w#<`)y)gtre0yk@i zmms&U@zhB^LbY;$5LQ$vOdq4yb;vja02%7t zrzB;bq|B1&v-2UzU3rppK}bou^CaDtWS5oi2E3E5JW2Yku>Fy6l~xnsduI3$LTQtD z7qCLY2hnFt`gI)utF*O2GBQ}SwAtR|HZ6CtWMkX+M0}Z$I=f2ijCir)^g1$y$LDsh z$$Lh^Z87+kM6aJFDqy+=Et@HrI-8KD3?Ni$DUR3sT?55${5NRm!JZ+#TPhqf_Vc_(-YV2Xsh-fj9R4fMJ0 z0v2U1^p?ATor$N3{8vnOaW?o_6(!;Hay> zzcsaZLGX%O!%zpbxzbI*W>c2|TO_^`(daJw%oSm)%v1m#*2=?*im+|QX#r&LQRKBZ z8leO{Ns%WhEs58T^GI#ycIVvgj2rI;ri(k*O0wLxC!o20WP+EW0TG&KO3e2i#>W^+c^A~ThMhZT94zN#&UhsEI%=G^X_+nsUa zaL;^2=Yb_uZ2>K$=3jGY@FHz`?MtV?=KDs*n3j* zJWebV@vcOSQ-Uk09*6@^NwPh7t2UiE0Mos36_aPP1;j)5 z9&PS6)17qa0r6;=s_CC=d!hyWj3nPtxUp$R0neKI{w8?X^tDZp+1Del_;e$Mm4xB; z<2CHp1+pxZXuf&`t6aTDu-?@zf*r0N5FB(B_ybep@OFJ!mmY~S0lz272Y?%!1^`S_ zFpYwfO<&stX*eH13M&blD7W?j0NckB;O{K7su*WUzE+B-JRSJtI z#0%oiGj0=DAmNPCBYeQk1RWhTgQwgKyklw$7-8Kk2S%CN1UlV1U$DWg8wGn@1s*W9 z1w821FiYch(C+CCL}>JZ(4Ky;88+Rp3`lE!GP*xE0vu)*XVKZUydl>jQ#^+zRY->mdP) zT^)ouc>W*jwSq(@;Ljv^Q@F9|hyva*_x(-qqUmd!AVbSf?x$pXOQNi}-*>fLtPU?f zT5z4Kzz>;P+#s0f*2#h?u7*|@E6YmH1ROB62^^Aebhj!rdd^;Lrm%uAy!Er=R#|ph zOzRQBqppUkO>I7Drv8*X9zg^0cu$u6aU*smV!SC@BhOm%HjfB~^hf~atnJ&h`DHV; z07l_M42>m1krUF3*U<`@=ox^UB>AqzjZM22SYYn^SAe9}du{QoJz3kgO0sn`^)~%4 z2#HL>|J2lYwOg&teP)V#ESch|faa*5&BL|Yoa828vcw0EcC$MGLhG|K zT9)gLunZU{VfTPHxEUZR=8$|C%RJ=95t5rD%*KR|kR)*5{6{*LB^nekQlZ``+9-(} z03)rBfXKhK$O0HHf=&Xfh=Z(!6>7Xc=*}kYd6`aFa0@tXY7;mk@j_@6$qtKyN_@SA3OmEC08R9IUyZhI~4LSEJOEWgBh|nRaVJ#k9k`FN^Z zygi<`*oV(bL<-b7z;XRkj(t-s@L*{-BJBnkt_QeQd{ zb{nApzGG@P5V&a-ZIE@N5n2GD^<)sX8leEbWokDNxGC8>t^D=A`hl&IdNK%`j8FjI zFtr;9+>~sMO02bNEr34i$snvVLIHfu)Dj5Xlx&`?^Nr8~7E9{MAS^UO0esoi5(wOs z?3nsJVXe1-_NDBLCNM%$&kOfe;}*bh<8}dooASOU!dc_C-Vi|0J`M*l3-xCtG64%D z^-?t2ZGE=@rsr}((+CBy%G4$hxT%*@E!~3@Rt=ac@nmRQ-2rTmj?gEOql{1h*AEhk z3hf4W03l^jq0Mv$FiS$MqC%VN4q#q%pe=LVK$>cPK3+uJ3a z4F$Vh4c^1re9=tt3_n_%6PyLiHnjDAS)F6}3Y zW)V1H>T=+u#H*QRN#dnGg%yOoXkmRo2rH@-7GF=jCc-<$jrSUJwYk(xEnua@tD^m? zI{+%y2Tx?55egtg78Tk(?f`b0+5|$9G(jX;Ct=z_7@CW)2i|Gw0hF77*`_uD0_*+2 zZ8t&z1VX9>VWd3N0i&tD)>$VqTD_6M(>at+}!cI00B|Y8S9o;#@QmWp65{ zu!6Al=Iu|!cu$syCB!vGY(hNc>N&xik`aw>HSWJ}vmVZ|<>k`8mC3v82G&XRMig1j zyZVN}W8%sRm6;@hRv5Ddtdd|R!ApZWcvhmBq9sojci%#pHktP>g4`RQ{XHhr0rR#1 z_r_;_m<~($G{gpdCIS6VB|Lm&#N*>(`pPfp8zB<)089}{CpzHAO>F_QB)(tJW}Bl4 zFyQ*mCEq#AR{+zD+XaLqx}*nTT-@rTiuN zUoc`5;$*+WnJt(r8PV82xJcRZa&eKSEZt-|VOjdfGR3m=b;g)@9wX)%39Au2EYT=| zmrPv_kV95rx}{nU++u1A@J`~=-!I}Ri&;U8d*d^?5egXRv4DHy1N(mMlwXsm9`KZ@ zP2d@c&o$Z$?g0LysV#v0UtfddyT=FxaLCjyAml45v=`k0gd}MVu9tO_5n9^?J6(ND zaLmh1PNh5R#ja?J)FwdAI(ND(vy9MMB)HwxQUF&A zF0{kzmXU4(s8P?vqm}vgI;Q}5Q3xSTIfMm9D1ksoCn^YEF+%)o3@;$}n5h7G-BnKt zVXqNN;CWNKfWS@ppX_Pt{1b^r1ss+55YS$92k?KGS^zIe>cdP)iabeCk>t2X0-mJI zlccFgNy8Hx=qmh3?D?b!Ua{%nNmAh3?D?b!Ua*LQREwC=^EDlX2sVs>J;tJo-KA z#CKwo-S&n=_bzEi#mnSwd1za&Gl2u9-Wk?TTO(eTcSYjR)`?+%|M%>;aE`ezX1Dd{ zZSd{2Ivu8`=mZ9$!_Xl65P=kwSRkC zBi@#dmTkOImxVf0v^m{OE#M&uZ>xQITt!}z3~q*i4Km@<*IcRUJ;od8C3m)U{-Q)f z1s*rG5BOi)3cTu8;BASYPS7s8Ba}+Xijd4t4k=$jKEm7)A_ru7%aZj2d5#HF7^<>?WC?lQ732*?MjJK$brx^-YOhv!p!nZtdYnT=ulokO%aU#aZ7OnO&rW zaZO{ywx5|)p}sEB-b@wZ1B+Cl3GpQ(Hi458UYBgv>k{-=%+&(UX0DVo9>zqUl6=CW zJ12cjA7{Wooc3dwhNt>Ycn&Cvp8TgonA zp2Rt5OWg7QN39N(o^0itx5ZB4>`ar12D4B1&eY}{$q4`2a_6Lqt+_^O0q~PEjEN;M zVZi1OSR(Q9=Y)n43SgAvn#R4~*s`%2Ep@DUngHRW^j6P?#>B5R#&2qjtFYWA`LxcZ zts6#u@WE%l*_f#7tE4s2|NS-YMUo$YBE~q}H-7NJFn8mkr4Pvv`lK-*NLLsL-_C1! zqQIi(`4TPUkUKj=O_pbhgs(8_phW$Gk(U9T$wTbov>CEblWC@e;}rZ!i56z66qoIM zExRxK3IsMubb2nqEvBz6K~^{RP++mP*O^UEfrM~W0C-@~3=)0 zO7!Ext16UkiGJM`=n3{v!AN;GO=qmAP&~58B3D#dWcp`j)NFZVe}&?att_%XkL-`9 zJtFCfSt0eeBpNEf*z(Cbw_M-lljuI-I=LnpGaf>CI^2YZ9g;ouz1XMUAhg&PFh-)( ztH9%u`XMr2mLn3y1OLv{xT~jVbH15+)(CdF`jFr$SHpBpRm}ww4F~9xcpbD~b_cM{ z)GmNF>%F8TMV_RnQj&rs&smZt5R#;O`jn*1layJKk|acCpV&@e-FaAd7S^4@;)O1S z_2gkaSy)dBi}!D5RQ#+p&;rhz8gHw%YxAI)3gBr855)9!939wf{cr9B7)HKuj%)kR z%)N}PKFWB!99pL5YZC1y;Jm3#;0=lI4YUjH2z&QhZC>xDse+!mm(9D))B@JK7kETc z-^Gbrz}+ulZGw>V4=5yRnNe3{)cDwjcE|PFuz)^Omjinw-T~U8J8Yi=k4W5scF-LF zd$itj%3hFtwM6G#AY|9?lxd5|?1Y@c%GA_~yea)inZo8q%jE+(*zQYT%3o9*1x$#NPB zowRK7SYJA|0AY`|vOT(-JsLV`RUvzQ(LFpE%#1%Sofv({rLC4M`26>Ua@j{EF3G!B`IQl%^oYi=S^6we$Bn~NBU^{3RoP5w;#G+>j9E8! zi5O2kc*x$NA93L8hoRCZwH<2dd4DMPF`2gxmw`f)bYz7%^eGbkGxEj_J9J~s28UiC zgndat`p_@Mg&a~t_^^ilgKG%QeoXE)MO?6`@_oS%C~@{{@rN|TXC?Yh(c#S%+8;|q z0G^MISERiew?ab%A9m|An=3RAF0x=bvS4lH!ACs!kp7)U3~pt?a%92U%7f`n;|zps z$k%C{GbJ7R*fo15Lb( za4|nOJ{0QtB|S-%X!!!WOl<;3CH3P1?n6c>fJ3G(2Ld;7e`|6La*gw$A@sqKN?(tf&n$c?-OA z%^Ocl$y?%`XWrPtdoq0>QRY$de4lw+z!-^MG@RZPnwTKNt>%vtGCi8&O*7@rTf+G9 z*kJnp#=Tp%ocYE^`{dgPA6%1t^6la;>Z$uGYXdlA>I&e3#P>YfD%*uCfHkJJfL#*j zpzU@Czz(Y)L8(wdp;skZFhD3&RH@K%3XvpxY@9NbWO&FjG=Y$zv<&0#CaejNg*M76 z<%_Qjrzvusglir6fJA!(c*E2I;IG_Di2-GV4F0MWX#v|z9RN;9V1WPG%q^f{0~xqh zFj)cv{An|{fF4r^fIHm^taK|t|HOqgkxf-Fy{8thv!Z>#7*k7t!n*L1ojln!c$BO@y2J8JRKI$Oy0P@@sf@!;KwheU(&*U^@<_qCmQ$f-Q2OhF_F-ay=DyK3K9Cn z;ux_*7mN@z)IKzBbmRVgn>$i$ioDztVrLAFExY&X)AX{~h7LE_`I)HCr&(Af>Q0F= z07UX&POqkJ9G1@(m1at`Vu2l|-U%>1c6k_Q_8>k4;a(-`YDq`q+l}AQ=^owpa{O*} zXEgm{7~uS9TA7=c%G}mi2{a}CC1$kc=7?vOaq4Zht&F%>UihjG7Ksia;DAmnT4=yg ziJuJ6UU3KTW^|x&d}m9Od@otP0(jEA13<{9cipu0nmd4yuc%VK_%?d#ucW`nEo?au z^63pYZN2IaAml5veDNXi$d$Syl&}xLc@phxV43gzZG&ME4lMVyQZmQYG?1+htZ+_U$8qe+yI}GlJ>@wrB+Ze$| z$s5M;QMhR|E7NG=87Yir&WDZVdk%DB9O;}78|U|&go#yHyno+*!t$Pf`J$~KRNwqw z1a{8EDjWp==yLjygFu^?9Z^Flo-*u>zwc0o9!{VA9t%@f(6BC{e%QJcHSCa&kTuNt zP0D)N6x3&ZyfTL={b7;6_mn9hOxQH{LCbl=riChADuFk`8^!j)xxTlO)~*+GL5k1IVb? zE&DcyoVF1X~w-1m=n2Z zkGTVQGCI(xknOdUuOQ!a^9}$ZUs0hQa0d|b6;;X??+4Z>$qeJ(McCu6CSrV0`jCh( zN=E4e!GCkp*Zeh@<~btoD-zv50<)~0e&8ofZP8?} zTY+D5E3nt1zg`a+KB=cz*~|ElXAI}GQH{n6 zU-YlH)nDXqQl;OJXljA`Vqvsh?f|G??=tV9bqEa5GkF!{sR=mU!q4H>vjVw1n+%&>}$ zF_L=4cl6}vJ%9QGw8x0u!z(t(SdTa^+FyDEaKY3jK(0Es^=tY}r9}Mzn^1Sis z$rza^{&9VHV)jk;FBU^DBUy}twy-~-Q~%?7Ks)FP?LaTCK&J(MA!N`MI)Yvfp}(lc zUy*R`5HODV>_T|M2n7%bX?6!>U2B9E@PMhyfEOg542?wD>=O34nF=6qiz;#B?81H4 zxFry{WyX!OyIll|XR{l6xzg-Hr+zlOp`9zuE_7PRW;b+nrP-Y%>X#&%U0|N1KD#G> zRZCM=Ub=!eNc4&pAXaf<85|Y!KS*Q(2&|`CC(C^jQi0D&^k@ViHcK^Jn?K|xV3Da^ zz|XlAxLx7}&{mtH3!qNDa>`ebZ=rGf0MA$C`HG5sYn%gwd}&3^lJzztv;a>MckrHj z^u%4F0Rg8??E?PNt-x7{H;H!199;mt*1J#n3i6#YZXe+JiacLYk?(!y03l!M{+O(< z8leSvlGy!`U)CvEqO(76UP3!5`~g`WaRLCpPH6s$?rbF*KQJJv59rKV{UC)z1YnGD zyMXH@?TxR^0&kOe9NHp@)?HX^DMdkwN#<<=A*`rUSiBWTVI^S;#OI?9AZ&eDpbSy@ zM<7PZ_d^mj49qiiIpA%@V_>}|W2b~AzDvklDJXQ^shV99nSh<9b^-Uh71$&3aicw9 zjxOL(bX=aVAm0w-_5q%+$n)tV1#%p84iNICU3-tL+l|lyJV{&`=XI5w-~$2{o7x1v z;?^aCez%4WiFrq&)dV!;wV!uKA&IY?8>B6gXa|#Hz|}m*kD93jR+!ocFx_NGZ@N*> zx!ph@q_06ixL^(S0IMunKM=U-|Ao@vN+T=>An;=i-71*=$LefZ=NV}kK>yi|{WGd@ z!pao@)qTieaMLu;(|yVTR*3KXK$s!RoXf1+?$zC$L@Nn+L{bmiDa&rjHF{(8bK@%1 zeUj{*S5iDEVXcDX$kr-pG0POZ@o8e{ZNB_H&H>h#+69oj-VoeABNV^}Q=35GrgaGS zP9v1SRtYzNAmscrJpkpyD-pAt+BM&c}`mZHHmqBFb!u zasuS5kL6Zb=18v54U#4o6;gKdFjAX0n5hMjv7Q3LSR)ibAf!3KI?V|HgzMC2t0Vp+ zU^ShV;g}72uR)@of%i=90;p844fiLEPyp|nx*Q1H)JEc#aP_YlRH7dU+;s3Q5aEDC zA8Bv&j_R!r4`vM8VScyCzDuHue=zOPCZRfXo)@%RnfT$h;AN@erZoD{XnxBh`P09B zS~-{etz?%Ei!y7)W|s_YMc?VkDSw4<8($&|6nb>9YQOYB-uM7I|sdC zq;F{(9rRJBQ89%FB$`GBeb!arP06sv`pp%}yKWETfO_0aC2&$Qtg&%(h4P=>9;i&4 z@26I(H9*%S(Mkh`+pdaF9u9r2t@D4E$P2K1>WeQC3J5PtIJQB^*^5q0XCyjjy&Jvp zyEgC3G|~d%1&Y+CBup6ix@qXTV?JAk#(fp*Xxz?0E|_LMsS zhFRY$bT{1y#R9<+S62$)W;+Gqd^44Rd*dF!JIcJ>0P)o6uFz;(-$Mdu)E#K|xdV78 zI?!la5kP1;UCF66*9bj;cM_Ke-;1X~gDn zGbULCQ=;E(+H&T^2Vbj*>&*>p^t)l3G1wq;3<=ANro80pFbi#s)w^Y7v{J)JrCuI$ zcZ#`tQ;fMg#oT>)%pED_j;%4~juaC=bu~uQd8bz{Amj zw%;AVBhi8Onmd3q(Sdf>9RRzwzCP)$*9gUW!B$rv62Q&YC&YDTDgpP#^@(@3dAkAP zeHo(BwiW|GqwYXE><-{~bfD3;B7o3xTA$QfYlI%aJBjO)@=MLz-6L2fVSR!d-OLzi zD_fs1nT33P62X+j#YWuj+`z_OH~9KwgUm4`tQ(s0lB>fkXeB-;E2EVfMw+e96mxfq zx%*&@xjV(g^_gPsNHKRj6=Uv5F>!squSZ5B#bB1eQ4+q}WJequ*Sf)n$ObzgGQtpf z_;x^|Wez+p@s);l&>eyM;@7oYCE@~SBzn;J!N2+7k2Y0oydkMC(}S`+Cs73Oyd*}j zLB@K-4p|9SD z^=0~RgR!BDdTdx|A+rVralbVdpBl{4=3Fxsz&weL+~4~PmLVIo%IH$_SQko^4}g%p zHkqi+sqO`)Nwn`g9~;!G&sIa0Q4)^5(DSw09wX7|2^cH+nEof|CpPQj2W(I!J9VAV zZQ`HVtzrwfB;mFXBzyjnE>Vk&x+0^-uW7ul@OLB{9q@sv@u}<+-_Yl4B$@_b?pD+R zV7|nMh<4zc<_IG@D(;Jt_Qvcu+FLo5JB z>yAJlDa#tS?n@u>K08>9ogRA07r-eMIV<6X)NnW1f&EEButl41C^9I|{yaSumsPgKN1%@MB z*eW!Fn*532&7QwPRZ>$*)?$2KU0SbgJDZ9u2Fp$75r`m^YSesj*-i+5p8%$xu7C)snoi zU>n*PybYdXY{w1hP9fOy9KklU9`ReOUg|m7(kH8uEggZuHZ&*s7$Q@uw3@I_mejBNnYDdO+-DOK_X^hhd=r@Yli*+*+8IlOdiiWWHfV#JFQs75 zxmy*xT~b?K!I&?vWJ|j$*oHR6UDWT}rL6_LD5>AKCqj`E(hG&&ZTh0ML?>%twWOY5 zi7d;U0Kl&k=E?FECjjv4gqgB@$q4}bI^kwnzTgA^ew{E*mLGNk0KZNcCCjIs0Kl&k z-q*~0!U+KUI^lu{e=E^E0PyRCv$Fh^69D*i!inu|oqsM-2H>=$PIyk1?>Yg1Une{z z%O5!bfPXbYkrUG1Oc~0Yklvt4gzlV>o>@JrqJQ8$0PyQQBtnrBQV)qx=7iKkB6R13 zEA`Nm6VltVhrZR;`R^r~YT#vwH;H!69l&3kdI#{1#5rj1n$GaN#f(ll%zXP(rro3Tas?To9fM*>dx}THz^(y z_g`693m|=ccP2uS6VmQXgfb_j-I)m8IU()N2UYZ6cn<*ldJl2iB9u8H^^geN zIU)71Q$>HrdjR0qdq{*LC!`({q09-XheYVk38{yTD*A2j0f1lcArXq4ka|djGAE=S z5}`XMq#jnQ=)K+p0KeWtA{03x_0X%3yFCK{zn&oxiky%#EK$fZ&j7%$XGnx1CtN8* znG@1H%u~*`H~X=_*WwoIU)6MvqHY$82}R2GbBQh6Rwn@%n4}}wxK3}~^%4LH>m?GQ$O);$;|lpVo&kVg&yWa3PPkHrGAE=a z_bKQ9>?Hsa)=MNpkrPshL@0AYDzQsB|EZS%;MYqeLXi_vi7g8GP0s+puV+YvA}6E_ z8+7ON9lwzR^b3z#zg@uZnpyzd3f1$bu!68hBs?VtA?HuY7i;^g5*-%6I#auVubEl^ z_%+@GbKJ6w3a)7boq6`6B746j zxf2N4iwcdD*$4c{_mJf)0ngW;=PR>({dvAJ%h!K-f8D9St~_72z7&YlZAA3Zl2leHdEdBp_x!u3m}x#b6kkjks6X`Pj{Ef<9jbo zLiWL7yuA{Qq?3_^K7u_<1kDpIqyK*{k@qoyuYqMD_L-e}%qY={1zwWydjNWv%I`al zuU?hm!cgPo!3DwaSmWtblCqZ&UY2M)wRwORv_r?8tPcBJ(YPy(=SFLsza7tnefF^FYfyWQaU#D?g zGHPF%`S^P?Q6V)5~Mc`jc zKG|5`zPG(|Qs?9w2?&$EPcE;rJXMM3<(K9CD~Tp+Q5<%h6uf7M*R+Cf7_*g_@exR1 zj?#5u#-#fj6ZO9j$6E~9^})%F6;ZcKYy-vTIGzNb7V(ILV&HL!4iTDOAdw0zl-TDm zQAjC!80r#jdeYutIxN#Ywix1ZluYr<#+Y7^uwOP+Xy29SqaDEO(Si2Y?f@n!uScN$ zuvIC6Dba!U1#=X@oajLNDRY#-!stNzvN>A7?a_f&n4<*NL+JBO0 zUV-bqfFjU7?FE1t(ShdER|2<12b#}P0SvaJRAJ1|sQ^~}UQIBakm;0_k4pj5OA;FY zdWH69MkoQe?g$wgN;t}r#tg|67Zaut5|2gugvGP~!s|)5$nvBSVp2?7o%r0w3hg(H zPy+j-1MPR+0gyzg6%qPPsbh1Pb~#Zi9qo4{+9SYV208K!_Zi`%H3#?d9(K4@Q;gSiN{%eS3#K^Ym@9wtzi$W7P*d zDDnFxG;YAMPlcqgg0NNQZ2}PMH-9rCp$oz;=cc4_zs^xFKPOQyz^kS40D2gy7ic4H_{@Sy3no_tQz?7R zM8qUB-36qGF=IY6VSE-5Zw`rIoSbgbcuR8oU`l{8Fv7g;Q`BjRzEj1#!Os4hNb(LO zZ@g=MQE?|EvH-a#|N_XQJZtJQ;IPDYc*xG={9BuW*c+y&%+&L2^u}>LDih}HCUS&MP@l1r zR127FY7_XpTY+07e%zzYGDj2Obm)%IQ_5G6FA&nHDiO+@kj?@SMoaWzSYWEDU4VB~ z<{focbabn8fKV`<5K_UOykI&Zj91ts%g`bj8FcCk11j&+VJ%TRz&?qe5YRYdWgpsw zyF$VW10RrRu3;W=^_<{>tH8Ua_5$O4M*|a0y#tu*)>7cL;?lZut<}_`h`w=+L&nPIJW6{lq|o=PbHf*^&O8X`evr}QL{h!!|bDGnf+f~#s0fjvbU>X z_#?+b$;Z^fj7j%4CbDrz(ynhQgNG#=Bf#869vd_z!)6N%8DYLA>1h1IcZTXL?+RR=XZDy~HHrRRY_wh>;^xMq(x#rL$&Z!c9 zVBETAW4ffhv91Bmm$WsO0yGnOAwlP$qoc8^);;#Q5*y_m-x+>e~DlGR%KFM>`WX7~bq8}jGSfNl-ubsj?gk&<20WW99 zbgG9y5=H=eeC+F1nHEaa7qCd;*Alc9?f_Os2ihuk0OYSEaRy!}tm> zluilXXD>fDzC!Pl=#@W}h|Yd_ew;SPOBf9})7)`qzN@!oMw+PwjFNb7XvAjM6u6h{ zZJg;9=T*wLaI0_tORPdpU?B$^Su zdXsV)>D4gS{@cLKq<4USko0$ef0FcFYVVKURExpyaHIV=ZnoRPKOylIrN8rk{4>7t zWaf8C!-M_zklZFQD+LVW9`o1yR#U%io8dszLqkX#{QPq6l|!q<`fS}F+Y z4=bEU^4CajwLbWCNK`o!)#e2)Xu6)>e*^VfB+m)) z0f`e=cu0Dq#r9wFDCDccH-lEE{$sMQ^uB~bh1#R0^mDjl!=f6Eo403!N{zde)V4@2-6G?Q0r&h0Td`5ghd)eh z{a+>#?V`GY=UXJACOiweAlRqjGezBtq0kYwgLZ|YTTf?oe=`+?)a^BO>&w9<6mF23 zVJNZ}!=T%B2_7imaig%GFS-9W1hjnkxF;bg;-8 zYIgN=5&tRzW)BUE%pN5*jTPC8y;bky(ESgp30!22hFvlLCaEFvB>dYko!i3opgrO5 zk=|&1G`207`)g54=#z%$v^G8;3Y{+w6dLEXrPEQ`71VgWb!Md2tWIS$uaKHOw(+|p z{vFRf;6c!ipdXEY(&JnjC+%r*CF^`TBHtJJfA+@z`F8zVN{Cu}L!Nr_smQ0Ee7aFC zKh!9P#=#GuwkAnjU#y}El-D>E9U$%DKH!tqR5d6TPJ}#Lm%rG0*2{AFzfS8P(fa?J z`ksBwzRCATEM6X=?^bV=`pjm*P!7*a1g$?vLP2mgyvcr{{e^9*`i&ETTuU=${>b-7 z{$=l)dd{C8Y1FHGmA#~>I=%p-Nnw(d-pZ^*L8<$4H?n4@S+lckOXJMt+@*|PYUd!hi^Va%gqf_MTSv(~-qbN92{>SUm$hE3-ZH zcs!#0)XO~C>d1cl8;aJ%zirVPC2mY1!KI0{NN`5|K4z2ZjoG9HMXilL|fbd(Oo zQ2W>rH2LyU^lcR^oJtGAcb>I+aWE?M1S(Vu0Fx#wsETmOfiej0ur%a4u;FTFf;fp{)(l=Z0+!85)h+aSn_p74`+~366;WK=h~I z*_P%g51mFch#5LT&w0$c0h~`NTngG2emiJKxEgeY*Xo#o(G}rL(Br}e$#atjGq9{y zJ(4x%_LCOgBPv#&S}|Mf3g@HZ!Wc?hp*S=?skkUSdENF`o&xJpXGP;Tl3M*( zRIg@~5$TfXnQ$#it4~O-B3jE*;cAptA00f6$Y@emxDut#vp6<+-6BycT#nK|8%4aF zCtV~_DjbQ@F9~x&+rp)k3O7@VY8;n&y-K3Ga4||x2&q^ttG6iK&&Jf{Tf9c%A+GT; zFp5PZgIG92YW{u$2I4Zbr^W1L4j(4}5Gyh244(WECSp!~i8(`kJudm;ebJwLlVFfa z`Azubo;oi-TJoF|@;j0L#ZO1b>rXijK=!mai`aw8E5E)c{hA0r=Ho;?SoxKC{dyeb zEX3&R*ZuG-%b&oHMZ1}oZ$+MShZA3(e&xATd=mdNQoMuA`{MG-ukTI2jz+t5=FfgQ zavlxfQNsN0i| zL&D2r(kX;|XRWmk?td$}I88!%w^AO*_XBC+(Z_alpz)~EP-xZ9VD8gVn;$KfaA}up z$V%&nFqnZk5R=)?zt;Li!M=Nni1r(?U;{6nBDu=7g*6Pa2A%~j#By|8xJoK3rTk7b zbG&#VPLjB^2}i=lyf${j#=PKZTh1f-LC!laYR7=|dS2Ke6)kzT^sScGlhM+OEscgt zD?*+*%s_5ZQ04?1wqH7aZV|1I@P(d3ag}2Bu|^wO77IyB(bIm8sgg} zE?75$wuMo8-T3*wRTS5=N>2#s zNLx6aQsHdS_C4T!QXwyJCxq!3o3@Y_#S_8>5={u%{S!16hYsH&Q7UAst4A?`>-<`b~CRpSHo`R>-Y`( zSL%%o{24B_wJ8$wO>mH2zParpEz?B48u^#+Tt<;&NKj?i&=?Xc4@)PJc+GA+_aOJu z&Fv<#7~sY`AQQ-DNVM1o1`EI`sM<(*jpG=v&fu=mQ#v``Oyk5~4UJ zd7U9)sV=SBF?h34T5Y_@(c!2d7=u0BA$`m}ntYrT|NKLN87KE>D*VW6@pyk4NvR?~ zKza)U+=>q0=Vdb;Ay1dDMleiLkQJRQ`ZD^D$HF;dAYCy6V zd1E8rp!$o0qy7}BJV=*UdW{F^>N#H=2+@IgqxG3@#vP;;8Xt6{XsB(wrhb{4mY1X1 zc9D&9_DsYX#O8(%{1v(5W|=1t8Y7pNz@W%NS|qK@H@X@)9j-x6%KH!)A%7^ z9N(a)fs9U<=Hr;BbTUd8i)aRNfy8tb9tB<2%MB7z;cn1n9Xc9Kw!1*KzAS7+>usTr zeJA4 zir$8s5g?Ah>E%d5*?TM}z%AVQT|& ziA1TFO-=D>ZtJW?oyAG?9iG=(YgTtR52Z#Nt}dIT?`i@a4&&9Zo}}KHs9XKY`$e*o z!&+AmJrAvpVCh?U&9`3b3!)=)Cv?_?iLlUv#qosKu@Ef^X}=m-?O!JmfSbVWpo^NZ zUgMMP56M0a(UOjghQ(!A9M)BXSs|$5JIhIKmhqCKszv9f)BTfRS3mW2bP z&$Pbr$tSIMEH!Jq8TS(QQNkVpuOdBx!s$?|0%JW#u+gQxWNnO3KnO=kd$OTz`C8;Z zAt>)`%TG1R$blXt3yHEHAALzNyYIuN41U`_wU6r)~@kmV;1hHM;;3f*Gk zUuE$wb-PS#*COVf4mWNVd3(>=<&=D+s>3nv1y&gJC!bn)CrkVF4 zPos2ENc+|Kd>+xoDD7Pat_5AxjP)AlvpdiSAzIRrCqb8so7Pp#r9{X^s;Im0KMJp^ zc2~*X2+@*Y=}Y}`Nj)1n9pORHYAwA=_I8MR!lR(o70i24g%>`H)NFen z^(LZ?-26eSquKTWq_d>5`I8@sJRi{IIh}m9&?j62syC+CS^^<(83u z%B`IKXRI?nFduvMe;eX(5Qp`X1xT=KY`g81k%tPde<%pX8>wKpkd}xeHQ2eLSF70} zj5_8_`ZDyagxYu1T@-MppAY+O;eOEG2v)Ky zJ)2q&qwU8)u3|l5U-;j)sXTkz51}^4(jeqjpgqe}c<~}jGgqUjzP4Rbx#Ubyryte7 zyai|&X>GLcseUH9(!UAh^{}ITr(5HqHC9#s&^j|wr&{0dQL0t9w%WN9#cTKzM`_U0 z{2+FXSo5A{gsOW<>;Z%c(r4M_oPUk`4{t_CFqcuTzIeBe;f&|n=_-h88p=+t-G*l5 zzFb$Yb{$8lzC~h+2p58O9T`U-DS|jwdA&knUZfzE9nQuT@-k(QLaQxU`WD~%8rr7q zQt&WzDoa+o7NW%)z;4j0^d8yAAzBo&$tvVlNOOH5ORKt`7&*s2aAJ)Tj7F!rRq2uu zI~b)^-3>}}QdV>NETX$4F0F#4FZItUcPVtLYwm5bcZNmh$hub`o+{r+DyZC;a5u@` z%TmE6o7YFOS+`>YSz5I_MTc@4RM+}xM5m*l9l_F zS;KaSm6r;yxu0qqLfWZe(*`zT`&M zGaE;RLqV&$hcR_8%?X~$FWl#-u@xE}L5-L0b6j(}q0Vptf%i3MC zR;Hpbg7rPEzw*gCcQ*2=$oo{OzLU9wp2i!G5>y+EdWnT2|H7roqLZYuX_P;Wd_J_5 z&v6o$a`}VEXSsZYnODl?7bBnLa%W~Kmp^Wl%blvFT<)|jPYLDrqLkxKb)15gjhejj zo2Q1g-?_;h@|$w~o(Mm(TweK2x%?mjE%xP=UzFE=W&O%2h)beZP}|V==G9caDN?a3 zKUng7Us%7NHS(j_7$+5d`Tmke-!>jL^7`%KQ1s>dN*?`h=XXEa%?)fFKQ`LD2V^_X zqMgjkpO-ujN#)f%Ag>?SNwM*!zC6dB`jpFE&q}#`BK*v9{hTJ1a(T{!EXUP2MtOC= zz}hCbn)<}`<9s@5Hm}lsJ7n-s6!wzhiR=2{iK_w!jwcTG^+{6UDaj|U1Dj^;9g0Fe zW$Bipa=*%x+`7GLv9dk)dtB#i z4Mc?ctABt)$e-3k7BhkBM(w{Hkz)ci|hTJ z5VeKJq&Hg|KJS9Xahg}f4Lgo^?#esDqbRMyc$4h?5G@K>x7zDzZX-&U&I0FyE^5Yl zhHP+L19wOa-)-Pt&}!OQR}D%9HTEzMzshx6o{d%`@{~AwJ>=}6Fb+kdh{n0q7=At+ zQc8YcP_jidxURqWeAo$ehQxi5aF6uDzDbSs(C7(jytHp}3LXocCE-fYwc_L{vgbq8 z7p@1b0)3F|;Sep)0!M@Pg=3^q?{VV!usJO?9;U95JsqOuP2gP6o^YP@_Tcu&hs)*% z=T`B`#s+oEhrTwAQFRoheDXB5=H_6%<4GHe3_GCk`yPAyr$FaMT=WZ(; zsh)N3X?^_KuQ#3}-@=ZKHv+sv*2ZaA(8`&TO+&@ImI=DWWn zmAd<>>ncV2E-fy%jTjuQELV-qBf6Fq1lxV-d8;e>M(Ff}yFshzc$w@@h!%zPygKju zh)zc7(kWm)=%Qw<*EsJlki8P3o{roMTAlaSRm{an$VQe+ukB`DN~(7EAzF*x_XJB{ z>X(;b3T#qI78*IF$4-a5Sl)iAEQXkzLJFeL54gR~xUc zS6WOni-LEXyoV91ocuhAtAwCew9NIZ8&NwCb8s zJw+;eZ~1QIb8jy{$RLz*xg%Hh?((~ha`_QjE9LSFk%PT)9mp_SivRq!ZLpkbkTt=S$v4L&;f{}#}NIc{{{{wtR zXBR#eerBF*b?k!`KjjBYo`==D@JEgOQ+VY!<#L9K`fTLM>-VjO-xinS7^IAgykGM8 zy$f%S+l%9*UFTG(FR#Xl`o`dXqa1T_(B;^Gvs36o4GC+`E}-W~1&t#Wa=BMEj!|9> z2~)L1hIzS*#GpWp$6opm)#Y3Umb7FPsCFAL@QqV#j5@1PJ+{MFg7)qK>0WOaYA{$( zT!=Kxo}z>VsrKzX)RXK=(4LSNmiBYb8m}UrM1x}-H0qq3!g|pDE|6<-NBj4qsgB?t zd2r*gFYK?)0>*uCdS|PB!N?^u*WRkaaomG2E}ohExDL~X&+w_0Bte&Xw{@p|Y~J5H-@gebPA zYBXljWwJN3RM04~=QWPAyr#LnkfoJnGzXJx*?8=b8dqcIbWXt~!{mT9`ge$I2C*8n z8ANA8t1VdiQvaN2^PyACgblKr!=fW(kA`SbMQJ2s1Cx3W~Q$wu$%x*Z$H z(yFerJIB7dDnCTz#f=sOOJC~2V|1R88nKu}Z+}$l7RR*oB(xS)9*@#RLFLBO*-LgR zOG}fD{#iFIF9|x-s5?h?u*Q^j`-rZD){-Z|PSR3(j;yCqBSzP&Q?uI4xCh=P(Zff8 z=NgR)xf84g{3)gmMQOY#>!s`~B*L-R!w;u7?BNdd*wZmwO@Y2oHkxgx!=1dP#3;XTPkoXHx1o-%09b z;$ryyfnCUOR_EyimfRWfxWPJk$~p_B1LM%P4Ui z<#miUSWfy?Qy*9-oBCk9>Osfq*P?oL)t#ccp~1M$?+;7eu*}OLl9|R_RoSjK&XhA` zZ-uBQSo+e<^9I6;B*sK|5_Fl@IBxLzfJBgl=RvD&fc7^-w73OaNUE8^=1b5-<4W!J z>Sl=IQ>FKV_5>Sv+owW&mer4LnSY+eyvAWGX}Tlqki4P(buK#c)ULL&2Z@=Z>~kH$ zo?G)idT|`7N|zm!+%i-hKZxi$3C{(G?1cxbhY`6?U?UJC9E!hY!V1a*jW@nDne zr4TI(S=ue7Gl<-{utppOx=H)M>7;@t8dvW#WY1=4y@gq>XeLF~0JyHad>ue7jwh6kabh+m?-W^Ag~t1| zt0Rm8iE%v(0WuL(yKxxo=TU)Ml~<=2nlA}!f0gqQc~qAg18oy?WZf) z1D>P3YWvxztZWbEm0n|eh&aBQ>8186+!J2zI&+tm-o$Z;*9#=RIC~Mel2m6$=`+$puYlstULYgeHnOWJJq?^m>Qugvw4O?BLw_WK+&1)n#~x#b z{(jO2K#oG&QMeQlZP#&bdn(*YX$kTeWITeqEKHL2v^E&9cedr8EDqn;H^2G4t~F%0 zNL=RYQRz7nIdP9B zbttYRbtsNRczX`TYEp;dMpD5s;F>M8BBniu;!slKe=@1@-$-iw&nGqhx04$GqY>$z z@%MYhIBERvC9UJ%GyWGN(mmsUHL3IbW>SaZPEw=i;X-+uL}-lYwWOQG?tFxC(JfBw6C@mVALlKWf<8e2s7mR!1_o9C1613>)mnT}av$ECQXlmKPn+yBPXMpQrf7t;! z8%CG4|2XMB?B^U_Hik!|sbvF~tuEKCE*q`g2+^`}xfb1CHUjC(GR?=KFPkK;K=t(M z8jOc2eF8j7s-4&lv<^+T4o%n4WIPN*9FpfGo+#Q~ z_uWvtdojAOWN*g8!zH_LIjPQ$hc8Pyn**{`x4Klfx>UDXJ&E(t#^q==E|8C+sTHGT z8(gvu0CpYfer9jaU2i#36q+5%^;Hr3t2yDdUSkWyfE7b(g zA&lJsoHj`DFOD@{&y%Lewp8|*mm5PF$ z9^nHeZ^aHHyT54nbAJ#Q(Tv1G9f{>>y5t1VxHG{1%f&0Cv?!a2v!Z!X^+a`ea6oW% z!Ck@CMJx3xv-lLzWW-}ZFn(#<@O}G>a7J{wTpTo9qANGbPR2ARb8CiE5p-V8kuvUG z!Ps*#8X>}?5%;dJH)va!Cj9`PJA3~f(tAJrN$dN*`OR;B^_^ds`r&Ph4v_vp6gNt~ z%3Z$&2T9+@_Pta={t-o!431|u?Op(Kx#|jcQ!3mevGrNsmgLATI;x)dQ#3g9r>5Th zh@JDhl0TYXg5a0beu4jcf)G!))f^*zexSV`b(*T{_Gnw3y`(?%D!pHrN~L2c(^&oyFTOko^iKG{2Yzo^5bX! z*7>HtXW&RouH(XV(Dos~b%G{^Q$ddlXGl&A@nVSEmw}wB?J_67yNG(akH>Us?**ok zI(wbBv|VN;OKh2x+;BPz@23K@Ee>a4PQCcn&o~o>OS0gc`%E=w;#s!S=(CmR{r4IZ zsOJRA*%7-A$9&>j&kpLAS@A=!8f_*JDrG|a;Hy+9cP``v=s5vy#i;j$oB;Fn1nAWh zpjS_TrFsH%>Iu-RCqTyu@Qmb-{S)-VF>vz^?OIZY)^S8ZxJq)A#hWP>a+G^zl)rss z9Ni~Tw({P{~VZ(0qz^jyCi%Nc7yiuFOE%K2kYuU5*wbuqFO|k@#1q#sV*Tn65aX*>~rb<60MqEbb-XVP`yV$hCL^kGT`E);gi?M7Y?JHp|R z_Jw}Xj(hXXlnOUe>eBWk=_s>xZ_L<^Fcq{fxajTSKZ$&e)oT`hw2?1Y)>7`Z^&W{4 zb+UU=g(jBDzZUR)}6&zUy8cFWPEmpDWQWqK9FiEsRANmd1g@L3@4RWYD(Y z;_e0$xDvGILa>w4(vCCAne94JWOoKK&Wa)uPm{`HAi3N3@)$@?V^z8QP~`LDX!1YV zD3>2=l*`XG%H_LwTI_4S9O*~Ci#g;6kD2u2jj)sD^2!g&Yd^Al$PdbEKeBwtj~5+60+V!No6JjHPw;nfCw zChsSow@Vb*8I%B2Wu?cJpmebk=v2oQ6?Sr^x!rLdJlM#^b&!(9>JQoVGn~~hFz@CC%wgbGBd*- z)QqEC^pKW>xp4GE?dXZx(G#_!Cukv# z8@%2m*=I35=pDe!kucTM)Wzs%&j%FOl4|vF(y+tJxj}XRC6g0Gcg~AA`(*xcQ}B$8-c}lBj)m)OTg>5V>u(NM+bHBdq+0#X(BgH{ zYpp*kWaA&&fjcCmf=%;&g774zg6$i;;s?rla5_BrP;hzXdZjb2vY61BTq{5HagISj zfrjJQ5(hAwDPD5kJax}$9~!k=Yjk(nDgOFLWa6`ANqjA?zq@e8PDUm%WHO_tKHSm>}pnX zY{QGyvao1cn-mq(WlGu1qbw2}U~6r*{+(_4wFqq2b2DSy9rzHRvP&oWI`JR^(ie_| zxh4I{{`8HF*0`1m&w?%q`@??w7_dsRmuuj~6kh^tntCM;(Bi=iZC#FLmxSj*KNMP6 zj@wAdNVK*nOa%Q<*iU+!?-l>Vd%x29(<~|Gr%9u%F@JjM8{Dv(J3#W=$Dep_3qLrd zVa{GMOeNwhYuAuuzdtO&X2RO*Mup$y~^ngl^Ed=&vR2ZRre& zwY=`>iMpo?bx#-UX%6dxkiNI|U8gxciti4#&fgAkyB^`{vBe0dV(z8e!l5`pdxwG9 zpz*eX%Qs;tv%<~xl`IupYbf0X9;H-pscFML+Ve%*OF%!u+bgBbQ`s?Di{g2se>v$@U?-`Q{8G&9c_;bZ zq(bgjm+LXF+MJ{6piPZ#g{7Xi0#}l1|5?z*Ei7qRr^K5iR#NX^?*#1$*;c1+t6FLg zV&+!hc8hP1?W08=YTkeg56ZLuTH4mx7t8 zKhGP$Y91r~Xr=vCYguJbA@W0Y)ZZdaXPvLA`<-i9BRjBIcc9uLdm%c425;&LUIF|W zecquh%7bj_u@y$6!UuvC_%ELMN$66g5;QBFry@ZV@`kkfSkhHQ_oDR6!jqsw9-cw8 zhiSaU?C3 zF}&3@+(2|QN*9G4l3zGuc;mx{&!T8q7@?v?zBgYy7(?d$+-t4>q}mqw%3&58jL(RPKAl z;+)iX8yS=qQ-f@2%!%h(G5FMl?Y>FZhR*58mI{saw1_TX<07eXJ#m417NY9hyiWG_ zwR%|L_q}@DpwfeA_(S19bgkY1Aeso#hr*$t)rHdrcSw6!7hFB$w@GYi?g00bYPJ;> ztMmNHKvXJPJeDfsz`mrmcqwU#+$}1Ogs5jvXM=tqTp+zYSS!ELSQL!l*-%>(953$y znTq@#BcD9XliR(|3*yqG1{`qDZa*(4?~<4RLZ9S6YMJ5x$b`KuXnqFiMric}oBjTw zW@p~}b*@xpk~L<6C(Nm+xhz<7aGLl7lC`@-!s6^vw9iE4>O;6QWbcJ&$=2*CkAO-A zLuV6Qz-wQsbH`Fm@|jjaGlQ?i7E^<4)0_eNuFsCkC^yKU(y7xFdJgmd`NBD?5#cKL?Oom)oUc zf*pLRjkHumiduDeZ&ZAg--~=cAd~M#KEEa)e;D~JhgOGg=@uX5l^uMPXT9uWsk9$5 zOJeAKa$p8OQ{ryGtbR%l=r;*RO zDEHQ@%w@SZT_x)BpKg@P=Nsj6pZt{i^1Gbnr9S4XBmKy^Jmd#+T|eFmJ6SHT{Ghz{ zBg=>UpuF}Y%ZL1+ymA6kW~yzf*PMm=Rmw$mcu1w%g^{3F0DFj(vN+~=-9lU*v=o(+ zAE?E1P8)cu^%v@gz1hNX;UKM4W%l@FQ()#4sqvvbvuBz*W;TX(%${xPn6W<%J7)8) z;CT2RJw5&ac$oAe9rh8xw|S&nKPTfAN;c_$igHki>F{=vaF-wKJj+oZvh{7dw%(!NjTK~wOI%qR|58slX4 zH3gGo_BREXj^hlkw#7RQLPnrxFnxH8RIoudSi+N(3btzGL_>zMa3pBYzF&{X_3Fq~ zn-C*#F`AthE|cEke2=#ju8~PUVm9tXi}SaE$4PB`Z?rORzowGf_MN1*eJ$FauiKu- zY#b^+W*e;Uj_uvhT=EQiOj2A_??KX)c?Y%%!05!1qy7L8tjQ?yqf2o`!r;I2!9jN9dF6*GbUx zfE`PHI`nstq&wBV(Yuelsp&m}j)&Eru$L5%P9^(79-pB*5VR*8CcVv8|0mu%!*ksq z-Zno&^6AH)p7Qyfxml8rI(*J6KQg3Y?h1)%XH4%WHHLe`|K21plT?@`ga zgZ8>WKdCX;O6r5;3`cJVdOM|MNQ^=DYF^NzH|YV7W~IkStd}}>FR9LD8}qiIaTH1$ zhTleRrMNUQ%3L0cY26lbosJ*MI+9XhK4`VMS>Pa{cTEri7FndY0u9lVQ=_Xkd9HHXN~6>8taD0OHUl0^s}T! z|6Sq-i&fE5bUC!DV9$_!5~Agzb&l-q5LKa3q=&w7VUOh(LuEyKw~{suTn|wdZnbto zRJDAT>|jAF6&0!3xKUHI9(}FuiyZ5HA*yUCdPMSDG{1s>^6XXofb>(c`Cal~CEU-* z?Tz|X{~jVb5Tfd~_%WjK5LK(XtsDwbwb&|pA$-oPW1&?=RM9la@adlXV5lq{2DXxx zDC{Te^U20NzrH;V(FgU^tX$Rn3w|kjA#AIajg{KQN@?^YrE8?`W6AQ9ko;2zUjIEW z`-(S6Ul=Yr6B=Jny&qPw*z&wOPimZ>XUOW0U%ApSPY8>7#pg(07%uuoXmE8=S#en4_`F5vK)rBfCkD z(tN&axZwMmdV^h^@q<`Uzm$>R#;A7Bx^*?&T5-#k9M^ z5f}--SL{Nb<}1P>QhW(Z;`xSl-L)0FcA7pRJp<%bH*QV5<|DOhSCZCUTd`~X=+BB> z%LimDewOcXO6_HS=xxPspZrkB|(f9bLA5W7y z><6OnZLcr0NsY*Q(k;LX2z&htz^$aliEt=2PA*tbLo=VW4o%z8%tdJ0j{2#jM(JA8 zo4~E44*)hY8XE`pCY=B>jBUfXmeO@#BdL@1QqnrOZG(F(!q_&rKGejn!F`zY5s-0i z8|VCHTf2^P+sS@A;#_@jV+;p9S9w29m?Sm7apk;g-1wQjL}J0HN2RxmY;Bc@U3!5o*RCba&6wi}76cZ8uoQG!y>QEewNXIvD*OEFE zJ4pq{fIYY{8ZqrT6f;SU|EZ+L|7=p@e=(`?zn9eb4?eVD{O?B4tB)ZQk~;o9<9{h4 z-826AY2u#qd?%$2g`X&HTvxq6IZg77cdsGxe7L!|3w=l;YS)S7t%z{^Ceibx&gI+# zEgGuXh|i+&d60CP?&ngpSWl@%yOc}Oq8{ftSZze+Y4Jw1y1WaFM^nq5c%p?YNne&}Hx7NdK;rpqJ@dM| zNcM&=-AQ17Qa!woR1dEvHE`a^W5KC87jvxZB)pl_nU~wAt}}0M^d|n@-La(3ybDP$ z16PyU^KrV2U3)&2)OhD@OSccblTs&PhNf$1PDebt&b%C(u48jQrFE3Lb(FgGFjcp+ zeS(m~v}8P{qmN4l;ZjnAa3}h>WFPm1-%E!8w+vjw?ZUqBaLF#@FfG*%EY%Jy)eck} z-gR1aS39^+Y8ZMLFbdFvz(n+Fu@9UHx**tfCbi%MLH8E$AgPePEDD1Q0}EV$rk zvtD=>Tf|^G;;qKhzKL~|G4r&>pWA># z$hlcg>F@4KL7x2kNZ;veR_aWWzU|kn`Y7aF=?cyl!v@?8+7<4nbe>bCA7@SbE|3?m z_8}&QlZk%RCs4mWf!g&6)b|9s8@k7Z`=s(UD^IBLm_EmaLqX%aRi5kkB&-KLE^LyV z7~+)>x32*?8QW#neRmP{?45||)Sd(mBz1l|GikfbO8QtPrJswW@IfjtmEv#~=G5ys z^>#^IMV(?ZB&gsNYkX73tkY%a8&~y2Y5WtnUYRK0{(D7bf_$5AT$Q=;t-f*Pw8**8 zb1vMC3D6UAF3i_+p;ym^UOg9<>bcOV=R&WZ3mxaeNDSQk7;q%1qkJZ*qwJ9K@JzTt za=^vgDHd|TtNqQlkBkHTJnHs@y$oJsAj}?&@$5PF$CB1#zf_NX=N^UkNsa1^bsS!D zawY25+kyTr(kVundE@2pTv9K8x%l@5F93c7*l+I0?~vFZ3VB_Kebrd38XaLKXlz$c zC*1<_!m%hkBo&LUHeL%$-r01JRPypeB!7`|(g#5GlHPehxE_;=ZuFFw3#7raTSV@3 z1`BEt-9z*+`ciG~XK`e(5*97@I)fFlh{}X7U$t^-?m3FI}iFL>Q7TJl*E285GAJ8tT?QY!4E)aCJ6(s8Ex1c{*( zTrG=5FTeARe7OXdaxcPeFiPI@qu&?@7bs^a9+in&RLdo^NpJB%rT8%yGb;Ko#wSBUraCm!2$8qF(;=$-+edabL_J=s zL#^VA{7~f67x{dnTz;}qE?;Yu%g;2*<*sDKzI-F{!+qU{>?nyC3tiGk>*G&Hw{5^m zjR$cSu7;?68nB5*zqNEML_HO)?|6u6bMY*d6c_&*H>vy4I!JocXQ5x%mL7_V?P8DC zbZH}{yvCu@9H}|_7U)pvzTB!WJ`0>g=J@#&uI0u!^)gRU922}ABM}Y3C}fyqR%nE& zPj(QdQ_#~H# z0$$^o;5EClAZ(GSb_KW|w7SVLt|vpZSeI5Olcl=BCf{MJO`itADUQM~6SI9qGtrg^3e~?5y z!3fhWVUv`Rl%2~0;e1sfyF{V}uW{_>m&V_2P)KXlkHKM6=FL%~Tuk0T3IQH>+kc3-;!HL*f@odTkeS9glI#%W&T|p@F*O-%z&jG`QF&q=8TX}L_R;6DBs^GN4+{O!)(U~h&M=b z(H*M~Sw;qRm6u9~AiE@8V@4YD7hJ>CnhOX#!V}V4t+#(_WRvZ^nXGvN z(6%LSeW*xkoVj=Go+QMDZ8?8^)w6{dx} znV1)Jr`b>aaYpdmO1KpCxNtq_!X&2j2Zc+(wV=lZ>>%w3+15g7ps|&64jm!wY0by~ z+LO;kKF948hE9{Bd|`NgWSmy_Q9MDSGeQP*6&rEriOn}VbsO0rC`CeaCU(;aP|K}Rm05B~o4Ezr76m#5LSji$_4T_C;I zT73jup%^OI>6m4Ifmvq8s+6G>$2_kaBnC~;5u&G&CqWm4XC#|DOx@L}zaVS{Z42i} zG0P-+&ny$J2W{U3>1if}Hax~4x~QK>sm;&kf+r;-Xg zK|4Y=J1;oc=$2+1XQ?s$lcYT@CKmsvQEu~*XFAF^N`8g^0|_@UrMv_w@|5e~1g({F z`EI0BbQ z%)?@0u#Q{}mlrhlIO!-S@kT5u3!A|Cq(0wxn)Dfv&jl82cZP(qbzm#$B|s05M(e!j zfQ~aOE&;nqg>1Dg6`{R&R5+}w5;8Ifiib&}QFrIWT z;1ogX%$Q9&2dpK%1YApMTy7=33#79>JDZguaI4b?GTxm!-W?stR;$k{&S3jw*l*YIj{B0auphs!<~hfjWZ)hoox=WfG}X4L zt)xcleo~vd938ASQZ}^~O)c5ft)#bs`$>0!Q(-^;qxh4g_G&VWF4^i_(qlk&aH;O# zQr*GoDZm^?FOddk%;hi|r-|J`>XKj|peKRsO8lqJdm)YgtLfOHZ~!=*R7eLp!r(M{ z0-a!aK$kY-ILd2Actx=5#Ig?d$`vFIGpE#Jpb__@;bFTEY>-?OL`U9jmUxMTIl(FZ z2KUpk70b>o+PU3OSrHm%V|IC^?s9y5BD>svNY9^;Y|$BR_vNBFsLJ5 zNU?A!Xj{mqh%18gKaA8T!s0Dt4@q=KFqEO<^F!BDqaqN|q#9#dW zIDU!k76o23-wdnUo{dC8=LF|3SK)b}pHi2Z&7_Zj$3f$N>KR`iogDzyg3g!7V$8r^ zOsQZ*k(L0~?%beYCkuu9q(*SeKF(4j+={^VjPW5-Ly@vLrVv})2*2l4pM zNmLeG?#kXlem9GRM~x!+X!J0CNa8TnQvjdrzVJs#?m>Yl{*TpL!VsMsjMs@LJ}CK`^Kwfrd|xo5=- zPl>X*w$0`G6WiVCFu!Cc(%W`D3EEmZp9;d|pgrLMX-{i((nU|cOY(E%#&UYrx&4Huo%P3H4rD z-$(LGDEv0=KYuTF0vVv{qI?hSM}nE+N_p}4gwNp-YVuw{IM<5GTve;@Af`Y4 zQtE8J9~I^W&A-{&;M)~dC)W^N4~?Fn##?B_chQO!bZZL7x4q#!*iuNz8R&jr6Lk-E^pQgi7UwE7tx{ ziML~}e`hO|O2dj4ye{C&VPG}sNx(Ldo&h$JZUU~XNY4Wol3oO~jFi_nn#+EX9f2Gp zjq>#7z`yHKWg}XzC7QZCB)LLPj37Yy2p{`W^ zzZInU43coC5hVG&ED|0!isWNVZbB=Jv0lC^v}w4pXFGA4id7p#S^mG0coHCJmz`B@ zzB6RLF)S!n6G0>DH7ANqmx&^(!){PD7HBCXj>Eh@XDM{WacU04jXhglT}ybl2h`Xu zsa$yV_emo!rwL|v*|V7&A(a|(eW^9f<)vuF+8&2UM@ZaZ3v;CSzVvt4v-Pn=l?nPZ zLxRo$$C7&SyO|VoaWv1^^GGsOy*bPr4O2Z$d9md>Qk&`xs>gQRI^_$j_QY#=$rrs- z5ZfxdG5ICZU=r=6S}B@_A86!f;IoZ9wc^m^28j#2;374&QOmB(>(MF+HM=quU74@D z;?TxnpYM>INp?8n*E4oqQgeb`r9zrtwAN(UTokNWCX?I^3HNM*hDuoEo;VZ@T8}rj z(`HwjcS-EZgz>Pkr1vvHyLvyLRM0&(9#I;VVg6{n+^OIuj69n# zb2mveDBKHLU6ya)!|iZq-uR3}>AWyT8tliUd$YuT&nC5>XOeCJmy+7X?WCpm56M0v z)jKb98KUa)av$x-q@hjLK3v*Q8WLVW;02jU+wfj*3=vbIw0jn%OQig9tuuVC?J7C< z0}Z8ZlJ2B68tv#~X@hK^4{)jsr#ty7fPYNN$Dvi%TM zH*xc12lKd8RCF=4spcTvcAw1r%QRt(KV#G@^223-`46io={Qz{rVq{5Yy z3cD#4Mk6$ff}zxPU@oOXMs%f)=!y}&oeDw*ccl*Q3UP{KAFt~q76AjB5$)|j_eCFj z#%_O719l|o9MDbb`L>zVfVmiB%qV4Odd6clded72&L%Yo7n9oaous#bdr2Pv&y%ul z4Zg9{b6QPB$KoG#o1Ba4{7O!mXqR;Z9P6F!){>y^JHyFj)BvS{HtX#K~t+ zt|#3AZY6yV{Ey#@NsUByzhn3JML#+RfP+bmL=Ic09=47ir<sb4%=I)UOZ$mwUjz#!;f@c65 zsZ}6HqUWM~E~LGufZ^w?s%Ph-gWv$rJz+BFqO)@|=zIw`3P$^SN`;JeuY|baB!%}w zuO~bqH9}@~Bw`#tu(>a383o4LL6|2s>JYCue2Y-c#`vsK;LWvP!1XDsJQvgEcTRVZ z-fd{fACuVhdzOq4$6`P}MWU!aUAmq%E}})NEU4x;Xx0(CIVd-O3x2zimp_R7*HfP; z+$0rya_4NZSEA~Dv-WT@4sARd*tNTI&&5(t{v`4rMLoH*gx)wia$S$#YC1%=v@Sm~ z$lIFy7>Qa=q|<|F9oTSAH<^ zsb7|YVsDPJ`G&qz^Kv6!rc<$B!q-RV6p0CR8rVo`P1ldcw7N*l98*_?Qdt})p(f0d zUUf4u5h@*_QfX}O$B-WkmFjv!Zt%s1_B8YmsTh_YCefzgx?hUqYgr_mY7{}^*vIP; zl8=3T#3P?0z18~oH(ygQPo_^Q3dLs0Qxu1W(v6;=4Lq{8HK3&;%LIZr_Va2-U;fsC zVX-dtR)K+u(g~yp<2b~tZM`@OlgLmLG*BV}jbnn>X;SG$AD(&{2C{M3t0N>ITbJ-0 zCI43IlMIg;9W4rdcpAzIWaH4#42jiC7=%aAf|GWg=koGC3C{%$QGwSuW_eYE(k{?X z%4-}(!qOKbVK=EE{IQ@tVIMO$KU^=%)vO9C<&~+6@P{PLicf>Tzg?;|o13KUJc(O4 ztEtkso72JUQO{C}`0EMdBp$!~maB(6D^}BF24y?Ug=+`cO)BJ0d`ZYU4n-WByq+c1 zPfX0&F0tS>jtO4(lMo3R+xRuT8zGJ6?k43mjsv{DFnT;&8Qs=&`cRqQ9f+DCLd3U< zqe?LSM zL3WKq0k3gP@Op^EcnOC|5qoVsOF6IA(NNW~vIfXclCUCNZWPI{WRYO=r4}@feY|Se z|C%uLU4_UN1B246l3hPaW)Ek%%ZM%*r;?X{mGo9?J(rbpWG*xmw42_f0kU!EP0q%i zHnUstwFJ%4!(!+&xI6lrJkNY@yVz=s^+A;N@7sMP!60vv%16B~!8KL#SK;X*ALZtc zY#gh+TKC1XU=kS)3LB(X#o4k~L~GwXT*W{mTt-~Y(sjGHQSyzhPa{+B#jYFbQdfR2^7&C>`Ta(@{7kHmSuQ^t`TWE@ z#no{JW?R~rMMo|k3;uq5THd-%e;oQ963>>brgG(pLUNJJE!Ha`+m{h*` zAfJu=a6Ghnnl$({l%aW}wYfjOJ+K?{wvaBY!s5_DMa>9VV3f*;$#u2NSowe3D3>3> zMk$v&0;N91)zO97mNvYK$we>7zF}MHHvO4KS9w!r1hTgaH=u_oX2=A4~Pb%Xhx0jJW{^^K4&1mH} zSL9C`<Rw6(t2$+hiAG!2KRhTF=SXx>12+d^ zF@5L>8q`=ZjP?UWj|O7#DXFn$UM6cta7+VgLwT)^W3Y0L$af;2tDgK;-_2sTgrCjcLUCQO>8|755j!l?-I|ph;xuH2a-J1ithvVfO8Y21N#ePu zut6GWZT!nUjSu1VuOhsb1^;Nz_72SUs8O1OBCL)BFoGs*1YOd{n@NS8pz#pjkztc& zU~(ju$PVl;)%L49%rO)vqE1(^bB$k!GkZEq>n6LUNu#nu>7CT5+w9u3?MB?H_Pcfa zT@^g+)N1tpRnhcp*dTE?ac+mJK;rpSD2UTVdXXy+um(=;V zl~g!KYShuT$4SI%Bp;;lo237IdfS{nHcqADpWQ8HBm8M2Ui-Y3Q$fBO`8?I+ry@Um zK}8h5%s^9np|d3ZC5zH>DE285paDMhRZ2v~`XNq{nA^g^pld=_>ciqFivEkO4c>Zg zXcrYxwPJS~&R`q>(pYs5iDXD~A~cr-D|!3Q$N0D9*2c&zkVdL=L=X0pz7K!=&DgDY z{iE*akyghZ7*P`5Cgtr+DOLJe5(>f?>02punhKqvCf-a7f(E~ph5yHzpiOq>(Ti96 zpu$KfbcEFHHg$(Pv@dkq!skiZA(`=R%x-e6cS6(=if(7S*6pa{Q3l}6*3zdVpN=>d zPL@4pd!LTTf3T6)f+JkY<$t7+m+MU_hsNru(u#oCU%Z>Gjrctcial z_%E#$8(nO8cGFYgmq}?uww?vTPS6G6ACXc=rW1{AU2U&ZTj*#Z73WLC#Zsg0M`(Sw z?P%r@3BQGzpbNqgQo1M8pGFf%2Gu%N`zaFJ5usG;#FNOZRyjL?m7fbs$BzM7dYoEu z{8&}GQkSlj(x0hH+jVKR|8R~vww(9EkC9$)eRXUfl@5?xQ-D8CdcAeVb2g5nypBh4 z)yxv2y!Gy`L;oR(*!*s#She^s5bdGv8?DcLb6YYN#_R3HJ1Dq$rn>MmLFa{^BV}kI zan!mUbq(Sht>3u$iA3!;TEBGj6R33f-ncw_2hM$0ms; zg!4gHh2J7&YqGze1-!;lSL;~qH%WZtQ7F|q+jX@QQHPgO&8vX*&XKrn5Y)zrx>7Yz zA5-#cQ956jRx^!)!7|e}KGu3UMwYPSYbp%K$P%3rT|ID0I1n_paT;#iZo4E+hG<@; zEFE&nMT`y!-%onksqd&Tk`{zLue6{OG$HIG@r3O&+Y)<`?aA^2+7>=v6+o(^;fSXG z6+CTNu>D~R_P*hRaUE7b5SQP7y=XOj_>S>@*~y>5ho2?kgW%~n>}0LbX)4sys8;AU z73xzBlg*hrRW%{|NfK=fU#tpbnx%l(>Tpm8v$+`Q#GWg4=PN}>>UM>q+YQ~H4kKNm zG}zs)8|)&F<0pAd-F98t9ux*>+jB?zxf~zZ77vH~{cZ85NVr@qsE#C#v)|jAG0{ok z8zk=3TR*fd`>Uik{f(v{s`Rbo_@OVD7BgRJ9WE_?CB_X^pZXfhwM z;J)A$v~eA-t97h>DHP*zf3eVsA1TOc)fD)<=>3b(Z43VwiOV9dd0YqnI}&XQKNxMU zWLds8mKbB3uFC!xiE4tr4WBFs24{4~)AAIFz6hsD>UJ7G+O>eJI5< z>o%%YowRONTNH|)i`%uIi~4EDxY%C(L{cm+Ru-d(k~o@%+S^w6bEM&379DPNi$dc) zz`At4F0Fj7OBd?Wp+M}RJpwFDzSJ~=xF&E;H5KaBNQDs+cX`5OWdGS~!>ds?u~;nd z2agXA9M)-suC-FXeYjT}CPct^<`xYPbtQJ}w z4R5TM-pGEG?1oL~ z+`FVk1Zz=sFNVTkeeLXn>bTwLY|C_&IVZSaWC5f)tU}P5HM>!BE(?TGb9gdl%~;cI ziD1+X#ttkk^sWsopa83mEbY{#RflHLafzaWutDNCeMYw>o0%Dl-RRlOjBiV}GPAe( ztpV!n+dhZ%e3neaqvVU3nT&UpuajxGWy429)De!6-e`SwB)^lKnbG*vMmIBK+me1} z#L+yi-*D<89qf(N~IAzY@8O$6=pRtNMpf_AEvACJsr8J{U;i zGLoX@B3iGs`bBgZa+Sm^EFy6{L~-u?7&K?D?B}w8*XsCw7}bTnB){MHNt}%4tmCPV zq}t~2A(LDi4pTT&DeyiH-1E6oFq16~c{hfb(^9ZiR|c1w;(>2+lDA1+aK-v;CHj%q z;tAon5Um>gZ^KxdgrYFK(5Hp2GvNnG{sT#N zmJ{1%Tzwp*5SV$lsR6GJtr%3sgXOsxWAKU@R)AulvC{rks{IcnM1qe%_&T-lMN;-g z_Ki290F^lEY8|WjOqwlGtvEl>Yt@Qf6@6Qh+f||1XM0cXH?u&nDI2cW;o8VzZDgTo zWU*mnp=o4syLj>?Okc=WgufqjLGbaHch;|Sl91RE{ygv>k=|(i%4^#zkPlNXd{pF; zk2CYew&WWmDqjRHCl&q%iS_l9ZON6$U{rFIgud{%QvUk37%VCXfmk|0~yp6;b&56Yz-?42F-{;?*qF@h5w!8%JIgnfACL#`rYk4c=1m7 z*8VZzi%IRouO%&xJfL-(-P3yGCN;Nh_kV8W<;IF~EpN-USoGyT-zYC}D*C0JdRG3v zPMvRH`oAX8Vc~BEofrO_pdI0Fk%pI&x?0C-S4ln#7FB+|RX+=^Rl5zFV-piTC89D~jJg zWnGx4b|<4|C;eI>rPc96Fghf7Ny=Wx2Db`=?GJYkK`U!^nl(Fd6;qu>T%B^HZnvr1 zZRmE3o_+tAgh#?(B4xv}znlev(`neFx@M@;iE;je3Ut@-t6WnL)Fcf*Kn zHr~cB)r`4{XGwA~RjW&~51R+?8w!o3?C)}VWj|z2I+iaC#9_63>fRClCK|Lalxm&r zx>|J=vD%N5*!>7Dl1x*fRO>dXtu$N9E6$>DEvg+CO0~sCwd2idzZR`634e`bhnBWw zKORPwgkoeVj6BE!;de<{L-u-vU`hBKDGOx(aTW-MDGQ1d9}imQvi+kN`Ew+w@L|x7 ztEJ|VYWnRk))Tbdn5?da>!G+*>b%~X*{(I0N}IohR$jTGrBsaDc3HnxQ z)qXDOr{O9^#gSvk+9Xc=BKk{Yb-D2q2^M)9gO+e7=yBmb>HlW$ZNsa&%60#l5NX7S zDMpMKX^N3zO({i6Q>3s;BSji1(iGEV0co02N-1KCNGYX}Mnpu+My!Zzh-|D_k)7fZCdsd6k;hY@F;m4qt6XRGF{47D+< znaZyWSc{UzZc=%ah}l=IhCT~a3Q3n$Q<7v8fw3FN??(W`L1J3$z3dWYeePJN?5D;C zb^PYsRrrW5(LeUqNho1An(*YDvu%**1>$>t@&xPTkg}Z6eSnlDPQ~83E{q-RQW;|s zTVrp%ME7`@*Gaft+jxl~E>vPz?5!uA*d^&VDE*^=HLRNSwQgK`}dXVv5~a!-r9s$?bd<3t~nP<7mBmCu#%!M~3-PSGxaylA3C zh&FCz5^Z9LwuzLsg3fGSKFdx;ez#!W_Zr^jxS02;N?(t?aqDe&Ue&?1-hD~y<(lmE zQr7C07d@nu8{;${l29g{qtC_p%kLWRA+?z6k=!m`rE_UaRvNvq$crXR^ahNN3v=XY za^Vt6FAfhCPAb@xRIn*%)k56?z0?Dt4#uma$lTalCowPf)=R93z4s-(AOH7oX`Fv9 zQH_@4fSbKa-z9o~9o_|T^hpwnVsE{KikKHoQlcs%Ue!W znJb`Qk0WG5fsD3@Vdi=(*F}>tRwSyZ)LpyZuXcCC^ZxKJH4I9K?s_9vge1=7B+lf+ zME{Sttl8HPZ-_^C?n8ETmr`;Cxjz{;lS93BQJ#*tO!caKewU##TB&ylne97(gG)dGcTJ)q=qsuSpP826e9F2qdq#`md4_PtfxC{H}+$wcxZ$cr9O@dn1t_<)3Zp;Ppk zCs!ux)B_mCPTPw?fNMx0XgySOk>g4TItcB!Jg6H*aSfcasv}6HG!f@R+v1>H@=8-z zcUXBPdIPtR%UA6b{N|jqZIF;ww#hOsD`$|kiDg$NiDhLIoPsG{&?>Ry98ID9fX>pN zjLLLrP;?N`bwC%ybvOm6D8>#JJ0;N{u)s^`xD#KrkjK?6chc3Dpdo;kmyni6Y@S5K zu83b>S|1YMC3@Y;{=GrmT#9~qb1BhofVP(?0X)u75MSXij!bSjA33{}-{l zV@^9r^Z>NOZ1dztt{s%3%Xi61d*hL|j*s)>W@ zC2E0dUp%qv&Tj^o1%mm^wOIv?lhB~br*4uJF1QMzq&S)5H|JzQpGpjK-kb`Li`yVk z9cyz#L{?pZmfOKdr_Lqaiy#G?-1@(kmzf60O=3>$ZIW0Mdz-f+b~-OHW2ZQR<}TtB zfH9l5QXUuU9tp+N4b%o!f+Uq(H;zEfUV~I7NK6Mz>qyciQkO)^b@W`cPXi)Jd>!OR zbEEA@SIAslXA(3EP%#OY#HG=A0ty{t1u8 zzd!jGJ9n!KcvCGQHRzR&?q9o*kSZa0E+mvYv1ufRGD}j1#7?mrfmtS0v5|4m1PSFx zbIgvjb}g1`4w;%-J5%oA%HvFP1FBEXG>b2GmHfKcxvhwL(glroHm)x-5N3hKMC`ir ztMofZMNi@`8SgnGi2O1>(mkf_Zm@Z{Xh_!#IC)xZsO`DC72M7qa8S&5KK zHvW5pD^XS=9W?uZd0hjeZKiKs1RzUIv}MMSJlj3Q`BXil~CqaXfHC83qMKYWeJX5 z3BO924phvH^CpH`s&dXPP<+~Qp$r7Qq_3=h{h*R*Jb1sp1Lmm>z#!rd4 zM6x!KtVtwSWTm8Hlc9u~h;8bVaa*YlgsTw$Fzfh0E_E>Hm~ zg0?hCQL-WbI0w`@*BKwxmhcrAjJGBZy=<_Wb}L2edQd*CbEF_qn^VYF?-Ua10T)BQ zMnDXSNx&)a#7?D1WuNgu>_TTtrAX$OHzH9#i8ppd{HoEIQxa+_`#=oTPT#)J)B&b< z9CTR=C{2njp~eW$f61?zu45NZY_WS2Q*#6hygBC*iJ#9Iao-<*9Vx5{eavBXiCSQN<0dD!bA^qiJRl!MT1^1F;;Q=gHm&}DTmz>tY9q2%K_ z%2OT(xF-?icZr4WQ>lIH;LEvud^EE}1yDtjL$IuzLA z_{gP+qdd&WkbSD9;!6=q)tO#ab8}MZdaF+29e^rG^Zhtbt7H?toO1&wKDkoErv`uLKh;IJMZ5o)?gEBSgFM3$F}!KD5`6QB$3=iP>E!(^;dER zpmY-RVsD*)T~SJ(LQ7D&U+97kp1=2iSwtO2n$7q=_aEy=k-oh3+w93&cn%NkGY5`zY7kW?)( z$XbKTH}0k()q3P6q2mdoTtY=7R6>)L(7_0$otg$!anLvkX;s+dvTu^;_%LKyY&2f0 z<7ne0hR5Cp377tOe6dTSH!8Zzs!?JH=p41gZ#YsKiWoTF*d?*=?LmNxeQ$`(p{#~b zmt*b#-<%gkj{>SL(Gq*>B%X@B4HB*3@=i&jH7J^HOli56l(Ai|6Vt3Qon%ZWx#H7C zM7;}87>UN%TPJZ}>}`-xdY2a_iPoTKO+bZ_l(8*LVwyFklZ@%>6lR=EL$*m@4vIKGIA4xtTjkRZelRb8YE><%RLVmWD>i9%FwVFq7B>l;OCQ^0`FD*+j<0i5zt?Btl8X z#jjd7FN_%Ii#Tqje3`h2<0Mo9mj}^v&gJ#r(HxV>L$#rbDsYJ_i5m2EOB+g5il;1& z)+pho<#>rhX8A;#F1bkkIQkqa&)bqTR7&SbqO@8XoYdn8YSEy zm?Gh#H!8Xs+q?j!oH&C)c+;Z%V*yLwM1(4iH_2pzN_hZ;2rBB!hRa_R=P^OqRXDG5 z9SC?sNWZuDdR@$=(Sk1asBrW>2&KNfxLX7TId+@0ikcVd|PtHltK`EZ6c`;qKbj zN!${LHb^MF%L|i4Yf!YoK!uT%u`Ntunl+}AjOptXW}Hkzw#h12M(Dc$rIk?9mzOIs zXs`y!N}CvDtwFNVCI;iIK~jdev*R)}P>%SW#VSL?N(~RiPOY0+BCt?MXqL)$+)DY} zv=}GRRSCrk`AXwN#!2+ZDdcmhk0WmElJkYej5rW|yq?Ij0kDWjJQu>{ajB^! zv75&4(}1>>aI>OOVwDTsg6MEwiB~}UUIlqB03s%ZtS2CL+Vb=RVS$i;Bw!hljk3q9 z%w0AUBsBj*1eJS};qq&O5i7|#{#LcxE?!aOaka~>D9yxh89c0dsIT&(hm-Q=Rs`)? z2Ldevk}lE|MRG|_!52G~xfSpVo;HM9N|BNlyH}A8Ig7&xm+8GpruPyUyQKPKlhTb% z495mTNp(AIEuq4iJ-6DrA`Z&c8}^Ux3&`3|RGAh4(w68PQ@a8Y5TApqqw$u#u7M76 z7)Z$I^69yRkS{p{iKqVyg9dAm%-1?YB&i#RWT^*wXJJ70}f5|DFU@G-R|T%z%nZzb%ezkEu;oQcDHgT;SQ&BWR!i4ZLt zUtD+5nh1}bl&-MZF?coLINys^o<4%q8KUHTz+8}62;!TA^0-8E13`(_0KI*0E}tHh zzYY*pLe@crH+I|k{TZM;CHBYOI*FHJZ-YcUurE7MCD9rbO%p)J21yyGhuk{}BL|5^ zvG*Q{WN65zBvaR6T(kxW9mIJyOorQ>m*1RohFOUPfbL0BRLx_j=2lx%5Q)2hZcui9 zyts4O%CWF|r<9ls;yVY(oO8MSU)SPF5+F|rmqU|8I8M~Z#|f=wR4B($w6dC?C-Zy(jC3;QO?ysF(sb{jMQfkTYRu& zd)zGdNa$Z}vX*qMbsx#)TqwpSLbia;3~#O|u9V*uYodgTqf{i1#QxU!F>Ep?%2QlK z^Y|Jg%PfYjbSHPYd`W;7>}0ou43&)sP*4COe1d9LKC5jhG&LCrErA@al`g zlgLXhSVHBEAI6ra4Dei*%6lD<`3R&ggVWa%b7Jp(5-l!NVgZn`isjA}bMR_2$;%5;J*%r5Hy~gQ}oL54R zXU5H&Jf}IKgD~|1Emqu*#0CN?A#ro;%^hy^hbK1|?o+yovzZCn5qD+g&+&4#=ko1D*qs$7A4M^dX$9bd>ZFLwV>7D#F z9?QNTWrR&2=;g29<}eQ_JmXRNgD4~P^B92?vK|YOk$3X1@z{VAwt%4Dzdgzv^f-(R z;k7%WOf!gn6lFR<2%kaNJg@-lmfpLC_}jo@@HAKotloxiKo{bvEC)PJAccz_MU+Q) z(WCN*QARjw$}{oDQDzpH2Nr^m?sNEstzg^hga=))--(TI0Gu%P=kW`?@-|Zpf_+c? zLLYD~s04#S(0BPslo5(Rckp`Q-As57{6ZP%X~G+KN12IWDp&|YI!!)&8gdS30rNr7 ztBvw^I`lvaS&v0X;fTjYq%f9x3T+;t?xC(Dsh`kB`GnmbTnWqw13gwCg*6@;})in1rvxzaDG=Gk%tY&%!?&%mJCbNq9B>;a~*l_VXmX zJN{D81DrA8=kT8guYs-m68r7=cYvLs?H5V-68uktrC|8}Bzz?P8ZZjoV~SJ2y|4jI~4{wW@Fk-~hBg-D^zV+m4N1w#Dd z!=w$mffCRI9DW)3>nJk_1iLoE=lzQD2&50;9fVKy;j54#TzPEsIE)lt^C3xfkIV+Q4G41S|#1z;Y1Et2pyLo<$0y zIvj=_rLRD($9SYL&0`i)c-iAPQaA%b`lY|4O+io43sitUpav`h!7k_(z6dM^OO3wr z7{@D61xA7pFZz!tQwX|&XFv#_hkqehlnPhbl&^4tbc9_dp8OX*ijOl!K)J^>q_Ejz zKT!NMWMKLZq<4qXQ`n z{DVW6lN`H1y@$##?D7~+IfON5lk)U>m2m;C1w%jv3L5@l(%r)q$mG5kD~LW11dZgB13sr<9`M`3wD|Cn!iy_P!Fo6@yhuNS1K<$2aEbLH%FF5Zdfi0Arhpg0MUbDDml+R2I>AoiWuOX-H2Q1t z5Ab0&o@~Z~I*$!TnCZ(F?9@gb9=-lb`+^Z3%aFnz zkAnYXoPqoc4!x1WNssaQNx9^20+YZLFc%yEA>SGJXMx!u=*}9w;=kt6uTx$|nCh_s zDID|YQIMArMuL!j<-N?CCWooW5Wa5$>o~XoN*a^!F=H76gb52hYS9ZXdnnD2PIGU@ z30Mf)zzVPm6!&r1g6#U<|Fga9_JVyW`^ls=&!@Q)+4mZkZV7gZ6UrgGsow4xloO49rN9ks|!4Y9W~+Y)af~}9UL|FTicKJ23tYp4fG@E z2U`2n7w=E%Gm)^lpmqRl4MIH?)(#Z5#Dpts3sBfb6MllQe9~6f0TW(8SfNK>q;%(v zegI*Ez+f;ENVn?7q#V)@^!jRKgf1U+2K~V-umXf~%U0<3OI*uLsb%A`sH91Sm*VnM!$iu5Pu7P;Q$zc&17TO zLD&&+6dVWAEd*`A=9eY^*(w82T|zxJVYeA<2QPvUeguD)n`sX)7EA<_LC_yVf7~OV z@L(78HctMaB%Z>Xz+$iw1bd}D1xy3;K?kt$27Q1v15|?%U<{ZILi~+`84Fvzq zGhaau5b}}TSTG430EfU45cGra2mK5aE}LnulYWRNeJ%R2faj{>ax_tfpr4Pw9jpS| zOnBW;(glxzHW2LB;ol7QfweQ`jjm@lMuF5aRDA>;O0j4uQkqBuLv0BTfk0g8u~ddIf}Z6m}FG2dhWB zc9=<9$i~)xFS{qdw4?;TK2wD3azZiLKW+$(Bd%{DQNu^G%kdT z9{K7^P{244$~-E@Vh{RwR3e3b9z&4AFprT)L3`Oy{%1PpW!8c9U^6&d$oaz?lYMe~ z7xZ8=*aBw1iE|gQ5A=CUV)tyyZb}jRcQ6~Q?wZ&g!mf(AV?i^R=J5z}76|21+8y9E zFsNG+zP>mwQ+;J#<{7XC1p5p4yI@xYtiAU96Fmywke3nmc{EWLVYo?O{xKd|6FwV% zD_9D)oA5dKTYUId6Mi0lm$z~b2Zn=CPK96ecs+dqww-;vVJ6-v{G$y*deaCK9s#pJ z2w#D}9jpS|P524?!YiO#Nn$@7{|Imv^m{nieK0c_L=ab_=S_;j0xA+);Jb4K82|sJCH(X z`_NXqD7WykM-S2y#&~Q&3P(J;mL}!ii~k@v1df5@;0y@$>irJ-9}EIxKs}fTg8mu& z&w{OBa*rhZDEt+04iuR1k@#yt7Fhdj@I7EJ*bfeXgCOM7_nnMIFc@UONU#C~eG~pE zU^d@N@XjgTkx$69`xa zHh>UsQZLE_rh;i8gsbfbc$CmKg4$D1dkE`14kLvU>LaMW!VZtUNMSVf5*B%^M+!$h z@+rG8)nf(a77lr++(JjW!?AZK<(0oj?}Qg$o0lmC<)8xe0oQ`Qpg#!ptj0eai~zMJ zeDVA8GQtwD6s!QNK!`W0GA|?4gUMhsco77>$}-PmEmG)vjYEH=u-~Jk5A6nedklXs zWdd_O_9KPCluuAOh1nkSk-~P5^GKl|tB0_Lf;C|8 z&?LM^hH(hWKso3IdV@aTT93ZSeqbO7`Hi}j{J?Us5rlBnX{5(2q_Ev%BJ~iS8Q@Se zFfSuq^q6`Ra|s;vcnvA^qn^Sjk0nS!^%n-+>@X22Z1p(!0oFQDNm~fRJk&12YL9bB zVK{9gsC|U))K^fwh2hjwP<@5`VGgB8p~>S2Qs{o0Lm5(N_1KRTc(^IXM5Hj=;|NkX z@6qu=)(>#bqvdw?VBl$w#u0fLVTQ+Iq_D~3B2w7?p`@SA;y(v2fc%k3cqM+J28=f0 zJMkX^$3gxbiTy_W!X~iUgpc?zX@D)Da1`?wWIz}vL4O?m1(4RCB z4QvMcK}c`*7}^BP1+8E{SPS-pin|g!wZTb`uGB>cbzX;GD5M@jvByZHFxq1~QmCwP z*oqXEQ%>Qm$FMsYb6}B2D`P|Fc1WNSv_kbC8!Ql16D^2(=(tHsd1LsWo756b_ z!8EW4ECU-rNbdyx{AS7phJz438vl6E0-iSE3Y!8R0keQ~8$gJ+;(o?C*anV(GvFKu z`r?UV1br#~GSCZ1AHvng>MvoH$3~=Z%0vAksQ$uk>L#dOg32k3p*(`h zCD{CTJis0V>;${P0dN=`0VhEy&nx)PfRaghnIYiy!Uvh~J^1&6ec)v<&KYz{tvT%0^_IBFCf?tB&^kkPd4G*@DB$gf#L*vwZSBh zIY^<+qa7)1_SlUS_ItdH6i#_$XcwWzV%n{JjBZCxLJQgE`f=@WiKngoN_9KOg z84lG*VWP(#q;S@w{*xRp!5k3kKX@i}26MqOumbD=yTKvQ0gixRU-TI3I~W5dgQ;K% zSO%U2>%j&P?3LF#kIhJ7kH^bM;i5+g`3OfnHj<7|GRvXMoE`cG*|{g zdc#R?Bp3t6f<{n8{GgXVVtsBdpmzfhL6ZAfoFw!P<4Hn7oS%u}=nSObDxKDsWT2=oO1U+g=3 z`(k9Nk2f7T6U+uJU>*qh?#CbUQ$C8f*yy(yeMnDXJ3MTB8@|iL>+S2N`i%wkU_1!< z+OTHAg=t1F+a@1A$%JdHcVX-ZWgcs3Tfw%Y{CiA1`Hy&idt!J(8Hq-QW)q_ zjTFXsG$MtmAk;_xM?6}P!Xl65Na0zJ%}8OV$9|-6#N!lFxad*zY03wBc=SOE13jvd z!WfT6q%hTEHd0vNu@osh9#{Z|En+-@{4e~yemVNXK>9|IjxYUI z5W>4*QwbJ;Gp>A0n%><(w_$xfVCUa#(o9N0Bs_$U*;kFW#aWzYenv+?$R5k2U$glmEzq^GcBKw(o&xcch6M~}}i z#=sztsYqdw$1bE$INxCiQaIzWc>!$%PI(OZ9D0zYpM^%+T~NCTl^z3;LdIh}Qkd?c zb`xy5<)7=Z0x7KX*p3vAc$`5B7eHu_^Iw94{HIwf#MJQkUF zx&QS<+*<{0Z{}Wo*W~`_T5K4*G*3pc;$>A>QlhMxh@KCK@}{S#=RwNME?%G0)h|$G;RT18cx` zuovtH!c*;CN+RZ`fWzg&2qQSuvd}(bs}WCbHEl?(6Bx2^TV8 z1jvHm%JC@9G|&oyQ(24iX&W$&Mw|{>KyZrF0`!_4{rNID^@+l2I=OfuybhiPjbI9x z31)*9a2A{g7eFz2l$d;8PnSVI0_g37ji4C>H-fzN|4Nm6FbJ*&|7cJP>OdA82f>}h zUrzp2KxGe3eNyD>RA=%TP55k(u7Ak?6mben`X%_wKm}+s;Y;xE0;fQM$+rZ58R!EB zfWcrR*bKIS;B1&}x1d*%_fwX`paRkd3^4U5N3ZdG78GI=+(|qNi^xmyf-8a-1C_5- zI?xZOjBCMqpfUw#!_E?J`?%DktNEPq z6fh0U1hYYKuczB%^c5It%&DC;=7Jl5zfqj@OF(cMYvrI4^aBIHHW1ul{OZSQP-pT{ zIaEHCZ9ZrN1+-rw(A*5phD|czS|?h;e6Y}jE1uS>Qcwm4fUuUTUcpIM4l01wW!Ve{ zvZ)1Gk0r>ZKy}odQXR5j7kTb6`D(2UwyW{41?t~jAjI8Be6@%A=mMxzI-Ti5a2Om1 z!L{IN^H93M$uG2%?nV&YSv&=B!OpMwRaclwD;NY*|CywHB%` zLK_Tt18oP|z*4Y{dbC}EAGCwLAUKVKS`RxOmJ_BqEUX8?ZN{(hxu0~aNw*Ft{oqCr zUI$vhd=Q+d|59okc$lOb6K`7|a*1NF@$ z5Zo^OYJ*dtoj5yy>SmptzvU=2KPy2$5S(n(KUP;2lwJm#5_l;n2NghZf(tg~1O%P> zI=EUq>bIp}KR5`E0_#E=|K0g0Pvxb2Y*|(BYET2#6flQCaMSV31Q$S^8D9!hy$)mB zVeB^(_K(KnY{rPN+Kd~G)0vAlU_4W zy1{8pYXmyhw1MD4TdNJLeHl7TITSVx=vdQg!iz~j2y2JNK}AT^%b=Iexx9rQ!I93{a!9j2w zq@C*00uBQ^FO*LR-*3`W_y{0-o1Sdj!5XjySXTfk1ZoGhK?P7cLNk~I4w8q?!Rn}! z_6Y5aWsUXVLYyiB27`(o`9g=P59tfO>%76jlf?1{Eee=+$<1>j(5R@x@lflns%%uP5+-uSeabzo4+jNIp_oIyjB|v#X#eu!UK_WL6>g#e-y5WN^3M& z4%BYJsgFWdopnR&q2%vFQ2h#Zw6qSRSU_Y2|+Cyth2%l-fm0lx|{ZSBH z6*hxG23Y%`FTk)mvo>PHD9P;2EWR!_t6bxUJn9V zSI2;(Db*BJ}~gTX`)9O`)O>x~>10+C&T+O->K2En!9nG4je2Y_{Y5v7o^ zfj&&(y-axcJZJd4W>D#aqWY3&;GOXl0>vK_0zFsRx`T2MTu(fzOJ7hG0=+CiDm{%Q z^{4Etv-(hX+1Y$$Z|$U4Ucu?ZDEi<^;3~KBQ+gUByFm$k)*Wc9SeH(>!YaLAb-orn z4U}HmsoymIHKyhmWfOU6tZV`&LGS#__f^K!dNU%OA|l{gid@%riinJ>@%Jw~>7awF zeJbcx6XxoLpAMDm6uA?!y_W)4FR)hUxI6JWp5y9q%9-Q({3F*&a$K#-ygn1sdsEDp zzZSS!oP9x#>#IwatCcL*cOWUxe}?$#EqE@zUP^2A>ILTN#bE!|n78E0r%}Oroa1jx zagADzZ8`nhW8R+QTIo1mSbS;(`%Kq?flOV~r__*F6A zpX22*KbYfJ$NXrH_lo)19DjGr&*!)sx%2;hkMIBY#QKFf?q=S?eWCrXiS9k&-zBDS3Sf0M5cSgHaN&%-Y-N&z6bsX2b^W7@q_$Lu=RdD=M2sg_e z{~W^2TF3PwcQ*?iUx_G}H+H8leG}!i{3be~fUW(s8}Q*^M&C zUqU3uyVI9`2X~{u>Hmbt$Q!%Um;Q=Odg=6~PI+#x8T4<4*EquO=}T{ik2d^jc&*{@ zgVz~;BRp&PPymhxyFFtKb*m>I3ojrR@8s_{}MvN%0TCvv1{{4%9>G)u;42AMPmO9T8st zL3aqxm49~1enyJVgJ0;*`}=%(|0$*amlXeYif>Hu=TrR0DZV$w55gOHr^X(n>URpM zcWXT2%hRP(6zM%16WO{*e+^vk+UW553|#Nr*y{E5@XYs557kZ}FB%#@*P?fE94T<| z7pL^!6o3BoQ1zeezYA}LXFT5y-vMv&{1@=*tqK2~^l*)F#Xk?PCI7&S$agQi$m`z? zKMW7)=^Q@0E#Y@b4=1rWz5B&~0HXY&EqvR*oF1yfUhPnpAwBt>6_qT^qb*Ff5dxU zy?!6Ojr4U4RQ(R8>`$lo1-RY~tTO?n|0Yf;^q$}`o_B}qUBMNeUjq+L_3fYHx4`u- z-cX*}6n`ki=fd^g-ZG#5a=6~z8{&TluJ`!%_WIo^{u{X7?VIuXKg0E&-w?kG>#5%L zt7D?-cRhTm&UXscK7FEFQ|s-h6wjvk#1z;4uF~K0-X5R+XW)9jYiO?(aJ}O-l>fVM zz3+9fx8DQTJ73jbD&KG61t)k9mFKU)^$yrd&#$E16X7AfK5)GgHt?Zvy&qOPbEP*H zu6M+a_55MD-VdvFT>5$N;MAXO@b+g<4`msQ$4@(aHN3_1weX5>CHm*#eGLC8JUFHI z%M?Ebuf$$^AdSzzr1YINF}+j#x5D*KQ|*yd-k$Id_%P3JgzFurq5d^+z3()P-}~Tt z=c&##6n_T%a(e7pE_aKHZV z75`qsUxo*#{7$6!8Mxko6z0R<;Cdg@Dk7=;1x!@E6KS{SMexR5N&el$_ay!Gc6bLo zgT2c8PIz$2|J^D6ez@K>GZ7=@cNbjmoN4v^(UkohxZYh7+W$)_zBa{wnBs@v!Kpl_ zQ~W$!@AU}jzs+5uh@;5<8n~`E&>hsTI2x4F-wD_GC*6Vmt?O7A)NdAQCY#1F%RQ~6H9^`HG~2~>M_Vk4pd@AvY&6t4g9hxO|H zaQ&ZuuGeSa`cHqo=Xb%IUrhERAA<*{{63}lx#LOyXlY8nHpPDg*MHhGB%<>D9rxjd?8%_#qH+xtKs@zZn5V-h3mh$8efWk6t4g22K&=+{jYX` z*B4W;5tQGJ*Z$EB@EUjp`aC|;t%6U3yY;z$R12SO>N_1i)9@$Yv*97V&%uLJ{l1do zUx%;VdwQsjPil{yDg6PsuFtvoRuY|rw;G z*MEGfynZ-b|MwZ?d7a|(pP!!IeiB^&{VDK#23-FETIKm?;QB96SbzQ*zT@Yohpr(# z_3yXgQ}!kNd3bQ@zn`S|&*A!yPFSyw!w>!00>LJf59lwN6yr}yjs zkB8QB*EjzEZjbk*`m1k>-<0A*Q~dT6zca<_QvBW&pPb^KNbx6Ad|`?&P4Q<^e0_>< zN%7q&{)-epoZ?4Q{A7xsP4T~_cxQJDBpw8sFKAZf)xL9inpiuniOB3;?Je{jud|}#SfsB}B*lBC zc%Kx%A;kx!_-!dZCdIQUeqV}DN%6;0d|rxwA;p)b_^K5DR*HW&#kZ#TPg49BDgLVz zKbGQuO7Xv?_!aJ!Uv55Jnd0wE@%N5=^-38iDEB&jurMKg=yvy73=f| zi6Xt{Ma#D07jw&bfT`bA@Nj=vZ&SMn4_JN&0`lIP2>S4H23>zghYz5SSX(;w8A zW{AuC0(!1lW}tEUi<+ZI?^kYPL$CV0f_~{0iC#D3j+*u>g>N(cS9}-OgI4fvBc)G$ zZbDyY?C*r@T?m}!#Oc?;7p+hFcQTwCgqfCDpBK%9Z#3!mizibe8h#{V`!YJV*cPomFmr zFy7hNH`ONN{{ZRhJrSWkcYcEXI@d?T_<0$9`5Tk+-Awv=pPTmYYTq;Hry2d5nU7_r zy?eu(P5a#f-w`G0-31T#zg6E!@T2rU$%*7e>hDNo_UTt8e8WipCSeGa16do@CP9EUG7^HDcfU-`DX z9x3}VcT!H?uM^t4xCiw!*Ta?Gv9Z+W z6a0TZ*3)0apK0nl2_BxOQ2Tri&VMK}n8)dV6<$)1@A>IVyBQyKQGSN%$Mt&_z1~HT z@A;cqh^FsneIr2avkkr85gOKu9eCe})$rew-6GecLRwSC@BkJ;IE?&G6~n-Sua!zun+RP5a#>ZpP0<_!2WdJ^>Hs z&sRo+q6ZlGMQh#la<%W9nb@nhxa+6lU&6lNO-cJb$-<&{hmQ31`#1D!O#6Qy9-fy_ z`~Pkr&(odddq&>=H|V#R`Fw)$GU_vYqrvO%XZ_TBv%>t^$9&Se%0l~nypHvU>%o(} z{ddbazC6Oa9Xwz8DCft_?{NI+cpvBE_wkJY>FJ+K1IBzgP$_#U0Fr_KEinS_IuGEHRJi4*KvJ}^-AaG>aX_qN0Gj#7S{jUCK676 zF82E05WmB$AO8st&+n+e-t;c6@7VHunEs@H+I@V!BNXZV`=LMHI4X+tZNHbjz6bFK znDIP;j(CpsKaA%p^x^p*<@aIqFE{e-xj25OXcT(>Uz>r(^K}vHZNL+vdVTXO_D_G~-8-I-BmGlm{5=j2&y%S<{{*+|?P_>< zUP$^4@Y$w*-}xBh`7p;1F3@RxcmX|2LWb<(^8Xe-mgfOF$N6`P{s5nE>URM?-K@9$ z`*HpE)nvWAR8IR|s*VnWjd<4$_?=q<4@=t_MG41tf_%t&(6HRLQ|i8aIME$ zU$2ZRqCdfRnfZ1R-eTIL2jjPy`cuq!JimqYdA-T69KOV)e-oS?7qwP-PhYBG{!jlb z-->~2yzs57XvbT5pN*eCV`BR=Is1>n?eX9-_(9Wue|nJTR9RoT`Scc}uQlu8vvB^0 zok1P9*K_a+(|+@N@yzHy^KB9zzYpV6@5vqO`KQ^h9i_Z8JpWP?PE)H?|CdQRz?_TLK+&*K*Jg!Lcb zm1aD@oBq{1HwlZ=E9k|1H|^WN`l4^ohW2?U`t>IMT^vuluHc(JK7J+oEvCI*nm~HD zCF#F-KhH;uNcKykupey7yYyb3hyPNPDfj6$uy8LJ%lisFABX)()4!jBmz(}S_;K2g z`N1+6*XJvY*V(K129oDr#s07<|M%ewO?iI~pKsQqU%}hW{$TDP`u~f3%h9LzSH(B^ zU&;K9On>)=A2;j4-7G{;Z{mD8#4qK1h50_r^P8}rZpsshvmdMWdcKbr>6`PR|3}fE zdjIoUufGHPT2uZ%j$wbkB-uZG0=?dC7slrtc&nLjUx80D<$oT|e@rqYAFpRU`*6ST z4}43~=XVnQ4l`cfP!a#9FlT=ae6VS69r*3>{%*LwyFfAH{_5PD`z<#l>-{6>ll7SO z=??C{{3Y4n+|PJg@O-kLTub|op?zuAIK46k!r5hfbIkKY+_*f2eQ5taBiK(q%DcS0 z{xR}vH2qaRh4ON}q)V*t6y4AHvEDt~*V}&$`(38Jeh9BL0p6x5gIp?ah4EuT%8&^^AAUM+W%%c40gmp3S%2#5sQUCB3yK|16wmlydc* zCT`mQy9~_5pW&O1KD|Zgml!?YUyY`i`O0^{BE1*5m$!coyFuL4%c{A{EHkf^-llAp6_6N)w}hJJ^!K7dtbue%6!mw;@$eh`3Cw{ zGhdFtPvz#z8>0*G<7WI0V?7(l{$i3(znt}v_cdjp@p^PS;(rug zY}#`we7Wi0IdHwVG_>bu;m333DU3>4n5y>i-bEo?GWNe3M*n=zJ^wBJ zUFi3l@i`T)_u{tYyZE1i>pMfC|JvZZZzPxh0rr#n7SUXv-@l{RH`trO6-&iXi$ zcQ$(cZ_rmTg`jc$F2a|a@p}~qHhn*%(A$r>kMn8fLl@8A%zljbDrKN?{A=OOraT$= z9_mB(@%7>d?_z!6cp8qEHRvl$fBwfk8xIR(j%eSnG@pmw}p0=6zI-k<`xiab%{S3}Ch8bvFp5Mdw^L&irU&+pW z)!nQY?58`!Ro}Dd!~d&_qZ^_(upa2$!o9qH5)H5K@=Wx+2tCJw3^Y#vJ@6sjL;r9; z2)@l6Pio=%mRJk+%I~-AH+KBl@86lPd-_t|jp2S$L3BU%ZD##_0K zex;vJZ$A1mGu~Fgx0wF;0lbeHZwDtce!2d`9Er>G8}xdYb4dRLywHrVdp^wdr0&W7 zhf|>FsA=C4_p+tJFVUYe?f)t~ zIsfB%EcQniO#RB>wdVMG6I|DSC=TP}^red&7zZ*R!+aUvo&NtS?>Sa^>Hk+*7_zO& z`T5&uFMR`IdA{qPw{v_c{f&FxN%p0jpLOMU9nN1ylHY8zUVUL0`%R9=Op~~O??JC` z;2rh+5%`Y${0x-x6+}{O#Row>&*E3 zG5oA)?^AF)|1ZJY&HU-cKt5&Ci^kDkT+a#X-PP#z?(nY4pYpyBzSr3QE62YcJCpOj zLFo0pi&AfYH+&DzFIV~cOorE*{vFTpZblo=b9?=#(C;$+_gxO`J(=I-aeAGi73im! z`gTVHB7D2s|?5?+O$%Sl>r`ef|xM@4m_Pthc~x zO#cjk_cQb3`#sseE#*76KK_))Ilo)NcOyK%4g0p-`gmh>7kq3_t}n;qt5ehnKX1}I zNq@h%n(xW`_W1le=pT-6-F$jqpTT~!DY;(y=Z`Tz=kV?C0*#MO(FCsV3^V5=gQs!7 zg87O%uK$(Ite5B=?-X5oEB({%*E7b~6O>2qjSv0(X}CR}tcJIk{`(<(rs2PVR~mjE zuJ?2g^!0fo^H1M)((yp!>B|1hZ~y;Z&DUxccYQmp!s~mY-(mXmIyiG7gPQr17u^D{ zG~@k-hu9Bre$2KdPJa#ii;Ij;rg_XC#D28t&!zC%r$TzCFRg~#`LYpSW%B<8+_uM` z;nU4{d@Ji~qp_dB@mk*on&R{Cg?^?Pe}mxmdcsJ!-n$>#e++z^IUYQCFXM^+4C8qU z`m?6J?|hK{{&@2I!amk7eLE)1$IoNGpXa^R|GIwp75GxK-?(usmwz~4=;q7&Z|LoQ zWea?V$*=xHjE4^-^Y0LPd;jJ4@T?i%Tj`&w-r@YCQ}kE#6{bD@jq@{o|3uSNQ6V{u8uxQ{q!xO5|Yt)x|!<<`u1fw{uJKCdSuGi53X;6gz;0%@w+?s&&K-r zZ>gvLO@2LR{r>>=Gfn=D@RMe}oC!Z@(*G*Fy(Brlu7-~=>)CcV|G~?UUEH1>aD9s* z%$Ixna6WQ2+0Xw8eT~Vl3;k1W*2CQ#4-P+_oR9ZqAnMy*VZB-P2uTap zG2`inZzFN$Ymu-2C)qF6Z%eNC48lHHuWpI%g6q30q5U4Ap=%q%ez;R~5BfIK9*@E8 zczuTX*u?Rq!squz^s`O-PRpS91>gRWp7HhX=PNJ$~4o>w8>ZVOYlf|10#H zjegL_IbZlfvY*&T`|A5-ee<3DrbjuR{UF&d|4Hea_IbQuZ5eKK6-jgfBPx(eNE6{>R{>&HSz}=Xtj0lKsTv=xfb-z69Q8#`{M; z$a>28lk(GifApiI&-D(Lg_!>f_BFMjW_07*vzNgE%-}t#G)9CH9=~!`w z4>I54<5j0GMuj6_%4`1Z^<4^D4 zd5e4aPLD5dh3u){D9?{iV?8^boG)CDJ~=s51<;htr@|1U*9$&APT@G`?c1aCL(`+2U{M)RWF z^A{7)+x^17UB&V6pZ)bS*0(w6OU-=PFq84gezPaZXnZX~Uv2994S12^MYE~@*WCZh zWq(yQ z!1}6hc2bPEyseLOzC?f5cz(O=P5Ufld>%9RAI77%?eir3%uDY7+N#e|IR9zRkX+n9 z{qANwal8ui{msn(j;>*Tc8b1%y}p}utL)AAL)kZFAgycVJ&=>>p{6m)Hl`ZBG=x}qaXY0^JLqJ|T?%-(p{C#`}kEW4+8K`|;P%uQ%=8X6__@BUS=*!o@YOdev3)}k8pik zY)2>8{`teW{$u7>34E;?Paj}^Ywy>*8@(;hjUVB8;<{wNJWTOT`NzR|2LP?^=I<YL-Cf6m}3;{2jm#Xv#YW-fGG-iuF(5PYvmR zmWg$KWpX{Z4f|&PUs_Inntxw|?>EPrAH(hXc@RFu=wE}k7=HLh&X<<)ejt^f_AISt z|7P^pF~9fjPOc~SM?cA|#}C}Z^CetgSw#b=eQrnJ=HHiB99(Q6s88be<314s8a~|Vi^!3Sj`6>D-CjDR1Kf@Vs;rRM8`U~AyU*h_8ihc(# zHR%n!j{4Om&r4lIKa%UUoxT0OEag9+Jnzz({j$EL8P?BAc#jv7bqCjVDC!us0p2T6Ut#{Ilj_D>^Z&-i_e^jDkqUkKOz zOw{rE{Y`kK8L#Jh!p|l1eQ^)^e}&(#klse@NA^#ym+fZ%Gi!5{nWg-w-%rq&n)UQ3 zy!YF~_4-cHpWrVaP3CXi9Xubvez?1j-`X7d`G5viKUSi7Mje)$)@T=h$%y_-3 zlHt{#H6}9qUElS7LwC%=bq*Ug%xNOT7I6^ass&ekbQ2m7^Ii zUO(hkJQT5jAC>Pe?6;Zqq=fmWZ^N^#iObuBKEA)gc)K#XE_wuhiuYqEzK(C7g4db( z_H}r(sedu!WhduTp+7dE&zSlig4^-;dw68px19Ca{@iUz<%*Q^ass)G6$~jFo*fJm-TGbSLrW5zh1na^OHN0=S`MjKib59BgdcR z2e>~gd#$JF?fm*NT;HMX;@k58yvmH1PtZT7&L_`bZf@lGz<3Gk=l`0?`Afg#_&1E> zd9l$yIEwX`>%rwd{XdhwZLiMEj~bI-Iefn9?_1$^z4#6TbLam^=J&pvdHy+{``JGI zk6>SD()$>^=@6Gde0$A?>pQy~cH;5#Rk*#M@-4Xjf1&mI%ILk(BOGX^o#1|*Z@&i^ zFNK?uq7VdGhd&9m-I>YYn$M8W<6iY`n8Sqw7{o#=pb)&BD*jNcbI-|O$w`#tu1P5b}(cIta4|4;Gyx$j}WczrT|{uBEG zGr!B(Ulp4A-2(5?JGovt20qx-ciAMa=W{%d+ne?HhWGLR=2w&F;aYCx`oN$4{bT0y z3$*V!_Ip`hp82%@u)5@V^Y&@X7uvhR>!*|7v3GO-A>XyneE3;Y-Vt2?n8tVw>%lkB zPch}coBe>jKeruyjT!%6zLw+T&Sd}m&c2)va=umV^KXAQ`=PPP`Th>-+iP}mJ>><; z`v~_3g8f0#uQKWX34W+&Ugn@rFQ4_L&Wy*e({TEZayu9u%|8=)ba7~0-SfA=J=b~AK3jvPq;n)-UipV>*|Eor0Z`$wEG~7kbkD7gd z?7EKYNp~g3o3~-V#^m>X*0;{=7sLA6#KbA*{#U5)jo42$>+ukHmD!Jtf}b_(!9(zJ zqkkOE?>gqs!jpNK^@`8< z-f%zTeIf7f_36EYJwqyIf3br75$kz(ub(xI_8RE_Pey;VUQa)ooqklL)ux!WUA&dP<(_Yog zH=fbYlEF{c$mff zqnYFOSFM5z&8UXJ&T?W@jez*xf{|sUTvDN-HYXT#AZbM5I*FVx?9Q6&1YH=2EV5 zTSRJ6)0QX-Rh0WZ=l44Q+1Xq9v}Vr#cYd$)JMZ6PXH0)zXFVRiJiTx6k<-Y}n)6yG zaK2>^>v6vC?-u;A$GWqHp$;2A@YwZJ!+ z@sHr|Tupv)Lh7^LlawEB==0MC@e20xxxW2(>>wUMUoQ?Y_)nVl_F(_Mfc@|K@{dq{ zk?H?)z>gXFeBf2!e>CNzzQO!IdssOCyC8c2_{wa4l;>|!pIB&!=9NFbPyE$*UOI2` zuhO4czn@_bKlxM||L-Wj)bQ)kF#bNnUvEPm7q$}pmr{P4DZdT<^1+vp@1%dxZ?B?! zv1#voV7tCu;6tLm<-R-cO-6rx1Q^>F=kqP#+ZQJIUx1G{>;1pc2QR)mohSJX<(Hd$ z@E_psi@v(XkMFs_*TO#wfn`6gg8sebnsmPBSjvw#;2^m;d4G;pb=IINeFU^9Eo4 zS>#U+>8AK_>ucc;;^{E|pHTm?%ToCP@bhBwk94c@c;E%-OQRniSdD!ko}cpVzaIPl zt7DS990UF`!>_Lfeh2H#uyj5b0N-r%$;H5z8~%C+@YRMs9|C^L^nVBNgjvtMz-O5G zAIkWChrPPX_xFL9lYb=sIoQMhc{cjRoL4`Bh5ZlY6Sbz}dyMwJV&v)IHzNN=-j4-7 z)Qo525cdVhUj+TPn)2Od{I3DN&$KrNyvDTmPT(hvynO=rQbUhVFNeQBl=SzjPrx6A z-wq1nohDu-emva6uOa?Fbl1G0UwQbQyO=Ndq5MwTxBFWU0Uv1A>p=9?HHMxq0s=$G^B{KlwcIH_-PVdl~rL z4`xl3{tX!K@=vDy*A3La*2qU0_#QL9{dMvcSETiAQ@-2ilS_ebVm~;@!yf}*Zr0=D z!1JF<=d-r$qCMlE{B&p09^483LbHC406%2t_jBNsA2=yH;7!;I!w(-jpZw>xM4#QK zBJT^+{zMJ_eRzHHw|;dg_>ZUe$^NQ^yj_<3^|2oOjyxac>9?Bv!g@3Q7t#NAGvAfK zw;TA#v+yUuKh)P>fd78(2h;h(_Z^3Q`gYnMIGz5^;5@-@!Ds!p(B2{w@BAEldI$N1 z%YFF;ls{_t=TCr#%=*3V4A%E1^oQ^R`tDPdA86#^cHplV{JVjzKlB*-_8#PUk?3Q_ z^M5Jd$9lHKAELcq0gssW=3m5k&3e3hhV|^Fe06ID=VQK;@;xsA|J;YNp~tnaxO!PP813mmIzvtVN#&yB~DFF`)n3(R=#K|XJUozkM1JW{UKso};tTL^ zHS_x|^m!6~hex#i5y~Gn_Na+H+y(s*b1kn?e(n;_f3&|Ic^ds3?R)y~qWpKn`->Hy zc#`&8k0gD0Ipr-gzcYZ(K!1Uz?e9IC@!rV!Yv0~);D7s`+Lz#u$Hvlm#-g64vYG$NP8?`W!>~TUu%T{vLU_s>R>)S;&0xXYN{s{vtmW{DGr!te!OX z`BlJY8-2GO_&x*I$(LMzZ91=h8Rhqw@&@$0Fc0~>1=;nK-zKy#FM-4x` zyhDHg$opKf{^*Zaf`6$Q|0hmoaqyppq#Szw2>sd`P5UipgTLFX-&=r}nDw{=+whX2B{ zYyHpRAK3Fmd#Qi8na|7cpOMxNeh(_Ker9}})uEr%->JZoAA#M`2d88QvA*};PdvZ}X>U;z{{;QWnP1=q z*%t7RGUNGY=C{ZAc_seOUB+L1g7PIszK;|ru-z}GtByZ2>LvFeah!=ru-0tf8r732mUtc?>gmI8~VQ&_!={xzm#(M z`#}6B`r*CUEBX7y$NTZzLV5Umms0+Bz;?dh0bXz9<==t#Mt)hG{TBFkGro*?|2pCy zctY3fxy=74!+$RYzSYRXAEICGxjEVEPb@b z`fa#?@h-yu*YV8H4ywQ}W_?}>yv69p*B(oMkNEvX5G3+kD1910QbY|0J-@pFIP8|CniiDey%` zo_~#@xc0KNzw}zl?fZXk0lwVKw+n3j=RX0q>-{0%n~l7j^lJ7$uLx1is3^GsEb&ZOQ*RgYsj|_(y>8)rM$A?ZXrJ=g<8W{=b)> z4(0m{{r2PUT=_t-zq|+YBKAw+m$2R+0RKVL|EGX2F!Jy>z%!=5Gth5`?@9UW1D2qF zX3~2h-v$3k)Bh8|XDm$PJz$*mGVo!*_I}oOCij+Rx_{V)zplGJ(eE(g&n4%F`Cxyr z4__ufb|CZ+`*afREi?SK3E1Wj>cB}qo|L^E*zO0sANai=O!9i%F5+$Y>2lxx0+BcL zW8ja^fd8b?pLYS@Z0Pwj;EN1B{|oqX1HbyE3RDe7&LXEx;F<_53^FhYbGrfp0hX-B(iomr37z>?QEGSBKqyD^V0p8 z3&H<}k)OvlA^$(|@jvu^2>i->L%wuj)&T!_GrvCtzR}q8+kw}c@%;nvQ)d1@1Geu2 zJOzBbDStltEb;S+*-HHNt@!Jx8C{=OP=1xsFGIjBGv6Fo{QZUC%X_hhv!1t+Pk;w|pnWlkgYitBgPLnBbfFJbWJVa&z*hjzM2<#~ufJ{tOZe#~b?o1b^d!(^EdU zx|Z{o?@arp0$yn3Ydi3W z;pZ;!RfeD64Sa)XzlHu@J%oSh>3J>XUorTf0p4!nxz7VX7}xWd?3=)QOnYBF27P7h z+rIUjzhpn*aKC=v2Y zxxiN&{5N7Of4n2*N5^S@*(=j~>l5JLW#r`w;3cO1b->mi`ZVyBhCg0<68!tG>=$|Z z-AVb7Y42wCM=r+yhE0{fe?Rh|Gyk^&UmyM9 z{ZD`90gNd z$$Xa4zKrKQ%JC>-eD{M3@Hf5@@)x{cMS0iI?=s*uW;|B|pAqRbFS{A|E~8)W0Jiq( z9b2&fwte2)db!R()&47|py-;wOMJo0F=*Hh#V);}+t zx5i%spSAGxn3r{ciTxt{Vc@#qzZ-!Unf4EOCGv^?a41w0{e2hZnVJ6&fv+{~&)Hu@`2RVSA8Pd5D}nc1zyHj6$d{a_UJ3k^DSsXC&8GeBz&D!lzZH0|8Sne0 z{?l^H%f;_s1b(5(UpyQ6d+fe+|KlG7-^lYK^wl!_ql0z63$h=gPcHog=Ls=z!aqL) zf2(P40rAyCX8m3c{Mn;9PvZ5(X}~fbsx!Y=XP;wacmF5;!2(Cm*HNDSe#voJ8~950 zqh6x@^Y=25|NGyN8r_}eT4Gc%=m5wUS;UJ=uOBo z{@6jjzbhA`f3o?}{(l2}F6?dRf057qPY+{H&If-!u<*loDYyB)M}U`@{(b>`tLg9A zIAba#k^tm$#Qf~Dr{B$|?J@|j)Z{dBGp|pSXEc*L$Hb3T5?xKDnKXEeqLFn(J zJU{*q?6G~n{RiM*Z~FTg@Pwhy3!ul6ud!dP<6oGaIKp`x{FSqPd#9ogu8Qiz6bfF&Oby6Uri zz}8+I3cU|E^E(YV(PRJ9_npuFKlzeZ`2IFiK4aFi0X$^Jy9-$Ib+8fZyCnPN8Tb#J ze`eY`-ggSV;g4&8A2;P`TwA71@JYd|E<8w%>28+DW9?b>G`i_KXy&} z`#bNT{3wH8&C!pBzn)V?-FNI$|0=~_6etMXA=)&YbeVXz|&3Nwve$ep8W5AD? z_52<1DnsvscVhnx{4(I94F2iB_C1u1z_*$9TfowSfb)~Pr1N~e7Vmi<9Bk->@^BosqZY6#6E6Qzt?Vw%w1BQQI z48M=Sf5-dw7gK(?k&oIc_|L@KCsTgV+f)ANT;LlGeclZGq=7F1KG5*n>*?w5kX<<}c}T?;JyMX}1`C*a@R4{&|}1`z)IJmq%3_B+5ffB7J=<&W21On%73i$A0M zYSZ6eFUCJ+elPLk`Nd12C-&FrOFAY0aH-MXpF4^33LocukoV`FL-{?1UQ2;*HSMnh zw);cFz=s%qsRA!F_}@AX`}5JnFK?s#QiJ~);EGxAF9S1{A%?H|`+g}mH|ur4rRa0x&%X%RzBlseQ_u&D4>v^DZ!`S0?9EAkoq0OrKpxll z@;`b#`IqUGuRZonS+$AN%2zD>~o0`5<~*3b8SCn7I(Dz&>yn^~{XDwQv(H=C`jT(6ee`fKS)rFMDZq;{=So;qo1 zv)66)x+hgjPgMfi%*)Wmb=Y1jch$XA0ByKzG2I{@N?_h@N0NW`1P9j zYb5oJI~?l{ z$GXF@?r^HRCbn{F{Ixs|aCmtf;Ye(IB(^;g+a5`6kE|WpHXPbow|3j`h5(G5zjjmj zea^Wf>++Gaw{93dJKH+7VWzyXU7D;8*LGF2yj5z{%K1d8QK?tkSzc>&tL=8L)y=Cj zwQknyHcLy(S-mvck$)<+DgN2fX~GQUtTSC|jrAJkY_eKexwO`4mzFNiYOY49+pK}Y zKXt+Ew%w21{mSbOeVHri363l3)l*rc)M%bKHP&h~s4>CFJ7cg`Id5l$qFj0!o0@Ld zx>bHnkM;z6x>N1;TKt$ST~c+Q#>VQs&V+obHEO%~w_B->)$?+5vemA3I(dB;zbn;_ z|E}1%vZ!`gi$c#hw4n1W#h{VP<)df>6BB`r-;Uii8$E&V0tu&~Bxuwt52CT*)3STTnXR=hU4{FgA2>xW{WcXOuck}v_ zN7|)EXRO)Q?<{q_HacD|ui#f}VrO2SsI~H`Q}T9mQaBi;v~KtfBkRsyddiBd+U?|} zs_?u1YK=m*@+Hbjf}fY-ms}UO|6{MApQZ9>Z5-b9Ejb{cY*t{n$!0^FuT<-$ogSgt zVwI|6rCz=3849A-%9nKVR<)h?I<5juc1v|gKi(*Hdu`$PN++K#)w+2N8CIm~SdVos zXXDjweo1v_-mVD!gf*77M3FBG(?$EpI2AvyHsJnRW84pCVzN}`r~G4@S5R5pmx$DP zHkYQDZ`(I8S*kVoS)QntFM+cgm38NBJ9lKm)}<#e=RwFppVurK_<8ke9c8Cg%PY-k z$Xn9+h|E<6RycXZz|X5!4*cxbya#1s`vVbIuFfjeE@muO++Jrimobetn_XGfYEWug z+MZFJ!DLrDo{D-*$kgtX@>VA>S-UHgmhYWvnKjiW`BJHkSCQJuQWt7<28?OtvNeM! zxpLX5%LidE$HdI0`$`$%pwFiaYHWwjEg`$n2sv--SQQuWzQ;}x`5FPL7pFT)K zZB(*T{9&bp_q3+2rs|sk^H?>QMyr+&kG80Y2xYDk{&q6Cz8@ltuGBct&1TnJ+Mke#@2rIt8Su^H#b_{!;X zwSn?=Rw@uxjA^T>u463H`P9UtX;-tc8kO4B@mjMHbY!*D^2`y2NB4REkjf?2O)2K4 z)@OA=doh(^u&Wx6ouQ>v2vq}hb{}qBv&n8w#GvI0S;4!c}{b~>nY5290{t( z`nJ0U%YB9S%(qTytm+q$ISOTjsaoB3njLCXwSHbIm+|mx;-#mq@j4rwx>$xbwzfA3 zb2WPs02v&|Bz~2|Lua8gzp$yLYD1inP+fd)w;W=366D%)l|f0>?M$4q8_lp%qex7H zm|OhGY6YUMzU9gk_<`_|lWtVDD?4QnxG4uFOXk-OJcy4+9f`wpjlT ziZXYfJKdhfp1lq0)=@?N$*1bIT+ktu_<)>3yZuy;&uh*r_TYLyu8Cyx?WC`4l>W<2oL|o%l_b=|c z!jrwaLugdT-52QXzVsT+HqA(_vD!>!tfR4gZHDCw04`X!Q>#dfKPJB^@{m-hXa)IR zDd2dBL3Y9*-H+;yjvu7^w_bJsGDwHOAl(-R>AvV7-8Tl=v4aeN8)T<2NC!y;H%OgT z0NjXe1tK=7j?abK15HQSZKGhJM4)50CKMmt1@j9%rc3op_!mj5qoVzy&Fk zomywKUTQczw02wEwOWT*gYZy()tl4mrqnv>O1az; z!IobW;nSohU-%M=CYw{$6GfgKCOJbvMF)$+DgWdGlOZaTr9fsAz_$RXr36Lm3U0IR zGfb`@`P6Ai+{v$sM(yrLXuMu7`8MjY27Z^TP@nc4H40+@@^u<>^^=MtWNfbIZu62*v)9sZJ3F1xwyY8vHNSEs(frzUn}Pb}?#@;<2aUX4Lzo~( zgvH@@got4DF2sFM*GScUz>dX8wmR$1SmEeMz&pDY>mP}g>vi%qqa+$S?G>4NJopnV zsN{r0Ww8!;(Ik(WIWEeM@SVI~Z*;0sTbVwHhDh-6mUA{q8qKxq{8EOQ<)b9+9H>fe z49*m*YTe+_W-_)iLG{NqUE=4zPR;6ighcH4ISPiVGVX4t+8{eaDg@$&f*gk(Ni_3K z!;ng3ngXf>ofmgY<4{F==vF6N&336>t49_-lL; zukEgYuAR`hI3^PNYY&w+%qC1ByqDtljtk^QOTCH?-6e4(<6P=83Nt&Bk*#Tp?Kd5^ zjxHzH5Q}6*UEWOn@lq7LFx{CJV<^Sui@9dYyV8>80S7Wt43xr{P|Ko>16Xf1#xI_1 z1yFh)9nGgJ<2qU>VM}T&2D3fpFeX1B#!V=S)KOVpy@FXKV+}m?C#Oy4w1lGW5CKoWHB}_sG?lg zKox|GNLYD|YW-B4Qrh4&`FAp##rJ)=b}Ayk?1RMaJ#%p96Z`^QC(rd&uist5y&t! zw{Gi%Y4VMlQQU&@irnRvS*)%jV^UUP*ju=Rd3ll)6*;?rB4gJ?4(fOXivuTBI&8L( z_*~J>r@i_ZW3wz@zKjgCZ`u2`0fZ!#%2X%0C3)V%8#EjjxqvZDkvUC%P||14Z;B!* zhH7@9BwSUU`H?scA`Dg%y+*p;7f6pPV&Yb*X$`!^x~O{eM5=b3jle5ZPct-7q@K%U zLLu=UEcd1%&e9ofxn{d9YwOWZ5*Br)(s2-5QlbCER^nKQBd`K*1_Qs5u+DL4L)-#C z4Z@#RWE82Z%q^Byvb1Ak0nrU=3tOnpadg$C!YH}!Hv4&bOBh8|(hU^W4!vTP0sEwvLWSuGr1oVTZ+zJ(( z#?sxW&{8xJy~aed9#!c!)v}VI^bNQb5V@9}^^u8ovo}7GpK})5m>z@u3)zG)1CBH` zsWBl@tm3CDWM#dDTS8+=LfFcm66*Kb4R!ERhq*sWkhGixSfPa^2{El%=vTIlOQil=533d*FalE zo|H0g2IKyT!hWqnW-Mo)mCYu@jRUp?;~sdxv+kHv_%1S?D6HgkZLB8zL&l@PL$aEh z%_is_M?gZWgDDqE9itZ`#~eq)D;{-HoM@>rTR+{{R2l9zTlhDUdai7(?%3QJ-@;ax zx~Xn$(q4$CKu}2p3bNTG!`I^=VH8SC(Sd%aDtu3z5xH8D_nwP`ok1&BFp)fKr&3UUIQQXm>e@55V>n@Imn@iWYqG!#1dJiuxK_LzXK?}QC1-5v-y02#7DRP8N!QQ$$Y1ZEL-9*E=JFS&y ziK$8aQq0qe;d@!8|Zm@K)nFdnZ!2|U>4U?v#()MPrKQk{vGL)?;BM^OyB(we{w?a3e=o@7as-kI*$W31+IoLHR`ap^SoktidHZ1JQd z4>OEKM9xAVaT3m{)l3B6ob>q(RJR!!2vl^>MF)2$P_WhrigKGAA6qVrOzu7OC7)fw zKQFg>n)>RYb_+g`cq6!svKXP7rp3sLXS&zXkj$dlmntZFzaLe!Lio(GZi8dL(20zV z!%pHv%8D_pSObDZtQ0>x3ia6zr8}8vR$OCHIS~`;CQ64*GM5`l5lk}sWi65##V9ZN zLDMyk!i1(}@NTtrH%QJ4h~5^y=CB*_zmChYraw=D4k8^Uqm*zkNj-5Cl+d77PkFU# zmGP+0NM%a0Jaq2F)cCzNhLMqpHe=(v)|rs}97hAx&V}m2 znk#7yxTM?@>k&#dC?bWrLK#_3Y+(zu=@6jJ5_3A=m8#P<+YLd?)n4Ti8$!~6^5!o7KnkJ@&IsApzu>Q@qv01&L$4^B27bP5Qcaor2Z?b+!W^ z)d8J5h7E@dq{T2HSpxCu0$-L(S!EJ-U`LA!CF&zf5GFXFa*kAX&O>Ecj}SnMlfwqL z^J|QE+2`luVzb~ROGHs;;xR+4H^})pwfSaIz%Px9h2#_7}`6{_*8^=J6#j#r|C;Bz`Gst54i{1 z%;dzb6}4(LijNS~S)3S25sumb82QEX3T;S0*gtF0MU(DSpFg&ioR4_IDm36zp4mn+ zfLr9~Z&&P-aRoIhb#9|4P|ha~T$^-5nysEdoV`}U+|!(X#&lR?n-)loh&z^~7&W#Y zc8Twhl(P{z4MO#xa#HRnME1rsk=)|6Ph=q64%zm~#BW>gjKW!ROfqOq0!5J^r+zsA zg>fr2lCG5n5n*9-faQZB(twhl5F|0}hJ)0#mx{hTuyg2zschEqj^)=P*y2;9>7zrhntZtZd%)Q)2c9T6K@t*|QD+tL5FzAjy zvYv>haxJ-gi83VtcCcpa;*|! zC{%PO5cFghQ7H#1<531(57CW=J^VIhXiF+I$C7|2ZgsLLDJD7U>UI^pQuND^C~J+k zp1Tl!_LPCf8o+olQ7hprmvQz}xAuS!KIt6P45q^{giyrgb>$%VIGK#3P2h9c)((?a zmeg&oif%F(x7jOVb$z3l$V554?c4-C(`{SoQ%T;Gd$yMZSwNO%gzHl%6l`Kad#2qV zl`Y)?ing_w-FBxRLi^ICx00ptLX(Cz<6g?S&fD_Ysqlv}h07x?uQ?%JBD^`1ZElRk9xv_IVw1qHi=&+rGXs`vi6GxFoEtZf; z9bC+_S-_-t!q$M{I94Du;pQMiKPQH*E_xg2?Kr*=oh-A1U7f??sYA-SE$8+_<4H19 ziY50XR#m*+u&ZU2rQHMd4#!sN^!poPDEhLZ#krYF4{;=E#NNj$kpg8aUsH-;Y2uTF zD94@V*t(L$!5fh0ZP5#uMF!_Bq6OGB3O&m;r10Cu^6q|&m$T5lZZOR?0In=0QC1xzU1b+(ds&m`E5{-AA$d*ay5#KXRAVW6ROI z1>VHyu{ns`awo>ZG#RtI`jX=p(+<~;LlGk~kzn|&@+mQt?6WwRV^F3U!;zInxkMJ~ zB_*wtG=6Ea`$EBV^(NGebgiXx6OyeAgpJB*mJ7yJDKgM$D+PGK=8AeqHnwTDV-8_( zCe+;*3*!@th;-=|1rAhPQz@86w4Y9D`4u6v7g8q^9&~POz{A@m+gi{HpIsJ|f5@wsdlMpgXxCFIU zI`NX0U4=H8bvGutLm0-ZY`ud6zR4|eNNiEpIp7xX{QVr$a$mp)!NvGR|1cQJq}@f@ zlm?+qViCDJSK$`nxM&hiDEgrqhccvdhh-O~&#Nqs2LDTsq~|+pRoOsEKFq8%>@0QI zmv>=I=|GBOiVbe}+@}sx9vZz@wkI_1)qdIR)mIhZ`__w({YQ}rz~Q{MM^>>ZagPd!|sd) zW_(UxH24{g(^b=JAmHFYtDJ?Qy&Qg{^2n5YiHUDO87;^tWgv z)rBs_-;&&?J9Jepu|ZoG;}_XNMkc*#0t&`Mm*Jm8BVX8Bk^o^2S3InD<~E3$-3iTE zOUrcLNv>U@-;x`|9p0#drEsk~Amq0IM0Sl3M&nV8{-u4B zGsRv9&Pa?G6q=rl!VB%!Z3#0Rq<3ff1Gfm*dI!qi*qG%*1q8%rXN*lr8k16IG+g35G@=J4)DAg@wZ2->uj7hCtzlT3 zEmS!V?M`<4E}c3_oqF~+0}?{WNf?dB-FYYOtSLJaNJ$ zFd_$cLThe8L9n53hY%E?eU%8`);Z`L$LP#hAI;4;;Y z9_dXpEE!MQf^_GG8%=IXh!Yt)5hTg4yVE$1iUW8npriYz$jV8c*yy_?;r(JJ0kZId zm`XR7*-?pz80D!*}n?y3KRc*WgUKrQSJ(-6=nQwI!iV=}W{-Qyv4h-DY`- z&d<@<-nQWmk?2V>$$`mXNKWj?#mgv-5}L?GNzar*RUZiHacaLe82s+I-KGntckE=W zZDV4hKN1|nXrAlQ1(7(5H!UKBa}?;hu>JrSb&@1o-J z$}mr!jGa zMbC1_G?%-$>E%-D21y}v)%6=kQP}#=MhU)X4^3SAEWcyzLZSeZhpqDowkYI5a$SYc z6o$qIYPy|A29O^79ns*2L3p7K7Is$442kCCYO*~!Cq3vX8o6@dl$7h*UjhsSOe^jz zmhSb@S#J`vjrHPmaX`gW^p`Zl7x7h0ZV;(S2GF@IM543hvE1DyyP4Yvx`tad7m4*} zrepq1d0Z3nZv2U>WjjgZe02*keL(%mGa&;ttdoN;Lb^6da&iA7T=5K3bnLv|WeCD` zf_~K|y|}D~%W$~eiQuhT0T0a}60fFy?NceOjsv98?i_e{f@g&`L?plGb2k7kC_IZYY1 z+wavBx@B1>6t96s=L|RoD-}r_OfuI*ok1K~6cwqadR`pN1qLuZl7cQNJS&45X zxi%wC>eUy`uI%s-R>}60`>E+?>C+i^E?&rJLn|~^S6kp)6_~51hRa+AM7+1)^U8|( zTa%7uG~L7n{m`f+r?Qb&{90L?8f0kegrY} zts07#$J(_S7BYO*gNAxgFtM2IED-1g6d{HPbkOyFZz|!Jt+Ss7QW&o@h4LvhE9>pt z3iU}@jrazMPo28;gz*B4B&n4#;UI;!-0qj`V+@q>82beLK9=Zr>SPY##+x#Fnv{PG z(DQZr?(-6MJ^l6h(5K0P^3;}ZAdbwjTRMQAS}q;~qm}r0MrcGbpgdtxZEuBT#Y(Sp z*S#DAc~a>nvIwxe+!Li&)>V%Vktvto1(#CXK(5~f{8~q!iU^>z>kbb#t7GmiZDNVE zQc1r`1=-@3#}DNkU{}r#y8IePqWkvO)BHVU9a}r2qM{KGMzv0g`#Rj~;OP&8_I+@NJSksCLidZ4VpgB;l0wz+i7e`qC4Vwl^3sJ-8Hy5RQa+uWgq1E`E9c z`DUX;gl9y3jE+iIF39fpw^jKovx$0=r=R7fi%O3?iXDc+2id!lX|Lx%x)8^`dBNLV zRi340t2t^{r^N!#D`|-y^#rY?6+@GD_d~XF93uuN$2SrgPMUG7l6GC@@}l%kmZw7) zMif2oa+2~71Cd2D8#aS>E)+%7j{1CoN}`Z<$u<7ak~*(`pRqU*?72SU6)=T>J}VzX zm^5X%!xQQ!Z^ftD(uOLFG3SvV$9sj-?ZueUj>O5dkXSiEWlK`E-FA{e5tV-P;r5Yc z`@LR6r=dr=h`sh}#M!bE>o}7TvMMHqb{qpkrH*Euw^L74o<|Eki;~hq24S1LFH%$| zMo8fUiBPX-rJ|GJ7L7)EWGkYwxcFLf?_D%T`0TY9>peE`;-9dy+Xjz$*FN45+c^8E zu|A8b_C;+c-Z|!}-sJpAPn=je*RQFiG!C95&qw?AqOEH!>1DN$?rnpPJK`E8S6D&G zw0t?nloL3t5Z+50mL&%h(KL8Y2Lhb|@Ju{70xDScbt-RLH5r`TVs%Dh8p|DK3ZmlI zBA6Jpmtp52Oy0GsCoO!U&pmYI)rIpg`UoeACwgbOL?3KIuCQ!}IGY_(5uy|hI;eka zVjsL4OD>Rej6zhMKQ>YxPxS+eQ?)lfNmFfePdR!l{^`1RiCjOyuK8?A^b4$eua2dC z0=Rf9D4Z;`XEsF6+?^_2%rHh#W=Vy}h0eI0t}0smnZ9VpBBOW{KD~C=bk?Y>4aMLYS;EDm-QIjgMk_b~ckxLXU{!^q{CvA@PpVAIbAoNF7 zG6gx^C|;4XR>c1`As{ZP*G+b?olS27v&_ei*U1h zWx(-FXaJ98gFHL1mMAQI6X{AUr_IW~5HsR6`GAy~R@DT<6j?EO_Ojg;mFd)&-?cE@ zp-VUG2%a#2*e}P#WCxv<9(W5R8Z}y#$YX$x7U7kST+&krZZAn=x3F!#i1&P){dk@cusQNMcooR_)8>y?6codc-)dvs@uOYjtlZ0I^Z~O)_hmI~~FK5fIe_bG@ z1GR<(TF{sm;bLy~HPx=jGm!(2U4-GNOKcyua^ou){5h-r?3#(gP0Y|=4eY&($ zbXZ1~Wxxpr>zM2M%kz!#By{d>&$x!oG#y!Onk8}9pnM;xRGaP-YRH{WNOP(jrcfnE+4$1e~?6+(PgA$)ao9clA^c0C{AG0@Fw zZ7J4xmJJLZ)9djUUtG$d@KlpRKHei#)II`Qwwm)ZoHlPNr=3V)o_Pkk=Wm%kVxA-CBmFC#2u8b0WwB(}_{e7`f|55KCa zh`q^p2c^pVv)i^Y^3nLUXk>qr-o3|dF?2&81pl;!_M}!=o&vKp?_)l>ux{HC(P+mb zvV(Xi<+bBYjN*Qd-;@fiCUq<;&Aqxrr44xg9;{t5Wp2GnO zotemmEQk9eOF8p#*&g-r!o3{UTbb89Ln!s!GRdV4&4yV`E0ikixH@+2*Wf$UEC$C| z_B}UjUgmu{6;gQu)CJOEf^wHg_qUUWAhZ!N6MZZ$meCyr7eO;z@)rnFTmBjgY9~fC zDtBT-lKt*mcj=EjF&9KgM?`&^ko;drNdb;p8Sm2?$rBo)^W+b|^*SOP-pe4RB!4Hb z_!MhjL@zmL^DYuA$f135SjBCO&|-I2u`#*|ug9{_oZj(M3URB)rU6}Yip>d0lDjjN zkSG~7I1XM5Bu!LM0S~#zLC^L%MaoV$S9xSt+ANz;CIl~Tol{WfV8O7viT=QAt2fF9 ztfnj2zcQCE6(3hg<;dQJOH)pKA;_AtC`N34z`U(=j-0~NogFe$aty4HLJzf(jG%>D$bZ9{k=^ z&=h92iE-y(&D4>z7;r(sXKuD^O4%=KP=umFOlL9_xm)QeBa_mzo8#^zPhzzSPYUTl zd~+yOuwAx^t*jX3)H)En6(941*!=aC(1G8g;m%YvoQ4{>rSiN`VT6esE+bGVjHF0* zCC(_tZ|2z`DV1bwLBr??LwmJC*OqmQXr0K0Z=*jQ z_TP{yybU3L<;?JLxNB;B_#g}N=ad3!{}lWq4$ii@u?AFO3q62OlI9Y4waQRnZXUz|c` zPy4b!CvvZ1N2HDPq$=U_qmzx$aK z+X&qiznXO{7C`UfG8K!dr)gHZ)|GFDg4%&!Vkt^=u?s9Ec6|fvmp6dAx&g3@E8oo8 z3TSAZhm{RmqB`6NI6p8gb+*)f$@mkXlaune^irMsQnp6g+}D#oM7-2J62p^bJZ2a{ zy-pB{Mn{Py0;0Sb9e$7D>qY?O5Wb^b!%yFA_WS;KB#86)|7W-gL)jr&wtG>k4XFPe z$NvUA%7=Czm1XzH2mfEdTLB#KHXWP|ZF+H*9oP$4S+>ysJjURST$T-uyg$pnvO6^x z@J{!5QgYN&_nw(uJ>R$B{t0*+J>CNTz3=IJ&%E#G`LQp-40snAyobPhXb!w7gZC(S zkIsSjL4&ssynWyu$hYuc==TeJkU7Zso&xWwIoi9|;9dRmd(XUj#o+n=lfm2b>wC}K zbJ}3MfAe_K_pRW~MZf*OC*E&NztY~VbM$)v9ftWn^c(1W`r!3A#NyH3Lvyrul*f}c zrMDH+JoI`yG(mmfp^ujsC0zXbpHi9Uu*Hccdz0tTpX}mUjlvH;E5iR_7)k!g!XPWc%p{{ z@6gm-T#qk-C!>-7AEbxENbmYR@$NPKN_*1pvH|_xZ}1-ScsdA=8|Lvt)9)bt62|xM zroBhdL(=b>0sTH<+8boILVNRI_{e|gD{0UE7x12K@Rq%QwC4;+Fbp^b@?f?7}C1PrT20JlF>RVE>sGCbf8F3^*X=(uJ9mC|^=U#m z_g|RPy&f;h1b)+H0f~RZ*zX6A|7(S!%fLH603J`kM}2#t=vMHyzcN5+ZJy}EI|OBa z#oB`+Vp!h=EPD7Yg&+LwqU?#kNngUR=k(#d=ko_=BexwetGyTX;XP72G`p6lI{X)S z>=hm_(B;zqb!hgn1);Y@my`S2d+|R$KdXpP`~O0Xp+3ATzkPT%vn609x(I%%4RGWU z+4eurve)tR#}vx=4&nbr{2^idZ~JGC$kx6sf{|v=;giMt=qp~Bohyy_|HAnGAJcgu AQvd(} literal 0 HcmV?d00001 diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld index fefad99c3d..48952989e1 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld @@ -1,7 +1,7 @@ -/* ROM function interface esp32b1z.rom.ld for esp32b1z +/* ROM function interface esp32h2.rom.ld for esp32h2 * * - * Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6 + * Generated from ./interface-esp32h2.yml md5sum 47e064f8d2b991d372a72a89ab7d47d3 * * Compatible with ROM where ECO version equal or greater to 0. * @@ -15,45 +15,44 @@ /* Functions */ rtc_get_reset_reason = 0x40000018; analog_super_wdt_reset_happened = 0x4000001c; -jtag_cpu_reset_happened = 0x40000020; -rtc_get_wakeup_cause = 0x40000024; -rtc_select_apb_bridge = 0x40000028; -rtc_unhold_all_pads = 0x4000002c; -ets_is_print_boot = 0x40000030; -ets_printf = 0x40000034; -ets_install_putc1 = 0x40000038; -ets_install_uart_printf = 0x4000003c; -ets_install_putc2 = 0x40000040; -PROVIDE( ets_delay_us = 0x40000044 ); -ets_get_stack_info = 0x40000048; -ets_install_lock = 0x4000004c; -ets_backup_dma_copy = 0x40000050; -ets_apb_backup_init_lock_func = 0x40000054; -UartRxString = 0x40000058; -uart_tx_one_char = 0x4000005c; -uart_tx_one_char2 = 0x40000060; -uart_rx_one_char = 0x40000064; -uart_rx_one_char_block = 0x40000068; -uart_rx_readbuff = 0x4000006c; -uartAttach = 0x40000070; -uart_tx_flush = 0x40000074; -uart_tx_wait_idle = 0x40000078; -uart_div_modify = 0x4000007c; -multofup = 0x40000080; -software_reset = 0x40000084; -software_reset_cpu = 0x40000088; -assist_debug_clock_enable = 0x4000008c; -assist_debug_record_enable = 0x40000090; -clear_super_wdt_reset_flag = 0x40000094; -disable_default_watchdog = 0x40000098; -esp_rom_set_rtc_wake_addr = 0x4000009c; -esp_rom_get_rtc_wake_addr = 0x400000a0; -send_packet = 0x400000a4; -recv_packet = 0x400000a8; -GetUartDevice = 0x400000ac; -UartDwnLdProc = 0x400000b0; -Uart_Init = 0x400000b4; -ets_set_user_start = 0x400000b8; +rtc_get_wakeup_cause = 0x40000020; +rtc_select_apb_bridge = 0x40000024; +rtc_unhold_all_pads = 0x40000028; +ets_is_print_boot = 0x4000002c; +ets_printf = 0x40000030; +ets_install_putc1 = 0x40000034; +ets_install_uart_printf = 0x40000038; +ets_install_putc2 = 0x4000003c; +PROVIDE( ets_delay_us = 0x40000040 ); +ets_get_stack_info = 0x40000044; +ets_install_lock = 0x40000048; +ets_backup_dma_copy = 0x4000004c; +ets_apb_backup_init_lock_func = 0x40000050; +UartRxString = 0x40000054; +uart_tx_one_char = 0x40000058; +uart_tx_one_char2 = 0x4000005c; +uart_rx_one_char = 0x40000060; +uart_rx_one_char_block = 0x40000064; +uart_rx_readbuff = 0x40000068; +uartAttach = 0x4000006c; +uart_tx_flush = 0x40000070; +uart_tx_wait_idle = 0x40000074; +uart_div_modify = 0x40000078; +multofup = 0x4000007c; +software_reset = 0x40000080; +software_reset_cpu = 0x40000084; +assist_debug_clock_enable = 0x40000088; +assist_debug_record_enable = 0x4000008c; +clear_super_wdt_reset_flag = 0x40000090; +disable_default_watchdog = 0x40000094; +esp_rom_set_rtc_wake_addr = 0x40000098; +esp_rom_get_rtc_wake_addr = 0x4000009c; +send_packet = 0x400000a0; +recv_packet = 0x400000a4; +GetUartDevice = 0x400000a8; +UartDwnLdProc = 0x400000ac; +Uart_Init = 0x400000b0; +ets_set_user_start = 0x400000b4; /* Data (.data, .bss, .rodata) */ ets_rom_layout_p = 0x3ff1fffc; ets_ops_table_ptr = 0x3fcdfffc; @@ -64,23 +63,22 @@ ets_ops_table_ptr = 0x3fcdfffc; ***************************************/ /* Functions */ -mz_adler32 = 0x400000bc; -mz_crc32 = 0x400000c0; -mz_free = 0x400000c4; -tdefl_compress = 0x400000c8; -tdefl_compress_buffer = 0x400000cc; -tdefl_compress_mem_to_heap = 0x400000d0; -tdefl_compress_mem_to_mem = 0x400000d4; -tdefl_compress_mem_to_output = 0x400000d8; -tdefl_get_adler32 = 0x400000dc; -tdefl_get_prev_return_status = 0x400000e0; -tdefl_init = 0x400000e4; -tdefl_write_image_to_png_file_in_memory = 0x400000e8; -tdefl_write_image_to_png_file_in_memory_ex = 0x400000ec; -tinfl_decompress = 0x400000f0; -tinfl_decompress_mem_to_callback = 0x400000f4; -tinfl_decompress_mem_to_heap = 0x400000f8; -tinfl_decompress_mem_to_mem = 0x400000fc; +mz_adler32 = 0x400000b8; +mz_free = 0x400000bc; +tdefl_compress = 0x400000c0; +tdefl_compress_buffer = 0x400000c4; +tdefl_compress_mem_to_heap = 0x400000c8; +tdefl_compress_mem_to_mem = 0x400000cc; +tdefl_compress_mem_to_output = 0x400000d0; +tdefl_get_adler32 = 0x400000d4; +tdefl_get_prev_return_status = 0x400000d8; +tdefl_init = 0x400000dc; +tdefl_write_image_to_png_file_in_memory = 0x400000e0; +tdefl_write_image_to_png_file_in_memory_ex = 0x400000e4; +tinfl_decompress = 0x400000e8; +tinfl_decompress_mem_to_callback = 0x400000ec; +tinfl_decompress_mem_to_heap = 0x400000f0; +tinfl_decompress_mem_to_mem = 0x400000f4; /*************************************** @@ -88,16 +86,8 @@ tinfl_decompress_mem_to_mem = 0x400000fc; ***************************************/ /* Functions */ -PROVIDE( jd_prepare = 0x40000100 ); -PROVIDE( jd_decomp = 0x40000104 ); - - -/*************************************** - Group esp-dsp - ***************************************/ - -/* Data (.data, .bss, .rodata) */ -dsps_fft2r_w_table_fc32_1024 = 0x3fcdfff8; +jd_prepare = 0x400000f8; +jd_decomp = 0x400000fc; /*************************************** @@ -105,82 +95,73 @@ dsps_fft2r_w_table_fc32_1024 = 0x3fcdfff8; ***************************************/ /* Functions */ -PROVIDE( esp_rom_spiflash_wait_idle = 0x40000108 ); -PROVIDE( esp_rom_spiflash_write_encrypted = 0x4000010c ); -PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000110 ); -PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000114 ); -PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x40000118 ); -PROVIDE( esp_rom_spiflash_erase_chip = 0x4000011c ); -PROVIDE( esp_rom_spiflash_erase_block = 0x40000120 ); -PROVIDE( esp_rom_spiflash_erase_sector = 0x40000124 ); -PROVIDE( esp_rom_spiflash_write = 0x40000128 ); -PROVIDE( esp_rom_spiflash_read = 0x4000012c ); -PROVIDE( esp_rom_spiflash_config_param = 0x40000130 ); -PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000134 ); -PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000138 ); -PROVIDE( esp_rom_spiflash_unlock = 0x4000013c ); -PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000140 ); -PROVIDE( esp_rom_spi_flash_send_resume = 0x40000144 ); -PROVIDE( esp_rom_spi_flash_update_id = 0x40000148 ); -PROVIDE( esp_rom_spiflash_config_clk = 0x4000014c ); -PROVIDE( esp_rom_spiflash_config_readmode = 0x40000150 ); -PROVIDE( esp_rom_spiflash_read_status = 0x40000154 ); -PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000158 ); -PROVIDE( esp_rom_spiflash_write_status = 0x4000015c ); -PROVIDE( spi_flash_attach = 0x40000160 ); -PROVIDE( spi_flash_get_chip_size = 0x40000164 ); -PROVIDE( spi_flash_guard_set = 0x40000168 ); -PROVIDE( spi_flash_guard_get = 0x4000016c ); -PROVIDE( spi_flash_write_config_set = 0x40000170 ); -PROVIDE( spi_flash_write_config_get = 0x40000174 ); -PROVIDE( spi_flash_safe_write_address_func_set = 0x40000178 ); -PROVIDE( spi_flash_unlock = 0x4000017c ); -PROVIDE( spi_flash_erase_range = 0x40000180 ); -PROVIDE( spi_flash_erase_sector = 0x40000184 ); -PROVIDE( spi_flash_write = 0x40000188 ); -PROVIDE( spi_flash_read = 0x4000018c ); -PROVIDE( spi_flash_write_encrypted = 0x40000190 ); -PROVIDE( spi_flash_read_encrypted = 0x40000194 ); -PROVIDE( spi_flash_mmap_os_func_set = 0x40000198 ); -PROVIDE( spi_flash_mmap_page_num_init = 0x4000019c ); -PROVIDE( spi_flash_mmap = 0x400001a0 ); -PROVIDE( spi_flash_mmap_pages = 0x400001a4 ); -PROVIDE( spi_flash_munmap = 0x400001a8 ); -PROVIDE( spi_flash_mmap_dump = 0x400001ac ); -PROVIDE( spi_flash_check_and_flush_cache = 0x400001b0 ); -PROVIDE( spi_flash_mmap_get_free_pages = 0x400001b4 ); -PROVIDE( spi_flash_cache2phys = 0x400001b8 ); -PROVIDE( spi_flash_phys2cache = 0x400001bc ); -PROVIDE( spi_flash_disable_cache = 0x400001c0 ); -PROVIDE( spi_flash_restore_cache = 0x400001c4 ); -PROVIDE( spi_flash_cache_enabled = 0x400001c8 ); -PROVIDE( spi_flash_enable_cache = 0x400001cc ); -PROVIDE( spi_cache_mode_switch = 0x400001d0 ); -PROVIDE( spi_common_set_dummy_output = 0x400001d4 ); -PROVIDE( spi_common_set_flash_cs_timing = 0x400001d8 ); -PROVIDE( esp_enable_cache_flash_wrap = 0x400001dc ); -PROVIDE( SPIEraseArea = 0x400001e0 ); -PROVIDE( SPILock = 0x400001e4 ); -PROVIDE( SPIMasterReadModeCnfig = 0x400001e8 ); -PROVIDE( SPI_Common_Command = 0x400001ec ); -PROVIDE( SPI_WakeUp = 0x400001f0 ); -PROVIDE( SPI_block_erase = 0x400001f4 ); -PROVIDE( SPI_chip_erase = 0x400001f8 ); -PROVIDE( SPI_init = 0x400001fc ); -PROVIDE( SPI_page_program = 0x40000200 ); -PROVIDE( SPI_read_data = 0x40000204 ); -PROVIDE( SPI_sector_erase = 0x40000208 ); -PROVIDE( SPI_write_enable = 0x4000020c ); -PROVIDE( SelectSpiFunction = 0x40000210 ); -PROVIDE( SetSpiDrvs = 0x40000214 ); -PROVIDE( Wait_SPI_Idle = 0x40000218 ); -PROVIDE( spi_dummy_len_fix = 0x4000021c ); -PROVIDE( Disable_QMode = 0x40000220 ); -PROVIDE( Enable_QMode = 0x40000224 ); +PROVIDE( esp_rom_spiflash_wait_idle = 0x40000100 ); +PROVIDE( esp_rom_spiflash_write_encrypted = 0x40000104 ); +PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000108 ); +PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x4000010c ); +PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x40000110 ); +PROVIDE( esp_rom_spiflash_erase_chip = 0x40000114 ); +PROVIDE( esp_rom_spiflash_erase_block = 0x40000118 ); +PROVIDE( esp_rom_spiflash_erase_sector = 0x4000011c ); +PROVIDE( esp_rom_spiflash_write = 0x40000120 ); +PROVIDE( esp_rom_spiflash_read = 0x40000124 ); +PROVIDE( esp_rom_spiflash_config_param = 0x40000128 ); +PROVIDE( esp_rom_spiflash_read_user_cmd = 0x4000012c ); +PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000130 ); +PROVIDE( esp_rom_spiflash_unlock = 0x40000134 ); +PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000138 ); +PROVIDE( esp_rom_spi_flash_send_resume = 0x4000013c ); +PROVIDE( esp_rom_spi_flash_update_id = 0x40000140 ); +PROVIDE( esp_rom_spiflash_config_clk = 0x40000144 ); +PROVIDE( esp_rom_spiflash_config_readmode = 0x40000148 ); +PROVIDE( esp_rom_spiflash_read_status = 0x4000014c ); +PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000150 ); +PROVIDE( esp_rom_spiflash_write_status = 0x40000154 ); +PROVIDE( spi_flash_attach = 0x40000158 ); +PROVIDE( spi_flash_get_chip_size = 0x4000015c ); +PROVIDE( spi_flash_guard_set = 0x40000160 ); +PROVIDE( spi_flash_guard_get = 0x40000164 ); +PROVIDE( spi_flash_read_encrypted = 0x40000168 ); +PROVIDE( spi_flash_mmap_os_func_set = 0x4000016c ); +PROVIDE( spi_flash_mmap_page_num_init = 0x40000170 ); +PROVIDE( spi_flash_mmap = 0x40000174 ); +PROVIDE( spi_flash_mmap_pages = 0x40000178 ); +PROVIDE( spi_flash_munmap = 0x4000017c ); +PROVIDE( spi_flash_mmap_dump = 0x40000180 ); +PROVIDE( spi_flash_check_and_flush_cache = 0x40000184 ); +PROVIDE( spi_flash_mmap_get_free_pages = 0x40000188 ); +PROVIDE( spi_flash_cache2phys = 0x4000018c ); +PROVIDE( spi_flash_phys2cache = 0x40000190 ); +PROVIDE( spi_flash_disable_cache = 0x40000194 ); +PROVIDE( spi_flash_restore_cache = 0x40000198 ); +PROVIDE( spi_flash_cache_enabled = 0x4000019c ); +PROVIDE( spi_flash_enable_cache = 0x400001a0 ); +PROVIDE( spi_cache_mode_switch = 0x400001a4 ); +PROVIDE( spi_common_set_dummy_output = 0x400001a8 ); +PROVIDE( spi_common_set_flash_cs_timing = 0x400001ac ); +PROVIDE( esp_enable_cache_flash_wrap = 0x400001b0 ); +PROVIDE( SPIEraseArea = 0x400001b4 ); +PROVIDE( SPILock = 0x400001b8 ); +PROVIDE( SPIMasterReadModeCnfig = 0x400001bc ); +PROVIDE( SPI_Common_Command = 0x400001c0 ); +PROVIDE( SPI_WakeUp = 0x400001c4 ); +PROVIDE( SPI_block_erase = 0x400001c8 ); +PROVIDE( SPI_chip_erase = 0x400001cc ); +PROVIDE( SPI_init = 0x400001d0 ); +PROVIDE( SPI_page_program = 0x400001d4 ); +PROVIDE( SPI_read_data = 0x400001d8 ); +PROVIDE( SPI_sector_erase = 0x400001dc ); +PROVIDE( SPI_write_enable = 0x400001e0 ); +PROVIDE( SelectSpiFunction = 0x400001e4 ); +PROVIDE( SetSpiDrvs = 0x400001e8 ); +PROVIDE( Wait_SPI_Idle = 0x400001ec ); +PROVIDE( spi_dummy_len_fix = 0x400001f0 ); +PROVIDE( Disable_QMode = 0x400001f4 ); +PROVIDE( Enable_QMode = 0x400001f8 ); /* Data (.data, .bss, .rodata) */ -PROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff0 ); -PROVIDE( rom_spiflash_legacy_data = 0x3fcdffec ); -PROVIDE( g_flash_guard_ops = 0x3fcdfff4 ); +PROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 ); +PROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 ); +PROVIDE( g_flash_guard_ops = 0x3fcdfff8 ); /*************************************** @@ -188,17 +169,17 @@ PROVIDE( g_flash_guard_ops = 0x3fcdfff4 ); ***************************************/ /* Functions */ -PROVIDE( spi_flash_hal_poll_cmd_done = 0x40000228 ); -PROVIDE( spi_flash_hal_device_config = 0x4000022c ); -PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000230 ); -PROVIDE( spi_flash_hal_common_command = 0x40000234 ); -PROVIDE( spi_flash_hal_read = 0x40000238 ); -PROVIDE( spi_flash_hal_erase_chip = 0x4000023c ); -PROVIDE( spi_flash_hal_erase_sector = 0x40000240 ); -PROVIDE( spi_flash_hal_erase_block = 0x40000244 ); -PROVIDE( spi_flash_hal_program_page = 0x40000248 ); -PROVIDE( spi_flash_hal_set_write_protect = 0x4000024c ); -PROVIDE( spi_flash_hal_host_idle = 0x40000250 ); +PROVIDE( spi_flash_hal_poll_cmd_done = 0x400001fc ); +PROVIDE( spi_flash_hal_device_config = 0x40000200 ); +PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000204 ); +PROVIDE( spi_flash_hal_common_command = 0x40000208 ); +PROVIDE( spi_flash_hal_read = 0x4000020c ); +PROVIDE( spi_flash_hal_erase_chip = 0x40000210 ); +PROVIDE( spi_flash_hal_erase_sector = 0x40000214 ); +PROVIDE( spi_flash_hal_erase_block = 0x40000218 ); +PROVIDE( spi_flash_hal_program_page = 0x4000021c ); +PROVIDE( spi_flash_hal_set_write_protect = 0x40000220 ); +PROVIDE( spi_flash_hal_host_idle = 0x40000224 ); /*************************************** @@ -206,37 +187,38 @@ PROVIDE( spi_flash_hal_host_idle = 0x40000250 ); ***************************************/ /* Functions */ -PROVIDE( spi_flash_chip_generic_probe = 0x40000254 ); -PROVIDE( spi_flash_chip_generic_detect_size = 0x40000258 ); -PROVIDE( spi_flash_chip_generic_write = 0x4000025c ); -PROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000260 ); -PROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000264 ); -PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000268 ); -PROVIDE( spi_flash_chip_generic_reset = 0x4000026c ); -PROVIDE( spi_flash_chip_generic_erase_chip = 0x40000270 ); -PROVIDE( spi_flash_chip_generic_erase_sector = 0x40000274 ); -PROVIDE( spi_flash_chip_generic_erase_block = 0x40000278 ); -PROVIDE( spi_flash_chip_generic_page_program = 0x4000027c ); -PROVIDE( spi_flash_chip_generic_get_write_protect = 0x40000280 ); -PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x40000284 ); -PROVIDE( spi_flash_chip_generic_read_reg = 0x40000288 ); -PROVIDE( spi_flash_chip_generic_yield = 0x4000028c ); -PROVIDE( spi_flash_generic_wait_host_idle = 0x40000290 ); -PROVIDE( spi_flash_chip_generic_wait_idle = 0x40000294 ); -PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x40000298 ); -PROVIDE( spi_flash_chip_generic_read = 0x4000029c ); -PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400002a0 ); -PROVIDE( spi_flash_chip_generic_get_io_mode = 0x400002a4 ); -PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400002a8 ); -PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400002ac ); -PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400002b0 ); -PROVIDE( spi_flash_common_set_io_mode = 0x400002b4 ); -PROVIDE( spi_flash_chip_generic_set_io_mode = 0x400002b8 ); -PROVIDE( spi_flash_chip_gd_get_io_mode = 0x400002bc ); -PROVIDE( spi_flash_chip_gd_probe = 0x400002c0 ); -PROVIDE( spi_flash_chip_gd_set_io_mode = 0x400002c4 ); +PROVIDE( spi_flash_chip_generic_probe = 0x40000228 ); +PROVIDE( spi_flash_chip_generic_detect_size = 0x4000022c ); +PROVIDE( spi_flash_chip_generic_write = 0x40000230 ); +PROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000234 ); +PROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000238 ); +PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x4000023c ); +PROVIDE( spi_flash_chip_generic_reset = 0x40000240 ); +PROVIDE( spi_flash_chip_generic_erase_chip = 0x40000244 ); +PROVIDE( spi_flash_chip_generic_erase_sector = 0x40000248 ); +PROVIDE( spi_flash_chip_generic_erase_block = 0x4000024c ); +PROVIDE( spi_flash_chip_generic_page_program = 0x40000250 ); +PROVIDE( spi_flash_chip_generic_get_write_protect = 0x40000254 ); +PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x40000258 ); +PROVIDE( spi_flash_chip_generic_read_reg = 0x4000025c ); +PROVIDE( spi_flash_chip_generic_yield = 0x40000260 ); +PROVIDE( spi_flash_generic_wait_host_idle = 0x40000264 ); +PROVIDE( spi_flash_chip_generic_wait_idle = 0x40000268 ); +PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x4000026c ); +PROVIDE( spi_flash_chip_generic_read = 0x40000270 ); +PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x40000274 ); +PROVIDE( spi_flash_chip_generic_get_io_mode = 0x40000278 ); +PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x4000027c ); +PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x40000280 ); +PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x40000284 ); +PROVIDE( spi_flash_common_set_io_mode = 0x40000288 ); +PROVIDE( spi_flash_chip_generic_set_io_mode = 0x4000028c ); +PROVIDE( spi_flash_chip_gd_get_io_mode = 0x40000290 ); +PROVIDE( spi_flash_chip_gd_probe = 0x40000294 ); +PROVIDE( spi_flash_chip_gd_set_io_mode = 0x40000298 ); /* Data (.data, .bss, .rodata) */ -PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 ); +PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffec ); +PROVIDE( spi_flash_encryption = 0x3fcdffe8 ); /*************************************** @@ -244,18 +226,18 @@ PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 ); ***************************************/ /* Functions */ -PROVIDE( memspi_host_read_id_hs = 0x400002c8 ); -PROVIDE( memspi_host_read_status_hs = 0x400002cc ); -PROVIDE( memspi_host_flush_cache = 0x400002d0 ); -PROVIDE( memspi_host_erase_chip = 0x400002d4 ); -PROVIDE( memspi_host_erase_sector = 0x400002d8 ); -PROVIDE( memspi_host_erase_block = 0x400002dc ); -PROVIDE( memspi_host_program_page = 0x400002e0 ); -PROVIDE( memspi_host_read = 0x400002e4 ); -PROVIDE( memspi_host_set_write_protect = 0x400002e8 ); -PROVIDE( memspi_host_set_max_read_len = 0x400002ec ); -PROVIDE( memspi_host_read_data_slicer = 0x400002f0 ); -PROVIDE( memspi_host_write_data_slicer = 0x400002f4 ); +PROVIDE( memspi_host_read_id_hs = 0x4000029c ); +PROVIDE( memspi_host_read_status_hs = 0x400002a0 ); +PROVIDE( memspi_host_flush_cache = 0x400002a4 ); +PROVIDE( memspi_host_erase_chip = 0x400002a8 ); +PROVIDE( memspi_host_erase_sector = 0x400002ac ); +PROVIDE( memspi_host_erase_block = 0x400002b0 ); +PROVIDE( memspi_host_program_page = 0x400002b4 ); +PROVIDE( memspi_host_read = 0x400002b8 ); +PROVIDE( memspi_host_set_write_protect = 0x400002bc ); +PROVIDE( memspi_host_set_max_read_len = 0x400002c0 ); +PROVIDE( memspi_host_read_data_slicer = 0x400002c4 ); +PROVIDE( memspi_host_write_data_slicer = 0x400002c8 ); /*************************************** @@ -263,30 +245,26 @@ PROVIDE( memspi_host_write_data_slicer = 0x400002f4 ); ***************************************/ /* Functions */ -PROVIDE( esp_flash_chip_driver_initialized = 0x400002f8 ); -PROVIDE( esp_flash_read_id = 0x400002fc ); -PROVIDE( esp_flash_get_size = 0x40000300 ); -PROVIDE( esp_flash_erase_chip = 0x40000304 ); -PROVIDE( rom_esp_flash_erase_region = 0x40000308 ); -PROVIDE( esp_flash_get_chip_write_protect = 0x4000030c ); -PROVIDE( esp_flash_set_chip_write_protect = 0x40000310 ); -PROVIDE( esp_flash_get_protectable_regions = 0x40000314 ); -PROVIDE( esp_flash_get_protected_region = 0x40000318 ); -PROVIDE( esp_flash_set_protected_region = 0x4000031c ); -PROVIDE( esp_flash_read = 0x40000320 ); -PROVIDE( esp_flash_write = 0x40000324 ); -PROVIDE( esp_flash_write_encrypted = 0x40000328 ); -PROVIDE( esp_flash_read_encrypted = 0x4000032c ); -PROVIDE( esp_flash_get_io_mode = 0x40000330 ); -PROVIDE( esp_flash_set_io_mode = 0x40000334 ); -PROVIDE( spi_flash_boot_attach = 0x40000338 ); -PROVIDE( spi_flash_dump_counters = 0x4000033c ); -PROVIDE( spi_flash_get_counters = 0x40000340 ); -PROVIDE( spi_flash_op_counters_config = 0x40000344 ); -PROVIDE( spi_flash_reset_counters = 0x40000348 ); -PROVIDE( esp_flash_read_chip_id = 0x4000034c ); -PROVIDE( detect_spi_flash_chip = 0x40000350 ); -PROVIDE( esp_rom_spiflash_write_disable = 0x40000354 ); +PROVIDE( esp_flash_chip_driver_initialized = 0x400002cc ); +PROVIDE( esp_flash_read_id = 0x400002d0 ); +PROVIDE( esp_flash_get_size = 0x400002d4 ); +PROVIDE( esp_flash_erase_chip = 0x400002d8 ); +PROVIDE( esp_flash_erase_region = 0x400002dc ); +PROVIDE( esp_flash_get_chip_write_protect = 0x400002e0 ); +PROVIDE( esp_flash_set_chip_write_protect = 0x400002e4 ); +PROVIDE( esp_flash_get_protectable_regions = 0x400002e8 ); +PROVIDE( esp_flash_get_protected_region = 0x400002ec ); +PROVIDE( esp_flash_set_protected_region = 0x400002f0 ); +PROVIDE( esp_flash_read = 0x400002f4 ); +PROVIDE( esp_flash_write = 0x400002f8 ); +PROVIDE( esp_flash_write_encrypted = 0x400002fc ); +PROVIDE( esp_flash_read_encrypted = 0x40000300 ); +PROVIDE( esp_flash_get_io_mode = 0x40000304 ); +PROVIDE( esp_flash_set_io_mode = 0x40000308 ); +PROVIDE( spi_flash_boot_attach = 0x4000030c ); +PROVIDE( esp_flash_read_chip_id = 0x40000310 ); +PROVIDE( detect_spi_flash_chip = 0x40000314 ); +PROVIDE( esp_rom_spiflash_write_disable = 0x40000318 ); /* Data (.data, .bss, .rodata) */ PROVIDE( esp_flash_default_chip = 0x3fcdffe4 ); PROVIDE( esp_flash_api_funcs = 0x3fcdffe0 ); @@ -297,58 +275,58 @@ PROVIDE( esp_flash_api_funcs = 0x3fcdffe0 ); ***************************************/ /* Functions */ -PROVIDE( Cache_Get_ICache_Line_Size = 0x400004b8 ); -PROVIDE( Cache_Get_Mode = 0x400004bc ); -PROVIDE( Cache_Address_Through_IBus = 0x400004c0 ); -PROVIDE( Cache_Address_Through_DBus = 0x400004c4 ); -PROVIDE( Cache_Set_Default_Mode = 0x400004c8 ); -PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400004cc ); -PROVIDE( ROM_Boot_Cache_Init = 0x400004d0 ); -PROVIDE( Cache_Invalidate_ICache_Items = 0x400004d4 ); -PROVIDE( Cache_Op_Addr = 0x400004d8 ); -PROVIDE( Cache_Invalidate_Addr = 0x400004dc ); -PROVIDE( Cache_Invalidate_ICache_All = 0x400004e0 ); -PROVIDE( Cache_Mask_All = 0x400004e4 ); -PROVIDE( Cache_UnMask_Dram0 = 0x400004e8 ); -PROVIDE( Cache_Suspend_ICache_Autoload = 0x400004ec ); -PROVIDE( Cache_Resume_ICache_Autoload = 0x400004f0 ); -PROVIDE( Cache_Start_ICache_Preload = 0x400004f4 ); -PROVIDE( Cache_ICache_Preload_Done = 0x400004f8 ); -PROVIDE( Cache_End_ICache_Preload = 0x400004fc ); -PROVIDE( Cache_Config_ICache_Autoload = 0x40000500 ); -PROVIDE( Cache_Enable_ICache_Autoload = 0x40000504 ); -PROVIDE( Cache_Disable_ICache_Autoload = 0x40000508 ); -PROVIDE( Cache_Enable_ICache_PreLock = 0x4000050c ); -PROVIDE( Cache_Disable_ICache_PreLock = 0x40000510 ); -PROVIDE( Cache_Lock_ICache_Items = 0x40000514 ); -PROVIDE( Cache_Unlock_ICache_Items = 0x40000518 ); -PROVIDE( Cache_Lock_Addr = 0x4000051c ); -PROVIDE( Cache_Unlock_Addr = 0x40000520 ); -PROVIDE( Cache_Disable_ICache = 0x40000524 ); -PROVIDE( Cache_Enable_ICache = 0x40000528 ); -PROVIDE( Cache_Suspend_ICache = 0x4000052c ); -PROVIDE( Cache_Resume_ICache = 0x40000530 ); -PROVIDE( Cache_Freeze_ICache_Enable = 0x40000534 ); -PROVIDE( Cache_Freeze_ICache_Disable = 0x40000538 ); -PROVIDE( Cache_Pms_Lock = 0x4000053c ); -PROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000540 ); -PROVIDE( Cache_Ibus_Pms_Set_Attr = 0x40000544 ); -PROVIDE( Cache_Dbus_Pms_Set_Addr = 0x40000548 ); -PROVIDE( Cache_Dbus_Pms_Set_Attr = 0x4000054c ); -PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000550 ); -PROVIDE( Cache_Get_IROM_MMU_End = 0x40000554 ); -PROVIDE( Cache_Get_DROM_MMU_End = 0x40000558 ); -PROVIDE( Cache_Owner_Init = 0x4000055c ); -PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000560 ); -PROVIDE( Cache_MMU_Init = 0x40000564 ); -PROVIDE( Cache_Ibus_MMU_Set = 0x40000568 ); -PROVIDE( Cache_Dbus_MMU_Set = 0x4000056c ); -PROVIDE( Cache_Count_Flash_Pages = 0x40000570 ); -PROVIDE( Cache_Travel_Tag_Memory = 0x40000574 ); -PROVIDE( Cache_Get_Virtual_Addr = 0x40000578 ); -PROVIDE( Cache_Get_Memory_BaseAddr = 0x4000057c ); -PROVIDE( Cache_Get_Memory_Addr = 0x40000580 ); -PROVIDE( Cache_Get_Memory_value = 0x40000584 ); +PROVIDE( Cache_Get_ICache_Line_Size = 0x4000047c ); +PROVIDE( Cache_Get_Mode = 0x40000480 ); +PROVIDE( Cache_Address_Through_IBus = 0x40000484 ); +PROVIDE( Cache_Address_Through_DBus = 0x40000488 ); +PROVIDE( Cache_Set_Default_Mode = 0x4000048c ); +PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x40000490 ); +PROVIDE( ROM_Boot_Cache_Init = 0x40000494 ); +PROVIDE( Cache_Invalidate_ICache_Items = 0x40000498 ); +PROVIDE( Cache_Op_Addr = 0x4000049c ); +PROVIDE( Cache_Invalidate_Addr = 0x400004a0 ); +PROVIDE( Cache_Invalidate_ICache_All = 0x400004a4 ); +PROVIDE( Cache_Mask_All = 0x400004a8 ); +PROVIDE( Cache_UnMask_Dram0 = 0x400004ac ); +PROVIDE( Cache_Suspend_ICache_Autoload = 0x400004b0 ); +PROVIDE( Cache_Resume_ICache_Autoload = 0x400004b4 ); +PROVIDE( Cache_Start_ICache_Preload = 0x400004b8 ); +PROVIDE( Cache_ICache_Preload_Done = 0x400004bc ); +PROVIDE( Cache_End_ICache_Preload = 0x400004c0 ); +PROVIDE( Cache_Config_ICache_Autoload = 0x400004c4 ); +PROVIDE( Cache_Enable_ICache_Autoload = 0x400004c8 ); +PROVIDE( Cache_Disable_ICache_Autoload = 0x400004cc ); +PROVIDE( Cache_Enable_ICache_PreLock = 0x400004d0 ); +PROVIDE( Cache_Disable_ICache_PreLock = 0x400004d4 ); +PROVIDE( Cache_Lock_ICache_Items = 0x400004d8 ); +PROVIDE( Cache_Unlock_ICache_Items = 0x400004dc ); +PROVIDE( Cache_Lock_Addr = 0x400004e0 ); +PROVIDE( Cache_Unlock_Addr = 0x400004e4 ); +PROVIDE( Cache_Disable_ICache = 0x400004e8 ); +PROVIDE( Cache_Enable_ICache = 0x400004ec ); +PROVIDE( Cache_Suspend_ICache = 0x400004f0 ); +PROVIDE( Cache_Resume_ICache = 0x400004f4 ); +PROVIDE( Cache_Freeze_ICache_Enable = 0x400004f8 ); +PROVIDE( Cache_Freeze_ICache_Disable = 0x400004fc ); +PROVIDE( Cache_Pms_Lock = 0x40000500 ); +PROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000504 ); +PROVIDE( Cache_Ibus_Pms_Set_Attr = 0x40000508 ); +PROVIDE( Cache_Dbus_Pms_Set_Addr = 0x4000050c ); +PROVIDE( Cache_Dbus_Pms_Set_Attr = 0x40000510 ); +PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000514 ); +PROVIDE( Cache_Get_IROM_MMU_End = 0x40000518 ); +PROVIDE( Cache_Get_DROM_MMU_End = 0x4000051c ); +PROVIDE( Cache_Owner_Init = 0x40000520 ); +PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000524 ); +PROVIDE( Cache_MMU_Init = 0x40000528 ); +PROVIDE( Cache_Ibus_MMU_Set = 0x4000052c ); +PROVIDE( Cache_Dbus_MMU_Set = 0x40000530 ); +PROVIDE( Cache_Count_Flash_Pages = 0x40000534 ); +PROVIDE( Cache_Travel_Tag_Memory = 0x40000538 ); +PROVIDE( Cache_Get_Virtual_Addr = 0x4000053c ); +PROVIDE( Cache_Get_Memory_BaseAddr = 0x40000540 ); +PROVIDE( Cache_Get_Memory_Addr = 0x40000544 ); +PROVIDE( Cache_Get_Memory_value = 0x40000548 ); /* Data (.data, .bss, .rodata) */ PROVIDE( rom_cache_op_cb = 0x3fcdffd4 ); PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffd0 ); @@ -359,13 +337,13 @@ PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffd0 ); ***************************************/ /* Functions */ -ets_get_apb_freq = 0x40000588; -ets_get_cpu_frequency = 0x4000058c; -ets_update_cpu_frequency = 0x40000590; -ets_get_printf_channel = 0x40000594; -ets_get_xtal_div = 0x40000598; -ets_set_xtal_div = 0x4000059c; -ets_get_xtal_freq = 0x400005a0; +ets_get_apb_freq = 0x4000054c; +ets_get_cpu_frequency = 0x40000550; +ets_update_cpu_frequency = 0x40000554; +ets_get_printf_channel = 0x40000558; +ets_get_xtal_div = 0x4000055c; +ets_set_xtal_div = 0x40000560; +ets_get_xtal_freq = 0x40000564; /*************************************** @@ -373,23 +351,23 @@ ets_get_xtal_freq = 0x400005a0; ***************************************/ /* Functions */ -gpio_input_get = 0x400005a4; -gpio_matrix_in = 0x400005a8; -gpio_matrix_out = 0x400005ac; -gpio_output_disable = 0x400005b0; -gpio_output_enable = 0x400005b4; -gpio_output_set = 0x400005b8; -gpio_pad_hold = 0x400005bc; -gpio_pad_input_disable = 0x400005c0; -gpio_pad_input_enable = 0x400005c4; -gpio_pad_pulldown = 0x400005c8; -gpio_pad_pullup = 0x400005cc; -gpio_pad_select_gpio = 0x400005d0; -gpio_pad_set_drv = 0x400005d4; -gpio_pad_unhold = 0x400005d8; -gpio_pin_wakeup_disable = 0x400005dc; -gpio_pin_wakeup_enable = 0x400005e0; -gpio_bypass_matrix_in = 0x400005e4; +gpio_input_get = 0x40000568; +gpio_matrix_in = 0x4000056c; +gpio_matrix_out = 0x40000570; +gpio_output_disable = 0x40000574; +gpio_output_enable = 0x40000578; +gpio_output_set = 0x4000057c; +gpio_pad_hold = 0x40000580; +gpio_pad_input_disable = 0x40000584; +gpio_pad_input_enable = 0x40000588; +gpio_pad_pulldown = 0x4000058c; +gpio_pad_pullup = 0x40000590; +gpio_pad_select_gpio = 0x40000594; +gpio_pad_set_drv = 0x40000598; +gpio_pad_unhold = 0x4000059c; +gpio_pin_wakeup_disable = 0x400005a0; +gpio_pin_wakeup_enable = 0x400005a4; +gpio_bypass_matrix_in = 0x400005a8; /*************************************** @@ -397,18 +375,18 @@ gpio_bypass_matrix_in = 0x400005e4; ***************************************/ /* Functions */ -esprv_intc_int_set_priority = 0x400005e8; -esprv_intc_int_set_threshold = 0x400005ec; -esprv_intc_int_enable = 0x400005f0; -esprv_intc_int_disable = 0x400005f4; -esprv_intc_int_set_type = 0x400005f8; -intr_matrix_set = 0x400005fc; -ets_intr_lock = 0x40000600; -ets_intr_unlock = 0x40000604; -PROVIDE( intr_handler_set = 0x40000608 ); -ets_isr_attach = 0x4000060c; -ets_isr_mask = 0x40000610; -ets_isr_unmask = 0x40000614; +esprv_intc_int_set_priority = 0x400005ac; +esprv_intc_int_set_threshold = 0x400005b0; +esprv_intc_int_enable = 0x400005b4; +esprv_intc_int_disable = 0x400005b8; +esprv_intc_int_set_type = 0x400005bc; +intr_matrix_set = 0x400005c0; +ets_intr_lock = 0x400005c4; +ets_intr_unlock = 0x400005c8; +PROVIDE( intr_handler_set = 0x400005cc ); +ets_isr_attach = 0x400005d0; +ets_isr_mask = 0x400005d4; +ets_isr_unmask = 0x400005d8; /*************************************** @@ -416,54 +394,61 @@ ets_isr_unmask = 0x40000614; ***************************************/ /* Functions */ -md5_vector = 0x40000618; -MD5Init = 0x4000061c; -MD5Update = 0x40000620; -MD5Final = 0x40000624; -hmac_md5_vector = 0x40000628; -hmac_md5 = 0x4000062c; -crc32_le = 0x40000630; -crc32_be = 0x40000634; -crc16_le = 0x40000638; -crc16_be = 0x4000063c; -crc8_le = 0x40000640; -crc8_be = 0x40000644; -esp_crc8 = 0x40000648; -ets_sha_enable = 0x4000064c; -ets_sha_disable = 0x40000650; -ets_sha_get_state = 0x40000654; -ets_sha_init = 0x40000658; -ets_sha_process = 0x4000065c; -ets_sha_starts = 0x40000660; -ets_sha_update = 0x40000664; -ets_sha_finish = 0x40000668; -ets_sha_clone = 0x4000066c; -ets_hmac_enable = 0x40000670; -ets_hmac_disable = 0x40000674; -ets_hmac_calculate_message = 0x40000678; -ets_hmac_calculate_downstream = 0x4000067c; -ets_hmac_invalidate_downstream = 0x40000680; -ets_jtag_enable_temporarily = 0x40000684; -ets_aes_enable = 0x40000688; -ets_aes_disable = 0x4000068c; -ets_aes_setkey = 0x40000690; -ets_aes_block = 0x40000694; -ets_bigint_enable = 0x40000698; -ets_bigint_disable = 0x4000069c; -ets_bigint_multiply = 0x400006a0; -ets_bigint_modmult = 0x400006a4; -ets_bigint_modexp = 0x400006a8; -ets_bigint_wait_finish = 0x400006ac; -ets_bigint_getz = 0x400006b0; -ets_ds_enable = 0x400006b4; -ets_ds_disable = 0x400006b8; -ets_ds_start_sign = 0x400006bc; -ets_ds_is_busy = 0x400006c0; -ets_ds_finish_sign = 0x400006c4; -ets_ds_encrypt_params = 0x400006c8; -ets_aes_setkey_dec = 0x400006cc; -ets_aes_setkey_enc = 0x400006d0; -ets_mgf1_sha256 = 0x400006d4; +md5_vector = 0x400005dc; +MD5Init = 0x400005e0; +MD5Update = 0x400005e4; +MD5Final = 0x400005e8; +hmac_md5_vector = 0x400005ec; +hmac_md5 = 0x400005f0; +crc32_le = 0x400005f4; +crc32_be = 0x400005f8; +crc16_le = 0x400005fc; +crc16_be = 0x40000600; +crc8_le = 0x40000604; +crc8_be = 0x40000608; +esp_crc8 = 0x4000060c; +ets_sha_enable = 0x40000610; +ets_sha_disable = 0x40000614; +ets_sha_get_state = 0x40000618; +ets_sha_init = 0x4000061c; +ets_sha_process = 0x40000620; +ets_sha_starts = 0x40000624; +ets_sha_update = 0x40000628; +ets_sha_finish = 0x4000062c; +ets_sha_clone = 0x40000630; +ets_hmac_enable = 0x40000634; +ets_hmac_disable = 0x40000638; +ets_hmac_calculate_message = 0x4000063c; +ets_hmac_calculate_downstream = 0x40000640; +ets_hmac_invalidate_downstream = 0x40000644; +ets_jtag_enable_temporarily = 0x40000648; +ets_aes_enable = 0x4000064c; +ets_aes_disable = 0x40000650; +ets_aes_setkey = 0x40000654; +ets_aes_block = 0x40000658; +ets_bigint_enable = 0x4000065c; +ets_bigint_disable = 0x40000660; +ets_bigint_multiply = 0x40000664; +ets_bigint_modmult = 0x40000668; +ets_bigint_modexp = 0x4000066c; +ets_bigint_wait_finish = 0x40000670; +ets_bigint_getz = 0x40000674; +ets_ds_enable = 0x40000678; +ets_ds_disable = 0x4000067c; +ets_ds_start_sign = 0x40000680; +ets_ds_is_busy = 0x40000684; +ets_ds_finish_sign = 0x40000688; +ets_ds_encrypt_params = 0x4000068c; +ets_aes_setkey_dec = 0x40000690; +ets_aes_setkey_enc = 0x40000694; +ets_mgf1_sha256 = 0x40000698; +/* Data (.data, .bss, .rodata) */ +crc32_le_table_ptr = 0x3ff1fff8; +crc16_le_table_ptr = 0x3ff1fff4; +crc8_le_table_ptr = 0x3ff1fff0; +crc32_be_table_ptr = 0x3ff1ffec; +crc16_be_table_ptr = 0x3ff1ffe8; +crc8_be_table_ptr = 0x3ff1ffe4; /*************************************** @@ -471,38 +456,36 @@ ets_mgf1_sha256 = 0x400006d4; ***************************************/ /* Functions */ -ets_efuse_read = 0x400006d8; -ets_efuse_program = 0x400006dc; -ets_efuse_clear_program_registers = 0x400006e0; -ets_efuse_write_key = 0x400006e4; -ets_efuse_get_read_register_address = 0x400006e8; -ets_efuse_get_key_purpose = 0x400006ec; -ets_efuse_key_block_unused = 0x400006f0; -ets_efuse_find_unused_key_block = 0x400006f4; -ets_efuse_rs_calculate = 0x400006f8; -ets_efuse_count_unused_key_blocks = 0x400006fc; -ets_efuse_secure_boot_enabled = 0x40000700; -ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000704; -ets_efuse_cache_encryption_enabled = 0x40000708; -ets_efuse_download_modes_disabled = 0x4000070c; -ets_efuse_find_purpose = 0x40000710; -ets_efuse_flash_opi_5pads_power_sel_vddspi = 0x40000714; -ets_efuse_force_send_resume = 0x40000718; -ets_efuse_get_flash_delay_us = 0x4000071c; -ets_efuse_get_mac = 0x40000720; -ets_efuse_get_spiconfig = 0x40000724; -ets_efuse_usb_print_is_disabled = 0x40000728; -ets_efuse_get_uart_print_channel = 0x4000072c; -ets_efuse_get_uart_print_control = 0x40000730; -ets_efuse_get_wp_pad = 0x40000734; -ets_efuse_direct_boot_mode_disabled = 0x40000738; -ets_efuse_security_download_modes_enabled = 0x4000073c; -ets_efuse_set_timing = 0x40000740; -ets_efuse_jtag_disabled = 0x40000744; -ets_efuse_usb_download_mode_disabled = 0x40000748; -ets_efuse_usb_module_disabled = 0x4000074c; -ets_efuse_usb_device_disabled = 0x40000750; -ets_efuse_secure_boot_fast_wake_enabled = 0x40000754; +ets_efuse_read = 0x4000069c; +ets_efuse_program = 0x400006a0; +ets_efuse_clear_program_registers = 0x400006a4; +ets_efuse_write_key = 0x400006a8; +ets_efuse_get_read_register_address = 0x400006ac; +ets_efuse_get_key_purpose = 0x400006b0; +ets_efuse_key_block_unused = 0x400006b4; +ets_efuse_find_unused_key_block = 0x400006b8; +ets_efuse_rs_calculate = 0x400006bc; +ets_efuse_count_unused_key_blocks = 0x400006c0; +ets_efuse_secure_boot_enabled = 0x400006c4; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x400006c8; +ets_efuse_cache_encryption_enabled = 0x400006cc; +ets_efuse_download_modes_disabled = 0x400006d0; +ets_efuse_find_purpose = 0x400006d4; +ets_efuse_force_send_resume = 0x400006dc; +ets_efuse_get_flash_delay_us = 0x400006e0; +ets_efuse_get_mac = 0x400006e4; +ets_efuse_get_spiconfig = 0x400006e8; +ets_efuse_usb_print_is_disabled = 0x400006ec; +ets_efuse_get_uart_print_control = 0x400006f4; +ets_efuse_get_wp_pad = 0x400006f8; +ets_efuse_direct_boot_mode_disabled = 0x400006fc; +ets_efuse_security_download_modes_enabled = 0x40000700; +ets_efuse_set_timing = 0x40000704; +ets_efuse_jtag_disabled = 0x40000708; +ets_efuse_usb_download_mode_disabled = 0x4000070c; +ets_efuse_usb_module_disabled = 0x40000710; +ets_efuse_usb_device_disabled = 0x40000714; +ets_efuse_secure_boot_fast_wake_enabled = 0x40000718; /*************************************** @@ -510,12 +493,13 @@ ets_efuse_secure_boot_fast_wake_enabled = 0x40000754; ***************************************/ /* Functions */ -ets_emsa_pss_verify = 0x40000758; -ets_rsa_pss_verify = 0x4000075c; -ets_secure_boot_verify_bootloader_with_keys = 0x40000760; -ets_secure_boot_verify_signature = 0x40000764; -ets_secure_boot_read_key_digests = 0x40000768; -ets_secure_boot_revoke_public_key_digest = 0x4000076c; +ets_emsa_pss_verify = 0x4000071c; +ets_rsa_pss_verify = 0x40000720; +ets_secure_boot_verify_bootloader_with_keys = 0x40000724; +ets_secure_boot_verify_signature = 0x40000728; +ets_secure_boot_read_key_digests = 0x4000072c; +ets_secure_boot_revoke_public_key_digest = 0x40000730; +ets_ecdsa_verify = 0x40000734; /*************************************** @@ -523,10 +507,10 @@ ets_secure_boot_revoke_public_key_digest = 0x4000076c; ***************************************/ /* Functions */ -PROVIDE( usb_uart_device_rx_one_char = 0x400008d8 ); -PROVIDE( usb_uart_device_rx_one_char_block = 0x400008dc ); -PROVIDE( usb_uart_device_tx_flush = 0x400008e0 ); -PROVIDE( usb_uart_device_tx_one_char = 0x400008e4 ); +PROVIDE( usb_uart_device_rx_one_char = 0x400008a0 ); +PROVIDE( usb_uart_device_rx_one_char_block = 0x400008a4 ); +PROVIDE( usb_uart_device_tx_flush = 0x400008a8 ); +PROVIDE( usb_uart_device_tx_one_char = 0x400008ac ); /* Data (.data, .bss, .rodata) */ PROVIDE( g_uart_print = 0x3fcdffcd ); PROVIDE( g_usb_print = 0x3fcdffcc ); @@ -537,180 +521,180 @@ PROVIDE( g_usb_print = 0x3fcdffcc ); ***************************************/ /* Functions */ -phy_get_romfuncs = 0x400008e8; -rom_abs_temp = 0x400008ec; -rom_bb_bss_cbw40_dig = 0x400008f0; -rom_bb_wdg_test_en = 0x400008f4; -rom_bb_wdt_get_status = 0x400008f8; -rom_bb_wdt_int_enable = 0x400008fc; -rom_bb_wdt_rst_enable = 0x40000900; -rom_bb_wdt_timeout_clear = 0x40000904; -rom_cbw2040_cfg = 0x40000908; -rom_check_noise_floor = 0x4000090c; -rom_chip_i2c_readReg = 0x40000910; -rom_chip_i2c_writeReg = 0x40000914; -rom_correct_rf_ana_gain = 0x40000918; -rom_dc_iq_est = 0x4000091c; -rom_disable_agc = 0x40000920; -rom_en_pwdet = 0x40000924; -rom_enable_agc = 0x40000928; -rom_get_bbgain_db = 0x4000092c; -rom_get_data_sat = 0x40000930; -rom_get_i2c_read_mask = 0x40000934; -rom_get_pwctrl_correct = 0x40000938; -rom_get_rf_gain_qdb = 0x4000093c; -rom_i2c_readReg = 0x40000940; -rom_i2c_readReg_Mask = 0x40000944; -rom_i2c_writeReg = 0x40000948; -rom_i2c_writeReg_Mask = 0x4000094c; -rom_index_to_txbbgain = 0x40000950; -rom_iq_est_disable = 0x40000954; -rom_iq_est_enable = 0x40000958; -rom_linear_to_db = 0x4000095c; -rom_loopback_mode_en = 0x40000960; -rom_mhz2ieee = 0x40000964; -rom_noise_floor_auto_set = 0x40000968; -rom_pbus_debugmode = 0x4000096c; -rom_pbus_force_mode = 0x40000970; -rom_pbus_force_test = 0x40000974; -rom_pbus_rd = 0x40000978; -rom_pbus_rd_addr = 0x4000097c; -rom_pbus_rd_shift = 0x40000980; -rom_pbus_set_dco = 0x40000984; -rom_pbus_set_rxgain = 0x40000988; -rom_pbus_workmode = 0x4000098c; -rom_pbus_xpd_rx_off = 0x40000990; -rom_pbus_xpd_rx_on = 0x40000994; -rom_pbus_xpd_tx_off = 0x40000998; -rom_pbus_xpd_tx_on = 0x4000099c; -rom_phy_byte_to_word = 0x400009a0; -rom_phy_disable_cca = 0x400009a4; -rom_phy_enable_cca = 0x400009a8; -rom_phy_get_noisefloor = 0x400009ac; -rom_phy_get_rx_freq = 0x400009b0; -rom_phy_set_bbfreq_init = 0x400009b4; -rom_pow_usr = 0x400009b8; -rom_pwdet_sar2_init = 0x400009bc; -rom_read_hw_noisefloor = 0x400009c0; -rom_read_sar_dout = 0x400009c4; -rom_set_cal_rxdc = 0x400009c8; -rom_set_chan_cal_interp = 0x400009cc; -rom_set_loopback_gain = 0x400009d0; -rom_set_noise_floor = 0x400009d4; -rom_set_rxclk_en = 0x400009d8; -rom_set_tx_dig_gain = 0x400009dc; -rom_set_txcap_reg = 0x400009e0; -rom_set_txclk_en = 0x400009e4; -rom_spur_cal = 0x400009e8; -rom_spur_reg_write_one_tone = 0x400009ec; -rom_target_power_add_backoff = 0x400009f0; -rom_tx_pwctrl_bg_init = 0x400009f4; -rom_txbbgain_to_index = 0x400009f8; -rom_wifi_11g_rate_chg = 0x400009fc; -rom_write_gain_mem = 0x40000a00; -chip726_phyrom_version = 0x40000a04; -rom_disable_wifi_agc = 0x40000a08; -rom_enable_wifi_agc = 0x40000a0c; -rom_set_tx_gain_table = 0x40000a10; -rom_bt_index_to_bb = 0x40000a14; -rom_bt_bb_to_index = 0x40000a18; -rom_wr_bt_tx_atten = 0x40000a1c; -rom_wr_bt_tx_gain_mem = 0x40000a20; -rom_spur_coef_cfg = 0x40000a24; -rom_bb_bss_cbw40 = 0x40000a28; -rom_set_cca = 0x40000a2c; -rom_tx_paon_set = 0x40000a30; -rom_i2cmst_reg_init = 0x40000a34; -rom_iq_corr_enable = 0x40000a38; -rom_fe_reg_init = 0x40000a3c; -rom_agc_reg_init = 0x40000a40; -rom_bb_reg_init = 0x40000a44; -rom_mac_enable_bb = 0x40000a48; -rom_bb_wdg_cfg = 0x40000a4c; -rom_force_txon = 0x40000a50; -rom_fe_txrx_reset = 0x40000a54; -rom_set_rx_comp = 0x40000a58; -rom_set_pbus_reg = 0x40000a5c; -rom_write_chan_freq = 0x40000a60; -rom_phy_xpd_rf = 0x40000a64; -rom_set_xpd_sar = 0x40000a68; -rom_write_dac_gain2 = 0x40000a6c; -rom_rtc_sar2_init = 0x40000a70; -rom_get_target_power_offset = 0x40000a74; -rom_write_txrate_power_offset = 0x40000a78; -rom_get_rate_fcc_index = 0x40000a7c; -rom_get_rate_target_power = 0x40000a80; -rom_write_wifi_dig_gain = 0x40000a84; -rom_bt_correct_rf_ana_gain = 0x40000a88; -rom_pkdet_vol_start = 0x40000a8c; -rom_read_sar2_code = 0x40000a90; -rom_get_sar2_vol = 0x40000a94; -rom_get_pll_vol = 0x40000a98; -rom_get_phy_target_power = 0x40000a9c; -rom_temp_to_power = 0x40000aa0; -rom_phy_track_pll_cap = 0x40000aa4; -rom_phy_pwdet_always_en = 0x40000aa8; -rom_phy_pwdet_onetime_en = 0x40000aac; -rom_get_i2c_mst0_mask = 0x40000ab0; -rom_get_i2c_hostid = 0x40000ab4; -rom_enter_critical_phy = 0x40000ab8; -rom_exit_critical_phy = 0x40000abc; -rom_chip_i2c_readReg_org = 0x40000ac0; -rom_i2c_paral_set_mst0 = 0x40000ac4; -rom_i2c_paral_set_read = 0x40000ac8; -rom_i2c_paral_read = 0x40000acc; -rom_i2c_paral_write = 0x40000ad0; -rom_i2c_paral_write_num = 0x40000ad4; -rom_i2c_paral_write_mask = 0x40000ad8; -rom_bb_bss_cbw40_ana = 0x40000adc; -rom_chan_to_freq = 0x40000ae0; -rom_open_i2c_xpd = 0x40000ae4; -rom_dac_rate_set = 0x40000ae8; -rom_tsens_read_init = 0x40000aec; -rom_tsens_code_read = 0x40000af0; -rom_tsens_index_to_dac = 0x40000af4; -rom_tsens_index_to_offset = 0x40000af8; -rom_tsens_dac_cal = 0x40000afc; -rom_code_to_temp = 0x40000b00; -rom_write_pll_cap_mem = 0x40000b04; -rom_pll_correct_dcap = 0x40000b08; -rom_phy_en_hw_set_freq = 0x40000b0c; -rom_phy_dis_hw_set_freq = 0x40000b10; -rom_pll_vol_cal = 0x40000b14; -rom_wrtie_pll_cap = 0x40000b18; -rom_set_tx_gain_mem = 0x40000b1c; -rom_bt_tx_dig_gain = 0x40000b20; -rom_bt_get_tx_gain = 0x40000b24; -rom_get_chan_target_power = 0x40000b28; -rom_get_tx_gain_value = 0x40000b2c; -rom_wifi_tx_dig_gain = 0x40000b30; -rom_wifi_get_tx_gain = 0x40000b34; -rom_fe_i2c_reg_renew = 0x40000b38; -rom_wifi_agc_sat_gain = 0x40000b3c; -rom_i2c_master_reset = 0x40000b40; -rom_bt_filter_reg = 0x40000b44; -rom_phy_bbpll_cal = 0x40000b48; -rom_i2c_sar2_init_code = 0x40000b4c; -rom_phy_param_addr = 0x40000b50; -rom_phy_reg_init = 0x40000b54; -rom_set_chan_reg = 0x40000b58; -rom_phy_wakeup_init = 0x40000b5c; -rom_phy_i2c_init1 = 0x40000b60; -rom_tsens_temp_read = 0x40000b64; -rom_bt_track_pll_cap = 0x40000b68; -rom_wifi_track_pll_cap = 0x40000b6c; -rom_wifi_set_tx_gain = 0x40000b70; -rom_txpwr_cal_track = 0x40000b74; -rom_tx_pwctrl_background = 0x40000b78; -rom_bt_set_tx_gain = 0x40000b7c; -rom_noise_check_loop = 0x40000b80; -rom_phy_close_rf = 0x40000b84; -rom_phy_xpd_tsens = 0x40000b88; -rom_phy_freq_mem_backup = 0x40000b8c; -rom_phy_ant_init = 0x40000b90; -rom_bt_track_tx_power = 0x40000b94; -rom_wifi_track_tx_power = 0x40000b98; -rom_phy_dig_reg_backup = 0x40000b9c; -chip726_phyrom_version_num = 0x40000ba0; +phy_get_romfuncs = 0x400008b0; +rom_abs_temp = 0x400008b4; +rom_bb_bss_cbw40_dig = 0x400008b8; +rom_bb_wdg_test_en = 0x400008bc; +rom_bb_wdt_get_status = 0x400008c0; +rom_bb_wdt_int_enable = 0x400008c4; +rom_bb_wdt_rst_enable = 0x400008c8; +rom_bb_wdt_timeout_clear = 0x400008cc; +rom_cbw2040_cfg = 0x400008d0; +rom_check_noise_floor = 0x400008d4; +rom_chip_i2c_readReg = 0x400008d8; +rom_chip_i2c_writeReg = 0x400008dc; +rom_correct_rf_ana_gain = 0x400008e0; +rom_dc_iq_est = 0x400008e4; +rom_disable_agc = 0x400008e8; +rom_en_pwdet = 0x400008ec; +rom_enable_agc = 0x400008f0; +rom_get_bbgain_db = 0x400008f4; +rom_get_data_sat = 0x400008f8; +rom_get_i2c_read_mask = 0x400008fc; +rom_get_pwctrl_correct = 0x40000900; +rom_get_rf_gain_qdb = 0x40000904; +rom_i2c_readReg = 0x40000908; +rom_i2c_readReg_Mask = 0x4000090c; +rom_i2c_writeReg = 0x40000910; +rom_i2c_writeReg_Mask = 0x40000914; +rom_index_to_txbbgain = 0x40000918; +rom_iq_est_disable = 0x4000091c; +rom_iq_est_enable = 0x40000920; +rom_linear_to_db = 0x40000924; +rom_loopback_mode_en = 0x40000928; +rom_mhz2ieee = 0x4000092c; +rom_noise_floor_auto_set = 0x40000930; +rom_pbus_debugmode = 0x40000934; +rom_pbus_force_mode = 0x40000938; +rom_pbus_force_test = 0x4000093c; +rom_pbus_rd = 0x40000940; +rom_pbus_rd_addr = 0x40000944; +rom_pbus_rd_shift = 0x40000948; +rom_pbus_set_dco = 0x4000094c; +rom_pbus_set_rxgain = 0x40000950; +rom_pbus_workmode = 0x40000954; +rom_pbus_xpd_rx_off = 0x40000958; +rom_pbus_xpd_rx_on = 0x4000095c; +rom_pbus_xpd_tx_off = 0x40000960; +rom_pbus_xpd_tx_on = 0x40000964; +rom_phy_byte_to_word = 0x40000968; +rom_phy_disable_cca = 0x4000096c; +rom_phy_enable_cca = 0x40000970; +rom_phy_get_noisefloor = 0x40000974; +rom_phy_get_rx_freq = 0x40000978; +rom_phy_set_bbfreq_init = 0x4000097c; +rom_pow_usr = 0x40000980; +rom_pwdet_sar2_init = 0x40000984; +rom_read_hw_noisefloor = 0x40000988; +rom_read_sar_dout = 0x4000098c; +rom_set_cal_rxdc = 0x40000990; +rom_set_chan_cal_interp = 0x40000994; +rom_set_loopback_gain = 0x40000998; +rom_set_noise_floor = 0x4000099c; +rom_set_rxclk_en = 0x400009a0; +rom_set_tx_dig_gain = 0x400009a4; +rom_set_txcap_reg = 0x400009a8; +rom_set_txclk_en = 0x400009ac; +rom_spur_cal = 0x400009b0; +rom_spur_reg_write_one_tone = 0x400009b4; +rom_target_power_add_backoff = 0x400009b8; +rom_tx_pwctrl_bg_init = 0x400009bc; +rom_txbbgain_to_index = 0x400009c0; +rom_wifi_11g_rate_chg = 0x400009c4; +rom_write_gain_mem = 0x400009c8; +chip726_phyrom_version = 0x400009cc; +rom_disable_wifi_agc = 0x400009d0; +rom_enable_wifi_agc = 0x400009d4; +rom_set_tx_gain_table = 0x400009d8; +rom_bt_index_to_bb = 0x400009dc; +rom_bt_bb_to_index = 0x400009e0; +rom_wr_bt_tx_atten = 0x400009e4; +rom_wr_bt_tx_gain_mem = 0x400009e8; +rom_spur_coef_cfg = 0x400009ec; +rom_bb_bss_cbw40 = 0x400009f0; +rom_set_cca = 0x400009f4; +rom_tx_paon_set = 0x400009f8; +rom_i2cmst_reg_init = 0x400009fc; +rom_iq_corr_enable = 0x40000a00; +rom_fe_reg_init = 0x40000a04; +rom_agc_reg_init = 0x40000a08; +rom_bb_reg_init = 0x40000a0c; +rom_mac_enable_bb = 0x40000a10; +rom_bb_wdg_cfg = 0x40000a14; +rom_force_txon = 0x40000a18; +rom_fe_txrx_reset = 0x40000a1c; +rom_set_rx_comp = 0x40000a20; +rom_set_pbus_reg = 0x40000a24; +rom_write_chan_freq = 0x40000a28; +rom_phy_xpd_rf = 0x40000a2c; +rom_set_xpd_sar = 0x40000a30; +rom_write_dac_gain2 = 0x40000a34; +rom_rtc_sar2_init = 0x40000a38; +rom_get_target_power_offset = 0x40000a3c; +rom_write_txrate_power_offset = 0x40000a40; +rom_get_rate_fcc_index = 0x40000a44; +rom_get_rate_target_power = 0x40000a48; +rom_write_wifi_dig_gain = 0x40000a4c; +rom_bt_correct_rf_ana_gain = 0x40000a50; +rom_pkdet_vol_start = 0x40000a54; +rom_read_sar2_code = 0x40000a58; +rom_get_sar2_vol = 0x40000a5c; +rom_get_pll_vol = 0x40000a60; +rom_get_phy_target_power = 0x40000a64; +rom_temp_to_power = 0x40000a68; +rom_phy_track_pll_cap = 0x40000a6c; +rom_phy_pwdet_always_en = 0x40000a70; +rom_phy_pwdet_onetime_en = 0x40000a74; +rom_get_i2c_mst0_mask = 0x40000a78; +rom_get_i2c_hostid = 0x40000a7c; +rom_enter_critical_phy = 0x40000a80; +rom_exit_critical_phy = 0x40000a84; +rom_chip_i2c_readReg_org = 0x40000a88; +rom_i2c_paral_set_mst0 = 0x40000a8c; +rom_i2c_paral_set_read = 0x40000a90; +rom_i2c_paral_read = 0x40000a94; +rom_i2c_paral_write = 0x40000a98; +rom_i2c_paral_write_num = 0x40000a9c; +rom_i2c_paral_write_mask = 0x40000aa0; +rom_bb_bss_cbw40_ana = 0x40000aa4; +rom_chan_to_freq = 0x40000aa8; +rom_open_i2c_xpd = 0x40000aac; +rom_dac_rate_set = 0x40000ab0; +rom_tsens_read_init = 0x40000ab4; +rom_tsens_code_read = 0x40000ab8; +rom_tsens_index_to_dac = 0x40000abc; +rom_tsens_index_to_offset = 0x40000ac0; +rom_tsens_dac_cal = 0x40000ac4; +rom_code_to_temp = 0x40000ac8; +rom_write_pll_cap_mem = 0x40000acc; +rom_pll_correct_dcap = 0x40000ad0; +rom_phy_en_hw_set_freq = 0x40000ad4; +rom_phy_dis_hw_set_freq = 0x40000ad8; +rom_pll_vol_cal = 0x40000adc; +rom_wrtie_pll_cap = 0x40000ae0; +rom_set_tx_gain_mem = 0x40000ae4; +rom_bt_tx_dig_gain = 0x40000ae8; +rom_bt_get_tx_gain = 0x40000aec; +rom_get_chan_target_power = 0x40000af0; +rom_get_tx_gain_value = 0x40000af4; +rom_wifi_tx_dig_gain = 0x40000af8; +rom_wifi_get_tx_gain = 0x40000afc; +rom_fe_i2c_reg_renew = 0x40000b00; +rom_wifi_agc_sat_gain = 0x40000b04; +rom_i2c_master_reset = 0x40000b08; +rom_bt_filter_reg = 0x40000b0c; +rom_phy_bbpll_cal = 0x40000b10; +rom_i2c_sar2_init_code = 0x40000b14; +rom_phy_param_addr = 0x40000b18; +rom_phy_reg_init = 0x40000b1c; +rom_set_chan_reg = 0x40000b20; +rom_phy_wakeup_init = 0x40000b24; +rom_phy_i2c_init1 = 0x40000b28; +rom_tsens_temp_read = 0x40000b2c; +rom_bt_track_pll_cap = 0x40000b30; +rom_wifi_track_pll_cap = 0x40000b34; +rom_wifi_set_tx_gain = 0x40000b38; +rom_txpwr_cal_track = 0x40000b3c; +rom_tx_pwctrl_background = 0x40000b40; +rom_bt_set_tx_gain = 0x40000b44; +rom_noise_check_loop = 0x40000b48; +rom_phy_close_rf = 0x40000b4c; +rom_phy_xpd_tsens = 0x40000b50; +rom_phy_freq_mem_backup = 0x40000b54; +rom_phy_ant_init = 0x40000b58; +rom_bt_track_tx_power = 0x40000b5c; +rom_wifi_track_tx_power = 0x40000b60; +rom_phy_dig_reg_backup = 0x40000b64; +chip726_phyrom_version_num = 0x40000b68; /* Data (.data, .bss, .rodata) */ phy_param_rom = 0x3fcdffc8; diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld index d70ed55864..ac0ab55199 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld @@ -1,7 +1,7 @@ -/* ROM function interface esp32b1z.rom.libgcc.ld for esp32b1z +/* ROM function interface esp32h2.rom.libgcc.ld for esp32h2 * * - * Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6 + * Generated from ./interface-esp32h2.yml md5sum 47e064f8d2b991d372a72a89ab7d47d3 * * Compatible with ROM where ECO version equal or greater to 0. * @@ -13,93 +13,93 @@ ***************************************/ /* Functions */ -__absvdi2 = 0x40000770; -__absvsi2 = 0x40000774; -__adddf3 = 0x40000778; -__addsf3 = 0x4000077c; -__addvdi3 = 0x40000780; -__addvsi3 = 0x40000784; -__ashldi3 = 0x40000788; -__ashrdi3 = 0x4000078c; -__bswapdi2 = 0x40000790; -__bswapsi2 = 0x40000794; -__clear_cache = 0x40000798; -__clrsbdi2 = 0x4000079c; -__clrsbsi2 = 0x400007a0; -__clzdi2 = 0x400007a4; -__clzsi2 = 0x400007a8; -__cmpdi2 = 0x400007ac; -__ctzdi2 = 0x400007b0; -__ctzsi2 = 0x400007b4; -__divdc3 = 0x400007b8; -__divdf3 = 0x400007bc; -__divdi3 = 0x400007c0; -__divsc3 = 0x400007c4; -__divsf3 = 0x400007c8; -__divsi3 = 0x400007cc; -__eqdf2 = 0x400007d0; -__eqsf2 = 0x400007d4; -__extendsfdf2 = 0x400007d8; -__ffsdi2 = 0x400007dc; -__ffssi2 = 0x400007e0; -__fixdfdi = 0x400007e4; -__fixdfsi = 0x400007e8; -__fixsfdi = 0x400007ec; -__fixsfsi = 0x400007f0; -__fixunsdfsi = 0x400007f4; -__fixunssfdi = 0x400007f8; -__fixunssfsi = 0x400007fc; -__floatdidf = 0x40000800; -__floatdisf = 0x40000804; -__floatsidf = 0x40000808; -__floatsisf = 0x4000080c; -__floatundidf = 0x40000810; -__floatundisf = 0x40000814; -__floatunsidf = 0x40000818; -__floatunsisf = 0x4000081c; -__gcc_bcmp = 0x40000820; -__gedf2 = 0x40000824; -__gesf2 = 0x40000828; -__gtdf2 = 0x4000082c; -__gtsf2 = 0x40000830; -__ledf2 = 0x40000834; -__lesf2 = 0x40000838; -__lshrdi3 = 0x4000083c; -__ltdf2 = 0x40000840; -__ltsf2 = 0x40000844; -__moddi3 = 0x40000848; -__modsi3 = 0x4000084c; -__muldc3 = 0x40000850; -__muldf3 = 0x40000854; -__muldi3 = 0x40000858; -__mulsc3 = 0x4000085c; -__mulsf3 = 0x40000860; -__mulsi3 = 0x40000864; -__mulvdi3 = 0x40000868; -__mulvsi3 = 0x4000086c; -__nedf2 = 0x40000870; -__negdf2 = 0x40000874; -__negdi2 = 0x40000878; -__negsf2 = 0x4000087c; -__negvdi2 = 0x40000880; -__negvsi2 = 0x40000884; -__nesf2 = 0x40000888; -__paritysi2 = 0x4000088c; -__popcountdi2 = 0x40000890; -__popcountsi2 = 0x40000894; -__powidf2 = 0x40000898; -__powisf2 = 0x4000089c; -__subdf3 = 0x400008a0; -__subsf3 = 0x400008a4; -__subvdi3 = 0x400008a8; -__subvsi3 = 0x400008ac; -__truncdfsf2 = 0x400008b0; -__ucmpdi2 = 0x400008b4; -__udivdi3 = 0x400008b8; -__udivmoddi4 = 0x400008bc; -__udivsi3 = 0x400008c0; -__udiv_w_sdiv = 0x400008c4; -__umoddi3 = 0x400008c8; -__umodsi3 = 0x400008cc; -__unorddf2 = 0x400008d0; -__unordsf2 = 0x400008d4; +__absvdi2 = 0x40000738; +__absvsi2 = 0x4000073c; +__adddf3 = 0x40000740; +__addsf3 = 0x40000744; +__addvdi3 = 0x40000748; +__addvsi3 = 0x4000074c; +__ashldi3 = 0x40000750; +__ashrdi3 = 0x40000754; +__bswapdi2 = 0x40000758; +__bswapsi2 = 0x4000075c; +__clear_cache = 0x40000760; +__clrsbdi2 = 0x40000764; +__clrsbsi2 = 0x40000768; +__clzdi2 = 0x4000076c; +__clzsi2 = 0x40000770; +__cmpdi2 = 0x40000774; +__ctzdi2 = 0x40000778; +__ctzsi2 = 0x4000077c; +__divdc3 = 0x40000780; +__divdf3 = 0x40000784; +__divdi3 = 0x40000788; +__divsc3 = 0x4000078c; +__divsf3 = 0x40000790; +__divsi3 = 0x40000794; +__eqdf2 = 0x40000798; +__eqsf2 = 0x4000079c; +__extendsfdf2 = 0x400007a0; +__ffsdi2 = 0x400007a4; +__ffssi2 = 0x400007a8; +__fixdfdi = 0x400007ac; +__fixdfsi = 0x400007b0; +__fixsfdi = 0x400007b4; +__fixsfsi = 0x400007b8; +__fixunsdfsi = 0x400007bc; +__fixunssfdi = 0x400007c0; +__fixunssfsi = 0x400007c4; +__floatdidf = 0x400007c8; +__floatdisf = 0x400007cc; +__floatsidf = 0x400007d0; +__floatsisf = 0x400007d4; +__floatundidf = 0x400007d8; +__floatundisf = 0x400007dc; +__floatunsidf = 0x400007e0; +__floatunsisf = 0x400007e4; +__gcc_bcmp = 0x400007e8; +__gedf2 = 0x400007ec; +__gesf2 = 0x400007f0; +__gtdf2 = 0x400007f4; +__gtsf2 = 0x400007f8; +__ledf2 = 0x400007fc; +__lesf2 = 0x40000800; +__lshrdi3 = 0x40000804; +__ltdf2 = 0x40000808; +__ltsf2 = 0x4000080c; +__moddi3 = 0x40000810; +__modsi3 = 0x40000814; +__muldc3 = 0x40000818; +__muldf3 = 0x4000081c; +__muldi3 = 0x40000820; +__mulsc3 = 0x40000824; +__mulsf3 = 0x40000828; +__mulsi3 = 0x4000082c; +__mulvdi3 = 0x40000830; +__mulvsi3 = 0x40000834; +__nedf2 = 0x40000838; +__negdf2 = 0x4000083c; +__negdi2 = 0x40000840; +__negsf2 = 0x40000844; +__negvdi2 = 0x40000848; +__negvsi2 = 0x4000084c; +__nesf2 = 0x40000850; +__paritysi2 = 0x40000854; +__popcountdi2 = 0x40000858; +__popcountsi2 = 0x4000085c; +__powidf2 = 0x40000860; +__powisf2 = 0x40000864; +__subdf3 = 0x40000868; +__subsf3 = 0x4000086c; +__subvdi3 = 0x40000870; +__subvsi3 = 0x40000874; +__truncdfsf2 = 0x40000878; +__ucmpdi2 = 0x4000087c; +__udivdi3 = 0x40000880; +__udivmoddi4 = 0x40000884; +__udivsi3 = 0x40000888; +__udiv_w_sdiv = 0x4000088c; +__umoddi3 = 0x40000890; +__umodsi3 = 0x40000894; +__unorddf2 = 0x40000898; +__unordsf2 = 0x4000089c; diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld index e050b3c90c..73f10bdaf5 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld @@ -1,7 +1,7 @@ -/* ROM function interface esp32b1z.rom.newlib-nano.ld for esp32b1z +/* ROM function interface esp32h2.rom.newlib-nano.ld for esp32h2 * * - * Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6 + * Generated from ./interface-esp32h2.yml md5sum 47e064f8d2b991d372a72a89ab7d47d3 * * Compatible with ROM where ECO version equal or greater to 0. * @@ -13,15 +13,15 @@ ***************************************/ /* Functions */ -__sprint_r = 0x40000488; -_fiprintf_r = 0x4000048c; -_fprintf_r = 0x40000490; -_printf_common = 0x40000494; -_printf_i = 0x40000498; -_vfiprintf_r = 0x4000049c; -_vfprintf_r = 0x400004a0; -fiprintf = 0x400004a4; -fprintf = 0x400004a8; -printf = 0x400004ac; -vfiprintf = 0x400004b0; -vfprintf = 0x400004b4; +__sprint_r = 0x4000044c; +_fiprintf_r = 0x40000450; +_fprintf_r = 0x40000454; +_printf_common = 0x40000458; +_printf_i = 0x4000045c; +_vfiprintf_r = 0x40000460; +_vfprintf_r = 0x40000464; +fiprintf = 0x40000468; +fprintf = 0x4000046c; +printf = 0x40000470; +vfiprintf = 0x40000474; +vfprintf = 0x40000478; diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld index 7ba3b8c113..76bdf45cfb 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld @@ -1,7 +1,7 @@ -/* ROM function interface esp32b1z.rom.newlib.ld for esp32b1z +/* ROM function interface esp32h2.rom.newlib.ld for esp32h2 * * - * Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6 + * Generated from ./interface-esp32h2.yml md5sum 47e064f8d2b991d372a72a89ab7d47d3 * * Compatible with ROM where ECO version equal or greater to 0. * @@ -13,82 +13,82 @@ ***************************************/ /* Functions */ -esp_rom_newlib_init_common_mutexes = 0x40000358; -memset = 0x4000035c; -memcpy = 0x40000360; -memmove = 0x40000364; -memcmp = 0x40000368; -strcpy = 0x4000036c; -strncpy = 0x40000370; -strcmp = 0x40000374; -strncmp = 0x40000378; -strlen = 0x4000037c; -strstr = 0x40000380; -bzero = 0x40000384; -_isatty_r = 0x40000388; -sbrk = 0x4000038c; -isalnum = 0x40000390; -isalpha = 0x40000394; -isascii = 0x40000398; -isblank = 0x4000039c; -iscntrl = 0x400003a0; -isdigit = 0x400003a4; -islower = 0x400003a8; -isgraph = 0x400003ac; -isprint = 0x400003b0; -ispunct = 0x400003b4; -isspace = 0x400003b8; -isupper = 0x400003bc; -toupper = 0x400003c0; -tolower = 0x400003c4; -toascii = 0x400003c8; -memccpy = 0x400003cc; -memchr = 0x400003d0; -memrchr = 0x400003d4; -strcasecmp = 0x400003d8; -strcasestr = 0x400003dc; -strcat = 0x400003e0; -strdup = 0x400003e4; -strchr = 0x400003e8; -strcspn = 0x400003ec; -strcoll = 0x400003f0; -strlcat = 0x400003f4; -strlcpy = 0x400003f8; -strlwr = 0x400003fc; -strncasecmp = 0x40000400; -strncat = 0x40000404; -strndup = 0x40000408; -strnlen = 0x4000040c; -strrchr = 0x40000410; -strsep = 0x40000414; -strspn = 0x40000418; -strtok_r = 0x4000041c; -strupr = 0x40000420; -longjmp = 0x40000424; -setjmp = 0x40000428; -abs = 0x4000042c; -div = 0x40000430; -labs = 0x40000434; -ldiv = 0x40000438; -qsort = 0x4000043c; -rand_r = 0x40000440; -rand = 0x40000444; -srand = 0x40000448; -utoa = 0x4000044c; -itoa = 0x40000450; -atoi = 0x40000454; -atol = 0x40000458; -strtol = 0x4000045c; -strtoul = 0x40000460; -PROVIDE( fflush = 0x40000464 ); -PROVIDE( _fflush_r = 0x40000468 ); -PROVIDE( _fwalk = 0x4000046c ); -PROVIDE( _fwalk_reent = 0x40000470 ); -PROVIDE( __smakebuf_r = 0x40000474 ); -PROVIDE( __swhatbuf_r = 0x40000478 ); -PROVIDE( __swbuf_r = 0x4000047c ); -__swbuf = 0x40000480; -PROVIDE( __swsetup_r = 0x40000484 ); +esp_rom_newlib_init_common_mutexes = 0x4000031c; +memset = 0x40000320; +memcpy = 0x40000324; +memmove = 0x40000328; +memcmp = 0x4000032c; +strcpy = 0x40000330; +strncpy = 0x40000334; +strcmp = 0x40000338; +strncmp = 0x4000033c; +strlen = 0x40000340; +strstr = 0x40000344; +bzero = 0x40000348; +_isatty_r = 0x4000034c; +sbrk = 0x40000350; +isalnum = 0x40000354; +isalpha = 0x40000358; +isascii = 0x4000035c; +isblank = 0x40000360; +iscntrl = 0x40000364; +isdigit = 0x40000368; +islower = 0x4000036c; +isgraph = 0x40000370; +isprint = 0x40000374; +ispunct = 0x40000378; +isspace = 0x4000037c; +isupper = 0x40000380; +toupper = 0x40000384; +tolower = 0x40000388; +toascii = 0x4000038c; +memccpy = 0x40000390; +memchr = 0x40000394; +memrchr = 0x40000398; +strcasecmp = 0x4000039c; +strcasestr = 0x400003a0; +strcat = 0x400003a4; +strdup = 0x400003a8; +strchr = 0x400003ac; +strcspn = 0x400003b0; +strcoll = 0x400003b4; +strlcat = 0x400003b8; +strlcpy = 0x400003bc; +strlwr = 0x400003c0; +strncasecmp = 0x400003c4; +strncat = 0x400003c8; +strndup = 0x400003cc; +strnlen = 0x400003d0; +strrchr = 0x400003d4; +strsep = 0x400003d8; +strspn = 0x400003dc; +strtok_r = 0x400003e0; +strupr = 0x400003e4; +longjmp = 0x400003e8; +setjmp = 0x400003ec; +abs = 0x400003f0; +div = 0x400003f4; +labs = 0x400003f8; +ldiv = 0x400003fc; +qsort = 0x40000400; +rand_r = 0x40000404; +rand = 0x40000408; +srand = 0x4000040c; +utoa = 0x40000410; +itoa = 0x40000414; +atoi = 0x40000418; +atol = 0x4000041c; +strtol = 0x40000420; +strtoul = 0x40000424; +PROVIDE( fflush = 0x40000428 ); +PROVIDE( _fflush_r = 0x4000042c ); +PROVIDE( _fwalk = 0x40000430 ); +PROVIDE( _fwalk_reent = 0x40000434 ); +PROVIDE( __smakebuf_r = 0x40000438 ); +PROVIDE( __swhatbuf_r = 0x4000043c ); +PROVIDE( __swbuf_r = 0x40000440 ); +__swbuf = 0x40000444; +PROVIDE( __swsetup_r = 0x40000448 ); /* Data (.data, .bss, .rodata) */ syscall_table_ptr = 0x3fcdffdc; _global_impure_ptr = 0x3fcdffd8; diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld index e2fe09a6df..eb52ba15d5 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld @@ -1,4 +1,4 @@ -/* ROM version variables for esp32b1z +/* ROM version variables for esp32h2 * * These addresses should be compatible with any ROM version for this chip. * diff --git a/components/esptool_py/Kconfig.projbuild b/components/esptool_py/Kconfig.projbuild index ff47b5107c..77e369823f 100644 --- a/components/esptool_py/Kconfig.projbuild +++ b/components/esptool_py/Kconfig.projbuild @@ -2,7 +2,9 @@ menu "Serial flasher config" config ESPTOOLPY_NO_STUB bool "Disable download stub" + default "y" if IDF_TARGET="esp32h2" default "n" + help The flasher tool sends a precompiled download stub first by default. That stub allows things like compressed downloads and more. Usually you should not need to disable that feature diff --git a/components/soc/esp32h2/CMakeLists.txt b/components/soc/esp32h2/CMakeLists.txt index a59b5173c1..4984df5d65 100644 --- a/components/soc/esp32h2/CMakeLists.txt +++ b/components/soc/esp32h2/CMakeLists.txt @@ -16,4 +16,14 @@ set(srcs add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") -target_include_directories(${COMPONENT_LIB} PUBLIC . include) + +if(target STREQUAL "esp32h2") + if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1) + set(inc_file "include/soc/rev1") + elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2) + set(inc_file "include/soc/rev2") + endif() + target_include_directories(${COMPONENT_LIB} PUBLIC . include ${inc_file}) +else() + target_include_directories(${COMPONENT_LIB} PUBLIC . include) +endif() diff --git a/components/soc/esp32h2/gpio_periph.c b/components/soc/esp32h2/gpio_periph.c index f9e5a805ad..475f279b1c 100644 --- a/components/soc/esp32h2/gpio_periph.c +++ b/components/soc/esp32h2/gpio_periph.c @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/gpio_periph.h" diff --git a/components/soc/esp32h2/include/soc/assist_debug_reg.h b/components/soc/esp32h2/include/soc/rev1/assist_debug_reg.h similarity index 98% rename from components/soc/esp32h2/include/soc/assist_debug_reg.h rename to components/soc/esp32h2/include/soc/rev1/assist_debug_reg.h index 2b13d1f5f4..2b224a9b29 100644 --- a/components/soc/esp32h2/include/soc/assist_debug_reg.h +++ b/components/soc/esp32h2/include/soc/rev1/assist_debug_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_ASSIST_DEBUG_REG_H_ #define _SOC_ASSIST_DEBUG_REG_H_ diff --git a/components/soc/esp32h2/include/soc/gpio_sd_reg.h b/components/soc/esp32h2/include/soc/rev1/gpio_sd_reg.h similarity index 84% rename from components/soc/esp32h2/include/soc/gpio_sd_reg.h rename to components/soc/esp32h2/include/soc/rev1/gpio_sd_reg.h index e1293c918d..4bda01041d 100644 --- a/components/soc/esp32h2/include/soc/gpio_sd_reg.h +++ b/components/soc/esp32h2/include/soc/rev1/gpio_sd_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_GPIO_SD_REG_H_ #define _SOC_GPIO_SD_REG_H_ diff --git a/components/soc/esp32h2/include/soc/interrupt_core0_reg.h b/components/soc/esp32h2/include/soc/rev1/interrupt_core0_reg.h similarity index 98% rename from components/soc/esp32h2/include/soc/interrupt_core0_reg.h rename to components/soc/esp32h2/include/soc/rev1/interrupt_core0_reg.h index 2864335f87..dad09391be 100644 --- a/components/soc/esp32h2/include/soc/interrupt_core0_reg.h +++ b/components/soc/esp32h2/include/soc/rev1/interrupt_core0_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_INTERRUPT_CORE0_REG_H_ #define _SOC_INTERRUPT_CORE0_REG_H_ diff --git a/components/soc/esp32h2/include/soc/io_mux_reg.h b/components/soc/esp32h2/include/soc/rev1/io_mux_reg.h similarity index 94% rename from components/soc/esp32h2/include/soc/io_mux_reg.h rename to components/soc/esp32h2/include/soc/rev1/io_mux_reg.h index e9a0795167..52f2c3e147 100644 --- a/components/soc/esp32h2/include/soc/io_mux_reg.h +++ b/components/soc/esp32h2/include/soc/rev1/io_mux_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_IO_MUX_REG_H_ #define _SOC_IO_MUX_REG_H_ diff --git a/components/soc/esp32h2/include/soc/rtc_cntl_reg.h b/components/soc/esp32h2/include/soc/rev1/rtc_cntl_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/rtc_cntl_reg.h rename to components/soc/esp32h2/include/soc/rev1/rtc_cntl_reg.h index e9928e814d..7c2d09ba65 100644 --- a/components/soc/esp32h2/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32h2/include/soc/rev1/rtc_cntl_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_RTC_CNTL_REG_H_ #define _SOC_RTC_CNTL_REG_H_ diff --git a/components/soc/esp32h2/include/soc/rtc_cntl_struct.h b/components/soc/esp32h2/include/soc/rev1/rtc_cntl_struct.h similarity index 98% rename from components/soc/esp32h2/include/soc/rtc_cntl_struct.h rename to components/soc/esp32h2/include/soc/rev1/rtc_cntl_struct.h index 473f236249..bde5f625c1 100644 --- a/components/soc/esp32h2/include/soc/rtc_cntl_struct.h +++ b/components/soc/esp32h2/include/soc/rev1/rtc_cntl_struct.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_RTC_CNTL_STRUCT_H_ #define _SOC_RTC_CNTL_STRUCT_H_ #ifdef __cplusplus diff --git a/components/soc/esp32h2/include/soc/sensitive_reg.h b/components/soc/esp32h2/include/soc/rev1/sensitive_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/sensitive_reg.h rename to components/soc/esp32h2/include/soc/rev1/sensitive_reg.h index f1ee26ab8f..7248cf227d 100644 --- a/components/soc/esp32h2/include/soc/sensitive_reg.h +++ b/components/soc/esp32h2/include/soc/rev1/sensitive_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SENSITIVE_REG_H_ #define _SOC_SENSITIVE_REG_H_ diff --git a/components/soc/esp32h2/include/soc/rev2/assist_debug_reg.h b/components/soc/esp32h2/include/soc/rev2/assist_debug_reg.h new file mode 100644 index 0000000000..4bb99b76a0 --- /dev/null +++ b/components/soc/esp32h2/include/soc/rev2/assist_debug_reg.h @@ -0,0 +1,685 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _SOC_ASSIST_DEBUG_REG_H_ +#define _SOC_ASSIST_DEBUG_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0) +/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11 +/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 + +#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4) +/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11 +/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 + +#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8) +/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S 11 +/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0 + +#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xC) +/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11 +/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10) +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14) +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18) +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1C) +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20) +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24) +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28) +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2C) +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30) +/* ASSIST_DEBUG_CORE_0_AREA_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PC_M ((ASSIST_DEBUG_CORE_0_AREA_PC_V)<<(ASSIST_DEBUG_CORE_0_AREA_PC_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34) +/* ASSIST_DEBUG_CORE_0_AREA_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_SP_M ((ASSIST_DEBUG_CORE_0_AREA_SP_V)<<(ASSIST_DEBUG_CORE_0_AREA_SP_S)) +#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0 + +#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38) +/* ASSIST_DEBUG_CORE_0_SP_MIN : RW ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_MIN_M ((ASSIST_DEBUG_CORE_0_SP_MIN_V)<<(ASSIST_DEBUG_CORE_0_SP_MIN_S)) +#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3C) +/* ASSIST_DEBUG_CORE_0_SP_MAX : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_MAX_M ((ASSIST_DEBUG_CORE_0_SP_MAX_V)<<(ASSIST_DEBUG_CORE_0_SP_MAX_S)) +#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40) +/* ASSIST_DEBUG_CORE_0_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_PC_M ((ASSIST_DEBUG_CORE_0_SP_PC_V)<<(ASSIST_DEBUG_CORE_0_SP_PC_S)) +#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_PC_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44) +/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : RW ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable CPU Pdebug function, if enable, CPU will update PdebugPC.*/ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x1 +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 +/* ASSIST_DEBUG_CORE_0_RCD_RECORDEN : RW ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable recording function, if enable, assist_debug will update PdebugPC, so you +can read it.*/ +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0)) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x1 +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48) +/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4C) +/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0 + +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50) +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25 +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24 +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFF +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0xFFFFFF +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0 + +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54) +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25 +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24 +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFF +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0xFFFFFF +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0 + +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58) +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[28:25] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000F +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0xF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 25 +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (BIT(24)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 24 +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x00FFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0xFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0 + +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5C) +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0 + +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60) +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[28:25] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000F +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0xF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 25 +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (BIT(24)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 24 +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x00FFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0xFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0 + +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64) +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0 + +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68) +/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFF +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)) +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0xFFFFF +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0 + +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6C) +/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFF +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)) +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0xFFFFF +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0 + +#define ASSIST_DEBUG_LOG_SETTING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70) +/* ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE (BIT(7)) +#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M (BIT(7)) +#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V 0x1 +#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S 7 +/* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[6:3] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_LOG_MODE 0x0000000F +#define ASSIST_DEBUG_LOG_MODE_M ((ASSIST_DEBUG_LOG_MODE_V)<<(ASSIST_DEBUG_LOG_MODE_S)) +#define ASSIST_DEBUG_LOG_MODE_V 0xF +#define ASSIST_DEBUG_LOG_MODE_S 3 +/* ASSIST_DEBUG_LOG_ENA : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_LOG_ENA 0x00000007 +#define ASSIST_DEBUG_LOG_ENA_M ((ASSIST_DEBUG_LOG_ENA_V)<<(ASSIST_DEBUG_LOG_ENA_S)) +#define ASSIST_DEBUG_LOG_ENA_V 0x7 +#define ASSIST_DEBUG_LOG_ENA_S 0 + +#define ASSIST_DEBUG_LOG_DATA_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74) +/* ASSIST_DEBUG_LOG_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_LOG_DATA_0 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_DATA_0_M ((ASSIST_DEBUG_LOG_DATA_0_V)<<(ASSIST_DEBUG_LOG_DATA_0_S)) +#define ASSIST_DEBUG_LOG_DATA_0_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_DATA_0_S 0 + +#define ASSIST_DEBUG_LOG_DATA_MASK_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78) +/* ASSIST_DEBUG_LOG_DATA_SIZE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_LOG_DATA_SIZE 0x0000FFFF +#define ASSIST_DEBUG_LOG_DATA_SIZE_M ((ASSIST_DEBUG_LOG_DATA_SIZE_V)<<(ASSIST_DEBUG_LOG_DATA_SIZE_S)) +#define ASSIST_DEBUG_LOG_DATA_SIZE_V 0xFFFF +#define ASSIST_DEBUG_LOG_DATA_SIZE_S 0 + +#define ASSIST_DEBUG_LOG_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x7C) +/* ASSIST_DEBUG_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_LOG_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MIN_M ((ASSIST_DEBUG_LOG_MIN_V)<<(ASSIST_DEBUG_LOG_MIN_S)) +#define ASSIST_DEBUG_LOG_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MIN_S 0 + +#define ASSIST_DEBUG_LOG_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x80) +/* ASSIST_DEBUG_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_LOG_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MAX_M ((ASSIST_DEBUG_LOG_MAX_V)<<(ASSIST_DEBUG_LOG_MAX_S)) +#define ASSIST_DEBUG_LOG_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MAX_S 0 + +#define ASSIST_DEBUG_LOG_MEM_START_REG (DR_REG_ASSIST_DEBUG_BASE + 0x84) +/* ASSIST_DEBUG_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_LOG_MEM_START 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_START_M ((ASSIST_DEBUG_LOG_MEM_START_V)<<(ASSIST_DEBUG_LOG_MEM_START_S)) +#define ASSIST_DEBUG_LOG_MEM_START_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_START_S 0 + +#define ASSIST_DEBUG_LOG_MEM_END_REG (DR_REG_ASSIST_DEBUG_BASE + 0x88) +/* ASSIST_DEBUG_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_LOG_MEM_END 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_END_M ((ASSIST_DEBUG_LOG_MEM_END_V)<<(ASSIST_DEBUG_LOG_MEM_END_S)) +#define ASSIST_DEBUG_LOG_MEM_END_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_END_S 0 + +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8C) +/* ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V)<<(ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S)) +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S 0 + +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG (DR_REG_ASSIST_DEBUG_BASE + 0x90) +/* ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG (BIT(1)) +#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_M (BIT(1)) +#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V 0x1 +#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S 1 +/* ASSIST_DEBUG_LOG_MEM_FULL_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG (BIT(0)) +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M (BIT(0)) +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V 0x1 +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S 0 + +#define ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x94) +/* ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M ((ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V)<<(ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)) +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0 + +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x98) +/* ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x1 +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1 +/* ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x1 +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0 + +#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1FC) +/* ASSIST_DEBUG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2008010 ; */ +/*description: Need add description.*/ +#define ASSIST_DEBUG_DATE 0x0FFFFFFF +#define ASSIST_DEBUG_DATE_M ((ASSIST_DEBUG_DATE_V)<<(ASSIST_DEBUG_DATE_S)) +#define ASSIST_DEBUG_DATE_V 0xFFFFFFF +#define ASSIST_DEBUG_DATE_S 0 + + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_ASSIST_DEBUG_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/rev2/gpio_sd_reg.h b/components/soc/esp32h2/include/soc/rev2/gpio_sd_reg.h new file mode 100644 index 0000000000..a74e368e8c --- /dev/null +++ b/components/soc/esp32h2/include/soc/rev2/gpio_sd_reg.h @@ -0,0 +1,175 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _SOC_GPIO_SD_REG_H_ +#define _SOC_GPIO_SD_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0) +/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: This field is used to set a divider value to divide APB clock..*/ +#define GPIO_SD0_PRESCALE 0x000000FF +#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S)) +#define GPIO_SD0_PRESCALE_V 0xFF +#define GPIO_SD0_PRESCALE_S 8 +/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: This field is used to configure the duty cycle of sigma delta modulation output..*/ +#define GPIO_SD0_IN 0x000000FF +#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S)) +#define GPIO_SD0_IN_V 0xFF +#define GPIO_SD0_IN_S 0 + +#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x4) +/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: This field is used to set a divider value to divide APB clock..*/ +#define GPIO_SD1_PRESCALE 0x000000FF +#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S)) +#define GPIO_SD1_PRESCALE_V 0xFF +#define GPIO_SD1_PRESCALE_S 8 +/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: This field is used to configure the duty cycle of sigma delta modulation output..*/ +#define GPIO_SD1_IN 0x000000FF +#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S)) +#define GPIO_SD1_IN_V 0xFF +#define GPIO_SD1_IN_S 0 + +#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x8) +/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: This field is used to set a divider value to divide APB clock..*/ +#define GPIO_SD2_PRESCALE 0x000000FF +#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S)) +#define GPIO_SD2_PRESCALE_V 0xFF +#define GPIO_SD2_PRESCALE_S 8 +/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: This field is used to configure the duty cycle of sigma delta modulation output..*/ +#define GPIO_SD2_IN 0x000000FF +#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S)) +#define GPIO_SD2_IN_V 0xFF +#define GPIO_SD2_IN_S 0 + +#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0xC) +/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: This field is used to set a divider value to divide APB clock..*/ +#define GPIO_SD3_PRESCALE 0x000000FF +#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S)) +#define GPIO_SD3_PRESCALE_V 0xFF +#define GPIO_SD3_PRESCALE_S 8 +/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: This field is used to configure the duty cycle of sigma delta modulation output..*/ +#define GPIO_SD3_IN 0x000000FF +#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S)) +#define GPIO_SD3_IN_V 0xFF +#define GPIO_SD3_IN_S 0 + +#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x20) +/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Clock enable bit of configuration registers for sigma delta modulation..*/ +#define GPIO_SD_CLK_EN (BIT(31)) +#define GPIO_SD_CLK_EN_M (BIT(31)) +#define GPIO_SD_CLK_EN_V 0x1 +#define GPIO_SD_CLK_EN_S 31 + +#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x24) +/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Reserved..*/ +#define GPIO_SPI_SWAP (BIT(31)) +#define GPIO_SPI_SWAP_M (BIT(31)) +#define GPIO_SPI_SWAP_V 0x1 +#define GPIO_SPI_SWAP_S 31 +/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: Clock enable bit of sigma delta modulation..*/ +#define GPIO_FUNCTION_CLK_EN (BIT(30)) +#define GPIO_FUNCTION_CLK_EN_M (BIT(30)) +#define GPIO_FUNCTION_CLK_EN_V 0x1 +#define GPIO_FUNCTION_CLK_EN_S 30 + +#define GPIO_PAD_COMP_CONFIG_REG (DR_REG_GPIO_SD_BASE + 0x28) +/* GPIO_ZERO_DET_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: Zero Detect mode select..*/ +#define GPIO_ZERO_DET_MODE 0x00000003 +#define GPIO_ZERO_DET_MODE_M ((GPIO_ZERO_DET_MODE_V)<<(GPIO_ZERO_DET_MODE_S)) +#define GPIO_ZERO_DET_MODE_V 0x3 +#define GPIO_ZERO_DET_MODE_S 4 +/* GPIO_DREF_COMP : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST..*/ +#define GPIO_DREF_COMP 0x00000003 +#define GPIO_DREF_COMP_M ((GPIO_DREF_COMP_V)<<(GPIO_DREF_COMP_S)) +#define GPIO_DREF_COMP_V 0x3 +#define GPIO_DREF_COMP_S 2 +/* GPIO_MODE_COMP : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: 1 to enable external reference from PAD[0]. 0 to enable internal reference, mean +while PAD[0] can be used as a regular GPIO..*/ +#define GPIO_MODE_COMP (BIT(1)) +#define GPIO_MODE_COMP_M (BIT(1)) +#define GPIO_MODE_COMP_V 0x1 +#define GPIO_MODE_COMP_S 1 +/* GPIO_XPD_COMP : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Pad compare enable bit..*/ +#define GPIO_XPD_COMP (BIT(0)) +#define GPIO_XPD_COMP_M (BIT(0)) +#define GPIO_XPD_COMP_V 0x1 +#define GPIO_XPD_COMP_S 0 + +#define GPIO_PAD_COMP_FILTER_REG (DR_REG_GPIO_SD_BASE + 0x2C) +/* GPIO_ZERO_DET_FILTER_CNT : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Zero Detect filter cycle length.*/ +#define GPIO_ZERO_DET_FILTER_CNT 0xFFFFFFFF +#define GPIO_ZERO_DET_FILTER_CNT_M ((GPIO_ZERO_DET_FILTER_CNT_V)<<(GPIO_ZERO_DET_FILTER_CNT_S)) +#define GPIO_ZERO_DET_FILTER_CNT_V 0xFFFFFFFF +#define GPIO_ZERO_DET_FILTER_CNT_S 0 + +#define GPIO_INT_RAW_REG (DR_REG_GPIO_SD_BASE + 0x80) +/* GPIO_PAD_COMP_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Pad compare raw interrupt.*/ +#define GPIO_PAD_COMP_INT_RAW (BIT(0)) +#define GPIO_PAD_COMP_INT_RAW_M (BIT(0)) +#define GPIO_PAD_COMP_INT_RAW_V 0x1 +#define GPIO_PAD_COMP_INT_RAW_S 0 + +#define GPIO_INT_ST_REG (DR_REG_GPIO_SD_BASE + 0x84) +/* GPIO_PAD_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Pad compare masked interrupt.*/ +#define GPIO_PAD_COMP_INT_ST (BIT(0)) +#define GPIO_PAD_COMP_INT_ST_M (BIT(0)) +#define GPIO_PAD_COMP_INT_ST_V 0x1 +#define GPIO_PAD_COMP_INT_ST_S 0 + +#define GPIO_INT_ENA_REG (DR_REG_GPIO_SD_BASE + 0x88) +/* GPIO_PAD_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Pad compare interrupt enable.*/ +#define GPIO_PAD_COMP_INT_ENA (BIT(0)) +#define GPIO_PAD_COMP_INT_ENA_M (BIT(0)) +#define GPIO_PAD_COMP_INT_ENA_V 0x1 +#define GPIO_PAD_COMP_INT_ENA_S 0 + +#define GPIO_INT_CLR_REG (DR_REG_GPIO_SD_BASE + 0x8C) +/* GPIO_PAD_COMP_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Pad compare interrupt clear.*/ +#define GPIO_PAD_COMP_INT_CLR (BIT(0)) +#define GPIO_PAD_COMP_INT_CLR_M (BIT(0)) +#define GPIO_PAD_COMP_INT_CLR_V 0x1 +#define GPIO_PAD_COMP_INT_CLR_S 0 + +#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0xFC) +/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h2109250 ; */ +/*description: Version control register..*/ +#define GPIO_SD_DATE 0x0FFFFFFF +#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S)) +#define GPIO_SD_DATE_V 0xFFFFFFF +#define GPIO_SD_DATE_S 0 + + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_GPIOSD_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/rev2/interrupt_core0_reg.h b/components/soc/esp32h2/include/soc/rev2/interrupt_core0_reg.h new file mode 100644 index 0000000000..b5833d1af2 --- /dev/null +++ b/components/soc/esp32h2/include/soc/rev2/interrupt_core0_reg.h @@ -0,0 +1,920 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _SOC_INTERRUPT_CORE0_REG_H_ +#define _SOC_INTERRUPT_CORE0_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE + +#define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x000) +/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_MAC_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_MAC_INTR_MAP_M ((INTERRUPT_CORE0_MAC_INTR_MAP_V)<<(INTERRUPT_CORE0_MAC_INTR_MAP_S)) +#define INTERRUPT_CORE0_MAC_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_MAC_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x004) +/* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_MAC_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_MAC_NMI_MAP_M ((INTERRUPT_CORE0_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_MAC_NMI_MAP_S)) +#define INTERRUPT_CORE0_MAC_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_MAC_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x008) +/* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_PWR_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_PWR_INTR_MAP_M ((INTERRUPT_CORE0_PWR_INTR_MAP_V)<<(INTERRUPT_CORE0_PWR_INTR_MAP_S)) +#define INTERRUPT_CORE0_PWR_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_PWR_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x00C) +/* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_BB_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_BB_INT_MAP_M ((INTERRUPT_CORE0_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BB_INT_MAP_S)) +#define INTERRUPT_CORE0_BB_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_BB_INT_MAP_S 0 + +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10) +/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_BT_MAC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S)) +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14) +/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_BT_BB_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_BT_BB_INT_MAP_M ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S)) +#define INTERRUPT_CORE0_BT_BB_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_BT_BB_INT_MAP_S 0 + +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18) +/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S)) +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1C) +/* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_RWBT_IRQ_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBT_IRQ_MAP_S)) +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S 0 + +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20) +/* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBLE_IRQ_MAP_S)) +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S 0 + +#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24) +/* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_RWBT_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBT_NMI_MAP_M ((INTERRUPT_CORE0_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBT_NMI_MAP_S)) +#define INTERRUPT_CORE0_RWBT_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBT_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28) +/* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_RWBLE_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBLE_NMI_MAP_S)) +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2C) +/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_I2C_MST_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S)) +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30) +/* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_SLC0_INTR_MAP_M ((INTERRUPT_CORE0_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC0_INTR_MAP_S)) +#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34) +/* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_SLC1_INTR_MAP_M ((INTERRUPT_CORE0_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC1_INTR_MAP_S)) +#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38) +/* INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M ((INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V)<<(INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S)) +#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3C) +/* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INTR_MAP_S)) +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40) +/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x1F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 + +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44) +/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48) +/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_SPI_INTR_1_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S)) +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S 0 + +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4C) +/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_SPI_INTR_2_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S)) +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0 + +#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50) +/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_I2S1_INT_MAP_M ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S)) +#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_I2S1_INT_MAP_S 0 + +#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54) +/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_UART_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UART_INTR_MAP_M ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S)) +#define INTERRUPT_CORE0_UART_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UART_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58) +/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UART1_INTR_MAP_M ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S)) +#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5C) +/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_LEDC_INT_MAP_M ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S)) +#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_LEDC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60) +/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_EFUSE_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_EFUSE_INT_MAP_M ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S)) +#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0 + +#define INTERRUPT_CORE0_CAN_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64) +/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CAN_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_CAN_INT_MAP_M ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S)) +#define INTERRUPT_CORE0_CAN_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_CAN_INT_MAP_S 0 + +#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68) +/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_USB_INTR_MAP_M ((INTERRUPT_CORE0_USB_INTR_MAP_V)<<(INTERRUPT_CORE0_USB_INTR_MAP_S)) +#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_USB_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6C) +/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S)) +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70) +/* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_RMT_INTR_MAP_M ((INTERRUPT_CORE0_RMT_INTR_MAP_V)<<(INTERRUPT_CORE0_RMT_INTR_MAP_S)) +#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74) +/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S)) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78) +/* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_TIMER_INT1_MAP 0x0000001F +#define INTERRUPT_CORE0_TIMER_INT1_MAP_M ((INTERRUPT_CORE0_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT1_MAP_S)) +#define INTERRUPT_CORE0_TIMER_INT1_MAP_V 0x1F +#define INTERRUPT_CORE0_TIMER_INT1_MAP_S 0 + +#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7C) +/* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_TIMER_INT2_MAP 0x0000001F +#define INTERRUPT_CORE0_TIMER_INT2_MAP_M ((INTERRUPT_CORE0_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT2_MAP_S)) +#define INTERRUPT_CORE0_TIMER_INT2_MAP_V 0x1F +#define INTERRUPT_CORE0_TIMER_INT2_MAP_S 0 + +#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80) +/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_TG_T0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG_T0_INT_MAP_M ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S)) +#define INTERRUPT_CORE0_TG_T0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG_T0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84) +/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_TG_WDT_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S)) +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88) +/* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_TG1_T0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T0_INT_MAP_S)) +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8C) +/* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_WDT_INT_MAP_S)) +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S 0 + +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90) +/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S)) +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94) +/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98) +/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9C) +/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA0) +/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S)) +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA4) +/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S)) +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S 0 + +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA8) +/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S)) +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xAC) +/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_APB_ADC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S)) +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB0) +/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH0_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB4) +/* INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH1_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB8) +/* INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH2_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_S 0 + +#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xBC) +/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_RSA_INT_MAP_M ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S)) +#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_RSA_INT_MAP_S 0 + +#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC0) +/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_AES_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_AES_INT_MAP_M ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S)) +#define INTERRUPT_CORE0_AES_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_AES_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC4) +/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SHA_INT_MAP_M ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S)) +#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SHA_INT_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC8) +/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xCC) +/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD0) +/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD4) +/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 + +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD8) +/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S)) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xDC) +/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE0) +/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE4) +/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE8) +/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xEC) +/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF0) +/* INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF4) +/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S)) +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TG3_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF8) +/* INTERRUPT_CORE0_TG3_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_TG3_T0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG3_T0_INT_MAP_M ((INTERRUPT_CORE0_TG3_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG3_T0_INT_MAP_S)) +#define INTERRUPT_CORE0_TG3_T0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG3_T0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xFC) +/* INTERRUPT_CORE0_TG3_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_TG3_WDT_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG3_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG3_WDT_INT_MAP_S)) +#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_S 0 + +#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +/* INTERRUPT_CORE0_BLE_SEC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_BLE_SEC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_M ((INTERRUPT_CORE0_BLE_SEC_INT_MAP_V)<<(INTERRUPT_CORE0_BLE_SEC_INT_MAP_S)) +#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) +/* INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_M ((INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_V)<<(INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_S)) +#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) +/* INTERRUPT_CORE0_ZIGBEEBB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_M ((INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_V)<<(INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_S)) +#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_S 0 + +#define INTERRUPT_CORE0_COEX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C) +/* INTERRUPT_CORE0_COEX_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_COEX_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_COEX_INT_MAP_M ((INTERRUPT_CORE0_COEX_INT_MAP_V)<<(INTERRUPT_CORE0_COEX_INT_MAP_S)) +#define INTERRUPT_CORE0_COEX_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_COEX_INT_MAP_S 0 + +#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) +/* INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_M ((INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V)<<(INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S)) +#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S 0 + +#define INTERRUPT_CORE0_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) +/* INTERRUPT_CORE0_ECC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_ECC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_ECC_INT_MAP_M ((INTERRUPT_CORE0_ECC_INT_MAP_V)<<(INTERRUPT_CORE0_ECC_INT_MAP_S)) +#define INTERRUPT_CORE0_ECC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_ECC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) +/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_0_M ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S)) +#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_0_S 0 + +#define INTERRUPT_CORE0_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C) +/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_1_M ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S)) +#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_1_S 0 + +#define INTERRUPT_CORE0_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) +/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_2_M ((INTERRUPT_CORE0_INTR_STATUS_2_V)<<(INTERRUPT_CORE0_INTR_STATUS_2_S)) +#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_2_S 0 + +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) +/* INTERRUPT_CORE0_REG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_REG_CLK_EN (BIT(0)) +#define INTERRUPT_CORE0_REG_CLK_EN_M (BIT(0)) +#define INTERRUPT_CORE0_REG_CLK_EN_V 0x1 +#define INTERRUPT_CORE0_REG_CLK_EN_S 0 + +#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) +/* INTERRUPT_CORE0_CPU_INT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_INT_ENABLE 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_ENABLE_M ((INTERRUPT_CORE0_CPU_INT_ENABLE_V)<<(INTERRUPT_CORE0_CPU_INT_ENABLE_S)) +#define INTERRUPT_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_ENABLE_S 0 + +#define INTERRUPT_CORE0_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C) +/* INTERRUPT_CORE0_CPU_INT_TYPE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_INT_TYPE 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_TYPE_M ((INTERRUPT_CORE0_CPU_INT_TYPE_V)<<(INTERRUPT_CORE0_CPU_INT_TYPE_S)) +#define INTERRUPT_CORE0_CPU_INT_TYPE_V 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_TYPE_S 0 + +#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) +/* INTERRUPT_CORE0_CPU_INT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_INT_CLEAR 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_CLEAR_M ((INTERRUPT_CORE0_CPU_INT_CLEAR_V)<<(INTERRUPT_CORE0_CPU_INT_CLEAR_S)) +#define INTERRUPT_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_CLEAR_S 0 + +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) +/* INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M ((INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V)<<(INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S)) +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) +/* INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_0_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M ((INTERRUPT_CORE0_CPU_PRI_0_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_0_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_0_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C) +/* INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_1_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M ((INTERRUPT_CORE0_CPU_PRI_1_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_1_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_1_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) +/* INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_2_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M ((INTERRUPT_CORE0_CPU_PRI_2_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_2_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_2_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) +/* INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_3_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M ((INTERRUPT_CORE0_CPU_PRI_3_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_3_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_3_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) +/* INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_4_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M ((INTERRUPT_CORE0_CPU_PRI_4_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_4_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_4_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C) +/* INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_5_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M ((INTERRUPT_CORE0_CPU_PRI_5_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_5_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_5_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) +/* INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_6_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M ((INTERRUPT_CORE0_CPU_PRI_6_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_6_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_6_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) +/* INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_7_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M ((INTERRUPT_CORE0_CPU_PRI_7_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_7_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_7_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) +/* INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_8_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M ((INTERRUPT_CORE0_CPU_PRI_8_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_8_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_8_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C) +/* INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_9_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M ((INTERRUPT_CORE0_CPU_PRI_9_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_9_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_9_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) +/* INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_10_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M ((INTERRUPT_CORE0_CPU_PRI_10_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_10_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_10_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) +/* INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_11_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M ((INTERRUPT_CORE0_CPU_PRI_11_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_11_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_11_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) +/* INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_12_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M ((INTERRUPT_CORE0_CPU_PRI_12_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_12_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_12_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C) +/* INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_13_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M ((INTERRUPT_CORE0_CPU_PRI_13_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_13_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_13_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) +/* INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_14_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M ((INTERRUPT_CORE0_CPU_PRI_14_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_14_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_14_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174) +/* INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_15_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M ((INTERRUPT_CORE0_CPU_PRI_15_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_15_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_15_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178) +/* INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_16_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M ((INTERRUPT_CORE0_CPU_PRI_16_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_16_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_16_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17C) +/* INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_17_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M ((INTERRUPT_CORE0_CPU_PRI_17_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_17_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_17_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) +/* INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_18_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M ((INTERRUPT_CORE0_CPU_PRI_18_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_18_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_18_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184) +/* INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_19_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M ((INTERRUPT_CORE0_CPU_PRI_19_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_19_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_19_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188) +/* INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_20_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M ((INTERRUPT_CORE0_CPU_PRI_20_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_20_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_20_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18C) +/* INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_21_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M ((INTERRUPT_CORE0_CPU_PRI_21_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_21_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_21_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190) +/* INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_22_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M ((INTERRUPT_CORE0_CPU_PRI_22_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_22_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_22_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194) +/* INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_23_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M ((INTERRUPT_CORE0_CPU_PRI_23_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_23_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_23_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198) +/* INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_24_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M ((INTERRUPT_CORE0_CPU_PRI_24_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_24_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_24_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19C) +/* INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_25_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M ((INTERRUPT_CORE0_CPU_PRI_25_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_25_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_25_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A0) +/* INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_26_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M ((INTERRUPT_CORE0_CPU_PRI_26_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_26_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_26_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A4) +/* INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_27_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M ((INTERRUPT_CORE0_CPU_PRI_27_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_27_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_27_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A8) +/* INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_28_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M ((INTERRUPT_CORE0_CPU_PRI_28_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_28_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_28_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1AC) +/* INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_29_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M ((INTERRUPT_CORE0_CPU_PRI_29_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_29_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_29_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B0) +/* INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_30_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M ((INTERRUPT_CORE0_CPU_PRI_30_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_30_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_30_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B4) +/* INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_PRI_31_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M ((INTERRUPT_CORE0_CPU_PRI_31_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_31_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_31_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B8) +/* INTERRUPT_CORE0_CPU_INT_THRESH : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_CPU_INT_THRESH 0x0000000F +#define INTERRUPT_CORE0_CPU_INT_THRESH_M ((INTERRUPT_CORE0_CPU_INT_THRESH_V)<<(INTERRUPT_CORE0_CPU_INT_THRESH_S)) +#define INTERRUPT_CORE0_CPU_INT_THRESH_V 0xF +#define INTERRUPT_CORE0_CPU_INT_THRESH_S 0 + +#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC) +/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2011090 ; */ +/*description: Need add description.*/ +#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF +#define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S)) +#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0xFFFFFFF +#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0 + +#define INTC_INT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4) +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/rev2/io_mux_reg.h b/components/soc/esp32h2/include/soc/rev2/io_mux_reg.h new file mode 100644 index 0000000000..cc79acc33d --- /dev/null +++ b/components/soc/esp32h2/include/soc/rev2/io_mux_reg.h @@ -0,0 +1,268 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once +#include "soc.h" + +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ +/* Output enable in sleep mode */ +#define SLP_OE (BIT(0)) +#define SLP_OE_M (BIT(0)) +#define SLP_OE_V 1 +#define SLP_OE_S 0 +/* Pin used for wakeup from sleep */ +#define SLP_SEL (BIT(1)) +#define SLP_SEL_M (BIT(1)) +#define SLP_SEL_V 1 +#define SLP_SEL_S 1 +/* Pulldown enable in sleep mode */ +#define SLP_PD (BIT(2)) +#define SLP_PD_M (BIT(2)) +#define SLP_PD_V 1 +#define SLP_PD_S 2 +/* Pullup enable in sleep mode */ +#define SLP_PU (BIT(3)) +#define SLP_PU_M (BIT(3)) +#define SLP_PU_V 1 +#define SLP_PU_S 3 +/* Input enable in sleep mode */ +#define SLP_IE (BIT(4)) +#define SLP_IE_M (BIT(4)) +#define SLP_IE_V 1 +#define SLP_IE_S 4 +/* Drive strength in sleep mode */ +#define SLP_DRV 0x3 +#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) +#define SLP_DRV_V 0x3 +#define SLP_DRV_S 5 +/* Pulldown enable */ +#define FUN_PD (BIT(7)) +#define FUN_PD_M (BIT(7)) +#define FUN_PD_V 1 +#define FUN_PD_S 7 +/* Pullup enable */ +#define FUN_PU (BIT(8)) +#define FUN_PU_M (BIT(8)) +#define FUN_PU_V 1 +#define FUN_PU_S 8 +/* Input enable */ +#define FUN_IE (BIT(9)) +#define FUN_IE_M (FUN_IE_V << FUN_IE_S) +#define FUN_IE_V 1 +#define FUN_IE_S 9 +/* Drive strength */ +#define FUN_DRV 0x3 +#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) +#define FUN_DRV_V 0x3 +#define FUN_DRV_S 10 +/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ +#define MCU_SEL 0x7 +#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) +#define MCU_SEL_V 0x7 +#define MCU_SEL_S 12 + +#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) + +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_MTMS_U +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_MTDO_U +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTCK_U +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_XTAL_32K_P_U +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_XTAL_32K_N_U +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_SPICS0_U +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPIQ_U +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPIWP_U +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPIHD_U +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPICLK_U +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_SPID_U +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_VDD_SPI_U +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0RXD_U +#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U0TXD_U +#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_GPIO23_U +#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U +#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_GPIO25_U + +#define FUNC_GPIO_GPIO 1 +#define PIN_FUNC_GPIO 1 + +#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) + +#define SPI_HD_GPIO_NUM 16 +#define SPI_WP_GPIO_NUM 15 +#define SPI_CS0_GPIO_NUM 13 +#define SPI_CLK_GPIO_NUM 17 +#define SPI_D_GPIO_NUM 18 +#define SPI_Q_GPIO_NUM 14 + +#define MAX_RTC_GPIO_NUM 5 +#define MAX_PAD_GPIO_NUM 20 +#define MAX_GPIO_NUM 24 +#define DIG_IO_HOLD_BIT_SHIFT 0 + + +#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE +#define PIN_CTRL (REG_IO_MUX_BASE +0x00) +#define PAD_POWER_SEL BIT(15) +#define PAD_POWER_SEL_V 0x1 +#define PAD_POWER_SEL_M BIT(15) +#define PAD_POWER_SEL_S 15 + +#define PAD_POWER_SWITCH_DELAY 0x7 +#define PAD_POWER_SWITCH_DELAY_V 0x7 +#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) +#define PAD_POWER_SWITCH_DELAY_S 12 + +#define CLK_OUT3 0xf +#define CLK_OUT3_V CLK_OUT3 +#define CLK_OUT3_S 8 +#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S) +#define CLK_OUT2 0xf +#define CLK_OUT2_V CLK_OUT2 +#define CLK_OUT2_S 4 +#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S) +#define CLK_OUT1 0xf +#define CLK_OUT1_V CLK_OUT1 +#define CLK_OUT1_S 0 +#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S) +// definitions above are inherited from previous version of code, should double check + +// definitions below are generated from pin_txt.csv +#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE + 0x4) +#define FUNC_GPIO0_FSPIQ 2 +#define FUNC_GPIO0_GPIO0 1 +#define FUNC_GPIO0_GPIO0_0 0 + +#define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE + 0x8) +#define FUNC_GPIO1_FSPICS0 2 +#define FUNC_GPIO1_GPIO1 1 +#define FUNC_GPIO1_GPIO1_0 0 + +#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0xC) +#define FUNC_MTMS_FSPIWP 2 +#define FUNC_MTMS_GPIO2 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x10) +#define FUNC_MTDO_FSPIHD 2 +#define FUNC_MTDO_GPIO3 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x14) +#define FUNC_MTCK_FSPICLK 2 +#define FUNC_MTCK_GPIO4 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x18) +#define FUNC_MTDI_FSPID 2 +#define FUNC_MTDI_GPIO5 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE + 0x1C) +#define FUNC_GPIO6_GPIO6 1 +#define FUNC_GPIO6_GPIO6_0 0 + +#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE + 0x20) +#define FUNC_GPIO7_GPIO7 1 +#define FUNC_GPIO7_GPIO7_0 0 + +#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24) +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_GPIO8_0 0 + +#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28) +#define FUNC_GPIO9_GPIO9 1 +#define FUNC_GPIO9_GPIO9_0 0 + +#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x2C) +#define FUNC_XTAL_32K_P_GPIO10 1 +#define FUNC_XTAL_32K_P_GPIO10_0 0 + +#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x30) +#define FUNC_XTAL_32K_N_GPIO11 1 +#define FUNC_XTAL_32K_N_GPIO11_0 0 + +#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE + 0x34) +#define FUNC_GPIO12_GPIO12 1 +#define FUNC_GPIO12_GPIO12_0 0 + +#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x38) +#define FUNC_SPICS0_GPIO13 1 +#define FUNC_SPICS0_SPICS0 0 + +#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x3C) +#define FUNC_SPIQ_GPIO14 1 +#define FUNC_SPIQ_SPIQ 0 + +#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x40) +#define FUNC_SPIWP_GPIO15 1 +#define FUNC_SPIWP_SPIWP 0 + +#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x44) +#define FUNC_SPIHD_GPIO16 1 +#define FUNC_SPIHD_SPIHD 0 + +#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x48) +#define FUNC_SPICLK_GPIO17 1 +#define FUNC_SPICLK_SPICLK 0 + +#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x4C) +#define FUNC_SPID_GPIO18 1 +#define FUNC_SPID_SPID 0 + +#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x50) +#define FUNC_VDD_SPI_GPIO19 1 +#define FUNC_VDD_SPI_GPIO19_0 0 + +#define PERIPHS_IO_MUX_GPIO20_U (REG_IO_MUX_BASE + 0x54) +#define FUNC_GPIO20_GPIO20 1 +#define FUNC_GPIO20_GPIO20_0 0 + +#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x58) +#define FUNC_U0RXD_GPIO21 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x5C) +#define FUNC_U0TXD_GPIO22 1 +#define FUNC_U0TXD_U0TXD 0 + +#define PERIPHS_IO_MUX_GPIO23_U (REG_IO_MUX_BASE + 0x60) +#define FUNC_GPIO23_GPIO23 1 +#define FUNC_GPIO23_GPIO23_0 0 + +#define PERIPHS_IO_MUX_GPIO24_U (REG_IO_MUX_BASE + 0x64) +#define FUNC_GPIO24_GPIO24 1 +#define FUNC_GPIO24_GPIO24_0 0 + +#define PERIPHS_IO_MUX_GPIO25_U (REG_IO_MUX_BASE + 0x68) +#define FUNC_GPIO25_GPIO25 1 +#define FUNC_GPIO25_GPIO25_0 0 diff --git a/components/soc/esp32h2/include/soc/rev2/rtc_cntl_reg.h b/components/soc/esp32h2/include/soc/rev2/rtc_cntl_reg.h new file mode 100644 index 0000000000..02d3012df6 --- /dev/null +++ b/components/soc/esp32h2/include/soc/rev2/rtc_cntl_reg.h @@ -0,0 +1,3276 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _SOC_RTC_CNTL_REG_H_ +#define _SOC_RTC_CNTL_REG_H_ + +/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */ +#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1 +/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */ +#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A + +/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */ +#define RTC_WDT_RESET_LENGTH_100_NS 0 +#define RTC_WDT_RESET_LENGTH_200_NS 1 +#define RTC_WDT_RESET_LENGTH_300_NS 2 +#define RTC_WDT_RESET_LENGTH_400_NS 3 +#define RTC_WDT_RESET_LENGTH_500_NS 4 +#define RTC_WDT_RESET_LENGTH_800_NS 5 +#define RTC_WDT_RESET_LENGTH_1600_NS 6 +#define RTC_WDT_RESET_LENGTH_3200_NS 7 + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG +#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG + +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) +/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW system reset.*/ +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_V 0x1 +#define RTC_CNTL_SW_SYS_RST_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force no reset in deep sleep.*/ +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 +/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: digital wrap force reset in deep sleep.*/ +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 +/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 +/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 +/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 +/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 +/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 +/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 +/* RTC_CNTL_XTL_EXT_CTR_SEL : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XTL_EXT_CTR_SEL 0x00000007 +#define RTC_CNTL_XTL_EXT_CTR_SEL_M ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S)) +#define RTC_CNTL_XTL_EXT_CTR_SEL_V 0x7 +#define RTC_CNTL_XTL_EXT_CTR_SEL_S 20 +/* RTC_CNTL_XPD_RFPLL_FORCE : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XPD_RFPLL_FORCE (BIT(19)) +#define RTC_CNTL_XPD_RFPLL_FORCE_M (BIT(19)) +#define RTC_CNTL_XPD_RFPLL_FORCE_V 0x1 +#define RTC_CNTL_XPD_RFPLL_FORCE_S 19 +/* RTC_CNTL_XPD_RFPLL : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XPD_RFPLL (BIT(18)) +#define RTC_CNTL_XPD_RFPLL_M (BIT(18)) +#define RTC_CNTL_XPD_RFPLL_V 0x1 +#define RTC_CNTL_XPD_RFPLL_S 18 +/* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ +/*description: wait bias_sleep and current source wakeup.*/ +#define RTC_CNTL_XTL_EN_WAIT 0x0000000F +#define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) +#define RTC_CNTL_XTL_EN_WAIT_V 0xF +#define RTC_CNTL_XTL_EN_WAIT_S 14 +/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ +/*description: crystall force power up.*/ +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_V 0x1 +#define RTC_CNTL_XTL_FORCE_PU_S 13 +/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: crystall force power down.*/ +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_V 0x1 +#define RTC_CNTL_XTL_FORCE_PD_S 12 +/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: BB_PLL force power up.*/ +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 +/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: BB_PLL force power down.*/ +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 +/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: BB_PLL_I2C force power up.*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: BB_PLL _I2C force power down.*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 +/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: BB_I2C force power up.*/ +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: BB_I2C force power down.*/ +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 +/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: PRO CPU SW reset.*/ +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_V 0x1 +#define RTC_CNTL_SW_PROCPU_RST_S 5 +/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: APP CPU SW reset.*/ +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_V 0x1 +#define RTC_CNTL_SW_APPCPU_RST_S 4 +/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall P +RO CPU.*/ +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 +/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall A +PP CPU.*/ +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 + +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) +/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC sleep timer low 32 bits.*/ +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 + +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ +/*description: timer alarm enable bit.*/ +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 +/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC sleep timer high 16 bits.*/ +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) +#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 + +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xC) +/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Set 1: to update register with RTC timer.*/ +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_V 0x1 +#define RTC_CNTL_TIME_UPDATE_S 31 +/* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: enable to record system reset time.*/ +#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_V 0x1 +#define RTC_CNTL_TIMER_SYS_RST_S 29 +/* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Enable to record 40M XTAL OFF time.*/ +#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_V 0x1 +#define RTC_CNTL_TIMER_XTL_OFF_S 28 +/* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Enable to record system stall time.*/ +#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_V 0x1 +#define RTC_CNTL_TIMER_SYS_STALL_S 27 + +#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10) +/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits.*/ +#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S)) +#define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_S 0 + +#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14) +/* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits.*/ +#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 + +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) +/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: sleep enable bit.*/ +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (BIT(31)) +#define RTC_CNTL_SLEEP_EN_V 0x1 +#define RTC_CNTL_SLEEP_EN_S 31 +/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: leep reject bit.*/ +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (BIT(30)) +#define RTC_CNTL_SLP_REJECT_V 0x1 +#define RTC_CNTL_SLP_REJECT_S 30 +/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: leep wakeup bit.*/ +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_S 29 +/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: SDIO active indication.*/ +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 +/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: APB to RTC using bridge, 0: APB to RTC using sync.*/ +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 +/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: clear rtc sleep reject cause.*/ +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 +/* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: rtc software interrupt to main cpu.*/ +#define RTC_CNTL_SW_CPU_INT (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_M (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_V 0x1 +#define RTC_CNTL_SW_CPU_INT_S 0 + +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1C) +/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ +/*description: PLL wait cycles in slow_clk_rtc.*/ +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) +#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 +/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ +/*description: XTAL wait cycles in slow_clk_rtc.*/ +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 +/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ +/*description: CK8M wait cycles in slow_clk_rtc.*/ +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) +#define RTC_CNTL_CK8M_WAIT_V 0xFF +#define RTC_CNTL_CK8M_WAIT_S 6 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 +/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ +/*description: CPU stall wait cycles in fast_clk_rtc.*/ +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 +/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: CPU stall enable bit.*/ +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_V 0x1 +#define RTC_CNTL_CPU_STALL_EN_S 0 + +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) +/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ +/*description: minimal cycles in slow_clk_rtc for CK8M in power down state.*/ +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 + +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) +/* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BT_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_BT_POWERUP_TIMER_M ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S)) +#define RTC_CNTL_BT_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_BT_POWERUP_TIMER_S 25 +/* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BT_WAIT_TIMER 0x000001FF +#define RTC_CNTL_BT_WAIT_TIMER_M ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S)) +#define RTC_CNTL_BT_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_BT_WAIT_TIMER_S 16 +/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 +/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) +/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 +/* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S)) +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9 +/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S)) +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2C) +/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ +/*description: minimal sleep cycles in slow_clk_rtc.*/ +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) +#define RTC_CNTL_MIN_SLP_VAL_V 0xFF +#define RTC_CNTL_MIN_SLP_VAL_S 8 +#define RTC_CNTL_MIN_SLP_VAL_MIN 2 + +#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x30) +/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_PERI_WAIT_TIMER_M ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S)) +#define RTC_CNTL_DG_PERI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_PERI_WAIT_TIMER_S 16 + +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x34) +/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_V 0x1 +#define RTC_CNTL_PLL_I2C_PU_S 31 +/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: 1: CKGEN_I2C power up , otherwise power down.*/ +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 +/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: 1: RFRX_PBUS power up , otherwise power down.*/ +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 +/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: 1: TXRF_I2C power up , otherwise power down.*/ +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_V 0x1 +#define RTC_CNTL_TXRF_I2C_PU_S 27 +/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: PVTMON power up , otherwise power down.*/ +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (BIT(26)) +#define RTC_CNTL_PVTMON_PU_V 0x1 +#define RTC_CNTL_PVTMON_PU_S 26 +/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: start BBPLL calibration during sleep.*/ +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 +/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: PLLA force power up.*/ +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PU_S 24 +/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: PLLA force power down.*/ +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PD_S 23 +/* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_SAR_I2C_PU (BIT(22)) +#define RTC_CNTL_SAR_I2C_PU_M (BIT(22)) +#define RTC_CNTL_SAR_I2C_PU_V 0x1 +#define RTC_CNTL_SAR_I2C_PU_S 22 +/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_V 0x1 +#define RTC_CNTL_GLITCH_RST_EN_S 20 +/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 +/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 +/* RTC_CNTL_XPD_TRX_FORCE_PU : R/W ;bitpos:[17] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XPD_TRX_FORCE_PU (BIT(17)) +#define RTC_CNTL_XPD_TRX_FORCE_PU_M (BIT(17)) +#define RTC_CNTL_XPD_TRX_FORCE_PU_V 0x1 +#define RTC_CNTL_XPD_TRX_FORCE_PU_S 17 +/* RTC_CNTL_XPD_TRX_FORCE_PD : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XPD_TRX_FORCE_PD (BIT(16)) +#define RTC_CNTL_XPD_TRX_FORCE_PD_M (BIT(16)) +#define RTC_CNTL_XPD_TRX_FORCE_PD_V 0x1 +#define RTC_CNTL_XPD_TRX_FORCE_PD_S 16 + +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) +/* RTC_CNTL_DRESET_MASK_PROCPU : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DRESET_MASK_PROCPU (BIT(25)) +#define RTC_CNTL_DRESET_MASK_PROCPU_M (BIT(25)) +#define RTC_CNTL_DRESET_MASK_PROCPU_V 0x1 +#define RTC_CNTL_DRESET_MASK_PROCPU_S 25 +/* RTC_CNTL_DRESET_MASK_APPCPU : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DRESET_MASK_APPCPU (BIT(24)) +#define RTC_CNTL_DRESET_MASK_APPCPU_M (BIT(24)) +#define RTC_CNTL_DRESET_MASK_APPCPU_V 0x1 +#define RTC_CNTL_DRESET_MASK_APPCPU_S 24 +/* RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU (BIT(23)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_M (BIT(23)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_S 23 +/* RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU (BIT(22)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_M (BIT(22)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_S 22 +/* RTC_CNTL_JTAG_RESET_FLAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU (BIT(21)) +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_M (BIT(21)) +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_S 21 +/* RTC_CNTL_JTAG_RESET_FLAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU (BIT(20)) +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_M (BIT(20)) +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_S 20 +/* RTC_CNTL_OCD_HALT_ON_RESET_PROCPU : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: PROCPU OcdHaltOnReset.*/ +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU (BIT(19)) +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M (BIT(19)) +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V 0x1 +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S 19 +/* RTC_CNTL_OCD_HALT_ON_RESET_APPCPU : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: APPCPU OcdHaltOnReset.*/ +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU (BIT(18)) +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_M (BIT(18)) +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_V 0x1 +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_S 18 +/* RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: clear APP CPU reset flag.*/ +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU (BIT(17)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_M (BIT(17)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_S 17 +/* RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: clear PRO CPU reset_flag.*/ +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU (BIT(16)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_M (BIT(16)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_S 16 +/* RTC_CNTL_ALL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: APP CPU reset flag.*/ +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU (BIT(15)) +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_M (BIT(15)) +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_S 15 +/* RTC_CNTL_ALL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: PRO CPU reset_flag.*/ +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU (BIT(14)) +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_M (BIT(14)) +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_S 14 +/* RTC_CNTL_STAT_VECTOR_SEL_PROCPU : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: PRO CPU state vector sel.*/ +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU (BIT(13)) +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M (BIT(13)) +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V 0x1 +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S 13 +/* RTC_CNTL_STAT_VECTOR_SEL_APPCPU : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: APP CPU state vector sel.*/ +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU (BIT(12)) +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_M (BIT(12)) +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_V 0x1 +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_S 12 +/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ +/*description: reset cause of APP CPU.*/ +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 +/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ +/*description: reset cause of PRO CPU.*/ +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 + +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x3C) +/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:13] ;default: 18'b1100 ; */ +/*description: wakeup enable bitmap.*/ +#define RTC_CNTL_WAKEUP_ENA 0x0007FFFF +#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) +#define RTC_CNTL_WAKEUP_ENA_V 0x7FFFF +#define RTC_CNTL_WAKEUP_ENA_S 13 + +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x40) +/* RTC_CNTL_VSET_DCDC_DONE_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_M (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_V 0x1 +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_S 22 +/* RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA : ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_M (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_V 0x1 +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_S 21 +/* RTC_CNTL_BBPLL_CAL_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BBPLL_CAL_INT_ENA (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ENA_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enbale gitch det interrupt.*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 +/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt.*/ +#define RTC_CNTL_SWD_INT_ENA (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt.*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 +/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt.*/ +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_S 3 +/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt.*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 + +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x44) +/* RTC_CNTL_VSET_DCDC_DONE_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW_M (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW_V 0x1 +#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW_S 22 +/* RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW_M (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW_V 0x1 +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW_S 21 +/* RTC_CNTL_BBPLL_CAL_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BBPLL_CAL_INT_RAW (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_RAW_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_RAW_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_RAW_S 20 +/* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: glitch_det_interrupt_raw.*/ +#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: xtal32k dead detection interrupt raw.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 +/* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: super watch dog interrupt raw.*/ +#define RTC_CNTL_SWD_INT_RAW (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_V 0x1 +#define RTC_CNTL_SWD_INT_RAW_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt raw.*/ +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 +/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: brown out interrupt raw.*/ +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 +/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt raw.*/ +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_V 0x1 +#define RTC_CNTL_WDT_INT_RAW_S 3 +/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt raw.*/ +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt raw.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 + +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x48) +/* RTC_CNTL_VSET_DCDC_DONE_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_DONE_INT_ST (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ST_M (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ST_V 0x1 +#define RTC_CNTL_VSET_DCDC_DONE_INT_ST_S 22 +/* RTC_CNTL_BLE_COMPARE_WAKE_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST_M (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST_V 0x1 +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST_S 21 +/* RTC_CNTL_BBPLL_CAL_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BBPLL_CAL_INT_ST (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ST_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ST_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ST_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: glitch_det_interrupt state.*/ +#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: xtal32k dead detection interrupt state.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 +/* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: super watch dog interrupt state.*/ +#define RTC_CNTL_SWD_INT_ST (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_V 0x1 +#define RTC_CNTL_SWD_INT_ST_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt state.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: brown out interrupt state.*/ +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 9 +/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt state.*/ +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_V 0x1 +#define RTC_CNTL_WDT_INT_ST_S 3 +/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt state.*/ +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt state.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 + +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x4C) +/* RTC_CNTL_VSET_DCDC_DONE_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR_M (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR_V 0x1 +#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR_S 22 +/* RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR_M (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR_V 0x1 +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR_S 21 +/* RTC_CNTL_BBPLL_CAL_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BBPLL_CAL_INT_CLR (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_CLR_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_CLR_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_CLR_S 20 +/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Clear glitch det interrupt state.*/ +#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 +/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Clear super watch dog interrupt state.*/ +#define RTC_CNTL_SWD_INT_CLR (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_V 0x1 +#define RTC_CNTL_SWD_INT_CLR_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Clear RTC main timer interrupt state.*/ +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 +/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Clear brown out interrupt state.*/ +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 +/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state.*/ +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_V 0x1 +#define RTC_CNTL_WDT_INT_CLR_S 3 +/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Clear sleep reject interrupt state.*/ +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Clear sleep wakeup interrupt state.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 + +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x50) +/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 + +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x54) +/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 + +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x58) +/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 + +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x5C) +/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 + +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) +/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 +/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: power down XTAL at high level, 1: power down XTAL at low level.*/ +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 +/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C.*/ +#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 +#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 +/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ +/*description: state of 32k_wdt.*/ +#define RTC_CNTL_WDT_STATE 0x00000007 +#define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) +#define RTC_CNTL_WDT_STATE_V 0x7 +#define RTC_CNTL_WDT_STATE_S 20 +/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ +/*description: DAC_XTAL_32K.*/ +#define RTC_CNTL_DAC_XTAL_32K 0x00000007 +#define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) +#define RTC_CNTL_DAC_XTAL_32K_V 0x7 +#define RTC_CNTL_DAC_XTAL_32K_S 17 +/* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: XPD_XTAL_32K.*/ +#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_V 0x1 +#define RTC_CNTL_XPD_XTAL_32K_S 16 +/* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ +/*description: DRES_XTAL_32K.*/ +#define RTC_CNTL_DRES_XTAL_32K 0x00000007 +#define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S)) +#define RTC_CNTL_DRES_XTAL_32K_V 0x7 +#define RTC_CNTL_DRES_XTAL_32K_S 13 +/* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ +/*description: xtal_32k gm control.*/ +#define RTC_CNTL_DGM_XTAL_32K 0x00000007 +#define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S)) +#define RTC_CNTL_DGM_XTAL_32K_V 0x7 +#define RTC_CNTL_DGM_XTAL_32K_S 10 +/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 0: single-end buffer 1: differential buffer.*/ +#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_V 0x1 +#define RTC_CNTL_DBUF_XTAL_32K_S 9 +/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: apply an internal clock to help xtal 32k to start.*/ +#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 +#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 +/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: Xtal 32k xpd control by sw or fsm.*/ +#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 +#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 +/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: xtal 32k switch back xtal when xtal is restarted.*/ +#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 +/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: xtal 32k restart xtal when xtal is dead.*/ +#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 +/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: xtal 32k switch to back up clock when xtal is dead.*/ +#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 +/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: xtal 32k external xtal clock force on.*/ +#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 +/* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog sw reset.*/ +#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 +/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog clock force on.*/ +#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 +/* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog enable.*/ +#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_EN_S 0 + +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable filter for gpio wakeup event.*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(31)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(31)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 31 + +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) +/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable reject for deep sleep.*/ +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 +/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable reject for light sleep.*/ +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 +/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:11] ;default: 18'd0 ; */ +/*description: sleep reject enable.*/ +#define RTC_CNTL_SLEEP_REJECT_ENA 0x0007FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) +#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x7FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_S 11 + +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6C) +/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 +/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: CPU sel option.*/ +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_V 0x1 +#define RTC_CNTL_CPUSEL_CONF_S 29 + +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) +/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 +/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M.*/ +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 +/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING (BIT(28)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M (BIT(28)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S 28 +/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING (BIT(27)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M (BIT(27)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V 0x1 +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S 27 +/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: CK8M force power up.*/ +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 +/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: CK8M force power down.*/ +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 +/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:15] ;default: 10'd600 ; */ +/*description: CK8M_DFREQ.*/ +#define RTC_CNTL_CK8M_DFREQ 0x000003FF +#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) +#define RTC_CNTL_CK8M_DFREQ_V 0x3FF +#define RTC_CNTL_CK8M_DFREQ_S 15 +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: CK8M force no gating during sleep.*/ +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(14)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(14)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 14 +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: XTAL force no gating during sleep.*/ +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(13)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(13)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 13 +/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ +/*description: divider = reg_ck8m_div_sel + 1.*/ +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 +#define RTC_CNTL_CK8M_DIV_SEL_S 10 +/* RTC_CNTL_BLE_TIMER_SEL : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BLE_TIMER_SEL (BIT(7)) +#define RTC_CNTL_BLE_TIMER_SEL_M (BIT(7)) +#define RTC_CNTL_BLE_TIMER_SEL_V 0x1 +#define RTC_CNTL_BLE_TIMER_SEL_S 7 +/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: enable CK8M for digital core (no relationship with RTC core).*/ +#define RTC_CNTL_DIG_CLK8M_EN (BIT(6)) +#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(6)) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_EN_S 6 +/* RTC_CNTL_DIG_RC32K_EN : R/W ;bitpos:[5] ;default: 1'd1 ; */ +/*description: enable RC32K for digital core (no relationship with RTC core).*/ +#define RTC_CNTL_DIG_RC32K_EN (BIT(5)) +#define RTC_CNTL_DIG_RC32K_EN_M (BIT(5)) +#define RTC_CNTL_DIG_RC32K_EN_V 0x1 +#define RTC_CNTL_DIG_RC32K_EN_S 5 +/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core).*/ +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(4)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(4)) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 +#define RTC_CNTL_DIG_XTAL32K_EN_S 4 +/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then s +et vld to actually switch the clk.*/ +#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 +#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 +/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING (BIT(2)) +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M (BIT(2)) +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S 2 +/* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING (BIT(1)) +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (BIT(1)) +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x1 +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1 +/* RTC_CNTL_BLE_TMR_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BLE_TMR_RST (BIT(0)) +#define RTC_CNTL_BLE_TMR_RST_M (BIT(0)) +#define RTC_CNTL_BLE_TMR_RST_V 0x1 +#define RTC_CNTL_BLE_TMR_RST_S 0 + +#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) +/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 +/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_ANA_CLK_DIV 0x000000FF +#define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S)) +#define RTC_CNTL_ANA_CLK_DIV_V 0xFF +#define RTC_CNTL_ANA_CLK_DIV_S 23 +/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to +actually switch the clk.*/ +#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 +#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 +/* RTC_CNTL_ANA_CLK_PD_IDLE : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_ANA_CLK_PD_IDLE (BIT(21)) +#define RTC_CNTL_ANA_CLK_PD_IDLE_M (BIT(21)) +#define RTC_CNTL_ANA_CLK_PD_IDLE_V 0x1 +#define RTC_CNTL_ANA_CLK_PD_IDLE_S 21 +/* RTC_CNTL_ANA_CLK_PD_MONITOR : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_ANA_CLK_PD_MONITOR (BIT(20)) +#define RTC_CNTL_ANA_CLK_PD_MONITOR_M (BIT(20)) +#define RTC_CNTL_ANA_CLK_PD_MONITOR_V 0x1 +#define RTC_CNTL_ANA_CLK_PD_MONITOR_S 20 +/* RTC_CNTL_ANA_CLK_PD_SLP : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_ANA_CLK_PD_SLP (BIT(19)) +#define RTC_CNTL_ANA_CLK_PD_SLP_M (BIT(19)) +#define RTC_CNTL_ANA_CLK_PD_SLP_V 0x1 +#define RTC_CNTL_ANA_CLK_PD_SLP_S 19 + +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) +/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_V 0x1 +#define RTC_CNTL_XPD_SDIO_REG_S 31 +/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ +/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) +#define RTC_CNTL_DREFH_SDIO_V 0x3 +#define RTC_CNTL_DREFH_SDIO_S 29 +/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */ +/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) +#define RTC_CNTL_DREFM_SDIO_V 0x3 +#define RTC_CNTL_DREFM_SDIO_S 27 +/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ +/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) +#define RTC_CNTL_DREFL_SDIO_V 0x3 +#define RTC_CNTL_DREFL_SDIO_S 25 +/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: read only register for REG1P8_READY.*/ +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (BIT(24)) +#define RTC_CNTL_REG1P8_READY_V 0x1 +#define RTC_CNTL_REG1P8_READY_S 24 +/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_V 0x1 +#define RTC_CNTL_SDIO_TIEH_S 23 +/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: use SW option to control SDIO_REG ,0: use state machine.*/ +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_V 0x1 +#define RTC_CNTL_SDIO_FORCE_S 22 +/* RTC_CNTL_SDIO_REG_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0.*/ +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_V 0x1 +#define RTC_CNTL_SDIO_PD_EN_S 21 +/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: enable current limit.*/ +#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_V 0x1 +#define RTC_CNTL_SDIO_ENCURLIM_S 20 +/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: select current limit mode.*/ +#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_V 0x1 +#define RTC_CNTL_SDIO_MODECURLIM_S 19 +/* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ +/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d).*/ +#define RTC_CNTL_SDIO_DCURLIM 0x00000007 +#define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S)) +#define RTC_CNTL_SDIO_DCURLIM_V 0x7 +#define RTC_CNTL_SDIO_DCURLIM_S 16 +/* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: 0 to set init[1:0]=0.*/ +#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_V 0x1 +#define RTC_CNTL_SDIO_EN_INITI_S 15 +/* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ +/*description: add resistor from ldo output to ground. 0: no res, 1: 6k, 2: 4k, 3: 2k.*/ +#define RTC_CNTL_SDIO_INITI 0x00000003 +#define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S)) +#define RTC_CNTL_SDIO_INITI_V 0x3 +#define RTC_CNTL_SDIO_INITI_S 13 +/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ +/*description: ability to prevent LDO from overshoot.*/ +#define RTC_CNTL_SDIO_DCAP 0x00000003 +#define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S)) +#define RTC_CNTL_SDIO_DCAP_V 0x3 +#define RTC_CNTL_SDIO_DCAP_S 11 +/* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ +/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to +3 after several us..*/ +#define RTC_CNTL_SDIO_DTHDRV 0x00000003 +#define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S)) +#define RTC_CNTL_SDIO_DTHDRV_V 0x3 +#define RTC_CNTL_SDIO_DTHDRV_S 9 +/* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ +/*description: timer count to apply reg_sdio_dcap after sdio power on.*/ +#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF +#define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S)) +#define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF +#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 + +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x7C) +/* RTC_CNTL_XPD_DCDC_IDLE : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XPD_DCDC_IDLE (BIT(28)) +#define RTC_CNTL_XPD_DCDC_IDLE_M (BIT(28)) +#define RTC_CNTL_XPD_DCDC_IDLE_V 0x1 +#define RTC_CNTL_XPD_DCDC_IDLE_S 28 +/* RTC_CNTL_XPD_DCDC_MONITOR : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XPD_DCDC_MONITOR (BIT(27)) +#define RTC_CNTL_XPD_DCDC_MONITOR_M (BIT(27)) +#define RTC_CNTL_XPD_DCDC_MONITOR_V 0x1 +#define RTC_CNTL_XPD_DCDC_MONITOR_S 27 +/* RTC_CNTL_XPD_DCDC_SLP : R/W ;bitpos:[26] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XPD_DCDC_SLP (BIT(26)) +#define RTC_CNTL_XPD_DCDC_SLP_M (BIT(26)) +#define RTC_CNTL_XPD_DCDC_SLP_V 0x1 +#define RTC_CNTL_XPD_DCDC_SLP_S 26 +/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ +/*description: DBG_ATTEN when rtc in monitor state.*/ +#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F +#define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) +#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF +#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 +/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ +/*description: DBG_ATTEN when rtc in sleep state.*/ +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 +/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: bias_sleep when rtc in monitor state.*/ +#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 +/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: bias_sleep when rtc in sleep_state.*/ +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 +/* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: xpd cur when rtc in monitor state.*/ +#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_V 0x1 +#define RTC_CNTL_PD_CUR_MONITOR_S 15 +/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: xpd cur when rtc in sleep_state.*/ +#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 +#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 +/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 +/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 +/* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 +#define RTC_CNTL_BIAS_BUF_WAKE_S 11 +/* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 +#define RTC_CNTL_BIAS_BUF_IDLE_S 10 + +#define RTC_CNTL_REGULATOR_REG (DR_REG_RTCCNTL_BASE + 0x80) +/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PU_S 31 +/* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0 +.8v or lower ).*/ +#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PD_S 30 +/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: RTC_DBOOST force power up.*/ +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 +/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RTC_DBOOST force power down.*/ +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 +/* RTC_CNTL_VDD_DRV_B_SLP_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VDD_DRV_B_SLP_EN (BIT(27)) +#define RTC_CNTL_VDD_DRV_B_SLP_EN_M (BIT(27)) +#define RTC_CNTL_VDD_DRV_B_SLP_EN_V 0x1 +#define RTC_CNTL_VDD_DRV_B_SLP_EN_S 27 +/* RTC_CNTL_VDD_DRV_B_SLP : R/W ;bitpos:[26:21] ;default: 6'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VDD_DRV_B_SLP 0x0000003F +#define RTC_CNTL_VDD_DRV_B_SLP_M ((RTC_CNTL_VDD_DRV_B_SLP_V)<<(RTC_CNTL_VDD_DRV_B_SLP_S)) +#define RTC_CNTL_VDD_DRV_B_SLP_V 0x3F +#define RTC_CNTL_VDD_DRV_B_SLP_S 21 +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ +#define RTC_CNTL_DIG_DBIAS_0V85 0 +#define RTC_CNTL_DIG_DBIAS_0V90 1 +#define RTC_CNTL_DIG_DBIAS_0V95 2 +#define RTC_CNTL_DIG_DBIAS_1V00 3 +#define RTC_CNTL_DIG_DBIAS_1V05 4 +#define RTC_CNTL_DIG_DBIAS_1V10 5 +#define RTC_CNTL_DIG_DBIAS_1V15 6 +#define RTC_CNTL_DIG_DBIAS_1V20 7 + +/* The value of 1V00 can be adjusted between 0~3*/ +#define RTC_CNTL_DBIAS_1V00 0 +#define RTC_CNTL_DBIAS_1V05 4 +#define RTC_CNTL_DBIAS_1V10 5 +#define RTC_CNTL_DBIAS_1V15 6 +#define RTC_CNTL_DBIAS_1V20 7 + +/* RTC_CNTL_VDD_DRV_B_ACTIVE : R/W ;bitpos:[20:15] ;default: 6'd0 ; */ +/*description: SCK_DCAP.*/ +#define RTC_CNTL_VDD_DRV_B_ACTIVE 0x0000003F +#define RTC_CNTL_VDD_DRV_B_ACTIVE_M ((RTC_CNTL_VDD_DRV_B_ACTIVE_V)<<(RTC_CNTL_VDD_DRV_B_ACTIVE_S)) +#define RTC_CNTL_VDD_DRV_B_ACTIVE_V 0x3F +#define RTC_CNTL_VDD_DRV_B_ACTIVE_S 15 +/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[11:4] ;default: 8'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) +#define RTC_CNTL_SCK_DCAP_V 0xFF +#define RTC_CNTL_SCK_DCAP_S 4 +/* RTC_CNTL_DIG_REG_CAL_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DIG_REG_CAL_EN (BIT(3)) +#define RTC_CNTL_DIG_REG_CAL_EN_M (BIT(3)) +#define RTC_CNTL_DIG_REG_CAL_EN_V 0x1 +#define RTC_CNTL_DIG_REG_CAL_EN_S 3 +/* RTC_CNTL_DBIAS_SWITCH_IDLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DBIAS_SWITCH_IDLE (BIT(2)) +#define RTC_CNTL_DBIAS_SWITCH_IDLE_M (BIT(2)) +#define RTC_CNTL_DBIAS_SWITCH_IDLE_V 0x1 +#define RTC_CNTL_DBIAS_SWITCH_IDLE_S 2 +/* RTC_CNTL_DBIAS_SWITCH_MONITOR : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DBIAS_SWITCH_MONITOR (BIT(1)) +#define RTC_CNTL_DBIAS_SWITCH_MONITOR_M (BIT(1)) +#define RTC_CNTL_DBIAS_SWITCH_MONITOR_V 0x1 +#define RTC_CNTL_DBIAS_SWITCH_MONITOR_S 1 +/* RTC_CNTL_DBIAS_SWITCH_SLP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DBIAS_SWITCH_SLP (BIT(0)) +#define RTC_CNTL_DBIAS_SWITCH_SLP_M (BIT(0)) +#define RTC_CNTL_DBIAS_SWITCH_SLP_V 0x1 +#define RTC_CNTL_DBIAS_SWITCH_SLP_S 0 + +#define RTC_CNTL_REGULATOR0_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x84) +/* RTC_CNTL_REGULATOR0_DBIAS_SEL : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: 1: select sw dbias_active 0: select pvt value.*/ +#define RTC_CNTL_REGULATOR0_DBIAS_SEL (BIT(31)) +#define RTC_CNTL_REGULATOR0_DBIAS_SEL_M (BIT(31)) +#define RTC_CNTL_REGULATOR0_DBIAS_SEL_V 0x1 +#define RTC_CNTL_REGULATOR0_DBIAS_SEL_S 31 +/* RTC_CNTL_REGULATOR0_DBIAS_ACTIVE : R/W ;bitpos:[29:25] ;default: 5'b10100 ; */ +/*description: the rtc regulator0 dbias when chip in active state.*/ +#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE 0x0000001F +#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_M ((RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_V)<<(RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_S)) +#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_V 0x1F +#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_S 25 +/* RTC_CNTL_REGULATOR0_DBIAS_SLP : R/W ;bitpos:[24:20] ;default: 5'b10100 ; */ +/*description: the rtc regulator0 dbias when chip in sleep state.*/ +#define RTC_CNTL_REGULATOR0_DBIAS_SLP 0x0000001F +#define RTC_CNTL_REGULATOR0_DBIAS_SLP_M ((RTC_CNTL_REGULATOR0_DBIAS_SLP_V)<<(RTC_CNTL_REGULATOR0_DBIAS_SLP_S)) +#define RTC_CNTL_REGULATOR0_DBIAS_SLP_V 0x1F +#define RTC_CNTL_REGULATOR0_DBIAS_SLP_S 20 +/* RTC_CNTL_PVT_RTC_DBIAS : RO ;bitpos:[19:15] ;default: 5'b10100 ; */ +/*description: get pvt dbias value.*/ +#define RTC_CNTL_PVT_RTC_DBIAS 0x0000001F +#define RTC_CNTL_PVT_RTC_DBIAS_M ((RTC_CNTL_PVT_RTC_DBIAS_V)<<(RTC_CNTL_PVT_RTC_DBIAS_S)) +#define RTC_CNTL_PVT_RTC_DBIAS_V 0x1F +#define RTC_CNTL_PVT_RTC_DBIAS_S 15 + +#define RTC_CNTL_REGULATOR1_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x88) +/* RTC_CNTL_REGULATOR1_DBIAS_ACTIVE : R/W ;bitpos:[28:25] ;default: 4'b1000 ; */ +/*description: the rtc regulator1 dbias when chip in active state.*/ +#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE 0x0000000F +#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_M ((RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_V)<<(RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_S)) +#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_V 0xF +#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_S 25 +/* RTC_CNTL_REGULATOR1_DBIAS_SLP : R/W ;bitpos:[23:20] ;default: 4'b1000 ; */ +/*description: the rtc regulator1 dbias when chip in sleep state.*/ +#define RTC_CNTL_REGULATOR1_DBIAS_SLP 0x0000000F +#define RTC_CNTL_REGULATOR1_DBIAS_SLP_M ((RTC_CNTL_REGULATOR1_DBIAS_SLP_V)<<(RTC_CNTL_REGULATOR1_DBIAS_SLP_S)) +#define RTC_CNTL_REGULATOR1_DBIAS_SLP_V 0xF +#define RTC_CNTL_REGULATOR1_DBIAS_SLP_S 20 + +#define RTC_CNTL_DIG_REGULATOR_REG (DR_REG_RTCCNTL_BASE + 0x8C) +/* RTC_CNTL_DG_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_REGULATOR_FORCE_PU (BIT(31)) +#define RTC_CNTL_DG_REGULATOR_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_DG_REGULATOR_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_REGULATOR_FORCE_PU_S 31 +/* RTC_CNTL_DG_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_REGULATOR_FORCE_PD (BIT(30)) +#define RTC_CNTL_DG_REGULATOR_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_DG_REGULATOR_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_REGULATOR_FORCE_PD_S 30 +/* RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU (BIT(29)) +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU_S 29 +/* RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD (BIT(28)) +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD_S 28 +/* RTC_CNTL_DG_VDD_DRV_B_SLP_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN (BIT(27)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M (BIT(27)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V 0x1 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S 27 +/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[26:3] ;default: 24'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_VDD_DRV_B_SLP 0x00FFFFFF +#define RTC_CNTL_DG_VDD_DRV_B_SLP_M ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0xFFFFFF +#define RTC_CNTL_DG_VDD_DRV_B_SLP_S 3 +/* RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PU (BIT(2)) +#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PU_M (BIT(2)) +#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PU_V 0x1 +#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PU_S 2 +/* RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PD (BIT(1)) +#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PD_M (BIT(1)) +#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PD_V 0x1 +#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PD_S 1 + +#define RTC_CNTL_DIG_REGULATOR_DRVB_REG (DR_REG_RTCCNTL_BASE + 0x90) +/* RTC_CNTL_DG_VDD_DRV_B_ACTIVE : R/W ;bitpos:[23:0] ;default: 24'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE 0x00FFFFFF +#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE_M ((RTC_CNTL_DG_VDD_DRV_B_ACTIVE_V)<<(RTC_CNTL_DG_VDD_DRV_B_ACTIVE_S)) +#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE_V 0xFFFFFF +#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE_S 0 + +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x94) +/* RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: 1: select sw dbias_active 0: select pvt value.*/ +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL (BIT(31)) +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL_M (BIT(31)) +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL_V 0x1 +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL_S 31 +/* RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT : WO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: initial pvt dbias value.*/ +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT (BIT(30)) +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT_M (BIT(30)) +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT_V 0x1 +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT_S 30 +/* RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE : R/W ;bitpos:[29:25] ;default: 5'b10100 ; */ +/*description: the dig regulator0 dbias when chip in active state.*/ +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE 0x0000001F +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_M ((RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_V)<<(RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_S)) +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_V 0x1F +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_S 25 +/* RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP : R/W ;bitpos:[24:20] ;default: 5'b10100 ; */ +/*description: the dig regulator0 dbias when chip in sleep state.*/ +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP 0x0000001F +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_M ((RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_V)<<(RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_S)) +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_V 0x1F +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_S 20 +/* RTC_CNTL_PVT_DIG_DBIAS : RO ;bitpos:[19:15] ;default: 5'b10100 ; */ +/*description: get pvt dbias value.*/ +#define RTC_CNTL_PVT_DIG_DBIAS 0x0000001F +#define RTC_CNTL_PVT_DIG_DBIAS_M ((RTC_CNTL_PVT_DIG_DBIAS_V)<<(RTC_CNTL_PVT_DIG_DBIAS_S)) +#define RTC_CNTL_PVT_DIG_DBIAS_V 0x1F +#define RTC_CNTL_PVT_DIG_DBIAS_S 15 + +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x98) +/* RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE : R/W ;bitpos:[28:25] ;default: 4'b1000 ; */ +/*description: the dig regulator1 dbias when chip in active state.*/ +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE 0x0000000F +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_M ((RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_V)<<(RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_S)) +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_V 0xF +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_S 25 +/* RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP : R/W ;bitpos:[23:20] ;default: 4'b1000 ; */ +/*description: the dig regulator1 dbias when chip in sleep state.*/ +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP 0x0000000F +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_M ((RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_V)<<(RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_S)) +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_V 0xF +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_S 20 +/* RTC_CNTL_MEM_REGULATOR1_DBIAS_ACTIVE : R/W ;bitpos:[19:16] ;default: 4'b1000 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_MEM_REGULATOR1_DBIAS_ACTIVE 0x0000000F +#define RTC_CNTL_MEM_REGULATOR1_DBIAS_ACTIVE_M ((RTC_CNTL_MEM_REGULATOR1_DBIAS_ACTIVE_V)<<(RTC_CNTL_MEM_REGULATOR1_DBIAS_ACTIVE_S)) +#define RTC_CNTL_MEM_REGULATOR1_DBIAS_ACTIVE_V 0xF +#define RTC_CNTL_MEM_REGULATOR1_DBIAS_ACTIVE_S 16 +/* RTC_CNTL_MEM_REGULATOR1_DBIAS_SLP : R/W ;bitpos:[15:12] ;default: 4'b1000 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_MEM_REGULATOR1_DBIAS_SLP 0x0000000F +#define RTC_CNTL_MEM_REGULATOR1_DBIAS_SLP_M ((RTC_CNTL_MEM_REGULATOR1_DBIAS_SLP_V)<<(RTC_CNTL_MEM_REGULATOR1_DBIAS_SLP_S)) +#define RTC_CNTL_MEM_REGULATOR1_DBIAS_SLP_V 0xF +#define RTC_CNTL_MEM_REGULATOR1_DBIAS_SLP_S 12 + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x9C) +/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: rtc pad force hold.*/ +#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_PAD_FORCE_HOLD_S 21 + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0xA0) +/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 +/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable power down wifi in sleep.*/ +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_V 0x1 +#define RTC_CNTL_WIFI_PD_EN_S 30 +/* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_CPU_TOP_PD_EN (BIT(29)) +#define RTC_CNTL_CPU_TOP_PD_EN_M (BIT(29)) +#define RTC_CNTL_CPU_TOP_PD_EN_V 0x1 +#define RTC_CNTL_CPU_TOP_PD_EN_S 29 +/* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_PERI_PD_EN (BIT(28)) +#define RTC_CNTL_DG_PERI_PD_EN_M (BIT(28)) +#define RTC_CNTL_DG_PERI_PD_EN_V 0x1 +#define RTC_CNTL_DG_PERI_PD_EN_S 28 +/* RTC_CNTL_BT_PD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BT_PD_EN (BIT(27)) +#define RTC_CNTL_BT_PD_EN_M (BIT(27)) +#define RTC_CNTL_BT_PD_EN_V 0x1 +#define RTC_CNTL_BT_PD_EN_S 27 +/* RTC_CNTL_DG_WRAP_RET_PD_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_WRAP_RET_PD_EN (BIT(26)) +#define RTC_CNTL_DG_WRAP_RET_PD_EN_M (BIT(26)) +#define RTC_CNTL_DG_WRAP_RET_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_RET_PD_EN_S 26 +/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) +#define RTC_CNTL_CPU_TOP_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_CPU_TOP_FORCE_PU_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_PU_S 22 +/* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21)) +#define RTC_CNTL_CPU_TOP_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_PD_S 21 +/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ +/*description: wifi force power up.*/ +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 +/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: wifi force power down.*/ +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 +/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(16)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(16)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 16 +/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(15)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(15)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 15 +/* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14)) +#define RTC_CNTL_DG_PERI_FORCE_PU_M (BIT(14)) +#define RTC_CNTL_DG_PERI_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_PU_S 14 +/* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13)) +#define RTC_CNTL_DG_PERI_FORCE_PD_M (BIT(13)) +#define RTC_CNTL_DG_PERI_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_PD_S 13 +/* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BT_FORCE_PU (BIT(12)) +#define RTC_CNTL_BT_FORCE_PU_M (BIT(12)) +#define RTC_CNTL_BT_FORCE_PU_V 0x1 +#define RTC_CNTL_BT_FORCE_PU_S 12 +/* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BT_FORCE_PD (BIT(11)) +#define RTC_CNTL_BT_FORCE_PD_M (BIT(11)) +#define RTC_CNTL_BT_FORCE_PD_V 0x1 +#define RTC_CNTL_BT_FORCE_PD_S 11 +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(10)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(10)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 10 +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(9)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(9)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 9 +/* RTC_CNTL_DG_MEM_FORCE_PU : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_MEM_FORCE_PU (BIT(8)) +#define RTC_CNTL_DG_MEM_FORCE_PU_M (BIT(8)) +#define RTC_CNTL_DG_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_MEM_FORCE_PU_S 8 +/* RTC_CNTL_DG_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_MEM_FORCE_PD (BIT(7)) +#define RTC_CNTL_DG_MEM_FORCE_PD_M (BIT(7)) +#define RTC_CNTL_DG_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_MEM_FORCE_PD_S 7 +/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: memories in digital core force no PD in sleep.*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 +/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: memories in digital core force PD in sleep.*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 +/* RTC_CNTL_VDD_SPI_PWR_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VDD_SPI_PWR_FORCE (BIT(2)) +#define RTC_CNTL_VDD_SPI_PWR_FORCE_M (BIT(2)) +#define RTC_CNTL_VDD_SPI_PWR_FORCE_V 0x1 +#define RTC_CNTL_VDD_SPI_PWR_FORCE_S 2 +/* RTC_CNTL_VDD_SPI_PWR_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VDD_SPI_PWR_DRV 0x00000003 +#define RTC_CNTL_VDD_SPI_PWR_DRV_M ((RTC_CNTL_VDD_SPI_PWR_DRV_V)<<(RTC_CNTL_VDD_SPI_PWR_DRV_S)) +#define RTC_CNTL_VDD_SPI_PWR_DRV_V 0x3 +#define RTC_CNTL_VDD_SPI_PWR_DRV_S 0 + +#define RTC_CNTL_DIG_POWER_SLAVE0_PD_REG (DR_REG_RTCCNTL_BASE + 0xA4) +/* RTC_CNTL_PD_MEM_SWITCH_MASK : R/W ;bitpos:[31:12] ;default: 20'h0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_PD_MEM_SWITCH_MASK 0x000FFFFF +#define RTC_CNTL_PD_MEM_SWITCH_MASK_M ((RTC_CNTL_PD_MEM_SWITCH_MASK_V)<<(RTC_CNTL_PD_MEM_SWITCH_MASK_S)) +#define RTC_CNTL_PD_MEM_SWITCH_MASK_V 0xFFFFF +#define RTC_CNTL_PD_MEM_SWITCH_MASK_S 12 +/* RTC_CNTL_PD_DG_WRAP_SWITCH_MASK : R/W ;bitpos:[11:7] ;default: 5'h0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_PD_DG_WRAP_SWITCH_MASK 0x0000001F +#define RTC_CNTL_PD_DG_WRAP_SWITCH_MASK_M ((RTC_CNTL_PD_DG_WRAP_SWITCH_MASK_V)<<(RTC_CNTL_PD_DG_WRAP_SWITCH_MASK_S)) +#define RTC_CNTL_PD_DG_WRAP_SWITCH_MASK_V 0x1F +#define RTC_CNTL_PD_DG_WRAP_SWITCH_MASK_S 7 +/* RTC_CNTL_PD_DG_PERI_SWITCH_MASK : R/W ;bitpos:[6:2] ;default: 5'h0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_PD_DG_PERI_SWITCH_MASK 0x0000001F +#define RTC_CNTL_PD_DG_PERI_SWITCH_MASK_M ((RTC_CNTL_PD_DG_PERI_SWITCH_MASK_V)<<(RTC_CNTL_PD_DG_PERI_SWITCH_MASK_S)) +#define RTC_CNTL_PD_DG_PERI_SWITCH_MASK_V 0x1F +#define RTC_CNTL_PD_DG_PERI_SWITCH_MASK_S 2 + +#define RTC_CNTL_DIG_POWER_SLAVE1_PD_REG (DR_REG_RTCCNTL_BASE + 0xA8) +/* RTC_CNTL_PD_CPU_SWITCH_MASK : R/W ;bitpos:[31:27] ;default: 5'h0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_PD_CPU_SWITCH_MASK 0x0000001F +#define RTC_CNTL_PD_CPU_SWITCH_MASK_M ((RTC_CNTL_PD_CPU_SWITCH_MASK_V)<<(RTC_CNTL_PD_CPU_SWITCH_MASK_S)) +#define RTC_CNTL_PD_CPU_SWITCH_MASK_V 0x1F +#define RTC_CNTL_PD_CPU_SWITCH_MASK_S 27 +/* RTC_CNTL_PD_WIFI_SWITCH_MASK : R/W ;bitpos:[26:22] ;default: 5'h0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_PD_WIFI_SWITCH_MASK 0x0000001F +#define RTC_CNTL_PD_WIFI_SWITCH_MASK_M ((RTC_CNTL_PD_WIFI_SWITCH_MASK_V)<<(RTC_CNTL_PD_WIFI_SWITCH_MASK_S)) +#define RTC_CNTL_PD_WIFI_SWITCH_MASK_V 0x1F +#define RTC_CNTL_PD_WIFI_SWITCH_MASK_S 22 + +#define RTC_CNTL_DIG_POWER_SLAVE0_FPU_REG (DR_REG_RTCCNTL_BASE + 0xAC) +/* RTC_CNTL_XPD_MEM_SWITCH_MASK : R/W ;bitpos:[31:12] ;default: 20'hfffff ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XPD_MEM_SWITCH_MASK 0x000FFFFF +#define RTC_CNTL_XPD_MEM_SWITCH_MASK_M ((RTC_CNTL_XPD_MEM_SWITCH_MASK_V)<<(RTC_CNTL_XPD_MEM_SWITCH_MASK_S)) +#define RTC_CNTL_XPD_MEM_SWITCH_MASK_V 0xFFFFF +#define RTC_CNTL_XPD_MEM_SWITCH_MASK_S 12 +/* RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK : R/W ;bitpos:[11:7] ;default: 5'h1f ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK 0x0000001F +#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_M ((RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_V)<<(RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_S)) +#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_V 0x1F +#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_S 7 +/* RTC_CNTL_XPD_DG_PERI_SWITCH_MASK : R/W ;bitpos:[6:2] ;default: 5'h1f ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK 0x0000001F +#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_M ((RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_V)<<(RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_S)) +#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_V 0x1F +#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_S 2 + +#define RTC_CNTL_DIG_POWER_SLAVE1_FPU_REG (DR_REG_RTCCNTL_BASE + 0xB0) +/* RTC_CNTL_XPD_CPU_SWITCH_MASK : R/W ;bitpos:[31:27] ;default: 5'h1f ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XPD_CPU_SWITCH_MASK 0x0000001F +#define RTC_CNTL_XPD_CPU_SWITCH_MASK_M ((RTC_CNTL_XPD_CPU_SWITCH_MASK_V)<<(RTC_CNTL_XPD_CPU_SWITCH_MASK_S)) +#define RTC_CNTL_XPD_CPU_SWITCH_MASK_V 0x1F +#define RTC_CNTL_XPD_CPU_SWITCH_MASK_S 27 +/* RTC_CNTL_XPD_WIFI_SWITCH_MASK : R/W ;bitpos:[26:22] ;default: 5'h1f ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XPD_WIFI_SWITCH_MASK 0x0000001F +#define RTC_CNTL_XPD_WIFI_SWITCH_MASK_M ((RTC_CNTL_XPD_WIFI_SWITCH_MASK_V)<<(RTC_CNTL_XPD_WIFI_SWITCH_MASK_S)) +#define RTC_CNTL_XPD_WIFI_SWITCH_MASK_V 0x1F +#define RTC_CNTL_XPD_WIFI_SWITCH_MASK_S 22 + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0xB4) +/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force ISO.*/ +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 +/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: wifi force no ISO.*/ +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 +/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: wifi force ISO.*/ +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 +/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: cpu force no ISO.*/ +#define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S 27 +/* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: cpu force ISO.*/ +#define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26)) +#define RTC_CNTL_CPU_TOP_FORCE_ISO_M (BIT(26)) +#define RTC_CNTL_CPU_TOP_FORCE_ISO_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_ISO_S 26 +/* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_DG_PERI_FORCE_NOISO_M (BIT(25)) +#define RTC_CNTL_DG_PERI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_NOISO_S 25 +/* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24)) +#define RTC_CNTL_DG_PERI_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_ISO_S 24 +/* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BT_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_BT_FORCE_NOISO_M (BIT(23)) +#define RTC_CNTL_BT_FORCE_NOISO_V 0x1 +#define RTC_CNTL_BT_FORCE_NOISO_S 23 +/* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BT_FORCE_ISO (BIT(22)) +#define RTC_CNTL_BT_FORCE_ISO_M (BIT(22)) +#define RTC_CNTL_BT_FORCE_ISO_V 0x1 +#define RTC_CNTL_BT_FORCE_ISO_S 22 +/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: digital pad force hold.*/ +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 +/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: digital pad force un-hold.*/ +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 +/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: digital pad force ISO.*/ +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 +/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: digital pad force no ISO.*/ +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 +/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: digital pad enable auto-hold.*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 +/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: wtite only register to clear digital pad auto-hold.*/ +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 +/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: read only register to indicate digital pad auto-hold status.*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 +/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 +/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 +/* RTC_CNTL_DG_MEM_FORCE_ISO : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_MEM_FORCE_ISO (BIT(6)) +#define RTC_CNTL_DG_MEM_FORCE_ISO_M (BIT(6)) +#define RTC_CNTL_DG_MEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_MEM_FORCE_ISO_S 6 +/* RTC_CNTL_DG_MEM_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DG_MEM_FORCE_NOISO (BIT(5)) +#define RTC_CNTL_DG_MEM_FORCE_NOISO_M (BIT(5)) +#define RTC_CNTL_DG_MEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_MEM_FORCE_NOISO_S 5 + +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0xB8) +/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (BIT(31)) +#define RTC_CNTL_WDT_EN_V 0x1 +#define RTC_CNTL_WDT_EN_S 31 +/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC r +eset stage en.*/ +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) +#define RTC_CNTL_WDT_STG0_V 0x7 +#define RTC_CNTL_WDT_STG0_S 28 +/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC r +eset stage en.*/ +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) +#define RTC_CNTL_WDT_STG1_V 0x7 +#define RTC_CNTL_WDT_STG1_S 25 +/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC r +eset stage en.*/ +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) +#define RTC_CNTL_WDT_STG2_V 0x7 +#define RTC_CNTL_WDT_STG2_S 22 +/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC r +eset stage en.*/ +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) +#define RTC_CNTL_WDT_STG3_V 0x7 +#define RTC_CNTL_WDT_STG3_S 19 +/* RTC_CNTL_WDT_STGX : */ +/*description: stage action selection values */ +#define RTC_WDT_STG_SEL_OFF 0 +#define RTC_WDT_STG_SEL_INT 1 +#define RTC_WDT_STG_SEL_RESET_CPU 2 +#define RTC_WDT_STG_SEL_RESET_SYSTEM 3 +#define RTC_WDT_STG_SEL_RESET_RTC 4 + +/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ +/*description: CPU reset counter length.*/ +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 +/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */ +/*description: system reset counter length.*/ +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 +/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: enable WDT in flash boot.*/ +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 +/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: enable WDT reset PRO CPU.*/ +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 +/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable WDT reset APP CPU.*/ +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 +/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: pause WDT in sleep.*/ +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 +/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: wdt reset whole chip enable.*/ +#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 +/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ +/*description: chip reset siginal pulse width.*/ +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 + +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0xBC) +/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0xC0) +/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0xC4) +/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: Need add description.*/ +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0xC8) +/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: Need add description.*/ +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 + +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xCC) +/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (BIT(31)) +#define RTC_CNTL_WDT_FEED_V 0x1 +#define RTC_CNTL_WDT_FEED_S 31 + +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xD0) +/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 + +#define RTC_CNTL_WDTRESET_CHIP_REG (DR_REG_RTCCNTL_BASE + 0xD4) +/* RTC_CNTL_RESET_CHIP_KEY : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_RESET_CHIP_KEY 0x000000FF +#define RTC_CNTL_RESET_CHIP_KEY_M ((RTC_CNTL_RESET_CHIP_KEY_V)<<(RTC_CNTL_RESET_CHIP_KEY_S)) +#define RTC_CNTL_RESET_CHIP_KEY_V 0xFF +#define RTC_CNTL_RESET_CHIP_KEY_S 24 +/* RTC_CNTL_RESET_CHIP_TARGET : R/W ;bitpos:[23:16] ;default: 8'ha5 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_RESET_CHIP_TARGET 0x000000FF +#define RTC_CNTL_RESET_CHIP_TARGET_M ((RTC_CNTL_RESET_CHIP_TARGET_V)<<(RTC_CNTL_RESET_CHIP_TARGET_S)) +#define RTC_CNTL_RESET_CHIP_TARGET_V 0xFF +#define RTC_CNTL_RESET_CHIP_TARGET_S 16 + +#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xD8) +/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: automatically feed swd when int comes.*/ +#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 +#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 +/* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: disabel SWD.*/ +#define RTC_CNTL_SWD_DISABLE (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_M (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_V 0x1 +#define RTC_CNTL_SWD_DISABLE_S 30 +/* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Sw feed swd.*/ +#define RTC_CNTL_SWD_FEED (BIT(29)) +#define RTC_CNTL_SWD_FEED_M (BIT(29)) +#define RTC_CNTL_SWD_FEED_V 0x1 +#define RTC_CNTL_SWD_FEED_S 29 +/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: reset swd reset flag.*/ +#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 +#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 +/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ +/*description: adjust signal width send to swd.*/ +#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S)) +#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 +/* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) +#define RTC_CNTL_SWD_BYPASS_RST_M (BIT(17)) +#define RTC_CNTL_SWD_BYPASS_RST_V 0x1 +#define RTC_CNTL_SWD_BYPASS_RST_S 17 +/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: swd interrupt for feeding.*/ +#define RTC_CNTL_SWD_FEED_INT (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_V 0x1 +#define RTC_CNTL_SWD_FEED_INT_S 1 +/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: swd reset flag.*/ +#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_V 0x1 +#define RTC_CNTL_SWD_RESET_FLAG_S 0 + +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xDC) +/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: swd write protect.*/ +#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) +#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_S 0 + +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xE0) +/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 +/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall A +PP CPU.*/ +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 + +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xE4) +/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 + +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xE8) +/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 + +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xEC) +/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 + +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xF0) +/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 + +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xF4) +/* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ +/*description: rtc main state machine status.*/ +#define RTC_CNTL_MAIN_STATE 0x0000000F +#define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S)) +#define RTC_CNTL_MAIN_STATE_V 0xF +#define RTC_CNTL_MAIN_STATE_S 28 +/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: rtc main state machine is in idle state.*/ +#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 +/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: rtc main state machine is in sleep state.*/ +#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait xtal state.*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait pll state.*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait 8m state.*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 +/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: rtc main state machine is in the states of low power.*/ +#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 +#define RTC_CNTL_IN_LOW_POWER_STATE_S 22 +/* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: rtc main state machine is in the states of wakeup process.*/ +#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 +#define RTC_CNTL_IN_WAKEUP_STATE_S 21 +/* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: rtc main state machine has been waited for some cycles.*/ +#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 +#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 +/* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: rtc is ready to receive wake up trigger from wake up source.*/ +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 +#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 +/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: rtc main state machine is in states that pll should be running.*/ +#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 +#define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 +/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: no use any more.*/ +#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 +/* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: ulp/cocpu is done.*/ +#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_V 0x1 +#define RTC_CNTL_COCPU_STATE_DONE_S 16 +/* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: ulp/cocpu is in sleep state.*/ +#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_V 0x1 +#define RTC_CNTL_COCPU_STATE_SLP_S 15 +/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: ulp/cocpu is about to working. Switch rtc main state.*/ +#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 +#define RTC_CNTL_COCPU_STATE_SWITCH_S 14 +/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: ulp/cocpu should start to work.*/ +#define RTC_CNTL_COCPU_STATE_START (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_V 0x1 +#define RTC_CNTL_COCPU_STATE_START_S 13 +/* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: touch is done.*/ +#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 +#define RTC_CNTL_TOUCH_STATE_DONE_S 12 +/* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: touch is in sleep state.*/ +#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SLP_S 11 +/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: touch is about to working. Switch rtc main state.*/ +#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 +/* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: touch should start to work.*/ +#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_V 0x1 +#define RTC_CNTL_TOUCH_STATE_START_S 9 +/* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: digital wrap power down.*/ +#define RTC_CNTL_XPD_DIG (BIT(8)) +#define RTC_CNTL_XPD_DIG_M (BIT(8)) +#define RTC_CNTL_XPD_DIG_V 0x1 +#define RTC_CNTL_XPD_DIG_S 8 +/* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: digital wrap iso.*/ +#define RTC_CNTL_DIG_ISO (BIT(7)) +#define RTC_CNTL_DIG_ISO_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_V 0x1 +#define RTC_CNTL_DIG_ISO_S 7 +/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: wifi wrap power down.*/ +#define RTC_CNTL_XPD_WIFI (BIT(6)) +#define RTC_CNTL_XPD_WIFI_M (BIT(6)) +#define RTC_CNTL_XPD_WIFI_V 0x1 +#define RTC_CNTL_XPD_WIFI_S 6 +/* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: wifi iso.*/ +#define RTC_CNTL_WIFI_ISO (BIT(5)) +#define RTC_CNTL_WIFI_ISO_M (BIT(5)) +#define RTC_CNTL_WIFI_ISO_V 0x1 +#define RTC_CNTL_WIFI_ISO_S 5 +/* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: rtc peripheral power down.*/ +#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_V 0x1 +#define RTC_CNTL_XPD_RTC_PERI_S 4 +/* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: rtc peripheral iso.*/ +#define RTC_CNTL_PERI_ISO (BIT(3)) +#define RTC_CNTL_PERI_ISO_M (BIT(3)) +#define RTC_CNTL_PERI_ISO_V 0x1 +#define RTC_CNTL_PERI_ISO_S 3 +/* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: External DCDC power down.*/ +#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_V 0x1 +#define RTC_CNTL_XPD_DIG_DCDC_S 2 +/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: rom0 power down.*/ +#define RTC_CNTL_XPD_ROM0 (BIT(0)) +#define RTC_CNTL_XPD_ROM0_M (BIT(0)) +#define RTC_CNTL_XPD_ROM0_V 0x1 +#define RTC_CNTL_XPD_ROM0_S 0 + +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xF8) +/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 + +#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xFC) +/* RTC_CNTL_GPIO_PIN5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN5_HOLD (BIT(5)) +#define RTC_CNTL_GPIO_PIN5_HOLD_M (BIT(5)) +#define RTC_CNTL_GPIO_PIN5_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN5_HOLD_S 5 +/* RTC_CNTL_GPIO_PIN4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN4_HOLD (BIT(4)) +#define RTC_CNTL_GPIO_PIN4_HOLD_M (BIT(4)) +#define RTC_CNTL_GPIO_PIN4_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN4_HOLD_S 4 +/* RTC_CNTL_GPIO_PIN3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN3_HOLD (BIT(3)) +#define RTC_CNTL_GPIO_PIN3_HOLD_M (BIT(3)) +#define RTC_CNTL_GPIO_PIN3_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN3_HOLD_S 3 +/* RTC_CNTL_GPIO_PIN2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN2_HOLD (BIT(2)) +#define RTC_CNTL_GPIO_PIN2_HOLD_M (BIT(2)) +#define RTC_CNTL_GPIO_PIN2_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN2_HOLD_S 2 +/* RTC_CNTL_GPIO_PIN1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN1_HOLD (BIT(1)) +#define RTC_CNTL_GPIO_PIN1_HOLD_M (BIT(1)) +#define RTC_CNTL_GPIO_PIN1_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN1_HOLD_S 1 +/* RTC_CNTL_GPIO_PIN0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN0_HOLD (BIT(0)) +#define RTC_CNTL_GPIO_PIN0_HOLD_M (BIT(0)) +#define RTC_CNTL_GPIO_PIN0_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN0_HOLD_S 0 + +#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x100) +/* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S)) +#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_S 0 + +#define RTC_CNTL_DIG_PAD_HOLD1_REG (DR_REG_RTCCNTL_BASE + 0x104) +/* RTC_CNTL_DIG_PAD_HOLD1 : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DIG_PAD_HOLD1 0x000001FF +#define RTC_CNTL_DIG_PAD_HOLD1_M ((RTC_CNTL_DIG_PAD_HOLD1_V)<<(RTC_CNTL_DIG_PAD_HOLD1_S)) +#define RTC_CNTL_DIG_PAD_HOLD1_V 0x1FF +#define RTC_CNTL_DIG_PAD_HOLD1_S 0 + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x108) +/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_V 0x1 +#define RTC_CNTL_BROWN_OUT_DET_S 31 +/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: enable brown out.*/ +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 +/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: clear brown out counter.*/ +#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 +/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28)) +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1 +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 +/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 1: 4-pos reset, 0: sys_reset.*/ +#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 +/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable brown out reset.*/ +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 +/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ +/*description: brown out reset wait cycles.*/ +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 +/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable power down RF when brown out happens.*/ +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 +/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable close flash when brown out happens.*/ +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 +/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */ +/*description: brown out interrupt wait cycles.*/ +#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 + +#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x10C) +/* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits.*/ +#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S)) +#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_S 0 + +#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x110) +/* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits.*/ +#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 + +#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x114) +/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: xtal 32k watch dog backup clock factor.*/ +#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S)) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 + +#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x118) +/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: if restarted xtal32k period is smaller than this, it is regarded as stable.*/ +#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F +#define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S)) +#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF +#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 +/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ +/*description: If no clock detected for this amount of time, 32k is regarded as dead.*/ +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 +/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ +/*description: cycles to wait to repower on xtal 32k.*/ +#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S)) +#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 +/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: cycles to wait to return noral xtal 32k.*/ +#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F +#define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) +#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF +#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 + +#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x11C) +/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 +#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 + +#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x120) +/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[18:0] ;default: 19'd0 ; */ +/*description: sleep reject cause.*/ +#define RTC_CNTL_REJECT_CAUSE 0x0007FFFF +#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) +#define RTC_CNTL_REJECT_CAUSE_V 0x7FFFF +#define RTC_CNTL_REJECT_CAUSE_S 0 + +#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x124) +/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 + +#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x128) +/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[18:0] ;default: 19'd0 ; */ +/*description: sleep wakeup cause.*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x0007FFFF +#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x7FFFF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x12C) +/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ +/*description: sleep cycles for ULP-coprocessor timer.*/ +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 + +#define RTC_CNTL_INT_ENA_RTC_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x130) +/* RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS_M (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS_S 22 +/* RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS_M (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS_S 21 +/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enbale gitch det interrupt.*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 +/* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt.*/ +#define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TS_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt.*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 +/* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt.*/ +#define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TS_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 +/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt.*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 + +#define RTC_CNTL_INT_ENA_RTC_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x134) +/* RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC_M (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC_S 22 +/* RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC_M (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC_S 21 +/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enbale gitch det interrupt.*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 +/* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt.*/ +#define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TC_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt.*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 +/* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt.*/ +#define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TC_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 +/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt.*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 + +#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x138) +/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */ +/*description: wait cycles for rention operation.*/ +#define RTC_CNTL_RETENTION_WAIT 0x0000001F +#define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S)) +#define RTC_CNTL_RETENTION_WAIT_V 0x1F +#define RTC_CNTL_RETENTION_WAIT_S 27 +/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_RETENTION_EN (BIT(26)) +#define RTC_CNTL_RETENTION_EN_M (BIT(26)) +#define RTC_CNTL_RETENTION_EN_V 0x1 +#define RTC_CNTL_RETENTION_EN_S 26 +/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[25:22] ;default: 4'd3 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000F +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S)) +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V 0xF +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 22 +/* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[21:19] ;default: 3'd2 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007 +#define RTC_CNTL_RETENTION_DONE_WAIT_M ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S)) +#define RTC_CNTL_RETENTION_DONE_WAIT_V 0x7 +#define RTC_CNTL_RETENTION_DONE_WAIT_S 19 +/* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_RETENTION_CLK_SEL (BIT(18)) +#define RTC_CNTL_RETENTION_CLK_SEL_M (BIT(18)) +#define RTC_CNTL_RETENTION_CLK_SEL_V 0x1 +#define RTC_CNTL_RETENTION_CLK_SEL_S 18 +/* RTC_CNTL_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_CLK_EN (BIT(17)) +#define RTC_CNTL_CLK_EN_M (BIT(17)) +#define RTC_CNTL_CLK_EN_V 0x1 +#define RTC_CNTL_CLK_EN_S 17 + +#define RTC_CNTL_RETENTION_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x13C) +/* RTC_CNTL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_RETENTION_LINK_ADDR 0x07FFFFFF +#define RTC_CNTL_RETENTION_LINK_ADDR_M ((RTC_CNTL_RETENTION_LINK_ADDR_V)<<(RTC_CNTL_RETENTION_LINK_ADDR_S)) +#define RTC_CNTL_RETENTION_LINK_ADDR_V 0x7FFFFFF +#define RTC_CNTL_RETENTION_LINK_ADDR_S 0 + +#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x140) +/* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ +/*description: select use analog fib signal.*/ +#define RTC_CNTL_FIB_SEL 0x00000007 +#define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S)) +#define RTC_CNTL_FIB_SEL_V 0x7 +#define RTC_CNTL_FIB_SEL_S 0 + +#define RTC_CNTL_FIB_GLITCH_RST BIT(0) +#define RTC_CNTL_FIB_BOR_RST BIT(1) +#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) + +#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x144) +/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE (BIT(31)) +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(31)) +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S 31 +/* RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE (BIT(30)) +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(30)) +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S 30 +/* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE (BIT(29)) +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(29)) +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S 29 +/* RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE (BIT(28)) +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(28)) +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S 28 +/* RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE (BIT(27)) +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(27)) +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S 27 +/* RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE (BIT(26)) +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(26)) +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S 26 +/* RTC_CNTL_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[25:23] ;default: 3'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN0_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN0_INT_TYPE_M ((RTC_CNTL_GPIO_PIN0_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN0_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN0_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN0_INT_TYPE_S 23 +/* RTC_CNTL_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN1_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN1_INT_TYPE_M ((RTC_CNTL_GPIO_PIN1_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN1_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN1_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN1_INT_TYPE_S 20 +/* RTC_CNTL_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[19:17] ;default: 3'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN2_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN2_INT_TYPE_M ((RTC_CNTL_GPIO_PIN2_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN2_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN2_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN2_INT_TYPE_S 17 +/* RTC_CNTL_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[16:14] ;default: 3'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN3_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN3_INT_TYPE_M ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN3_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN3_INT_TYPE_S 14 +/* RTC_CNTL_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[13:11] ;default: 3'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN4_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN4_INT_TYPE_M ((RTC_CNTL_GPIO_PIN4_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN4_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN4_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN4_INT_TYPE_S 11 +/* RTC_CNTL_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[10:8] ;default: 3'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN5_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN5_INT_TYPE_M ((RTC_CNTL_GPIO_PIN5_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN5_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN5_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN5_INT_TYPE_S 8 +/* RTC_CNTL_GPIO_PIN_CLK_GATE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN_CLK_GATE (BIT(7)) +#define RTC_CNTL_GPIO_PIN_CLK_GATE_M (BIT(7)) +#define RTC_CNTL_GPIO_PIN_CLK_GATE_V 0x1 +#define RTC_CNTL_GPIO_PIN_CLK_GATE_S 7 +/* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR (BIT(6)) +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M (BIT(6)) +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S 6 +/* RTC_CNTL_GPIO_WAKEUP_STATUS : RO ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_WAKEUP_STATUS 0x0000003F +#define RTC_CNTL_GPIO_WAKEUP_STATUS_M ((RTC_CNTL_GPIO_WAKEUP_STATUS_V)<<(RTC_CNTL_GPIO_WAKEUP_STATUS_S)) +#define RTC_CNTL_GPIO_WAKEUP_STATUS_V 0x3F +#define RTC_CNTL_GPIO_WAKEUP_STATUS_S 0 + +#define RTC_CNTL_DBG_SEL_REG (DR_REG_RTCCNTL_BASE + 0x148) +/* RTC_CNTL_DEBUG_SEL4 : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DEBUG_SEL4 0x0000001F +#define RTC_CNTL_DEBUG_SEL4_M ((RTC_CNTL_DEBUG_SEL4_V)<<(RTC_CNTL_DEBUG_SEL4_S)) +#define RTC_CNTL_DEBUG_SEL4_V 0x1F +#define RTC_CNTL_DEBUG_SEL4_S 27 +/* RTC_CNTL_DEBUG_SEL3 : R/W ;bitpos:[26:22] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DEBUG_SEL3 0x0000001F +#define RTC_CNTL_DEBUG_SEL3_M ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S)) +#define RTC_CNTL_DEBUG_SEL3_V 0x1F +#define RTC_CNTL_DEBUG_SEL3_S 22 +/* RTC_CNTL_DEBUG_SEL2 : R/W ;bitpos:[21:17] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DEBUG_SEL2 0x0000001F +#define RTC_CNTL_DEBUG_SEL2_M ((RTC_CNTL_DEBUG_SEL2_V)<<(RTC_CNTL_DEBUG_SEL2_S)) +#define RTC_CNTL_DEBUG_SEL2_V 0x1F +#define RTC_CNTL_DEBUG_SEL2_S 17 +/* RTC_CNTL_DEBUG_SEL1 : R/W ;bitpos:[16:12] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DEBUG_SEL1 0x0000001F +#define RTC_CNTL_DEBUG_SEL1_M ((RTC_CNTL_DEBUG_SEL1_V)<<(RTC_CNTL_DEBUG_SEL1_S)) +#define RTC_CNTL_DEBUG_SEL1_V 0x1F +#define RTC_CNTL_DEBUG_SEL1_S 12 +/* RTC_CNTL_DEBUG_SEL0 : R/W ;bitpos:[11:7] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DEBUG_SEL0 0x0000001F +#define RTC_CNTL_DEBUG_SEL0_M ((RTC_CNTL_DEBUG_SEL0_V)<<(RTC_CNTL_DEBUG_SEL0_S)) +#define RTC_CNTL_DEBUG_SEL0_V 0x1F +#define RTC_CNTL_DEBUG_SEL0_S 7 +/* RTC_CNTL_DEBUG_BIT_SEL : R/W ;bitpos:[6:2] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DEBUG_BIT_SEL 0x0000001F +#define RTC_CNTL_DEBUG_BIT_SEL_M ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S)) +#define RTC_CNTL_DEBUG_BIT_SEL_V 0x1F +#define RTC_CNTL_DEBUG_BIT_SEL_S 2 +/* RTC_CNTL_DEBUG_12M_NO_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DEBUG_12M_NO_GATING (BIT(1)) +#define RTC_CNTL_DEBUG_12M_NO_GATING_M (BIT(1)) +#define RTC_CNTL_DEBUG_12M_NO_GATING_V 0x1 +#define RTC_CNTL_DEBUG_12M_NO_GATING_S 1 +/* RTC_CNTL_MTDI_ENAMUX : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_MTDI_ENAMUX (BIT(0)) +#define RTC_CNTL_MTDI_ENAMUX_M (BIT(0)) +#define RTC_CNTL_MTDI_ENAMUX_V 0x1 +#define RTC_CNTL_MTDI_ENAMUX_S 0 + +#define RTC_CNTL_DBG_MAP_REG (DR_REG_RTCCNTL_BASE + 0x14C) +/* RTC_CNTL_GPIO_PIN0_FUN_SEL : R/W ;bitpos:[31:28] ;default: 4'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN0_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN0_FUN_SEL_M ((RTC_CNTL_GPIO_PIN0_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN0_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN0_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN0_FUN_SEL_S 28 +/* RTC_CNTL_GPIO_PIN1_FUN_SEL : R/W ;bitpos:[27:24] ;default: 4'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN1_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN1_FUN_SEL_M ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN1_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN1_FUN_SEL_S 24 +/* RTC_CNTL_GPIO_PIN2_FUN_SEL : R/W ;bitpos:[23:20] ;default: 4'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN2_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN2_FUN_SEL_M ((RTC_CNTL_GPIO_PIN2_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN2_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN2_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN2_FUN_SEL_S 20 +/* RTC_CNTL_GPIO_PIN3_FUN_SEL : R/W ;bitpos:[19:16] ;default: 4'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN3_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN3_FUN_SEL_M ((RTC_CNTL_GPIO_PIN3_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN3_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN3_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN3_FUN_SEL_S 16 +/* RTC_CNTL_GPIO_PIN4_FUN_SEL : R/W ;bitpos:[15:12] ;default: 4'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN4_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN4_FUN_SEL_M ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN4_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN4_FUN_SEL_S 12 +/* RTC_CNTL_GPIO_PIN5_FUN_SEL : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN5_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN5_FUN_SEL_M ((RTC_CNTL_GPIO_PIN5_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN5_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN5_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN5_FUN_SEL_S 8 +/* RTC_CNTL_GPIO_PIN0_MUX_SEL : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN0_MUX_SEL (BIT(7)) +#define RTC_CNTL_GPIO_PIN0_MUX_SEL_M (BIT(7)) +#define RTC_CNTL_GPIO_PIN0_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN0_MUX_SEL_S 7 +/* RTC_CNTL_GPIO_PIN1_MUX_SEL : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN1_MUX_SEL (BIT(6)) +#define RTC_CNTL_GPIO_PIN1_MUX_SEL_M (BIT(6)) +#define RTC_CNTL_GPIO_PIN1_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN1_MUX_SEL_S 6 +/* RTC_CNTL_GPIO_PIN2_MUX_SEL : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN2_MUX_SEL (BIT(5)) +#define RTC_CNTL_GPIO_PIN2_MUX_SEL_M (BIT(5)) +#define RTC_CNTL_GPIO_PIN2_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN2_MUX_SEL_S 5 +/* RTC_CNTL_GPIO_PIN3_MUX_SEL : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN3_MUX_SEL (BIT(4)) +#define RTC_CNTL_GPIO_PIN3_MUX_SEL_M (BIT(4)) +#define RTC_CNTL_GPIO_PIN3_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN3_MUX_SEL_S 4 +/* RTC_CNTL_GPIO_PIN4_MUX_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN4_MUX_SEL (BIT(3)) +#define RTC_CNTL_GPIO_PIN4_MUX_SEL_M (BIT(3)) +#define RTC_CNTL_GPIO_PIN4_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN4_MUX_SEL_S 3 +/* RTC_CNTL_GPIO_PIN5_MUX_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_GPIO_PIN5_MUX_SEL (BIT(2)) +#define RTC_CNTL_GPIO_PIN5_MUX_SEL_M (BIT(2)) +#define RTC_CNTL_GPIO_PIN5_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN5_MUX_SEL_S 2 +/* RTC_CNTL_VDD_DIG_TEST : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VDD_DIG_TEST 0x00000003 +#define RTC_CNTL_VDD_DIG_TEST_M ((RTC_CNTL_VDD_DIG_TEST_V)<<(RTC_CNTL_VDD_DIG_TEST_S)) +#define RTC_CNTL_VDD_DIG_TEST_V 0x3 +#define RTC_CNTL_VDD_DIG_TEST_S 0 + +#define RTC_CNTL_DBG_SAR_SEL_REG (DR_REG_RTCCNTL_BASE + 0x150) +/* RTC_CNTL_SAR_DEBUG_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_SAR_DEBUG_SEL 0x0000001F +#define RTC_CNTL_SAR_DEBUG_SEL_M ((RTC_CNTL_SAR_DEBUG_SEL_V)<<(RTC_CNTL_SAR_DEBUG_SEL_S)) +#define RTC_CNTL_SAR_DEBUG_SEL_V 0x1F +#define RTC_CNTL_SAR_DEBUG_SEL_S 27 + +#define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x154) +/* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_POWER_GLITCH_EN (BIT(31)) +#define RTC_CNTL_POWER_GLITCH_EN_M (BIT(31)) +#define RTC_CNTL_POWER_GLITCH_EN_V 0x1 +#define RTC_CNTL_POWER_GLITCH_EN_S 31 +/* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL (BIT(30)) +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M (BIT(30)) +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V 0x1 +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S 30 +/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_POWER_GLITCH_FORCE_PU (BIT(29)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V 0x1 +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S 29 +/* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_POWER_GLITCH_FORCE_PD (BIT(28)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V 0x1 +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S 28 +/* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_POWER_GLITCH_DSENSE 0x00000003 +#define RTC_CNTL_POWER_GLITCH_DSENSE_M ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S)) +#define RTC_CNTL_POWER_GLITCH_DSENSE_V 0x3 +#define RTC_CNTL_POWER_GLITCH_DSENSE_S 26 + +#define RTC_CNTL_DCDC_CTRL0_REG (DR_REG_RTCCNTL_BASE + 0x158) +/* RTC_CNTL_POCPENB_DCDC : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_POCPENB_DCDC (BIT(31)) +#define RTC_CNTL_POCPENB_DCDC_M (BIT(31)) +#define RTC_CNTL_POCPENB_DCDC_V 0x1 +#define RTC_CNTL_POCPENB_DCDC_S 31 +/* RTC_CNTL_SSTIME_DCDC : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_SSTIME_DCDC (BIT(30)) +#define RTC_CNTL_SSTIME_DCDC_M (BIT(30)) +#define RTC_CNTL_SSTIME_DCDC_V 0x1 +#define RTC_CNTL_SSTIME_DCDC_S 30 +/* RTC_CNTL_CCM_DCDC : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_CCM_DCDC (BIT(29)) +#define RTC_CNTL_CCM_DCDC_M (BIT(29)) +#define RTC_CNTL_CCM_DCDC_V 0x1 +#define RTC_CNTL_CCM_DCDC_S 29 +/* RTC_CNTL_FSW_DCDC : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_FSW_DCDC 0x00000007 +#define RTC_CNTL_FSW_DCDC_M ((RTC_CNTL_FSW_DCDC_V)<<(RTC_CNTL_FSW_DCDC_S)) +#define RTC_CNTL_FSW_DCDC_V 0x7 +#define RTC_CNTL_FSW_DCDC_S 26 +/* RTC_CNTL_DCMLEVEL_DCDC : R/W ;bitpos:[25:24] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DCMLEVEL_DCDC 0x00000003 +#define RTC_CNTL_DCMLEVEL_DCDC_M ((RTC_CNTL_DCMLEVEL_DCDC_V)<<(RTC_CNTL_DCMLEVEL_DCDC_S)) +#define RTC_CNTL_DCMLEVEL_DCDC_V 0x3 +#define RTC_CNTL_DCMLEVEL_DCDC_S 24 +/* RTC_CNTL_DCM2ENB_DCDC : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DCM2ENB_DCDC (BIT(23)) +#define RTC_CNTL_DCM2ENB_DCDC_M (BIT(23)) +#define RTC_CNTL_DCM2ENB_DCDC_V 0x1 +#define RTC_CNTL_DCM2ENB_DCDC_S 23 +/* RTC_CNTL_RAMP_DCDC : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_RAMP_DCDC (BIT(22)) +#define RTC_CNTL_RAMP_DCDC_M (BIT(22)) +#define RTC_CNTL_RAMP_DCDC_V 0x1 +#define RTC_CNTL_RAMP_DCDC_S 22 +/* RTC_CNTL_RAMPLEVEL_DCDC : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_RAMPLEVEL_DCDC (BIT(21)) +#define RTC_CNTL_RAMPLEVEL_DCDC_M (BIT(21)) +#define RTC_CNTL_RAMPLEVEL_DCDC_V 0x1 +#define RTC_CNTL_RAMPLEVEL_DCDC_S 21 +/* RTC_CNTL_PMU_MODE : R/W ;bitpos:[20:19] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_PMU_MODE 0x00000003 +#define RTC_CNTL_PMU_MODE_M ((RTC_CNTL_PMU_MODE_V)<<(RTC_CNTL_PMU_MODE_S)) +#define RTC_CNTL_PMU_MODE_V 0x3 +#define RTC_CNTL_PMU_MODE_S 19 +/* RTC_CNTL_POWER_GOOD_DCDC : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_POWER_GOOD_DCDC (BIT(5)) +#define RTC_CNTL_POWER_GOOD_DCDC_M (BIT(5)) +#define RTC_CNTL_POWER_GOOD_DCDC_V 0x1 +#define RTC_CNTL_POWER_GOOD_DCDC_S 5 +/* RTC_CNTL_VSET_DCDC_VALUE : RO ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_VALUE 0x0000001F +#define RTC_CNTL_VSET_DCDC_VALUE_M ((RTC_CNTL_VSET_DCDC_VALUE_V)<<(RTC_CNTL_VSET_DCDC_VALUE_S)) +#define RTC_CNTL_VSET_DCDC_VALUE_V 0x1F +#define RTC_CNTL_VSET_DCDC_VALUE_S 0 + +#define RTC_CNTL_DCDC_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x15C) +/* RTC_CNTL_DCDC_MODE_IDLE : R/W ;bitpos:[31:29] ;default: 3'b100 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DCDC_MODE_IDLE 0x00000007 +#define RTC_CNTL_DCDC_MODE_IDLE_M ((RTC_CNTL_DCDC_MODE_IDLE_V)<<(RTC_CNTL_DCDC_MODE_IDLE_S)) +#define RTC_CNTL_DCDC_MODE_IDLE_V 0x7 +#define RTC_CNTL_DCDC_MODE_IDLE_S 29 +/* RTC_CNTL_DCDC_MODE_MONITOR : R/W ;bitpos:[28:26] ;default: 3'b100 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DCDC_MODE_MONITOR 0x00000007 +#define RTC_CNTL_DCDC_MODE_MONITOR_M ((RTC_CNTL_DCDC_MODE_MONITOR_V)<<(RTC_CNTL_DCDC_MODE_MONITOR_S)) +#define RTC_CNTL_DCDC_MODE_MONITOR_V 0x7 +#define RTC_CNTL_DCDC_MODE_MONITOR_S 26 +/* RTC_CNTL_DCDC_MODE_SLP : R/W ;bitpos:[25:23] ;default: 3'b100 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DCDC_MODE_SLP 0x00000007 +#define RTC_CNTL_DCDC_MODE_SLP_M ((RTC_CNTL_DCDC_MODE_SLP_V)<<(RTC_CNTL_DCDC_MODE_SLP_S)) +#define RTC_CNTL_DCDC_MODE_SLP_V 0x7 +#define RTC_CNTL_DCDC_MODE_SLP_S 23 + +#define RTC_CNTL_DCDC_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x160) +/* RTC_CNTL_VSET_DCDC_SW_SEL : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_SW_SEL (BIT(28)) +#define RTC_CNTL_VSET_DCDC_SW_SEL_M (BIT(28)) +#define RTC_CNTL_VSET_DCDC_SW_SEL_V 0x1 +#define RTC_CNTL_VSET_DCDC_SW_SEL_S 28 +/* RTC_CNTL_VSET_DCDC_SEL_HW_SW : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_SEL_HW_SW (BIT(27)) +#define RTC_CNTL_VSET_DCDC_SEL_HW_SW_M (BIT(27)) +#define RTC_CNTL_VSET_DCDC_SEL_HW_SW_V 0x1 +#define RTC_CNTL_VSET_DCDC_SEL_HW_SW_S 27 +/* RTC_CNTL_VSET_DCDC_GAP : R/W ;bitpos:[26:22] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_GAP 0x0000001F +#define RTC_CNTL_VSET_DCDC_GAP_M ((RTC_CNTL_VSET_DCDC_GAP_V)<<(RTC_CNTL_VSET_DCDC_GAP_S)) +#define RTC_CNTL_VSET_DCDC_GAP_V 0x1F +#define RTC_CNTL_VSET_DCDC_GAP_S 22 +/* RTC_CNTL_VSET_DCDC_STEP : R/W ;bitpos:[21:17] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_STEP 0x0000001F +#define RTC_CNTL_VSET_DCDC_STEP_M ((RTC_CNTL_VSET_DCDC_STEP_V)<<(RTC_CNTL_VSET_DCDC_STEP_S)) +#define RTC_CNTL_VSET_DCDC_STEP_V 0x1F +#define RTC_CNTL_VSET_DCDC_STEP_S 17 +/* RTC_CNTL_VSET_DCDC_FIX : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_FIX (BIT(16)) +#define RTC_CNTL_VSET_DCDC_FIX_M (BIT(16)) +#define RTC_CNTL_VSET_DCDC_FIX_V 0x1 +#define RTC_CNTL_VSET_DCDC_FIX_S 16 +/* RTC_CNTL_VSET_DCDC_INIT : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_INIT (BIT(15)) +#define RTC_CNTL_VSET_DCDC_INIT_M (BIT(15)) +#define RTC_CNTL_VSET_DCDC_INIT_V 0x1 +#define RTC_CNTL_VSET_DCDC_INIT_S 15 +/* RTC_CNTL_VSET_DCDC_INIT_VALUE : R/W ;bitpos:[14:10] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_INIT_VALUE 0x0000001F +#define RTC_CNTL_VSET_DCDC_INIT_VALUE_M ((RTC_CNTL_VSET_DCDC_INIT_VALUE_V)<<(RTC_CNTL_VSET_DCDC_INIT_VALUE_S)) +#define RTC_CNTL_VSET_DCDC_INIT_VALUE_V 0x1F +#define RTC_CNTL_VSET_DCDC_INIT_VALUE_S 10 +/* RTC_CNTL_VSET_DCDC_TARGET_VALUE0 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0 0x0000001F +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0_M ((RTC_CNTL_VSET_DCDC_TARGET_VALUE0_V)<<(RTC_CNTL_VSET_DCDC_TARGET_VALUE0_S)) +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0_V 0x1F +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0_S 5 +/* RTC_CNTL_VSET_DCDC_TARGET_VALUE1 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1 0x0000001F +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1_M ((RTC_CNTL_VSET_DCDC_TARGET_VALUE1_V)<<(RTC_CNTL_VSET_DCDC_TARGET_VALUE1_S)) +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1_V 0x1F +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1_S 0 + +#define RTC_CNTL_RC32K_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x164) +/* RTC_CNTL_RC32K_XPD : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_RC32K_XPD (BIT(31)) +#define RTC_CNTL_RC32K_XPD_M (BIT(31)) +#define RTC_CNTL_RC32K_XPD_V 0x1 +#define RTC_CNTL_RC32K_XPD_S 31 +/* RTC_CNTL_RC32K_DFREQ : R/W ;bitpos:[30:21] ;default: 10'h1ff ; */ +/*description: Need add description.*/ +#define RTC_CNTL_RC32K_DFREQ 0x000003FF +#define RTC_CNTL_RC32K_DFREQ_M ((RTC_CNTL_RC32K_DFREQ_V)<<(RTC_CNTL_RC32K_DFREQ_S)) +#define RTC_CNTL_RC32K_DFREQ_V 0x3FF +#define RTC_CNTL_RC32K_DFREQ_S 21 + +#define RTC_CNTL_PLL8M_REG (DR_REG_RTCCNTL_BASE + 0x168) +/* RTC_CNTL_XPD_PLL8M : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_XPD_PLL8M (BIT(31)) +#define RTC_CNTL_XPD_PLL8M_M (BIT(31)) +#define RTC_CNTL_XPD_PLL8M_V 0x1 +#define RTC_CNTL_XPD_PLL8M_S 31 +/* RTC_CNTL_CKREF_PLL8M_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_CKREF_PLL8M_SEL (BIT(30)) +#define RTC_CNTL_CKREF_PLL8M_SEL_M (BIT(30)) +#define RTC_CNTL_CKREF_PLL8M_SEL_V 0x1 +#define RTC_CNTL_CKREF_PLL8M_SEL_S 30 + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x1FC) +/* RTC_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2109240 ; */ +/*description: Need add description.*/ +#define RTC_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_DATE_M ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S)) +#define RTC_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_DATE_S 0 + + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_RTC_CNTL_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/rev2/rtc_cntl_struct.h b/components/soc/esp32h2/include/soc/rev2/rtc_cntl_struct.h new file mode 100644 index 0000000000..ffd97153fa --- /dev/null +++ b/components/soc/esp32h2/include/soc/rev2/rtc_cntl_struct.h @@ -0,0 +1,1021 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _SOC_RTC_CNTL_STRUCT_H_ +#define _SOC_RTC_CNTL_STRUCT_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +typedef volatile struct { + union { + struct { + uint32_t sw_stall_appcpu_c0 : 2; /*{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t sw_stall_procpu_c0 : 2; /*{reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ + uint32_t sw_appcpu_rst : 1; /*APP CPU SW reset*/ + uint32_t sw_procpu_rst : 1; /*PRO CPU SW reset*/ + uint32_t bb_i2c_force_pd : 1; /*BB_I2C force power down*/ + uint32_t bb_i2c_force_pu : 1; /*BB_I2C force power up*/ + uint32_t bbpll_i2c_force_pd : 1; /*BB_PLL _I2C force power down*/ + uint32_t bbpll_i2c_force_pu : 1; /*BB_PLL_I2C force power up*/ + uint32_t bbpll_force_pd : 1; /*BB_PLL force power down*/ + uint32_t bbpll_force_pu : 1; /*BB_PLL force power up*/ + uint32_t xtl_force_pd : 1; /*crystall force power down*/ + uint32_t xtl_force_pu : 1; /*crystall force power up*/ + uint32_t xtl_en_wait : 4; /*wait bias_sleep and current source wakeup*/ + uint32_t xpd_rfpll : 1; /*Need add description*/ + uint32_t xpd_rfpll_force : 1; /*Need add description*/ + uint32_t ctr_sel : 3; /*Need add description*/ + uint32_t xtl_force_iso : 1; /*Need add description*/ + uint32_t pll_force_iso : 1; /*Need add description*/ + uint32_t analog_force_iso : 1; /*Need add description*/ + uint32_t xtl_force_noiso : 1; /*Need add description*/ + uint32_t pll_force_noiso : 1; /*Need add description*/ + uint32_t analog_force_noiso : 1; /*Need add description*/ + uint32_t dg_wrap_force_rst : 1; /*digital wrap force reset in deep sleep*/ + uint32_t dg_wrap_force_norst : 1; /*digital core force no reset in deep sleep*/ + uint32_t sw_sys_rst : 1; /*SW system reset*/ + }; + uint32_t val; + } options0; + uint32_t slp_timer0; + union { + struct { + uint32_t slp_val_hi : 16; /*RTC sleep timer high 16 bits*/ + uint32_t main_timer_alarm_en : 1; /*timer alarm enable bit*/ + uint32_t reserved17 : 15; /*Reserved*/ + }; + uint32_t val; + } slp_timer1; + union { + struct { + uint32_t reserved0 : 27; /*Reserved*/ + uint32_t timer_sys_stall : 1; /*Enable to record system stall time*/ + uint32_t timer_xtl_off : 1; /*Enable to record 40M XTAL OFF time*/ + uint32_t timer_sys_rst : 1; /*enable to record system reset time*/ + uint32_t reserved30 : 1; /*Reserved*/ + uint32_t update : 1; /*Set 1: to update register with RTC timer*/ + }; + uint32_t val; + } time_update; + uint32_t time_low0; + union { + struct { + uint32_t rtc_timer_value0_high : 16; /*RTC timer high 16 bits*/ + uint32_t reserved16 : 16; /*Reserved*/ + }; + uint32_t val; + } time_high0; + union { + struct { + uint32_t rtc_sw_cpu_int : 1; /*rtc software interrupt to main cpu*/ + uint32_t rtc_slp_reject_cause_clr : 1; /*clear rtc sleep reject cause*/ + uint32_t reserved2 : 20; /*Reserved*/ + uint32_t apb2rtc_bridge_sel : 1; /*1: APB to RTC using bridge, 0: APB to RTC using sync*/ + uint32_t reserved23 : 5; /*Reserved*/ + uint32_t sdio_active_ind : 1; /*SDIO active indication*/ + uint32_t slp_wakeup : 1; /*leep wakeup bit*/ + uint32_t slp_reject : 1; /*leep reject bit*/ + uint32_t sleep_en : 1; /*sleep enable bit*/ + }; + uint32_t val; + } state0; + union { + struct { + uint32_t cpu_stall_en : 1; /*CPU stall enable bit*/ + uint32_t cpu_stall_wait : 5; /*CPU stall wait cycles in fast_clk_rtc*/ + uint32_t ck8m_wait : 8; /*CK8M wait cycles in slow_clk_rtc*/ + uint32_t xtl_buf_wait : 10; /*XTAL wait cycles in slow_clk_rtc*/ + uint32_t pll_buf_wait : 8; /*PLL wait cycles in slow_clk_rtc*/ + }; + uint32_t val; + } timer1; + union { + struct { + uint32_t reserved0 : 24; /*Reserved*/ + uint32_t min_time_ck8m_off : 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ + }; + uint32_t val; + } timer2; + union { + struct { + uint32_t wifi_wait_timer : 9; /*Need add description*/ + uint32_t wifi_powerup_timer : 7; /*Need add description*/ + uint32_t bt_wait_timer : 9; /*Need add description*/ + uint32_t bt_powerup_timer : 7; /*Need add description*/ + }; + uint32_t val; + } timer3; + union { + struct { + uint32_t cpu_top_wait_timer : 9; /*Need add description*/ + uint32_t cpu_top_powerup_timer : 7; /*Need add description*/ + uint32_t dg_wrap_wait_timer : 9; /*Need add description*/ + uint32_t dg_wrap_powerup_timer : 7; /*Need add description*/ + }; + uint32_t val; + } timer4; + union { + struct { + uint32_t reserved0 : 8; /*Reserved*/ + uint32_t min_slp_val : 8; /*minimal sleep cycles in slow_clk_rtc*/ + uint32_t reserved16 : 16; /*Reserved*/ + }; + uint32_t val; + } timer5; + union { + struct { + uint32_t reserved0 : 16; /*Reserved*/ + uint32_t dg_peri_wait_timer : 9; /*Need add description*/ + uint32_t dg_peri_powerup_timer : 7; /*Need add description*/ + }; + uint32_t val; + } timer6; + union { + struct { + uint32_t reserved0 : 16; /*Reserved*/ + uint32_t xpd_trx_force_pd : 1; /*Need add description*/ + uint32_t xpd_trx_force_pu : 1; /*Need add description*/ + uint32_t i2c_reset_por_force_pd : 1; /*Need add description*/ + uint32_t i2c_reset_por_force_pu : 1; /*Need add description*/ + uint32_t glitch_rst_en : 1; /*Need add description*/ + uint32_t reserved21 : 1; /*ReservedPLLA force power down*/ + uint32_t peri_i2c_pu : 1; /*PLLA force power up*/ + uint32_t plla_force_pd : 1; /*PLLA force power down*/ + uint32_t plla_force_pu : 1; /*PLLA force power up*/ + uint32_t bbpll_cal_slp_start : 1; /*start BBPLL calibration during sleep*/ + uint32_t pvtmon_pu : 1; /*1: PVTMON power up , otherwise power down*/ + uint32_t txrf_i2c_pu : 1; /*1: TXRF_I2C power up , otherwise power down*/ + uint32_t rfrx_pbus_pu : 1; /*1: RFRX_PBUS power up , otherwise power down*/ + uint32_t reserved29 : 1; /*Reserved*/ + uint32_t ckgen_i2c_pu : 1; /*1: CKGEN_I2C power up , otherwise power down*/ + uint32_t pll_i2c_pu : 1; /*Need add description*/ + }; + uint32_t val; + } ana_conf; + union { + struct { + uint32_t reset_cause_procpu : 6; /*reset cause of PRO CPU*/ + uint32_t reset_cause_appcpu : 6; /*reset cause of APP CPU*/ + uint32_t stat_vector_sel_appcpu : 1; /*APP CPU state vector sel*/ + uint32_t stat_vector_sel_procpu : 1; /*PRO CPU state vector sel*/ + uint32_t all_reset_flag_procpu : 1; /*PRO CPU reset_flag*/ + uint32_t all_reset_flag_appcpu : 1; /*APP CPU reset flag*/ + uint32_t all_reset_flag_clr_procpu : 1; /*clear PRO CPU reset_flag*/ + uint32_t all_reset_flag_clr_appcpu : 1; /*clear APP CPU reset flag*/ + uint32_t ocd_halt_on_reset_appcpu : 1; /*APPCPU OcdHaltOnReset*/ + uint32_t ocd_halt_on_reset_procpu : 1; /*PROCPU OcdHaltOnReset*/ + uint32_t jtag_reset_flag_procpu : 1; /*Need add description*/ + uint32_t jtag_reset_flag_appcpu : 1; /*Need add description*/ + uint32_t jtag_reset_flag_clr_procpu : 1; /*Need add description*/ + uint32_t jtag_reset_flag_clr_appcpu : 1; /*Need add description*/ + uint32_t rtc_dreset_mask_appcpu : 1; /*Need add description*/ + uint32_t rtc_dreset_mask_procpu : 1; /*Need add description*/ + uint32_t reserved26 : 6; /*Reserved*/ + }; + uint32_t val; + } reset_state; + union { + struct { + uint32_t reserved0 : 13; /*Reserved*/ + uint32_t rtc_wakeup_ena : 19; /*wakeup enable bitmap*/ + }; + uint32_t val; + } wakeup_state; + union { + struct { + uint32_t slp_wakeup : 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject : 1; /*enable sleep reject interrupt*/ + uint32_t reserved2 : 1; /*Reservedenable SDIO idle interrupt*/ + uint32_t rtc_wdt : 1; /*enable RTC WDT interrupt*/ + uint32_t reserved4 : 5; /*Reserved*/ + uint32_t rtc_brown_out : 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer : 1; /*enable RTC main timer interrupt*/ + uint32_t reserved11 : 4; /*Reservedenable saradc2 interrupt*/ + uint32_t rtc_swd : 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead : 1; /*enable xtal32k_dead interrupt*/ + uint32_t reserved17 : 2; /*Reservedenable touch timeout interrupt*/ + uint32_t rtc_glitch_det : 1; /*enbale gitch det interrupt*/ + uint32_t rtc_bbpll_cal : 1; /*Need add description*/ + uint32_t rtc_ble_compare_wake : 1; /*Need add description*/ + uint32_t vset_dcdc_done : 1; /*Need add description*/ + uint32_t reserved23 : 9; /*Reserved*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t slp_wakeup : 1; /*sleep wakeup interrupt raw*/ + uint32_t slp_reject : 1; /*sleep reject interrupt raw*/ + uint32_t reserved2 : 1; /*ReservedSDIO idle interrupt raw*/ + uint32_t rtc_wdt : 1; /*RTC WDT interrupt raw*/ + uint32_t reserved4 : 5; /*Reservedtouch inactive interrupt raw*/ + uint32_t rtc_brown_out : 1; /*brown out interrupt raw*/ + uint32_t rtc_main_timer : 1; /*RTC main timer interrupt raw*/ + uint32_t reserved11 : 4; /*Reservedsaradc2 interrupt raw*/ + uint32_t rtc_swd : 1; /*super watch dog interrupt raw*/ + uint32_t rtc_xtal32k_dead : 1; /*xtal32k dead detection interrupt raw*/ + uint32_t reserved17 : 2; /*Reservedtouch timeout interrupt raw*/ + uint32_t rtc_glitch_det : 1; /*glitch_det_interrupt_raw*/ + uint32_t rtc_bbpll_cal : 1; /*Need add description*/ + uint32_t rtc_ble_compare_wake : 1; /*Need add description*/ + uint32_t vset_dcdc_done : 1; /*Need add description*/ + uint32_t reserved23 : 9; /*Reserved*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t slp_wakeup : 1; /*sleep wakeup interrupt state*/ + uint32_t slp_reject : 1; /*sleep reject interrupt state*/ + uint32_t reserved2 : 1; /*Reserved*/ + uint32_t rtc_wdt : 1; /*RTC WDT interrupt state*/ + uint32_t reserved4 : 5; /*Reserved*/ + uint32_t rtc_brown_out : 1; /*brown out interrupt state*/ + uint32_t rtc_main_timer : 1; /*RTC main timer interrupt state*/ + uint32_t reserved11 : 4; /*Reserved*/ + uint32_t rtc_swd : 1; /*super watch dog interrupt state*/ + uint32_t rtc_xtal32k_dead : 1; /*xtal32k dead detection interrupt state*/ + uint32_t reserved17 : 2; /*Reserved*/ + uint32_t rtc_glitch_det : 1; /*glitch_det_interrupt state*/ + uint32_t rtc_bbpll_cal : 1; /*Need add description*/ + uint32_t rtc_ble_compare_wake : 1; /*Need add description*/ + uint32_t vset_dcdc_done : 1; /*Need add description*/ + uint32_t reserved23 : 9; /*Reserved*/ + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t slp_wakeup : 1; /*Clear sleep wakeup interrupt state*/ + uint32_t slp_reject : 1; /*Clear sleep reject interrupt state*/ + uint32_t reserved2 : 1; /*Reserved*/ + uint32_t rtc_wdt : 1; /*Clear RTC WDT interrupt state*/ + uint32_t reserved4 : 5; /*Reserved*/ + uint32_t rtc_brown_out : 1; /*Clear brown out interrupt state*/ + uint32_t rtc_main_timer : 1; /*Clear RTC main timer interrupt state*/ + uint32_t reserved11 : 4; /*Reserved*/ + uint32_t rtc_swd : 1; /*Clear super watch dog interrupt state*/ + uint32_t rtc_xtal32k_dead : 1; /*Clear RTC WDT interrupt state*/ + uint32_t reserved17 : 2; /*Reserved*/ + uint32_t rtc_glitch_det : 1; /*Clear glitch det interrupt state*/ + uint32_t rtc_bbpll_cal : 1; /*Need add description*/ + uint32_t rtc_ble_compare_wake : 1; /*Need add description*/ + uint32_t vset_dcdc_done : 1; /*Need add description*/ + uint32_t reserved23 : 9; /*Reserved*/ + }; + uint32_t val; + } int_clr; + uint32_t store[4]; + union { + struct { + uint32_t xtal32k_wdt_en : 1; /*xtal 32k watch dog enable*/ + uint32_t xtal32k_wdt_clk_fo : 1; /*xtal 32k watch dog clock force on*/ + uint32_t xtal32k_wdt_reset : 1; /*xtal 32k watch dog sw reset*/ + uint32_t xtal32k_ext_clk_fo : 1; /*xtal 32k external xtal clock force on*/ + uint32_t xtal32k_auto_backup : 1; /*xtal 32k switch to back up clock when xtal is dead*/ + uint32_t xtal32k_auto_restart : 1; /*xtal 32k restart xtal when xtal is dead*/ + uint32_t xtal32k_auto_return : 1; /*xtal 32k switch back xtal when xtal is restarted*/ + uint32_t xtal32k_xpd_force : 1; /*Xtal 32k xpd control by sw or fsm*/ + uint32_t enckinit_xtal_32k : 1; /*apply an internal clock to help xtal 32k to start*/ + uint32_t dbuf_xtal_32k : 1; /*0: single-end buffer 1: differential buffer*/ + uint32_t dgm_xtal_32k : 3; /*xtal_32k gm control*/ + uint32_t dres_xtal_32k : 3; /*DRES_XTAL_32K*/ + uint32_t xpd_xtal_32k : 1; /*XPD_XTAL_32K*/ + uint32_t dac_xtal_32k : 3; /*DAC_XTAL_32K*/ + uint32_t rtc_wdt_state : 3; /*state of 32k_wdt*/ + uint32_t rtc_xtal32k_gpio_sel : 1; /*XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C*/ + uint32_t reserved24 : 6; /*Reserved*/ + uint32_t ctr_lv : 1; /*0: power down XTAL at high level, 1: power down XTAL at low level*/ + uint32_t ctr_en : 1; /*Need add description*/ + }; + uint32_t val; + } ext_xtl_conf; + union { + struct { + uint32_t reserved0 : 31; /*Reserved*/ + uint32_t gpio_wakeup_filter : 1; /*enable filter for gpio wakeup event*/ + }; + uint32_t val; + } ext_wakeup_conf; + union { + struct { + uint32_t reserved0 : 11; /*Reserved*/ + uint32_t rtc_sleep_reject_ena : 19; /*sleep reject enable*/ + uint32_t light_slp_reject_en : 1; /*enable reject for light sleep*/ + uint32_t deep_slp_reject_en : 1; /*enable reject for deep sleep*/ + }; + uint32_t val; + } slp_reject_conf; + union { + struct { + uint32_t reserved0 : 29; /*Reserved*/ + uint32_t cpusel_conf : 1; /*CPU sel option*/ + uint32_t cpuperiod_sel : 2; /*Need add description*/ + }; + uint32_t val; + } cpu_period_conf; + union { + struct { + uint32_t rtc_ble_tmr_rst : 1; /*Need add description*/ + uint32_t efuse_clk_force_gating : 1; /*Need add description*/ + uint32_t efuse_clk_force_nogating : 1; /*Need add description*/ + uint32_t ck8m_div_sel_vld : 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set vld to actually switch the clk*/ + uint32_t dig_xtal32k_en : 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ + uint32_t dig_rc32k_en : 1; /*enable RC32K for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_en : 1; /*enable CK8M for digital core (no relationship with RTC core)*/ + uint32_t rtc_ble_timer_sel : 1; /*Need add description*/ + uint32_t reserved8 : 2; /*Reserved*/ + uint32_t ck8m_div_sel : 3; /*divider = reg_ck8m_div_sel + 1*/ + uint32_t xtal_force_nogating : 1; /*XTAL force no gating during sleep*/ + uint32_t ck8m_force_nogating : 1; /*CK8M force no gating during sleep*/ + uint32_t ck8m_dfreq : 10; /*CK8M_DFREQ*/ + uint32_t ck8m_force_pd : 1; /*CK8M force power down*/ + uint32_t ck8m_force_pu : 1; /*CK8M force power up*/ + uint32_t xtal_global_force_gating : 1; /*Need add description*/ + uint32_t xtal_global_force_nogating : 1; /*Need add description*/ + uint32_t fast_clk_rtc_sel : 1; /*fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M */ + uint32_t ana_clk_rtc_sel : 2; /*Need add description*/ + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t reserved0 : 19; /*Reserved*/ + uint32_t rtc_ana_clk_pd_slp : 1; /*Need add description*/ + uint32_t rtc_ana_clk_pd_monitor : 1; /*Need add description*/ + uint32_t rtc_ana_clk_pd_idle : 1; /*Need add description*/ + uint32_t rtc_ana_clk_div_vld : 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to actually switch the clk */ + uint32_t rtc_ana_clk_div : 8; /*Need add description*/ + uint32_t slow_clk_next_edge : 1; /*Need add description*/ + }; + uint32_t val; + } slow_clk_conf; + union { + struct { + uint32_t sdio_timer_target : 8; /*timer count to apply reg_sdio_dcap after sdio power on*/ + uint32_t reserved8 : 1; /*Reserved*/ + uint32_t sdio_dthdrv : 2; /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3 after several us.*/ + uint32_t sdio_dcap : 2; /*ability to prevent LDO from overshoot*/ + uint32_t sdio_initi : 2; /*add resistor from ldo output to ground. 0: no res, 1: 6k, 2: 4k, 3: 2k */ + uint32_t sdio_en_initi : 1; /*0 to set init[1:0]=0*/ + uint32_t sdio_dcurlim : 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ + uint32_t sdio_modecurlim : 1; /*select current limit mode*/ + uint32_t sdio_encurlim : 1; /*enable current limit*/ + uint32_t sdio_pd_en : 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ + uint32_t sdio_force : 1; /*1: use SW option to control SDIO_REG ,0: use state machine*/ + uint32_t sdio_tieh : 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ + uint32_t reg1p8_ready : 1; /*read only register for REG1P8_READY*/ + uint32_t drefl_sdio : 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefm_sdio : 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefh_sdio : 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t xpd_sdio : 1; /*Need add description*/ + }; + uint32_t val; + } sdio_conf; + union { + struct { + uint32_t reserved0 : 10; /*Reserved*/ + uint32_t bias_buf_idle : 1; /*Need add description*/ + uint32_t bias_buf_wake : 1; /*Need add description*/ + uint32_t bias_buf_deep_slp : 1; /*Need add description*/ + uint32_t bias_buf_monitor : 1; /*Need add description*/ + uint32_t pd_cur_deep_slp : 1; /*xpd cur when rtc in sleep_state*/ + uint32_t pd_cur_monitor : 1; /*xpd cur when rtc in monitor state*/ + uint32_t bias_sleep_deep_slp : 1; /*bias_sleep when rtc in sleep_state*/ + uint32_t bias_sleep_monitor : 1; /*bias_sleep when rtc in monitor state*/ + uint32_t dbg_atten_deep_slp : 4; /*DBG_ATTEN when rtc in sleep state*/ + uint32_t dbg_atten_monitor : 4; /*DBG_ATTEN when rtc in monitor state*/ + uint32_t xpd_dcdc_slp : 1; /*Need add description*/ + uint32_t xpd_dcdc_monitor : 1; /*Need add description*/ + uint32_t xpd_dcdc_idle : 1; /*Need add description*/ + uint32_t reserved29 : 3; /*Reserved*/ + }; + uint32_t val; + } bias_conf; + union { + struct { + uint32_t dbias_switch_slp : 1; /*Need add description*/ + uint32_t dbias_switch_monitor : 1; /*Need add description*/ + uint32_t dbias_switch_idle : 1; /*Need add description*/ + uint32_t dig_cal_en : 1; /*Need add description*/ + uint32_t sck_dcap : 8; /*Need add description*/ + uint32_t reserved12 : 3; /*Reserved*/ + uint32_t rtc_vdd_drv_b_active : 6; /*SCK_DCAP*/ + uint32_t rtc_vdd_drv_b_slp : 6; /*Need add description*/ + uint32_t rtc_vdd_drv_b_slp_en : 1; /*Need add description*/ + uint32_t rtc_dboost_force_pd : 1; /*RTC_DBOOST force power down*/ + uint32_t rtc_dboost_force_pu : 1; /*RTC_DBOOST force power up*/ + uint32_t rtculator_force_pd : 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ + uint32_t rtculator_force_pu : 1; /*Need add description*/ + }; + uint32_t val; + } rtculator; + union { + struct { + uint32_t reserved0 : 15; /*Reserved*/ + uint32_t pvt_rtc_dbias : 5; /*get pvt dbias value*/ + uint32_t rtculator0_dbias_slp : 5; /*the rtc regulator0 dbias when chip in sleep state*/ + uint32_t rtculator0_dbias_active : 5; /*the rtc regulator0 dbias when chip in active state*/ + uint32_t reserved30 : 1; /*Reserved*/ + uint32_t rtculator0_dbias_sel : 1; /*1: select sw dbias_active 0: select pvt value*/ + }; + uint32_t val; + } rtculator0_dbias; + union { + struct { + uint32_t reserved0 : 20; /*Reserved*/ + uint32_t rtculator1_dbias_slp : 4; /*the rtc regulator1 dbias when chip in sleep state*/ + uint32_t reserved24 : 1; /*Reserved*/ + uint32_t rtculator1_dbias_active : 4; /*the rtc regulator1 dbias when chip in active state*/ + uint32_t reserved29 : 3; /*Reserved*/ + }; + uint32_t val; + } rtculator1_dbias; + union { + struct { + uint32_t reserved0 : 1; /*Reserved*/ + uint32_t memulator_slp_force_pd : 1; /*Need add description*/ + uint32_t memulator_slp_force_pu : 1; /*Need add description*/ + uint32_t dg_vdd_drv_b_slp : 24; /*Need add description*/ + uint32_t dg_vdd_drv_b_slp_en : 1; /*Need add description*/ + uint32_t dgulator_slp_force_pd : 1; /*Need add description*/ + uint32_t dgulator_slp_force_pu : 1; /*Need add description*/ + uint32_t dgulator_force_pd : 1; /*Need add description*/ + uint32_t dgulator_force_pu : 1; /*Need add description*/ + }; + uint32_t val; + } digulator; + union { + struct { + uint32_t dg_vdd_drv_b_active : 24; /*Need add description*/ + uint32_t reserved24 : 8; /*Reserved*/ + }; + uint32_t val; + } digulator_drvb; + union { + struct { + uint32_t reserved0 : 15; /*Reserved*/ + uint32_t pvt_dig_dbias : 5; /*get pvt dbias value*/ + uint32_t digulator0_dbias_slp : 5; /*the dig regulator0 dbias when chip in sleep state*/ + uint32_t digulator0_dbias_active : 5; /*the dig regulator0 dbias when chip in active state*/ + uint32_t digulator0_dbias_init : 1; /*initial pvt dbias value*/ + uint32_t digulator0_dbias_sel : 1; /*1: select sw dbias_active 0: select pvt value*/ + }; + uint32_t val; + } digulator0_dbias; + union { + struct { + uint32_t reserved0 : 12; /*Reserved*/ + uint32_t memulator1_dbias_slp : 4; /*Need add description*/ + uint32_t memulator1_dbias_active : 4; /*Need add description*/ + uint32_t digulator1_dbias_slp : 4; /*the dig regulator1 dbias when chip in sleep state*/ + uint32_t reserved24 : 1; /*Reserved*/ + uint32_t digulator1_dbias_active : 4; /*the dig regulator1 dbias when chip in active state*/ + uint32_t reserved29 : 3; /*Reserved*/ + }; + uint32_t val; + } digulator1_dbias; + union { + struct { + uint32_t reserved0 : 21; /*Reserved*/ + uint32_t rtc_pad_force_hold : 1; /*rtc pad force hold*/ + uint32_t reserved22 : 10; /*Reserved*/ + }; + uint32_t val; + } pwc; + union { + struct { + uint32_t vdd_spi_pwr_drv : 2; /*Need add description*/ + uint32_t vdd_spi_pwr_force : 1; /*Need add description*/ + uint32_t lslp_mem_force_pd : 1; /*memories in digital core force PD in sleep*/ + uint32_t lslp_mem_force_pu : 1; /*memories in digital core force no PD in sleep*/ + uint32_t reserved5 : 2; /*Reserved*/ + uint32_t dg_mem_force_pd : 1; /*Need add description*/ + uint32_t dg_mem_force_pu : 1; /*Need add description*/ + uint32_t dg_wrap_force_pd : 1; /*Need add description*/ + uint32_t dg_wrap_force_pu : 1; /*Need add description*/ + uint32_t bt_force_pd : 1; /*Need add description*/ + uint32_t bt_force_pu : 1; /*Need add description*/ + uint32_t dg_peri_force_pd : 1; /*Need add description*/ + uint32_t dg_peri_force_pu : 1; /*Need add description*/ + uint32_t fastmem_force_lpd : 1; /*Need add description*/ + uint32_t fastmem_force_lpu : 1; /*Need add description*/ + uint32_t wifi_force_pd : 1; /*wifi force power down*/ + uint32_t wifi_force_pu : 1; /*wifi force power up*/ + uint32_t reserved19 : 2; /*Reserveddigital core force power down*/ + uint32_t cpu_top_force_pd : 1; /*Need add description*/ + uint32_t cpu_top_force_pu : 1; /*Need add description*/ + uint32_t reserved23 : 3; /*Reserved*/ + uint32_t dg_wrap_ret_pd_en : 1; /*Need add description*/ + uint32_t bt_pd_en : 1; /*Need add description*/ + uint32_t dg_peri_pd_en : 1; /*Need add description*/ + uint32_t cpu_top_pd_en : 1; /*Need add description*/ + uint32_t wifi_pd_en : 1; /*enable power down wifi in sleep*/ + uint32_t dg_wrap_pd_en : 1; /*Need add description*/ + }; + uint32_t val; + } dig_pwc; + union { + struct { + uint32_t reserved0 : 2; /*Reserved*/ + uint32_t pd_dg_peri_switch_mask : 5; /*Need add description*/ + uint32_t pd_dg_wrap_switch_mask : 5; /*Need add description*/ + uint32_t pd_mem_switch_mask : 20; /*Need add description*/ + }; + uint32_t val; + } dig_power_slave0_pd; + union { + struct { + uint32_t reserved0 : 22; /*Reserved*/ + uint32_t pd_wifi_switch_mask : 5; /*Need add description*/ + uint32_t pd_cpu_switch_mask : 5; /*Need add description*/ + }; + uint32_t val; + } dig_power_slave1_pd; + union { + struct { + uint32_t reserved0 : 2; /*Reserved*/ + uint32_t xpd_dg_peri_switch_mask : 5; /*Need add description*/ + uint32_t xpd_dg_wrap_switch_mask : 5; /*Need add description*/ + uint32_t xpd_mem_switch_mask : 20; /*Need add description*/ + }; + uint32_t val; + } dig_power_slave0_fpu; + union { + struct { + uint32_t reserved0 : 22; /*Reserved*/ + uint32_t xpd_wifi_switch_mask : 5; /*Need add description*/ + uint32_t xpd_cpu_switch_mask : 5; /*Need add description*/ + }; + uint32_t val; + } dig_power_slave1_fpu; + union { + struct { + uint32_t reserved0 : 5; /*Reserved*/ + uint32_t dg_mem_force_noiso : 1; /*Need add description*/ + uint32_t dg_mem_force_iso : 1; /*Need add description*/ + uint32_t dig_iso_force_off : 1; /*Need add description*/ + uint32_t dig_iso_force_on : 1; /*Need add description*/ + uint32_t dg_pad_autohold : 1; /*read only register to indicate digital pad auto-hold status*/ + uint32_t clr_dg_pad_autohold : 1; /*wtite only register to clear digital pad auto-hold*/ + uint32_t dg_pad_autohold_en : 1; /*digital pad enable auto-hold*/ + uint32_t dg_pad_force_noiso : 1; /*digital pad force no ISO*/ + uint32_t dg_pad_force_iso : 1; /*digital pad force ISO*/ + uint32_t dg_pad_force_unhold : 1; /*digital pad force un-hold*/ + uint32_t dg_pad_force_hold : 1; /*digital pad force hold*/ + uint32_t reserved16 : 6; /*Reserved*/ + uint32_t bt_force_iso : 1; /*Need add description*/ + uint32_t bt_force_noiso : 1; /*Need add description*/ + uint32_t dg_peri_force_iso : 1; /*Need add description*/ + uint32_t dg_peri_force_noiso : 1; /*Need add description*/ + uint32_t cpu_top_force_iso : 1; /*cpu force ISO*/ + uint32_t cpu_top_force_noiso : 1; /*cpu force no ISO*/ + uint32_t wifi_force_iso : 1; /*wifi force ISO*/ + uint32_t wifi_force_noiso : 1; /*wifi force no ISO*/ + uint32_t dg_wrap_force_iso : 1; /*digital core force ISO*/ + uint32_t dg_wrap_force_noiso : 1; /*Need add description*/ + }; + uint32_t val; + } dig_iso; + union { + struct { + uint32_t chip_reset_width : 8; /*chip reset siginal pulse width*/ + uint32_t chip_reset_en : 1; /*wdt reset whole chip enable*/ + uint32_t pause_in_slp : 1; /*pause WDT in sleep*/ + uint32_t appcpu_reset_en : 1; /*enable WDT reset APP CPU*/ + uint32_t procpu_reset_en : 1; /*enable WDT reset PRO CPU*/ + uint32_t flashboot_mod_en : 1; /*enable WDT in flash boot*/ + uint32_t sys_reset_length : 3; /*system reset counter length*/ + uint32_t cpu_reset_length : 3; /*CPU reset counter length*/ + uint32_t stg3 : 3; /*1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC reset stage en*/ + uint32_t stg2 : 3; /*1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC reset stage en*/ + uint32_t stg1 : 3; /*1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC reset stage en*/ + uint32_t stg0 : 3; /*1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC reset stage en*/ + uint32_t en : 1; /*Need add description*/ + }; + uint32_t val; + } wdt_config0; + uint32_t wdt_config1; + uint32_t wdt_config2; + uint32_t wdt_config3; + uint32_t wdt_config4; + union { + struct { + uint32_t reserved0 : 31; /*Reserved*/ + uint32_t feed : 1; /*Need add description*/ + }; + uint32_t val; + } wdt_feed; + uint32_t wdt_wprotect; + union { + struct { + uint32_t reserved0 : 16; /*Reserved*/ + uint32_t reset_chip_target : 8; /*Need add description*/ + uint32_t reset_chip_key : 8; /*Need add description*/ + }; + uint32_t val; + } wdtreset_chip; + union { + struct { + uint32_t swd_reset_flag : 1; /*swd reset flag*/ + uint32_t swd_feed_int : 1; /*swd interrupt for feeding*/ + uint32_t reserved2 : 15; /*Reserved*/ + uint32_t swd_bypass_rst : 1; /*Need add description*/ + uint32_t swd_signal_width : 10; /*adjust signal width send to swd*/ + uint32_t swd_rst_flag_clr : 1; /*reset swd reset flag*/ + uint32_t swd_feed : 1; /*Sw feed swd*/ + uint32_t swd_disable : 1; /*disabel SWD*/ + uint32_t swd_auto_feed_en : 1; /*automatically feed swd when int comes*/ + }; + uint32_t val; + } swd_conf; + uint32_t swd_wprotect; + union { + struct { + uint32_t reserved0 : 20; /*Reserved*/ + uint32_t appcpu_c1 : 6; /*{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t procpu_c1 : 6; /*Need add description*/ + }; + uint32_t val; + } sw_cpu_stall; + uint32_t store4; + uint32_t store5; + uint32_t store6; + uint32_t store7; + union { + struct { + uint32_t xpd_rom0 : 1; /*rom0 power down*/ + uint32_t reserved1 : 1; /*Reserved*/ + uint32_t xpd_dig_dcdc : 1; /*External DCDC power down*/ + uint32_t rtc_peri_iso : 1; /*rtc peripheral iso*/ + uint32_t xpd_rtc_peri : 1; /*rtc peripheral power down */ + uint32_t wifi_iso : 1; /*wifi iso*/ + uint32_t xpd_wifi : 1; /*wifi wrap power down*/ + uint32_t dig_iso : 1; /*digital wrap iso*/ + uint32_t xpd_dig : 1; /*digital wrap power down*/ + uint32_t rtc_touch_state_start : 1; /*touch should start to work*/ + uint32_t rtc_touch_state_switch : 1; /*touch is about to working. Switch rtc main state*/ + uint32_t rtc_touch_state_slp : 1; /*touch is in sleep state*/ + uint32_t rtc_touch_state_done : 1; /*touch is done*/ + uint32_t rtc_cocpu_state_start : 1; /*ulp/cocpu should start to work*/ + uint32_t rtc_cocpu_state_switch : 1; /*ulp/cocpu is about to working. Switch rtc main state*/ + uint32_t rtc_cocpu_state_slp : 1; /*ulp/cocpu is in sleep state*/ + uint32_t rtc_cocpu_state_done : 1; /*ulp/cocpu is done*/ + uint32_t rtc_main_state_xtal_iso : 1; /*no use any more*/ + uint32_t rtc_main_state_pll_on : 1; /*rtc main state machine is in states that pll should be running*/ + uint32_t rtc_rdy_for_wakeup : 1; /*rtc is ready to receive wake up trigger from wake up source*/ + uint32_t rtc_main_state_wait_end : 1; /*rtc main state machine has been waited for some cycles*/ + uint32_t rtc_in_wakeup_state : 1; /*rtc main state machine is in the states of wakeup process*/ + uint32_t rtc_in_low_power_state : 1; /*rtc main state machine is in the states of low power*/ + uint32_t rtc_main_state_in_wait_8m : 1; /*rtc main state machine is in wait 8m state*/ + uint32_t rtc_main_state_in_wait_pll : 1; /*rtc main state machine is in wait pll state*/ + uint32_t rtc_main_state_in_wait_xtl : 1; /*rtc main state machine is in wait xtal state*/ + uint32_t rtc_main_state_in_slp : 1; /*rtc main state machine is in sleep state*/ + uint32_t rtc_main_state_in_idle : 1; /*rtc main state machine is in idle state*/ + uint32_t rtc_main_state : 4; /*rtc main state machine status*/ + }; + uint32_t val; + } low_power_st; + uint32_t diag0; + union { + struct { + uint32_t rtc_gpio_pin0_hold : 1; /*Need add description*/ + uint32_t rtc_gpio_pin1_hold : 1; /*Need add description*/ + uint32_t rtc_gpio_pin2_hold : 1; /*Need add description*/ + uint32_t rtc_gpio_pin3_hold : 1; /*Need add description*/ + uint32_t rtc_gpio_pin4_hold : 1; /*Need add description*/ + uint32_t rtc_gpio_pin5_hold : 1; /*Need add description*/ + uint32_t reserved6 : 26; /*Reserved*/ + }; + uint32_t val; + } pad_hold; + uint32_t dig_pad_hold; + union { + struct { + uint32_t dig_pad_hold1 : 9; /*Need add description*/ + uint32_t reserved9 : 23; /*Reserved*/ + }; + uint32_t val; + } dig_pad_hold1; + union { + struct { + uint32_t reserved0 : 4; /*Reserved*/ + uint32_t int_wait : 10; /*brown out interrupt wait cycles*/ + uint32_t close_flash_ena : 1; /*enable close flash when brown out happens*/ + uint32_t pd_rf_ena : 1; /*enable power down RF when brown out happens*/ + uint32_t rst_wait : 10; /*brown out reset wait cycles*/ + uint32_t rst_ena : 1; /*enable brown out reset*/ + uint32_t rst_sel : 1; /*1: 4-pos reset, 0: sys_reset*/ + uint32_t ana_rst_en : 1; /*Need add description*/ + uint32_t cnt_clr : 1; /*clear brown out counter*/ + uint32_t ena : 1; /*enable brown out*/ + uint32_t det : 1; /*Need add description*/ + }; + uint32_t val; + } brown_out; + uint32_t time_low1; + union { + struct { + uint32_t rtc_timer_value1_high : 16; /*RTC timer high 16 bits*/ + uint32_t reserved16 : 16; /*Reserved*/ + }; + uint32_t val; + } time_high1; + uint32_t xtal32k_clk_factor; + union { + struct { + uint32_t xtal32k_return_wait : 4; /*cycles to wait to return noral xtal 32k*/ + uint32_t xtal32k_restart_wait : 16; /*cycles to wait to repower on xtal 32k*/ + uint32_t xtal32k_wdt_timeout : 8; /*If no clock detected for this amount of time, 32k is regarded as dead*/ + uint32_t xtal32k_stable_thres : 4; /*if restarted xtal32k period is smaller than this, it is regarded as stable*/ + }; + uint32_t val; + } xtal32k_conf; + union { + struct { + uint32_t reserved0 : 18; /*Reserved*/ + uint32_t io_mux_reset_disable : 1; /*Need add description*/ + uint32_t reserved19 : 13; /*Reserved*/ + }; + uint32_t val; + } usb_conf; + union { + struct { + uint32_t reject_cause : 19; /*sleep reject cause*/ + uint32_t reserved19 : 13; /*Reserved*/ + }; + uint32_t val; + } slp_reject_cause; + union { + struct { + uint32_t force_download_boot : 1; /*Need add description*/ + uint32_t reserved1 : 31; /*Reserved*/ + }; + uint32_t val; + } option1; + union { + struct { + uint32_t wakeup_cause : 19; /*sleep wakeup cause*/ + uint32_t reserved19 : 13; /*Reserved*/ + }; + uint32_t val; + } slp_wakeup_cause; + union { + struct { + uint32_t reserved0 : 8; /*Reserved*/ + uint32_t ulp_cp_timer_slp_cycle : 24; /*sleep cycles for ULP-coprocessor timer*/ + }; + uint32_t val; + } ulp_cp_timer_1; + union { + struct { + uint32_t slp_wakeup_w1ts : 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject_w1ts : 1; /*enable sleep reject interrupt*/ + uint32_t reserved2 : 1; /*Reserved*/ + uint32_t rtc_wdt_w1ts : 1; /*enable RTC WDT interrupt*/ + uint32_t reserved4 : 5; /*Reserved*/ + uint32_t w1ts : 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer_w1ts : 1; /*enable RTC main timer interrupt*/ + uint32_t reserved11 : 4; /*Reserved*/ + uint32_t rtc_swd_w1ts : 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead_w1ts : 1; /*enable xtal32k_dead interrupt*/ + uint32_t reserved17 : 2; /*Reserved*/ + uint32_t rtc_glitch_det_w1ts : 1; /*enbale gitch det interrupt*/ + uint32_t rtc_bbpll_cal_w1ts : 1; /*Need add description*/ + uint32_t rtc_ble_compare_wake_w1ts : 1; /*Need add description*/ + uint32_t vset_dcdc_done_w1ts : 1; /*Need add description*/ + uint32_t reserved23 : 9; /*Reserved*/ + }; + uint32_t val; + } int_ena_w1ts; + union { + struct { + uint32_t slp_wakeup_w1tc : 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject_w1tc : 1; /*enable sleep reject interrupt*/ + uint32_t reserved2 : 1; /*Reserved*/ + uint32_t rtc_wdt_w1tc : 1; /*enable RTC WDT interrupt*/ + uint32_t reserved4 : 5; /*Reserved*/ + uint32_t w1tc : 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer_w1tc : 1; /*enable RTC main timer interrupt*/ + uint32_t reserved11 : 4; /*Reserved*/ + uint32_t rtc_swd_w1tc : 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead_w1tc : 1; /*enable xtal32k_dead interrupt*/ + uint32_t reserved17 : 2; /*Reserved*/ + uint32_t rtc_glitch_det_w1tc : 1; /*enbale gitch det interrupt*/ + uint32_t rtc_bbpll_cal_w1tc : 1; /*Need add description*/ + uint32_t rtc_ble_compare_wake_w1tc : 1; /*Need add description*/ + uint32_t vset_dcdc_done_w1tc : 1; /*Need add description*/ + uint32_t reserved23 : 9; /*Reserved*/ + }; + uint32_t val; + } int_ena_w1tc; + union { + struct { + uint32_t reserved0 : 17; /*Reserved*/ + uint32_t rtc_cntl_clk_en : 1; /*Need add description*/ + uint32_t retention_clk_sel : 1; /*Need add description*/ + uint32_t retention_done_wait : 3; /*Need add description*/ + uint32_t retention_clkoff_wait : 4; /*Need add description*/ + uint32_t retention_en : 1; /*Need add description*/ + uint32_t retention_wait : 5; /*wait cycles for rention operation*/ + }; + uint32_t val; + } retention_ctrl; + union { + struct { + uint32_t retention_link_addr : 27; /*Need add description*/ + uint32_t reserved27 : 5; /*Reserved*/ + }; + uint32_t val; + } retention_ctrl1; + union { + struct { + uint32_t rtc_fib_sel : 3; /*select use analog fib signal*/ + uint32_t reserved3 : 29; /*Reserved*/ + }; + uint32_t val; + } fib_sel; + union { + struct { + uint32_t rtc_gpio_wakeup_status : 6; /*Need add description*/ + uint32_t rtc_gpio_wakeup_status_clr : 1; /*Need add description*/ + uint32_t rtc_gpio_pin_clk_gate : 1; /*Need add description*/ + uint32_t rtc_gpio_pin5_int_type : 3; /*Need add description*/ + uint32_t rtc_gpio_pin4_int_type : 3; /*Need add description*/ + uint32_t rtc_gpio_pin3_int_type : 3; /*Need add description*/ + uint32_t rtc_gpio_pin2_int_type : 3; /*Need add description*/ + uint32_t rtc_gpio_pin1_int_type : 3; /*Need add description*/ + uint32_t rtc_gpio_pin0_int_type : 3; /*Need add description*/ + uint32_t rtc_gpio_pin5_wakeup_enable : 1; /*Need add description*/ + uint32_t rtc_gpio_pin4_wakeup_enable : 1; /*Need add description*/ + uint32_t rtc_gpio_pin3_wakeup_enable : 1; /*Need add description*/ + uint32_t rtc_gpio_pin2_wakeup_enable : 1; /*Need add description*/ + uint32_t rtc_gpio_pin1_wakeup_enable : 1; /*Need add description*/ + uint32_t rtc_gpio_pin0_wakeup_enable : 1; /*Need add description*/ + }; + uint32_t val; + } gpio_wakeup; + union { + struct { + uint32_t rtc_mtdi_enamux : 1; /*Need add description*/ + uint32_t rtc_debug_12m_no_gating : 1; /*Need add description*/ + uint32_t rtc_debug_bit_sel : 5; /*Need add description*/ + uint32_t rtc_debug_sel0 : 5; /*Need add description*/ + uint32_t rtc_debug_sel1 : 5; /*Need add description*/ + uint32_t rtc_debug_sel2 : 5; /*Need add description*/ + uint32_t rtc_debug_sel3 : 5; /*Need add description*/ + uint32_t rtc_debug_sel4 : 5; /*Need add description*/ + }; + uint32_t val; + } dbg_sel; + union { + struct { + uint32_t vdd_dig_test : 2; /*Need add description*/ + uint32_t rtc_gpio_pin5_mux_sel : 1; /*Need add description*/ + uint32_t rtc_gpio_pin4_mux_sel : 1; /*Need add description*/ + uint32_t rtc_gpio_pin3_mux_sel : 1; /*Need add description*/ + uint32_t rtc_gpio_pin2_mux_sel : 1; /*Need add description*/ + uint32_t rtc_gpio_pin1_mux_sel : 1; /*Need add description*/ + uint32_t rtc_gpio_pin0_mux_sel : 1; /*Need add description*/ + uint32_t rtc_gpio_pin5_fun_sel : 4; /*Need add description*/ + uint32_t rtc_gpio_pin4_fun_sel : 4; /*Need add description*/ + uint32_t rtc_gpio_pin3_fun_sel : 4; /*Need add description*/ + uint32_t rtc_gpio_pin2_fun_sel : 4; /*Need add description*/ + uint32_t rtc_gpio_pin1_fun_sel : 4; /*Need add description*/ + uint32_t rtc_gpio_pin0_fun_sel : 4; /*Need add description*/ + }; + uint32_t val; + } dbg_map; + union { + struct { + uint32_t reserved0 : 27; /*Reserved*/ + uint32_t sar_debug_sel : 5; /*Need add description*/ + }; + uint32_t val; + } dbg_sar_sel; + union { + struct { + uint32_t reserved0 : 26; /*Reserved*/ + uint32_t power_glitch_dsense : 2; /*Need add description*/ + uint32_t power_glitch_force_pd : 1; /*Need add description*/ + uint32_t power_glitch_force_pu : 1; /*Need add description*/ + uint32_t power_glitch_efuse_sel : 1; /*Need add description*/ + uint32_t power_glitch_en : 1; /*Need add description*/ + }; + uint32_t val; + } pg_ctrl; + union { + struct { + uint32_t vset_dcdc_value : 5; /*Need add description*/ + uint32_t power_good_dcdc : 1; /*Need add description*/ + uint32_t reserved6 : 13; /*Reserved*/ + uint32_t pmu_mode : 2; /*Need add description*/ + uint32_t ramplevel_dcdc : 1; /*Need add description*/ + uint32_t ramp_dcdc : 1; /*Need add description*/ + uint32_t dcm2enb_dcdc : 1; /*Need add description*/ + uint32_t dcmlevel_dcdc : 2; /*Need add description*/ + uint32_t fsw_dcdc : 3; /*Need add description*/ + uint32_t ccm_dcdc : 1; /*Need add description*/ + uint32_t sstime_dcdc : 1; /*Need add description*/ + uint32_t pocpenb_dcdc : 1; /*Need add description*/ + }; + uint32_t val; + } dcdc_ctrl0; + union { + struct { + uint32_t reserved0 : 23; /*Reserved*/ + uint32_t dcdc_mode_slp : 3; /*Need add description*/ + uint32_t dcdc_mode_monitor : 3; /*Need add description*/ + uint32_t dcdc_mode_idle : 3; /*Need add description*/ + }; + uint32_t val; + } dcdc_ctrl1; + union { + struct { + uint32_t vset_dcdc_target_value1 : 5; /*Need add description*/ + uint32_t vset_dcdc_target_value0 : 5; /*Need add description*/ + uint32_t vset_dcdc_init_value : 5; /*Need add description*/ + uint32_t vset_dcdc_init : 1; /*Need add description*/ + uint32_t vset_dcdc_fix : 1; /*Need add description*/ + uint32_t vset_dcdc_step : 5; /*Need add description*/ + uint32_t vset_dcdc_gap : 5; /*Need add description*/ + uint32_t vset_dcdc_sel_hw_sw : 1; /*Need add description*/ + uint32_t vset_dcdc_sw_sel : 1; /*Need add description*/ + uint32_t reserved29 : 3; /*Reserved*/ + }; + uint32_t val; + } dcdc_ctrl2; + union { + struct { + uint32_t reserved0 : 21; /*Reserved*/ + uint32_t rc32k_dfreq : 10; /*Need add description*/ + uint32_t rc32k_xpd : 1; /*Need add description*/ + }; + uint32_t val; + } rc32k_ctrl; + union { + struct { + uint32_t reserved0 : 30; /*Reserved*/ + uint32_t ckref_pll8m_sel : 1; /*Need add description*/ + uint32_t xpd_pll8m : 1; /*Need add description*/ + }; + uint32_t val; + } pll8m; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + union { + struct { + uint32_t date : 28; /*Need add description*/ + uint32_t reserved28 : 4; /*Reserved*/ + }; + uint32_t val; + } date; +} rtc_cntl_dev_t; +extern rtc_cntl_dev_t RTCCNTL; +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_RTC_CNTL_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/rev2/sensitive_reg.h b/components/soc/esp32h2/include/soc/rev2/sensitive_reg.h new file mode 100644 index 0000000000..9a3e6bd81a --- /dev/null +++ b/components/soc/esp32h2/include/soc/rev2/sensitive_reg.h @@ -0,0 +1,2532 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _SOC_SENSITIVE_REG_H_ +#define _SOC_SENSITIVE_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +#define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x0) +/* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_ROM_TABLE_LOCK (BIT(0)) +#define SENSITIVE_ROM_TABLE_LOCK_M (BIT(0)) +#define SENSITIVE_ROM_TABLE_LOCK_V 0x1 +#define SENSITIVE_ROM_TABLE_LOCK_S 0 + +#define SENSITIVE_ROM_TABLE_REG (DR_REG_SENSITIVE_BASE + 0x4) +/* SENSITIVE_ROM_TABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_ROM_TABLE 0xFFFFFFFF +#define SENSITIVE_ROM_TABLE_M ((SENSITIVE_ROM_TABLE_V)<<(SENSITIVE_ROM_TABLE_S)) +#define SENSITIVE_ROM_TABLE_V 0xFFFFFFFF +#define SENSITIVE_ROM_TABLE_S 0 + +#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x8) +/* SENSITIVE_PRIVILEGE_MODE_SEL_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK (BIT(0)) +#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_M (BIT(0)) +#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_V 0x1 +#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_S 0 + +#define SENSITIVE_PRIVILEGE_MODE_SEL_REG (DR_REG_SENSITIVE_BASE + 0xC) +/* SENSITIVE_PRIVILEGE_MODE_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_PRIVILEGE_MODE_SEL (BIT(0)) +#define SENSITIVE_PRIVILEGE_MODE_SEL_M (BIT(0)) +#define SENSITIVE_PRIVILEGE_MODE_SEL_V 0x1 +#define SENSITIVE_PRIVILEGE_MODE_SEL_S 0 + +#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x10) +/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V 0x1 +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S 0 + +#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x14) +/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V 0x1 +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S 0 + +#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x18) +/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V 0x1 +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S 0 + +#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x1C) +/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W ;bitpos:[3:1] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM 0x00000007 +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M ((SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V 0x7 +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S 1 +/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V 0x1 +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S 0 + +#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x20) +/* SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP (BIT(3)) +#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M (BIT(3)) +#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V 0x1 +#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S 3 +/* SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM 0x00000007 +#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M ((SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V 0x7 +#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S 0 + +#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG (DR_REG_SENSITIVE_BASE + 0x24) +/* SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_M (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_V 0x1 +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_S 0 + +#define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x28) +/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M (BIT(0)) +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V 0x1 +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S 0 + +#define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x2C) +/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3)) +#define SENSITIVE_PRO_D_TAG_WR_ACS_M (BIT(3)) +#define SENSITIVE_PRO_D_TAG_WR_ACS_V 0x1 +#define SENSITIVE_PRO_D_TAG_WR_ACS_S 3 +/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_PRO_D_TAG_RD_ACS (BIT(2)) +#define SENSITIVE_PRO_D_TAG_RD_ACS_M (BIT(2)) +#define SENSITIVE_PRO_D_TAG_RD_ACS_V 0x1 +#define SENSITIVE_PRO_D_TAG_RD_ACS_S 2 +/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1)) +#define SENSITIVE_PRO_I_TAG_WR_ACS_M (BIT(1)) +#define SENSITIVE_PRO_I_TAG_WR_ACS_V 0x1 +#define SENSITIVE_PRO_I_TAG_WR_ACS_S 1 +/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_PRO_I_TAG_RD_ACS (BIT(0)) +#define SENSITIVE_PRO_I_TAG_RD_ACS_M (BIT(0)) +#define SENSITIVE_PRO_I_TAG_RD_ACS_V 0x1 +#define SENSITIVE_PRO_I_TAG_RD_ACS_S 0 + +#define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x30) +/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M (BIT(0)) +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V 0x1 +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S 0 + +#define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x34) +/* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_PRO_MMU_WR_ACS (BIT(1)) +#define SENSITIVE_PRO_MMU_WR_ACS_M (BIT(1)) +#define SENSITIVE_PRO_MMU_WR_ACS_V 0x1 +#define SENSITIVE_PRO_MMU_WR_ACS_S 1 +/* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_PRO_MMU_RD_ACS (BIT(0)) +#define SENSITIVE_PRO_MMU_RD_ACS_M (BIT(0)) +#define SENSITIVE_PRO_MMU_RD_ACS_V 0x1 +#define SENSITIVE_PRO_MMU_RD_ACS_S 0 + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x38) +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x3C) +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x40) +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x44) +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x48) +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x4C) +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x50) +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x54) +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x58) +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x5C) +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x60) +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x64) +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x68) +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x6C) +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x70) +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x74) +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x78) +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x7C) +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x80) +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x84) +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x88) +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x8C) +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x90) +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x94) +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x98) +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x9C) +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xA0) +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[26:3] ;default: 24'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 3 +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 1 +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0xA4) +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000000F +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xF +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xA8) +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xAC) +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0xB0) +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0xB4) +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0xB8) +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0xBC) +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xC0) +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xC4) +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[20:18] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 18 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 12 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[11:9] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 9 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[8:6] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 6 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[5:3] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 3 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[2:0] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0xC8) +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[20:18] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 18 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 12 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[11:9] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 9 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[8:6] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 6 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[5:3] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 3 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[2:0] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0xCC) +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0xD0) +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xD4) +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 5 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 3 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE (BIT(2)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M (BIT(2)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S 2 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 1 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xD8) +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xDC) +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[27:26] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 26 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[25:24] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 24 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0xE0) +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0xE4) +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xE8) +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[27:4] ;default: 24'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 4 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 2 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S 1 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0xEC) +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000000F +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xF +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xF0) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xF4) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0xF8) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0xFC) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x100) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST : R/W ;bitpos:[31:30] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR : R/W ;bitpos:[29:28] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX : R/W ;bitpos:[27:26] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ZIGBEEMAC : R/W ;bitpos:[23:22] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ZIGBEEMAC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ZIGBEEMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ZIGBEEMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ZIGBEEMAC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ZIGBEEMAC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ZIGBEEMAC_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC : R/W ;bitpos:[21:20] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S 4 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x104) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[11:10] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[9:8] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x108) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x10C) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x110) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x114) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST : R/W ;bitpos:[31:30] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR : R/W ;bitpos:[29:28] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX : R/W ;bitpos:[27:26] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ZIGBEEMAC : R/W ;bitpos:[23:22] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ZIGBEEMAC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ZIGBEEMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ZIGBEEMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ZIGBEEMAC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ZIGBEEMAC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ZIGBEEMAC_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC : R/W ;bitpos:[21:20] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S 4 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x118) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[11:10] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[9:8] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x11C) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: 11'h7ff ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S 11 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: 11'h7ff ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x120) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S 9 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S 3 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: 3'b111 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x124) +/* SENSITIVE_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x128) +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S 12 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S 10 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S 8 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S 6 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S 4 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S 2 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x12C) +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S 12 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S 10 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S 8 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S 6 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S 4 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S 2 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x130) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x134) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x138) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x13C) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x140) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x144) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x148) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x14C) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x150) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x154) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x158) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(5)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (BIT(5)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 5 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S 1 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x15C) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x160) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x164) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S 3 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x168) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x16C) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x170) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W ;bitpos:[31:30] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S 30 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C : R/W ;bitpos:[27:26] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S 26 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC : R/W ;bitpos:[25:24] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S 24 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S 18 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S 16 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S 14 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W ;bitpos:[11:10] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S 10 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S 6 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S 4 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S 2 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x174) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W ;bitpos:[31:30] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S 30 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S 28 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP : R/W ;bitpos:[27:26] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S 26 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_S 18 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S 16 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT : R/W ;bitpos:[11:10] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S 10 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S 6 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S 4 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x178) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W ;bitpos:[23:22] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S 22 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S 14 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W ;bitpos:[11:10] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S 10 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S 4 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x17C) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST : R/W ;bitpos:[31:30] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_S 30 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR : R/W ;bitpos:[29:28] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_S 28 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX : R/W ;bitpos:[27:26] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_S 26 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ZIGBEEMAC : R/W ;bitpos:[23:22] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ZIGBEEMAC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ZIGBEEMAC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ZIGBEEMAC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ZIGBEEMAC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ZIGBEEMAC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ZIGBEEMAC_S 22 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC : R/W ;bitpos:[21:20] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_S 20 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_S 18 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM : R/W ;bitpos:[17:16] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_S 16 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W ;bitpos:[15:14] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S 14 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W ;bitpos:[9:8] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S 8 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S 6 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S 4 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x180) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_S 2 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x184) +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x188) +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x18C) +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(6)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (BIT(6)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 6 +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x7 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 3 +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S 1 +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x190) +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Need add description.*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR 0xFFFFFFFF +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_M ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V 0xFFFFFFFF +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S 0 + +#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x194) +/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Need add description.*/ +#define SENSITIVE_CLK_EN (BIT(0)) +#define SENSITIVE_CLK_EN_M (BIT(0)) +#define SENSITIVE_CLK_EN_V 0x1 +#define SENSITIVE_CLK_EN_S 0 + +#define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xFFC) +/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2108250 ; */ +/*description: Need add description.*/ +#define SENSITIVE_DATE 0x0FFFFFFF +#define SENSITIVE_DATE_M ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S)) +#define SENSITIVE_DATE_V 0xFFFFFFF +#define SENSITIVE_DATE_S 0 + + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_SENSITIVE_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/rtc.h b/components/soc/esp32h2/include/soc/rtc.h index 5585986ed2..eaa0f39a89 100644 --- a/components/soc/esp32h2/include/soc/rtc.h +++ b/components/soc/esp32h2/include/soc/rtc.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include @@ -154,6 +146,19 @@ typedef enum { RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL } rtc_xtal_freq_t; +#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 +/** + * @brief CPU frequency values + */ +typedef enum { + RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency + RTC_CPU_FREQ_80M = 1, //!< 80 MHz + RTC_CPU_FREQ_160M = 2, //!< 160 MHz + RTC_CPU_FREQ_240M = 3, //!< 240 MHz + RTC_CPU_FREQ_2M = 4, //!< 2 MHz +} rtc_cpu_freq_t; +#endif + /** * @brief CPU clock source */ diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index d3b8ddecfa..9f62fba39b 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -4,6 +4,7 @@ // include them here. #pragma once +#include "sdkconfig.h" /*-------------------------- COMMON CAPS ---------------------------------------*/ #define SOC_CPU_CORES_NUM 1 @@ -79,7 +80,11 @@ /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-C3 has 1 GPIO peripheral #define SOC_GPIO_PORT (1) +#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 +#define SOC_GPIO_PIN_COUNT (26) +#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 #define SOC_GPIO_PIN_COUNT (22) +#endif // Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC // On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers. diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 686edcbc74..dbacea4ab0 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -1949,6 +1949,7 @@ components/soc/esp32c3/spi_periph.c components/soc/esp32c3/uart_periph.c components/soc/esp32h2/adc_periph.c components/soc/esp32h2/gpio_periph.c +components/soc/esp32h2/gdma_periph.c components/soc/esp32h2/i2c_periph.c components/soc/esp32h2/i2s_periph.c components/soc/esp32h2/include/soc/adc_channel.h @@ -1956,7 +1957,6 @@ components/soc/esp32h2/include/soc/apb_ctrl_reg.h components/soc/esp32h2/include/soc/apb_ctrl_struct.h components/soc/esp32h2/include/soc/apb_saradc_reg.h components/soc/esp32h2/include/soc/apb_saradc_struct.h -components/soc/esp32h2/include/soc/assist_debug_reg.h components/soc/esp32h2/include/soc/bb_reg.h components/soc/esp32h2/include/soc/boot_mode.h components/soc/esp32h2/include/soc/clkout_channel.h @@ -1977,7 +1977,6 @@ components/soc/esp32h2/include/soc/i2c_reg.h components/soc/esp32h2/include/soc/i2c_struct.h components/soc/esp32h2/include/soc/i2s_reg.h components/soc/esp32h2/include/soc/i2s_struct.h -components/soc/esp32h2/include/soc/interrupt_core0_reg.h components/soc/esp32h2/include/soc/interrupt_reg.h components/soc/esp32h2/include/soc/io_mux_reg.h components/soc/esp32h2/include/soc/ledc_reg.h @@ -1987,14 +1986,10 @@ components/soc/esp32h2/include/soc/periph_defs.h components/soc/esp32h2/include/soc/reset_reasons.h components/soc/esp32h2/include/soc/rmt_reg.h components/soc/esp32h2/include/soc/rmt_struct.h -components/soc/esp32h2/include/soc/rtc.h components/soc/esp32h2/include/soc/rtc_caps.h -components/soc/esp32h2/include/soc/rtc_cntl_reg.h -components/soc/esp32h2/include/soc/rtc_cntl_struct.h components/soc/esp32h2/include/soc/rtc_i2c_reg.h components/soc/esp32h2/include/soc/rtc_i2c_struct.h components/soc/esp32h2/include/soc/rtc_io_caps.h -components/soc/esp32h2/include/soc/sensitive_reg.h components/soc/esp32h2/include/soc/sensitive_struct.h components/soc/esp32h2/include/soc/soc.h components/soc/esp32h2/include/soc/soc_caps.h