diff --git a/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h b/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h index 55d843484d..a487424ff7 100644 --- a/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h +++ b/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -68,13 +68,12 @@ #define SLAVE_IOMUX_PIN_WP SPI3_IOMUX_PIN_NUM_WP #define SLAVE_IOMUX_PIN_HD SPI3_IOMUX_PIN_NUM_HD -#define UNCONNECTED_PIN 27 #define INPUT_ONLY_PIN 34 #define GPIO_DELAY (12.5*2) #define ESP_SPI_SLAVE_TV (12.5*3.5) #define WIRE_DELAY 12.5 -#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32H4 +#else // CONFIG_IDF_TARGET_ESP32 #define SLAVE_IOMUX_PIN_MISO -1 #define SLAVE_IOMUX_PIN_MOSI -1 #define SLAVE_IOMUX_PIN_SCLK -1 @@ -82,24 +81,13 @@ #define SLAVE_IOMUX_PIN_WP -1 #define SLAVE_IOMUX_PIN_HD -1 -#if CONFIG_IDF_TARGET_ESP32H4 -#define UNCONNECTED_PIN 27 -#else -#define UNCONNECTED_PIN 41 -#endif #define INPUT_ONLY_PIN 46 #define GPIO_DELAY 0 #define ESP_SPI_SLAVE_TV 0 #define WIRE_DELAY 12.5 - -#else -#define UNCONNECTED_PIN 8 -#define GPIO_DELAY 0 -#define ESP_SPI_SLAVE_TV 0 -#define WIRE_DELAY 12.5 #endif //CONFIG_IDF_TARGET_ESP32 -#define FUNC_SPI SPI2_FUNC_NUM +#define FUNC_SPI SPI2_FUNC_NUM_QUAD #define FUNC_GPIO PIN_FUNC_GPIO //Delay information diff --git a/components/esp_driver_sdspi/test_apps/sdspi/README.md b/components/esp_driver_sdspi/test_apps/sdspi/README.md index 44f3780f1d..d76348d52c 100644 --- a/components/esp_driver_sdspi/test_apps/sdspi/README.md +++ b/components/esp_driver_sdspi/test_apps/sdspi/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | diff --git a/components/esp_driver_spi/src/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c index de5ec5d309..24d8f468c6 100644 --- a/components/esp_driver_spi/src/gpspi/spi_common.c +++ b/components/esp_driver_spi/src/gpspi/spi_common.c @@ -536,25 +536,18 @@ static bool check_iomux_pins_oct(spi_host_device_t host, const spi_bus_config_t* static bool check_iomux_pins_quad(spi_host_device_t host, const spi_bus_config_t* bus_config) { - if (bus_config->sclk_io_num >= 0 && - bus_config->sclk_io_num != spi_periph_signal[host].spiclk_iomux_pin) { - return false; - } - if (bus_config->quadwp_io_num >= 0 && - bus_config->quadwp_io_num != spi_periph_signal[host].spiwp_iomux_pin) { - return false; - } - if (bus_config->quadhd_io_num >= 0 && - bus_config->quadhd_io_num != spi_periph_signal[host].spihd_iomux_pin) { - return false; - } - if (bus_config->mosi_io_num >= 0 && - bus_config->mosi_io_num != spi_periph_signal[host].spid_iomux_pin) { - return false; - } - if (bus_config->miso_io_num >= 0 && - bus_config->miso_io_num != spi_periph_signal[host].spiq_iomux_pin) { - return false; + int io_nums[] = {bus_config->data0_io_num, bus_config->data1_io_num, bus_config->data2_io_num, bus_config->data3_io_num, bus_config->sclk_io_num}; + int io_mux_nums[] = {spi_periph_signal[host].spid_iomux_pin, spi_periph_signal[host].spiq_iomux_pin, spi_periph_signal[host].spiwp_iomux_pin, spi_periph_signal[host].spihd_iomux_pin, spi_periph_signal[host].spiclk_iomux_pin}; +#ifdef SPI2_IOMUX_PIN_2_NUM_MOSI + int io_mux_2_nums[] = {SPI2_IOMUX_PIN_2_NUM_MOSI, SPI2_IOMUX_PIN_2_NUM_MISO, SPI2_IOMUX_PIN_2_NUM_WP, SPI2_IOMUX_PIN_2_NUM_HD, SPI2_IOMUX_PIN_2_NUM_CLK}; +#else + // use same pin again to fake the second set of pins + int *io_mux_2_nums = io_mux_nums; +#endif + for (size_t i = 0; i < sizeof(io_nums) / sizeof(io_nums[0]); i++) { + if (io_nums[i] >= 0 && (io_nums[i] != io_mux_nums[i]) && (io_nums[i] != io_mux_2_nums[i])) { + return false; + } } return true; } @@ -594,25 +587,14 @@ static void bus_iomux_pins_set_oct(spi_host_device_t host, const spi_bus_config_ static void bus_iomux_pins_set_quad(spi_host_device_t host, const spi_bus_config_t* bus_config) { - if (bus_config->mosi_io_num >= 0) { - gpio_iomux_input(bus_config->mosi_io_num, spi_periph_signal[host].func, spi_periph_signal[host].spid_in); - gpio_iomux_output(bus_config->mosi_io_num, spi_periph_signal[host].func); - } - if (bus_config->miso_io_num >= 0) { - gpio_iomux_input(bus_config->miso_io_num, spi_periph_signal[host].func, spi_periph_signal[host].spiq_in); - gpio_iomux_output(bus_config->miso_io_num, spi_periph_signal[host].func); - } - if (bus_config->quadwp_io_num >= 0) { - gpio_iomux_input(bus_config->quadwp_io_num, spi_periph_signal[host].func, spi_periph_signal[host].spiwp_in); - gpio_iomux_output(bus_config->quadwp_io_num, spi_periph_signal[host].func); - } - if (bus_config->quadhd_io_num >= 0) { - gpio_iomux_input(bus_config->quadhd_io_num, spi_periph_signal[host].func, spi_periph_signal[host].spihd_in); - gpio_iomux_output(bus_config->quadhd_io_num, spi_periph_signal[host].func); - } - if (bus_config->sclk_io_num >= 0) { - gpio_iomux_input(bus_config->sclk_io_num, spi_periph_signal[host].func, spi_periph_signal[host].spiclk_in); - gpio_iomux_output(bus_config->sclk_io_num, spi_periph_signal[host].func); + int io_nums[] = {bus_config->data0_io_num, bus_config->data1_io_num, bus_config->data2_io_num, bus_config->data3_io_num, bus_config->sclk_io_num}; + int io_signals[] = {spi_periph_signal[host].spid_in, spi_periph_signal[host].spiq_in, spi_periph_signal[host].spiwp_in, spi_periph_signal[host].spihd_in, spi_periph_signal[host].spiclk_in}; + + for (size_t i = 0; i < sizeof(io_nums) / sizeof(io_nums[0]); i++) { + if (io_nums[i] >= 0) { + gpio_iomux_input(io_nums[i], spi_periph_signal[host].func, io_signals[i]); + gpio_iomux_output(io_nums[i], spi_periph_signal[host].func); + } } } diff --git a/components/esp_driver_spi/src/gpspi/spi_master.c b/components/esp_driver_spi/src/gpspi/spi_master.c index bdcb863dc1..c999d9a47d 100644 --- a/components/esp_driver_spi/src/gpspi/spi_master.c +++ b/components/esp_driver_spi/src/gpspi/spi_master.c @@ -687,6 +687,7 @@ static SPI_MASTER_ISR_ATTR void spi_setup_device(spi_device_t *dev, spi_trans_pr #if SPI_LL_SRC_PRE_DIV_MAX //we set mst_div as const 2, then (hs_clk = 2*mst_clk) to ensure timing turning work as past //and sure (hs_div * mst_div = source_pre_div) + assert(hal_dev->timing_conf.source_pre_div >= 2); // source_pre_div must be even and at least 2 spi_ll_clk_source_pre_div(hal->hw, hal_dev->timing_conf.source_pre_div / 2, 2); #endif spi_ll_set_clk_source(hal->hw, hal_dev->timing_conf.clock_source); diff --git a/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h b/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h index 0abbdf81b5..a7e3005e81 100644 --- a/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h +++ b/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h @@ -104,4 +104,10 @@ #define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 60 #define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 25 +#elif CONFIG_IDF_TARGET_ESP32S31 +#define IDF_TARGET_MAX_SPI_CLK_FREQ 40*1000*1000 +#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 22 +#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 17 +#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 32 +#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 28 #endif diff --git a/components/esp_driver_spi/test_apps/master/README.md b/components/esp_driver_spi/test_apps/master/README.md index 44f3780f1d..d76348d52c 100644 --- a/components/esp_driver_spi/test_apps/master/README.md +++ b/components/esp_driver_spi/test_apps/master/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | diff --git a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c index acaac7cc13..9900bba71a 100644 --- a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c +++ b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c @@ -138,7 +138,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") // Test All clock source #define TEST_CLK_BYTE_LEN 10000 -#define TEST_TRANS_TIME_BIAS_RATIO (float)10.0/100 // think 10% transfer time bias as acceptable +#define TEST_TRANS_TIME_BIAS_RATIO (float)15.0/100 // think 15% transfer time bias as acceptable TEST_CASE("SPI Master clk_source and divider accuracy", "[spi]") { int64_t start = 0, end = 0; @@ -677,6 +677,24 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") }; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + +#ifdef SPI2_IOMUX_PIN_2_NUM_MOSI + ESP_LOGI(TAG, "check 2nd set of iomux pins..."); + flags_expected = SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_QUAD | SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_IOMUX_PINS; + // all 2nd iomux pins + cfg = (spi_bus_config_t) { + .mosi_io_num = SPI2_IOMUX_PIN_2_NUM_MOSI, .miso_io_num = SPI2_IOMUX_PIN_2_NUM_MISO, .sclk_io_num = SPI2_IOMUX_PIN_2_NUM_CLK, .quadhd_io_num = SPI2_IOMUX_PIN_2_NUM_HD, .quadwp_io_num = SPI2_IOMUX_PIN_2_NUM_WP, + }; + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o); + + // mixed 1st and 2nd iomux pins + cfg = (spi_bus_config_t) { + .mosi_io_num = SPI2_IOMUX_PIN_NUM_MOSI, .miso_io_num = SPI2_IOMUX_PIN_2_NUM_MISO, .sclk_io_num = SPI2_IOMUX_PIN_2_NUM_CLK, .quadhd_io_num = SPI2_IOMUX_PIN_NUM_HD, .quadwp_io_num = SPI2_IOMUX_PIN_2_NUM_WP, + }; + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o); +#endif } TEST_CASE("SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)", "[spi]") @@ -934,7 +952,7 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first) //initial master, mode 0, 1MHz spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG(); - buscfg.quadhd_io_num = UNCONNECTED_PIN; + buscfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS; TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO)); spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); devcfg.clock_speed_hz = 1 * 1000 * 1000; diff --git a/components/esp_driver_spi/test_apps/master/main/test_spi_sio.c b/components/esp_driver_spi/test_apps/master/main/test_spi_sio.c index 1b6064a76c..a3fedd9daf 100644 --- a/components/esp_driver_spi/test_apps/master/main/test_spi_sio.c +++ b/components/esp_driver_spi/test_apps/master/main/test_spi_sio.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -35,27 +35,6 @@ /******************************************************************************** * Test SIO ********************************************************************************/ -#if CONFIG_IDF_TARGET_ESP32 -#define MASTER_DIN_SIGNAL HSPID_IN_IDX -#elif CONFIG_IDF_TARGET_ESP32P4 -#define MASTER_DIN_SIGNAL SPI2_D_PAD_IN_IDX -#else -#define MASTER_DIN_SIGNAL FSPID_IN_IDX -#endif -static void inner_connect(spi_bus_config_t bus) -{ - //Master MOSI(spid_out) output to `mosi_num` - spitest_gpio_output_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); - //Slave MOSI(spid_in) input to `mosi_num` - spitest_gpio_input_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spid_in); - - //Master MOSI input(spid_in) to `miso_num`, due to SIO mode, we use Master's `spid_in` to receive data - spitest_gpio_input_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_in); - //Slave MISO output(spiq_out) - spitest_gpio_output_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out); - //Force this signal goes through gpio matrix - GPIO.func_in_sel_cfg[MASTER_DIN_SIGNAL].sig_in_sel = 1; -} TEST_CASE("SPI Single Board Test SIO", "[spi]") { @@ -76,7 +55,8 @@ TEST_CASE("SPI Single Board Test SIO", "[spi]") TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, SPI_DMA_DISABLED)); same_pin_func_sel(TEST_SPI_HOST, TEST_SLAVE_HOST, bus_cfg, dev_cfg.spics_io_num); - inner_connect(bus_cfg); + // fix sio internal connection + spitest_gpio_input_sel(bus_cfg.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_in); WORD_ALIGNED_ATTR uint8_t master_rx_buffer[320]; WORD_ALIGNED_ATTR uint8_t slave_rx_buffer[320]; diff --git a/components/esp_driver_spi/test_apps/master/pytest_spi_master.py b/components/esp_driver_spi/test_apps/master/pytest_spi_master.py index 0ad809771e..5f30618445 100644 --- a/components/esp_driver_spi/test_apps/master/pytest_spi_master.py +++ b/components/esp_driver_spi/test_apps/master/pytest_spi_master.py @@ -85,6 +85,6 @@ def test_master_esp_flash(case_tester) -> None: # type: ignore indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) -@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done') +@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='no runner') def test_master_multi_dev(case_tester) -> None: # type: ignore case_tester.run_all_multi_dev_cases(reset=True) diff --git a/components/esp_driver_spi/test_apps/param/README.md b/components/esp_driver_spi/test_apps/param/README.md index 44f3780f1d..d76348d52c 100644 --- a/components/esp_driver_spi/test_apps/param/README.md +++ b/components/esp_driver_spi/test_apps/param/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | diff --git a/components/esp_driver_spi/test_apps/param/main/test_spi_param.c b/components/esp_driver_spi/test_apps/param/main/test_spi_param.c index d8617f9385..f666e5dcf9 100644 --- a/components/esp_driver_spi/test_apps/param/main/test_spi_param.c +++ b/components/esp_driver_spi/test_apps/param/main/test_spi_param.c @@ -106,8 +106,8 @@ static void local_test_start(spi_device_handle_t *spi, int freq, const spitest_p devcfg.spics_io_num = MASTER_IOMUX_PIN_CS; slvcfg.spics_io_num = MASTER_IOMUX_PIN_CS; } - //this does nothing, but avoid the driver from using iomux pins if required - buscfg.quadhd_io_num = (!pset->master_iomux && !pset->slave_iomux ? UNCONNECTED_PIN : -1); + bool use_iomux = pset->master_iomux || pset->slave_iomux; + buscfg.flags |= (use_iomux ? 0 : SPICOMMON_BUSFLAG_GPIO_PINS); devcfg.mode = pset->mode; const int cs_pretrans_max = 15; if (pset->dup == HALF_DUPLEX_MISO) { @@ -721,10 +721,8 @@ static void test_master_start(spi_device_handle_t *spi, int freq, const spitest_ { //master config spi_bus_config_t buspset = SPI_BUS_TEST_DEFAULT_CONFIG(); - //this does nothing, but avoid the driver from using native pins - if (!pset->master_iomux) { - buspset.quadhd_io_num = UNCONNECTED_PIN; - } + buspset.flags |= (pset->master_iomux ? 0 : SPICOMMON_BUSFLAG_GPIO_PINS); + spi_device_interface_config_t devpset = SPI_DEVICE_TEST_DEFAULT_CONFIG(); devpset.spics_io_num = PIN_NUM_CS; devpset.mode = pset->mode; @@ -865,10 +863,8 @@ static void timing_slave_start(int speed, const spitest_param_set_t *pset, spite { //slave config spi_bus_config_t slv_buscfg = SPI_BUS_TEST_DEFAULT_CONFIG(); - //this does nothing, but avoid the driver from using native pins - if (!pset->slave_iomux) { - slv_buscfg.quadhd_io_num = UNCONNECTED_PIN; - } + slv_buscfg.flags |= (pset->slave_iomux ? 0 : SPICOMMON_BUSFLAG_GPIO_PINS); + spi_slave_interface_config_t slvcfg = SPI_SLAVE_TEST_DEFAULT_CONFIG(); slvcfg.spics_io_num = PIN_NUM_CS; slvcfg.mode = pset->mode; diff --git a/components/esp_driver_spi/test_apps/param/pytest_spi_param.py b/components/esp_driver_spi/test_apps/param/pytest_spi_param.py index 93ad65cc09..9813e838d1 100644 --- a/components/esp_driver_spi/test_apps/param/pytest_spi_param.py +++ b/components/esp_driver_spi/test_apps/param/pytest_spi_param.py @@ -6,7 +6,6 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.generic @idf_parametrize('target', ['supported_targets'], indirect=['target']) -@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done') def test_param_single_dev(case_tester) -> None: # type: ignore case_tester.run_all_normal_cases(reset=True) @@ -14,6 +13,6 @@ def test_param_single_dev(case_tester) -> None: # type: ignore @pytest.mark.generic_multi_device @pytest.mark.parametrize('count', [2], indirect=True) @idf_parametrize('target', ['supported_targets'], indirect=['target']) -@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done') +@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='no runner') def test_param_multi_dev(case_tester) -> None: # type: ignore case_tester.run_all_multi_dev_cases(reset=True) diff --git a/components/esp_driver_spi/test_apps/slave/README.md b/components/esp_driver_spi/test_apps/slave/README.md index 44f3780f1d..d76348d52c 100644 --- a/components/esp_driver_spi/test_apps/slave/README.md +++ b/components/esp_driver_spi/test_apps/slave/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | diff --git a/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py b/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py index 7cc16d2bef..e2d3e2a48b 100644 --- a/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py +++ b/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py @@ -32,6 +32,7 @@ def test_slave_single_dev_esp32c5_rev1(case_tester) -> None: # type: ignore @pytest.mark.generic_multi_device @pytest.mark.parametrize('count, config', [(2, 'release'), (2, 'iram_safe')], indirect=True) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='no runner') @pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done') def test_slave_multi_dev(case_tester) -> None: # type: ignore case_tester.run_all_multi_dev_cases(reset=True) diff --git a/components/esp_driver_spi/test_apps/slave_hd/README.md b/components/esp_driver_spi/test_apps/slave_hd/README.md index b91fc54735..c5f27873ef 100644 --- a/components/esp_driver_spi/test_apps/slave_hd/README.md +++ b/components/esp_driver_spi/test_apps/slave_hd/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | diff --git a/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py b/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py index 6ad2b4d1d3..58c1f5ff75 100644 --- a/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py +++ b/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py @@ -28,5 +28,6 @@ def test_slave_hd_single_dev_esp32c5_rev1(case_tester) -> None: # type: ignore @pytest.mark.generic_multi_device @pytest.mark.parametrize('count, config', [(2, 'release')], indirect=True) @idf_parametrize('target', soc_filtered_targets('SOC_SPI_SUPPORT_SLAVE_HD_VER2 == 1'), indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='no runner') def test_slave_hd_multi_dev(case_tester) -> None: # type: ignore case_tester.run_all_multi_dev_cases(reset=True) diff --git a/components/esp_hal_gpspi/esp32/include/soc/spi_pins.h b/components/esp_hal_gpspi/esp32/include/soc/spi_pins.h index 2603bb381b..573708e8c7 100644 --- a/components/esp_hal_gpspi/esp32/include/soc/spi_pins.h +++ b/components/esp_hal_gpspi/esp32/include/soc/spi_pins.h @@ -23,7 +23,7 @@ #define SPI_D2WD_PIN_NUM_WP 7 #define SPI_D2WD_PIN_NUM_HD 11 -#define SPI2_FUNC_NUM 1 +#define SPI2_FUNC_NUM_QUAD 1 #define SPI2_IOMUX_PIN_NUM_MISO 12 #define SPI2_IOMUX_PIN_NUM_MOSI 13 #define SPI2_IOMUX_PIN_NUM_CLK 14 diff --git a/components/esp_hal_gpspi/esp32/spi_periph.c b/components/esp_hal_gpspi/esp32/spi_periph.c index ef1a28181e..a607705145 100644 --- a/components/esp_hal_gpspi/esp32/spi_periph.c +++ b/components/esp_hal_gpspi/esp32/spi_periph.c @@ -54,7 +54,7 @@ const spi_signal_conn_t spi_periph_signal[3] = { .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS, .irq = ETS_SPI2_INTR_SOURCE, .irq_dma = ETS_SPI2_DMA_INTR_SOURCE, - .func = SPI2_FUNC_NUM, + .func = SPI2_FUNC_NUM_QUAD, .hw = &SPI2 }, { .spiclk_out = VSPICLK_OUT_IDX, diff --git a/components/esp_hal_gpspi/esp32c2/include/soc/spi_pins.h b/components/esp_hal_gpspi/esp32c2/include/soc/spi_pins.h index 45bccaef27..3318872b61 100644 --- a/components/esp_hal_gpspi/esp32c2/include/soc/spi_pins.h +++ b/components/esp_hal_gpspi/esp32c2/include/soc/spi_pins.h @@ -16,7 +16,7 @@ #define MSPI_IOMUX_PIN_NUM_MISO 17 // GPSPI2 IOMUX PINs -#define SPI2_FUNC_NUM 2 +#define SPI2_FUNC_NUM_QUAD 2 #define SPI2_IOMUX_PIN_NUM_MISO 2 #define SPI2_IOMUX_PIN_NUM_HD 4 #define SPI2_IOMUX_PIN_NUM_WP 5 diff --git a/components/esp_hal_gpspi/esp32c2/spi_periph.c b/components/esp_hal_gpspi/esp32c2/spi_periph.c index 437d0e2732..59915609e4 100644 --- a/components/esp_hal_gpspi/esp32c2/spi_periph.c +++ b/components/esp_hal_gpspi/esp32c2/spi_periph.c @@ -57,6 +57,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .irq = ETS_SPI2_INTR_SOURCE, .irq_dma = -1, .hw = &GPSPI2, - .func = SPI2_FUNC_NUM, + .func = SPI2_FUNC_NUM_QUAD, } }; diff --git a/components/esp_hal_gpspi/esp32c3/include/soc/spi_pins.h b/components/esp_hal_gpspi/esp32c3/include/soc/spi_pins.h index 45bccaef27..3318872b61 100644 --- a/components/esp_hal_gpspi/esp32c3/include/soc/spi_pins.h +++ b/components/esp_hal_gpspi/esp32c3/include/soc/spi_pins.h @@ -16,7 +16,7 @@ #define MSPI_IOMUX_PIN_NUM_MISO 17 // GPSPI2 IOMUX PINs -#define SPI2_FUNC_NUM 2 +#define SPI2_FUNC_NUM_QUAD 2 #define SPI2_IOMUX_PIN_NUM_MISO 2 #define SPI2_IOMUX_PIN_NUM_HD 4 #define SPI2_IOMUX_PIN_NUM_WP 5 diff --git a/components/esp_hal_gpspi/esp32c3/spi_periph.c b/components/esp_hal_gpspi/esp32c3/spi_periph.c index 437d0e2732..59915609e4 100644 --- a/components/esp_hal_gpspi/esp32c3/spi_periph.c +++ b/components/esp_hal_gpspi/esp32c3/spi_periph.c @@ -57,6 +57,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .irq = ETS_SPI2_INTR_SOURCE, .irq_dma = -1, .hw = &GPSPI2, - .func = SPI2_FUNC_NUM, + .func = SPI2_FUNC_NUM_QUAD, } }; diff --git a/components/esp_hal_gpspi/esp32c5/include/soc/spi_pins.h b/components/esp_hal_gpspi/esp32c5/include/soc/spi_pins.h index 535ba47d50..8749dde0db 100644 --- a/components/esp_hal_gpspi/esp32c5/include/soc/spi_pins.h +++ b/components/esp_hal_gpspi/esp32c5/include/soc/spi_pins.h @@ -17,7 +17,7 @@ #define MSPI_IOMUX_PIN_NUM_CS1 15 // GPSPI2 IOMUX PINs -#define SPI2_FUNC_NUM 2 +#define SPI2_FUNC_NUM_QUAD 2 #define SPI2_IOMUX_PIN_NUM_MISO 2 #define SPI2_IOMUX_PIN_NUM_HD 4 #define SPI2_IOMUX_PIN_NUM_WP 5 diff --git a/components/esp_hal_gpspi/esp32c5/spi_periph.c b/components/esp_hal_gpspi/esp32c5/spi_periph.c index 4c5fd84d12..5931f666e9 100644 --- a/components/esp_hal_gpspi/esp32c5/spi_periph.c +++ b/components/esp_hal_gpspi/esp32c5/spi_periph.c @@ -35,7 +35,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .irq = ETS_GPSPI2_INTR_SOURCE, .irq_dma = -1, .hw = &GPSPI2, - .func = SPI2_FUNC_NUM, + .func = SPI2_FUNC_NUM_QUAD, }, }; diff --git a/components/esp_hal_gpspi/esp32c6/include/soc/spi_pins.h b/components/esp_hal_gpspi/esp32c6/include/soc/spi_pins.h index d49ad210fb..a1b335626c 100644 --- a/components/esp_hal_gpspi/esp32c6/include/soc/spi_pins.h +++ b/components/esp_hal_gpspi/esp32c6/include/soc/spi_pins.h @@ -16,7 +16,7 @@ #define MSPI_IOMUX_PIN_NUM_MISO 25 // GPSPI2 IOMUX PINs -#define SPI2_FUNC_NUM 2 +#define SPI2_FUNC_NUM_QUAD 2 #define SPI2_IOMUX_PIN_NUM_MISO 2 #define SPI2_IOMUX_PIN_NUM_HD 4 #define SPI2_IOMUX_PIN_NUM_WP 5 diff --git a/components/esp_hal_gpspi/esp32c6/spi_periph.c b/components/esp_hal_gpspi/esp32c6/spi_periph.c index 8331c591b9..06f9c3a884 100644 --- a/components/esp_hal_gpspi/esp32c6/spi_periph.c +++ b/components/esp_hal_gpspi/esp32c6/spi_periph.c @@ -35,7 +35,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .irq = ETS_GSPI2_INTR_SOURCE, .irq_dma = -1, .hw = &GPSPI2, - .func = SPI2_FUNC_NUM, + .func = SPI2_FUNC_NUM_QUAD, } }; diff --git a/components/esp_hal_gpspi/esp32c61/include/soc/spi_pins.h b/components/esp_hal_gpspi/esp32c61/include/soc/spi_pins.h index b3673f360d..c210d33d10 100644 --- a/components/esp_hal_gpspi/esp32c61/include/soc/spi_pins.h +++ b/components/esp_hal_gpspi/esp32c61/include/soc/spi_pins.h @@ -17,7 +17,7 @@ #define MSPI_IOMUX_PIN_NUM_HD 19 // GPSPI2 IOMUX PINs -#define SPI2_FUNC_NUM 2 +#define SPI2_FUNC_NUM_QUAD 2 #define SPI2_IOMUX_PIN_NUM_MISO 2 #define SPI2_IOMUX_PIN_NUM_HD 3 #define SPI2_IOMUX_PIN_NUM_WP 4 diff --git a/components/esp_hal_gpspi/esp32c61/spi_periph.c b/components/esp_hal_gpspi/esp32c61/spi_periph.c index 4c5fd84d12..5931f666e9 100644 --- a/components/esp_hal_gpspi/esp32c61/spi_periph.c +++ b/components/esp_hal_gpspi/esp32c61/spi_periph.c @@ -35,7 +35,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .irq = ETS_GPSPI2_INTR_SOURCE, .irq_dma = -1, .hw = &GPSPI2, - .func = SPI2_FUNC_NUM, + .func = SPI2_FUNC_NUM_QUAD, }, }; diff --git a/components/esp_hal_gpspi/esp32h2/include/soc/spi_pins.h b/components/esp_hal_gpspi/esp32h2/include/soc/spi_pins.h index 13b399e75d..3957355ccc 100644 --- a/components/esp_hal_gpspi/esp32h2/include/soc/spi_pins.h +++ b/components/esp_hal_gpspi/esp32h2/include/soc/spi_pins.h @@ -16,7 +16,7 @@ #define MSPI_IOMUX_PIN_NUM_MISO 16 // GPSPI2 IOMUX PINs -#define SPI2_FUNC_NUM 2 +#define SPI2_FUNC_NUM_QUAD 2 #define SPI2_IOMUX_PIN_NUM_MISO 0 #define SPI2_IOMUX_PIN_NUM_HD 3 #define SPI2_IOMUX_PIN_NUM_WP 2 diff --git a/components/esp_hal_gpspi/esp32h2/spi_periph.c b/components/esp_hal_gpspi/esp32h2/spi_periph.c index c668285789..450d0a3f5e 100644 --- a/components/esp_hal_gpspi/esp32h2/spi_periph.c +++ b/components/esp_hal_gpspi/esp32h2/spi_periph.c @@ -35,7 +35,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .irq = ETS_GSPI2_INTR_SOURCE, .irq_dma = -1, .hw = &GPSPI2, - .func = SPI2_FUNC_NUM, + .func = SPI2_FUNC_NUM_QUAD, } }; diff --git a/components/esp_hal_gpspi/esp32h21/include/soc/spi_pins.h b/components/esp_hal_gpspi/esp32h21/include/soc/spi_pins.h index 9d884a5d41..165472c04d 100644 --- a/components/esp_hal_gpspi/esp32h21/include/soc/spi_pins.h +++ b/components/esp_hal_gpspi/esp32h21/include/soc/spi_pins.h @@ -17,7 +17,7 @@ #define MSPI_IOMUX_PIN_NUM_MISO 21 // GPSPI2 IOMUX PINs -#define SPI2_FUNC_NUM 2 +#define SPI2_FUNC_NUM_QUAD 2 #define SPI2_IOMUX_PIN_NUM_WP 0 #define SPI2_IOMUX_PIN_NUM_HD 1 #define SPI2_IOMUX_PIN_NUM_CLK 2 diff --git a/components/esp_hal_gpspi/esp32h21/spi_periph.c b/components/esp_hal_gpspi/esp32h21/spi_periph.c index 65928c8df2..8faa447f4e 100644 --- a/components/esp_hal_gpspi/esp32h21/spi_periph.c +++ b/components/esp_hal_gpspi/esp32h21/spi_periph.c @@ -35,7 +35,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .irq = ETS_GPSPI2_INTR_SOURCE, .irq_dma = -1, .hw = &GPSPI2, - .func = SPI2_FUNC_NUM, + .func = SPI2_FUNC_NUM_QUAD, } }; diff --git a/components/esp_hal_gpspi/esp32h4/include/soc/spi_pins.h b/components/esp_hal_gpspi/esp32h4/include/soc/spi_pins.h index fa9dffa36d..1bb316299b 100644 --- a/components/esp_hal_gpspi/esp32h4/include/soc/spi_pins.h +++ b/components/esp_hal_gpspi/esp32h4/include/soc/spi_pins.h @@ -15,7 +15,7 @@ #define MSPI_IOMUX_PIN_NUM_CLK 11 #define MSPI_IOMUX_PIN_NUM_MOSI 12 -#define SPI2_FUNC_NUM 2 +#define SPI2_FUNC_NUM_QUAD 2 #define SPI2_IOMUX_PIN_NUM_MISO 15 #define SPI2_IOMUX_PIN_NUM_HD 19 #define SPI2_IOMUX_PIN_NUM_WP 18 diff --git a/components/esp_hal_gpspi/esp32h4/spi_periph.c b/components/esp_hal_gpspi/esp32h4/spi_periph.c index a013e32f2b..8b227d3ff2 100644 --- a/components/esp_hal_gpspi/esp32h4/spi_periph.c +++ b/components/esp_hal_gpspi/esp32h4/spi_periph.c @@ -35,7 +35,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .irq = ETS_GPSPI2_INTR_SOURCE, .irq_dma = -1, .hw = &GPSPI2, - .func = SPI2_FUNC_NUM, + .func = SPI2_FUNC_NUM_QUAD, }, { .spiclk_out = FSPI3CLK_OUT_IDX, .spiclk_in = FSPI3CLK_IN_IDX, diff --git a/components/esp_hal_gpspi/esp32p4/include/soc/spi_pins.h b/components/esp_hal_gpspi/esp32p4/include/soc/spi_pins.h index 416ad7cf20..1404d7cfdc 100644 --- a/components/esp_hal_gpspi/esp32p4/include/soc/spi_pins.h +++ b/components/esp_hal_gpspi/esp32p4/include/soc/spi_pins.h @@ -24,7 +24,7 @@ #define MSPI_IOMUX_PIN_NUM_DQS GPIO_NUM_INVALID // Normal IOMUX pins -#define SPI2_FUNC_NUM 3 +#define SPI2_FUNC_NUM_QUAD 3 #define SPI2_IOMUX_PIN_NUM_HD 6 #define SPI2_IOMUX_PIN_NUM_CS 7 #define SPI2_IOMUX_PIN_NUM_MOSI 8 diff --git a/components/esp_hal_gpspi/esp32p4/spi_periph.c b/components/esp_hal_gpspi/esp32p4/spi_periph.c index 4afb9842bd..a577821f6e 100644 --- a/components/esp_hal_gpspi/esp32p4/spi_periph.c +++ b/components/esp_hal_gpspi/esp32p4/spi_periph.c @@ -43,7 +43,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .irq = ETS_SPI2_INTR_SOURCE, .irq_dma = -1, .hw = &GPSPI2, - .func = SPI2_FUNC_NUM, + .func = SPI2_FUNC_NUM_QUAD, }, { .spiclk_out = SPI3_CK_PAD_OUT_IDX, .spiclk_in = SPI3_CK_PAD_IN_IDX, diff --git a/components/esp_hal_gpspi/esp32s2/include/soc/spi_pins.h b/components/esp_hal_gpspi/esp32s2/include/soc/spi_pins.h index 65e1ee9d0b..f36327561d 100644 --- a/components/esp_hal_gpspi/esp32s2/include/soc/spi_pins.h +++ b/components/esp_hal_gpspi/esp32s2/include/soc/spi_pins.h @@ -23,8 +23,8 @@ // There are 2 sets of GPIO pins which could be routed to FSPICS0, FSPICLK, FSPID, FSPIQ, FSPIHD, FSPIWP. // However, there is only one set of GPIO pins which could be routed to FSPIIO4, FSPIIO5, FSPIIO6, FSPIIO7. -// As default (when we are not going to use Octal SPI), we make use of SPI2_FUNC_NUM to route one of the 2 sets of GPIO pins to FSPICS0 ~ FSPIWP as follows. -#define SPI2_FUNC_NUM 4 +// As default (when we are not going to use Octal SPI), we make use of SPI2_FUNC_NUM_QUAD to route one of the 2 sets of GPIO pins to FSPICS0 ~ FSPIWP as follows. +#define SPI2_FUNC_NUM_QUAD 4 #define SPI2_IOMUX_PIN_NUM_HD 9 #define SPI2_IOMUX_PIN_NUM_CS 10 #define SPI2_IOMUX_PIN_NUM_MOSI 11 diff --git a/components/esp_hal_gpspi/esp32s2/spi_periph.c b/components/esp_hal_gpspi/esp32s2/spi_periph.c index 61a853123f..ca894eb856 100644 --- a/components/esp_hal_gpspi/esp32s2/spi_periph.c +++ b/components/esp_hal_gpspi/esp32s2/spi_periph.c @@ -65,7 +65,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .irq = ETS_SPI2_INTR_SOURCE, .irq_dma = ETS_SPI2_DMA_INTR_SOURCE, .hw = &GPSPI2, - .func = SPI2_FUNC_NUM, + .func = SPI2_FUNC_NUM_QUAD, }, { .spiclk_out = SPI3_CLK_OUT_MUX_IDX, .spiclk_in = SPI3_CLK_IN_IDX, diff --git a/components/esp_hal_gpspi/esp32s3/include/soc/spi_pins.h b/components/esp_hal_gpspi/esp32s3/include/soc/spi_pins.h index 48b9fdf1dd..fd0e279b63 100644 --- a/components/esp_hal_gpspi/esp32s3/include/soc/spi_pins.h +++ b/components/esp_hal_gpspi/esp32s3/include/soc/spi_pins.h @@ -23,8 +23,8 @@ // There are 2 sets of GPIO pins which could be routed to FSPICS0, FSPICLK, FSPID, FSPIQ, FSPIHD, FSPIWP. // However, there is only one set of GPIO pins which could be routed to FSPIIO4, FSPIIO5, FSPIIO6, FSPIIO7. -// As default (when we are not going to use Octal SPI), we make use of SPI2_FUNC_NUM to route one of the 2 sets of GPIO pins to FSPICS0 ~ FSPIWP as follows. -#define SPI2_FUNC_NUM 4 +// As default (when we are not going to use Octal SPI), we make use of SPI2_FUNC_NUM_QUAD to route one of the 2 sets of GPIO pins to FSPICS0 ~ FSPIWP as follows. +#define SPI2_FUNC_NUM_QUAD 4 #define SPI2_IOMUX_PIN_NUM_HD 9 #define SPI2_IOMUX_PIN_NUM_CS 10 #define SPI2_IOMUX_PIN_NUM_MOSI 11 diff --git a/components/esp_hal_gpspi/esp32s3/spi_periph.c b/components/esp_hal_gpspi/esp32s3/spi_periph.c index 59f671159d..fcf1facacc 100644 --- a/components/esp_hal_gpspi/esp32s3/spi_periph.c +++ b/components/esp_hal_gpspi/esp32s3/spi_periph.c @@ -65,7 +65,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .irq = ETS_SPI2_INTR_SOURCE, .irq_dma = -1, .hw = &GPSPI2, - .func = SPI2_FUNC_NUM, + .func = SPI2_FUNC_NUM_QUAD, }, { .spiclk_out = SPI3_CLK_OUT_IDX, .spiclk_in = SPI3_CLK_IN_IDX, diff --git a/components/esp_hal_gpspi/esp32s31/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32s31/include/hal/spi_ll.h new file mode 100644 index 0000000000..8b75c3f048 --- /dev/null +++ b/components/esp_hal_gpspi/esp32s31/include/hal/spi_ll.h @@ -0,0 +1,1381 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The LL layer is not public api, don't use in application code. + * See readme.md in esp_hal_gpspi/readme.md + ******************************************************************************/ + +#pragma once + +#include //for abs() +#include +#include "hal/config.h" +#include "esp_types.h" +#include "soc/spi_reg.h" +#include "soc/spi_struct.h" +#include "hal/assert.h" +#include "hal/misc.h" +#include "hal/spi_types.h" +#include "soc/hp_sys_clkrst_struct.h" +#include "soc/hp_sys_clkrst_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPI_LL_GET_HW(ID) ((ID)==SPI2_HOST ? &GPSPI2 : (ID)==SPI3_HOST ? &GPSPI3 : NULL) +/// Interrupt not used. Don't use in app. +#define SPI_LL_UNUSED_INT_MASK (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA) +/// These 2 masks together will set SPI transaction to one line mode +#define SPI_LL_ONE_LINE_CTRL_MASK (SPI_FREAD_QUAD | SPI_FREAD_DUAL | SPI_FCMD_QUAD | SPI_FCMD_DUAL | SPI_FADDR_QUAD | SPI_FADDR_DUAL) +#define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_QUAD | SPI_FWRITE_DUAL) +/// Swap the bit order to its correct place to send +#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len)) + +#define SPI_LL_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) +#define SPI_LL_DMA_MAX_BIT_LEN SPI_MS_DATA_BITLEN +#define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words +#define SPI_LL_TX_MINI_EXTRA_BITS 1 //Minimum length of TX non byte aligned data in bits +#define SPI_LL_RX_MINI_EXTRA_BITS 1 //Minimum length of RX non byte aligned data in bits +#define SPI_LL_MAX_PRE_DIV_NUM (SPI_CLKDIV_PRE + 1) +#define SPI_LL_SRC_PRE_DIV_MAX (HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM + 1) //source pre divider max before peripheral +#define SPI_LL_PERIPH_CLK_DIV_MAX ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider +#define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized +#define SPI_LL_PERIPH_BITWIDTH(host) ((host == 2) ? 4 : 8) // Supported line mode: SPI3: 1, 2, 4, SPI1/2: 1, 2, 4, 8 + +/** + * The data structure holding calculated clock configuration. Since the + * calculation needs long time, it should be calculated during initialization and + * stored somewhere to be quickly used. + */ +typedef uint32_t spi_ll_clock_val_t; +typedef spi_dev_t spi_dma_dev_t; + +// Type definition of all supported interrupts +typedef enum { + SPI_LL_INTR_TRANS_DONE = BIT(0), ///< A transaction has done + SPI_LL_INTR_IN_FULL = BIT(4), ///< DMA in_full error happened + SPI_LL_INTR_OUT_EMPTY = BIT(5), ///< DMA out_empty error happened + SPI_LL_INTR_RDBUF = BIT(6), ///< Has received RDBUF command. Only available in slave HD. + SPI_LL_INTR_WRBUF = BIT(7), ///< Has received WRBUF command. Only available in slave HD. + SPI_LL_INTR_RDDMA = BIT(8), ///< Has received RDDMA command. Only available in slave HD. + SPI_LL_INTR_WRDMA = BIT(9), ///< Has received WRDMA command. Only available in slave HD. + SPI_LL_INTR_CMD7 = BIT(10), ///< Has received CMD7 command. Only available in slave HD. + SPI_LL_INTR_CMD8 = BIT(11), ///< Has received CMD8 command. Only available in slave HD. + SPI_LL_INTR_CMD9 = BIT(12), ///< Has received CMD9 command. Only available in slave HD. + SPI_LL_INTR_CMDA = BIT(13), ///< Has received CMDA command. Only available in slave HD. + SPI_LL_INTR_SEG_DONE = BIT(14), +} spi_ll_intr_t; + +// Flags for conditions under which the transaction length should be recorded +typedef enum { + SPI_LL_TRANS_LEN_COND_WRBUF = BIT(0), ///< WRBUF length will be recorded + SPI_LL_TRANS_LEN_COND_RDBUF = BIT(1), ///< RDBUF length will be recorded + SPI_LL_TRANS_LEN_COND_WRDMA = BIT(2), ///< WRDMA length will be recorded + SPI_LL_TRANS_LEN_COND_RDDMA = BIT(3), ///< RDDMA length will be recorded +} spi_ll_trans_len_cond_t; + +// SPI base command +typedef enum { + /* Slave HD Only */ + SPI_LL_BASE_CMD_HD_WRBUF = 0x01, + SPI_LL_BASE_CMD_HD_RDBUF = 0x02, + SPI_LL_BASE_CMD_HD_WRDMA = 0x03, + SPI_LL_BASE_CMD_HD_RDDMA = 0x04, + SPI_LL_BASE_CMD_HD_SEG_END = 0x05, + SPI_LL_BASE_CMD_HD_EN_QPI = 0x06, + SPI_LL_BASE_CMD_HD_WR_END = 0x07, + SPI_LL_BASE_CMD_HD_INT0 = 0x08, + SPI_LL_BASE_CMD_HD_INT1 = 0x09, + SPI_LL_BASE_CMD_HD_INT2 = 0x0A, +} spi_ll_base_command_t; +/*------------------------------------------------------------------------------ + * Control + *----------------------------------------------------------------------------*/ + +/** + * Enable peripheral register clock + * + * @param host_id Peripheral index number, see `spi_host_device_t` + * @param enable Enable/Disable + */ +static inline void _spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +{ + switch (host_id) { + case SPI2_HOST: + HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_sys_clk_en = enable; + HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_apb_clk_en = enable; + break; + case SPI3_HOST: + HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_sys_clk_en = enable; + HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_apb_clk_en = enable; + break; + default: HAL_ASSERT(false); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define spi_ll_enable_bus_clock(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + _spi_ll_enable_bus_clock(__VA_ARGS__); \ + } while(0) + +/** + * Reset whole peripheral register to init value defined by HW design + * + * @param host_id Peripheral index number, see `spi_host_device_t` + */ +static inline void spi_ll_reset_register(spi_host_device_t host_id) +{ + switch (host_id) { + case SPI2_HOST: + HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_rst_en = 1; + HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_rst_en = 0; + break; + case SPI3_HOST: + HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_rst_en = 1; + HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_rst_en = 0; + break; + default: HAL_ASSERT(false); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define spi_ll_reset_register(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + spi_ll_reset_register(__VA_ARGS__); \ + } while(0) + +/** + * Enable functional output clock within peripheral + * + * @param host_id Peripheral index number, see `spi_host_device_t` + * @param enable Enable/Disable + */ +static inline void _spi_ll_enable_clock(spi_host_device_t host_id, bool enable) +{ + switch (host_id) { + case SPI2_HOST: + HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_hs_clk_en = enable; + HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_mst_clk_en = enable; + break; + case SPI3_HOST: + HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_hs_clk_en = enable; + HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_mst_clk_en = enable; + break; + default: HAL_ASSERT(false); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define spi_ll_enable_clock(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + _spi_ll_enable_clock(__VA_ARGS__); \ + } while(0) + +/** + * Select SPI peripheral clock source (master). + * + * @param hw Beginning address of the peripheral registers. + * @param clk_source clock source to select, see valid sources in type `spi_clock_source_t` + */ +__attribute__((always_inline)) +static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source) +{ + uint32_t clk_id = 0; + switch (clk_source) { + case SPI_CLK_SRC_BBPLL: + clk_id = 2; + break; + case SPI_CLK_SRC_RC_FAST: + clk_id = 1; + break; + case SPI_CLK_SRC_XTAL: + clk_id = 0; + break; + default: + HAL_ASSERT(false); + } + + if (hw == &GPSPI2) { + HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_clk_src_sel = clk_id; + } else if (hw == &GPSPI3) { + HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_clk_src_sel = clk_id; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define spi_ll_set_clk_source(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + spi_ll_set_clk_source(__VA_ARGS__); \ + } while(0) + +/** + * Config clock source integrate pre_div before it enter GPSPI peripheral + * + * @note 1. For timing turning(e.g. input_delay) feature available, should be (mst_div >= 2) + * 2. From peripheral limitation: (sour_freq/hs_div <= 160M) and (sour_freq/hs_div/mst_div <= 80M) + * + * @param hw Beginning address of the peripheral registers. + * @param hs_div Timing turning clock divider: (hs_clk_o = sour_freq/hs_div) + * @param mst_div Functional output clock divider: (mst_clk_o = sour_freq/hs_div/mst_div) + */ +__attribute__((always_inline)) +static inline void spi_ll_clk_source_pre_div(spi_dev_t *hw, uint8_t hs_div, uint8_t mst_div) +{ + if (hw == &GPSPI2) { + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.gpspi2_ctrl0, reg_gpspi2_hs_clk_div_num, hs_div - 1); + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.gpspi2_ctrl0, reg_gpspi2_mst_clk_div_num, mst_div - 1); + } else if (hw == &GPSPI3) { + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.gpspi3_ctrl0, reg_gpspi3_hs_clk_div_num, hs_div - 1); + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.gpspi3_ctrl0, reg_gpspi3_mst_clk_div_num, mst_div - 1); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define spi_ll_clk_source_pre_div(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + spi_ll_clk_source_pre_div(__VA_ARGS__); \ + } while(0) + +/** + * Initialize SPI peripheral (master). + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_master_init(spi_dev_t *hw) +{ + //Reset timing + hw->user1.cs_setup_time = 0; + hw->user1.cs_hold_time = 0; + + //use all 64 bytes of the buffer + hw->user.usr_miso_highpart = 0; + hw->user.usr_mosi_highpart = 0; + + //Disable unneeded ints + hw->slave.val = 0; + hw->user.val = 0; + + //Disable unused error_end condition + hw->user1.mst_wfull_err_end_en = 0; + hw->user2.mst_rempty_err_end_en = 0; + + hw->dma_conf.val = 0; + hw->dma_conf.slv_tx_seg_trans_clr_en = 1; + hw->dma_conf.slv_rx_seg_trans_clr_en = 1; + hw->dma_conf.dma_slv_seg_trans_en = 0; +} + +/** + * Initialize SPI peripheral (slave). + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_slave_init(spi_dev_t *hw) +{ + //Configure slave + hw->clock.val = 0; + hw->user.val = 0; + hw->ctrl.val = 0; + hw->user.doutdin = 1; //we only support full duplex + hw->user.sio = 0; + hw->slave.slave_mode = 1; + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; + //use all 64 bytes of the buffer + hw->user.usr_miso_highpart = 0; + hw->user.usr_mosi_highpart = 0; + + // Configure DMA In-Link to not be terminated when transaction bit counter exceeds + hw->dma_conf.rx_eof_en = 0; + hw->dma_conf.dma_slv_seg_trans_en = 0; + + //Disable unneeded ints + hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK; +} + +/** + * Initialize SPI peripheral (slave half duplex mode) + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_slave_hd_init(spi_dev_t *hw) +{ + hw->clock.val = 0; + hw->user.val = 0; + hw->ctrl.val = 0; + hw->user.doutdin = 0; + hw->user.sio = 0; + + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; + hw->slave.slave_mode = 1; +} + +/** + * Check whether user-defined transaction is done. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if transaction is done, otherwise false. + */ +static inline bool spi_ll_usr_is_done(spi_dev_t *hw) +{ + return hw->dma_int_raw.trans_done_int_raw; +} + +/** + * Apply the register configurations and wait until it's done + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_apply_config(spi_dev_t *hw) +{ + hw->cmd.update = 1; + while (hw->cmd.update); //waiting config applied +} + +/** + * Trigger start of user-defined transaction. + * The synchronization between two clock domains is required in ESP32S31 + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_user_start(spi_dev_t *hw) +{ + hw->cmd.usr = 1; +} + +/** + * Get current running command bit-mask. (Preview) + * + * @param hw Beginning address of the peripheral registers. + * + * @return Bitmask of running command, see ``SPI_CMD_REG``. 0 if no in-flight command. + */ +static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) +{ + return hw->cmd.usr; +} + +/** + * Reset the slave peripheral before next transaction. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_slave_reset(spi_dev_t *hw) +{ + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; +} + +/** + * Reset SPI CPU TX FIFO + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw) +{ + hw->dma_conf.buf_afifo_rst = 1; + hw->dma_conf.buf_afifo_rst = 0; +} + +/** + * Reset SPI CPU RX FIFO + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_cpu_rx_fifo_reset(spi_dev_t *hw) +{ + hw->dma_conf.rx_afifo_rst = 1; + hw->dma_conf.rx_afifo_rst = 0; +} + +/** + * Reset SPI DMA TX FIFO + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_dma_tx_fifo_reset(spi_dev_t *hw) +{ + hw->dma_conf.dma_afifo_rst = 1; + hw->dma_conf.dma_afifo_rst = 0; +} + +/** + * Reset SPI DMA RX FIFO + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw) +{ + hw->dma_conf.rx_afifo_rst = 1; + hw->dma_conf.rx_afifo_rst = 0; +} + +/** + * Clear in fifo full error + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) +{ + hw->dma_int_clr.dma_infifo_full_err_int_clr = 1; +} + +/** + * Clear out fifo empty error + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) +{ + hw->dma_int_clr.dma_outfifo_empty_err_int_clr = 1; +} + +/*------------------------------------------------------------------------------ + * DMA + *----------------------------------------------------------------------------*/ +/** + * Enable/Disable RX DMA (Peripherals->DMA->RAM) + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: enable; 2: disable + */ +static inline void spi_ll_dma_rx_enable(spi_dev_t *hw, bool enable) +{ + hw->dma_conf.dma_rx_ena = enable; +} + +/** + * Enable/Disable TX DMA (RAM->DMA->Peripherals) + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: enable; 2: disable + */ +static inline void spi_ll_dma_tx_enable(spi_dev_t *hw, bool enable) +{ + hw->dma_conf.dma_tx_ena = enable; +} + +/** + * Configuration of RX DMA EOF interrupt generation way + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + */ +static inline void spi_ll_dma_set_rx_eof_generation(spi_dev_t *hw, bool enable) +{ + hw->dma_conf.rx_eof_en = enable; +} + +/*------------------------------------------------------------------------------ + * Buffer + *----------------------------------------------------------------------------*/ +/** + * Write to SPI hardware data buffer. + * + * @param hw Beginning address of the peripheral registers. + * @param buffer_to_send Address of the data to be written to the hardware data buffer. + * @param bitlen Length to write, in bits. + */ +static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen) +{ + for (int x = 0; x < bitlen; x += 32) { + //Use memcpy to get around alignment issues for txdata + uint32_t word; + memcpy(&word, &buffer_to_send[x / 8], 4); + hw->data_buf[(x / 32)].buf = word; + } +} + +/** + * Write to SPI hardware data buffer by buffer ID (address) + * + * @param hw Beginning address of the peripheral registers + * @param byte_id Start ID (address) of the hardware buffer to be written + * @param data Address of the data to be written to the hardware data buffer. + * @param len Length to write, in bytes. + */ +static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *data, int len) +{ + HAL_ASSERT(byte_id + len <= 64); + HAL_ASSERT(len > 0); + HAL_ASSERT(byte_id >= 0); + + while (len > 0) { + uint32_t word; + int offset = byte_id % 4; + int copy_len = 4 - offset; + if (copy_len > len) { + copy_len = len; + } + + //read-modify-write + if (copy_len != 4) { + word = hw->data_buf[byte_id / 4].buf; //read + } + memcpy(((uint8_t *)&word) + offset, data, copy_len); //modify + hw->data_buf[byte_id / 4].buf = word; //write + + data += copy_len; + byte_id += copy_len; + len -= copy_len; + } +} + +/** + * Read from SPI hardware data buffer. + * + * @param hw Beginning address of the peripheral registers. + * @param buffer_to_rcv Address of a buffer to read data from hardware data buffer + * @param bitlen Length to read, in bits. + */ +static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen) +{ + for (int x = 0; x < bitlen; x += 32) { + //Do a memcpy to get around possible alignment issues in rx_buffer + uint32_t word = hw->data_buf[x / 32].buf; + int len = bitlen - x; + if (len > 32) { + len = 32; + } + memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8); + } +} + +/** + * Read from SPI hardware data buffer by buffer ID (address) + * + * @param hw Beginning address of the peripheral registers + * @param byte_id Start ID (address) of the hardware buffer to be read + * @param data Address of a buffer to read data from hardware data buffer + * @param len Length to read, in bytes. + */ +static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *out_data, int len) +{ + while (len > 0) { + uint32_t word = hw->data_buf[byte_id / 4].buf; + int offset = byte_id % 4; + int copy_len = 4 - offset; + if (copy_len > len) { + copy_len = len; + } + + memcpy(out_data, ((uint8_t *)&word) + offset, copy_len); + byte_id += copy_len; + out_data += copy_len; + len -= copy_len; + } +} + +/*------------------------------------------------------------------------------ + * Configs: mode + *----------------------------------------------------------------------------*/ +/** + * Enable/disable the postive-cs feature. + * + * @param hw Beginning address of the peripheral registers. + * @param cs One of the CS (0-2) to enable/disable the feature. + * @param pos_cs True to enable the feature, otherwise disable (default). + */ +static inline void spi_ll_master_set_pos_cs(spi_dev_t *hw, int cs, uint32_t pos_cs) +{ + if (pos_cs) { + hw->misc.master_cs_pol |= (1 << cs); + } else { + hw->misc.master_cs_pol &= ~(1 << cs); + } +} + +/** + * Enable/disable the LSBFIRST feature for TX data. + * + * @param hw Beginning address of the peripheral registers. + * @param lsbfirst True if LSB of TX data to be sent first, otherwise MSB is sent first (default). + */ +static inline void spi_ll_set_tx_lsbfirst(spi_dev_t *hw, bool lsbfirst) +{ + hw->ctrl.wr_bit_order = lsbfirst; +} + +/** + * Enable/disable the LSBFIRST feature for RX data. + * + * @param hw Beginning address of the peripheral registers. + * @param lsbfirst True if first bit received as LSB, otherwise as MSB (default). + */ +static inline void spi_ll_set_rx_lsbfirst(spi_dev_t *hw, bool lsbfirst) +{ + hw->ctrl.rd_bit_order = lsbfirst; +} + +/** + * Set SPI mode for the peripheral as master. + * + * @param hw Beginning address of the peripheral registers. + * @param mode SPI mode to work at, 0-3. + */ +static inline void spi_ll_master_set_mode(spi_dev_t *hw, uint8_t mode) +{ + //Configure polarity + if (mode == 0) { + hw->misc.ck_idle_edge = 0; + hw->user.ck_out_edge = 0; + } else if (mode == 1) { + hw->misc.ck_idle_edge = 0; + hw->user.ck_out_edge = 1; + } else if (mode == 2) { + hw->misc.ck_idle_edge = 1; + hw->user.ck_out_edge = 1; + } else if (mode == 3) { + hw->misc.ck_idle_edge = 1; + hw->user.ck_out_edge = 0; + } +} + +/** + * Set SPI mode for the peripheral as slave. + * + * @param hw Beginning address of the peripheral registers. + * @param mode SPI mode to work at, 0-3. + */ +static inline void spi_ll_slave_set_mode(spi_dev_t *hw, const int mode, bool dma_used) +{ + if (mode == 0) { + hw->misc.ck_idle_edge = 0; + hw->user.rsck_i_edge = 0; + hw->user.tsck_i_edge = 0; + hw->slave.clk_mode_13 = 0; + } else if (mode == 1) { + hw->misc.ck_idle_edge = 0; + hw->user.rsck_i_edge = 1; + hw->user.tsck_i_edge = 1; + hw->slave.clk_mode_13 = 1; + } else if (mode == 2) { + hw->misc.ck_idle_edge = 1; + hw->user.rsck_i_edge = 1; + hw->user.tsck_i_edge = 1; + hw->slave.clk_mode_13 = 0; + } else if (mode == 3) { + hw->misc.ck_idle_edge = 1; + hw->user.rsck_i_edge = 0; + hw->user.tsck_i_edge = 0; + hw->slave.clk_mode_13 = 1; + } + hw->slave.rsck_data_out = 0; +} + +/** + * Set SPI to work in full duplex or half duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * @param half_duplex True to work in half duplex mode, otherwise in full duplex mode. + */ +static inline void spi_ll_set_half_duplex(spi_dev_t *hw, bool half_duplex) +{ + hw->user.doutdin = !half_duplex; +} + +/** + * Set SPI to work in SIO mode or not. + * + * SIO is a mode which MOSI and MISO share a line. The device MUST work in half-duplexmode. + * + * @param hw Beginning address of the peripheral registers. + * @param sio_mode True to work in SIO mode, otherwise false. + */ +static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode) +{ + hw->user.sio = sio_mode; +} + +/** + * Configure the SPI transaction line mode for the master to use. + * + * @param hw Beginning address of the peripheral registers. + * @param line_mode SPI transaction line mode to use, see ``spi_line_mode_t``. + */ +static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t line_mode) +{ + hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK; + hw->user.val &= ~SPI_LL_ONE_LINE_USER_MASK; + hw->ctrl.fcmd_dual = (line_mode.cmd_lines == 2); + hw->ctrl.fcmd_quad = (line_mode.cmd_lines == 4); + hw->ctrl.fcmd_oct = (line_mode.cmd_lines == 8); + hw->ctrl.faddr_dual = (line_mode.addr_lines == 2); + hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); + hw->ctrl.faddr_oct = (line_mode.addr_lines == 8); + hw->ctrl.fread_dual = (line_mode.data_lines == 2); + hw->user.fwrite_dual = (line_mode.data_lines == 2); + hw->ctrl.fread_quad = (line_mode.data_lines == 4); + hw->user.fwrite_quad = (line_mode.data_lines == 4); + hw->ctrl.fread_oct = (line_mode.data_lines == 8); + hw->user.fwrite_oct = (line_mode.data_lines == 8); +} + +/** + * Set the SPI slave to work in segment transaction mode + * + * @param hw Beginning address of the peripheral registers. + * @param seg_trans True to work in seg mode, otherwise false. + */ +static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans) +{ + hw->dma_conf.dma_slv_seg_trans_en = seg_trans; +} + +/** + * Select one of the CS to use in current transaction. + * + * @param hw Beginning address of the peripheral registers. + * @param cs_id The cs to use, 0-2, otherwise none of them is used. + */ +static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id) +{ + hw->misc.cs0_dis = (cs_id == 0) ? 0 : 1; + hw->misc.cs1_dis = (cs_id == 1) ? 0 : 1; + hw->misc.cs2_dis = (cs_id == 2) ? 0 : 1; + hw->misc.cs3_dis = (cs_id == 3) ? 0 : 1; + hw->misc.cs4_dis = (cs_id == 4) ? 0 : 1; + hw->misc.cs5_dis = (cs_id == 5) ? 0 : 1; +} + +/** + * Keep Chip Select activated after the current transaction. + * + * @param hw Beginning address of the peripheral registers. + * @param keep_active if 0 don't keep CS activated, else keep CS activated + */ +static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active) +{ + hw->misc.cs_keep_active = (keep_active != 0) ? 1 : 0; +} + +/*------------------------------------------------------------------------------ + * Configs: parameters + *----------------------------------------------------------------------------*/ +/** + * Set the standard clock mode for master. + * This config take effect only when SPI_CLK (pre-div before periph) div >=2 + * + * @param hw Beginning address of the peripheral registers. + * @param enable_std True for std timing, False for half cycle delay sampling. + */ +static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_point_t sample_point) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + hw->clock.clk_edge_sel = (sample_point == SPI_SAMPLING_POINT_PHASE_1); +#endif +} + +/** + * Get if standard clock mode is supported. + */ +static inline bool spi_ll_master_is_rx_std_sample_supported(void) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + return true; +#else + return false; +#endif +} + +/** + * Set the clock for master by stored value. + * + * @param hw Beginning address of the peripheral registers. + * @param val Stored clock configuration calculated before (by ``spi_ll_cal_clock``). + */ +static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_clock_val_t *val) +{ + hw->clock.val = *(uint32_t *)val; +} + +/** + * Get the frequency of given dividers. Don't use in app. + * + * @param fapb APB clock of the system. + * @param pre Pre divider. + * @param n Main divider. + * + * @return Frequency of given dividers. + */ +__attribute__((always_inline)) +static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n) +{ + return (fapb / (pre * n)); +} + +/** + * Calculate the nearest frequency available for master. + * + * @param fapb APB clock of the system. + * @param hz Frequency desired. + * @param duty_cycle Duty cycle desired. + * @param out_reg Output address to store the calculated clock configurations for the return frequency. + * + * @return Actual (nearest) frequency. + */ +__attribute__((always_inline)) +static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ll_clock_val_t *out_reg) +{ + typeof(GPSPI2.clock) reg = {.val = 0}; + int eff_clk; + + //In hw, n, h and l are 1-64, pre is 1-8K. Value written to register is one lower than used value. + if (hz > ((fapb / 4) * 3)) { + //Using Fapb directly will give us the best result here. + reg.clkcnt_l = 0; + reg.clkcnt_h = 0; + reg.clkcnt_n = 0; + reg.clkdiv_pre = 0; + reg.clk_equ_sysclk = 1; + eff_clk = fapb; + } else { + //For best duty cycle resolution, we want n to be as close to 32 as possible, but + //we also need a pre/n combo that gets us as close as possible to the intended freq. + //To do this, we bruteforce n and calculate the best pre to go along with that. + //If there's a choice between pre/n combos that give the same result, use the one + //with the higher n. + int pre, n, h, l; + int bestn = -1; + int bestpre = -1; + int besterr = 0; + int errval; + for (n = 2; n <= 64; n++) { //Start at 2: we need to be able to set h/l so we have at least one high and one low pulse. + //Effectively, this does pre=round((fapb/n)/hz). + pre = ((fapb / n) + (hz / 2)) / hz; + if (pre <= 0) { + pre = 1; + } + if (pre > SPI_LL_MAX_PRE_DIV_NUM) { + pre = SPI_LL_MAX_PRE_DIV_NUM; + } + errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); + if (bestn == -1 || errval <= besterr) { + besterr = errval; + bestn = n; + bestpre = pre; + } + } + + n = bestn; + pre = bestpre; + l = n; + //This effectively does round((duty_cycle*n)/256) + h = (duty_cycle * n + 127) / 256; + if (h <= 0) { + h = 1; + } + + reg.clk_equ_sysclk = 0; + reg.clkcnt_n = n - 1; + reg.clkdiv_pre = pre - 1; + reg.clkcnt_h = h - 1; + reg.clkcnt_l = l - 1; + eff_clk = spi_ll_freq_for_pre_n(fapb, pre, n); + } + if (out_reg != NULL) { + *(uint32_t *)out_reg = reg.val; + } + return eff_clk; +} + +/** + * Calculate and set clock for SPI master according to desired parameters. + * + * This takes long, suggest to calculate the configuration during + * initialization by ``spi_ll_master_cal_clock`` and store the result, then + * configure the clock by stored value when used by + * ``spi_ll_msater_set_clock_by_reg``. + * + * @param hw Beginning address of the peripheral registers. + * @param fapb APB clock of the system. + * @param hz Frequency desired. + * @param duty_cycle Duty cycle desired. + * + * @return Actual frequency that is used. + */ +static inline int spi_ll_master_set_clock(spi_dev_t *hw, int fapb, int hz, int duty_cycle) +{ + spi_ll_clock_val_t reg_val; + int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val); + spi_ll_master_set_clock_by_reg(hw, ®_val); + return freq; +} + +/** + * Set the mosi delay after the output edge to the signal. (Preview) + * + * The delay mode/num is a Espressif conception, may change in the new chips. + * + * @param hw Beginning address of the peripheral registers. + * @param delay_mode Delay mode, see TRM. + * @param delay_num APB clocks to delay. + */ +static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int delay_num) +{ +} + +/** + * Determine and unify the default level of data line when bus idle + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_set_data_pin_idle_level(spi_dev_t *hw, bool level) +{ + hw->ctrl.d_pol = level; + hw->ctrl.q_pol = level; + hw->ctrl.wp_pol = level; + hw->ctrl.hold_pol = level; +} + +/** + * Set the miso delay applied to the input signal before the internal peripheral. (Preview) + * + * The delay mode/num is a Espressif conception, may change in the new chips. + * + * @param hw Beginning address of the peripheral registers. + * @param delay_mode Delay mode, see TRM. + * @param delay_num APB clocks to delay. + */ +static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int delay_num) +{ +} + +/** + * Set the delay of SPI clocks before the CS inactive edge after the last SPI clock. + * + * @param hw Beginning address of the peripheral registers. + * @param hold Delay of SPI clocks after the last clock, 0 to disable the hold phase. + */ +static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) +{ + hw->user1.cs_hold_time = hold; + hw->user.cs_hold = hold ? 1 : 0; +} + +/** + * Set the delay of SPI clocks before the first SPI clock after the CS active edge. + * + * Note ESP32S31 doesn't support to use this feature when command/address phases + * are used in full duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * @param setup Delay of SPI clocks after the CS active edge, 0 to disable the setup phase. + */ +static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup) +{ + hw->user1.cs_setup_time = setup - 1; + hw->user.cs_setup = setup ? 1 : 0; +} + +/*------------------------------------------------------------------------------ + * Configs: data + *----------------------------------------------------------------------------*/ +/** + * Set the output length (master). + * This should be called before master setting MISO(input) length + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen output length, in bits. + */ +static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen) +{ + if (bitlen > 0) { + hw->ms_dlen.ms_data_bitlen = bitlen - 1; + } +} + +/** + * Set the input length (master). + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen input length, in bits. + */ +static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen) +{ + if (bitlen > 0) { + hw->ms_dlen.ms_data_bitlen = bitlen - 1; + } +} + +/** + * Set the maximum input length (slave). + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Input length, in bits. + */ +static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen) +{ + //This is not used +} + +/** + * Set the maximum output length (slave). + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Output length, in bits. + */ +static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen) +{ + //This is not used +} + +/** + * Set the length of command phase. + * + * When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit + * command phases takes 4 cycles in 4-bit mode. + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Length of command phase, in bits. 0 to disable the command phase. + */ +static inline void spi_ll_set_command_bitlen(spi_dev_t *hw, int bitlen) +{ + hw->user2.usr_command_bitlen = bitlen - 1; + hw->user.usr_command = bitlen ? 1 : 0; +} + +/** + * Set the length of address phase. + * + * When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit + * address phases takes 4 cycles in 4-bit mode. + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Length of address phase, in bits. 0 to disable the address phase. + */ +static inline void spi_ll_set_addr_bitlen(spi_dev_t *hw, int bitlen) +{ + hw->user1.usr_addr_bitlen = bitlen - 1; + hw->user.usr_addr = bitlen ? 1 : 0; +} + +/** + * Set the address value in an intuitive way. + * + * The length and lsbfirst is required to shift and swap the address to the right place. + * + * @param hw Beginning address of the peripheral registers. + * @param address Address to set + * @param addrlen Length of the address phase + * @param lsbfirst Whether the LSB first feature is enabled. + */ +static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, uint32_t lsbfirst) +{ + if (lsbfirst) { + /* The output address start from the LSB of the highest byte, i.e. + * addr[24] -> addr[31] + * ... + * addr[0] -> addr[7] + * So swap the byte order to let the LSB sent first. + */ + addr = HAL_SWAP32(addr); + //otherwise only addr register is sent + hw->addr.val = addr; + } else { + // shift the address to MSB of addr register. + // output address will be sent from MSB to LSB of addr register + hw->addr.val = addr << (32 - addrlen); + } +} + +/** + * Set the command value in an intuitive way. + * + * The length and lsbfirst is required to shift and swap the command to the right place. + * + * @param hw Beginning command of the peripheral registers. + * @param command Command to set + * @param addrlen Length of the command phase + * @param lsbfirst Whether the LSB first feature is enabled. + */ +static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst) +{ + if (lsbfirst) { + // The output command start from bit0 to bit 15, kept as is. + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd); + } else { + /* Output command will be sent from bit 7 to 0 of command_value, and + * then bit 15 to 8 of the same register field. Shift and swap to send + * more straightly. + */ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen)); + } +} + +/** + * Set dummy clocks to output before RX phase (master), or clocks to skip + * before the data phase and after the address phase (slave). + * + * Note this phase is also used to compensate RX timing in half duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * @param dummy_n Dummy cycles used. 0 to disable the dummy phase. + */ +static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) +{ + hw->user.usr_dummy = dummy_n ? 1 : 0; + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + } +} + +/** + * Enable/disable the RX data phase. + * + * @param hw Beginning address of the peripheral registers. + * @param enable True if RX phase exist, otherwise false. + */ +static inline void spi_ll_enable_miso(spi_dev_t *hw, int enable) +{ + hw->user.usr_miso = enable; +} + +/** + * Enable/disable the TX data phase. + * + * @param hw Beginning address of the peripheral registers. + * @param enable True if TX phase exist, otherwise false. + */ +static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable) +{ + hw->user.usr_mosi = enable; +} + +/** + * Get the received bit length of the slave. + * + * @param hw Beginning address of the peripheral registers. + * + * @return Received bits of the slave. + */ +static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) +{ + return hw->slave1.slv_data_bitlen; +} + +/*------------------------------------------------------------------------------ + * Interrupts + *----------------------------------------------------------------------------*/ +//helper macros to generate code for each interrupts +#define FOR_EACH_ITEM(op, list) do { list(op) } while(0) +#define INTR_LIST(item) \ + item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done_int_ena, dma_int_raw.trans_done_int_raw, dma_int_clr.trans_done_int_clr, dma_int_set.trans_done_int_set) \ + item(SPI_LL_INTR_IN_FULL, dma_int_ena.dma_infifo_full_err_int_ena, dma_int_raw.dma_infifo_full_err_int_raw, dma_int_clr.dma_infifo_full_err_int_clr, dma_int_set.dma_infifo_full_err_int_set) \ + item(SPI_LL_INTR_OUT_EMPTY, dma_int_ena.dma_outfifo_empty_err_int_ena, dma_int_raw.dma_outfifo_empty_err_int_raw, dma_int_clr.dma_outfifo_empty_err_int_clr, dma_int_set.dma_outfifo_empty_err_int_set) \ + item(SPI_LL_INTR_RDBUF, dma_int_ena.slv_rd_buf_done_int_ena, dma_int_raw.slv_rd_buf_done_int_raw, dma_int_clr.slv_rd_buf_done_int_clr, dma_int_set.slv_rd_buf_done_int_set) \ + item(SPI_LL_INTR_WRBUF, dma_int_ena.slv_wr_buf_done_int_ena, dma_int_raw.slv_wr_buf_done_int_raw, dma_int_clr.slv_wr_buf_done_int_clr, dma_int_set.slv_wr_buf_done_int_set) \ + item(SPI_LL_INTR_RDDMA, dma_int_ena.slv_rd_dma_done_int_ena, dma_int_raw.slv_rd_dma_done_int_raw, dma_int_clr.slv_rd_dma_done_int_clr, dma_int_set.slv_rd_dma_done_int_set) \ + item(SPI_LL_INTR_WRDMA, dma_int_ena.slv_wr_dma_done_int_ena, dma_int_raw.slv_wr_dma_done_int_raw, dma_int_clr.slv_wr_dma_done_int_clr, dma_int_set.slv_wr_dma_done_int_set) \ + item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done_int_ena, dma_int_raw.dma_seg_trans_done_int_raw, dma_int_clr.dma_seg_trans_done_int_clr, dma_int_set.dma_seg_trans_done_int_set) \ + item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7_int_ena, dma_int_raw.slv_cmd7_int_raw, dma_int_clr.slv_cmd7_int_clr, dma_int_set.slv_cmd7_int_set) \ + item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8_int_ena, dma_int_raw.slv_cmd8_int_raw, dma_int_clr.slv_cmd8_int_clr, dma_int_set.slv_cmd8_int_set) \ + item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9_int_ena, dma_int_raw.slv_cmd9_int_raw, dma_int_clr.slv_cmd9_int_clr, dma_int_set.slv_cmd9_int_set) \ + item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda_int_ena, dma_int_raw.slv_cmda_int_raw, dma_int_clr.slv_cmda_int_clr, dma_int_set.slv_cmda_int_set) + +static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ +#define ENA_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 1; + FOR_EACH_ITEM(ENA_INTR, INTR_LIST); +#undef ENA_INTR +} + +static inline void spi_ll_disable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ +#define DIS_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 0; + FOR_EACH_ITEM(DIS_INTR, INTR_LIST); +#undef DIS_INTR +} + +static inline void spi_ll_set_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ +#define SET_INTR(intr_bit, _, __, ___, set_reg) if (intr_mask & (intr_bit)) hw->set_reg = 1; + FOR_EACH_ITEM(SET_INTR, INTR_LIST); +#undef SET_INTR +} + +static inline void spi_ll_clear_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ +#define CLR_INTR(intr_bit, _, __, clr_reg, ...) if (intr_mask & (intr_bit)) hw->clr_reg = 1; + FOR_EACH_ITEM(CLR_INTR, INTR_LIST); +#undef CLR_INTR +} + +static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ +#define GET_INTR(intr_bit, _, sta_reg, ...) if (intr_mask & (intr_bit) && hw->sta_reg) return true; + FOR_EACH_ITEM(GET_INTR, INTR_LIST); + return false; +#undef GET_INTR +} + +#undef FOR_EACH_ITEM +#undef INTR_LIST + +/** + * Disable the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_disable_int(spi_dev_t *hw) +{ + hw->dma_int_ena.trans_done_int_ena = 0; +} + +/** + * Clear the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_clear_int_stat(spi_dev_t *hw) +{ + hw->dma_int_clr.trans_done_int_clr = 1; +} + +/** + * Set the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_set_int_stat(spi_dev_t *hw) +{ + hw->dma_int_set.trans_done_int_set = 1; +} + +/** + * Enable the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_enable_int(spi_dev_t *hw) +{ + hw->dma_int_ena.trans_done_int_ena = 1; +} + +/*------------------------------------------------------------------------------ + * Slave HD + *----------------------------------------------------------------------------*/ +static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_cond_t cond_mask) +{ + hw->slave.slv_rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; + hw->slave.slv_wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; + hw->slave.slv_rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; + hw->slave.slv_wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; +} + +static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw) +{ + return hw->slave1.slv_data_bitlen / 8; +} + +static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) +{ + return hw->slave1.slv_last_addr; +} + +#undef SPI_LL_RST_MASK +#undef SPI_LL_UNUSED_INT_MASK + +/** + * Get the base spi command + * + * @param cmd_t Command value + */ +static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) +{ + uint8_t cmd_base = 0x00; + switch (cmd_t) { + case SPI_CMD_HD_WRBUF: + cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + break; + case SPI_CMD_HD_RDBUF: + cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + break; + case SPI_CMD_HD_WRDMA: + cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + break; + case SPI_CMD_HD_RDDMA: + cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + break; + case SPI_CMD_HD_SEG_END: + cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + break; + case SPI_CMD_HD_EN_QPI: + cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + break; + case SPI_CMD_HD_WR_END: + cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + break; + case SPI_CMD_HD_INT0: + cmd_base = SPI_LL_BASE_CMD_HD_INT0; + break; + case SPI_CMD_HD_INT1: + cmd_base = SPI_LL_BASE_CMD_HD_INT1; + break; + case SPI_CMD_HD_INT2: + cmd_base = SPI_LL_BASE_CMD_HD_INT2; + break; + default: + HAL_ASSERT(cmd_base); + } + return cmd_base; +} + +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + + if (line_mode.data_lines == 2) { + if (line_mode.addr_lines == 2) { + cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + } else { + cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + } + } else if (line_mode.data_lines == 4) { + if (line_mode.addr_lines == 4) { + cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + } else { + cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + } + } + if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + cmd_mod = 0x00; + } + + return cmd_base | cmd_mod; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + return 8; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_gpspi/esp32s31/include/soc/spi_pins.h b/components/esp_hal_gpspi/esp32s31/include/soc/spi_pins.h index 210b74b379..a5cc2c152e 100644 --- a/components/esp_hal_gpspi/esp32s31/include/soc/spi_pins.h +++ b/components/esp_hal_gpspi/esp32s31/include/soc/spi_pins.h @@ -1,16 +1,13 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -// TODO: to be checked IDF-14734 - -// MSPI IOMUX PINs +// MSPI IOMUX PINs Please check iomux_mspi_pin_struct/reg.h // On S31, SPI pins defined here are all wrong. these pins are individual pins, don't use normal GPIO pins anymore. -// Please check iomux_mspi_pin_struct/reg.h #define GPIO_NUM_INVALID -1 #define MSPI_IOMUX_PIN_NUM_CS1 GPIO_NUM_INVALID #define MSPI_IOMUX_PIN_NUM_HD GPIO_NUM_INVALID @@ -25,26 +22,34 @@ #define MSPI_IOMUX_PIN_NUM_D7 GPIO_NUM_INVALID #define MSPI_IOMUX_PIN_NUM_DQS GPIO_NUM_INVALID -// Normal IOMUX pins -#define SPI2_FUNC_NUM 3 -#define SPI2_IOMUX_PIN_NUM_HD 6 -#define SPI2_IOMUX_PIN_NUM_CS 7 -#define SPI2_IOMUX_PIN_NUM_MOSI 8 -#define SPI2_IOMUX_PIN_NUM_CLK 9 -#define SPI2_IOMUX_PIN_NUM_MISO 10 -#define SPI2_IOMUX_PIN_NUM_WP 11 +// GPSPI2 has two sets of Qaud IOMUX pins +#define SPI2_FUNC_NUM_QUAD 2 +#define SPI2_IOMUX_PIN_NUM_CLK 20 +#define SPI2_IOMUX_PIN_NUM_MOSI 21 +#define SPI2_IOMUX_PIN_NUM_MISO 22 +#define SPI2_IOMUX_PIN_NUM_CS 23 +#define SPI2_IOMUX_PIN_NUM_HD 24 +#define SPI2_IOMUX_PIN_NUM_WP 25 + +#define SPI2_IOMUX_PIN_2_NUM_CS 52 +#define SPI2_IOMUX_PIN_2_NUM_CLK 53 +#define SPI2_IOMUX_PIN_2_NUM_MOSI 54 +#define SPI2_IOMUX_PIN_2_NUM_MISO 55 +#define SPI2_IOMUX_PIN_2_NUM_HD 56 +#define SPI2_IOMUX_PIN_2_NUM_WP 57 // When using Octal SPI, we make use of SPI2_FUNC_NUM_OCT to route them as follows. -#define SPI2_FUNC_NUM_OCT 2 -#define SPI2_IOMUX_PIN_NUM_HD_OCT 32 -#define SPI2_IOMUX_PIN_NUM_CS_OCT 28 -#define SPI2_IOMUX_PIN_NUM_MOSI_OCT 29 -#define SPI2_IOMUX_PIN_NUM_CLK_OCT 30 -#define SPI2_IOMUX_PIN_NUM_MISO_OCT 31 -#define SPI2_IOMUX_PIN_NUM_WP_OCT 33 -#define SPI2_IOMUX_PIN_NUM_IO4_OCT 34 -#define SPI2_IOMUX_PIN_NUM_IO5_OCT 35 -#define SPI2_IOMUX_PIN_NUM_IO6_OCT 36 -#define SPI2_IOMUX_PIN_NUM_IO7_OCT 37 +#define SPI2_FUNC_NUM_OCT 0 +#define SPI2_IOMUX_PIN_NUM_HD_OCT 9 +#define SPI2_IOMUX_PIN_NUM_CS_OCT 10 +#define SPI2_IOMUX_PIN_NUM_MOSI_OCT 11 +#define SPI2_IOMUX_PIN_NUM_CLK_OCT 12 +#define SPI2_IOMUX_PIN_NUM_MISO_OCT 13 +#define SPI2_IOMUX_PIN_NUM_WP_OCT 14 +#define SPI2_IOMUX_PIN_NUM_IO4_OCT 15 +#define SPI2_IOMUX_PIN_NUM_IO5_OCT 16 +#define SPI2_IOMUX_PIN_NUM_IO6_OCT 17 +#define SPI2_IOMUX_PIN_NUM_IO7_OCT 18 +#define SPI2_IOMUX_PIN_NUM_DQS_OCT 19 //SPI3 have no iomux pins diff --git a/components/esp_hal_gpspi/esp32s31/spi_periph.c b/components/esp_hal_gpspi/esp32s31/spi_periph.c new file mode 100644 index 0000000000..7e36360e11 --- /dev/null +++ b/components/esp_hal_gpspi/esp32s31/spi_periph.c @@ -0,0 +1,125 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "soc/spi_periph.h" + +/* + Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { + { + // MSPI on S31 has dedicated iomux pins + }, { + .spiclk_out = SPI2_CK_PAD_OUT_IDX, + .spiclk_in = SPI2_CK_PAD_IN_IDX, + .spid_out = SPI2_D_PAD_OUT_IDX, + .spiq_out = SPI2_Q_PAD_OUT_IDX, + .spiwp_out = SPI2_WP_PAD_OUT_IDX, + .spihd_out = SPI2_HOLD_PAD_OUT_IDX, + .spid4_out = SPI2_IO4_PAD_OUT_IDX, + .spid5_out = SPI2_IO5_PAD_OUT_IDX, + .spid6_out = SPI2_IO6_PAD_OUT_IDX, + .spid7_out = SPI2_IO7_PAD_OUT_IDX, + .spid_in = SPI2_D_PAD_IN_IDX, + .spiq_in = SPI2_Q_PAD_IN_IDX, + .spiwp_in = SPI2_WP_PAD_IN_IDX, + .spihd_in = SPI2_HOLD_PAD_IN_IDX, + .spid4_in = SPI2_IO4_PAD_IN_IDX, + .spid5_in = SPI2_IO5_PAD_IN_IDX, + .spid6_in = SPI2_IO6_PAD_IN_IDX, + .spid7_in = SPI2_IO7_PAD_IN_IDX, + .spics_out = {SPI2_CS_PAD_OUT_IDX, SPI2_CS1_PAD_OUT_IDX, SPI2_CS2_PAD_OUT_IDX, SPI2_CS3_PAD_OUT_IDX, SPI2_CS4_PAD_OUT_IDX, SPI2_CS5_PAD_OUT_IDX}, + .spics_in = SPI2_CS_PAD_IN_IDX, + .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK, + .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI, + .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO, + .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP, + .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD, + .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS, + .irq = ETS_SPI2_INTR_SOURCE, + .irq_dma = -1, + .hw = &GPSPI2, + .func = SPI2_FUNC_NUM_QUAD, + }, { + .spiclk_out = SPI3_CK_PAD_OUT_IDX, + .spiclk_in = SPI3_CK_PAD_IN_IDX, + .spid_out = SPI3_D_PAD_OUT_IDX, + .spiq_out = SPI3_QO_PAD_OUT_IDX, + .spiwp_out = SPI3_WP_PAD_OUT_IDX, + .spihd_out = SPI3_HOLD_PAD_OUT_IDX, + .spid_in = SPI3_D_PAD_IN_IDX, + .spiq_in = SPI3_Q_PAD_IN_IDX, + .spiwp_in = SPI3_WP_PAD_IN_IDX, + .spihd_in = SPI3_HOLD_PAD_IN_IDX, + .spics_out = {SPI3_CS_PAD_OUT_IDX, SPI3_CS1_PAD_OUT_IDX, SPI3_CS2_PAD_OUT_IDX}, + .spics_in = SPI3_CS_PAD_IN_IDX, + //SPI3 doesn't have iomux pins + .spiclk_iomux_pin = -1, + .spid_iomux_pin = -1, + .spiq_iomux_pin = -1, + .spiwp_iomux_pin = -1, + .spihd_iomux_pin = -1, + .spics0_iomux_pin = -1, + .irq = ETS_SPI3_INTR_SOURCE, + .irq_dma = -1, + .hw = &GPSPI3, + .func = -1, + } +}; + +#if SOC_PAU_SUPPORTED +/** + * Backup registers in Light sleep: (total cnt 29) + * + * cmd + * addr + * ctrl + * clock + * user + * user1 + * user2 + * ms_dlen + * misc + * dma_conf + * dma_int_ena + * data_buf[0-15] // slave driver only + * slave + * slave1 + */ +#define SPI_RETENTION_REGS_CNT 29 +static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0}; +#define SPI_REG_RETENTION_ENTRIES(num) { \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \ + REG_SPI_BASE(num), REG_SPI_BASE(num), \ + SPI_RETENTION_REGS_CNT, 0, 0, \ + spi_regs_map[0], spi_regs_map[1], \ + spi_regs_map[2], spi_regs_map[3]), \ + .owner = ENTRY(0) }, \ + /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \ + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \ + SPI_DMA_INT_SET_REG(num), \ + SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \ + UINT32_MAX, 1, 0), \ + .owner = ENTRY(0) }, \ +} + +static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2 +static const regdma_entries_config_t spi3_regs_retention[] = SPI_REG_RETENTION_ENTRIES(3); + +const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi + { + .module_id = SLEEP_RETENTION_MODULE_GPSPI2, + .entry_array = spi2_regs_retention, + .array_size = ARRAY_SIZE(spi2_regs_retention), + }, + { + .module_id = SLEEP_RETENTION_MODULE_GPSPI3, + .entry_array = spi3_regs_retention, + .array_size = ARRAY_SIZE(spi3_regs_retention), + }, +}; +#endif // SOC_PAU_SUPPORTED diff --git a/components/esp_lcd/test_apps/.build-test-rules.yml b/components/esp_lcd/test_apps/.build-test-rules.yml index cb9ec57a2f..e618bd6651 100644 --- a/components/esp_lcd/test_apps/.build-test-rules.yml +++ b/components/esp_lcd/test_apps/.build-test-rules.yml @@ -58,3 +58,4 @@ components/esp_lcd/test_apps/spi_lcd: - esp_driver_spi disable: - if: SOC_GPSPI_SUPPORTED != 1 + - if: CONFIG_NAME == "virt_flash_enc" and SOC_FLASH_ENC_SUPPORTED != 1 diff --git a/components/esp_lcd/test_apps/spi_lcd/README.md b/components/esp_lcd/test_apps/spi_lcd/README.md index 78b6ac489f..ac65d6cc65 100644 --- a/components/esp_lcd/test_apps/spi_lcd/README.md +++ b/components/esp_lcd/test_apps/spi_lcd/README.md @@ -1,4 +1,4 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | This test app is used to test LCDs with SPI interface. diff --git a/components/esp_lcd/test_apps/spi_lcd/pytest_spi_lcd.py b/components/esp_lcd/test_apps/spi_lcd/pytest_spi_lcd.py index 9b581018a9..5df66ea347 100644 --- a/components/esp_lcd/test_apps/spi_lcd/pytest_spi_lcd.py +++ b/components/esp_lcd/test_apps/spi_lcd/pytest_spi_lcd.py @@ -14,7 +14,6 @@ from pytest_embedded_idf.utils import idf_parametrize indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) -@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done') def test_spi_lcd(dut: Dut) -> None: dut.run_all_single_board_cases() @@ -28,7 +27,6 @@ def test_spi_lcd(dut: Dut) -> None: indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) -@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done') def test_spi_lcd_with_virt_flash_enc(dut: Dut) -> None: print(' - Erase flash') dut.serial.erase_flash() diff --git a/components/fatfs/test_apps/sdcard/README.md b/components/fatfs/test_apps/sdcard/README.md index 44f972bb17..245834f8d7 100644 --- a/components/fatfs/test_apps/sdcard/README.md +++ b/components/fatfs/test_apps/sdcard/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | This test app runs a few FATFS test cases in a FAT-formatted SD card. diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in index 5cc6fa23d8..6c8de0e8d8 100644 --- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in @@ -71,6 +71,10 @@ config SOC_SDM_SUPPORTED bool default y +config SOC_GPSPI_SUPPORTED + bool + default y + config SOC_LEDC_SUPPORTED bool default y @@ -443,6 +447,18 @@ config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 +config SOC_SPI_SUPPORT_SLEEP_RETENTION + bool + default y + +config SOC_SPI_SUPPORT_SLAVE_HD_VER2 + bool + default y + +config SOC_SPI_SUPPORT_OCT + bool + default y + config SOC_SPIRAM_XIP_SUPPORTED bool default y diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h index f15c451f87..06d5a0a81c 100644 --- a/components/soc/esp32s31/include/soc/soc_caps.h +++ b/components/soc/esp32s31/include/soc/soc_caps.h @@ -57,7 +57,7 @@ #define SOC_RMT_SUPPORTED 1 // #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32S31] IDF-14771 #define SOC_SDM_SUPPORTED 1 -// #define SOC_GPSPI_SUPPORTED 1 // TODO: [ESP32S31] IDF-14734 +#define SOC_GPSPI_SUPPORTED 1 #define SOC_LEDC_SUPPORTED 1 // #define SOC_ISP_SUPPORTED 1 // TODO: [ESP32S31] IDF-14769 // #define SOC_I2C_SUPPORTED 1 // TODO: [ESP32S31] IDF-14726 @@ -237,11 +237,11 @@ #define SOC_MMU_PER_EXT_MEM_TARGET (1) /*!< MMU is per physical external memory target (flash, psram) */ /*-------------------------- SPI CAPS ----------------------------------------*/ -// TODO: [ESP32S31] IDF-14734 -#define SOC_SPI_PERIPH_NUM 3 -#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) -#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 -#define SOC_SPI_MAX_BITWIDTH(host_id) ((host_id == 2) ? 4 : 8) // Supported line mode: SPI3: 1, 2, 4, SPI1/2: 1, 2, 4, 8 +#define SOC_SPI_PERIPH_NUM 3 +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 +#define SOC_SPI_SUPPORT_SLEEP_RETENTION 1 +#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 +#define SOC_SPI_SUPPORT_OCT 1 /*-------------------------- SPIRAM CAPS ----------------------------------------*/ #define SOC_SPIRAM_XIP_SUPPORTED 1 diff --git a/components/soc/esp32s31/register/soc/spi_reg.h b/components/soc/esp32s31/register/soc/spi_reg.h index 3c69edfc81..b295c56b47 100644 --- a/components/soc/esp32s31/register/soc/spi_reg.h +++ b/components/soc/esp32s31/register/soc/spi_reg.h @@ -5,15 +5,17 @@ */ #pragma once -#include "soc/soc.h" +#include "soc/reg_base.h" #ifdef __cplusplus extern "C" { #endif +#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_GPSPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 + /** SPI_CMD_REG register * Command control register */ -#define SPI_CMD_REG (DR_REG_SPI_BASE + 0x0) +#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) /** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0; * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. */ @@ -42,7 +44,7 @@ extern "C" { /** SPI_ADDR_REG register * Address value register */ -#define SPI_ADDR_REG (DR_REG_SPI_BASE + 0x4) +#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) /** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; * Address to slave. Can be configured in CONF state. */ @@ -54,7 +56,7 @@ extern "C" { /** SPI_CTRL_REG register * SPI control register */ -#define SPI_CTRL_REG (DR_REG_SPI_BASE + 0x8) +#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) /** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0; * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, * the FSPI bus signals are output. Can be configured in CONF state. @@ -187,7 +189,7 @@ extern "C" { /** SPI_CLOCK_REG register * SPI clock control register */ -#define SPI_CLOCK_REG (DR_REG_SPI_BASE + 0xc) +#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xc) /** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3; * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be * 0. Can be configured in CONF state. @@ -242,7 +244,7 @@ extern "C" { /** SPI_USER_REG register * SPI USER control register */ -#define SPI_USER_REG (DR_REG_SPI_BASE + 0x10) +#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) /** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0; * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be * configured in CONF state. @@ -413,7 +415,7 @@ extern "C" { /** SPI_USER1_REG register * SPI USER control register 1 */ -#define SPI_USER1_REG (DR_REG_SPI_BASE + 0x14) +#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14) /** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; * The length in spi_clk cycles of dummy phase. The register value shall be * (cycle_num-1). Can be configured in CONF state. @@ -459,7 +461,7 @@ extern "C" { /** SPI_USER2_REG register * SPI USER control register 2 */ -#define SPI_USER2_REG (DR_REG_SPI_BASE + 0x18) +#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18) /** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; * The value of command. Can be configured in CONF state. */ @@ -488,7 +490,7 @@ extern "C" { /** SPI_MS_DLEN_REG register * SPI data bit length control register */ -#define SPI_MS_DLEN_REG (DR_REG_SPI_BASE + 0x1c) +#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1c) /** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0; * The value of these bits is the configured SPI transmission data bit length in * master mode DMA controlled transfer or CPU controlled transfer. The value is also @@ -503,7 +505,7 @@ extern "C" { /** SPI_MISC_REG register * SPI misc register */ -#define SPI_MISC_REG (DR_REG_SPI_BASE + 0x20) +#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20) /** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0; * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can * be configured in CONF state. @@ -644,7 +646,7 @@ extern "C" { /** SPI_DIN_MODE_REG register * SPI input delay mode configuration */ -#define SPI_DIN_MODE_REG (DR_REG_SPI_BASE + 0x24) +#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24) /** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0; * the input signals are delayed by SPI module clock cycles, 0: input without delayed, * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input @@ -729,7 +731,7 @@ extern "C" { /** SPI_DIN_NUM_REG register * SPI input delay number configuration */ -#define SPI_DIN_NUM_REG (DR_REG_SPI_BASE + 0x28) +#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28) /** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... Can be configured in CONF state. @@ -798,7 +800,7 @@ extern "C" { /** SPI_DOUT_MODE_REG register * SPI output delay mode configuration */ -#define SPI_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x2c) +#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c) /** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0; * The output signal $n is delayed by the SPI module clock, 0: output without delayed, * 1: output delay for a SPI module clock cycle at its negative edge. Can be @@ -884,7 +886,7 @@ extern "C" { /** SPI_DMA_CONF_REG register * SPI DMA control register */ -#define SPI_DMA_CONF_REG (DR_REG_SPI_BASE + 0x30) +#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30) /** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1; * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: * DMA TX FIFO is ready for sending data. @@ -976,7 +978,7 @@ extern "C" { /** SPI_DMA_INT_ENA_REG register * SPI interrupt enable register */ -#define SPI_DMA_INT_ENA_REG (DR_REG_SPI_BASE + 0x34) +#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34) /** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0; * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ @@ -1128,7 +1130,7 @@ extern "C" { /** SPI_DMA_INT_CLR_REG register * SPI interrupt clear register */ -#define SPI_DMA_INT_CLR_REG (DR_REG_SPI_BASE + 0x38) +#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38) /** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0; * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ @@ -1280,7 +1282,7 @@ extern "C" { /** SPI_DMA_INT_RAW_REG register * SPI interrupt raw register */ -#define SPI_DMA_INT_RAW_REG (DR_REG_SPI_BASE + 0x3c) +#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x3c) /** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the * receive data. 0: Others. @@ -1454,7 +1456,7 @@ extern "C" { /** SPI_DMA_INT_ST_REG register * SPI interrupt status register */ -#define SPI_DMA_INT_ST_REG (DR_REG_SPI_BASE + 0x40) +#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x40) /** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0; * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ @@ -1606,7 +1608,7 @@ extern "C" { /** SPI_DMA_INT_SET_REG register * SPI interrupt software set register */ -#define SPI_DMA_INT_SET_REG (DR_REG_SPI_BASE + 0x44) +#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x44) /** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0; * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ @@ -1758,7 +1760,7 @@ extern "C" { /** SPI_W0_REG register * SPI CPU-controlled buffer0 */ -#define SPI_W0_REG (DR_REG_SPI_BASE + 0x98) +#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98) /** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1770,7 +1772,7 @@ extern "C" { /** SPI_W1_REG register * SPI CPU-controlled buffer1 */ -#define SPI_W1_REG (DR_REG_SPI_BASE + 0x9c) +#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9c) /** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1782,7 +1784,7 @@ extern "C" { /** SPI_W2_REG register * SPI CPU-controlled buffer2 */ -#define SPI_W2_REG (DR_REG_SPI_BASE + 0xa0) +#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xa0) /** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1794,7 +1796,7 @@ extern "C" { /** SPI_W3_REG register * SPI CPU-controlled buffer3 */ -#define SPI_W3_REG (DR_REG_SPI_BASE + 0xa4) +#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xa4) /** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1806,7 +1808,7 @@ extern "C" { /** SPI_W4_REG register * SPI CPU-controlled buffer4 */ -#define SPI_W4_REG (DR_REG_SPI_BASE + 0xa8) +#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xa8) /** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1818,7 +1820,7 @@ extern "C" { /** SPI_W5_REG register * SPI CPU-controlled buffer5 */ -#define SPI_W5_REG (DR_REG_SPI_BASE + 0xac) +#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xac) /** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1830,7 +1832,7 @@ extern "C" { /** SPI_W6_REG register * SPI CPU-controlled buffer6 */ -#define SPI_W6_REG (DR_REG_SPI_BASE + 0xb0) +#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xb0) /** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1842,7 +1844,7 @@ extern "C" { /** SPI_W7_REG register * SPI CPU-controlled buffer7 */ -#define SPI_W7_REG (DR_REG_SPI_BASE + 0xb4) +#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xb4) /** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1854,7 +1856,7 @@ extern "C" { /** SPI_W8_REG register * SPI CPU-controlled buffer8 */ -#define SPI_W8_REG (DR_REG_SPI_BASE + 0xb8) +#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xb8) /** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1866,7 +1868,7 @@ extern "C" { /** SPI_W9_REG register * SPI CPU-controlled buffer9 */ -#define SPI_W9_REG (DR_REG_SPI_BASE + 0xbc) +#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xbc) /** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1878,7 +1880,7 @@ extern "C" { /** SPI_W10_REG register * SPI CPU-controlled buffer10 */ -#define SPI_W10_REG (DR_REG_SPI_BASE + 0xc0) +#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xc0) /** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1890,7 +1892,7 @@ extern "C" { /** SPI_W11_REG register * SPI CPU-controlled buffer11 */ -#define SPI_W11_REG (DR_REG_SPI_BASE + 0xc4) +#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xc4) /** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1902,7 +1904,7 @@ extern "C" { /** SPI_W12_REG register * SPI CPU-controlled buffer12 */ -#define SPI_W12_REG (DR_REG_SPI_BASE + 0xc8) +#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xc8) /** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1914,7 +1916,7 @@ extern "C" { /** SPI_W13_REG register * SPI CPU-controlled buffer13 */ -#define SPI_W13_REG (DR_REG_SPI_BASE + 0xcc) +#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xcc) /** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1926,7 +1928,7 @@ extern "C" { /** SPI_W14_REG register * SPI CPU-controlled buffer14 */ -#define SPI_W14_REG (DR_REG_SPI_BASE + 0xd0) +#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xd0) /** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1938,7 +1940,7 @@ extern "C" { /** SPI_W15_REG register * SPI CPU-controlled buffer15 */ -#define SPI_W15_REG (DR_REG_SPI_BASE + 0xd4) +#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xd4) /** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -1950,7 +1952,7 @@ extern "C" { /** SPI_SLAVE_REG register * SPI slave control register */ -#define SPI_SLAVE_REG (DR_REG_SPI_BASE + 0xe0) +#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0) /** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: @@ -2059,7 +2061,7 @@ extern "C" { /** SPI_SLAVE1_REG register * SPI slave control register 1 */ -#define SPI_SLAVE1_REG (DR_REG_SPI_BASE + 0xe4) +#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xe4) /** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0; * The transferred data bit length in SPI slave FD and HD mode. */ @@ -2085,7 +2087,7 @@ extern "C" { /** SPI_CLK_GATE_REG register * SPI module clock and register clock control */ -#define SPI_CLK_GATE_REG (DR_REG_SPI_BASE + 0xe8) +#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8) /** SPI_CLK_EN : R/W; bitpos: [0]; default: 0; * Set this bit to enable clk gate */ @@ -2112,7 +2114,7 @@ extern "C" { /** SPI_DATE_REG register * Version control */ -#define SPI_DATE_REG (DR_REG_SPI_BASE + 0xf0) +#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0) /** SPI_DATE : R/W; bitpos: [27:0]; default: 37761424; * SPI register version. */ diff --git a/components/soc/esp32s31/register/soc/spi_struct.h b/components/soc/esp32s31/register/soc/spi_struct.h index c3eb24f70c..2716f0edf7 100644 --- a/components/soc/esp32s31/register/soc/spi_struct.h +++ b/components/soc/esp32s31/register/soc/spi_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -1343,214 +1343,18 @@ typedef union { /** Group: CPU-controlled data buffer */ -/** Type of w0 register - * SPI CPU-controlled buffer0 +/** Type of wn register + * SPI CPU-controlled buffer */ typedef union { struct { - /** buf0 : R/W/SS; bitpos: [31:0]; default: 0; + /** buf : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ - uint32_t buf0:32; + uint32_t buf:32; }; uint32_t val; -} spi_w0_reg_t; - -/** Type of w1 register - * SPI CPU-controlled buffer1 - */ -typedef union { - struct { - /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf1:32; - }; - uint32_t val; -} spi_w1_reg_t; - -/** Type of w2 register - * SPI CPU-controlled buffer2 - */ -typedef union { - struct { - /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf2:32; - }; - uint32_t val; -} spi_w2_reg_t; - -/** Type of w3 register - * SPI CPU-controlled buffer3 - */ -typedef union { - struct { - /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf3:32; - }; - uint32_t val; -} spi_w3_reg_t; - -/** Type of w4 register - * SPI CPU-controlled buffer4 - */ -typedef union { - struct { - /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf4:32; - }; - uint32_t val; -} spi_w4_reg_t; - -/** Type of w5 register - * SPI CPU-controlled buffer5 - */ -typedef union { - struct { - /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf5:32; - }; - uint32_t val; -} spi_w5_reg_t; - -/** Type of w6 register - * SPI CPU-controlled buffer6 - */ -typedef union { - struct { - /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf6:32; - }; - uint32_t val; -} spi_w6_reg_t; - -/** Type of w7 register - * SPI CPU-controlled buffer7 - */ -typedef union { - struct { - /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf7:32; - }; - uint32_t val; -} spi_w7_reg_t; - -/** Type of w8 register - * SPI CPU-controlled buffer8 - */ -typedef union { - struct { - /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf8:32; - }; - uint32_t val; -} spi_w8_reg_t; - -/** Type of w9 register - * SPI CPU-controlled buffer9 - */ -typedef union { - struct { - /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf9:32; - }; - uint32_t val; -} spi_w9_reg_t; - -/** Type of w10 register - * SPI CPU-controlled buffer10 - */ -typedef union { - struct { - /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf10:32; - }; - uint32_t val; -} spi_w10_reg_t; - -/** Type of w11 register - * SPI CPU-controlled buffer11 - */ -typedef union { - struct { - /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf11:32; - }; - uint32_t val; -} spi_w11_reg_t; - -/** Type of w12 register - * SPI CPU-controlled buffer12 - */ -typedef union { - struct { - /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf12:32; - }; - uint32_t val; -} spi_w12_reg_t; - -/** Type of w13 register - * SPI CPU-controlled buffer13 - */ -typedef union { - struct { - /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf13:32; - }; - uint32_t val; -} spi_w13_reg_t; - -/** Type of w14 register - * SPI CPU-controlled buffer14 - */ -typedef union { - struct { - /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf14:32; - }; - uint32_t val; -} spi_w14_reg_t; - -/** Type of w15 register - * SPI CPU-controlled buffer15 - */ -typedef union { - struct { - /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf15:32; - }; - uint32_t val; -} spi_w15_reg_t; - +} spi_wn_reg_t; /** Group: Version register */ /** Type of date register @@ -1588,22 +1392,7 @@ typedef struct { volatile spi_dma_int_st_reg_t dma_int_st; volatile spi_dma_int_set_reg_t dma_int_set; uint32_t reserved_048[20]; - volatile spi_w0_reg_t w0; - volatile spi_w1_reg_t w1; - volatile spi_w2_reg_t w2; - volatile spi_w3_reg_t w3; - volatile spi_w4_reg_t w4; - volatile spi_w5_reg_t w5; - volatile spi_w6_reg_t w6; - volatile spi_w7_reg_t w7; - volatile spi_w8_reg_t w8; - volatile spi_w9_reg_t w9; - volatile spi_w10_reg_t w10; - volatile spi_w11_reg_t w11; - volatile spi_w12_reg_t w12; - volatile spi_w13_reg_t w13; - volatile spi_w14_reg_t w14; - volatile spi_w15_reg_t w15; + volatile spi_wn_reg_t data_buf[16]; uint32_t reserved_0d8[2]; volatile spi_slave_reg_t slave; volatile spi_slave1_reg_t slave1; diff --git a/examples/peripherals/lcd/spi_lcd_touch/README.md b/examples/peripherals/lcd/spi_lcd_touch/README.md index 2f4e0ec119..d54c605ec9 100644 --- a/examples/peripherals/lcd/spi_lcd_touch/README.md +++ b/examples/peripherals/lcd/spi_lcd_touch/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | # SPI LCD and Touch Panel Example diff --git a/examples/peripherals/lcd/tjpgd/README.md b/examples/peripherals/lcd/tjpgd/README.md index 999eb0f19d..df0e47c98d 100644 --- a/examples/peripherals/lcd/tjpgd/README.md +++ b/examples/peripherals/lcd/tjpgd/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | ## LCD tjpgd example diff --git a/examples/peripherals/spi_master/hd_eeprom/README.md b/examples/peripherals/spi_master/hd_eeprom/README.md index 5efc228a77..62e25b55f1 100644 --- a/examples/peripherals/spi_master/hd_eeprom/README.md +++ b/examples/peripherals/spi_master/hd_eeprom/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | ## SPI master half duplex EEPROM example diff --git a/examples/peripherals/spi_master/lcd/README.md b/examples/peripherals/spi_master/lcd/README.md index 2ac30e1bb3..feb74b243f 100644 --- a/examples/peripherals/spi_master/lcd/README.md +++ b/examples/peripherals/spi_master/lcd/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | # SPI Host Driver Example diff --git a/examples/peripherals/spi_slave/README.md b/examples/peripherals/spi_slave/README.md index c5eb327e3a..5500fc031a 100644 --- a/examples/peripherals/spi_slave/README.md +++ b/examples/peripherals/spi_slave/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | ## SPI slave example diff --git a/examples/peripherals/spi_slave_hd/append_mode/master/README.md b/examples/peripherals/spi_slave_hd/append_mode/master/README.md index 718bc74519..a19ef8c5b4 100644 --- a/examples/peripherals/spi_slave_hd/append_mode/master/README.md +++ b/examples/peripherals/spi_slave_hd/append_mode/master/README.md @@ -1,4 +1,4 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | See README.md in the parent directory diff --git a/examples/peripherals/spi_slave_hd/append_mode/slave/README.md b/examples/peripherals/spi_slave_hd/append_mode/slave/README.md index 718bc74519..a19ef8c5b4 100644 --- a/examples/peripherals/spi_slave_hd/append_mode/slave/README.md +++ b/examples/peripherals/spi_slave_hd/append_mode/slave/README.md @@ -1,4 +1,4 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | See README.md in the parent directory diff --git a/examples/peripherals/spi_slave_hd/segment_mode/seg_master/README.md b/examples/peripherals/spi_slave_hd/segment_mode/seg_master/README.md index 718bc74519..a19ef8c5b4 100644 --- a/examples/peripherals/spi_slave_hd/segment_mode/seg_master/README.md +++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_master/README.md @@ -1,4 +1,4 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | See README.md in the parent directory diff --git a/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/README.md b/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/README.md index b91fc54735..c5f27873ef 100644 --- a/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/README.md +++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | diff --git a/examples/storage/.build-test-rules.yml b/examples/storage/.build-test-rules.yml index afbff82ad2..dfd41a3726 100644 --- a/examples/storage/.build-test-rules.yml +++ b/examples/storage/.build-test-rules.yml @@ -58,6 +58,9 @@ examples/storage/perf_benchmark: - if: IDF_TARGET == "esp32p4" and CONFIG_NAME in ["sdmmc_1line", "sdmmc_4line", "sdspi_1line"] temporary: true reason: lack of runners, build only # TODO: IDF-8970 + - if: IDF_TARGET == "esp32s31" + temporary: true + reason: lack of runners, but spi_flash not supported yet examples/storage/sd_card/sdmmc: depends_components: diff --git a/examples/storage/perf_benchmark/README.md b/examples/storage/perf_benchmark/README.md index 9e556b8cf1..d397dd3fdb 100644 --- a/examples/storage/perf_benchmark/README.md +++ b/examples/storage/perf_benchmark/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | # Storage performance benchmark example diff --git a/examples/storage/perf_benchmark/pytest_perf_benchmark_example.py b/examples/storage/perf_benchmark/pytest_perf_benchmark_example.py index e7f9ccd445..9fea5fcae4 100644 --- a/examples/storage/perf_benchmark/pytest_perf_benchmark_example.py +++ b/examples/storage/perf_benchmark/pytest_perf_benchmark_example.py @@ -50,7 +50,8 @@ def test_examples_perf_benchmark_sdcard_sdmmc(dut: Dut) -> None: @pytest.mark.temp_skip_ci(targets=['esp32'], reason='IDFCI-2059, temporary lack runner') -@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C5 C61 GPSPI same, so testing on C5 is enough') +@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='GPSPI is same, testing on C5 is enough') +@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='GPSPI is same, testing on C5 is enough') @pytest.mark.sdcard_spimode @pytest.mark.parametrize( 'config', diff --git a/examples/storage/sd_card/sdspi/README.md b/examples/storage/sd_card/sdspi/README.md index 0386e4d1f7..04b8248df1 100644 --- a/examples/storage/sd_card/sdspi/README.md +++ b/examples/storage/sd_card/sdspi/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | # SD Card example (SDSPI)