diff --git a/components/esp_driver_ledc/src/ledc.c b/components/esp_driver_ledc/src/ledc.c index e12ef6b4cd..43216629fc 100644 --- a/components/esp_driver_ledc/src/ledc.c +++ b/components/esp_driver_ledc/src/ledc.c @@ -874,7 +874,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf) /*set channel parameters*/ /* channel parameters decide how the waveform looks like in one period */ /* set channel duty and hpoint value, duty range is [0, (2**duty_res)], hpoint range is [0, (2**duty_res)-1] */ - /* Note: On ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4, due to a hardware bug, + /* Note: On ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4 (rev < 3.0), due to a hardware bug, * 100% duty cycle (i.e. 2**duty_res) is not reachable when the binded timer selects the maximum duty * resolution. For example, the max duty resolution on ESP32C3 is 14-bit width, then set duty to (2**14) * will mess up the duty calculation in hardware. diff --git a/components/esp_driver_ppa/include/driver/ppa.h b/components/esp_driver_ppa/include/driver/ppa.h index 5f209e85e0..9f019a4557 100644 --- a/components/esp_driver_ppa/include/driver/ppa.h +++ b/components/esp_driver_ppa/include/driver/ppa.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -127,6 +127,7 @@ typedef struct { }; ppa_color_range_t yuv_range; /*!< When the color mode is any YUV color space, this field is to describe its color range */ ppa_color_conv_std_rgb_yuv_t yuv_std; /*!< When the color mode is any YUV color space, this field is to describe its YUV<->RGB conversion standard */ + color_yuv422_pack_order_t yuv422_pack_order; /*!< When the color mode is YUV422, this field is to describe its data pack order */ } ppa_in_pic_blk_config_t; /** @@ -268,7 +269,12 @@ typedef struct { uint32_t fill_block_w; /*!< The width of the block to be filled (unit: pixel) */ uint32_t fill_block_h; /*!< The height of the block to be filled (unit: pixel) */ - color_pixel_argb8888_data_t fill_argb_color; /*!< The color to be filled, in ARGB8888 format */ + union { + color_pixel_argb8888_data_t fill_argb_color; /*!< For any ARGB/RGB format color to be filled, use this field to fill A (if applicable)/R/G/B components */ + color_pixel_gray8_data_t fill_gray8_color; /*!< For GRAY8 format color to be filled */ + color_macroblock_yuv_data_t fill_yuv_color; /*!< For any YUV format color to be filled, use this field to fill Y/U/V components */ + uint32_t fill_color_val; /*!< The color to be filled, in a raw 32-bit value. The interpretation of the value depends on the selected `fill_cm` */ + }; ppa_trans_mode_t mode; /*!< Determines whether to block inside the operation functions, see `ppa_trans_mode_t` */ void *user_data; /*!< User registered data to be passed into `done_cb` callback function */ @@ -287,6 +293,23 @@ typedef struct { */ esp_err_t ppa_do_fill(ppa_client_handle_t ppa_client, const ppa_fill_oper_config_t *config); +/** + * @brief Configure the RGB888 to GRAY8 color conversion coefficients for ppa_do_scale_rotate_mirror and ppa_do_fill + * + * The gray value is calculated as: gray = (r_weight * R + g_weight * G + b_weight * B) >> 8 + * Note: (r_weight + g_weight + b_weight) should equal to 256. + * + * @param r_weight Coefficient for R component, range: [0, 255] + * @param g_weight Coefficient for G component, range: [0, 255] + * @param b_weight Coefficient for B component, range: [0, 255] + * @return + * - ESP_OK: Set the RGB888 to GRAY color conversion formula successfully + * - ESP_ERR_NOT_SUPPORTED: Set the RGB888 to GRAY color conversion formula failed because the PPA peripheral does not support this feature + * - ESP_ERR_INVALID_ARG: Set the RGB888 to GRAY color conversion formula failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Set the RGB888 to GRAY color conversion formula failed because the PPA peripheral not initialized + */ +esp_err_t ppa_set_rgb2gray_formula(uint8_t r_weight, uint8_t g_weight, uint8_t b_weight); + #ifdef __cplusplus } #endif diff --git a/components/esp_driver_ppa/src/ppa_blend.c b/components/esp_driver_ppa/src/ppa_blend.c index eec46e560d..7a44dce2df 100644 --- a/components/esp_driver_ppa/src/ppa_blend.c +++ b/components/esp_driver_ppa/src/ppa_blend.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -140,6 +140,13 @@ bool ppa_blend_transaction_on_picked(uint32_t num_chans, const dma2d_trans_chann // Configure PPA Blending engine ppa_ll_blend_set_rx_bg_color_mode(platform->hal.dev, blend_trans_desc->in_bg.blend_cm); + if (COLOR_SPACE_TYPE((uint32_t)blend_trans_desc->in_bg.blend_cm) == COLOR_SPACE_YUV) { + ppa_ll_blend_set_rx_bg_yuv_range(platform->hal.dev, blend_trans_desc->in_bg.yuv_range); + ppa_ll_blend_set_rx_bg_yuv2rgb_std(platform->hal.dev, blend_trans_desc->in_bg.yuv_std); + } + if ((uint32_t)blend_trans_desc->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_YUV422) { + ppa_ll_blend_set_rx_bg_yuv422_pack_order(platform->hal.dev, blend_trans_desc->in_bg.yuv422_pack_order); + } ppa_ll_blend_enable_rx_bg_byte_swap(platform->hal.dev, blend_trans_desc->bg_byte_swap); ppa_ll_blend_enable_rx_bg_rgb_swap(platform->hal.dev, blend_trans_desc->bg_rgb_swap); ppa_ll_blend_configure_rx_bg_alpha(platform->hal.dev, blend_trans_desc->bg_alpha_update_mode, blend_trans_desc->bg_alpha_value); @@ -153,6 +160,10 @@ bool ppa_blend_transaction_on_picked(uint32_t num_chans, const dma2d_trans_chann ppa_ll_blend_configure_rx_fg_alpha(platform->hal.dev, blend_trans_desc->fg_alpha_update_mode, blend_trans_desc->fg_alpha_value); ppa_ll_blend_set_tx_color_mode(platform->hal.dev, blend_trans_desc->out.blend_cm); + if (COLOR_SPACE_TYPE((uint32_t)blend_trans_desc->out.blend_cm) == COLOR_SPACE_YUV) { + ppa_ll_blend_set_tx_yuv_range(platform->hal.dev, blend_trans_desc->out.yuv_range); + ppa_ll_blend_set_tx_rgb2yuv_std(platform->hal.dev, blend_trans_desc->out.yuv_std); + } // Color keying color_pixel_rgb888_data_t rgb888_min = {.b = 0x00, .g = 0x00, .r = 0x00}; @@ -182,6 +193,41 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf uint32_t buf_alignment_size = (uint32_t)ppa_client->engine->platform->buf_alignment_size; ESP_RETURN_ON_FALSE(((uint32_t)config->out.buffer & (buf_alignment_size - 1)) == 0 && (config->out.buffer_size & (buf_alignment_size - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "out.buffer addr or out.buffer_size not aligned to cache line size"); + ESP_RETURN_ON_FALSE(ppa_ll_blend_is_color_mode_supported(config->in_bg.blend_cm) && ppa_ll_blend_is_color_mode_supported(config->in_fg.blend_cm) && ppa_ll_blend_is_color_mode_supported(config->out.blend_cm), ESP_ERR_INVALID_ARG, TAG, "unsupported color mode"); + // For YUV420 input/output: in desc, ha/hb/va/vb/x/y must be even number + // For YUV422 input/output: in desc, ha/hb/x must be even number + if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_YUV420) { + ESP_RETURN_ON_FALSE(config->in_bg.pic_h % 2 == 0 && config->in_bg.pic_w % 2 == 0 && + config->in_bg.block_h % 2 == 0 && config->in_bg.block_w % 2 == 0 && + config->in_bg.block_offset_x % 2 == 0 && config->in_bg.block_offset_y % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV420 input does not support odd h/w/offset_x/offset_y"); + } else if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_YUV422) { + ESP_RETURN_ON_FALSE(config->in_bg.pic_w % 2 == 0 && config->in_bg.block_w % 2 == 0 && config->in_bg.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 input does not support odd w/offset_x"); + } + // TODO: Support CLUT to support L4/L8 color mode + // else if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_L4) { + // ESP_RETURN_ON_FALSE(config->in_bg.block_w % 2 == 0 && config->in_bg.block_offset_x % 2 == 0, + // ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w and in_bg.block_offset_x must be even"); + // } + if (config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_A4) { // || config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_L4 + ESP_RETURN_ON_FALSE(config->in_fg.block_w % 2 == 0 && config->in_fg.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "in_fg.block_w and in_fg.block_offset_x must be even"); + } + if (config->out.blend_cm == PPA_BLEND_COLOR_MODE_YUV420) { + ESP_RETURN_ON_FALSE(config->out.pic_h % 2 == 0 && config->out.pic_w % 2 == 0 && + config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y"); + } else if (config->out.blend_cm == PPA_BLEND_COLOR_MODE_YUV422) { + ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x"); + } + ESP_RETURN_ON_FALSE(config->in_bg.block_w <= (config->in_bg.pic_w - config->in_bg.block_offset_x) && + config->in_bg.block_h <= (config->in_bg.pic_h - config->in_bg.block_offset_y), + ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w/h + in_bg.block_offset_x/y does not fit in the in pic"); + ESP_RETURN_ON_FALSE(config->in_fg.block_w <= (config->in_fg.pic_w - config->in_fg.block_offset_x) && + config->in_fg.block_h <= (config->in_fg.pic_h - config->in_fg.block_offset_y), + ESP_ERR_INVALID_ARG, TAG, "in_fg.block_w/h + in_fg.block_offset_x/y does not fit in the in pic"); color_space_pixel_format_t out_pixel_format = { .color_type_id = config->out.blend_cm, }; @@ -190,6 +236,9 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf ESP_RETURN_ON_FALSE(out_pic_len <= config->out.buffer_size, ESP_ERR_INVALID_ARG, TAG, "out.pic_w/h mismatch with out.buffer_size"); ESP_RETURN_ON_FALSE(config->in_bg.block_w == config->in_fg.block_w && config->in_bg.block_h == config->in_fg.block_h, ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w/h must be equal to in_fg.block_w/h"); + ESP_RETURN_ON_FALSE(config->in_fg.block_w <= (config->out.pic_w - config->out.block_offset_x) && + config->in_fg.block_h <= (config->out.pic_h - config->out.block_offset_y), + ESP_ERR_INVALID_ARG, TAG, "block does not fit in the out pic"); if (config->bg_byte_swap) { PPA_CHECK_CM_SUPPORT_BYTE_SWAP("in_bg.blend", (uint32_t)config->in_bg.blend_cm); } @@ -218,15 +267,7 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf ESP_RETURN_ON_FALSE(config->fg_alpha_scale_ratio > 0 && config->fg_alpha_scale_ratio < 1, ESP_ERR_INVALID_ARG, TAG, "invalid fg_alpha_scale_ratio"); new_fg_alpha_value = (uint32_t)(config->fg_alpha_scale_ratio * 256); } - // if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_L4) { - // ESP_RETURN_ON_FALSE(config->in_bg.block_w % 2 == 0 && config->in_bg.block_offset_x % 2 == 0, - // ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w and in_bg.block_offset_x must be even"); - // } - if (config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_A4) { // || config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_L4 - ESP_RETURN_ON_FALSE(config->in_fg.block_w % 2 == 0 && config->in_fg.block_offset_x % 2 == 0, - ESP_ERR_INVALID_ARG, TAG, "in_fg.block_w and in_fg.block_offset_x must be even"); - } - // To reduce complexity, color_mode, alpha_update_mode correctness are checked in their corresponding LL functions + // To reduce complexity, specific color_mode, alpha_update_mode correctness are checked in their corresponding LL functions // Write back and invalidate necessary data (note that the window content is not continuous in the buffer) // Write back in_bg_buffer, in_fg_buffer extended windows (alignment not necessary on C2M direction) diff --git a/components/esp_driver_ppa/src/ppa_core.c b/components/esp_driver_ppa/src/ppa_core.c index a622abdbb5..a7b371478e 100644 --- a/components/esp_driver_ppa/src/ppa_core.c +++ b/components/esp_driver_ppa/src/ppa_core.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -513,3 +513,15 @@ bool ppa_transaction_done_cb(dma2d_channel_handle_t dma2d_chan, dma2d_event_data return need_yield; } + +esp_err_t ppa_set_rgb2gray_formula(uint8_t r_weight, uint8_t g_weight, uint8_t b_weight) +{ + ESP_RETURN_ON_FALSE(ppa_ll_srm_is_color_mode_supported(PPA_SRM_COLOR_MODE_GRAY8) || ppa_ll_blend_is_color_mode_supported(PPA_BLEND_COLOR_MODE_GRAY8), ESP_ERR_NOT_SUPPORTED, TAG, "GRAY color mode not supported"); + ESP_RETURN_ON_FALSE((r_weight + g_weight + b_weight) == 256, ESP_ERR_INVALID_ARG, TAG, "invalid rgb2gray formula"); + ESP_RETURN_ON_FALSE(s_platform.hal.dev, ESP_ERR_INVALID_STATE, TAG, "no PPA client registered yet"); + + _lock_acquire(&s_platform.mutex); + ppa_ll_set_rgb2gray_coeff(s_platform.hal.dev, r_weight, g_weight, b_weight); + _lock_release(&s_platform.mutex); + return ESP_OK; +} diff --git a/components/esp_driver_ppa/src/ppa_fill.c b/components/esp_driver_ppa/src/ppa_fill.c index d8c3aef456..9ec997649b 100644 --- a/components/esp_driver_ppa/src/ppa_fill.c +++ b/components/esp_driver_ppa/src/ppa_fill.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -77,7 +77,7 @@ bool ppa_fill_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channe dma2d_start(dma2d_rx_chan); // Configure PPA Blending engine - ppa_ll_blend_configure_filling_block(platform->hal.dev, &fill_trans_desc->fill_argb_color, fill_trans_desc->fill_block_w, fill_trans_desc->fill_block_h); + ppa_ll_blend_configure_filling_block(platform->hal.dev, fill_trans_desc->out.fill_cm, (void *)&fill_trans_desc->fill_color_val, fill_trans_desc->fill_block_w, fill_trans_desc->fill_block_h); ppa_ll_blend_set_tx_color_mode(platform->hal.dev, fill_trans_desc->out.fill_cm); ppa_ll_blend_start(platform->hal.dev, PPA_LL_BLEND_TRANS_MODE_FILL); @@ -96,13 +96,28 @@ esp_err_t ppa_do_fill(ppa_client_handle_t ppa_client, const ppa_fill_oper_config uint32_t buf_alignment_size = (uint32_t)ppa_client->engine->platform->buf_alignment_size; ESP_RETURN_ON_FALSE(((uint32_t)config->out.buffer & (buf_alignment_size - 1)) == 0 && (config->out.buffer_size & (buf_alignment_size - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "out.buffer addr or out.buffer_size not aligned to cache line size"); + ESP_RETURN_ON_FALSE(ppa_ll_blend_is_color_mode_supported((ppa_blend_color_mode_t)config->out.fill_cm), ESP_ERR_INVALID_ARG, TAG, "unsupported color mode"); + // For YUV420 output: in desc, ha/hb/va/vb/x/y must be even number + // For YUV422 output: in desc, ha/hb/x must be even number + // if (config->out.fill_cm == PPA_FILL_COLOR_MODE_YUV420) { + // ESP_RETURN_ON_FALSE(config->out.pic_h % 2 == 0 && config->out.pic_w % 2 == 0 && + // config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0, + // ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y"); + // } else + if (config->out.fill_cm == PPA_FILL_COLOR_MODE_YUV422) { + ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x"); + } color_space_pixel_format_t out_pixel_format = { .color_type_id = config->out.fill_cm, }; uint32_t out_pixel_depth = color_hal_pixel_format_get_bit_depth(out_pixel_format); uint32_t out_pic_len = config->out.pic_w * config->out.pic_h * out_pixel_depth / 8; ESP_RETURN_ON_FALSE(out_pic_len <= config->out.buffer_size, ESP_ERR_INVALID_ARG, TAG, "out.pic_w/h mismatch with out.buffer_size"); - // To reduce complexity, color_mode, fill_block_w/h correctness are checked in their corresponding LL functions + ESP_RETURN_ON_FALSE(config->fill_block_w <= (config->out.pic_w - config->out.block_offset_x) && + config->fill_block_h <= (config->out.pic_h - config->out.block_offset_y), + ESP_ERR_INVALID_ARG, TAG, "block does not fit in the out pic"); + // To reduce complexity, specific color_mode, fill_block_w/h correctness are checked in their corresponding LL functions // Write back and invalidate necessary data (note that the window content is not continuous in the buffer) // Write back and invalidate buffer extended window (alignment not necessary on C2M direction, but alignment strict on M2C direction) diff --git a/components/esp_driver_ppa/src/ppa_priv.h b/components/esp_driver_ppa/src/ppa_priv.h index 6cefafefd2..d335145a45 100644 --- a/components/esp_driver_ppa/src/ppa_priv.h +++ b/components/esp_driver_ppa/src/ppa_priv.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -174,7 +174,12 @@ typedef struct { uint32_t fill_block_w; uint32_t fill_block_h; - color_pixel_argb8888_data_t fill_argb_color; + union { + color_pixel_argb8888_data_t fill_argb_color; + color_pixel_gray8_data_t fill_gray8_color; + color_macroblock_yuv_data_t fill_yuv_color; + uint32_t fill_color_val; + }; ppa_trans_mode_t mode; void *user_data; diff --git a/components/esp_driver_ppa/src/ppa_srm.c b/components/esp_driver_ppa/src/ppa_srm.c index 51849c1c9a..9e48868238 100644 --- a/components/esp_driver_ppa/src/ppa_srm.c +++ b/components/esp_driver_ppa/src/ppa_srm.c @@ -100,13 +100,6 @@ bool ppa_srm_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel dma2d_set_transfer_ability(dma2d_tx_chan, &dma_transfer_ability); dma2d_set_transfer_ability(dma2d_rx_chan, &dma_transfer_ability); - // Configure the block size to be received by the SRM engine, which is passed from the 2D-DMA TX channel (i.e. 2D-DMA dscr-port mode) - dma2d_dscr_port_mode_config_t dma_dscr_port_mode_config = { - .block_h = (srm_trans_desc->in.srm_cm == PPA_SRM_COLOR_MODE_YUV420) ? PPA_LL_SRM_YUV420_BLOCK_SIZE : PPA_LL_SRM_DEFAULT_BLOCK_SIZE, - .block_v = (srm_trans_desc->in.srm_cm == PPA_SRM_COLOR_MODE_YUV420) ? PPA_LL_SRM_YUV420_BLOCK_SIZE : PPA_LL_SRM_DEFAULT_BLOCK_SIZE, - }; - dma2d_configure_dscr_port_mode(dma2d_tx_chan, &dma_dscr_port_mode_config); - // YUV444 is not supported by PPA module, need to utilize 2D-DMA color space conversion feature to do a conversion ppa_srm_color_mode_t ppa_in_color_mode = srm_trans_desc->in.srm_cm; if (ppa_in_color_mode == PPA_SRM_COLOR_MODE_YUV444) { @@ -129,6 +122,15 @@ bool ppa_srm_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel dma2d_configure_color_space_conversion(dma2d_rx_chan, &dma_rx_csc); } + // Configure the block size to be received by the SRM engine, which is passed from the 2D-DMA TX channel (i.e. 2D-DMA dscr-port mode) + uint32_t block_h = 0, block_v = 0; + ppa_ll_srm_get_dma_dscr_port_mode_block_size(platform->hal.dev, ppa_in_color_mode, ppa_ll_srm_get_mb_size(platform->hal.dev), &block_h, &block_v); + dma2d_dscr_port_mode_config_t dma_dscr_port_mode_config = { + .block_h = block_h, + .block_v = block_v, + }; + dma2d_configure_dscr_port_mode(dma2d_tx_chan, &dma_dscr_port_mode_config); + dma2d_rx_event_callbacks_t dma_event_cbs = { .on_recv_eof = ppa_transaction_done_cb, }; @@ -145,6 +147,9 @@ bool ppa_srm_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel ppa_ll_srm_set_rx_yuv_range(platform->hal.dev, srm_trans_desc->in.yuv_range); ppa_ll_srm_set_rx_yuv2rgb_std(platform->hal.dev, srm_trans_desc->in.yuv_std); } + if ((uint32_t)ppa_in_color_mode == COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422)) { + ppa_ll_srm_set_rx_yuv422_pack_order(platform->hal.dev, srm_trans_desc->in.yuv422_pack_order); + } ppa_ll_srm_enable_rx_byte_swap(platform->hal.dev, srm_trans_desc->byte_swap); ppa_ll_srm_enable_rx_rgb_swap(platform->hal.dev, srm_trans_desc->rgb_swap); ppa_ll_srm_configure_rx_alpha(platform->hal.dev, srm_trans_desc->alpha_update_mode, srm_trans_desc->alpha_value); @@ -177,22 +182,25 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s uint32_t buf_alignment_size = (uint32_t)ppa_client->engine->platform->buf_alignment_size; ESP_RETURN_ON_FALSE(((uint32_t)config->out.buffer & (buf_alignment_size - 1)) == 0 && (config->out.buffer_size & (buf_alignment_size - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "out.buffer addr or out.buffer_size not aligned to cache line size"); + ESP_RETURN_ON_FALSE(ppa_ll_srm_is_color_mode_supported(config->in.srm_cm) && ppa_ll_srm_is_color_mode_supported(config->out.srm_cm), ESP_ERR_INVALID_ARG, TAG, "unsupported color mode"); // For YUV420 input/output: in desc, ha/hb/va/vb/x/y must be even number + // For YUV422 input/output: in desc, ha/hb/x must be even number if (config->in.srm_cm == PPA_SRM_COLOR_MODE_YUV420) { ESP_RETURN_ON_FALSE(config->in.pic_h % 2 == 0 && config->in.pic_w % 2 == 0 && config->in.block_h % 2 == 0 && config->in.block_w % 2 == 0 && config->in.block_offset_x % 2 == 0 && config->in.block_offset_y % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV420 input does not support odd h/w/offset_x/offset_y"); + } else if (config->in.srm_cm == PPA_SRM_COLOR_MODE_YUV422) { + ESP_RETURN_ON_FALSE(config->in.pic_w % 2 == 0 && config->in.block_w % 2 == 0 && config->in.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 input does not support odd w/offset_x"); } - // TODO: P4 ECO2 support YUV422 - // else if (config->in.srm_cm == PPA_SRM_COLOR_MODE_YUV422) { - // ESP_RETURN_ON_FALSE(config->in.pic_w % 2 == 0 && config->in.block_w % 2 == 0 && config->in.block_offset_x % 2 == 0, - // ESP_ERR_INVALID_ARG, TAG, "YUV422 input does not support odd w/offset_x"); - // } if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV420) { ESP_RETURN_ON_FALSE(config->out.pic_h % 2 == 0 && config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y"); + } else if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV422) { + ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x"); } ESP_RETURN_ON_FALSE(config->in.block_w <= (config->in.pic_w - config->in.block_offset_x) && config->in.block_h <= (config->in.pic_h - config->in.block_offset_y), @@ -232,7 +240,7 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s ESP_RETURN_ON_FALSE(config->alpha_scale_ratio > 0 && config->alpha_scale_ratio < 1, ESP_ERR_INVALID_ARG, TAG, "invalid alpha_scale_ratio"); new_alpha_value = (uint32_t)(config->alpha_scale_ratio * 256); } - // To reduce complexity, rotation_angle, color_mode, alpha_update_mode correctness are checked in their corresponding LL functions + // To reduce complexity, rotation_angle, alpha_update_mode correctness are checked in their corresponding LL functions // Write back and invalidate necessary data (note that the window content is not continuous in the buffer) // Write back in_buffer extended window (alignment not necessary on C2M direction) @@ -270,6 +278,8 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV420) { srm_trans_desc->scale_x_frag = srm_trans_desc->scale_x_frag & ~1; srm_trans_desc->scale_y_frag = srm_trans_desc->scale_y_frag & ~1; + } else if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV422) { + srm_trans_desc->scale_x_frag = srm_trans_desc->scale_x_frag & ~1; } srm_trans_desc->alpha_value = new_alpha_value; srm_trans_desc->data_burst_length = ppa_client->data_burst_length; diff --git a/components/esp_driver_ppa/test_apps/main/ppa_performance.h b/components/esp_driver_ppa/test_apps/main/ppa_performance.h new file mode 100644 index 0000000000..edab08fc14 --- /dev/null +++ b/components/esp_driver_ppa/test_apps/main/ppa_performance.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "sdkconfig.h" + +/* + * The time spend (T) to complete a PPA transaction is proportional to the amount of pixels (x) need to be processed. + * T = k * x + b + * k = (T - b) / x + */ + +#if CONFIG_IDF_TARGET_ESP32P4 +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 +#define PPA_SRM_MIN_PERFORMANCE_PX_PER_SEC (21000 * 1000) // k_min +#define PPA_SRM_TIME_OFFSET (-26000) // b_approx +#else +#define PPA_SRM_MIN_PERFORMANCE_PX_PER_SEC (35000 * 1000) // k_min +#define PPA_SRM_TIME_OFFSET (-37000) // b_approx +#endif + +#define PPA_BLEND_MIN_PERFORMANCE_PX_PER_SEC (31500 * 1000) // k_min +#define PPA_BLEND_TIME_OFFSET (-37150) // b_approx + +#define PPA_FILL_MIN_PERFORMANCE_PX_PER_SEC (150000 * 1000) // k_min +#define PPA_FILL_TIME_OFFSET (-106000) // b_approx +#endif diff --git a/components/esp_driver_ppa/test_apps/main/test_ppa.c b/components/esp_driver_ppa/test_apps/main/test_ppa.c index b1ce989141..5b8dce8b5f 100644 --- a/components/esp_driver_ppa/test_apps/main/test_ppa.c +++ b/components/esp_driver_ppa/test_apps/main/test_ppa.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,6 +17,7 @@ #include "ccomp_timer.h" #include "hal/color_hal.h" #include "esp_cache.h" +#include "ppa_performance.h" #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) @@ -350,6 +351,39 @@ TEST_CASE("ppa_srm_basic_data_correctness_check", "[PPA]") printf("\n"); TEST_ASSERT_EQUAL_UINT8_ARRAY((void *)out_buf_expected, (void *)out_buf, buf_len); +#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3) + // Test a rgb2gray color conversion + memset(out_buf, 0, out_buf_size); + esp_cache_msync((void *)out_buf, out_buf_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M); + + const uint8_t r_weight = 100; + const uint8_t g_weight = 56; + const uint8_t b_weight = 100; + TEST_ESP_OK(ppa_set_rgb2gray_formula(r_weight, g_weight, b_weight)); + oper_config.out.srm_cm = PPA_SRM_COLOR_MODE_GRAY8; + oper_config.rotation_angle = PPA_SRM_ROTATION_ANGLE_0; + uint8_t out_buf_expected_gray[16] = {}; + for (int i = 0; i < block_w * block_h; i++) { + const uint16_t pix = in_buf[(i / block_w + in_block_offset_y) * w + (i % block_w + in_block_offset_x)]; + uint8_t _r = ((pix >> 8) & 0xF8); + uint8_t _g = ((pix >> 3) & 0xFC); + uint8_t _b = ((pix << 3) & 0xF8); + out_buf_expected_gray[(i / block_w + out_block_offset_y) * w + (i % block_w + out_block_offset_x)] = (_r * r_weight + _g * g_weight + _b * b_weight) >> 8; + } + + TEST_ESP_OK(ppa_do_scale_rotate_mirror(ppa_client_handle, &oper_config)); + + // Check result + for (int i = 0; i < w * h; i++) { + if (i % 4 == 0) { + printf("\n"); + } + printf("0x%02X ", out_buf[i]); + } + printf("\n"); + TEST_ASSERT_EQUAL_UINT8_ARRAY((void *)out_buf_expected_gray, (void *)out_buf, w * h); +#endif // !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3) + TEST_ESP_OK(ppa_unregister_client(ppa_client_handle)); free(out_buf); @@ -526,6 +560,20 @@ TEST_CASE("ppa_fill_basic_data_correctness_check", "[PPA]") }; TEST_ASSERT_EACH_EQUAL_UINT16(fill_pixel_expected.val, (void *)((uint32_t)out_buf + w * block_offset_y * out_pixel_depth / 8), block_w * block_h); +#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3) + // Test a yuv color fill + oper_config.out.fill_cm = PPA_FILL_COLOR_MODE_YUV422; // output YUV422 is with YVYU packed order + const color_macroblock_yuv_data_t fill_yuv_color = {.y = 0xFF, .u = 0x55, .v = 0xAA}; + oper_config.fill_yuv_color = fill_yuv_color; + out_pixel_format.color_type_id = PPA_FILL_COLOR_MODE_YUV422; + out_pixel_depth = color_hal_pixel_format_get_bit_depth(out_pixel_format); // bits + TEST_ESP_OK(ppa_do_fill(ppa_client_handle, &oper_config)); + + // Check result (2 pixels per macro pixel) + const uint32_t fill_pixel_expected_yuv422 = ((fill_yuv_color.y << 24) | (fill_yuv_color.v << 16) | (fill_yuv_color.y << 8) | (fill_yuv_color.u)); + TEST_ASSERT_EACH_EQUAL_UINT32(fill_pixel_expected_yuv422, (void *)((uint32_t)out_buf + w * block_offset_y * out_pixel_depth / 8), block_w * block_h / 2); +#endif // !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3) + TEST_ESP_OK(ppa_unregister_client(ppa_client_handle)); free(out_buf); @@ -542,15 +590,6 @@ TEST_CASE("ppa_fill_basic_data_correctness_check", "[PPA]") * k = (T - b) / x */ -#define PPA_SRM_MIN_PERFORMANCE_PX_PER_SEC (21000 * 1000) // k_min -#define PPA_SRM_TIME_OFFSET (-26000) // b_approx - -#define PPA_BLEND_MIN_PERFORMANCE_PX_PER_SEC (31500 * 1000) // k_min -#define PPA_BLEND_TIME_OFFSET (-37150) // b_approx - -#define PPA_FILL_MIN_PERFORMANCE_PX_PER_SEC (150000 * 1000) // k_min -#define PPA_FILL_TIME_OFFSET (-106000) // b_approx - TEST_CASE("ppa_srm_performance", "[PPA]") { // Configurable parameters diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/main/test_app_main.c b/components/esp_driver_sdmmc/test_apps/sdmmc/main/test_app_main.c index 2950ffce24..ab60ea24b8 100644 --- a/components/esp_driver_sdmmc/test_apps/sdmmc/main/test_app_main.c +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/main/test_app_main.c @@ -10,7 +10,7 @@ #include "esp_newlib.h" #include "sdkconfig.h" -#define TEST_MEMORY_LEAK_THRESHOLD (300) +#define TEST_MEMORY_LEAK_THRESHOLD (350) void setUp(void) { diff --git a/components/esp_hw_support/dma/dma2d.c b/components/esp_hw_support/dma/dma2d.c index 86666610a1..bc31ef81b0 100644 --- a/components/esp_hw_support/dma/dma2d.c +++ b/components/esp_hw_support/dma/dma2d.c @@ -23,7 +23,6 @@ #include "hal/dma2d_ll.h" #include "soc/dma2d_channel.h" #include "soc/dma2d_periph.h" -#include "soc/soc_caps.h" #include "esp_bit_defs.h" /** @@ -365,20 +364,20 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl _lock_acquire(&s_platform.mutex); if (!s_platform.groups[group_id]) { dma2d_group_t *pre_alloc_group = heap_caps_calloc(1, sizeof(dma2d_group_t), DMA2D_MEM_ALLOC_CAPS); - dma2d_tx_channel_t *pre_alloc_tx_channels = heap_caps_calloc(SOC_DMA2D_TX_CHANNELS_PER_GROUP, sizeof(dma2d_tx_channel_t), DMA2D_MEM_ALLOC_CAPS); - dma2d_rx_channel_t *pre_alloc_rx_channels = heap_caps_calloc(SOC_DMA2D_RX_CHANNELS_PER_GROUP, sizeof(dma2d_rx_channel_t), DMA2D_MEM_ALLOC_CAPS); + dma2d_tx_channel_t *pre_alloc_tx_channels = heap_caps_calloc(DMA2D_LL_TX_CHANNELS_PER_GROUP, sizeof(dma2d_tx_channel_t), DMA2D_MEM_ALLOC_CAPS); + dma2d_rx_channel_t *pre_alloc_rx_channels = heap_caps_calloc(DMA2D_LL_RX_CHANNELS_PER_GROUP, sizeof(dma2d_rx_channel_t), DMA2D_MEM_ALLOC_CAPS); if (pre_alloc_group && pre_alloc_tx_channels && pre_alloc_rx_channels) { pre_alloc_group->group_id = group_id; pre_alloc_group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; TAILQ_INIT(&pre_alloc_group->pending_trans_tailq); - pre_alloc_group->tx_channel_free_mask = (1 << SOC_DMA2D_TX_CHANNELS_PER_GROUP) - 1; - pre_alloc_group->rx_channel_free_mask = (1 << SOC_DMA2D_RX_CHANNELS_PER_GROUP) - 1; + pre_alloc_group->tx_channel_free_mask = (1 << DMA2D_LL_TX_CHANNELS_PER_GROUP) - 1; + pre_alloc_group->rx_channel_free_mask = (1 << DMA2D_LL_RX_CHANNELS_PER_GROUP) - 1; pre_alloc_group->tx_channel_reserved_mask = dma2d_tx_channel_reserved_mask[group_id]; pre_alloc_group->rx_channel_reserved_mask = dma2d_rx_channel_reserved_mask[group_id]; pre_alloc_group->tx_periph_m2m_free_id_mask = DMA2D_LL_TX_CHANNEL_PERIPH_M2M_AVAILABLE_ID_MASK; pre_alloc_group->rx_periph_m2m_free_id_mask = DMA2D_LL_RX_CHANNEL_PERIPH_M2M_AVAILABLE_ID_MASK; pre_alloc_group->intr_priority = -1; - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { pre_alloc_group->tx_chans[i] = &pre_alloc_tx_channels[i]; dma2d_tx_channel_t *tx_chan = pre_alloc_group->tx_chans[i]; tx_chan->base.group = pre_alloc_group; @@ -386,7 +385,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl tx_chan->base.direction = DMA2D_CHANNEL_DIRECTION_TX; tx_chan->base.spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; } - for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) { pre_alloc_group->rx_chans[i] = &pre_alloc_rx_channels[i]; dma2d_rx_channel_t *rx_chan = pre_alloc_group->rx_chans[i]; rx_chan->base.group = pre_alloc_group; @@ -435,7 +434,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl // Allocate TX and RX interrupts if (s_platform.groups[group_id]) { - for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) { dma2d_rx_channel_t *rx_chan = s_platform.groups[group_id]->rx_chans[i]; if (rx_chan->base.intr == NULL) { ret = esp_intr_alloc_intrstatus(dma2d_periph_signals.groups[group_id].rx_irq_id[i], @@ -450,7 +449,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl } } - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { dma2d_tx_channel_t *tx_chan = s_platform.groups[group_id]->tx_chans[i]; if (tx_chan->base.intr == NULL) { ret = esp_intr_alloc_intrstatus(dma2d_periph_signals.groups[group_id].tx_irq_id[i], @@ -510,12 +509,12 @@ esp_err_t dma2d_release_pool(dma2d_pool_handle_t dma2d_pool) } if (do_deinitialize) { - for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) { if (dma2d_group->rx_chans[i]->base.intr) { esp_intr_free(dma2d_group->rx_chans[i]->base.intr); } } - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { if (dma2d_group->tx_chans[i]->base.intr) { esp_intr_free(dma2d_group->tx_chans[i]->base.intr); } @@ -983,7 +982,7 @@ esp_err_t dma2d_force_end(dma2d_trans_t *trans, bool *need_yield) // Stop the RX channel and its bundled TX channels first dma2d_stop(&rx_chan->base); uint32_t tx_chans = rx_chan->bundled_tx_channel_mask; - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { if (tx_chans & (1 << i)) { dma2d_stop(&group->tx_chans[i]->base); } diff --git a/components/esp_hw_support/dma/dma2d_priv.h b/components/esp_hw_support/dma/dma2d_priv.h index dcf46bf328..074553c052 100644 --- a/components/esp_hw_support/dma/dma2d_priv.h +++ b/components/esp_hw_support/dma/dma2d_priv.h @@ -57,8 +57,8 @@ struct dma2d_group_t { uint8_t rx_channel_reserved_mask; // Bit mask indicating the being reserved RX channels uint32_t tx_periph_m2m_free_id_mask; // Bit mask indicating the available TX M2M peripheral selelction IDs at the moment uint32_t rx_periph_m2m_free_id_mask; // Bit mask indicating the available RX M2M peripheral selelction IDs at the moment - dma2d_tx_channel_t *tx_chans[SOC_DMA2D_TX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA TX channels - dma2d_rx_channel_t *rx_chans[SOC_DMA2D_RX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA RX channels + dma2d_tx_channel_t *tx_chans[DMA2D_LL_TX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA TX channels + dma2d_rx_channel_t *rx_chans[DMA2D_LL_RX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA RX channels int intr_priority; // All channels in the same group should share the same interrupt priority }; diff --git a/components/esp_hw_support/intr_alloc.c b/components/esp_hw_support/intr_alloc.c index ce67ad3cf2..f2e5a5e2c9 100644 --- a/components/esp_hw_support/intr_alloc.c +++ b/components/esp_hw_support/intr_alloc.c @@ -66,7 +66,7 @@ typedef struct vector_desc_t vector_desc_t; struct shared_vector_desc_t { int disabled: 1; - int source: 8; + int source: 16; volatile uint32_t *statusreg; uint32_t statusmask; intr_handler_t isr; @@ -94,7 +94,7 @@ struct vector_desc_t { int flags: 16; //OR of VECDESC_FL_* defines unsigned int cpu: 1; unsigned int intno: 5; - int source: 8; //Interrupt mux flags, used when not shared + int source: 16; //Interrupt mux flags, used when not shared shared_vector_desc_t *shared_vec_info; //used when VECDESC_FL_SHARED vector_desc_t *next; }; diff --git a/components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c b/components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c index 33a49d1a47..931688448e 100644 --- a/components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c +++ b/components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c @@ -22,7 +22,7 @@ // This tests the hardware capability of multiple 2D-DMA transactions running together, and the driver capbility of // transactions being send to a queue, and waiting for free channels becoming available, and being picked to start the // real hardware operation. -#define M2M_TRANS_TIMES (8) +#define M2M_TRANS_TIMES (12) // Descriptor and buffer address and size should aligned to 64 bytes (the cacheline size alignment restriction) to be used by CPU diff --git a/components/esp_system/port/soc/esp32p4/Kconfig.cpu b/components/esp_system/port/soc/esp32p4/Kconfig.cpu index d88464cc99..47064a383a 100644 --- a/components/esp_system/port/soc/esp32p4/Kconfig.cpu +++ b/components/esp_system/port/soc/esp32p4/Kconfig.cpu @@ -14,6 +14,7 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ depends on ESP32P4_SELECTS_REV_LESS_V3 config ESP_DEFAULT_CPU_FREQ_MHZ_400 bool "400 MHz" + depends on !ESP32P4_SELECTS_REV_LESS_V3 endchoice config ESP_DEFAULT_CPU_FREQ_MHZ diff --git a/components/esp_system/port/soc/esp32p4/system_internal.c b/components/esp_system/port/soc/esp32p4/system_internal.c index e9abe6472f..a96eb7e45d 100644 --- a/components/esp_system/port/soc/esp32p4/system_internal.c +++ b/components/esp_system/port/soc/esp32p4/system_internal.c @@ -53,11 +53,11 @@ void esp_system_reset_modules_on_exit(void) } } if (dma2d_ll_is_bus_clock_enabled(0)) { - for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) { dma2d_ll_rx_abort(DMA2D_LL_GET_HW(0), i, true); while (!dma2d_ll_rx_is_reset_avail(DMA2D_LL_GET_HW(0), i)); } - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { dma2d_ll_tx_abort(DMA2D_LL_GET_HW(0), i, true); while (!dma2d_ll_tx_is_reset_avail(DMA2D_LL_GET_HW(0), i)); } diff --git a/components/hal/esp32p4/include/hal/dma2d_ll.h b/components/hal/esp32p4/include/hal/dma2d_ll.h index f36fcdd433..8c0fab8884 100644 --- a/components/hal/esp32p4/include/hal/dma2d_ll.h +++ b/components/hal/esp32p4/include/hal/dma2d_ll.h @@ -11,8 +11,10 @@ #include "hal/dma2d_types.h" #include "soc/dma2d_channel.h" #include "soc/dma2d_struct.h" +#include "soc/soc_caps.h" #include "hal/misc.h" #include "hal/assert.h" +#include "hal/config.h" #include "soc/soc.h" #include "soc/hp_sys_clkrst_struct.h" @@ -22,6 +24,14 @@ extern "C" { #define DMA2D_LL_GET_HW(id) (((id) == 0) ? (&DMA2D) : NULL) +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +#define DMA2D_LL_TX_CHANNELS_PER_GROUP SOC_DMA2D_TX_CHANNELS_PER_GROUP // Number of 2D-DMA TX (OUT) channels in each group +#define DMA2D_LL_RX_CHANNELS_PER_GROUP SOC_DMA2D_RX_CHANNELS_PER_GROUP // Number of 2D-DMA RX (IN) channels in each group +#else +#define DMA2D_LL_TX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA TX (OUT) channels in each group +#define DMA2D_LL_RX_CHANNELS_PER_GROUP (2) // Number of 2D-DMA RX (IN) channels in each group +#endif + // 2D-DMA interrupts #define DMA2D_LL_RX_EVENT_MASK (0x3FFF) #define DMA2D_LL_TX_EVENT_MASK (0x1FFF) @@ -57,8 +67,11 @@ extern "C" { // Bit masks that are used to indicate availability of some sub-features in the channels #define DMA2D_LL_TX_CHANNEL_SUPPORT_RO_MASK (0U | BIT0) // TX channels that support reorder feature +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +#define DMA2D_LL_TX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0 | BIT1 | BIT2 | BIT3) // TX channels that support color space conversion feature +#else #define DMA2D_LL_TX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0 | BIT1 | BIT2) // TX channels that support color space conversion feature - +#endif #define DMA2D_LL_RX_CHANNEL_SUPPORT_RO_MASK (0U | BIT0) // RX channels that support reorder feature #define DMA2D_LL_RX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0) // RX channels that support color space conversion feature @@ -158,16 +171,13 @@ static inline uint32_t dma2d_ll_get_scramble_order_sel(dma2d_scramble_order_t or } /////////////////////////////////////// RX /////////////////////////////////////////// -#define DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, ch, reg) ((volatile void*[]){&dev->in_channel0.reg, &dev->in_channel1.reg}[(ch)]) - /** * @brief Get 2D-DMA RX channel interrupt status word */ __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_interrupt_status(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_int_st_chn_reg_t *reg = (volatile dma2d_in_int_st_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_st); - return reg->val; + return dev->in_channel[channel].in_int_st.val & DMA2D_LL_RX_EVENT_MASK; } /** @@ -176,11 +186,10 @@ static inline uint32_t dma2d_ll_rx_get_interrupt_status(dma2d_dev_t *dev, uint32 __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_interrupt(dma2d_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) { - volatile dma2d_in_int_ena_chn_reg_t *reg = (volatile dma2d_in_int_ena_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_ena); if (enable) { - reg->val = reg->val | (mask & DMA2D_LL_RX_EVENT_MASK); + dev->in_channel[channel].in_int_ena.val = dev->in_channel[channel].in_int_ena.val | (mask & DMA2D_LL_RX_EVENT_MASK); } else { - reg->val = reg->val & ~(mask & DMA2D_LL_RX_EVENT_MASK); + dev->in_channel[channel].in_int_ena.val = dev->in_channel[channel].in_int_ena.val & ~(mask & DMA2D_LL_RX_EVENT_MASK); } } @@ -190,8 +199,7 @@ static inline void dma2d_ll_rx_enable_interrupt(dma2d_dev_t *dev, uint32_t chann __attribute__((always_inline)) static inline void dma2d_ll_rx_clear_interrupt_status(dma2d_dev_t *dev, uint32_t channel, uint32_t mask) { - volatile dma2d_in_int_clr_chn_reg_t *reg = (volatile dma2d_in_int_clr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_clr); - reg->val = (mask & DMA2D_LL_RX_EVENT_MASK); + dev->in_channel[channel].in_int_clr.val = (mask & DMA2D_LL_RX_EVENT_MASK); } /** @@ -199,7 +207,7 @@ static inline void dma2d_ll_rx_clear_interrupt_status(dma2d_dev_t *dev, uint32_t */ static inline volatile void *dma2d_ll_rx_get_interrupt_status_reg(dma2d_dev_t *dev, uint32_t channel) { - return (volatile void *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_st); + return (volatile void *)(&dev->in_channel[channel].in_int_st); } /** @@ -208,8 +216,7 @@ static inline volatile void *dma2d_ll_rx_get_interrupt_status_reg(dma2d_dev_t *d __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_owner_check(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_check_owner_chn = enable; + dev->in_channel[channel].in_conf0.in_check_owner_chn = enable; } /** @@ -218,8 +225,7 @@ static inline void dma2d_ll_rx_enable_owner_check(dma2d_dev_t *dev, uint32_t cha __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_page_bound_wrap(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_page_bound_en_chn = enable; + dev->in_channel[channel].in_conf0.in_page_bound_en_chn = enable; } /** @@ -249,8 +255,7 @@ static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t // Unsupported data burst length abort(); } - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_mem_burst_length_chn = sel; + dev->in_channel[channel].in_conf0.in_mem_burst_length_chn = sel; } /** @@ -259,8 +264,7 @@ static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_descriptor_burst(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->indscr_burst_en_chn = enable; + dev->in_channel[channel].in_conf0.indscr_burst_en_chn = enable; } /** @@ -269,9 +273,8 @@ static inline void dma2d_ll_rx_enable_descriptor_burst(dma2d_dev_t *dev, uint32_ __attribute__((always_inline)) static inline void dma2d_ll_rx_reset_channel(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_rst_chn = 1; - reg->in_rst_chn = 0; + dev->in_channel[channel].in_conf0.in_rst_chn = 1; + dev->in_channel[channel].in_conf0.in_rst_chn = 0; } /** @@ -280,8 +283,7 @@ static inline void dma2d_ll_rx_reset_channel(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline bool dma2d_ll_rx_is_reset_avail(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_state_chn_reg_t *reg = (volatile dma2d_in_state_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_state); - return reg->in_reset_avail_chn; + return dev->in_channel[channel].in_state.in_reset_avail_chn; } /** @@ -290,8 +292,7 @@ static inline bool dma2d_ll_rx_is_reset_avail(dma2d_dev_t *dev, uint32_t channel __attribute__((always_inline)) static inline void dma2d_ll_rx_abort(dma2d_dev_t *dev, uint32_t channel, bool disable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_cmd_disable_chn = disable; + dev->in_channel[channel].in_conf0.in_cmd_disable_chn = disable; } /** @@ -300,8 +301,7 @@ static inline void dma2d_ll_rx_abort(dma2d_dev_t *dev, uint32_t channel, bool di __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_dscr_port(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_dscr_port_en_chn = enable; + dev->in_channel[channel].in_conf0.in_dscr_port_en_chn = enable; } /** @@ -328,8 +328,7 @@ static inline void dma2d_ll_rx_set_macro_block_size(dma2d_dev_t *dev, uint32_t c // Unsupported macro block size abort(); } - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_macro_block_size_chn = sel; + dev->in_channel[channel].in_conf0.in_macro_block_size_chn = sel; } /** @@ -338,9 +337,8 @@ static inline void dma2d_ll_rx_set_macro_block_size(dma2d_dev_t *dev, uint32_t c __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_pop_data(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_pop_chn_reg_t *reg = (volatile dma2d_in_pop_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_pop); - reg->infifo_pop_chn = 1; - return reg->infifo_rdata_chn; + dev->in_channel[channel].in_pop.infifo_pop_chn = 1; + return dev->in_channel[channel].in_pop.infifo_rdata_chn; } /** @@ -349,8 +347,7 @@ static inline uint32_t dma2d_ll_rx_pop_data(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline void dma2d_ll_rx_set_desc_addr(dma2d_dev_t *dev, uint32_t channel, uint32_t addr) { - volatile dma2d_in_link_addr_chn_reg_t *reg = (volatile dma2d_in_link_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_addr); - reg->inlink_addr_chn = addr; + dev->in_channel[channel].in_link_addr.inlink_addr_chn = addr; } /** @@ -359,8 +356,7 @@ static inline void dma2d_ll_rx_set_desc_addr(dma2d_dev_t *dev, uint32_t channel, __attribute__((always_inline)) static inline void dma2d_ll_rx_start(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - reg->inlink_start_chn = 1; + dev->in_channel[channel].in_link_conf.inlink_start_chn = 1; } /** @@ -369,8 +365,7 @@ static inline void dma2d_ll_rx_start(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline void dma2d_ll_rx_stop(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - reg->inlink_stop_chn = 1; + dev->in_channel[channel].in_link_conf.inlink_stop_chn = 1; } /** @@ -379,8 +374,7 @@ static inline void dma2d_ll_rx_stop(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline void dma2d_ll_rx_restart(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - reg->inlink_restart_chn = 1; + dev->in_channel[channel].in_link_conf.inlink_restart_chn = 1; } /** @@ -389,8 +383,7 @@ static inline void dma2d_ll_rx_restart(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline void dma2d_ll_rx_set_auto_return_owner(dma2d_dev_t *dev, uint32_t channel, int owner) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - reg->inlink_auto_ret_chn = owner; + dev->in_channel[channel].in_link_conf.inlink_auto_ret_chn = owner; } /** @@ -399,8 +392,7 @@ static inline void dma2d_ll_rx_set_auto_return_owner(dma2d_dev_t *dev, uint32_t __attribute__((always_inline)) static inline bool dma2d_ll_rx_is_desc_fsm_idle(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - return reg->inlink_park_chn; + return dev->in_channel[channel].in_link_conf.inlink_park_chn; } /** @@ -409,8 +401,7 @@ static inline bool dma2d_ll_rx_is_desc_fsm_idle(dma2d_dev_t *dev, uint32_t chann __attribute__((always_inline)) static inline bool dma2d_ll_rx_is_fsm_idle(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_state_chn_reg_t *reg = (volatile dma2d_in_state_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_state); - return (reg->in_state_chn == 0); + return (dev->in_channel[channel].in_state.in_state_chn == 0); } /** @@ -419,8 +410,7 @@ static inline bool dma2d_ll_rx_is_fsm_idle(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_success_eof_desc_addr(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_suc_eof_des_addr_chn_reg_t *reg = (volatile dma2d_in_suc_eof_des_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_suc_eof_des_addr); - return reg->val; + return dev->in_channel[channel].in_suc_eof_des_addr.val; } /** @@ -429,8 +419,7 @@ static inline uint32_t dma2d_ll_rx_get_success_eof_desc_addr(dma2d_dev_t *dev, u __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_error_eof_desc_addr(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_err_eof_des_addr_chn_reg_t *reg = (volatile dma2d_in_err_eof_des_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_err_eof_des_addr); - return reg->val; + return dev->in_channel[channel].in_err_eof_des_addr.val; } /** @@ -439,18 +428,7 @@ static inline uint32_t dma2d_ll_rx_get_error_eof_desc_addr(dma2d_dev_t *dev, uin __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_prefetched_desc_addr(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_dscr_chn_reg_t *reg = (volatile dma2d_in_dscr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_dscr); - return reg->val; -} - -/** - * @brief Set priority for 2D-DMA RX channel - */ -__attribute__((always_inline)) -static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t prio) -{ - volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb); - reg->in_arb_priority_chn = prio; + return dev->in_channel[channel].in_dscr.val; } /** @@ -459,10 +437,8 @@ static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, __attribute__((always_inline)) static inline void dma2d_ll_rx_connect_to_periph(dma2d_dev_t *dev, uint32_t channel, dma2d_trigger_peripheral_t periph, int periph_id) { - volatile dma2d_in_peri_sel_chn_reg_t *peri_sel_reg = (volatile dma2d_in_peri_sel_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_peri_sel); - peri_sel_reg->in_peri_sel_chn = periph_id; - volatile dma2d_in_conf0_chn_reg_t *conf0_reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - conf0_reg->in_mem_trans_en_chn = (periph == DMA2D_TRIG_PERIPH_M2M); + dev->in_channel[channel].in_peri_sel.in_peri_sel_chn = periph_id; + dev->in_channel[channel].in_conf0.in_mem_trans_en_chn = (periph == DMA2D_TRIG_PERIPH_M2M); } /** @@ -471,10 +447,8 @@ static inline void dma2d_ll_rx_connect_to_periph(dma2d_dev_t *dev, uint32_t chan __attribute__((always_inline)) static inline void dma2d_ll_rx_disconnect_from_periph(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_peri_sel_chn_reg_t *peri_sel_reg = (volatile dma2d_in_peri_sel_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_peri_sel); - peri_sel_reg->in_peri_sel_chn = DMA2D_LL_CHANNEL_PERIPH_NO_CHOICE; - volatile dma2d_in_conf0_chn_reg_t *conf0_reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - conf0_reg->in_mem_trans_en_chn = false; + dev->in_channel[channel].in_peri_sel.in_peri_sel_chn = DMA2D_LL_CHANNEL_PERIPH_NO_CHOICE; + dev->in_channel[channel].in_conf0.in_mem_trans_en_chn = false; } // REORDER FUNCTION (Only CH0 supports this feature) @@ -485,8 +459,7 @@ static inline void dma2d_ll_rx_disconnect_from_periph(dma2d_dev_t *dev, uint32_t __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_reorder(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_reorder_en_chn = enable; + dev->in_channel[channel].in_conf0.in_reorder_en_chn = enable; } // COLOR SPACE CONVERSION FUNCTION @@ -524,6 +497,17 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint proc_en = false; output_sel = 1; break; + case DMA2D_CSC_RX_YUV444_TO_YUV422: + input_sel = 0; + proc_en = false; + output_sel = 2; + break; + case DMA2D_CSC_RX_YUV444_TO_YUV420: + case DMA2D_CSC_RX_YUV422_TO_YUV420: + input_sel = 0; + proc_en = false; + output_sel = 3; + break; case DMA2D_CSC_RX_YUV420_TO_RGB888_601: case DMA2D_CSC_RX_YUV422_TO_RGB888_601: input_sel = 0; @@ -581,13 +565,13 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint abort(); } - dev->in_channel0.in_color_convert.in_color_input_sel_chn = input_sel; - dev->in_channel0.in_color_convert.in_color_3b_proc_en_chn = proc_en; - dev->in_channel0.in_color_convert.in_color_output_sel_chn = output_sel; + dev->in_channel[channel].in_color_convert.in_color_input_sel_chn = input_sel; + dev->in_channel[channel].in_color_convert.in_color_3b_proc_en_chn = proc_en; + dev->in_channel[channel].in_color_convert.in_color_output_sel_chn = output_sel; if (proc_en) { HAL_ASSERT(table); - typeof(dev->in_channel0.in_color_param_group) color_param_group; + typeof(dev->in_channel[channel].in_color_param_group) color_param_group; color_param_group.param_h.a = table[0][0]; color_param_group.param_h.b = table[0][1]; @@ -604,12 +588,12 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint color_param_group.param_l.c = table[2][2]; color_param_group.param_l.d = table[2][3]; - dev->in_channel0.in_color_param_group.param_h.val[0] = color_param_group.param_h.val[0]; - dev->in_channel0.in_color_param_group.param_h.val[1] = color_param_group.param_h.val[1]; - dev->in_channel0.in_color_param_group.param_m.val[0] = color_param_group.param_m.val[0]; - dev->in_channel0.in_color_param_group.param_m.val[1] = color_param_group.param_m.val[1]; - dev->in_channel0.in_color_param_group.param_l.val[0] = color_param_group.param_l.val[0]; - dev->in_channel0.in_color_param_group.param_l.val[1] = color_param_group.param_l.val[1]; + dev->in_channel[channel].in_color_param_group.param_h.val[0] = color_param_group.param_h.val[0]; + dev->in_channel[channel].in_color_param_group.param_h.val[1] = color_param_group.param_h.val[1]; + dev->in_channel[channel].in_color_param_group.param_m.val[0] = color_param_group.param_m.val[0]; + dev->in_channel[channel].in_color_param_group.param_m.val[1] = color_param_group.param_m.val[1]; + dev->in_channel[channel].in_color_param_group.param_l.val[0] = color_param_group.param_l.val[0]; + dev->in_channel[channel].in_color_param_group.param_l.val[1] = color_param_group.param_l.val[1]; } } @@ -620,7 +604,7 @@ __attribute__((always_inline)) static inline void dma2d_ll_rx_set_csc_pre_scramble(dma2d_dev_t *dev, uint32_t channel, dma2d_scramble_order_t order) { HAL_ASSERT(channel == 0); // Only channel 0 supports scramble - dev->in_channel0.in_scramble.in_scramble_sel_pre_chn = dma2d_ll_get_scramble_order_sel(order); + dev->in_channel[channel].in_scramble.in_scramble_sel_pre_chn = dma2d_ll_get_scramble_order_sel(order); } /** @@ -630,7 +614,7 @@ __attribute__((always_inline)) static inline void dma2d_ll_rx_set_csc_post_scramble(dma2d_dev_t *dev, uint32_t channel, dma2d_scramble_order_t order) { HAL_ASSERT(channel == 0); // Only channel 0 supports scramble - dev->in_channel0.in_scramble.in_scramble_sel_post_chn = dma2d_ll_get_scramble_order_sel(order); + dev->in_channel[channel].in_scramble.in_scramble_sel_post_chn = dma2d_ll_get_scramble_order_sel(order); } // Arbiter @@ -659,8 +643,7 @@ static inline void dma2d_ll_rx_set_arb_timeout(dma2d_dev_t *dev, uint32_t timeou __attribute__((always_inline)) static inline void dma2d_ll_rx_set_arb_token_num(dma2d_dev_t *dev, uint32_t channel, uint32_t token_num) { - volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb); - reg->in_arb_token_num_chn = token_num; + dev->in_channel[channel].in_arb.in_arb_token_num_chn = token_num; } /** @@ -669,20 +652,22 @@ static inline void dma2d_ll_rx_set_arb_token_num(dma2d_dev_t *dev, uint32_t chan __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_arb_token_num(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb); - return reg->in_arb_token_num_chn; + return dev->in_channel[channel].in_arb.in_arb_token_num_chn; } /** - * @brief Set 2D-DMA RX channel arbiter priority + * @brief Set priority for 2D-DMA RX channel */ __attribute__((always_inline)) -static inline void dma2d_ll_rx_set_arb_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority) +static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority) { - volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb); - reg->in_arb_priority_chn = priority; + dev->in_channel[channel].in_arb.in_arb_priority_chn = priority; } +// ETM + +// note that in_ch1 in_etm_conf register addr is different before and after rev3 chip! + /////////////////////////////////////// TX /////////////////////////////////////////// /** * @brief Get 2D-DMA TX channel interrupt status word @@ -954,15 +939,6 @@ static inline uint32_t dma2d_ll_tx_get_prefetched_desc_addr(dma2d_dev_t *dev, ui return dev->out_channel[channel].out_dscr.val; } -/** - * @brief Set priority for 2D-DMA TX channel - */ -__attribute__((always_inline)) -static inline void dma2d_ll_tx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t prio) -{ - dev->out_channel[channel].out_arb.out_arb_priority_chn = prio; -} - /** * @brief Connect 2D-DMA TX channel to a given peripheral */ @@ -1165,10 +1141,10 @@ static inline uint32_t dma2d_ll_tx_get_arb_token_num(dma2d_dev_t *dev, uint32_t } /** - * @brief Set 2D-DMA TX channel arbiter priority + * @brief Set priority for 2D-DMA TX channel */ __attribute__((always_inline)) -static inline void dma2d_ll_tx_set_arb_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority) +static inline void dma2d_ll_tx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority) { dev->out_channel[channel].out_arb.out_arb_priority_chn = priority; } diff --git a/components/hal/esp32p4/include/hal/ledc_ll.h b/components/hal/esp32p4/include/hal/ledc_ll.h index 1f25865572..0876a928f0 100644 --- a/components/hal/esp32p4/include/hal/ledc_ll.h +++ b/components/hal/esp32p4/include/hal/ledc_ll.h @@ -245,7 +245,6 @@ static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_m static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src) { // The target has no timer-specific clock source option - HAL_ASSERT(hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel == 0); *clk_src = LEDC_SCLK; } @@ -365,7 +364,7 @@ static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_m */ static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *duty_val) { - *duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_r.duty >> 4); + *duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_r.duty_r >> 4); } /** @@ -406,7 +405,7 @@ static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t spee */ static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t range_num) { - hw->chn_gamma_conf[channel_num].ch0_gamma_entry_num = range_num; + hw->chn_gamma_conf[channel_num].gamma_entry_num = range_num; } /** @@ -421,7 +420,7 @@ static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mo */ static inline void ledc_ll_get_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *range_num) { - *range_num = hw->chn_gamma_conf[channel_num].ch0_gamma_entry_num; + *range_num = hw->chn_gamma_conf[channel_num].gamma_entry_num; } /** diff --git a/components/hal/esp32p4/include/hal/ppa_ll.h b/components/hal/esp32p4/include/hal/ppa_ll.h index 1d82fdce92..d20cf73ad4 100644 --- a/components/hal/esp32p4/include/hal/ppa_ll.h +++ b/components/hal/esp32p4/include/hal/ppa_ll.h @@ -14,6 +14,7 @@ #include "soc/hp_sys_clkrst_struct.h" #include "hal/assert.h" #include "hal/misc.h" +#include "hal/config.h" #ifdef __cplusplus extern "C" { @@ -27,9 +28,15 @@ extern "C" { #define PPA_LL_SRM_SCALING_INT_MAX (PPA_SR_SCAL_X_INT_V + 1) #define PPA_LL_SRM_SCALING_FRAG_MAX (PPA_SR_SCAL_X_FRAG_V + 1) -// TODO: On P4 ECO2, SRM block size needs update -#define PPA_LL_SRM_DEFAULT_BLOCK_SIZE 18 // 18 x 18 block size -#define PPA_LL_SRM_YUV420_BLOCK_SIZE 20 // 20 x 20 block size +/** + * @brief Enumeration of PPA SRM macro block size options + */ +typedef enum { + PPA_LL_SRM_MB_SIZE_16_16, /*!< SRM engine processes with a macro block size of 16 x 16 */ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + PPA_LL_SRM_MB_SIZE_32_32, /*!< SRM engine processes with a macro block size of 32 x 32 */ +#endif +} ppa_ll_srm_mb_size_t; /** * @brief Enumeration of PPA blending mode @@ -68,6 +75,29 @@ static inline void ppa_ll_reset_register(void) /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance #define ppa_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; ppa_ll_reset_register(__VA_ARGS__) +/** + * @brief Configure the RGB888 to GRAY8 color conversion coefficients for SRM and Blending (excluding Fill) + * + * The gray value is calculated as: gray = (r_coeff * R + g_coeff * G + b_coeff * B) >> 8 + * + * @param dev Peripheral instance address + * @param r_coeff Coefficient for Red channel, range 0-255 + * @param g_coeff Coefficient for Green channel, range 0-255 + * @param b_coeff Coefficient for Blue channel, range 0-255 + */ +static inline void ppa_ll_set_rgb2gray_coeff(ppa_dev_t *dev, uint8_t r_coeff, uint8_t g_coeff, uint8_t b_coeff) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + HAL_ASSERT((r_coeff + g_coeff + b_coeff == 256) && "Sum of RGB to GRAY coefficients must be 256"); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_r, r_coeff); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_g, g_coeff); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_b, b_coeff); +#else + // GRAY8 color mode is not supported by PPA hardware before P4 ECO5 + abort(); +#endif +} + ///////////////////////// Scaling, Rotating, Mirroring (SRM) ////////////////////////////// /** * @brief Reset PPA scaling-rotating-mirroring engine @@ -169,6 +199,30 @@ static inline void ppa_ll_srm_start(ppa_dev_t *dev) dev->sr_scal_rotate.scal_rotate_start = 1; } +/** + * @brief Check if the given color mode is supported by PPA SRM engine + * + * @param color_mode One of the values in ppa_srm_color_mode_t + * @return true if supported; false if not supported + */ +static inline bool ppa_ll_srm_is_color_mode_supported(ppa_srm_color_mode_t color_mode) +{ + switch (color_mode) { + case PPA_SRM_COLOR_MODE_ARGB8888: + case PPA_SRM_COLOR_MODE_RGB888: + case PPA_SRM_COLOR_MODE_RGB565: + case PPA_SRM_COLOR_MODE_YUV420: + case PPA_SRM_COLOR_MODE_YUV444: // YUV444 not supported by PPA hardware, but can be converted by 2D-DMA before/after PPA +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_SRM_COLOR_MODE_YUV422: + case PPA_SRM_COLOR_MODE_GRAY8: +#endif + return true; + default: + return false; + } +} + /** * @brief Set the source image color mode for PPA Scaling-Rotating-Mirroring engine RX * @@ -191,6 +245,14 @@ static inline void ppa_ll_srm_set_rx_color_mode(ppa_dev_t *dev, ppa_srm_color_mo case PPA_SRM_COLOR_MODE_YUV420: val = 8; break; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_SRM_COLOR_MODE_YUV422: + val = 9; + break; + case PPA_SRM_COLOR_MODE_GRAY8: + val = 12; + break; +#endif default: // Unsupported SRM rx color mode abort(); @@ -220,6 +282,14 @@ static inline void ppa_ll_srm_set_tx_color_mode(ppa_dev_t *dev, ppa_srm_color_mo case PPA_SRM_COLOR_MODE_YUV420: val = 8; break; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_SRM_COLOR_MODE_YUV422: + val = 9; + break; + case PPA_SRM_COLOR_MODE_GRAY8: + val = 12; + break; +#endif default: // Unsupported SRM tx color mode abort(); @@ -311,6 +381,38 @@ static inline void ppa_ll_srm_set_tx_yuv_range(ppa_dev_t *dev, ppa_color_range_t } } +/** + * @brief Set PPA SRM input side YUV422 data format packing order + * + * @param dev Peripheral instance address + * @param pack_order One of the pack order options in color_yuv422_pack_order_t + */ +static inline void ppa_ll_srm_set_rx_yuv422_pack_order(ppa_dev_t *dev, color_yuv422_pack_order_t pack_order) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (pack_order) { + case COLOR_YUV422_PACK_ORDER_YVYU: + dev->sr_color_mode.yuv422_rx_byte_order = 0; + break; + case COLOR_YUV422_PACK_ORDER_YUYV: + dev->sr_color_mode.yuv422_rx_byte_order = 1; + break; + case COLOR_YUV422_PACK_ORDER_VYUY: + dev->sr_color_mode.yuv422_rx_byte_order = 2; + break; + case COLOR_YUV422_PACK_ORDER_UYVY: + dev->sr_color_mode.yuv422_rx_byte_order = 3; + break; + default: + // Unsupported YUV422 pack order + abort(); + } +#else + // YUV422 not supported by PPA SRM hardware before P4 ECO5 + abort(); +#endif +} + /** * @brief Enable PPA SRM input data swap in RGB (e.g. ARGB becomes BGRA, RGB becomes BGR) * @@ -371,6 +473,112 @@ static inline void ppa_ll_srm_configure_rx_alpha(ppa_dev_t *dev, ppa_alpha_updat } } +/** + * @brief Get the current configured PPA SRM macro block size + * + * @param dev Peripheral instance address + * @return The current configured macro block size, one of the values in ppa_ll_srm_mb_size_t + */ +static inline ppa_ll_srm_mb_size_t ppa_ll_srm_get_mb_size(ppa_dev_t *dev) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + return (dev->sr_byte_order.sr_bk_size_sel == 0) ? PPA_LL_SRM_MB_SIZE_32_32 : PPA_LL_SRM_MB_SIZE_16_16; +#else + return PPA_LL_SRM_MB_SIZE_16_16; +#endif +} + +/** + * @brief Set PPA SRM macro block size + * + * @param dev Peripheral instance address + * @param mb_size Macro block size to be set, one of the values in ppa_ll_srm_mb_size_t + */ +static inline void ppa_ll_srm_set_mb_size(ppa_dev_t *dev, ppa_ll_srm_mb_size_t mb_size) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (mb_size) { + case PPA_LL_SRM_MB_SIZE_16_16: + dev->sr_byte_order.sr_bk_size_sel = 1; + break; + case PPA_LL_SRM_MB_SIZE_32_32: + dev->sr_byte_order.sr_bk_size_sel = 0; + break; + default: + // Unsupported SRM macro block size + abort(); + } +#else + HAL_ASSERT(mb_size == PPA_LL_SRM_MB_SIZE_16_16); +#endif +} + +/** + * @brief Retrieve the 2D-DMA descriptor port mode block size (in pixel) according to the PPA SRM input color mode and configured macro block size + * + * @param dev Peripheral instance address + * @param in_color_mode Input color mode, one of the values in ppa_srm_color_mode_t + * @param mb_size SRM macro block size, one of the values in ppa_ll_srm_mb_size_t + * @param[out] block_h Returned block horizontal width + * @param[out] block_v Returned block wvertical height + */ +static inline void ppa_ll_srm_get_dma_dscr_port_mode_block_size(ppa_dev_t *dev, ppa_srm_color_mode_t in_color_mode, ppa_ll_srm_mb_size_t mb_size, uint32_t *block_h, uint32_t *block_v) +{ + if (mb_size == PPA_LL_SRM_MB_SIZE_16_16) { + switch (in_color_mode) { + case PPA_SRM_COLOR_MODE_ARGB8888: + case PPA_SRM_COLOR_MODE_RGB888: + case PPA_SRM_COLOR_MODE_RGB565: + case PPA_SRM_COLOR_MODE_GRAY8: + *block_h = 18; + *block_v = 18; + break; + case PPA_SRM_COLOR_MODE_YUV420: + *block_h = 20; + *block_v = 18; + break; + case PPA_SRM_COLOR_MODE_YUV422: + *block_h = 20; + *block_v = 20; + break; + default: + // Unsupported SRM input color mode + *block_h = 0; + *block_v = 0; + } + } +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + else if (mb_size == PPA_LL_SRM_MB_SIZE_32_32) { + switch (in_color_mode) { + case PPA_SRM_COLOR_MODE_ARGB8888: + case PPA_SRM_COLOR_MODE_RGB888: + case PPA_SRM_COLOR_MODE_RGB565: + case PPA_SRM_COLOR_MODE_GRAY8: + *block_h = 34; + *block_v = 34; + break; + case PPA_SRM_COLOR_MODE_YUV420: + *block_h = 36; + *block_v = 34; + break; + case PPA_SRM_COLOR_MODE_YUV422: + *block_h = 36; + *block_v = 36; + break; + default: + // Unsupported SRM input color mode + *block_h = 0; + *block_v = 0; + } + } +#endif + else { + // Unsupported SRM macro block size + *block_h = 0; + *block_v = 0; + } +} + //////////////////////////////////// Blending //////////////////////////////////////// /* * Alpha Blending Calculation: @@ -420,6 +628,33 @@ static inline void ppa_ll_blend_start(ppa_dev_t *dev, ppa_ll_blend_trans_mode_t dev->blend_trans_mode.blend_trans_mode_update = 1; } +/** + * @brief Check if the given color mode is supported by PPA blending engine + * + * @param color_mode One of the values in ppa_blend_color_mode_t + * @return true if supported (by any of rx_bg, rx_fg, tx); false if not supported + */ +static inline bool ppa_ll_blend_is_color_mode_supported(ppa_blend_color_mode_t color_mode) +{ + switch (color_mode) { + case PPA_BLEND_COLOR_MODE_ARGB8888: + case PPA_BLEND_COLOR_MODE_RGB888: + case PPA_BLEND_COLOR_MODE_RGB565: + case PPA_BLEND_COLOR_MODE_A8: + case PPA_BLEND_COLOR_MODE_A4: + // case PPA_BLEND_COLOR_MODE_L8: + // case PPA_BLEND_COLOR_MODE_L4: +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_BLEND_COLOR_MODE_YUV420: + case PPA_BLEND_COLOR_MODE_YUV422: + case PPA_BLEND_COLOR_MODE_GRAY8: +#endif + return true; + default: + return false; + } +} + /** * @brief Set the source image color mode for background for PPA blending engine RX * @@ -445,6 +680,17 @@ static inline void ppa_ll_blend_set_rx_bg_color_mode(ppa_dev_t *dev, ppa_blend_c // case PPA_BLEND_COLOR_MODE_L4: // val = 5; // break; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_BLEND_COLOR_MODE_YUV420: + val = 8; + break; + case PPA_BLEND_COLOR_MODE_YUV422: + val = 9; + break; + case PPA_BLEND_COLOR_MODE_GRAY8: + val = 12; + break; +#endif default: // Unsupported blending rx background color mode abort(); @@ -509,6 +755,17 @@ static inline void ppa_ll_blend_set_tx_color_mode(ppa_dev_t *dev, ppa_blend_colo case PPA_BLEND_COLOR_MODE_RGB565: val = 2; break; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_BLEND_COLOR_MODE_YUV420: + val = 8; + break; + case PPA_BLEND_COLOR_MODE_YUV422: + val = 9; + break; + case PPA_BLEND_COLOR_MODE_GRAY8: + val = 12; + break; +#endif default: // Unsupported blending tx color mode abort(); @@ -516,6 +773,142 @@ static inline void ppa_ll_blend_set_tx_color_mode(ppa_dev_t *dev, ppa_blend_colo dev->blend_color_mode.blend_tx_cm = val; } +/** + * @brief Set YUV to RGB protocol when PPA blending source image background pixel color space is YUV + * + * @param dev Peripheral instance address + * @param std One of the RGB-YUV conversion standards in ppa_color_conv_std_rgb_yuv_t + */ +static inline void ppa_ll_blend_set_rx_bg_yuv2rgb_std(ppa_dev_t *dev, ppa_color_conv_std_rgb_yuv_t std) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (std) { + case PPA_COLOR_CONV_STD_RGB_YUV_BT601: + dev->blend_color_mode.blend0_rx_yuv2rgb_protocol = 0; + break; + case PPA_COLOR_CONV_STD_RGB_YUV_BT709: + dev->blend_color_mode.blend0_rx_yuv2rgb_protocol = 1; + break; + default: + // Unsupported RGB-YUV conversion standard + abort(); + } +#else + // YUV not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + +/** + * @brief Set RGB to YUV protocol when PPA blending destination image pixel color space is YUV + * + * @param dev Peripheral instance address + * @param std One of the RGB-YUV conversion standards in ppa_color_conv_std_rgb_yuv_t + */ +static inline void ppa_ll_blend_set_tx_rgb2yuv_std(ppa_dev_t *dev, ppa_color_conv_std_rgb_yuv_t std) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (std) { + case PPA_COLOR_CONV_STD_RGB_YUV_BT601: + dev->blend_color_mode.blend_tx_rgb2yuv_protocol = 0; + break; + case PPA_COLOR_CONV_STD_RGB_YUV_BT709: + dev->blend_color_mode.blend_tx_rgb2yuv_protocol = 1; + break; + default: + // Unsupported RGB-YUV conversion standard + abort(); + } +#else + // YUV not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + +/** + * @brief Set PPA blending source image background YUV input range + * + * @param dev Peripheral instance address + * @param range One of color range options in ppa_color_range_t + */ +static inline void ppa_ll_blend_set_rx_bg_yuv_range(ppa_dev_t *dev, ppa_color_range_t range) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (range) { + case PPA_COLOR_RANGE_LIMIT: + dev->blend_color_mode.blend0_rx_yuv_range = 0; + break; + case PPA_COLOR_RANGE_FULL: + dev->blend_color_mode.blend0_rx_yuv_range = 1; + break; + default: + // Unsupported color range + abort(); + } +#else + // YUV not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + +/** + * @brief Set PPA blending destination image YUV output range + * + * @param dev Peripheral instance address + * @param range One of color range options in ppa_color_range_t + */ +static inline void ppa_ll_blend_set_tx_yuv_range(ppa_dev_t *dev, ppa_color_range_t range) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (range) { + case PPA_COLOR_RANGE_LIMIT: + dev->blend_color_mode.blend_tx_yuv_range = 0; + break; + case PPA_COLOR_RANGE_FULL: + dev->blend_color_mode.blend_tx_yuv_range = 1; + break; + default: + // Unsupported color range + abort(); + } +#else + // YUV not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + +/** + * @brief Set PPA blending source image background YUV422 data format packing order + * + * @param dev Peripheral instance address + * @param pack_order One of the pack order options in color_yuv422_pack_order_t + */ +static inline void ppa_ll_blend_set_rx_bg_yuv422_pack_order(ppa_dev_t *dev, color_yuv422_pack_order_t pack_order) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (pack_order) { + case COLOR_YUV422_PACK_ORDER_YVYU: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 0; + break; + case COLOR_YUV422_PACK_ORDER_YUYV: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 1; + break; + case COLOR_YUV422_PACK_ORDER_VYUY: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 2; + break; + case COLOR_YUV422_PACK_ORDER_UYVY: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 3; + break; + default: + // Unsupported YUV422 pack order + abort(); + } +#else + // YUV422 not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + /** * @brief Enable PPA blending input background data wrap in RGB (e.g. ARGB becomes BGRA, RGB becomes BGR) * @@ -639,15 +1032,44 @@ static inline void ppa_ll_blend_configure_rx_fg_alpha(ppa_dev_t *dev, ppa_alpha_ /** * @brief Configure PPA blending pixel filling image block * + * The color to be filled is directly relying on the blend_tx_fix_pixel register field value. + * For fill operation, the data does not go through any color space conversion in the blending engine. + * * @param dev Peripheral instance address - * @param data The fix data to be filled to the image block pixels in ARGB8888 format + * @param color_mode One of the values in ppa_fill_color_mode_t + * @param data The point of the fix data to be filled to the image block pixels * @param hb The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel. * @param vb The vertical height of image block that would be filled in fix pixel filling mode. The unit is pixel. */ -static inline void ppa_ll_blend_configure_filling_block(ppa_dev_t *dev, color_pixel_argb8888_data_t *data, uint32_t hb, uint32_t vb) +static inline void ppa_ll_blend_configure_filling_block(ppa_dev_t *dev, ppa_fill_color_mode_t color_mode, void *data, uint32_t hb, uint32_t vb) { HAL_ASSERT(hb <= PPA_BLEND_HB_V && vb <= PPA_BLEND_VB_V); - dev->blend_fix_pixel.blend_tx_fix_pixel = data->val; + uint32_t fill_color_data = 0; + switch (color_mode) { + case PPA_FILL_COLOR_MODE_ARGB8888: + case PPA_FILL_COLOR_MODE_RGB888: + case PPA_FILL_COLOR_MODE_RGB565: + case PPA_FILL_COLOR_MODE_GRAY8: + fill_color_data = *(uint32_t *)data; + break; + case PPA_FILL_COLOR_MODE_YUV422: { + color_macroblock_yuv_data_t *yuv_data = (color_macroblock_yuv_data_t *)data; + fill_color_data = ((yuv_data->y) << 24) | ((yuv_data->v) << 16) | ((yuv_data->y) << 8) | (yuv_data->u); + break; + } + // case PPA_FILL_COLOR_MODE_YUV420: { + // color_macroblock_yuv_data_t *yuv_data = (color_macroblock_yuv_data_t *)data; + // if (yuv_data->u != yuv_data->v) { + // abort(); + // } + // fill_color_data = ((yuv_data->y) << 16) | ((yuv_data->y) << 8) | (yuv_data->v); + // break; + // } + default: + // Unsupported filling color mode + abort(); + } + dev->blend_fix_pixel.blend_tx_fix_pixel = fill_color_data; dev->blend_tx_size.blend_hb = hb; dev->blend_tx_size.blend_vb = vb; } diff --git a/components/hal/include/hal/color_types.h b/components/hal/include/hal/color_types.h index 93c69b323d..b222db3abf 100644 --- a/components/hal/include/hal/color_types.h +++ b/components/hal/include/hal/color_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -179,10 +179,13 @@ typedef union { /** * @brief Data structure for RGB888 pixel unit */ -typedef struct { - uint8_t b; /*!< B component [0, 255] */ - uint8_t g; /*!< G component [0, 255] */ - uint8_t r; /*!< R component [0, 255] */ +typedef union { + struct { + uint8_t b; /*!< B component [0, 255] */ + uint8_t g; /*!< G component [0, 255] */ + uint8_t r; /*!< R component [0, 255] */ + }; + uint32_t val; /*!< 32-bit RGB888 value */ } color_pixel_rgb888_data_t; /** @@ -197,6 +200,29 @@ typedef union { uint16_t val; /*!< 16-bit RGB565 value */ } color_pixel_rgb565_data_t; +/** + * @brief Data structure for GRAY8 pixel unit + */ +typedef union { + struct { + uint8_t gray; /*!< Gray component [0, 255] */ + }; + uint8_t val; /*!< 8-bit GRAY8 value */ +} color_pixel_gray8_data_t; + +/** + * @brief Data structure for YUV macroblock unit + * + * For YUV420, a macroblock is 2x2 pixels + * For YUV422, a macroblock is 2x1 pixels + * For YUV444, a macro block is a 1x1 pixel + */ +typedef struct { + uint8_t y; /*!< Y component [0, 255] */ + uint8_t u; /*!< U component [0, 255] */ + uint8_t v; /*!< V component [0, 255] */ +} color_macroblock_yuv_data_t; + /*--------------------------------------------------------------- Color Components ---------------------------------------------------------------*/ diff --git a/components/hal/include/hal/dma2d_types.h b/components/hal/include/hal/dma2d_types.h index b66c791deb..3e9142f2e2 100644 --- a/components/hal/include/hal/dma2d_types.h +++ b/components/hal/include/hal/dma2d_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -236,20 +236,23 @@ typedef enum { typedef enum { DMA2D_CSC_RX_NONE, /*!< 2D-DMA RX perform no CSC */ DMA2D_CSC_RX_SCRAMBLE, /*!< 2D-DMA RX perform only data scramble */ - DMA2D_CSC_RX_YUV422_TO_YUV444, /*!< 2D-DMA RX perform YUV422 to YUV444 conversion */ - DMA2D_CSC_RX_YUV420_TO_YUV444, /*!< 2D-DMA RX perform YUV420 to YUV444 conversion */ - DMA2D_CSC_RX_YUV420_TO_RGB888_601, /*!< 2D-DMA RX perform YUV420 to RGB888 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV420_TO_RGB565_601, /*!< 2D-DMA RX perform YUV420 to RGB565 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV420_TO_RGB888_709, /*!< 2D-DMA RX perform YUV420 to RGB888 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV420_TO_RGB565_709, /*!< 2D-DMA RX perform YUV420 to RGB565 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV422_TO_RGB888_601, /*!< 2D-DMA RX perform YUV422 to RGB888 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV422_TO_RGB565_601, /*!< 2D-DMA RX perform YUV422 to RGB565 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV422_TO_RGB888_709, /*!< 2D-DMA RX perform YUV422 to RGB888 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV422_TO_RGB565_709, /*!< 2D-DMA RX perform YUV422 to RGB565 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV444_TO_RGB888_601, /*!< 2D-DMA RX perform YUV444 to RGB888 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV444_TO_RGB565_601, /*!< 2D-DMA RX perform YUV444 to RGB565 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV444_TO_RGB888_709, /*!< 2D-DMA RX perform YUV444 to RGB888 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV444_TO_RGB565_709, /*!< 2D-DMA RX perform YUV444 to RGB565 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV422_TO_YUV444, /*!< 2D-DMA RX perform YUV422-JPEG to YUV444 conversion */ + DMA2D_CSC_RX_YUV422_TO_YUV420, /*!< 2D-DMA RX perform YUV422-JPEG to YUV420 conversion */ + DMA2D_CSC_RX_YUV420_TO_YUV444, /*!< 2D-DMA RX perform YUV420-JPEG to YUV444 conversion */ + DMA2D_CSC_RX_YUV420_TO_RGB888_601, /*!< 2D-DMA RX perform YUV420-JPEG to RGB888 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV420_TO_RGB565_601, /*!< 2D-DMA RX perform YUV420-JPEG to RGB565 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV420_TO_RGB888_709, /*!< 2D-DMA RX perform YUV420-JPEG to RGB888 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV420_TO_RGB565_709, /*!< 2D-DMA RX perform YUV420-JPEG to RGB565 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV422_TO_RGB888_601, /*!< 2D-DMA RX perform YUV422-JPEG to RGB888 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV422_TO_RGB565_601, /*!< 2D-DMA RX perform YUV422-JPEG to RGB565 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV422_TO_RGB888_709, /*!< 2D-DMA RX perform YUV422-JPEG to RGB888 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV422_TO_RGB565_709, /*!< 2D-DMA RX perform YUV422-JPEG to RGB565 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV444_TO_YUV422, /*!< 2D-DMA RX perform YUV444-JPEG to YUV422-MIPI conversion */ + DMA2D_CSC_RX_YUV444_TO_YUV420, /*!< 2D-DMA RX perform YUV444-JPEG to YUV420 conversion */ + DMA2D_CSC_RX_YUV444_TO_RGB888_601, /*!< 2D-DMA RX perform YUV444-JPEG to RGB888 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV444_TO_RGB565_601, /*!< 2D-DMA RX perform YUV444-JPEG to RGB565 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV444_TO_RGB888_709, /*!< 2D-DMA RX perform YUV444-JPEG to RGB888 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV444_TO_RGB565_709, /*!< 2D-DMA RX perform YUV444-JPEG to RGB565 conversion (follow BT709 standard) */ DMA2D_CSC_RX_INVALID, /*!< Invalid 2D-DMA RX color space conversion */ } dma2d_csc_rx_option_t; diff --git a/components/hal/include/hal/ppa_types.h b/components/hal/include/hal/ppa_types.h index 67741433c5..dd967e4218 100644 --- a/components/hal/include/hal/ppa_types.h +++ b/components/hal/include/hal/ppa_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -44,8 +44,8 @@ typedef enum { // YUV444 not supported by PPA hardware, but we can use 2D-DMA to do conversion before sending into and after coming out from the PPA module // If in_pic is YUV444, then TX DMA channel could do DMA2D_CSC_TX_YUV444_TO_RGB888_601/709, so PPA in_color_mode is RGB888 // If out_pic is YUV444, then RX DMA channel could do DMA2D_CSC_RX_YUV420_TO_YUV444, so PPA out_color_mode is YUV420 - // TODO: P4 ECO2 supports YUV422 - // PPA_SRM_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA SRM color mode: YUV422 (input only, limited range only) */ + PPA_SRM_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA SRM color mode: YUV422 (input data pack order all supported, but output data format is fixed to YVYU) */ + PPA_SRM_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA SRM color mode: GRAY8 */ } ppa_srm_color_mode_t; /** @@ -57,9 +57,12 @@ typedef enum { PPA_BLEND_COLOR_MODE_RGB565 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565), /*!< PPA blend color mode: RGB565 */ PPA_BLEND_COLOR_MODE_A8 = COLOR_TYPE_ID(COLOR_SPACE_ALPHA, COLOR_PIXEL_A8), /*!< PPA blend color mode: A8, only available on blend foreground input */ PPA_BLEND_COLOR_MODE_A4 = COLOR_TYPE_ID(COLOR_SPACE_ALPHA, COLOR_PIXEL_A4), /*!< PPA blend color mode: A4, only available on blend foreground input */ + PPA_BLEND_COLOR_MODE_YUV420 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV420), /*!< PPA blend color mode: YUV420, only available on blend background input or on output */ + PPA_BLEND_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA blend color mode: YUV422, only available on blend background input (all pack order supported) or on output (fixed to YVYU) */ + PPA_BLEND_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA blend color mode: GRAY8, only available on blend background input or on output */ // TODO: Support CLUT to support L4/L8 color mode - // PPA_BLEND_COLOR_MODE_L8 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L8), /*!< PPA blend color mode: L8, only available on blend inputs */ - // PPA_BLEND_COLOR_MODE_L4 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L4), /*!< PPA blend color mode: L4, only available on blend inputs */ + // PPA_BLEND_COLOR_MODE_L8 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L8), /*!< PPA blend color mode: L8, only available on blend input */ + // PPA_BLEND_COLOR_MODE_L4 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L4), /*!< PPA blend color mode: L4, only available on blend input */ } ppa_blend_color_mode_t; /** @@ -69,6 +72,9 @@ typedef enum { PPA_FILL_COLOR_MODE_ARGB8888 = COLOR_TYPE_ID(COLOR_SPACE_ARGB, COLOR_PIXEL_ARGB8888), /*!< PPA fill color mode: ARGB8888 */ PPA_FILL_COLOR_MODE_RGB888 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB888), /*!< PPA fill color mode: RGB888 */ PPA_FILL_COLOR_MODE_RGB565 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565), /*!< PPA fill color mode: RGB565 */ + // PPA_FILL_COLOR_MODE_YUV420 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV420), /*!< PPA fill color mode: YUV420 */ // Non-typical YUV420, U and V components have to be the same value + PPA_FILL_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA fill color mode: YUV422 (w/ YVYU pack order) */ + PPA_FILL_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA fill color mode: GRAY8 */ } ppa_fill_color_mode_t; /** diff --git a/components/soc/esp32p4/dma2d_periph.c b/components/soc/esp32p4/dma2d_periph.c index e7043df942..7cd670382a 100644 --- a/components/soc/esp32p4/dma2d_periph.c +++ b/components/soc/esp32p4/dma2d_periph.c @@ -14,10 +14,12 @@ const dma2d_signal_conn_t dma2d_periph_signals = { [0] = ETS_DMA2D_OUT_CH0_INTR_SOURCE, [1] = ETS_DMA2D_OUT_CH1_INTR_SOURCE, [2] = ETS_DMA2D_OUT_CH2_INTR_SOURCE, + [3] = ETS_DMA2D_OUT_CH3_INTR_SOURCE, // This channel only exists on P4 ver. >= 3.0 }, .rx_irq_id = { [0] = ETS_DMA2D_IN_CH0_INTR_SOURCE, [1] = ETS_DMA2D_IN_CH1_INTR_SOURCE, + [2] = ETS_DMA2D_IN_CH2_INTR_SOURCE, // This channel only exists on P4 ver. >= 3.0 } } } diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 7b9197317c..82190d0d6b 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -629,11 +629,11 @@ config SOC_DMA2D_GROUPS config SOC_DMA2D_TX_CHANNELS_PER_GROUP int - default 3 + default 4 config SOC_DMA2D_RX_CHANNELS_PER_GROUP int - default 2 + default 3 config SOC_ETM_GROUPS int diff --git a/components/soc/esp32p4/include/soc/interrupts.h b/components/soc/esp32p4/include/soc/interrupts.h index 3653913c7d..8745eed115 100644 --- a/components/soc/esp32p4/include/soc/interrupts.h +++ b/components/soc/esp32p4/include/soc/interrupts.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -152,7 +152,14 @@ typedef enum { ETS_H264_REG_INTR_SOURCE, ETS_ASSIST_DEBUG_INTR_SOURCE, - ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ + // The following sources' int_map_reg addr are not continuous with previous ones (check interrupt_core0/1_struct.h), + // but esp_rom_route_intr_matrix and interrupt_clic_ll_route assume all int_map_reg addr are continuous. + // Therefore, the workaround is to give the three new interrupt sources ID numbers that match with the corresponding correct addresses. + ETS_DMA2D_IN_CH2_INTR_SOURCE = 133, /**< This interrupt source only exists on chip ver. >= 3.0 */ + ETS_DMA2D_OUT_CH3_INTR_SOURCE, /**< This interrupt source only exists on chip ver. >= 3.0 */ + ETS_AXI_PERF_MON_INTR_SOURCE, /**< This interrupt source only exists on chip ver. >= 3.0 */ + + ETS_MAX_INTR_SOURCE, /**< number of interrupt sources (this value is larger than the real number of sources on ver. less than 3.0, but it should be fine)*/ } periph_interrupt_t; typedef periph_interrupt_t periph_interrput_t __attribute__((deprecated("in favor of periph_interrupt_t"))); diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index cc25040c09..cc23a12dc4 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -225,8 +225,8 @@ /*-------------------------- 2D-DMA CAPS -------------------------------------*/ #define SOC_DMA2D_GROUPS (1U) // Number of 2D-DMA groups -#define SOC_DMA2D_TX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA TX (OUT) channels in each group -#define SOC_DMA2D_RX_CHANNELS_PER_GROUP (2) // Number of 2D-DMA RX (IN) channels in each group +#define SOC_DMA2D_TX_CHANNELS_PER_GROUP (4) // Number of 2D-DMA TX (OUT) channels in each group (4th channel only exists on P4 ver. >= 3.0) +#define SOC_DMA2D_RX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA RX (IN) channels in each group (3rd channel only exists on P4 ver. >= 3.0) // #define SOC_DMA2D_SUPPORT_ETM (1) // Support ETM submodule /*-------------------------- ETM CAPS --------------------------------------*/ diff --git a/components/soc/esp32p4/interrupts.c b/components/soc/esp32p4/interrupts.c index 818367e955..c02b70eb15 100644 --- a/components/soc/esp32p4/interrupts.c +++ b/components/soc/esp32p4/interrupts.c @@ -135,4 +135,7 @@ const char *const esp_isr_names[] = { [ETS_H264_DMA2D_IN_CH5_INTR_SOURCE] = "H264_DMA2D_IN_CH5", [ETS_H264_REG_INTR_SOURCE] = "H264_REG", [ETS_ASSIST_DEBUG_INTR_SOURCE] = "ASSIST_DEBUG", + [ETS_DMA2D_IN_CH2_INTR_SOURCE] = "DMA2D_IN_CH2", /* This interrupt source only exists on chip ver. >= 3.0 */ + [ETS_DMA2D_OUT_CH3_INTR_SOURCE] = "DMA2D_OUT_CH3", /* This interrupt source only exists on chip ver. >= 3.0 */ + [ETS_AXI_PERF_MON_INTR_SOURCE] = "AXI_PERF_MON", /* This interrupt source only exists on chip ver. >= 3.0 */ }; diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld index 01c5644f08..d25499b74e 100644 --- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld +++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld @@ -26,7 +26,7 @@ PROVIDE ( LP2HP_PERI_PMS = 0x500A5800 ); PROVIDE ( DMA_PMS = 0x500A6000 ); PROVIDE ( AXI_PERF_MON = 0x500A8000 ); PROVIDE ( LEDC = 0x500D3000 ); -PROVIDE ( LEDC_GAMMA_RAM = 0x500D3400 ); +PROVIDE ( LEDC_GAMMA_RAM = 0x500D3400 ); PROVIDE ( TIMERG0 = 0x500C2000 ); PROVIDE ( TIMERG1 = 0x500C3000 ); PROVIDE ( SYSTIMER = 0x500E2000 ); diff --git a/components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h index b3f91e92b3..a63f6d64ff 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -1763,42 +1763,21 @@ typedef struct { volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel; volatile dma2d_in_arb_chn_reg_t in_arb; volatile dma2d_in_ro_status_chn_reg_t in_ro_status; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert; - volatile dma2d_in_scramble_chn_reg_t in_scramble; - volatile dma2d_color_param_group_chn_reg_t in_color_param_group; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; - uint32_t reserved_570[36]; -} dma2d_in_ch0_reg_t; - -typedef struct { - volatile dma2d_in_conf0_chn_reg_t in_conf0; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena; - volatile dma2d_in_int_st_chn_reg_t in_int_st; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr; - volatile dma2d_infifo_status_chn_reg_t infifo_status; - volatile dma2d_in_pop_chn_reg_t in_pop; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr; - volatile dma2d_in_state_chn_reg_t in_state; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr; - volatile dma2d_in_dscr_chn_reg_t in_dscr; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel; - volatile dma2d_in_arb_chn_reg_t in_arb; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; - uint32_t reserved_64c[45]; -} dma2d_in_ch1_reg_t; + union { + volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; /* only exist on channel0 */ + volatile dma2d_in_etm_conf_chn_reg_t in1_etm_conf; /* specific for channel1 */ + }; + volatile dma2d_in_color_convert_chn_reg_t in_color_convert; /* only exist on channel0 */ + volatile dma2d_in_scramble_chn_reg_t in_scramble; /* only exist on channel0 */ + volatile dma2d_color_param_group_chn_reg_t in_color_param_group; /* only exist on channel0 */ + volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; /* On ver. less than 3.0, channel 1 in_etm_conf register is at the in_ro_pd_conf addr. Here is to only be compatible with new ECOs. Workaround should be done in LL layer. */ + uint32_t reserved_in[36]; +} dma2d_in_chn_reg_t; typedef struct dma2d_dev_t { volatile dma2d_out_chn_reg_t out_channel[3]; uint32_t reserved_300[128]; - volatile dma2d_in_ch0_reg_t in_channel0; - volatile dma2d_in_ch1_reg_t in_channel1; + volatile dma2d_in_chn_reg_t in_channel[2]; uint32_t reserved_700[192]; volatile dma2d_axi_err_reg_t axi_err; volatile dma2d_rst_conf_reg_t rst_conf; diff --git a/components/soc/esp32p4/register/hw_ver1/soc/ledc_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/ledc_struct.h index df2c5df873..2dbc716a79 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/ledc_struct.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/ledc_struct.h @@ -106,10 +106,10 @@ typedef union { */ typedef union { struct { - /** duty_ch0_r : RO; bitpos: [24:0]; default: 0; + /** duty_r : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel n. */ - uint32_t duty:25; + uint32_t duty_r:25; uint32_t reserved_25:7; }; uint32_t val; @@ -577,20 +577,20 @@ typedef union { */ typedef union { struct { - /** ch0_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; + /** gamma_entry_num : R/W; bitpos: [4:0]; default: 0; * Configures the number of duty cycle fading rages for LEDC chn. */ - uint32_t ch0_gamma_entry_num:5; - /** ch0_gamma_pause : WT; bitpos: [5]; default: 0; + uint32_t gamma_entry_num:5; + /** gamma_pause : WT; bitpos: [5]; default: 0; * Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No * effect\\1: Pause */ - uint32_t ch0_gamma_pause:1; - /** ch0_gamma_resume : WT; bitpos: [6]; default: 0; + uint32_t gamma_pause:1; + /** gamma_resume : WT; bitpos: [6]; default: 0; * Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No * effect\\1: Resume */ - uint32_t ch0_gamma_resume:1; + uint32_t gamma_resume:1; uint32_t reserved_7:25; }; uint32_t val; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h deleted file mode 100644 index 3077ad0e45..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h +++ /dev/null @@ -1,7537 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** DMA2D_OUT_CONF0_CH0_REG register - * Configures the tx direction of channel 0 - */ -#define DMA2D_OUT_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x0) -/** DMA2D_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ -#define DMA2D_OUT_AUTO_WRBACK_CH0 (BIT(0)) -#define DMA2D_OUT_AUTO_WRBACK_CH0_M (DMA2D_OUT_AUTO_WRBACK_CH0_V << DMA2D_OUT_AUTO_WRBACK_CH0_S) -#define DMA2D_OUT_AUTO_WRBACK_CH0_V 0x00000001U -#define DMA2D_OUT_AUTO_WRBACK_CH0_S 0 -/** DMA2D_OUT_EOF_MODE_CH0 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ -#define DMA2D_OUT_EOF_MODE_CH0 (BIT(1)) -#define DMA2D_OUT_EOF_MODE_CH0_M (DMA2D_OUT_EOF_MODE_CH0_V << DMA2D_OUT_EOF_MODE_CH0_S) -#define DMA2D_OUT_EOF_MODE_CH0_V 0x00000001U -#define DMA2D_OUT_EOF_MODE_CH0_S 1 -/** DMA2D_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ -#define DMA2D_OUTDSCR_BURST_EN_CH0 (BIT(2)) -#define DMA2D_OUTDSCR_BURST_EN_CH0_M (DMA2D_OUTDSCR_BURST_EN_CH0_V << DMA2D_OUTDSCR_BURST_EN_CH0_S) -#define DMA2D_OUTDSCR_BURST_EN_CH0_V 0x00000001U -#define DMA2D_OUTDSCR_BURST_EN_CH0_S 2 -/** DMA2D_OUT_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_OUT_ECC_AES_EN_CH0 (BIT(3)) -#define DMA2D_OUT_ECC_AES_EN_CH0_M (DMA2D_OUT_ECC_AES_EN_CH0_V << DMA2D_OUT_ECC_AES_EN_CH0_S) -#define DMA2D_OUT_ECC_AES_EN_CH0_V 0x00000001U -#define DMA2D_OUT_ECC_AES_EN_CH0_S 3 -/** DMA2D_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_OUT_CHECK_OWNER_CH0 (BIT(4)) -#define DMA2D_OUT_CHECK_OWNER_CH0_M (DMA2D_OUT_CHECK_OWNER_CH0_V << DMA2D_OUT_CHECK_OWNER_CH0_S) -#define DMA2D_OUT_CHECK_OWNER_CH0_V 0x00000001U -#define DMA2D_OUT_CHECK_OWNER_CH0_S 4 -/** DMA2D_OUT_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_OUT_LOOP_TEST_CH0 (BIT(5)) -#define DMA2D_OUT_LOOP_TEST_CH0_M (DMA2D_OUT_LOOP_TEST_CH0_V << DMA2D_OUT_LOOP_TEST_CH0_S) -#define DMA2D_OUT_LOOP_TEST_CH0_V 0x00000001U -#define DMA2D_OUT_LOOP_TEST_CH0_S 5 -/** DMA2D_OUT_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_OUT_MEM_BURST_LENGTH_CH0 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_M (DMA2D_OUT_MEM_BURST_LENGTH_CH0_V << DMA2D_OUT_MEM_BURST_LENGTH_CH0_S) -#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_V 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_S 6 -/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S) -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S 9 -/** DMA2D_OUT_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_OUT_DSCR_PORT_EN_CH0 (BIT(11)) -#define DMA2D_OUT_DSCR_PORT_EN_CH0_M (DMA2D_OUT_DSCR_PORT_EN_CH0_V << DMA2D_OUT_DSCR_PORT_EN_CH0_S) -#define DMA2D_OUT_DSCR_PORT_EN_CH0_V 0x00000001U -#define DMA2D_OUT_DSCR_PORT_EN_CH0_S 11 -/** DMA2D_OUT_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ -#define DMA2D_OUT_PAGE_BOUND_EN_CH0 (BIT(12)) -#define DMA2D_OUT_PAGE_BOUND_EN_CH0_M (DMA2D_OUT_PAGE_BOUND_EN_CH0_V << DMA2D_OUT_PAGE_BOUND_EN_CH0_S) -#define DMA2D_OUT_PAGE_BOUND_EN_CH0_V 0x00000001U -#define DMA2D_OUT_PAGE_BOUND_EN_CH0_S 12 -/** DMA2D_OUT_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_OUT_REORDER_EN_CH0 (BIT(16)) -#define DMA2D_OUT_REORDER_EN_CH0_M (DMA2D_OUT_REORDER_EN_CH0_V << DMA2D_OUT_REORDER_EN_CH0_S) -#define DMA2D_OUT_REORDER_EN_CH0_V 0x00000001U -#define DMA2D_OUT_REORDER_EN_CH0_S 16 -/** DMA2D_OUT_RST_CH0 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ -#define DMA2D_OUT_RST_CH0 (BIT(24)) -#define DMA2D_OUT_RST_CH0_M (DMA2D_OUT_RST_CH0_V << DMA2D_OUT_RST_CH0_S) -#define DMA2D_OUT_RST_CH0_V 0x00000001U -#define DMA2D_OUT_RST_CH0_S 24 -/** DMA2D_OUT_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_OUT_CMD_DISABLE_CH0 (BIT(25)) -#define DMA2D_OUT_CMD_DISABLE_CH0_M (DMA2D_OUT_CMD_DISABLE_CH0_V << DMA2D_OUT_CMD_DISABLE_CH0_S) -#define DMA2D_OUT_CMD_DISABLE_CH0_V 0x00000001U -#define DMA2D_OUT_CMD_DISABLE_CH0_S 25 -/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0 (BIT(26)) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S 26 - -/** DMA2D_OUT_INT_RAW_CH0_REG register - * Raw interrupt status of TX channel 0 - */ -#define DMA2D_OUT_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x4) -/** DMA2D_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ -#define DMA2D_OUT_DONE_CH0_INT_RAW (BIT(0)) -#define DMA2D_OUT_DONE_CH0_INT_RAW_M (DMA2D_OUT_DONE_CH0_INT_RAW_V << DMA2D_OUT_DONE_CH0_INT_RAW_S) -#define DMA2D_OUT_DONE_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DONE_CH0_INT_RAW_S 0 -/** DMA2D_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ -#define DMA2D_OUT_EOF_CH0_INT_RAW (BIT(1)) -#define DMA2D_OUT_EOF_CH0_INT_RAW_M (DMA2D_OUT_EOF_CH0_INT_RAW_V << DMA2D_OUT_EOF_CH0_INT_RAW_S) -#define DMA2D_OUT_EOF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_EOF_CH0_INT_RAW_S 1 -/** DMA2D_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ -#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S 12 - -/** DMA2D_OUT_INT_ENA_CH0_REG register - * Interrupt enable bits of TX channel 0 - */ -#define DMA2D_OUT_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x8) -/** DMA2D_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH0_INT_ENA (BIT(0)) -#define DMA2D_OUT_DONE_CH0_INT_ENA_M (DMA2D_OUT_DONE_CH0_INT_ENA_V << DMA2D_OUT_DONE_CH0_INT_ENA_S) -#define DMA2D_OUT_DONE_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DONE_CH0_INT_ENA_S 0 -/** DMA2D_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH0_INT_ENA (BIT(1)) -#define DMA2D_OUT_EOF_CH0_INT_ENA_M (DMA2D_OUT_EOF_CH0_INT_ENA_V << DMA2D_OUT_EOF_CH0_INT_ENA_S) -#define DMA2D_OUT_EOF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_EOF_CH0_INT_ENA_S 1 -/** DMA2D_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S 12 - -/** DMA2D_OUT_INT_ST_CH0_REG register - * Masked interrupt status of TX channel 0 - */ -#define DMA2D_OUT_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0xc) -/** DMA2D_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH0_INT_ST (BIT(0)) -#define DMA2D_OUT_DONE_CH0_INT_ST_M (DMA2D_OUT_DONE_CH0_INT_ST_V << DMA2D_OUT_DONE_CH0_INT_ST_S) -#define DMA2D_OUT_DONE_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_DONE_CH0_INT_ST_S 0 -/** DMA2D_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH0_INT_ST (BIT(1)) -#define DMA2D_OUT_EOF_CH0_INT_ST_M (DMA2D_OUT_EOF_CH0_INT_ST_V << DMA2D_OUT_EOF_CH0_INT_ST_S) -#define DMA2D_OUT_EOF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_EOF_CH0_INT_ST_S 1 -/** DMA2D_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S 12 - -/** DMA2D_OUT_INT_CLR_CH0_REG register - * Interrupt clear bits of TX channel 0 - */ -#define DMA2D_OUT_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x10) -/** DMA2D_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH0_INT_CLR (BIT(0)) -#define DMA2D_OUT_DONE_CH0_INT_CLR_M (DMA2D_OUT_DONE_CH0_INT_CLR_V << DMA2D_OUT_DONE_CH0_INT_CLR_S) -#define DMA2D_OUT_DONE_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DONE_CH0_INT_CLR_S 0 -/** DMA2D_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH0_INT_CLR (BIT(1)) -#define DMA2D_OUT_EOF_CH0_INT_CLR_M (DMA2D_OUT_EOF_CH0_INT_CLR_V << DMA2D_OUT_EOF_CH0_INT_CLR_S) -#define DMA2D_OUT_EOF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_EOF_CH0_INT_CLR_S 1 -/** DMA2D_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S 12 - -/** DMA2D_OUTFIFO_STATUS_CH0_REG register - * Represents the status of the tx fifo of channel 0 - */ -#define DMA2D_OUTFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x14) -/** DMA2D_OUTFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L2_CH0 (BIT(0)) -#define DMA2D_OUTFIFO_FULL_L2_CH0_M (DMA2D_OUTFIFO_FULL_L2_CH0_V << DMA2D_OUTFIFO_FULL_L2_CH0_S) -#define DMA2D_OUTFIFO_FULL_L2_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L2_CH0_S 0 -/** DMA2D_OUTFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L2_CH0 (BIT(1)) -#define DMA2D_OUTFIFO_EMPTY_L2_CH0_M (DMA2D_OUTFIFO_EMPTY_L2_CH0_V << DMA2D_OUTFIFO_EMPTY_L2_CH0_S) -#define DMA2D_OUTFIFO_EMPTY_L2_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L2_CH0_S 1 -/** DMA2D_OUTFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L2_CH0 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH0_M (DMA2D_OUTFIFO_CNT_L2_CH0_V << DMA2D_OUTFIFO_CNT_L2_CH0_S) -#define DMA2D_OUTFIFO_CNT_L2_CH0_V 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH0_S 2 -/** DMA2D_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_1B_CH0 (BIT(7)) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_M (DMA2D_OUT_REMAIN_UNDER_1B_CH0_V << DMA2D_OUT_REMAIN_UNDER_1B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_S 7 -/** DMA2D_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_2B_CH0 (BIT(8)) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_M (DMA2D_OUT_REMAIN_UNDER_2B_CH0_V << DMA2D_OUT_REMAIN_UNDER_2B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_S 8 -/** DMA2D_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_3B_CH0 (BIT(9)) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_M (DMA2D_OUT_REMAIN_UNDER_3B_CH0_V << DMA2D_OUT_REMAIN_UNDER_3B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_S 9 -/** DMA2D_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_4B_CH0 (BIT(10)) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_M (DMA2D_OUT_REMAIN_UNDER_4B_CH0_V << DMA2D_OUT_REMAIN_UNDER_4B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_S 10 -/** DMA2D_OUT_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_5B_CH0 (BIT(11)) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_M (DMA2D_OUT_REMAIN_UNDER_5B_CH0_V << DMA2D_OUT_REMAIN_UNDER_5B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_S 11 -/** DMA2D_OUT_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_6B_CH0 (BIT(12)) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_M (DMA2D_OUT_REMAIN_UNDER_6B_CH0_V << DMA2D_OUT_REMAIN_UNDER_6B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_S 12 -/** DMA2D_OUT_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_7B_CH0 (BIT(13)) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_M (DMA2D_OUT_REMAIN_UNDER_7B_CH0_V << DMA2D_OUT_REMAIN_UNDER_7B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_S 13 -/** DMA2D_OUT_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_8B_CH0 (BIT(14)) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_M (DMA2D_OUT_REMAIN_UNDER_8B_CH0_V << DMA2D_OUT_REMAIN_UNDER_8B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_S 14 -/** DMA2D_OUTFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L1_CH0 (BIT(15)) -#define DMA2D_OUTFIFO_FULL_L1_CH0_M (DMA2D_OUTFIFO_FULL_L1_CH0_V << DMA2D_OUTFIFO_FULL_L1_CH0_S) -#define DMA2D_OUTFIFO_FULL_L1_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L1_CH0_S 15 -/** DMA2D_OUTFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L1_CH0 (BIT(16)) -#define DMA2D_OUTFIFO_EMPTY_L1_CH0_M (DMA2D_OUTFIFO_EMPTY_L1_CH0_V << DMA2D_OUTFIFO_EMPTY_L1_CH0_S) -#define DMA2D_OUTFIFO_EMPTY_L1_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L1_CH0_S 16 -/** DMA2D_OUTFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L1_CH0 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH0_M (DMA2D_OUTFIFO_CNT_L1_CH0_V << DMA2D_OUTFIFO_CNT_L1_CH0_S) -#define DMA2D_OUTFIFO_CNT_L1_CH0_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH0_S 17 -/** DMA2D_OUTFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L3_CH0 (BIT(22)) -#define DMA2D_OUTFIFO_FULL_L3_CH0_M (DMA2D_OUTFIFO_FULL_L3_CH0_V << DMA2D_OUTFIFO_FULL_L3_CH0_S) -#define DMA2D_OUTFIFO_FULL_L3_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L3_CH0_S 22 -/** DMA2D_OUTFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L3_CH0 (BIT(23)) -#define DMA2D_OUTFIFO_EMPTY_L3_CH0_M (DMA2D_OUTFIFO_EMPTY_L3_CH0_V << DMA2D_OUTFIFO_EMPTY_L3_CH0_S) -#define DMA2D_OUTFIFO_EMPTY_L3_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L3_CH0_S 23 -/** DMA2D_OUTFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L3_CH0 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH0_M (DMA2D_OUTFIFO_CNT_L3_CH0_V << DMA2D_OUTFIFO_CNT_L3_CH0_S) -#define DMA2D_OUTFIFO_CNT_L3_CH0_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH0_S 24 - -/** DMA2D_OUT_PUSH_CH0_REG register - * Configures the tx fifo of channel 0 - */ -#define DMA2D_OUT_PUSH_CH0_REG (DR_REG_DMA2D_BASE + 0x18) -/** DMA2D_OUTFIFO_WDATA_CH0 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_WDATA_CH0 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH0_M (DMA2D_OUTFIFO_WDATA_CH0_V << DMA2D_OUTFIFO_WDATA_CH0_S) -#define DMA2D_OUTFIFO_WDATA_CH0_V 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH0_S 0 -/** DMA2D_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_PUSH_CH0 (BIT(10)) -#define DMA2D_OUTFIFO_PUSH_CH0_M (DMA2D_OUTFIFO_PUSH_CH0_V << DMA2D_OUTFIFO_PUSH_CH0_S) -#define DMA2D_OUTFIFO_PUSH_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_PUSH_CH0_S 10 - -/** DMA2D_OUT_LINK_CONF_CH0_REG register - * Configures the tx descriptor operations of channel 0 - */ -#define DMA2D_OUT_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x1c) -/** DMA2D_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_STOP_CH0 (BIT(20)) -#define DMA2D_OUTLINK_STOP_CH0_M (DMA2D_OUTLINK_STOP_CH0_V << DMA2D_OUTLINK_STOP_CH0_S) -#define DMA2D_OUTLINK_STOP_CH0_V 0x00000001U -#define DMA2D_OUTLINK_STOP_CH0_S 20 -/** DMA2D_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_START_CH0 (BIT(21)) -#define DMA2D_OUTLINK_START_CH0_M (DMA2D_OUTLINK_START_CH0_V << DMA2D_OUTLINK_START_CH0_S) -#define DMA2D_OUTLINK_START_CH0_V 0x00000001U -#define DMA2D_OUTLINK_START_CH0_S 21 -/** DMA2D_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ -#define DMA2D_OUTLINK_RESTART_CH0 (BIT(22)) -#define DMA2D_OUTLINK_RESTART_CH0_M (DMA2D_OUTLINK_RESTART_CH0_V << DMA2D_OUTLINK_RESTART_CH0_S) -#define DMA2D_OUTLINK_RESTART_CH0_V 0x00000001U -#define DMA2D_OUTLINK_RESTART_CH0_S 22 -/** DMA2D_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ -#define DMA2D_OUTLINK_PARK_CH0 (BIT(23)) -#define DMA2D_OUTLINK_PARK_CH0_M (DMA2D_OUTLINK_PARK_CH0_V << DMA2D_OUTLINK_PARK_CH0_S) -#define DMA2D_OUTLINK_PARK_CH0_V 0x00000001U -#define DMA2D_OUTLINK_PARK_CH0_S 23 - -/** DMA2D_OUT_LINK_ADDR_CH0_REG register - * Configures the tx descriptor address of channel 0 - */ -#define DMA2D_OUT_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x20) -/** DMA2D_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ -#define DMA2D_OUTLINK_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH0_M (DMA2D_OUTLINK_ADDR_CH0_V << DMA2D_OUTLINK_ADDR_CH0_S) -#define DMA2D_OUTLINK_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH0_S 0 - -/** DMA2D_OUT_STATE_CH0_REG register - * Represents the working status of the tx descriptor of channel 0 - */ -#define DMA2D_OUT_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x24) -/** DMA2D_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ -#define DMA2D_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH0_M (DMA2D_OUTLINK_DSCR_ADDR_CH0_V << DMA2D_OUTLINK_DSCR_ADDR_CH0_S) -#define DMA2D_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH0_S 0 -/** DMA2D_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ -#define DMA2D_OUT_DSCR_STATE_CH0 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH0_M (DMA2D_OUT_DSCR_STATE_CH0_V << DMA2D_OUT_DSCR_STATE_CH0_S) -#define DMA2D_OUT_DSCR_STATE_CH0_V 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH0_S 18 -/** DMA2D_OUT_STATE_CH0 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ -#define DMA2D_OUT_STATE_CH0 0x0000000FU -#define DMA2D_OUT_STATE_CH0_M (DMA2D_OUT_STATE_CH0_V << DMA2D_OUT_STATE_CH0_S) -#define DMA2D_OUT_STATE_CH0_V 0x0000000FU -#define DMA2D_OUT_STATE_CH0_S 20 -/** DMA2D_OUT_RESET_AVAIL_CH0 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_OUT_RESET_AVAIL_CH0 (BIT(24)) -#define DMA2D_OUT_RESET_AVAIL_CH0_M (DMA2D_OUT_RESET_AVAIL_CH0_V << DMA2D_OUT_RESET_AVAIL_CH0_S) -#define DMA2D_OUT_RESET_AVAIL_CH0_V 0x00000001U -#define DMA2D_OUT_RESET_AVAIL_CH0_S 24 - -/** DMA2D_OUT_EOF_DES_ADDR_CH0_REG register - * Represents the address associated with the outlink descriptor of channel 0 - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x28) -/** DMA2D_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH0_M (DMA2D_OUT_EOF_DES_ADDR_CH0_V << DMA2D_OUT_EOF_DES_ADDR_CH0_S) -#define DMA2D_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH0_S 0 - -/** DMA2D_OUT_DSCR_CH0_REG register - * Represents the address associated with the outlink descriptor of channel 0 - */ -#define DMA2D_OUT_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x2c) -/** DMA2D_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ -#define DMA2D_OUTLINK_DSCR_CH0 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH0_M (DMA2D_OUTLINK_DSCR_CH0_V << DMA2D_OUTLINK_DSCR_CH0_S) -#define DMA2D_OUTLINK_DSCR_CH0_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH0_S 0 - -/** DMA2D_OUT_DSCR_BF0_CH0_REG register - * Represents the address associated with the outlink descriptor of channel 0 - */ -#define DMA2D_OUT_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x30) -/** DMA2D_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ -#define DMA2D_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH0_M (DMA2D_OUTLINK_DSCR_BF0_CH0_V << DMA2D_OUTLINK_DSCR_BF0_CH0_S) -#define DMA2D_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH0_S 0 - -/** DMA2D_OUT_DSCR_BF1_CH0_REG register - * Represents the address associated with the outlink descriptor of channel 0 - */ -#define DMA2D_OUT_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x34) -/** DMA2D_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ -#define DMA2D_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH0_M (DMA2D_OUTLINK_DSCR_BF1_CH0_V << DMA2D_OUTLINK_DSCR_BF1_CH0_S) -#define DMA2D_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH0_S 0 - -/** DMA2D_OUT_PERI_SEL_CH0_REG register - * Configures the tx peripheral of channel 0 - */ -#define DMA2D_OUT_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x38) -/** DMA2D_OUT_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ -#define DMA2D_OUT_PERI_SEL_CH0 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH0_M (DMA2D_OUT_PERI_SEL_CH0_V << DMA2D_OUT_PERI_SEL_CH0_S) -#define DMA2D_OUT_PERI_SEL_CH0_V 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH0_S 0 - -/** DMA2D_OUT_ARB_CH0_REG register - * Configures the tx arbiter of channel 0 - */ -#define DMA2D_OUT_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x3c) -/** DMA2D_OUT_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_OUT_ARB_TOKEN_NUM_CH0 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_M (DMA2D_OUT_ARB_TOKEN_NUM_CH0_V << DMA2D_OUT_ARB_TOKEN_NUM_CH0_S) -#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_V 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_CH0 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH0_M (DMA2D_OUT_ARB_PRIORITY_CH0_V << DMA2D_OUT_ARB_PRIORITY_CH0_S) -#define DMA2D_OUT_ARB_PRIORITY_CH0_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH0_S 4 -/** DMA2D_OUT_ARB_PRIORITY_H_CH0 : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_H_CH0 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH0_M (DMA2D_OUT_ARB_PRIORITY_H_CH0_V << DMA2D_OUT_ARB_PRIORITY_H_CH0_S) -#define DMA2D_OUT_ARB_PRIORITY_H_CH0_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH0_S 6 - -/** DMA2D_OUT_RO_STATUS_CH0_REG register - * Represents the status of the tx reorder module of channel 0 - */ -#define DMA2D_OUT_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x40) -/** DMA2D_OUTFIFO_RO_CNT_CH0 : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ -#define DMA2D_OUTFIFO_RO_CNT_CH0 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH0_M (DMA2D_OUTFIFO_RO_CNT_CH0_V << DMA2D_OUTFIFO_RO_CNT_CH0_S) -#define DMA2D_OUTFIFO_RO_CNT_CH0_V 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH0_S 0 -/** DMA2D_OUT_RO_WR_STATE_CH0 : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_OUT_RO_WR_STATE_CH0 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH0_M (DMA2D_OUT_RO_WR_STATE_CH0_V << DMA2D_OUT_RO_WR_STATE_CH0_S) -#define DMA2D_OUT_RO_WR_STATE_CH0_V 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH0_S 6 -/** DMA2D_OUT_RO_RD_STATE_CH0 : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_OUT_RO_RD_STATE_CH0 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH0_M (DMA2D_OUT_RO_RD_STATE_CH0_V << DMA2D_OUT_RO_RD_STATE_CH0_S) -#define DMA2D_OUT_RO_RD_STATE_CH0_V 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH0_S 8 -/** DMA2D_OUT_PIXEL_BYTE_CH0 : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_OUT_PIXEL_BYTE_CH0 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH0_M (DMA2D_OUT_PIXEL_BYTE_CH0_V << DMA2D_OUT_PIXEL_BYTE_CH0_S) -#define DMA2D_OUT_PIXEL_BYTE_CH0_V 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH0_S 10 -/** DMA2D_OUT_BURST_BLOCK_NUM_CH0 : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ -#define DMA2D_OUT_BURST_BLOCK_NUM_CH0 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_M (DMA2D_OUT_BURST_BLOCK_NUM_CH0_V << DMA2D_OUT_BURST_BLOCK_NUM_CH0_S) -#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_V 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_S 14 - -/** DMA2D_OUT_RO_PD_CONF_CH0_REG register - * Configures the tx reorder memory of channel 0 - */ -#define DMA2D_OUT_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x44) -/** DMA2D_OUT_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ -#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0 (BIT(4)) -#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_M (DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S) -#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V 0x00000001U -#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S 4 -/** DMA2D_OUT_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ -#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0 (BIT(5)) -#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_M (DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S) -#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V 0x00000001U -#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S 5 -/** DMA2D_OUT_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ -#define DMA2D_OUT_RO_RAM_CLK_FO_CH0 (BIT(6)) -#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_M (DMA2D_OUT_RO_RAM_CLK_FO_CH0_V << DMA2D_OUT_RO_RAM_CLK_FO_CH0_S) -#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_V 0x00000001U -#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_S 6 - -/** DMA2D_OUT_COLOR_CONVERT_CH0_REG register - * Configures the tx color convert of channel 0 - */ -#define DMA2D_OUT_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x48) -/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S) -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S 0 -/** DMA2D_OUT_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0 (BIT(2)) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V 0x00000001U -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S 2 -/** DMA2D_OUT_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ -#define DMA2D_OUT_COLOR_INPUT_SEL_CH0 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_M (DMA2D_OUT_COLOR_INPUT_SEL_CH0_V << DMA2D_OUT_COLOR_INPUT_SEL_CH0_S) -#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_V 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_S 3 - -/** DMA2D_OUT_SCRAMBLE_CH0_REG register - * Configures the tx scramble of channel 0 - */ -#define DMA2D_OUT_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x4c) -/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S) -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM0_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x50) -/** DMA2D_OUT_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H0_CH0 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH0_M (DMA2D_OUT_COLOR_PARAM_H0_CH0_V << DMA2D_OUT_COLOR_PARAM_H0_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_H0_CH0_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM1_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x54) -/** DMA2D_OUT_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H1_CH0 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH0_M (DMA2D_OUT_COLOR_PARAM_H1_CH0_V << DMA2D_OUT_COLOR_PARAM_H1_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_H1_CH0_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM2_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x58) -/** DMA2D_OUT_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M0_CH0 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH0_M (DMA2D_OUT_COLOR_PARAM_M0_CH0_V << DMA2D_OUT_COLOR_PARAM_M0_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_M0_CH0_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM3_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x5c) -/** DMA2D_OUT_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M1_CH0 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH0_M (DMA2D_OUT_COLOR_PARAM_M1_CH0_V << DMA2D_OUT_COLOR_PARAM_M1_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_M1_CH0_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM4_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x60) -/** DMA2D_OUT_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L0_CH0 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH0_M (DMA2D_OUT_COLOR_PARAM_L0_CH0_V << DMA2D_OUT_COLOR_PARAM_L0_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_L0_CH0_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM5_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x64) -/** DMA2D_OUT_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L1_CH0 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH0_M (DMA2D_OUT_COLOR_PARAM_L1_CH0_V << DMA2D_OUT_COLOR_PARAM_L1_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_L1_CH0_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH0_S 0 - -/** DMA2D_OUT_ETM_CONF_CH0_REG register - * Configures the tx etm of channel 0 - */ -#define DMA2D_OUT_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x68) -/** DMA2D_OUT_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_EN_CH0 (BIT(0)) -#define DMA2D_OUT_ETM_EN_CH0_M (DMA2D_OUT_ETM_EN_CH0_V << DMA2D_OUT_ETM_EN_CH0_S) -#define DMA2D_OUT_ETM_EN_CH0_V 0x00000001U -#define DMA2D_OUT_ETM_EN_CH0_S 0 -/** DMA2D_OUT_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_LOOP_EN_CH0 (BIT(1)) -#define DMA2D_OUT_ETM_LOOP_EN_CH0_M (DMA2D_OUT_ETM_LOOP_EN_CH0_V << DMA2D_OUT_ETM_LOOP_EN_CH0_S) -#define DMA2D_OUT_ETM_LOOP_EN_CH0_V 0x00000001U -#define DMA2D_OUT_ETM_LOOP_EN_CH0_S 1 -/** DMA2D_OUT_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_OUT_DSCR_TASK_MAK_CH0 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH0_M (DMA2D_OUT_DSCR_TASK_MAK_CH0_V << DMA2D_OUT_DSCR_TASK_MAK_CH0_S) -#define DMA2D_OUT_DSCR_TASK_MAK_CH0_V 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH0_S 2 - -/** DMA2D_OUT_DSCR_PORT_BLK_CH0_REG register - * Configures the tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_CH0_REG (DR_REG_DMA2D_BASE + 0x6c) -/** DMA2D_OUT_DSCR_PORT_BLK_H_CH0 : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S) -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S 0 -/** DMA2D_OUT_DSCR_PORT_BLK_V_CH0 : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S) -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S 14 - -/** DMA2D_OUT_CONF0_CH1_REG register - * Configures the tx direction of channel 1 - */ -#define DMA2D_OUT_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x100) -/** DMA2D_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ -#define DMA2D_OUT_AUTO_WRBACK_CH1 (BIT(0)) -#define DMA2D_OUT_AUTO_WRBACK_CH1_M (DMA2D_OUT_AUTO_WRBACK_CH1_V << DMA2D_OUT_AUTO_WRBACK_CH1_S) -#define DMA2D_OUT_AUTO_WRBACK_CH1_V 0x00000001U -#define DMA2D_OUT_AUTO_WRBACK_CH1_S 0 -/** DMA2D_OUT_EOF_MODE_CH1 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ -#define DMA2D_OUT_EOF_MODE_CH1 (BIT(1)) -#define DMA2D_OUT_EOF_MODE_CH1_M (DMA2D_OUT_EOF_MODE_CH1_V << DMA2D_OUT_EOF_MODE_CH1_S) -#define DMA2D_OUT_EOF_MODE_CH1_V 0x00000001U -#define DMA2D_OUT_EOF_MODE_CH1_S 1 -/** DMA2D_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ -#define DMA2D_OUTDSCR_BURST_EN_CH1 (BIT(2)) -#define DMA2D_OUTDSCR_BURST_EN_CH1_M (DMA2D_OUTDSCR_BURST_EN_CH1_V << DMA2D_OUTDSCR_BURST_EN_CH1_S) -#define DMA2D_OUTDSCR_BURST_EN_CH1_V 0x00000001U -#define DMA2D_OUTDSCR_BURST_EN_CH1_S 2 -/** DMA2D_OUT_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_OUT_ECC_AES_EN_CH1 (BIT(3)) -#define DMA2D_OUT_ECC_AES_EN_CH1_M (DMA2D_OUT_ECC_AES_EN_CH1_V << DMA2D_OUT_ECC_AES_EN_CH1_S) -#define DMA2D_OUT_ECC_AES_EN_CH1_V 0x00000001U -#define DMA2D_OUT_ECC_AES_EN_CH1_S 3 -/** DMA2D_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_OUT_CHECK_OWNER_CH1 (BIT(4)) -#define DMA2D_OUT_CHECK_OWNER_CH1_M (DMA2D_OUT_CHECK_OWNER_CH1_V << DMA2D_OUT_CHECK_OWNER_CH1_S) -#define DMA2D_OUT_CHECK_OWNER_CH1_V 0x00000001U -#define DMA2D_OUT_CHECK_OWNER_CH1_S 4 -/** DMA2D_OUT_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_OUT_LOOP_TEST_CH1 (BIT(5)) -#define DMA2D_OUT_LOOP_TEST_CH1_M (DMA2D_OUT_LOOP_TEST_CH1_V << DMA2D_OUT_LOOP_TEST_CH1_S) -#define DMA2D_OUT_LOOP_TEST_CH1_V 0x00000001U -#define DMA2D_OUT_LOOP_TEST_CH1_S 5 -/** DMA2D_OUT_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_OUT_MEM_BURST_LENGTH_CH1 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_M (DMA2D_OUT_MEM_BURST_LENGTH_CH1_V << DMA2D_OUT_MEM_BURST_LENGTH_CH1_S) -#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_V 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_S 6 -/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S) -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S 9 -/** DMA2D_OUT_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_OUT_DSCR_PORT_EN_CH1 (BIT(11)) -#define DMA2D_OUT_DSCR_PORT_EN_CH1_M (DMA2D_OUT_DSCR_PORT_EN_CH1_V << DMA2D_OUT_DSCR_PORT_EN_CH1_S) -#define DMA2D_OUT_DSCR_PORT_EN_CH1_V 0x00000001U -#define DMA2D_OUT_DSCR_PORT_EN_CH1_S 11 -/** DMA2D_OUT_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ -#define DMA2D_OUT_PAGE_BOUND_EN_CH1 (BIT(12)) -#define DMA2D_OUT_PAGE_BOUND_EN_CH1_M (DMA2D_OUT_PAGE_BOUND_EN_CH1_V << DMA2D_OUT_PAGE_BOUND_EN_CH1_S) -#define DMA2D_OUT_PAGE_BOUND_EN_CH1_V 0x00000001U -#define DMA2D_OUT_PAGE_BOUND_EN_CH1_S 12 -/** DMA2D_OUT_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_OUT_REORDER_EN_CH1 (BIT(16)) -#define DMA2D_OUT_REORDER_EN_CH1_M (DMA2D_OUT_REORDER_EN_CH1_V << DMA2D_OUT_REORDER_EN_CH1_S) -#define DMA2D_OUT_REORDER_EN_CH1_V 0x00000001U -#define DMA2D_OUT_REORDER_EN_CH1_S 16 -/** DMA2D_OUT_RST_CH1 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ -#define DMA2D_OUT_RST_CH1 (BIT(24)) -#define DMA2D_OUT_RST_CH1_M (DMA2D_OUT_RST_CH1_V << DMA2D_OUT_RST_CH1_S) -#define DMA2D_OUT_RST_CH1_V 0x00000001U -#define DMA2D_OUT_RST_CH1_S 24 -/** DMA2D_OUT_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_OUT_CMD_DISABLE_CH1 (BIT(25)) -#define DMA2D_OUT_CMD_DISABLE_CH1_M (DMA2D_OUT_CMD_DISABLE_CH1_V << DMA2D_OUT_CMD_DISABLE_CH1_S) -#define DMA2D_OUT_CMD_DISABLE_CH1_V 0x00000001U -#define DMA2D_OUT_CMD_DISABLE_CH1_S 25 -/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1 (BIT(26)) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S 26 - -/** DMA2D_OUT_INT_RAW_CH1_REG register - * Raw interrupt status of TX channel 1 - */ -#define DMA2D_OUT_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x104) -/** DMA2D_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ -#define DMA2D_OUT_DONE_CH1_INT_RAW (BIT(0)) -#define DMA2D_OUT_DONE_CH1_INT_RAW_M (DMA2D_OUT_DONE_CH1_INT_RAW_V << DMA2D_OUT_DONE_CH1_INT_RAW_S) -#define DMA2D_OUT_DONE_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DONE_CH1_INT_RAW_S 0 -/** DMA2D_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ -#define DMA2D_OUT_EOF_CH1_INT_RAW (BIT(1)) -#define DMA2D_OUT_EOF_CH1_INT_RAW_M (DMA2D_OUT_EOF_CH1_INT_RAW_V << DMA2D_OUT_EOF_CH1_INT_RAW_S) -#define DMA2D_OUT_EOF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_EOF_CH1_INT_RAW_S 1 -/** DMA2D_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ -#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S 12 - -/** DMA2D_OUT_INT_ENA_CH1_REG register - * Interrupt enable bits of TX channel 1 - */ -#define DMA2D_OUT_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x108) -/** DMA2D_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH1_INT_ENA (BIT(0)) -#define DMA2D_OUT_DONE_CH1_INT_ENA_M (DMA2D_OUT_DONE_CH1_INT_ENA_V << DMA2D_OUT_DONE_CH1_INT_ENA_S) -#define DMA2D_OUT_DONE_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DONE_CH1_INT_ENA_S 0 -/** DMA2D_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH1_INT_ENA (BIT(1)) -#define DMA2D_OUT_EOF_CH1_INT_ENA_M (DMA2D_OUT_EOF_CH1_INT_ENA_V << DMA2D_OUT_EOF_CH1_INT_ENA_S) -#define DMA2D_OUT_EOF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_EOF_CH1_INT_ENA_S 1 -/** DMA2D_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S 12 - -/** DMA2D_OUT_INT_ST_CH1_REG register - * Masked interrupt status of TX channel 1 - */ -#define DMA2D_OUT_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x10c) -/** DMA2D_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH1_INT_ST (BIT(0)) -#define DMA2D_OUT_DONE_CH1_INT_ST_M (DMA2D_OUT_DONE_CH1_INT_ST_V << DMA2D_OUT_DONE_CH1_INT_ST_S) -#define DMA2D_OUT_DONE_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_DONE_CH1_INT_ST_S 0 -/** DMA2D_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH1_INT_ST (BIT(1)) -#define DMA2D_OUT_EOF_CH1_INT_ST_M (DMA2D_OUT_EOF_CH1_INT_ST_V << DMA2D_OUT_EOF_CH1_INT_ST_S) -#define DMA2D_OUT_EOF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_EOF_CH1_INT_ST_S 1 -/** DMA2D_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S 12 - -/** DMA2D_OUT_INT_CLR_CH1_REG register - * Interrupt clear bits of TX channel 1 - */ -#define DMA2D_OUT_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x110) -/** DMA2D_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH1_INT_CLR (BIT(0)) -#define DMA2D_OUT_DONE_CH1_INT_CLR_M (DMA2D_OUT_DONE_CH1_INT_CLR_V << DMA2D_OUT_DONE_CH1_INT_CLR_S) -#define DMA2D_OUT_DONE_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DONE_CH1_INT_CLR_S 0 -/** DMA2D_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH1_INT_CLR (BIT(1)) -#define DMA2D_OUT_EOF_CH1_INT_CLR_M (DMA2D_OUT_EOF_CH1_INT_CLR_V << DMA2D_OUT_EOF_CH1_INT_CLR_S) -#define DMA2D_OUT_EOF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_EOF_CH1_INT_CLR_S 1 -/** DMA2D_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S 12 - -/** DMA2D_OUTFIFO_STATUS_CH1_REG register - * Represents the status of the tx fifo of channel 1 - */ -#define DMA2D_OUTFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x114) -/** DMA2D_OUTFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L2_CH1 (BIT(0)) -#define DMA2D_OUTFIFO_FULL_L2_CH1_M (DMA2D_OUTFIFO_FULL_L2_CH1_V << DMA2D_OUTFIFO_FULL_L2_CH1_S) -#define DMA2D_OUTFIFO_FULL_L2_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L2_CH1_S 0 -/** DMA2D_OUTFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L2_CH1 (BIT(1)) -#define DMA2D_OUTFIFO_EMPTY_L2_CH1_M (DMA2D_OUTFIFO_EMPTY_L2_CH1_V << DMA2D_OUTFIFO_EMPTY_L2_CH1_S) -#define DMA2D_OUTFIFO_EMPTY_L2_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L2_CH1_S 1 -/** DMA2D_OUTFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L2_CH1 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH1_M (DMA2D_OUTFIFO_CNT_L2_CH1_V << DMA2D_OUTFIFO_CNT_L2_CH1_S) -#define DMA2D_OUTFIFO_CNT_L2_CH1_V 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH1_S 2 -/** DMA2D_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_1B_CH1 (BIT(7)) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_M (DMA2D_OUT_REMAIN_UNDER_1B_CH1_V << DMA2D_OUT_REMAIN_UNDER_1B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_S 7 -/** DMA2D_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_2B_CH1 (BIT(8)) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_M (DMA2D_OUT_REMAIN_UNDER_2B_CH1_V << DMA2D_OUT_REMAIN_UNDER_2B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_S 8 -/** DMA2D_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_3B_CH1 (BIT(9)) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_M (DMA2D_OUT_REMAIN_UNDER_3B_CH1_V << DMA2D_OUT_REMAIN_UNDER_3B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_S 9 -/** DMA2D_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_4B_CH1 (BIT(10)) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_M (DMA2D_OUT_REMAIN_UNDER_4B_CH1_V << DMA2D_OUT_REMAIN_UNDER_4B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_S 10 -/** DMA2D_OUT_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_5B_CH1 (BIT(11)) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_M (DMA2D_OUT_REMAIN_UNDER_5B_CH1_V << DMA2D_OUT_REMAIN_UNDER_5B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_S 11 -/** DMA2D_OUT_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_6B_CH1 (BIT(12)) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_M (DMA2D_OUT_REMAIN_UNDER_6B_CH1_V << DMA2D_OUT_REMAIN_UNDER_6B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_S 12 -/** DMA2D_OUT_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_7B_CH1 (BIT(13)) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_M (DMA2D_OUT_REMAIN_UNDER_7B_CH1_V << DMA2D_OUT_REMAIN_UNDER_7B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_S 13 -/** DMA2D_OUT_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_8B_CH1 (BIT(14)) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_M (DMA2D_OUT_REMAIN_UNDER_8B_CH1_V << DMA2D_OUT_REMAIN_UNDER_8B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_S 14 -/** DMA2D_OUTFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L1_CH1 (BIT(15)) -#define DMA2D_OUTFIFO_FULL_L1_CH1_M (DMA2D_OUTFIFO_FULL_L1_CH1_V << DMA2D_OUTFIFO_FULL_L1_CH1_S) -#define DMA2D_OUTFIFO_FULL_L1_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L1_CH1_S 15 -/** DMA2D_OUTFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L1_CH1 (BIT(16)) -#define DMA2D_OUTFIFO_EMPTY_L1_CH1_M (DMA2D_OUTFIFO_EMPTY_L1_CH1_V << DMA2D_OUTFIFO_EMPTY_L1_CH1_S) -#define DMA2D_OUTFIFO_EMPTY_L1_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L1_CH1_S 16 -/** DMA2D_OUTFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L1_CH1 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH1_M (DMA2D_OUTFIFO_CNT_L1_CH1_V << DMA2D_OUTFIFO_CNT_L1_CH1_S) -#define DMA2D_OUTFIFO_CNT_L1_CH1_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH1_S 17 -/** DMA2D_OUTFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L3_CH1 (BIT(22)) -#define DMA2D_OUTFIFO_FULL_L3_CH1_M (DMA2D_OUTFIFO_FULL_L3_CH1_V << DMA2D_OUTFIFO_FULL_L3_CH1_S) -#define DMA2D_OUTFIFO_FULL_L3_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L3_CH1_S 22 -/** DMA2D_OUTFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L3_CH1 (BIT(23)) -#define DMA2D_OUTFIFO_EMPTY_L3_CH1_M (DMA2D_OUTFIFO_EMPTY_L3_CH1_V << DMA2D_OUTFIFO_EMPTY_L3_CH1_S) -#define DMA2D_OUTFIFO_EMPTY_L3_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L3_CH1_S 23 -/** DMA2D_OUTFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L3_CH1 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH1_M (DMA2D_OUTFIFO_CNT_L3_CH1_V << DMA2D_OUTFIFO_CNT_L3_CH1_S) -#define DMA2D_OUTFIFO_CNT_L3_CH1_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH1_S 24 - -/** DMA2D_OUT_PUSH_CH1_REG register - * Configures the tx fifo of channel 1 - */ -#define DMA2D_OUT_PUSH_CH1_REG (DR_REG_DMA2D_BASE + 0x118) -/** DMA2D_OUTFIFO_WDATA_CH1 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_WDATA_CH1 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH1_M (DMA2D_OUTFIFO_WDATA_CH1_V << DMA2D_OUTFIFO_WDATA_CH1_S) -#define DMA2D_OUTFIFO_WDATA_CH1_V 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH1_S 0 -/** DMA2D_OUTFIFO_PUSH_CH1 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_PUSH_CH1 (BIT(10)) -#define DMA2D_OUTFIFO_PUSH_CH1_M (DMA2D_OUTFIFO_PUSH_CH1_V << DMA2D_OUTFIFO_PUSH_CH1_S) -#define DMA2D_OUTFIFO_PUSH_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_PUSH_CH1_S 10 - -/** DMA2D_OUT_LINK_CONF_CH1_REG register - * Configures the tx descriptor operations of channel 1 - */ -#define DMA2D_OUT_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x11c) -/** DMA2D_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_STOP_CH1 (BIT(20)) -#define DMA2D_OUTLINK_STOP_CH1_M (DMA2D_OUTLINK_STOP_CH1_V << DMA2D_OUTLINK_STOP_CH1_S) -#define DMA2D_OUTLINK_STOP_CH1_V 0x00000001U -#define DMA2D_OUTLINK_STOP_CH1_S 20 -/** DMA2D_OUTLINK_START_CH1 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_START_CH1 (BIT(21)) -#define DMA2D_OUTLINK_START_CH1_M (DMA2D_OUTLINK_START_CH1_V << DMA2D_OUTLINK_START_CH1_S) -#define DMA2D_OUTLINK_START_CH1_V 0x00000001U -#define DMA2D_OUTLINK_START_CH1_S 21 -/** DMA2D_OUTLINK_RESTART_CH1 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ -#define DMA2D_OUTLINK_RESTART_CH1 (BIT(22)) -#define DMA2D_OUTLINK_RESTART_CH1_M (DMA2D_OUTLINK_RESTART_CH1_V << DMA2D_OUTLINK_RESTART_CH1_S) -#define DMA2D_OUTLINK_RESTART_CH1_V 0x00000001U -#define DMA2D_OUTLINK_RESTART_CH1_S 22 -/** DMA2D_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ -#define DMA2D_OUTLINK_PARK_CH1 (BIT(23)) -#define DMA2D_OUTLINK_PARK_CH1_M (DMA2D_OUTLINK_PARK_CH1_V << DMA2D_OUTLINK_PARK_CH1_S) -#define DMA2D_OUTLINK_PARK_CH1_V 0x00000001U -#define DMA2D_OUTLINK_PARK_CH1_S 23 - -/** DMA2D_OUT_LINK_ADDR_CH1_REG register - * Configures the tx descriptor address of channel 1 - */ -#define DMA2D_OUT_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x120) -/** DMA2D_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ -#define DMA2D_OUTLINK_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH1_M (DMA2D_OUTLINK_ADDR_CH1_V << DMA2D_OUTLINK_ADDR_CH1_S) -#define DMA2D_OUTLINK_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH1_S 0 - -/** DMA2D_OUT_STATE_CH1_REG register - * Represents the working status of the tx descriptor of channel 1 - */ -#define DMA2D_OUT_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x124) -/** DMA2D_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ -#define DMA2D_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH1_M (DMA2D_OUTLINK_DSCR_ADDR_CH1_V << DMA2D_OUTLINK_DSCR_ADDR_CH1_S) -#define DMA2D_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH1_S 0 -/** DMA2D_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ -#define DMA2D_OUT_DSCR_STATE_CH1 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH1_M (DMA2D_OUT_DSCR_STATE_CH1_V << DMA2D_OUT_DSCR_STATE_CH1_S) -#define DMA2D_OUT_DSCR_STATE_CH1_V 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH1_S 18 -/** DMA2D_OUT_STATE_CH1 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ -#define DMA2D_OUT_STATE_CH1 0x0000000FU -#define DMA2D_OUT_STATE_CH1_M (DMA2D_OUT_STATE_CH1_V << DMA2D_OUT_STATE_CH1_S) -#define DMA2D_OUT_STATE_CH1_V 0x0000000FU -#define DMA2D_OUT_STATE_CH1_S 20 -/** DMA2D_OUT_RESET_AVAIL_CH1 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_OUT_RESET_AVAIL_CH1 (BIT(24)) -#define DMA2D_OUT_RESET_AVAIL_CH1_M (DMA2D_OUT_RESET_AVAIL_CH1_V << DMA2D_OUT_RESET_AVAIL_CH1_S) -#define DMA2D_OUT_RESET_AVAIL_CH1_V 0x00000001U -#define DMA2D_OUT_RESET_AVAIL_CH1_S 24 - -/** DMA2D_OUT_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 1 - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x128) -/** DMA2D_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH1_M (DMA2D_OUT_EOF_DES_ADDR_CH1_V << DMA2D_OUT_EOF_DES_ADDR_CH1_S) -#define DMA2D_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH1_S 0 - -/** DMA2D_OUT_DSCR_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 1 - */ -#define DMA2D_OUT_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x12c) -/** DMA2D_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ -#define DMA2D_OUTLINK_DSCR_CH1 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH1_M (DMA2D_OUTLINK_DSCR_CH1_V << DMA2D_OUTLINK_DSCR_CH1_S) -#define DMA2D_OUTLINK_DSCR_CH1_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH1_S 0 - -/** DMA2D_OUT_DSCR_BF0_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 1 - */ -#define DMA2D_OUT_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x130) -/** DMA2D_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ -#define DMA2D_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH1_M (DMA2D_OUTLINK_DSCR_BF0_CH1_V << DMA2D_OUTLINK_DSCR_BF0_CH1_S) -#define DMA2D_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH1_S 0 - -/** DMA2D_OUT_DSCR_BF1_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 1 - */ -#define DMA2D_OUT_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x134) -/** DMA2D_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ -#define DMA2D_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH1_M (DMA2D_OUTLINK_DSCR_BF1_CH1_V << DMA2D_OUTLINK_DSCR_BF1_CH1_S) -#define DMA2D_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH1_S 0 - -/** DMA2D_OUT_PERI_SEL_CH1_REG register - * Configures the tx peripheral of channel 1 - */ -#define DMA2D_OUT_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x138) -/** DMA2D_OUT_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ -#define DMA2D_OUT_PERI_SEL_CH1 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH1_M (DMA2D_OUT_PERI_SEL_CH1_V << DMA2D_OUT_PERI_SEL_CH1_S) -#define DMA2D_OUT_PERI_SEL_CH1_V 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH1_S 0 - -/** DMA2D_OUT_ARB_CH1_REG register - * Configures the tx arbiter of channel 1 - */ -#define DMA2D_OUT_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x13c) -/** DMA2D_OUT_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_OUT_ARB_TOKEN_NUM_CH1 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_M (DMA2D_OUT_ARB_TOKEN_NUM_CH1_V << DMA2D_OUT_ARB_TOKEN_NUM_CH1_S) -#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_V 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_CH1 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH1_M (DMA2D_OUT_ARB_PRIORITY_CH1_V << DMA2D_OUT_ARB_PRIORITY_CH1_S) -#define DMA2D_OUT_ARB_PRIORITY_CH1_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH1_S 4 -/** DMA2D_OUT_ARB_PRIORITY_H_CH1 : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_H_CH1 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH1_M (DMA2D_OUT_ARB_PRIORITY_H_CH1_V << DMA2D_OUT_ARB_PRIORITY_H_CH1_S) -#define DMA2D_OUT_ARB_PRIORITY_H_CH1_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH1_S 6 - -/** DMA2D_OUT_RO_STATUS_CH1_REG register - * Represents the status of the tx reorder module of channel 1 - */ -#define DMA2D_OUT_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x140) -/** DMA2D_OUTFIFO_RO_CNT_CH1 : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ -#define DMA2D_OUTFIFO_RO_CNT_CH1 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH1_M (DMA2D_OUTFIFO_RO_CNT_CH1_V << DMA2D_OUTFIFO_RO_CNT_CH1_S) -#define DMA2D_OUTFIFO_RO_CNT_CH1_V 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH1_S 0 -/** DMA2D_OUT_RO_WR_STATE_CH1 : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_OUT_RO_WR_STATE_CH1 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH1_M (DMA2D_OUT_RO_WR_STATE_CH1_V << DMA2D_OUT_RO_WR_STATE_CH1_S) -#define DMA2D_OUT_RO_WR_STATE_CH1_V 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH1_S 6 -/** DMA2D_OUT_RO_RD_STATE_CH1 : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_OUT_RO_RD_STATE_CH1 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH1_M (DMA2D_OUT_RO_RD_STATE_CH1_V << DMA2D_OUT_RO_RD_STATE_CH1_S) -#define DMA2D_OUT_RO_RD_STATE_CH1_V 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH1_S 8 -/** DMA2D_OUT_PIXEL_BYTE_CH1 : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_OUT_PIXEL_BYTE_CH1 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH1_M (DMA2D_OUT_PIXEL_BYTE_CH1_V << DMA2D_OUT_PIXEL_BYTE_CH1_S) -#define DMA2D_OUT_PIXEL_BYTE_CH1_V 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH1_S 10 -/** DMA2D_OUT_BURST_BLOCK_NUM_CH1 : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ -#define DMA2D_OUT_BURST_BLOCK_NUM_CH1 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_M (DMA2D_OUT_BURST_BLOCK_NUM_CH1_V << DMA2D_OUT_BURST_BLOCK_NUM_CH1_S) -#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_V 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_S 14 - -/** DMA2D_OUT_COLOR_CONVERT_CH1_REG register - * Configures the tx color convert of channel 1 - */ -#define DMA2D_OUT_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x148) -/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S) -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S 0 -/** DMA2D_OUT_COLOR_3B_PROC_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1 (BIT(2)) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V 0x00000001U -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S 2 -/** DMA2D_OUT_COLOR_INPUT_SEL_CH1 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ -#define DMA2D_OUT_COLOR_INPUT_SEL_CH1 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_M (DMA2D_OUT_COLOR_INPUT_SEL_CH1_V << DMA2D_OUT_COLOR_INPUT_SEL_CH1_S) -#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_V 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_S 3 - -/** DMA2D_OUT_SCRAMBLE_CH1_REG register - * Configures the tx scramble of channel 1 - */ -#define DMA2D_OUT_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x14c) -/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S) -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM0_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x150) -/** DMA2D_OUT_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H0_CH1 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH1_M (DMA2D_OUT_COLOR_PARAM_H0_CH1_V << DMA2D_OUT_COLOR_PARAM_H0_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_H0_CH1_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM1_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x154) -/** DMA2D_OUT_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H1_CH1 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH1_M (DMA2D_OUT_COLOR_PARAM_H1_CH1_V << DMA2D_OUT_COLOR_PARAM_H1_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_H1_CH1_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM2_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x158) -/** DMA2D_OUT_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M0_CH1 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH1_M (DMA2D_OUT_COLOR_PARAM_M0_CH1_V << DMA2D_OUT_COLOR_PARAM_M0_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_M0_CH1_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM3_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x15c) -/** DMA2D_OUT_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M1_CH1 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH1_M (DMA2D_OUT_COLOR_PARAM_M1_CH1_V << DMA2D_OUT_COLOR_PARAM_M1_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_M1_CH1_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM4_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x160) -/** DMA2D_OUT_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L0_CH1 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH1_M (DMA2D_OUT_COLOR_PARAM_L0_CH1_V << DMA2D_OUT_COLOR_PARAM_L0_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_L0_CH1_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM5_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x164) -/** DMA2D_OUT_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L1_CH1 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH1_M (DMA2D_OUT_COLOR_PARAM_L1_CH1_V << DMA2D_OUT_COLOR_PARAM_L1_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_L1_CH1_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH1_S 0 - -/** DMA2D_OUT_ETM_CONF_CH1_REG register - * Configures the tx etm of channel 1 - */ -#define DMA2D_OUT_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x168) -/** DMA2D_OUT_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_EN_CH1 (BIT(0)) -#define DMA2D_OUT_ETM_EN_CH1_M (DMA2D_OUT_ETM_EN_CH1_V << DMA2D_OUT_ETM_EN_CH1_S) -#define DMA2D_OUT_ETM_EN_CH1_V 0x00000001U -#define DMA2D_OUT_ETM_EN_CH1_S 0 -/** DMA2D_OUT_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_LOOP_EN_CH1 (BIT(1)) -#define DMA2D_OUT_ETM_LOOP_EN_CH1_M (DMA2D_OUT_ETM_LOOP_EN_CH1_V << DMA2D_OUT_ETM_LOOP_EN_CH1_S) -#define DMA2D_OUT_ETM_LOOP_EN_CH1_V 0x00000001U -#define DMA2D_OUT_ETM_LOOP_EN_CH1_S 1 -/** DMA2D_OUT_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_OUT_DSCR_TASK_MAK_CH1 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH1_M (DMA2D_OUT_DSCR_TASK_MAK_CH1_V << DMA2D_OUT_DSCR_TASK_MAK_CH1_S) -#define DMA2D_OUT_DSCR_TASK_MAK_CH1_V 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH1_S 2 - -/** DMA2D_OUT_DSCR_PORT_BLK_CH1_REG register - * Configures the tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_CH1_REG (DR_REG_DMA2D_BASE + 0x16c) -/** DMA2D_OUT_DSCR_PORT_BLK_H_CH1 : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S) -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S 0 -/** DMA2D_OUT_DSCR_PORT_BLK_V_CH1 : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S) -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S 14 - -/** DMA2D_OUT_CONF0_CH2_REG register - * Configures the tx direction of channel 2 - */ -#define DMA2D_OUT_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x200) -/** DMA2D_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ -#define DMA2D_OUT_AUTO_WRBACK_CH2 (BIT(0)) -#define DMA2D_OUT_AUTO_WRBACK_CH2_M (DMA2D_OUT_AUTO_WRBACK_CH2_V << DMA2D_OUT_AUTO_WRBACK_CH2_S) -#define DMA2D_OUT_AUTO_WRBACK_CH2_V 0x00000001U -#define DMA2D_OUT_AUTO_WRBACK_CH2_S 0 -/** DMA2D_OUT_EOF_MODE_CH2 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ -#define DMA2D_OUT_EOF_MODE_CH2 (BIT(1)) -#define DMA2D_OUT_EOF_MODE_CH2_M (DMA2D_OUT_EOF_MODE_CH2_V << DMA2D_OUT_EOF_MODE_CH2_S) -#define DMA2D_OUT_EOF_MODE_CH2_V 0x00000001U -#define DMA2D_OUT_EOF_MODE_CH2_S 1 -/** DMA2D_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ -#define DMA2D_OUTDSCR_BURST_EN_CH2 (BIT(2)) -#define DMA2D_OUTDSCR_BURST_EN_CH2_M (DMA2D_OUTDSCR_BURST_EN_CH2_V << DMA2D_OUTDSCR_BURST_EN_CH2_S) -#define DMA2D_OUTDSCR_BURST_EN_CH2_V 0x00000001U -#define DMA2D_OUTDSCR_BURST_EN_CH2_S 2 -/** DMA2D_OUT_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_OUT_ECC_AES_EN_CH2 (BIT(3)) -#define DMA2D_OUT_ECC_AES_EN_CH2_M (DMA2D_OUT_ECC_AES_EN_CH2_V << DMA2D_OUT_ECC_AES_EN_CH2_S) -#define DMA2D_OUT_ECC_AES_EN_CH2_V 0x00000001U -#define DMA2D_OUT_ECC_AES_EN_CH2_S 3 -/** DMA2D_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_OUT_CHECK_OWNER_CH2 (BIT(4)) -#define DMA2D_OUT_CHECK_OWNER_CH2_M (DMA2D_OUT_CHECK_OWNER_CH2_V << DMA2D_OUT_CHECK_OWNER_CH2_S) -#define DMA2D_OUT_CHECK_OWNER_CH2_V 0x00000001U -#define DMA2D_OUT_CHECK_OWNER_CH2_S 4 -/** DMA2D_OUT_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_OUT_LOOP_TEST_CH2 (BIT(5)) -#define DMA2D_OUT_LOOP_TEST_CH2_M (DMA2D_OUT_LOOP_TEST_CH2_V << DMA2D_OUT_LOOP_TEST_CH2_S) -#define DMA2D_OUT_LOOP_TEST_CH2_V 0x00000001U -#define DMA2D_OUT_LOOP_TEST_CH2_S 5 -/** DMA2D_OUT_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_OUT_MEM_BURST_LENGTH_CH2 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_M (DMA2D_OUT_MEM_BURST_LENGTH_CH2_V << DMA2D_OUT_MEM_BURST_LENGTH_CH2_S) -#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_V 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_S 6 -/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S) -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S 9 -/** DMA2D_OUT_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_OUT_DSCR_PORT_EN_CH2 (BIT(11)) -#define DMA2D_OUT_DSCR_PORT_EN_CH2_M (DMA2D_OUT_DSCR_PORT_EN_CH2_V << DMA2D_OUT_DSCR_PORT_EN_CH2_S) -#define DMA2D_OUT_DSCR_PORT_EN_CH2_V 0x00000001U -#define DMA2D_OUT_DSCR_PORT_EN_CH2_S 11 -/** DMA2D_OUT_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ -#define DMA2D_OUT_PAGE_BOUND_EN_CH2 (BIT(12)) -#define DMA2D_OUT_PAGE_BOUND_EN_CH2_M (DMA2D_OUT_PAGE_BOUND_EN_CH2_V << DMA2D_OUT_PAGE_BOUND_EN_CH2_S) -#define DMA2D_OUT_PAGE_BOUND_EN_CH2_V 0x00000001U -#define DMA2D_OUT_PAGE_BOUND_EN_CH2_S 12 -/** DMA2D_OUT_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_OUT_REORDER_EN_CH2 (BIT(16)) -#define DMA2D_OUT_REORDER_EN_CH2_M (DMA2D_OUT_REORDER_EN_CH2_V << DMA2D_OUT_REORDER_EN_CH2_S) -#define DMA2D_OUT_REORDER_EN_CH2_V 0x00000001U -#define DMA2D_OUT_REORDER_EN_CH2_S 16 -/** DMA2D_OUT_RST_CH2 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ -#define DMA2D_OUT_RST_CH2 (BIT(24)) -#define DMA2D_OUT_RST_CH2_M (DMA2D_OUT_RST_CH2_V << DMA2D_OUT_RST_CH2_S) -#define DMA2D_OUT_RST_CH2_V 0x00000001U -#define DMA2D_OUT_RST_CH2_S 24 -/** DMA2D_OUT_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_OUT_CMD_DISABLE_CH2 (BIT(25)) -#define DMA2D_OUT_CMD_DISABLE_CH2_M (DMA2D_OUT_CMD_DISABLE_CH2_V << DMA2D_OUT_CMD_DISABLE_CH2_S) -#define DMA2D_OUT_CMD_DISABLE_CH2_V 0x00000001U -#define DMA2D_OUT_CMD_DISABLE_CH2_S 25 -/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2 (BIT(26)) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V 0x00000001U -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S 26 - -/** DMA2D_OUT_INT_RAW_CH2_REG register - * Raw interrupt status of TX channel 2 - */ -#define DMA2D_OUT_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x204) -/** DMA2D_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ -#define DMA2D_OUT_DONE_CH2_INT_RAW (BIT(0)) -#define DMA2D_OUT_DONE_CH2_INT_RAW_M (DMA2D_OUT_DONE_CH2_INT_RAW_V << DMA2D_OUT_DONE_CH2_INT_RAW_S) -#define DMA2D_OUT_DONE_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DONE_CH2_INT_RAW_S 0 -/** DMA2D_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ -#define DMA2D_OUT_EOF_CH2_INT_RAW (BIT(1)) -#define DMA2D_OUT_EOF_CH2_INT_RAW_M (DMA2D_OUT_EOF_CH2_INT_RAW_V << DMA2D_OUT_EOF_CH2_INT_RAW_S) -#define DMA2D_OUT_EOF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_EOF_CH2_INT_RAW_S 1 -/** DMA2D_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ -#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S 12 - -/** DMA2D_OUT_INT_ENA_CH2_REG register - * Interrupt enable bits of TX channel 2 - */ -#define DMA2D_OUT_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x208) -/** DMA2D_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH2_INT_ENA (BIT(0)) -#define DMA2D_OUT_DONE_CH2_INT_ENA_M (DMA2D_OUT_DONE_CH2_INT_ENA_V << DMA2D_OUT_DONE_CH2_INT_ENA_S) -#define DMA2D_OUT_DONE_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DONE_CH2_INT_ENA_S 0 -/** DMA2D_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH2_INT_ENA (BIT(1)) -#define DMA2D_OUT_EOF_CH2_INT_ENA_M (DMA2D_OUT_EOF_CH2_INT_ENA_V << DMA2D_OUT_EOF_CH2_INT_ENA_S) -#define DMA2D_OUT_EOF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_EOF_CH2_INT_ENA_S 1 -/** DMA2D_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S 12 - -/** DMA2D_OUT_INT_ST_CH2_REG register - * Masked interrupt status of TX channel 2 - */ -#define DMA2D_OUT_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x20c) -/** DMA2D_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH2_INT_ST (BIT(0)) -#define DMA2D_OUT_DONE_CH2_INT_ST_M (DMA2D_OUT_DONE_CH2_INT_ST_V << DMA2D_OUT_DONE_CH2_INT_ST_S) -#define DMA2D_OUT_DONE_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_DONE_CH2_INT_ST_S 0 -/** DMA2D_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH2_INT_ST (BIT(1)) -#define DMA2D_OUT_EOF_CH2_INT_ST_M (DMA2D_OUT_EOF_CH2_INT_ST_V << DMA2D_OUT_EOF_CH2_INT_ST_S) -#define DMA2D_OUT_EOF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_EOF_CH2_INT_ST_S 1 -/** DMA2D_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S 12 - -/** DMA2D_OUT_INT_CLR_CH2_REG register - * Interrupt clear bits of TX channel 2 - */ -#define DMA2D_OUT_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x210) -/** DMA2D_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH2_INT_CLR (BIT(0)) -#define DMA2D_OUT_DONE_CH2_INT_CLR_M (DMA2D_OUT_DONE_CH2_INT_CLR_V << DMA2D_OUT_DONE_CH2_INT_CLR_S) -#define DMA2D_OUT_DONE_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DONE_CH2_INT_CLR_S 0 -/** DMA2D_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH2_INT_CLR (BIT(1)) -#define DMA2D_OUT_EOF_CH2_INT_CLR_M (DMA2D_OUT_EOF_CH2_INT_CLR_V << DMA2D_OUT_EOF_CH2_INT_CLR_S) -#define DMA2D_OUT_EOF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_EOF_CH2_INT_CLR_S 1 -/** DMA2D_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S 12 - -/** DMA2D_OUTFIFO_STATUS_CH2_REG register - * Represents the status of the tx fifo of channel 2 - */ -#define DMA2D_OUTFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x214) -/** DMA2D_OUTFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L2_CH2 (BIT(0)) -#define DMA2D_OUTFIFO_FULL_L2_CH2_M (DMA2D_OUTFIFO_FULL_L2_CH2_V << DMA2D_OUTFIFO_FULL_L2_CH2_S) -#define DMA2D_OUTFIFO_FULL_L2_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L2_CH2_S 0 -/** DMA2D_OUTFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L2_CH2 (BIT(1)) -#define DMA2D_OUTFIFO_EMPTY_L2_CH2_M (DMA2D_OUTFIFO_EMPTY_L2_CH2_V << DMA2D_OUTFIFO_EMPTY_L2_CH2_S) -#define DMA2D_OUTFIFO_EMPTY_L2_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L2_CH2_S 1 -/** DMA2D_OUTFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L2_CH2 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH2_M (DMA2D_OUTFIFO_CNT_L2_CH2_V << DMA2D_OUTFIFO_CNT_L2_CH2_S) -#define DMA2D_OUTFIFO_CNT_L2_CH2_V 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH2_S 2 -/** DMA2D_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_1B_CH2 (BIT(7)) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_M (DMA2D_OUT_REMAIN_UNDER_1B_CH2_V << DMA2D_OUT_REMAIN_UNDER_1B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_S 7 -/** DMA2D_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_2B_CH2 (BIT(8)) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_M (DMA2D_OUT_REMAIN_UNDER_2B_CH2_V << DMA2D_OUT_REMAIN_UNDER_2B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_S 8 -/** DMA2D_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_3B_CH2 (BIT(9)) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_M (DMA2D_OUT_REMAIN_UNDER_3B_CH2_V << DMA2D_OUT_REMAIN_UNDER_3B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_S 9 -/** DMA2D_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_4B_CH2 (BIT(10)) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_M (DMA2D_OUT_REMAIN_UNDER_4B_CH2_V << DMA2D_OUT_REMAIN_UNDER_4B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_S 10 -/** DMA2D_OUT_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_5B_CH2 (BIT(11)) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_M (DMA2D_OUT_REMAIN_UNDER_5B_CH2_V << DMA2D_OUT_REMAIN_UNDER_5B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_S 11 -/** DMA2D_OUT_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_6B_CH2 (BIT(12)) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_M (DMA2D_OUT_REMAIN_UNDER_6B_CH2_V << DMA2D_OUT_REMAIN_UNDER_6B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_S 12 -/** DMA2D_OUT_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_7B_CH2 (BIT(13)) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_M (DMA2D_OUT_REMAIN_UNDER_7B_CH2_V << DMA2D_OUT_REMAIN_UNDER_7B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_S 13 -/** DMA2D_OUT_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_8B_CH2 (BIT(14)) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_M (DMA2D_OUT_REMAIN_UNDER_8B_CH2_V << DMA2D_OUT_REMAIN_UNDER_8B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_S 14 -/** DMA2D_OUTFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L1_CH2 (BIT(15)) -#define DMA2D_OUTFIFO_FULL_L1_CH2_M (DMA2D_OUTFIFO_FULL_L1_CH2_V << DMA2D_OUTFIFO_FULL_L1_CH2_S) -#define DMA2D_OUTFIFO_FULL_L1_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L1_CH2_S 15 -/** DMA2D_OUTFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L1_CH2 (BIT(16)) -#define DMA2D_OUTFIFO_EMPTY_L1_CH2_M (DMA2D_OUTFIFO_EMPTY_L1_CH2_V << DMA2D_OUTFIFO_EMPTY_L1_CH2_S) -#define DMA2D_OUTFIFO_EMPTY_L1_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L1_CH2_S 16 -/** DMA2D_OUTFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L1_CH2 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH2_M (DMA2D_OUTFIFO_CNT_L1_CH2_V << DMA2D_OUTFIFO_CNT_L1_CH2_S) -#define DMA2D_OUTFIFO_CNT_L1_CH2_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH2_S 17 -/** DMA2D_OUTFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L3_CH2 (BIT(22)) -#define DMA2D_OUTFIFO_FULL_L3_CH2_M (DMA2D_OUTFIFO_FULL_L3_CH2_V << DMA2D_OUTFIFO_FULL_L3_CH2_S) -#define DMA2D_OUTFIFO_FULL_L3_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L3_CH2_S 22 -/** DMA2D_OUTFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L3_CH2 (BIT(23)) -#define DMA2D_OUTFIFO_EMPTY_L3_CH2_M (DMA2D_OUTFIFO_EMPTY_L3_CH2_V << DMA2D_OUTFIFO_EMPTY_L3_CH2_S) -#define DMA2D_OUTFIFO_EMPTY_L3_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L3_CH2_S 23 -/** DMA2D_OUTFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L3_CH2 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH2_M (DMA2D_OUTFIFO_CNT_L3_CH2_V << DMA2D_OUTFIFO_CNT_L3_CH2_S) -#define DMA2D_OUTFIFO_CNT_L3_CH2_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH2_S 24 - -/** DMA2D_OUT_PUSH_CH2_REG register - * Configures the tx fifo of channel 2 - */ -#define DMA2D_OUT_PUSH_CH2_REG (DR_REG_DMA2D_BASE + 0x218) -/** DMA2D_OUTFIFO_WDATA_CH2 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_WDATA_CH2 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH2_M (DMA2D_OUTFIFO_WDATA_CH2_V << DMA2D_OUTFIFO_WDATA_CH2_S) -#define DMA2D_OUTFIFO_WDATA_CH2_V 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH2_S 0 -/** DMA2D_OUTFIFO_PUSH_CH2 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_PUSH_CH2 (BIT(10)) -#define DMA2D_OUTFIFO_PUSH_CH2_M (DMA2D_OUTFIFO_PUSH_CH2_V << DMA2D_OUTFIFO_PUSH_CH2_S) -#define DMA2D_OUTFIFO_PUSH_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_PUSH_CH2_S 10 - -/** DMA2D_OUT_LINK_CONF_CH2_REG register - * Configures the tx descriptor operations of channel 2 - */ -#define DMA2D_OUT_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x21c) -/** DMA2D_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_STOP_CH2 (BIT(20)) -#define DMA2D_OUTLINK_STOP_CH2_M (DMA2D_OUTLINK_STOP_CH2_V << DMA2D_OUTLINK_STOP_CH2_S) -#define DMA2D_OUTLINK_STOP_CH2_V 0x00000001U -#define DMA2D_OUTLINK_STOP_CH2_S 20 -/** DMA2D_OUTLINK_START_CH2 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_START_CH2 (BIT(21)) -#define DMA2D_OUTLINK_START_CH2_M (DMA2D_OUTLINK_START_CH2_V << DMA2D_OUTLINK_START_CH2_S) -#define DMA2D_OUTLINK_START_CH2_V 0x00000001U -#define DMA2D_OUTLINK_START_CH2_S 21 -/** DMA2D_OUTLINK_RESTART_CH2 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ -#define DMA2D_OUTLINK_RESTART_CH2 (BIT(22)) -#define DMA2D_OUTLINK_RESTART_CH2_M (DMA2D_OUTLINK_RESTART_CH2_V << DMA2D_OUTLINK_RESTART_CH2_S) -#define DMA2D_OUTLINK_RESTART_CH2_V 0x00000001U -#define DMA2D_OUTLINK_RESTART_CH2_S 22 -/** DMA2D_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ -#define DMA2D_OUTLINK_PARK_CH2 (BIT(23)) -#define DMA2D_OUTLINK_PARK_CH2_M (DMA2D_OUTLINK_PARK_CH2_V << DMA2D_OUTLINK_PARK_CH2_S) -#define DMA2D_OUTLINK_PARK_CH2_V 0x00000001U -#define DMA2D_OUTLINK_PARK_CH2_S 23 - -/** DMA2D_OUT_LINK_ADDR_CH2_REG register - * Configures the tx descriptor address of channel 2 - */ -#define DMA2D_OUT_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x220) -/** DMA2D_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ -#define DMA2D_OUTLINK_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH2_M (DMA2D_OUTLINK_ADDR_CH2_V << DMA2D_OUTLINK_ADDR_CH2_S) -#define DMA2D_OUTLINK_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH2_S 0 - -/** DMA2D_OUT_STATE_CH2_REG register - * Represents the working status of the tx descriptor of channel 2 - */ -#define DMA2D_OUT_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x224) -/** DMA2D_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ -#define DMA2D_OUTLINK_DSCR_ADDR_CH2 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH2_M (DMA2D_OUTLINK_DSCR_ADDR_CH2_V << DMA2D_OUTLINK_DSCR_ADDR_CH2_S) -#define DMA2D_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH2_S 0 -/** DMA2D_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ -#define DMA2D_OUT_DSCR_STATE_CH2 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH2_M (DMA2D_OUT_DSCR_STATE_CH2_V << DMA2D_OUT_DSCR_STATE_CH2_S) -#define DMA2D_OUT_DSCR_STATE_CH2_V 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH2_S 18 -/** DMA2D_OUT_STATE_CH2 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ -#define DMA2D_OUT_STATE_CH2 0x0000000FU -#define DMA2D_OUT_STATE_CH2_M (DMA2D_OUT_STATE_CH2_V << DMA2D_OUT_STATE_CH2_S) -#define DMA2D_OUT_STATE_CH2_V 0x0000000FU -#define DMA2D_OUT_STATE_CH2_S 20 -/** DMA2D_OUT_RESET_AVAIL_CH2 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_OUT_RESET_AVAIL_CH2 (BIT(24)) -#define DMA2D_OUT_RESET_AVAIL_CH2_M (DMA2D_OUT_RESET_AVAIL_CH2_V << DMA2D_OUT_RESET_AVAIL_CH2_S) -#define DMA2D_OUT_RESET_AVAIL_CH2_V 0x00000001U -#define DMA2D_OUT_RESET_AVAIL_CH2_S 24 - -/** DMA2D_OUT_EOF_DES_ADDR_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 2 - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x228) -/** DMA2D_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH2_M (DMA2D_OUT_EOF_DES_ADDR_CH2_V << DMA2D_OUT_EOF_DES_ADDR_CH2_S) -#define DMA2D_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH2_S 0 - -/** DMA2D_OUT_DSCR_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 2 - */ -#define DMA2D_OUT_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x22c) -/** DMA2D_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ -#define DMA2D_OUTLINK_DSCR_CH2 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH2_M (DMA2D_OUTLINK_DSCR_CH2_V << DMA2D_OUTLINK_DSCR_CH2_S) -#define DMA2D_OUTLINK_DSCR_CH2_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH2_S 0 - -/** DMA2D_OUT_DSCR_BF0_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 2 - */ -#define DMA2D_OUT_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x230) -/** DMA2D_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ -#define DMA2D_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH2_M (DMA2D_OUTLINK_DSCR_BF0_CH2_V << DMA2D_OUTLINK_DSCR_BF0_CH2_S) -#define DMA2D_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH2_S 0 - -/** DMA2D_OUT_DSCR_BF1_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 2 - */ -#define DMA2D_OUT_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x234) -/** DMA2D_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ -#define DMA2D_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH2_M (DMA2D_OUTLINK_DSCR_BF1_CH2_V << DMA2D_OUTLINK_DSCR_BF1_CH2_S) -#define DMA2D_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH2_S 0 - -/** DMA2D_OUT_PERI_SEL_CH2_REG register - * Configures the tx peripheral of channel 2 - */ -#define DMA2D_OUT_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x238) -/** DMA2D_OUT_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ -#define DMA2D_OUT_PERI_SEL_CH2 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH2_M (DMA2D_OUT_PERI_SEL_CH2_V << DMA2D_OUT_PERI_SEL_CH2_S) -#define DMA2D_OUT_PERI_SEL_CH2_V 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH2_S 0 - -/** DMA2D_OUT_ARB_CH2_REG register - * Configures the tx arbiter of channel 2 - */ -#define DMA2D_OUT_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x23c) -/** DMA2D_OUT_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_OUT_ARB_TOKEN_NUM_CH2 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_M (DMA2D_OUT_ARB_TOKEN_NUM_CH2_V << DMA2D_OUT_ARB_TOKEN_NUM_CH2_S) -#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_V 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_CH2 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH2_M (DMA2D_OUT_ARB_PRIORITY_CH2_V << DMA2D_OUT_ARB_PRIORITY_CH2_S) -#define DMA2D_OUT_ARB_PRIORITY_CH2_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH2_S 4 -/** DMA2D_OUT_ARB_PRIORITY_H_CH2 : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_H_CH2 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH2_M (DMA2D_OUT_ARB_PRIORITY_H_CH2_V << DMA2D_OUT_ARB_PRIORITY_H_CH2_S) -#define DMA2D_OUT_ARB_PRIORITY_H_CH2_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH2_S 6 - -/** DMA2D_OUT_RO_STATUS_CH2_REG register - * Represents the status of the tx reorder module of channel 2 - */ -#define DMA2D_OUT_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x240) -/** DMA2D_OUTFIFO_RO_CNT_CH2 : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ -#define DMA2D_OUTFIFO_RO_CNT_CH2 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH2_M (DMA2D_OUTFIFO_RO_CNT_CH2_V << DMA2D_OUTFIFO_RO_CNT_CH2_S) -#define DMA2D_OUTFIFO_RO_CNT_CH2_V 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH2_S 0 -/** DMA2D_OUT_RO_WR_STATE_CH2 : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_OUT_RO_WR_STATE_CH2 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH2_M (DMA2D_OUT_RO_WR_STATE_CH2_V << DMA2D_OUT_RO_WR_STATE_CH2_S) -#define DMA2D_OUT_RO_WR_STATE_CH2_V 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH2_S 6 -/** DMA2D_OUT_RO_RD_STATE_CH2 : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_OUT_RO_RD_STATE_CH2 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH2_M (DMA2D_OUT_RO_RD_STATE_CH2_V << DMA2D_OUT_RO_RD_STATE_CH2_S) -#define DMA2D_OUT_RO_RD_STATE_CH2_V 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH2_S 8 -/** DMA2D_OUT_PIXEL_BYTE_CH2 : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_OUT_PIXEL_BYTE_CH2 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH2_M (DMA2D_OUT_PIXEL_BYTE_CH2_V << DMA2D_OUT_PIXEL_BYTE_CH2_S) -#define DMA2D_OUT_PIXEL_BYTE_CH2_V 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH2_S 10 -/** DMA2D_OUT_BURST_BLOCK_NUM_CH2 : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ -#define DMA2D_OUT_BURST_BLOCK_NUM_CH2 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_M (DMA2D_OUT_BURST_BLOCK_NUM_CH2_V << DMA2D_OUT_BURST_BLOCK_NUM_CH2_S) -#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_V 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_S 14 - -/** DMA2D_OUT_COLOR_CONVERT_CH2_REG register - * Configures the tx color convert of channel 2 - */ -#define DMA2D_OUT_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x248) -/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S) -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S 0 -/** DMA2D_OUT_COLOR_3B_PROC_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2 (BIT(2)) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V 0x00000001U -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S 2 -/** DMA2D_OUT_COLOR_INPUT_SEL_CH2 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ -#define DMA2D_OUT_COLOR_INPUT_SEL_CH2 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_M (DMA2D_OUT_COLOR_INPUT_SEL_CH2_V << DMA2D_OUT_COLOR_INPUT_SEL_CH2_S) -#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_V 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_S 3 - -/** DMA2D_OUT_SCRAMBLE_CH2_REG register - * Configures the tx scramble of channel 2 - */ -#define DMA2D_OUT_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x24c) -/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S) -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM0_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x250) -/** DMA2D_OUT_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H0_CH2 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH2_M (DMA2D_OUT_COLOR_PARAM_H0_CH2_V << DMA2D_OUT_COLOR_PARAM_H0_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_H0_CH2_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM1_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x254) -/** DMA2D_OUT_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H1_CH2 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH2_M (DMA2D_OUT_COLOR_PARAM_H1_CH2_V << DMA2D_OUT_COLOR_PARAM_H1_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_H1_CH2_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM2_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x258) -/** DMA2D_OUT_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M0_CH2 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH2_M (DMA2D_OUT_COLOR_PARAM_M0_CH2_V << DMA2D_OUT_COLOR_PARAM_M0_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_M0_CH2_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM3_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x25c) -/** DMA2D_OUT_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M1_CH2 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH2_M (DMA2D_OUT_COLOR_PARAM_M1_CH2_V << DMA2D_OUT_COLOR_PARAM_M1_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_M1_CH2_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM4_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x260) -/** DMA2D_OUT_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L0_CH2 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH2_M (DMA2D_OUT_COLOR_PARAM_L0_CH2_V << DMA2D_OUT_COLOR_PARAM_L0_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_L0_CH2_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM5_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x264) -/** DMA2D_OUT_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L1_CH2 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH2_M (DMA2D_OUT_COLOR_PARAM_L1_CH2_V << DMA2D_OUT_COLOR_PARAM_L1_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_L1_CH2_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH2_S 0 - -/** DMA2D_OUT_ETM_CONF_CH2_REG register - * Configures the tx etm of channel 2 - */ -#define DMA2D_OUT_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x268) -/** DMA2D_OUT_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_EN_CH2 (BIT(0)) -#define DMA2D_OUT_ETM_EN_CH2_M (DMA2D_OUT_ETM_EN_CH2_V << DMA2D_OUT_ETM_EN_CH2_S) -#define DMA2D_OUT_ETM_EN_CH2_V 0x00000001U -#define DMA2D_OUT_ETM_EN_CH2_S 0 -/** DMA2D_OUT_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_LOOP_EN_CH2 (BIT(1)) -#define DMA2D_OUT_ETM_LOOP_EN_CH2_M (DMA2D_OUT_ETM_LOOP_EN_CH2_V << DMA2D_OUT_ETM_LOOP_EN_CH2_S) -#define DMA2D_OUT_ETM_LOOP_EN_CH2_V 0x00000001U -#define DMA2D_OUT_ETM_LOOP_EN_CH2_S 1 -/** DMA2D_OUT_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_OUT_DSCR_TASK_MAK_CH2 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH2_M (DMA2D_OUT_DSCR_TASK_MAK_CH2_V << DMA2D_OUT_DSCR_TASK_MAK_CH2_S) -#define DMA2D_OUT_DSCR_TASK_MAK_CH2_V 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH2_S 2 - -/** DMA2D_OUT_DSCR_PORT_BLK_CH2_REG register - * Configures the tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_CH2_REG (DR_REG_DMA2D_BASE + 0x26c) -/** DMA2D_OUT_DSCR_PORT_BLK_H_CH2 : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S) -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S 0 -/** DMA2D_OUT_DSCR_PORT_BLK_V_CH2 : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S) -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S 14 - -/** DMA2D_OUT_CONF0_CH3_REG register - * Configures the tx direction of channel 3 - */ -#define DMA2D_OUT_CONF0_CH3_REG (DR_REG_DMA2D_BASE + 0x300) -/** DMA2D_OUT_AUTO_WRBACK_CH3 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ -#define DMA2D_OUT_AUTO_WRBACK_CH3 (BIT(0)) -#define DMA2D_OUT_AUTO_WRBACK_CH3_M (DMA2D_OUT_AUTO_WRBACK_CH3_V << DMA2D_OUT_AUTO_WRBACK_CH3_S) -#define DMA2D_OUT_AUTO_WRBACK_CH3_V 0x00000001U -#define DMA2D_OUT_AUTO_WRBACK_CH3_S 0 -/** DMA2D_OUT_EOF_MODE_CH3 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ -#define DMA2D_OUT_EOF_MODE_CH3 (BIT(1)) -#define DMA2D_OUT_EOF_MODE_CH3_M (DMA2D_OUT_EOF_MODE_CH3_V << DMA2D_OUT_EOF_MODE_CH3_S) -#define DMA2D_OUT_EOF_MODE_CH3_V 0x00000001U -#define DMA2D_OUT_EOF_MODE_CH3_S 1 -/** DMA2D_OUTDSCR_BURST_EN_CH3 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ -#define DMA2D_OUTDSCR_BURST_EN_CH3 (BIT(2)) -#define DMA2D_OUTDSCR_BURST_EN_CH3_M (DMA2D_OUTDSCR_BURST_EN_CH3_V << DMA2D_OUTDSCR_BURST_EN_CH3_S) -#define DMA2D_OUTDSCR_BURST_EN_CH3_V 0x00000001U -#define DMA2D_OUTDSCR_BURST_EN_CH3_S 2 -/** DMA2D_OUT_ECC_AES_EN_CH3 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_OUT_ECC_AES_EN_CH3 (BIT(3)) -#define DMA2D_OUT_ECC_AES_EN_CH3_M (DMA2D_OUT_ECC_AES_EN_CH3_V << DMA2D_OUT_ECC_AES_EN_CH3_S) -#define DMA2D_OUT_ECC_AES_EN_CH3_V 0x00000001U -#define DMA2D_OUT_ECC_AES_EN_CH3_S 3 -/** DMA2D_OUT_CHECK_OWNER_CH3 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_OUT_CHECK_OWNER_CH3 (BIT(4)) -#define DMA2D_OUT_CHECK_OWNER_CH3_M (DMA2D_OUT_CHECK_OWNER_CH3_V << DMA2D_OUT_CHECK_OWNER_CH3_S) -#define DMA2D_OUT_CHECK_OWNER_CH3_V 0x00000001U -#define DMA2D_OUT_CHECK_OWNER_CH3_S 4 -/** DMA2D_OUT_LOOP_TEST_CH3 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_OUT_LOOP_TEST_CH3 (BIT(5)) -#define DMA2D_OUT_LOOP_TEST_CH3_M (DMA2D_OUT_LOOP_TEST_CH3_V << DMA2D_OUT_LOOP_TEST_CH3_S) -#define DMA2D_OUT_LOOP_TEST_CH3_V 0x00000001U -#define DMA2D_OUT_LOOP_TEST_CH3_S 5 -/** DMA2D_OUT_MEM_BURST_LENGTH_CH3 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_OUT_MEM_BURST_LENGTH_CH3 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_M (DMA2D_OUT_MEM_BURST_LENGTH_CH3_V << DMA2D_OUT_MEM_BURST_LENGTH_CH3_S) -#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_V 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_S 6 -/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S) -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S 9 -/** DMA2D_OUT_DSCR_PORT_EN_CH3 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_OUT_DSCR_PORT_EN_CH3 (BIT(11)) -#define DMA2D_OUT_DSCR_PORT_EN_CH3_M (DMA2D_OUT_DSCR_PORT_EN_CH3_V << DMA2D_OUT_DSCR_PORT_EN_CH3_S) -#define DMA2D_OUT_DSCR_PORT_EN_CH3_V 0x00000001U -#define DMA2D_OUT_DSCR_PORT_EN_CH3_S 11 -/** DMA2D_OUT_PAGE_BOUND_EN_CH3 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ -#define DMA2D_OUT_PAGE_BOUND_EN_CH3 (BIT(12)) -#define DMA2D_OUT_PAGE_BOUND_EN_CH3_M (DMA2D_OUT_PAGE_BOUND_EN_CH3_V << DMA2D_OUT_PAGE_BOUND_EN_CH3_S) -#define DMA2D_OUT_PAGE_BOUND_EN_CH3_V 0x00000001U -#define DMA2D_OUT_PAGE_BOUND_EN_CH3_S 12 -/** DMA2D_OUT_REORDER_EN_CH3 : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_OUT_REORDER_EN_CH3 (BIT(16)) -#define DMA2D_OUT_REORDER_EN_CH3_M (DMA2D_OUT_REORDER_EN_CH3_V << DMA2D_OUT_REORDER_EN_CH3_S) -#define DMA2D_OUT_REORDER_EN_CH3_V 0x00000001U -#define DMA2D_OUT_REORDER_EN_CH3_S 16 -/** DMA2D_OUT_RST_CH3 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ -#define DMA2D_OUT_RST_CH3 (BIT(24)) -#define DMA2D_OUT_RST_CH3_M (DMA2D_OUT_RST_CH3_V << DMA2D_OUT_RST_CH3_S) -#define DMA2D_OUT_RST_CH3_V 0x00000001U -#define DMA2D_OUT_RST_CH3_S 24 -/** DMA2D_OUT_CMD_DISABLE_CH3 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_OUT_CMD_DISABLE_CH3 (BIT(25)) -#define DMA2D_OUT_CMD_DISABLE_CH3_M (DMA2D_OUT_CMD_DISABLE_CH3_V << DMA2D_OUT_CMD_DISABLE_CH3_S) -#define DMA2D_OUT_CMD_DISABLE_CH3_V 0x00000001U -#define DMA2D_OUT_CMD_DISABLE_CH3_S 25 -/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 (BIT(26)) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V 0x00000001U -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S 26 - -/** DMA2D_OUT_INT_RAW_CH3_REG register - * Raw interrupt status of TX channel 3 - */ -#define DMA2D_OUT_INT_RAW_CH3_REG (DR_REG_DMA2D_BASE + 0x304) -/** DMA2D_OUT_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ -#define DMA2D_OUT_DONE_CH3_INT_RAW (BIT(0)) -#define DMA2D_OUT_DONE_CH3_INT_RAW_M (DMA2D_OUT_DONE_CH3_INT_RAW_V << DMA2D_OUT_DONE_CH3_INT_RAW_S) -#define DMA2D_OUT_DONE_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DONE_CH3_INT_RAW_S 0 -/** DMA2D_OUT_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ -#define DMA2D_OUT_EOF_CH3_INT_RAW (BIT(1)) -#define DMA2D_OUT_EOF_CH3_INT_RAW_M (DMA2D_OUT_EOF_CH3_INT_RAW_V << DMA2D_OUT_EOF_CH3_INT_RAW_S) -#define DMA2D_OUT_EOF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_EOF_CH3_INT_RAW_S 1 -/** DMA2D_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ -#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S 12 - -/** DMA2D_OUT_INT_ENA_CH3_REG register - * Interrupt enable bits of TX channel 3 - */ -#define DMA2D_OUT_INT_ENA_CH3_REG (DR_REG_DMA2D_BASE + 0x308) -/** DMA2D_OUT_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH3_INT_ENA (BIT(0)) -#define DMA2D_OUT_DONE_CH3_INT_ENA_M (DMA2D_OUT_DONE_CH3_INT_ENA_V << DMA2D_OUT_DONE_CH3_INT_ENA_S) -#define DMA2D_OUT_DONE_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DONE_CH3_INT_ENA_S 0 -/** DMA2D_OUT_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH3_INT_ENA (BIT(1)) -#define DMA2D_OUT_EOF_CH3_INT_ENA_M (DMA2D_OUT_EOF_CH3_INT_ENA_V << DMA2D_OUT_EOF_CH3_INT_ENA_S) -#define DMA2D_OUT_EOF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_EOF_CH3_INT_ENA_S 1 -/** DMA2D_OUT_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S 12 - -/** DMA2D_OUT_INT_ST_CH3_REG register - * Masked interrupt status of TX channel 3 - */ -#define DMA2D_OUT_INT_ST_CH3_REG (DR_REG_DMA2D_BASE + 0x30c) -/** DMA2D_OUT_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH3_INT_ST (BIT(0)) -#define DMA2D_OUT_DONE_CH3_INT_ST_M (DMA2D_OUT_DONE_CH3_INT_ST_V << DMA2D_OUT_DONE_CH3_INT_ST_S) -#define DMA2D_OUT_DONE_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_DONE_CH3_INT_ST_S 0 -/** DMA2D_OUT_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH3_INT_ST (BIT(1)) -#define DMA2D_OUT_EOF_CH3_INT_ST_M (DMA2D_OUT_EOF_CH3_INT_ST_V << DMA2D_OUT_EOF_CH3_INT_ST_S) -#define DMA2D_OUT_EOF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_EOF_CH3_INT_ST_S 1 -/** DMA2D_OUT_DSCR_ERR_CH3_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S 12 - -/** DMA2D_OUT_INT_CLR_CH3_REG register - * Interrupt clear bits of TX channel 3 - */ -#define DMA2D_OUT_INT_CLR_CH3_REG (DR_REG_DMA2D_BASE + 0x310) -/** DMA2D_OUT_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH3_INT_CLR (BIT(0)) -#define DMA2D_OUT_DONE_CH3_INT_CLR_M (DMA2D_OUT_DONE_CH3_INT_CLR_V << DMA2D_OUT_DONE_CH3_INT_CLR_S) -#define DMA2D_OUT_DONE_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DONE_CH3_INT_CLR_S 0 -/** DMA2D_OUT_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH3_INT_CLR (BIT(1)) -#define DMA2D_OUT_EOF_CH3_INT_CLR_M (DMA2D_OUT_EOF_CH3_INT_CLR_V << DMA2D_OUT_EOF_CH3_INT_CLR_S) -#define DMA2D_OUT_EOF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_EOF_CH3_INT_CLR_S 1 -/** DMA2D_OUT_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S 12 - -/** DMA2D_OUTFIFO_STATUS_CH3_REG register - * Represents the status of the tx fifo of channel 3 - */ -#define DMA2D_OUTFIFO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x314) -/** DMA2D_OUTFIFO_FULL_L2_CH3 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L2_CH3 (BIT(0)) -#define DMA2D_OUTFIFO_FULL_L2_CH3_M (DMA2D_OUTFIFO_FULL_L2_CH3_V << DMA2D_OUTFIFO_FULL_L2_CH3_S) -#define DMA2D_OUTFIFO_FULL_L2_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L2_CH3_S 0 -/** DMA2D_OUTFIFO_EMPTY_L2_CH3 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L2_CH3 (BIT(1)) -#define DMA2D_OUTFIFO_EMPTY_L2_CH3_M (DMA2D_OUTFIFO_EMPTY_L2_CH3_V << DMA2D_OUTFIFO_EMPTY_L2_CH3_S) -#define DMA2D_OUTFIFO_EMPTY_L2_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L2_CH3_S 1 -/** DMA2D_OUTFIFO_CNT_L2_CH3 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L2_CH3 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH3_M (DMA2D_OUTFIFO_CNT_L2_CH3_V << DMA2D_OUTFIFO_CNT_L2_CH3_S) -#define DMA2D_OUTFIFO_CNT_L2_CH3_V 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH3_S 2 -/** DMA2D_OUT_REMAIN_UNDER_1B_CH3 : RO; bitpos: [7]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_1B_CH3 (BIT(7)) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_M (DMA2D_OUT_REMAIN_UNDER_1B_CH3_V << DMA2D_OUT_REMAIN_UNDER_1B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_S 7 -/** DMA2D_OUT_REMAIN_UNDER_2B_CH3 : RO; bitpos: [8]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_2B_CH3 (BIT(8)) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_M (DMA2D_OUT_REMAIN_UNDER_2B_CH3_V << DMA2D_OUT_REMAIN_UNDER_2B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_S 8 -/** DMA2D_OUT_REMAIN_UNDER_3B_CH3 : RO; bitpos: [9]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_3B_CH3 (BIT(9)) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_M (DMA2D_OUT_REMAIN_UNDER_3B_CH3_V << DMA2D_OUT_REMAIN_UNDER_3B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_S 9 -/** DMA2D_OUT_REMAIN_UNDER_4B_CH3 : RO; bitpos: [10]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_4B_CH3 (BIT(10)) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_M (DMA2D_OUT_REMAIN_UNDER_4B_CH3_V << DMA2D_OUT_REMAIN_UNDER_4B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_S 10 -/** DMA2D_OUT_REMAIN_UNDER_5B_CH3 : RO; bitpos: [11]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_5B_CH3 (BIT(11)) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_M (DMA2D_OUT_REMAIN_UNDER_5B_CH3_V << DMA2D_OUT_REMAIN_UNDER_5B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_S 11 -/** DMA2D_OUT_REMAIN_UNDER_6B_CH3 : RO; bitpos: [12]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_6B_CH3 (BIT(12)) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_M (DMA2D_OUT_REMAIN_UNDER_6B_CH3_V << DMA2D_OUT_REMAIN_UNDER_6B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_S 12 -/** DMA2D_OUT_REMAIN_UNDER_7B_CH3 : RO; bitpos: [13]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_7B_CH3 (BIT(13)) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_M (DMA2D_OUT_REMAIN_UNDER_7B_CH3_V << DMA2D_OUT_REMAIN_UNDER_7B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_S 13 -/** DMA2D_OUT_REMAIN_UNDER_8B_CH3 : RO; bitpos: [14]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_8B_CH3 (BIT(14)) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_M (DMA2D_OUT_REMAIN_UNDER_8B_CH3_V << DMA2D_OUT_REMAIN_UNDER_8B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_S 14 -/** DMA2D_OUTFIFO_FULL_L1_CH3 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L1_CH3 (BIT(15)) -#define DMA2D_OUTFIFO_FULL_L1_CH3_M (DMA2D_OUTFIFO_FULL_L1_CH3_V << DMA2D_OUTFIFO_FULL_L1_CH3_S) -#define DMA2D_OUTFIFO_FULL_L1_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L1_CH3_S 15 -/** DMA2D_OUTFIFO_EMPTY_L1_CH3 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L1_CH3 (BIT(16)) -#define DMA2D_OUTFIFO_EMPTY_L1_CH3_M (DMA2D_OUTFIFO_EMPTY_L1_CH3_V << DMA2D_OUTFIFO_EMPTY_L1_CH3_S) -#define DMA2D_OUTFIFO_EMPTY_L1_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L1_CH3_S 16 -/** DMA2D_OUTFIFO_CNT_L1_CH3 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L1_CH3 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH3_M (DMA2D_OUTFIFO_CNT_L1_CH3_V << DMA2D_OUTFIFO_CNT_L1_CH3_S) -#define DMA2D_OUTFIFO_CNT_L1_CH3_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH3_S 17 -/** DMA2D_OUTFIFO_FULL_L3_CH3 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L3_CH3 (BIT(22)) -#define DMA2D_OUTFIFO_FULL_L3_CH3_M (DMA2D_OUTFIFO_FULL_L3_CH3_V << DMA2D_OUTFIFO_FULL_L3_CH3_S) -#define DMA2D_OUTFIFO_FULL_L3_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L3_CH3_S 22 -/** DMA2D_OUTFIFO_EMPTY_L3_CH3 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L3_CH3 (BIT(23)) -#define DMA2D_OUTFIFO_EMPTY_L3_CH3_M (DMA2D_OUTFIFO_EMPTY_L3_CH3_V << DMA2D_OUTFIFO_EMPTY_L3_CH3_S) -#define DMA2D_OUTFIFO_EMPTY_L3_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L3_CH3_S 23 -/** DMA2D_OUTFIFO_CNT_L3_CH3 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L3_CH3 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH3_M (DMA2D_OUTFIFO_CNT_L3_CH3_V << DMA2D_OUTFIFO_CNT_L3_CH3_S) -#define DMA2D_OUTFIFO_CNT_L3_CH3_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH3_S 24 - -/** DMA2D_OUT_PUSH_CH3_REG register - * Configures the tx fifo of channel 3 - */ -#define DMA2D_OUT_PUSH_CH3_REG (DR_REG_DMA2D_BASE + 0x318) -/** DMA2D_OUTFIFO_WDATA_CH3 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_WDATA_CH3 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH3_M (DMA2D_OUTFIFO_WDATA_CH3_V << DMA2D_OUTFIFO_WDATA_CH3_S) -#define DMA2D_OUTFIFO_WDATA_CH3_V 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH3_S 0 -/** DMA2D_OUTFIFO_PUSH_CH3 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_PUSH_CH3 (BIT(10)) -#define DMA2D_OUTFIFO_PUSH_CH3_M (DMA2D_OUTFIFO_PUSH_CH3_V << DMA2D_OUTFIFO_PUSH_CH3_S) -#define DMA2D_OUTFIFO_PUSH_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_PUSH_CH3_S 10 - -/** DMA2D_OUT_LINK_CONF_CH3_REG register - * Configures the tx descriptor operations of channel 3 - */ -#define DMA2D_OUT_LINK_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x31c) -/** DMA2D_OUTLINK_STOP_CH3 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_STOP_CH3 (BIT(20)) -#define DMA2D_OUTLINK_STOP_CH3_M (DMA2D_OUTLINK_STOP_CH3_V << DMA2D_OUTLINK_STOP_CH3_S) -#define DMA2D_OUTLINK_STOP_CH3_V 0x00000001U -#define DMA2D_OUTLINK_STOP_CH3_S 20 -/** DMA2D_OUTLINK_START_CH3 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_START_CH3 (BIT(21)) -#define DMA2D_OUTLINK_START_CH3_M (DMA2D_OUTLINK_START_CH3_V << DMA2D_OUTLINK_START_CH3_S) -#define DMA2D_OUTLINK_START_CH3_V 0x00000001U -#define DMA2D_OUTLINK_START_CH3_S 21 -/** DMA2D_OUTLINK_RESTART_CH3 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ -#define DMA2D_OUTLINK_RESTART_CH3 (BIT(22)) -#define DMA2D_OUTLINK_RESTART_CH3_M (DMA2D_OUTLINK_RESTART_CH3_V << DMA2D_OUTLINK_RESTART_CH3_S) -#define DMA2D_OUTLINK_RESTART_CH3_V 0x00000001U -#define DMA2D_OUTLINK_RESTART_CH3_S 22 -/** DMA2D_OUTLINK_PARK_CH3 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ -#define DMA2D_OUTLINK_PARK_CH3 (BIT(23)) -#define DMA2D_OUTLINK_PARK_CH3_M (DMA2D_OUTLINK_PARK_CH3_V << DMA2D_OUTLINK_PARK_CH3_S) -#define DMA2D_OUTLINK_PARK_CH3_V 0x00000001U -#define DMA2D_OUTLINK_PARK_CH3_S 23 - -/** DMA2D_OUT_LINK_ADDR_CH3_REG register - * Configures the tx descriptor address of channel 3 - */ -#define DMA2D_OUT_LINK_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x320) -/** DMA2D_OUTLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ -#define DMA2D_OUTLINK_ADDR_CH3 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH3_M (DMA2D_OUTLINK_ADDR_CH3_V << DMA2D_OUTLINK_ADDR_CH3_S) -#define DMA2D_OUTLINK_ADDR_CH3_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH3_S 0 - -/** DMA2D_OUT_STATE_CH3_REG register - * Represents the working status of the tx descriptor of channel 3 - */ -#define DMA2D_OUT_STATE_CH3_REG (DR_REG_DMA2D_BASE + 0x324) -/** DMA2D_OUTLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ -#define DMA2D_OUTLINK_DSCR_ADDR_CH3 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH3_M (DMA2D_OUTLINK_DSCR_ADDR_CH3_V << DMA2D_OUTLINK_DSCR_ADDR_CH3_S) -#define DMA2D_OUTLINK_DSCR_ADDR_CH3_V 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH3_S 0 -/** DMA2D_OUT_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ -#define DMA2D_OUT_DSCR_STATE_CH3 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH3_M (DMA2D_OUT_DSCR_STATE_CH3_V << DMA2D_OUT_DSCR_STATE_CH3_S) -#define DMA2D_OUT_DSCR_STATE_CH3_V 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH3_S 18 -/** DMA2D_OUT_STATE_CH3 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ -#define DMA2D_OUT_STATE_CH3 0x0000000FU -#define DMA2D_OUT_STATE_CH3_M (DMA2D_OUT_STATE_CH3_V << DMA2D_OUT_STATE_CH3_S) -#define DMA2D_OUT_STATE_CH3_V 0x0000000FU -#define DMA2D_OUT_STATE_CH3_S 20 -/** DMA2D_OUT_RESET_AVAIL_CH3 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_OUT_RESET_AVAIL_CH3 (BIT(24)) -#define DMA2D_OUT_RESET_AVAIL_CH3_M (DMA2D_OUT_RESET_AVAIL_CH3_V << DMA2D_OUT_RESET_AVAIL_CH3_S) -#define DMA2D_OUT_RESET_AVAIL_CH3_V 0x00000001U -#define DMA2D_OUT_RESET_AVAIL_CH3_S 24 - -/** DMA2D_OUT_EOF_DES_ADDR_CH3_REG register - * Represents the address associated with the outlink descriptor of channel 3 - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x328) -/** DMA2D_OUT_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH3 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH3_M (DMA2D_OUT_EOF_DES_ADDR_CH3_V << DMA2D_OUT_EOF_DES_ADDR_CH3_S) -#define DMA2D_OUT_EOF_DES_ADDR_CH3_V 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH3_S 0 - -/** DMA2D_OUT_DSCR_CH3_REG register - * Represents the address associated with the outlink descriptor of channel 3 - */ -#define DMA2D_OUT_DSCR_CH3_REG (DR_REG_DMA2D_BASE + 0x32c) -/** DMA2D_OUTLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ -#define DMA2D_OUTLINK_DSCR_CH3 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH3_M (DMA2D_OUTLINK_DSCR_CH3_V << DMA2D_OUTLINK_DSCR_CH3_S) -#define DMA2D_OUTLINK_DSCR_CH3_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH3_S 0 - -/** DMA2D_OUT_DSCR_BF0_CH3_REG register - * Represents the address associated with the outlink descriptor of channel 3 - */ -#define DMA2D_OUT_DSCR_BF0_CH3_REG (DR_REG_DMA2D_BASE + 0x330) -/** DMA2D_OUTLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ -#define DMA2D_OUTLINK_DSCR_BF0_CH3 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH3_M (DMA2D_OUTLINK_DSCR_BF0_CH3_V << DMA2D_OUTLINK_DSCR_BF0_CH3_S) -#define DMA2D_OUTLINK_DSCR_BF0_CH3_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH3_S 0 - -/** DMA2D_OUT_DSCR_BF1_CH3_REG register - * Represents the address associated with the outlink descriptor of channel 3 - */ -#define DMA2D_OUT_DSCR_BF1_CH3_REG (DR_REG_DMA2D_BASE + 0x334) -/** DMA2D_OUTLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ -#define DMA2D_OUTLINK_DSCR_BF1_CH3 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH3_M (DMA2D_OUTLINK_DSCR_BF1_CH3_V << DMA2D_OUTLINK_DSCR_BF1_CH3_S) -#define DMA2D_OUTLINK_DSCR_BF1_CH3_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH3_S 0 - -/** DMA2D_OUT_PERI_SEL_CH3_REG register - * Configures the tx peripheral of channel 3 - */ -#define DMA2D_OUT_PERI_SEL_CH3_REG (DR_REG_DMA2D_BASE + 0x338) -/** DMA2D_OUT_PERI_SEL_CH3 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ -#define DMA2D_OUT_PERI_SEL_CH3 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH3_M (DMA2D_OUT_PERI_SEL_CH3_V << DMA2D_OUT_PERI_SEL_CH3_S) -#define DMA2D_OUT_PERI_SEL_CH3_V 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH3_S 0 - -/** DMA2D_OUT_ARB_CH3_REG register - * Configures the tx arbiter of channel 3 - */ -#define DMA2D_OUT_ARB_CH3_REG (DR_REG_DMA2D_BASE + 0x33c) -/** DMA2D_OUT_ARB_TOKEN_NUM_CH3 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_OUT_ARB_TOKEN_NUM_CH3 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_M (DMA2D_OUT_ARB_TOKEN_NUM_CH3_V << DMA2D_OUT_ARB_TOKEN_NUM_CH3_S) -#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_V 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH3 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_CH3 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH3_M (DMA2D_OUT_ARB_PRIORITY_CH3_V << DMA2D_OUT_ARB_PRIORITY_CH3_S) -#define DMA2D_OUT_ARB_PRIORITY_CH3_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH3_S 4 -/** DMA2D_OUT_ARB_PRIORITY_H_CH3 : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_H_CH3 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH3_M (DMA2D_OUT_ARB_PRIORITY_H_CH3_V << DMA2D_OUT_ARB_PRIORITY_H_CH3_S) -#define DMA2D_OUT_ARB_PRIORITY_H_CH3_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH3_S 6 - -/** DMA2D_OUT_RO_STATUS_CH3_REG register - * Represents the status of the tx reorder module of channel 3 - */ -#define DMA2D_OUT_RO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x340) -/** DMA2D_OUTFIFO_RO_CNT_CH3 : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ -#define DMA2D_OUTFIFO_RO_CNT_CH3 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH3_M (DMA2D_OUTFIFO_RO_CNT_CH3_V << DMA2D_OUTFIFO_RO_CNT_CH3_S) -#define DMA2D_OUTFIFO_RO_CNT_CH3_V 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH3_S 0 -/** DMA2D_OUT_RO_WR_STATE_CH3 : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_OUT_RO_WR_STATE_CH3 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH3_M (DMA2D_OUT_RO_WR_STATE_CH3_V << DMA2D_OUT_RO_WR_STATE_CH3_S) -#define DMA2D_OUT_RO_WR_STATE_CH3_V 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH3_S 6 -/** DMA2D_OUT_RO_RD_STATE_CH3 : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_OUT_RO_RD_STATE_CH3 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH3_M (DMA2D_OUT_RO_RD_STATE_CH3_V << DMA2D_OUT_RO_RD_STATE_CH3_S) -#define DMA2D_OUT_RO_RD_STATE_CH3_V 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH3_S 8 -/** DMA2D_OUT_PIXEL_BYTE_CH3 : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_OUT_PIXEL_BYTE_CH3 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH3_M (DMA2D_OUT_PIXEL_BYTE_CH3_V << DMA2D_OUT_PIXEL_BYTE_CH3_S) -#define DMA2D_OUT_PIXEL_BYTE_CH3_V 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH3_S 10 -/** DMA2D_OUT_BURST_BLOCK_NUM_CH3 : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ -#define DMA2D_OUT_BURST_BLOCK_NUM_CH3 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_M (DMA2D_OUT_BURST_BLOCK_NUM_CH3_V << DMA2D_OUT_BURST_BLOCK_NUM_CH3_S) -#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_V 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_S 14 - -/** DMA2D_OUT_COLOR_CONVERT_CH3_REG register - * Configures the tx color convert of channel 3 - */ -#define DMA2D_OUT_COLOR_CONVERT_CH3_REG (DR_REG_DMA2D_BASE + 0x348) -/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S) -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S 0 -/** DMA2D_OUT_COLOR_3B_PROC_EN_CH3 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3 (BIT(2)) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V 0x00000001U -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S 2 -/** DMA2D_OUT_COLOR_INPUT_SEL_CH3 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ -#define DMA2D_OUT_COLOR_INPUT_SEL_CH3 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_M (DMA2D_OUT_COLOR_INPUT_SEL_CH3_V << DMA2D_OUT_COLOR_INPUT_SEL_CH3_S) -#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_V 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_S 3 - -/** DMA2D_OUT_SCRAMBLE_CH3_REG register - * Configures the tx scramble of channel 3 - */ -#define DMA2D_OUT_SCRAMBLE_CH3_REG (DR_REG_DMA2D_BASE + 0x34c) -/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S) -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM0_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM0_CH3_REG (DR_REG_DMA2D_BASE + 0x350) -/** DMA2D_OUT_COLOR_PARAM_H0_CH3 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H0_CH3 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH3_M (DMA2D_OUT_COLOR_PARAM_H0_CH3_V << DMA2D_OUT_COLOR_PARAM_H0_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_H0_CH3_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM1_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM1_CH3_REG (DR_REG_DMA2D_BASE + 0x354) -/** DMA2D_OUT_COLOR_PARAM_H1_CH3 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H1_CH3 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH3_M (DMA2D_OUT_COLOR_PARAM_H1_CH3_V << DMA2D_OUT_COLOR_PARAM_H1_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_H1_CH3_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM2_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM2_CH3_REG (DR_REG_DMA2D_BASE + 0x358) -/** DMA2D_OUT_COLOR_PARAM_M0_CH3 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M0_CH3 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH3_M (DMA2D_OUT_COLOR_PARAM_M0_CH3_V << DMA2D_OUT_COLOR_PARAM_M0_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_M0_CH3_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM3_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM3_CH3_REG (DR_REG_DMA2D_BASE + 0x35c) -/** DMA2D_OUT_COLOR_PARAM_M1_CH3 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M1_CH3 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH3_M (DMA2D_OUT_COLOR_PARAM_M1_CH3_V << DMA2D_OUT_COLOR_PARAM_M1_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_M1_CH3_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM4_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM4_CH3_REG (DR_REG_DMA2D_BASE + 0x360) -/** DMA2D_OUT_COLOR_PARAM_L0_CH3 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L0_CH3 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH3_M (DMA2D_OUT_COLOR_PARAM_L0_CH3_V << DMA2D_OUT_COLOR_PARAM_L0_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_L0_CH3_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM5_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM5_CH3_REG (DR_REG_DMA2D_BASE + 0x364) -/** DMA2D_OUT_COLOR_PARAM_L1_CH3 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L1_CH3 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH3_M (DMA2D_OUT_COLOR_PARAM_L1_CH3_V << DMA2D_OUT_COLOR_PARAM_L1_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_L1_CH3_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH3_S 0 - -/** DMA2D_OUT_ETM_CONF_CH3_REG register - * Configures the tx etm of channel 3 - */ -#define DMA2D_OUT_ETM_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x368) -/** DMA2D_OUT_ETM_EN_CH3 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_EN_CH3 (BIT(0)) -#define DMA2D_OUT_ETM_EN_CH3_M (DMA2D_OUT_ETM_EN_CH3_V << DMA2D_OUT_ETM_EN_CH3_S) -#define DMA2D_OUT_ETM_EN_CH3_V 0x00000001U -#define DMA2D_OUT_ETM_EN_CH3_S 0 -/** DMA2D_OUT_ETM_LOOP_EN_CH3 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_LOOP_EN_CH3 (BIT(1)) -#define DMA2D_OUT_ETM_LOOP_EN_CH3_M (DMA2D_OUT_ETM_LOOP_EN_CH3_V << DMA2D_OUT_ETM_LOOP_EN_CH3_S) -#define DMA2D_OUT_ETM_LOOP_EN_CH3_V 0x00000001U -#define DMA2D_OUT_ETM_LOOP_EN_CH3_S 1 -/** DMA2D_OUT_DSCR_TASK_MAK_CH3 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_OUT_DSCR_TASK_MAK_CH3 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH3_M (DMA2D_OUT_DSCR_TASK_MAK_CH3_V << DMA2D_OUT_DSCR_TASK_MAK_CH3_S) -#define DMA2D_OUT_DSCR_TASK_MAK_CH3_V 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH3_S 2 - -/** DMA2D_OUT_DSCR_PORT_BLK_CH3_REG register - * Configures the tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_CH3_REG (DR_REG_DMA2D_BASE + 0x36c) -/** DMA2D_OUT_DSCR_PORT_BLK_H_CH3 : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S) -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S 0 -/** DMA2D_OUT_DSCR_PORT_BLK_V_CH3 : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S) -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S 14 - -/** DMA2D_IN_CONF0_CH0_REG register - * Configures the rx direction of channel 0 - */ -#define DMA2D_IN_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x500) -/** DMA2D_IN_MEM_TRANS_EN_CH0 : R/W; bitpos: [0]; default: 0; - * enable memory trans of the same channel - */ -#define DMA2D_IN_MEM_TRANS_EN_CH0 (BIT(0)) -#define DMA2D_IN_MEM_TRANS_EN_CH0_M (DMA2D_IN_MEM_TRANS_EN_CH0_V << DMA2D_IN_MEM_TRANS_EN_CH0_S) -#define DMA2D_IN_MEM_TRANS_EN_CH0_V 0x00000001U -#define DMA2D_IN_MEM_TRANS_EN_CH0_S 0 -/** DMA2D_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ -#define DMA2D_INDSCR_BURST_EN_CH0 (BIT(2)) -#define DMA2D_INDSCR_BURST_EN_CH0_M (DMA2D_INDSCR_BURST_EN_CH0_V << DMA2D_INDSCR_BURST_EN_CH0_S) -#define DMA2D_INDSCR_BURST_EN_CH0_V 0x00000001U -#define DMA2D_INDSCR_BURST_EN_CH0_S 2 -/** DMA2D_IN_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_IN_ECC_AES_EN_CH0 (BIT(3)) -#define DMA2D_IN_ECC_AES_EN_CH0_M (DMA2D_IN_ECC_AES_EN_CH0_V << DMA2D_IN_ECC_AES_EN_CH0_S) -#define DMA2D_IN_ECC_AES_EN_CH0_V 0x00000001U -#define DMA2D_IN_ECC_AES_EN_CH0_S 3 -/** DMA2D_IN_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_IN_CHECK_OWNER_CH0 (BIT(4)) -#define DMA2D_IN_CHECK_OWNER_CH0_M (DMA2D_IN_CHECK_OWNER_CH0_V << DMA2D_IN_CHECK_OWNER_CH0_S) -#define DMA2D_IN_CHECK_OWNER_CH0_V 0x00000001U -#define DMA2D_IN_CHECK_OWNER_CH0_S 4 -/** DMA2D_IN_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_IN_LOOP_TEST_CH0 (BIT(5)) -#define DMA2D_IN_LOOP_TEST_CH0_M (DMA2D_IN_LOOP_TEST_CH0_V << DMA2D_IN_LOOP_TEST_CH0_S) -#define DMA2D_IN_LOOP_TEST_CH0_V 0x00000001U -#define DMA2D_IN_LOOP_TEST_CH0_S 5 -/** DMA2D_IN_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_IN_MEM_BURST_LENGTH_CH0 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH0_M (DMA2D_IN_MEM_BURST_LENGTH_CH0_V << DMA2D_IN_MEM_BURST_LENGTH_CH0_S) -#define DMA2D_IN_MEM_BURST_LENGTH_CH0_V 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH0_S 6 -/** DMA2D_IN_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0; - * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S) -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S 9 -/** DMA2D_IN_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_IN_DSCR_PORT_EN_CH0 (BIT(11)) -#define DMA2D_IN_DSCR_PORT_EN_CH0_M (DMA2D_IN_DSCR_PORT_EN_CH0_V << DMA2D_IN_DSCR_PORT_EN_CH0_S) -#define DMA2D_IN_DSCR_PORT_EN_CH0_V 0x00000001U -#define DMA2D_IN_DSCR_PORT_EN_CH0_S 11 -/** DMA2D_IN_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ -#define DMA2D_IN_PAGE_BOUND_EN_CH0 (BIT(12)) -#define DMA2D_IN_PAGE_BOUND_EN_CH0_M (DMA2D_IN_PAGE_BOUND_EN_CH0_V << DMA2D_IN_PAGE_BOUND_EN_CH0_S) -#define DMA2D_IN_PAGE_BOUND_EN_CH0_V 0x00000001U -#define DMA2D_IN_PAGE_BOUND_EN_CH0_S 12 -/** DMA2D_IN_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0; - * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_IN_REORDER_EN_CH0 (BIT(16)) -#define DMA2D_IN_REORDER_EN_CH0_M (DMA2D_IN_REORDER_EN_CH0_V << DMA2D_IN_REORDER_EN_CH0_S) -#define DMA2D_IN_REORDER_EN_CH0_V 0x00000001U -#define DMA2D_IN_REORDER_EN_CH0_S 16 -/** DMA2D_IN_RST_CH0 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ -#define DMA2D_IN_RST_CH0 (BIT(24)) -#define DMA2D_IN_RST_CH0_M (DMA2D_IN_RST_CH0_V << DMA2D_IN_RST_CH0_S) -#define DMA2D_IN_RST_CH0_V 0x00000001U -#define DMA2D_IN_RST_CH0_S 24 -/** DMA2D_IN_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_IN_CMD_DISABLE_CH0 (BIT(25)) -#define DMA2D_IN_CMD_DISABLE_CH0_M (DMA2D_IN_CMD_DISABLE_CH0_V << DMA2D_IN_CMD_DISABLE_CH0_S) -#define DMA2D_IN_CMD_DISABLE_CH0_V 0x00000001U -#define DMA2D_IN_CMD_DISABLE_CH0_S 25 -/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 (BIT(26)) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S 26 - -/** DMA2D_IN_INT_RAW_CH0_REG register - * Raw interrupt status of RX channel 0 - */ -#define DMA2D_IN_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x504) -/** DMA2D_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 0. - */ -#define DMA2D_IN_DONE_CH0_INT_RAW (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_RAW_M (DMA2D_IN_DONE_CH0_INT_RAW_V << DMA2D_IN_DONE_CH0_INT_RAW_S) -#define DMA2D_IN_DONE_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_RAW_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 0. - */ -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_M (DMA2D_IN_SUC_EOF_CH0_INT_RAW_V << DMA2D_IN_SUC_EOF_CH0_INT_RAW_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_M (DMA2D_IN_ERR_EOF_CH0_INT_RAW_V << DMA2D_IN_ERR_EOF_CH0_INT_RAW_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 0. - */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S 13 - -/** DMA2D_IN_INT_ENA_CH0_REG register - * Interrupt enable bits of RX channel 0 - */ -#define DMA2D_IN_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x508) -/** DMA2D_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH0_INT_ENA (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_ENA_M (DMA2D_IN_DONE_CH0_INT_ENA_V << DMA2D_IN_DONE_CH0_INT_ENA_S) -#define DMA2D_IN_DONE_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_ENA_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_M (DMA2D_IN_SUC_EOF_CH0_INT_ENA_V << DMA2D_IN_SUC_EOF_CH0_INT_ENA_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_M (DMA2D_IN_ERR_EOF_CH0_INT_ENA_V << DMA2D_IN_ERR_EOF_CH0_INT_ENA_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S 13 - -/** DMA2D_IN_INT_ST_CH0_REG register - * Masked interrupt status of RX channel 0 - */ -#define DMA2D_IN_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0x50c) -/** DMA2D_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH0_INT_ST (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_ST_M (DMA2D_IN_DONE_CH0_INT_ST_V << DMA2D_IN_DONE_CH0_INT_ST_S) -#define DMA2D_IN_DONE_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_ST_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH0_INT_ST (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_ST_M (DMA2D_IN_SUC_EOF_CH0_INT_ST_V << DMA2D_IN_SUC_EOF_CH0_INT_ST_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_ST_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH0_INT_ST (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_ST_M (DMA2D_IN_ERR_EOF_CH0_INT_ST_V << DMA2D_IN_ERR_EOF_CH0_INT_ST_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_ST_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_M (DMA2D_IN_DSCR_ERR_CH0_INT_ST_V << DMA2D_IN_DSCR_ERR_CH0_INT_ST_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S 13 - -/** DMA2D_IN_INT_CLR_CH0_REG register - * Interrupt clear bits of RX channel 0 - */ -#define DMA2D_IN_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x510) -/** DMA2D_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH0_INT_CLR (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_CLR_M (DMA2D_IN_DONE_CH0_INT_CLR_V << DMA2D_IN_DONE_CH0_INT_CLR_S) -#define DMA2D_IN_DONE_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_CLR_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_M (DMA2D_IN_SUC_EOF_CH0_INT_CLR_V << DMA2D_IN_SUC_EOF_CH0_INT_CLR_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_M (DMA2D_IN_ERR_EOF_CH0_INT_CLR_V << DMA2D_IN_ERR_EOF_CH0_INT_CLR_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S 13 - -/** DMA2D_INFIFO_STATUS_CH0_REG register - * Represents the status of the rx fifo of channel 0 - */ -#define DMA2D_INFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x514) -/** DMA2D_INFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ -#define DMA2D_INFIFO_FULL_L2_CH0 (BIT(0)) -#define DMA2D_INFIFO_FULL_L2_CH0_M (DMA2D_INFIFO_FULL_L2_CH0_V << DMA2D_INFIFO_FULL_L2_CH0_S) -#define DMA2D_INFIFO_FULL_L2_CH0_V 0x00000001U -#define DMA2D_INFIFO_FULL_L2_CH0_S 0 -/** DMA2D_INFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ -#define DMA2D_INFIFO_EMPTY_L2_CH0 (BIT(1)) -#define DMA2D_INFIFO_EMPTY_L2_CH0_M (DMA2D_INFIFO_EMPTY_L2_CH0_V << DMA2D_INFIFO_EMPTY_L2_CH0_S) -#define DMA2D_INFIFO_EMPTY_L2_CH0_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L2_CH0_S 1 -/** DMA2D_INFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ -#define DMA2D_INFIFO_CNT_L2_CH0 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH0_M (DMA2D_INFIFO_CNT_L2_CH0_V << DMA2D_INFIFO_CNT_L2_CH0_S) -#define DMA2D_INFIFO_CNT_L2_CH0_V 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH0_S 2 -/** DMA2D_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_1B_CH0 (BIT(7)) -#define DMA2D_IN_REMAIN_UNDER_1B_CH0_M (DMA2D_IN_REMAIN_UNDER_1B_CH0_V << DMA2D_IN_REMAIN_UNDER_1B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_1B_CH0_S 7 -/** DMA2D_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_2B_CH0 (BIT(8)) -#define DMA2D_IN_REMAIN_UNDER_2B_CH0_M (DMA2D_IN_REMAIN_UNDER_2B_CH0_V << DMA2D_IN_REMAIN_UNDER_2B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_2B_CH0_S 8 -/** DMA2D_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_3B_CH0 (BIT(9)) -#define DMA2D_IN_REMAIN_UNDER_3B_CH0_M (DMA2D_IN_REMAIN_UNDER_3B_CH0_V << DMA2D_IN_REMAIN_UNDER_3B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_3B_CH0_S 9 -/** DMA2D_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_4B_CH0 (BIT(10)) -#define DMA2D_IN_REMAIN_UNDER_4B_CH0_M (DMA2D_IN_REMAIN_UNDER_4B_CH0_V << DMA2D_IN_REMAIN_UNDER_4B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_4B_CH0_S 10 -/** DMA2D_IN_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_5B_CH0 (BIT(11)) -#define DMA2D_IN_REMAIN_UNDER_5B_CH0_M (DMA2D_IN_REMAIN_UNDER_5B_CH0_V << DMA2D_IN_REMAIN_UNDER_5B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_5B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_5B_CH0_S 11 -/** DMA2D_IN_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_6B_CH0 (BIT(12)) -#define DMA2D_IN_REMAIN_UNDER_6B_CH0_M (DMA2D_IN_REMAIN_UNDER_6B_CH0_V << DMA2D_IN_REMAIN_UNDER_6B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_6B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_6B_CH0_S 12 -/** DMA2D_IN_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_7B_CH0 (BIT(13)) -#define DMA2D_IN_REMAIN_UNDER_7B_CH0_M (DMA2D_IN_REMAIN_UNDER_7B_CH0_V << DMA2D_IN_REMAIN_UNDER_7B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_7B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_7B_CH0_S 13 -/** DMA2D_IN_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_8B_CH0 (BIT(14)) -#define DMA2D_IN_REMAIN_UNDER_8B_CH0_M (DMA2D_IN_REMAIN_UNDER_8B_CH0_V << DMA2D_IN_REMAIN_UNDER_8B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_8B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_8B_CH0_S 14 -/** DMA2D_INFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L1_CH0 (BIT(15)) -#define DMA2D_INFIFO_FULL_L1_CH0_M (DMA2D_INFIFO_FULL_L1_CH0_V << DMA2D_INFIFO_FULL_L1_CH0_S) -#define DMA2D_INFIFO_FULL_L1_CH0_V 0x00000001U -#define DMA2D_INFIFO_FULL_L1_CH0_S 15 -/** DMA2D_INFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L1_CH0 (BIT(16)) -#define DMA2D_INFIFO_EMPTY_L1_CH0_M (DMA2D_INFIFO_EMPTY_L1_CH0_V << DMA2D_INFIFO_EMPTY_L1_CH0_S) -#define DMA2D_INFIFO_EMPTY_L1_CH0_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L1_CH0_S 16 -/** DMA2D_INFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L1_CH0 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH0_M (DMA2D_INFIFO_CNT_L1_CH0_V << DMA2D_INFIFO_CNT_L1_CH0_S) -#define DMA2D_INFIFO_CNT_L1_CH0_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH0_S 17 -/** DMA2D_INFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L3_CH0 (BIT(22)) -#define DMA2D_INFIFO_FULL_L3_CH0_M (DMA2D_INFIFO_FULL_L3_CH0_V << DMA2D_INFIFO_FULL_L3_CH0_S) -#define DMA2D_INFIFO_FULL_L3_CH0_V 0x00000001U -#define DMA2D_INFIFO_FULL_L3_CH0_S 22 -/** DMA2D_INFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L3_CH0 (BIT(23)) -#define DMA2D_INFIFO_EMPTY_L3_CH0_M (DMA2D_INFIFO_EMPTY_L3_CH0_V << DMA2D_INFIFO_EMPTY_L3_CH0_S) -#define DMA2D_INFIFO_EMPTY_L3_CH0_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L3_CH0_S 23 -/** DMA2D_INFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L3_CH0 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH0_M (DMA2D_INFIFO_CNT_L3_CH0_V << DMA2D_INFIFO_CNT_L3_CH0_S) -#define DMA2D_INFIFO_CNT_L3_CH0_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH0_S 24 - -/** DMA2D_IN_POP_CH0_REG register - * Configures the rx fifo of channel 0 - */ -#define DMA2D_IN_POP_CH0_REG (DR_REG_DMA2D_BASE + 0x518) -/** DMA2D_INFIFO_RDATA_CH0 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_RDATA_CH0 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH0_M (DMA2D_INFIFO_RDATA_CH0_V << DMA2D_INFIFO_RDATA_CH0_S) -#define DMA2D_INFIFO_RDATA_CH0_V 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH0_S 0 -/** DMA2D_INFIFO_POP_CH0 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_POP_CH0 (BIT(11)) -#define DMA2D_INFIFO_POP_CH0_M (DMA2D_INFIFO_POP_CH0_V << DMA2D_INFIFO_POP_CH0_S) -#define DMA2D_INFIFO_POP_CH0_V 0x00000001U -#define DMA2D_INFIFO_POP_CH0_S 11 - -/** DMA2D_IN_LINK_CONF_CH0_REG register - * Configures the rx descriptor operations of channel 0 - */ -#define DMA2D_IN_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x51c) -/** DMA2D_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ -#define DMA2D_INLINK_AUTO_RET_CH0 (BIT(20)) -#define DMA2D_INLINK_AUTO_RET_CH0_M (DMA2D_INLINK_AUTO_RET_CH0_V << DMA2D_INLINK_AUTO_RET_CH0_S) -#define DMA2D_INLINK_AUTO_RET_CH0_V 0x00000001U -#define DMA2D_INLINK_AUTO_RET_CH0_S 20 -/** DMA2D_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_STOP_CH0 (BIT(21)) -#define DMA2D_INLINK_STOP_CH0_M (DMA2D_INLINK_STOP_CH0_V << DMA2D_INLINK_STOP_CH0_S) -#define DMA2D_INLINK_STOP_CH0_V 0x00000001U -#define DMA2D_INLINK_STOP_CH0_S 21 -/** DMA2D_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_START_CH0 (BIT(22)) -#define DMA2D_INLINK_START_CH0_M (DMA2D_INLINK_START_CH0_V << DMA2D_INLINK_START_CH0_S) -#define DMA2D_INLINK_START_CH0_V 0x00000001U -#define DMA2D_INLINK_START_CH0_S 22 -/** DMA2D_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ -#define DMA2D_INLINK_RESTART_CH0 (BIT(23)) -#define DMA2D_INLINK_RESTART_CH0_M (DMA2D_INLINK_RESTART_CH0_V << DMA2D_INLINK_RESTART_CH0_S) -#define DMA2D_INLINK_RESTART_CH0_V 0x00000001U -#define DMA2D_INLINK_RESTART_CH0_S 23 -/** DMA2D_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ -#define DMA2D_INLINK_PARK_CH0 (BIT(24)) -#define DMA2D_INLINK_PARK_CH0_M (DMA2D_INLINK_PARK_CH0_V << DMA2D_INLINK_PARK_CH0_S) -#define DMA2D_INLINK_PARK_CH0_V 0x00000001U -#define DMA2D_INLINK_PARK_CH0_S 24 - -/** DMA2D_IN_LINK_ADDR_CH0_REG register - * Configures the rx descriptor address of channel 0 - */ -#define DMA2D_IN_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x520) -/** DMA2D_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ -#define DMA2D_INLINK_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH0_M (DMA2D_INLINK_ADDR_CH0_V << DMA2D_INLINK_ADDR_CH0_S) -#define DMA2D_INLINK_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH0_S 0 - -/** DMA2D_IN_STATE_CH0_REG register - * Represents the working status of the rx descriptor of channel 0 - */ -#define DMA2D_IN_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x524) -/** DMA2D_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ -#define DMA2D_INLINK_DSCR_ADDR_CH0 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH0_M (DMA2D_INLINK_DSCR_ADDR_CH0_V << DMA2D_INLINK_DSCR_ADDR_CH0_S) -#define DMA2D_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH0_S 0 -/** DMA2D_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define DMA2D_IN_DSCR_STATE_CH0 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH0_M (DMA2D_IN_DSCR_STATE_CH0_V << DMA2D_IN_DSCR_STATE_CH0_S) -#define DMA2D_IN_DSCR_STATE_CH0_V 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH0_S 18 -/** DMA2D_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * reserved - */ -#define DMA2D_IN_STATE_CH0 0x00000007U -#define DMA2D_IN_STATE_CH0_M (DMA2D_IN_STATE_CH0_V << DMA2D_IN_STATE_CH0_S) -#define DMA2D_IN_STATE_CH0_V 0x00000007U -#define DMA2D_IN_STATE_CH0_S 20 -/** DMA2D_IN_RESET_AVAIL_CH0 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_IN_RESET_AVAIL_CH0 (BIT(23)) -#define DMA2D_IN_RESET_AVAIL_CH0_M (DMA2D_IN_RESET_AVAIL_CH0_V << DMA2D_IN_RESET_AVAIL_CH0_S) -#define DMA2D_IN_RESET_AVAIL_CH0_V 0x00000001U -#define DMA2D_IN_RESET_AVAIL_CH0_S 23 - -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x528) -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S) -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S 0 - -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x52c) -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S) -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S 0 - -/** DMA2D_IN_DSCR_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x530) -/** DMA2D_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ -#define DMA2D_INLINK_DSCR_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH0_M (DMA2D_INLINK_DSCR_CH0_V << DMA2D_INLINK_DSCR_CH0_S) -#define DMA2D_INLINK_DSCR_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH0_S 0 - -/** DMA2D_IN_DSCR_BF0_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x534) -/** DMA2D_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ -#define DMA2D_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH0_M (DMA2D_INLINK_DSCR_BF0_CH0_V << DMA2D_INLINK_DSCR_BF0_CH0_S) -#define DMA2D_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH0_S 0 - -/** DMA2D_IN_DSCR_BF1_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x538) -/** DMA2D_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ -#define DMA2D_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH0_M (DMA2D_INLINK_DSCR_BF1_CH0_V << DMA2D_INLINK_DSCR_BF1_CH0_S) -#define DMA2D_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH0_S 0 - -/** DMA2D_IN_PERI_SEL_CH0_REG register - * Configures the rx peripheral of channel 0 - */ -#define DMA2D_IN_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x53c) -/** DMA2D_IN_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Rx channel 0: jpeg 1: - * display-1 2: display-2 7: no choose - */ -#define DMA2D_IN_PERI_SEL_CH0 0x00000007U -#define DMA2D_IN_PERI_SEL_CH0_M (DMA2D_IN_PERI_SEL_CH0_V << DMA2D_IN_PERI_SEL_CH0_S) -#define DMA2D_IN_PERI_SEL_CH0_V 0x00000007U -#define DMA2D_IN_PERI_SEL_CH0_S 0 - -/** DMA2D_IN_ARB_CH0_REG register - * Configures the rx arbiter of channel 0 - */ -#define DMA2D_IN_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x540) -/** DMA2D_IN_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_IN_ARB_TOKEN_NUM_CH0 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH0_M (DMA2D_IN_ARB_TOKEN_NUM_CH0_V << DMA2D_IN_ARB_TOKEN_NUM_CH0_S) -#define DMA2D_IN_ARB_TOKEN_NUM_CH0_V 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH0_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_CH0 (BIT(4)) -#define DMA2D_IN_ARB_PRIORITY_CH0_M (DMA2D_IN_ARB_PRIORITY_CH0_V << DMA2D_IN_ARB_PRIORITY_CH0_S) -#define DMA2D_IN_ARB_PRIORITY_CH0_V 0x00000001U -#define DMA2D_IN_ARB_PRIORITY_CH0_S 4 -/** DMA2D_IN_ARB_PRIORITY_H_CH0 : R/W; bitpos: [7:5]; default: 0; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_H_CH0 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH0_M (DMA2D_IN_ARB_PRIORITY_H_CH0_V << DMA2D_IN_ARB_PRIORITY_H_CH0_S) -#define DMA2D_IN_ARB_PRIORITY_H_CH0_V 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH0_S 5 - -/** DMA2D_IN_RO_STATUS_CH0_REG register - * Represents the status of the rx reorder module of channel 0 - */ -#define DMA2D_IN_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x544) -/** DMA2D_INFIFO_RO_CNT_CH0 : RO; bitpos: [4:0]; default: 0; - * The register stores the byte number of the data in color convert Rx FIFO for - * channel 0. - */ -#define DMA2D_INFIFO_RO_CNT_CH0 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH0_M (DMA2D_INFIFO_RO_CNT_CH0_V << DMA2D_INFIFO_RO_CNT_CH0_S) -#define DMA2D_INFIFO_RO_CNT_CH0_V 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH0_S 0 -/** DMA2D_IN_RO_WR_STATE_CH0 : RO; bitpos: [6:5]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_IN_RO_WR_STATE_CH0 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH0_M (DMA2D_IN_RO_WR_STATE_CH0_V << DMA2D_IN_RO_WR_STATE_CH0_S) -#define DMA2D_IN_RO_WR_STATE_CH0_V 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH0_S 5 -/** DMA2D_IN_RO_RD_STATE_CH0 : RO; bitpos: [8:7]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_IN_RO_RD_STATE_CH0 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH0_M (DMA2D_IN_RO_RD_STATE_CH0_V << DMA2D_IN_RO_RD_STATE_CH0_S) -#define DMA2D_IN_RO_RD_STATE_CH0_V 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH0_S 7 -/** DMA2D_IN_PIXEL_BYTE_CH0 : RO; bitpos: [12:9]; default: 0; - * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_IN_PIXEL_BYTE_CH0 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH0_M (DMA2D_IN_PIXEL_BYTE_CH0_V << DMA2D_IN_PIXEL_BYTE_CH0_S) -#define DMA2D_IN_PIXEL_BYTE_CH0_V 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH0_S 9 -/** DMA2D_IN_BURST_BLOCK_NUM_CH0 : RO; bitpos: [16:13]; default: 0; - * the number of macro blocks contained in a burst of data at RX channel - */ -#define DMA2D_IN_BURST_BLOCK_NUM_CH0 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH0_M (DMA2D_IN_BURST_BLOCK_NUM_CH0_V << DMA2D_IN_BURST_BLOCK_NUM_CH0_S) -#define DMA2D_IN_BURST_BLOCK_NUM_CH0_V 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH0_S 13 - -/** DMA2D_IN_RO_PD_CONF_CH0_REG register - * Configures the rx reorder memory of channel 0 - */ -#define DMA2D_IN_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x548) -/** DMA2D_IN_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0 (BIT(4)) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_M (DMA2D_IN_RO_RAM_FORCE_PD_CH0_V << DMA2D_IN_RO_RAM_FORCE_PD_CH0_S) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_S 4 -/** DMA2D_IN_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0 (BIT(5)) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_M (DMA2D_IN_RO_RAM_FORCE_PU_CH0_V << DMA2D_IN_RO_RAM_FORCE_PU_CH0_S) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_S 5 -/** DMA2D_IN_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ -#define DMA2D_IN_RO_RAM_CLK_FO_CH0 (BIT(6)) -#define DMA2D_IN_RO_RAM_CLK_FO_CH0_M (DMA2D_IN_RO_RAM_CLK_FO_CH0_V << DMA2D_IN_RO_RAM_CLK_FO_CH0_S) -#define DMA2D_IN_RO_RAM_CLK_FO_CH0_V 0x00000001U -#define DMA2D_IN_RO_RAM_CLK_FO_CH0_S 6 - -/** DMA2D_IN_COLOR_CONVERT_CH0_REG register - * Configures the Rx color convert of channel 0 - */ -#define DMA2D_IN_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x54c) -/** DMA2D_IN_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 - */ -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_M (DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S) -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S 0 -/** DMA2D_IN_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0 (BIT(2)) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_M (DMA2D_IN_COLOR_3B_PROC_EN_CH0_V << DMA2D_IN_COLOR_3B_PROC_EN_CH0_S) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_V 0x00000001U -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_S 2 -/** DMA2D_IN_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: YUV422/420 to YUV444 - * 1: YUV422 2: YUV444/420 7: disable color space convert - */ -#define DMA2D_IN_COLOR_INPUT_SEL_CH0 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH0_M (DMA2D_IN_COLOR_INPUT_SEL_CH0_V << DMA2D_IN_COLOR_INPUT_SEL_CH0_S) -#define DMA2D_IN_COLOR_INPUT_SEL_CH0_V 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH0_S 3 - -/** DMA2D_IN_SCRAMBLE_CH0_REG register - * Configures the rx scramble of channel 0 - */ -#define DMA2D_IN_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x550) -/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_M (DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S) -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S 0 -/** DMA2D_IN_SCRAMBLE_SEL_POST_CH0 : R/W; bitpos: [5:3]; default: 0; - * Scramble data after color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : BYTE1-0-2 - * 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_M (DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S) -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S 3 - -/** DMA2D_IN_COLOR_PARAM0_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x554) -/** DMA2D_IN_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H0_CH0 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH0_M (DMA2D_IN_COLOR_PARAM_H0_CH0_V << DMA2D_IN_COLOR_PARAM_H0_CH0_S) -#define DMA2D_IN_COLOR_PARAM_H0_CH0_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM1_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x558) -/** DMA2D_IN_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H1_CH0 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH0_M (DMA2D_IN_COLOR_PARAM_H1_CH0_V << DMA2D_IN_COLOR_PARAM_H1_CH0_S) -#define DMA2D_IN_COLOR_PARAM_H1_CH0_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM2_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x55c) -/** DMA2D_IN_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M0_CH0 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH0_M (DMA2D_IN_COLOR_PARAM_M0_CH0_V << DMA2D_IN_COLOR_PARAM_M0_CH0_S) -#define DMA2D_IN_COLOR_PARAM_M0_CH0_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM3_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x560) -/** DMA2D_IN_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M1_CH0 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH0_M (DMA2D_IN_COLOR_PARAM_M1_CH0_V << DMA2D_IN_COLOR_PARAM_M1_CH0_S) -#define DMA2D_IN_COLOR_PARAM_M1_CH0_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM4_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x564) -/** DMA2D_IN_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L0_CH0 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH0_M (DMA2D_IN_COLOR_PARAM_L0_CH0_V << DMA2D_IN_COLOR_PARAM_L0_CH0_S) -#define DMA2D_IN_COLOR_PARAM_L0_CH0_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM5_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x568) -/** DMA2D_IN_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L1_CH0 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH0_M (DMA2D_IN_COLOR_PARAM_L1_CH0_V << DMA2D_IN_COLOR_PARAM_L1_CH0_S) -#define DMA2D_IN_COLOR_PARAM_L1_CH0_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH0_S 0 - -/** DMA2D_IN_ETM_CONF_CH0_REG register - * Configures the rx etm of channel 0 - */ -#define DMA2D_IN_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x56c) -/** DMA2D_IN_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_EN_CH0 (BIT(0)) -#define DMA2D_IN_ETM_EN_CH0_M (DMA2D_IN_ETM_EN_CH0_V << DMA2D_IN_ETM_EN_CH0_S) -#define DMA2D_IN_ETM_EN_CH0_V 0x00000001U -#define DMA2D_IN_ETM_EN_CH0_S 0 -/** DMA2D_IN_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_LOOP_EN_CH0 (BIT(1)) -#define DMA2D_IN_ETM_LOOP_EN_CH0_M (DMA2D_IN_ETM_LOOP_EN_CH0_V << DMA2D_IN_ETM_LOOP_EN_CH0_S) -#define DMA2D_IN_ETM_LOOP_EN_CH0_V 0x00000001U -#define DMA2D_IN_ETM_LOOP_EN_CH0_S 1 -/** DMA2D_IN_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_IN_DSCR_TASK_MAK_CH0 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH0_M (DMA2D_IN_DSCR_TASK_MAK_CH0_V << DMA2D_IN_DSCR_TASK_MAK_CH0_S) -#define DMA2D_IN_DSCR_TASK_MAK_CH0_V 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH0_S 2 - -/** DMA2D_IN_CONF0_CH1_REG register - * Configures the rx direction of channel 1 - */ -#define DMA2D_IN_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x600) -/** DMA2D_IN_MEM_TRANS_EN_CH1 : R/W; bitpos: [0]; default: 0; - * enable memory trans of the same channel - */ -#define DMA2D_IN_MEM_TRANS_EN_CH1 (BIT(0)) -#define DMA2D_IN_MEM_TRANS_EN_CH1_M (DMA2D_IN_MEM_TRANS_EN_CH1_V << DMA2D_IN_MEM_TRANS_EN_CH1_S) -#define DMA2D_IN_MEM_TRANS_EN_CH1_V 0x00000001U -#define DMA2D_IN_MEM_TRANS_EN_CH1_S 0 -/** DMA2D_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ -#define DMA2D_INDSCR_BURST_EN_CH1 (BIT(2)) -#define DMA2D_INDSCR_BURST_EN_CH1_M (DMA2D_INDSCR_BURST_EN_CH1_V << DMA2D_INDSCR_BURST_EN_CH1_S) -#define DMA2D_INDSCR_BURST_EN_CH1_V 0x00000001U -#define DMA2D_INDSCR_BURST_EN_CH1_S 2 -/** DMA2D_IN_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_IN_ECC_AES_EN_CH1 (BIT(3)) -#define DMA2D_IN_ECC_AES_EN_CH1_M (DMA2D_IN_ECC_AES_EN_CH1_V << DMA2D_IN_ECC_AES_EN_CH1_S) -#define DMA2D_IN_ECC_AES_EN_CH1_V 0x00000001U -#define DMA2D_IN_ECC_AES_EN_CH1_S 3 -/** DMA2D_IN_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_IN_CHECK_OWNER_CH1 (BIT(4)) -#define DMA2D_IN_CHECK_OWNER_CH1_M (DMA2D_IN_CHECK_OWNER_CH1_V << DMA2D_IN_CHECK_OWNER_CH1_S) -#define DMA2D_IN_CHECK_OWNER_CH1_V 0x00000001U -#define DMA2D_IN_CHECK_OWNER_CH1_S 4 -/** DMA2D_IN_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_IN_LOOP_TEST_CH1 (BIT(5)) -#define DMA2D_IN_LOOP_TEST_CH1_M (DMA2D_IN_LOOP_TEST_CH1_V << DMA2D_IN_LOOP_TEST_CH1_S) -#define DMA2D_IN_LOOP_TEST_CH1_V 0x00000001U -#define DMA2D_IN_LOOP_TEST_CH1_S 5 -/** DMA2D_IN_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_IN_MEM_BURST_LENGTH_CH1 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH1_M (DMA2D_IN_MEM_BURST_LENGTH_CH1_V << DMA2D_IN_MEM_BURST_LENGTH_CH1_S) -#define DMA2D_IN_MEM_BURST_LENGTH_CH1_V 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH1_S 6 -/** DMA2D_IN_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0; - * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S) -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S 9 -/** DMA2D_IN_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_IN_DSCR_PORT_EN_CH1 (BIT(11)) -#define DMA2D_IN_DSCR_PORT_EN_CH1_M (DMA2D_IN_DSCR_PORT_EN_CH1_V << DMA2D_IN_DSCR_PORT_EN_CH1_S) -#define DMA2D_IN_DSCR_PORT_EN_CH1_V 0x00000001U -#define DMA2D_IN_DSCR_PORT_EN_CH1_S 11 -/** DMA2D_IN_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ -#define DMA2D_IN_PAGE_BOUND_EN_CH1 (BIT(12)) -#define DMA2D_IN_PAGE_BOUND_EN_CH1_M (DMA2D_IN_PAGE_BOUND_EN_CH1_V << DMA2D_IN_PAGE_BOUND_EN_CH1_S) -#define DMA2D_IN_PAGE_BOUND_EN_CH1_V 0x00000001U -#define DMA2D_IN_PAGE_BOUND_EN_CH1_S 12 -/** DMA2D_IN_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0; - * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_IN_REORDER_EN_CH1 (BIT(16)) -#define DMA2D_IN_REORDER_EN_CH1_M (DMA2D_IN_REORDER_EN_CH1_V << DMA2D_IN_REORDER_EN_CH1_S) -#define DMA2D_IN_REORDER_EN_CH1_V 0x00000001U -#define DMA2D_IN_REORDER_EN_CH1_S 16 -/** DMA2D_IN_RST_CH1 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ -#define DMA2D_IN_RST_CH1 (BIT(24)) -#define DMA2D_IN_RST_CH1_M (DMA2D_IN_RST_CH1_V << DMA2D_IN_RST_CH1_S) -#define DMA2D_IN_RST_CH1_V 0x00000001U -#define DMA2D_IN_RST_CH1_S 24 -/** DMA2D_IN_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_IN_CMD_DISABLE_CH1 (BIT(25)) -#define DMA2D_IN_CMD_DISABLE_CH1_M (DMA2D_IN_CMD_DISABLE_CH1_V << DMA2D_IN_CMD_DISABLE_CH1_S) -#define DMA2D_IN_CMD_DISABLE_CH1_V 0x00000001U -#define DMA2D_IN_CMD_DISABLE_CH1_S 25 -/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 (BIT(26)) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S 26 - -/** DMA2D_IN_INT_RAW_CH1_REG register - * Raw interrupt status of RX channel 1 - */ -#define DMA2D_IN_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x604) -/** DMA2D_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 0. - */ -#define DMA2D_IN_DONE_CH1_INT_RAW (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_RAW_M (DMA2D_IN_DONE_CH1_INT_RAW_V << DMA2D_IN_DONE_CH1_INT_RAW_S) -#define DMA2D_IN_DONE_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_RAW_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 0. - */ -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_M (DMA2D_IN_SUC_EOF_CH1_INT_RAW_V << DMA2D_IN_SUC_EOF_CH1_INT_RAW_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_M (DMA2D_IN_ERR_EOF_CH1_INT_RAW_V << DMA2D_IN_ERR_EOF_CH1_INT_RAW_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 0. - */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S 13 - -/** DMA2D_IN_INT_ENA_CH1_REG register - * Interrupt enable bits of RX channel 1 - */ -#define DMA2D_IN_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x608) -/** DMA2D_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH1_INT_ENA (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_ENA_M (DMA2D_IN_DONE_CH1_INT_ENA_V << DMA2D_IN_DONE_CH1_INT_ENA_S) -#define DMA2D_IN_DONE_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_ENA_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_M (DMA2D_IN_SUC_EOF_CH1_INT_ENA_V << DMA2D_IN_SUC_EOF_CH1_INT_ENA_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_M (DMA2D_IN_ERR_EOF_CH1_INT_ENA_V << DMA2D_IN_ERR_EOF_CH1_INT_ENA_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S 13 - -/** DMA2D_IN_INT_ST_CH1_REG register - * Masked interrupt status of RX channel 1 - */ -#define DMA2D_IN_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x60c) -/** DMA2D_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH1_INT_ST (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_ST_M (DMA2D_IN_DONE_CH1_INT_ST_V << DMA2D_IN_DONE_CH1_INT_ST_S) -#define DMA2D_IN_DONE_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_ST_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH1_INT_ST (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_ST_M (DMA2D_IN_SUC_EOF_CH1_INT_ST_V << DMA2D_IN_SUC_EOF_CH1_INT_ST_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_ST_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH1_INT_ST (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_ST_M (DMA2D_IN_ERR_EOF_CH1_INT_ST_V << DMA2D_IN_ERR_EOF_CH1_INT_ST_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_ST_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_M (DMA2D_IN_DSCR_ERR_CH1_INT_ST_V << DMA2D_IN_DSCR_ERR_CH1_INT_ST_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S 13 - -/** DMA2D_IN_INT_CLR_CH1_REG register - * Interrupt clear bits of RX channel 1 - */ -#define DMA2D_IN_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x610) -/** DMA2D_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH1_INT_CLR (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_CLR_M (DMA2D_IN_DONE_CH1_INT_CLR_V << DMA2D_IN_DONE_CH1_INT_CLR_S) -#define DMA2D_IN_DONE_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_CLR_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_M (DMA2D_IN_SUC_EOF_CH1_INT_CLR_V << DMA2D_IN_SUC_EOF_CH1_INT_CLR_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_M (DMA2D_IN_ERR_EOF_CH1_INT_CLR_V << DMA2D_IN_ERR_EOF_CH1_INT_CLR_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S 13 - -/** DMA2D_INFIFO_STATUS_CH1_REG register - * Represents the status of the rx fifo of channel 1 - */ -#define DMA2D_INFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x614) -/** DMA2D_INFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ -#define DMA2D_INFIFO_FULL_L2_CH1 (BIT(0)) -#define DMA2D_INFIFO_FULL_L2_CH1_M (DMA2D_INFIFO_FULL_L2_CH1_V << DMA2D_INFIFO_FULL_L2_CH1_S) -#define DMA2D_INFIFO_FULL_L2_CH1_V 0x00000001U -#define DMA2D_INFIFO_FULL_L2_CH1_S 0 -/** DMA2D_INFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ -#define DMA2D_INFIFO_EMPTY_L2_CH1 (BIT(1)) -#define DMA2D_INFIFO_EMPTY_L2_CH1_M (DMA2D_INFIFO_EMPTY_L2_CH1_V << DMA2D_INFIFO_EMPTY_L2_CH1_S) -#define DMA2D_INFIFO_EMPTY_L2_CH1_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L2_CH1_S 1 -/** DMA2D_INFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ -#define DMA2D_INFIFO_CNT_L2_CH1 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH1_M (DMA2D_INFIFO_CNT_L2_CH1_V << DMA2D_INFIFO_CNT_L2_CH1_S) -#define DMA2D_INFIFO_CNT_L2_CH1_V 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH1_S 2 -/** DMA2D_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_1B_CH1 (BIT(7)) -#define DMA2D_IN_REMAIN_UNDER_1B_CH1_M (DMA2D_IN_REMAIN_UNDER_1B_CH1_V << DMA2D_IN_REMAIN_UNDER_1B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_1B_CH1_S 7 -/** DMA2D_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_2B_CH1 (BIT(8)) -#define DMA2D_IN_REMAIN_UNDER_2B_CH1_M (DMA2D_IN_REMAIN_UNDER_2B_CH1_V << DMA2D_IN_REMAIN_UNDER_2B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_2B_CH1_S 8 -/** DMA2D_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_3B_CH1 (BIT(9)) -#define DMA2D_IN_REMAIN_UNDER_3B_CH1_M (DMA2D_IN_REMAIN_UNDER_3B_CH1_V << DMA2D_IN_REMAIN_UNDER_3B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_3B_CH1_S 9 -/** DMA2D_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_4B_CH1 (BIT(10)) -#define DMA2D_IN_REMAIN_UNDER_4B_CH1_M (DMA2D_IN_REMAIN_UNDER_4B_CH1_V << DMA2D_IN_REMAIN_UNDER_4B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_4B_CH1_S 10 -/** DMA2D_IN_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_5B_CH1 (BIT(11)) -#define DMA2D_IN_REMAIN_UNDER_5B_CH1_M (DMA2D_IN_REMAIN_UNDER_5B_CH1_V << DMA2D_IN_REMAIN_UNDER_5B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_5B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_5B_CH1_S 11 -/** DMA2D_IN_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_6B_CH1 (BIT(12)) -#define DMA2D_IN_REMAIN_UNDER_6B_CH1_M (DMA2D_IN_REMAIN_UNDER_6B_CH1_V << DMA2D_IN_REMAIN_UNDER_6B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_6B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_6B_CH1_S 12 -/** DMA2D_IN_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_7B_CH1 (BIT(13)) -#define DMA2D_IN_REMAIN_UNDER_7B_CH1_M (DMA2D_IN_REMAIN_UNDER_7B_CH1_V << DMA2D_IN_REMAIN_UNDER_7B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_7B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_7B_CH1_S 13 -/** DMA2D_IN_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_8B_CH1 (BIT(14)) -#define DMA2D_IN_REMAIN_UNDER_8B_CH1_M (DMA2D_IN_REMAIN_UNDER_8B_CH1_V << DMA2D_IN_REMAIN_UNDER_8B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_8B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_8B_CH1_S 14 -/** DMA2D_INFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L1_CH1 (BIT(15)) -#define DMA2D_INFIFO_FULL_L1_CH1_M (DMA2D_INFIFO_FULL_L1_CH1_V << DMA2D_INFIFO_FULL_L1_CH1_S) -#define DMA2D_INFIFO_FULL_L1_CH1_V 0x00000001U -#define DMA2D_INFIFO_FULL_L1_CH1_S 15 -/** DMA2D_INFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L1_CH1 (BIT(16)) -#define DMA2D_INFIFO_EMPTY_L1_CH1_M (DMA2D_INFIFO_EMPTY_L1_CH1_V << DMA2D_INFIFO_EMPTY_L1_CH1_S) -#define DMA2D_INFIFO_EMPTY_L1_CH1_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L1_CH1_S 16 -/** DMA2D_INFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L1_CH1 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH1_M (DMA2D_INFIFO_CNT_L1_CH1_V << DMA2D_INFIFO_CNT_L1_CH1_S) -#define DMA2D_INFIFO_CNT_L1_CH1_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH1_S 17 -/** DMA2D_INFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L3_CH1 (BIT(22)) -#define DMA2D_INFIFO_FULL_L3_CH1_M (DMA2D_INFIFO_FULL_L3_CH1_V << DMA2D_INFIFO_FULL_L3_CH1_S) -#define DMA2D_INFIFO_FULL_L3_CH1_V 0x00000001U -#define DMA2D_INFIFO_FULL_L3_CH1_S 22 -/** DMA2D_INFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L3_CH1 (BIT(23)) -#define DMA2D_INFIFO_EMPTY_L3_CH1_M (DMA2D_INFIFO_EMPTY_L3_CH1_V << DMA2D_INFIFO_EMPTY_L3_CH1_S) -#define DMA2D_INFIFO_EMPTY_L3_CH1_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L3_CH1_S 23 -/** DMA2D_INFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L3_CH1 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH1_M (DMA2D_INFIFO_CNT_L3_CH1_V << DMA2D_INFIFO_CNT_L3_CH1_S) -#define DMA2D_INFIFO_CNT_L3_CH1_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH1_S 24 - -/** DMA2D_IN_POP_CH1_REG register - * Configures the rx fifo of channel 1 - */ -#define DMA2D_IN_POP_CH1_REG (DR_REG_DMA2D_BASE + 0x618) -/** DMA2D_INFIFO_RDATA_CH1 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_RDATA_CH1 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH1_M (DMA2D_INFIFO_RDATA_CH1_V << DMA2D_INFIFO_RDATA_CH1_S) -#define DMA2D_INFIFO_RDATA_CH1_V 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH1_S 0 -/** DMA2D_INFIFO_POP_CH1 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_POP_CH1 (BIT(11)) -#define DMA2D_INFIFO_POP_CH1_M (DMA2D_INFIFO_POP_CH1_V << DMA2D_INFIFO_POP_CH1_S) -#define DMA2D_INFIFO_POP_CH1_V 0x00000001U -#define DMA2D_INFIFO_POP_CH1_S 11 - -/** DMA2D_IN_LINK_CONF_CH1_REG register - * Configures the rx descriptor operations of channel 1 - */ -#define DMA2D_IN_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x61c) -/** DMA2D_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ -#define DMA2D_INLINK_AUTO_RET_CH1 (BIT(20)) -#define DMA2D_INLINK_AUTO_RET_CH1_M (DMA2D_INLINK_AUTO_RET_CH1_V << DMA2D_INLINK_AUTO_RET_CH1_S) -#define DMA2D_INLINK_AUTO_RET_CH1_V 0x00000001U -#define DMA2D_INLINK_AUTO_RET_CH1_S 20 -/** DMA2D_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_STOP_CH1 (BIT(21)) -#define DMA2D_INLINK_STOP_CH1_M (DMA2D_INLINK_STOP_CH1_V << DMA2D_INLINK_STOP_CH1_S) -#define DMA2D_INLINK_STOP_CH1_V 0x00000001U -#define DMA2D_INLINK_STOP_CH1_S 21 -/** DMA2D_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_START_CH1 (BIT(22)) -#define DMA2D_INLINK_START_CH1_M (DMA2D_INLINK_START_CH1_V << DMA2D_INLINK_START_CH1_S) -#define DMA2D_INLINK_START_CH1_V 0x00000001U -#define DMA2D_INLINK_START_CH1_S 22 -/** DMA2D_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ -#define DMA2D_INLINK_RESTART_CH1 (BIT(23)) -#define DMA2D_INLINK_RESTART_CH1_M (DMA2D_INLINK_RESTART_CH1_V << DMA2D_INLINK_RESTART_CH1_S) -#define DMA2D_INLINK_RESTART_CH1_V 0x00000001U -#define DMA2D_INLINK_RESTART_CH1_S 23 -/** DMA2D_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ -#define DMA2D_INLINK_PARK_CH1 (BIT(24)) -#define DMA2D_INLINK_PARK_CH1_M (DMA2D_INLINK_PARK_CH1_V << DMA2D_INLINK_PARK_CH1_S) -#define DMA2D_INLINK_PARK_CH1_V 0x00000001U -#define DMA2D_INLINK_PARK_CH1_S 24 - -/** DMA2D_IN_LINK_ADDR_CH1_REG register - * Configures the rx descriptor address of channel 1 - */ -#define DMA2D_IN_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x620) -/** DMA2D_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ -#define DMA2D_INLINK_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH1_M (DMA2D_INLINK_ADDR_CH1_V << DMA2D_INLINK_ADDR_CH1_S) -#define DMA2D_INLINK_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH1_S 0 - -/** DMA2D_IN_STATE_CH1_REG register - * Represents the working status of the rx descriptor of channel 1 - */ -#define DMA2D_IN_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x624) -/** DMA2D_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ -#define DMA2D_INLINK_DSCR_ADDR_CH1 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH1_M (DMA2D_INLINK_DSCR_ADDR_CH1_V << DMA2D_INLINK_DSCR_ADDR_CH1_S) -#define DMA2D_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH1_S 0 -/** DMA2D_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define DMA2D_IN_DSCR_STATE_CH1 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH1_M (DMA2D_IN_DSCR_STATE_CH1_V << DMA2D_IN_DSCR_STATE_CH1_S) -#define DMA2D_IN_DSCR_STATE_CH1_V 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH1_S 18 -/** DMA2D_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; - * reserved - */ -#define DMA2D_IN_STATE_CH1 0x00000007U -#define DMA2D_IN_STATE_CH1_M (DMA2D_IN_STATE_CH1_V << DMA2D_IN_STATE_CH1_S) -#define DMA2D_IN_STATE_CH1_V 0x00000007U -#define DMA2D_IN_STATE_CH1_S 20 -/** DMA2D_IN_RESET_AVAIL_CH1 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_IN_RESET_AVAIL_CH1 (BIT(23)) -#define DMA2D_IN_RESET_AVAIL_CH1_M (DMA2D_IN_RESET_AVAIL_CH1_V << DMA2D_IN_RESET_AVAIL_CH1_S) -#define DMA2D_IN_RESET_AVAIL_CH1_V 0x00000001U -#define DMA2D_IN_RESET_AVAIL_CH1_S 23 - -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x628) -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S) -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S 0 - -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x62c) -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S) -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S 0 - -/** DMA2D_IN_DSCR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x630) -/** DMA2D_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ -#define DMA2D_INLINK_DSCR_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH1_M (DMA2D_INLINK_DSCR_CH1_V << DMA2D_INLINK_DSCR_CH1_S) -#define DMA2D_INLINK_DSCR_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH1_S 0 - -/** DMA2D_IN_DSCR_BF0_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x634) -/** DMA2D_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ -#define DMA2D_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH1_M (DMA2D_INLINK_DSCR_BF0_CH1_V << DMA2D_INLINK_DSCR_BF0_CH1_S) -#define DMA2D_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH1_S 0 - -/** DMA2D_IN_DSCR_BF1_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x638) -/** DMA2D_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ -#define DMA2D_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH1_M (DMA2D_INLINK_DSCR_BF1_CH1_V << DMA2D_INLINK_DSCR_BF1_CH1_S) -#define DMA2D_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH1_S 0 - -/** DMA2D_IN_PERI_SEL_CH1_REG register - * Configures the rx peripheral of channel 1 - */ -#define DMA2D_IN_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x63c) -/** DMA2D_IN_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Rx channel 0: jpeg 1: - * display-1 2: display-2 7: no choose - */ -#define DMA2D_IN_PERI_SEL_CH1 0x00000007U -#define DMA2D_IN_PERI_SEL_CH1_M (DMA2D_IN_PERI_SEL_CH1_V << DMA2D_IN_PERI_SEL_CH1_S) -#define DMA2D_IN_PERI_SEL_CH1_V 0x00000007U -#define DMA2D_IN_PERI_SEL_CH1_S 0 - -/** DMA2D_IN_ARB_CH1_REG register - * Configures the rx arbiter of channel 1 - */ -#define DMA2D_IN_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x640) -/** DMA2D_IN_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_IN_ARB_TOKEN_NUM_CH1 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH1_M (DMA2D_IN_ARB_TOKEN_NUM_CH1_V << DMA2D_IN_ARB_TOKEN_NUM_CH1_S) -#define DMA2D_IN_ARB_TOKEN_NUM_CH1_V 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH1_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_CH1 (BIT(4)) -#define DMA2D_IN_ARB_PRIORITY_CH1_M (DMA2D_IN_ARB_PRIORITY_CH1_V << DMA2D_IN_ARB_PRIORITY_CH1_S) -#define DMA2D_IN_ARB_PRIORITY_CH1_V 0x00000001U -#define DMA2D_IN_ARB_PRIORITY_CH1_S 4 -/** DMA2D_IN_ARB_PRIORITY_H_CH1 : R/W; bitpos: [7:5]; default: 0; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_H_CH1 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH1_M (DMA2D_IN_ARB_PRIORITY_H_CH1_V << DMA2D_IN_ARB_PRIORITY_H_CH1_S) -#define DMA2D_IN_ARB_PRIORITY_H_CH1_V 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH1_S 5 - -/** DMA2D_IN_RO_STATUS_CH1_REG register - * Represents the status of the rx reorder module of channel 1 - */ -#define DMA2D_IN_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x644) -/** DMA2D_INFIFO_RO_CNT_CH1 : RO; bitpos: [4:0]; default: 0; - * The register stores the byte number of the data in color convert Rx FIFO for - * channel 0. - */ -#define DMA2D_INFIFO_RO_CNT_CH1 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH1_M (DMA2D_INFIFO_RO_CNT_CH1_V << DMA2D_INFIFO_RO_CNT_CH1_S) -#define DMA2D_INFIFO_RO_CNT_CH1_V 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH1_S 0 -/** DMA2D_IN_RO_WR_STATE_CH1 : RO; bitpos: [6:5]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_IN_RO_WR_STATE_CH1 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH1_M (DMA2D_IN_RO_WR_STATE_CH1_V << DMA2D_IN_RO_WR_STATE_CH1_S) -#define DMA2D_IN_RO_WR_STATE_CH1_V 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH1_S 5 -/** DMA2D_IN_RO_RD_STATE_CH1 : RO; bitpos: [8:7]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_IN_RO_RD_STATE_CH1 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH1_M (DMA2D_IN_RO_RD_STATE_CH1_V << DMA2D_IN_RO_RD_STATE_CH1_S) -#define DMA2D_IN_RO_RD_STATE_CH1_V 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH1_S 7 -/** DMA2D_IN_PIXEL_BYTE_CH1 : RO; bitpos: [12:9]; default: 0; - * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_IN_PIXEL_BYTE_CH1 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH1_M (DMA2D_IN_PIXEL_BYTE_CH1_V << DMA2D_IN_PIXEL_BYTE_CH1_S) -#define DMA2D_IN_PIXEL_BYTE_CH1_V 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH1_S 9 -/** DMA2D_IN_BURST_BLOCK_NUM_CH1 : RO; bitpos: [16:13]; default: 0; - * the number of macro blocks contained in a burst of data at RX channel - */ -#define DMA2D_IN_BURST_BLOCK_NUM_CH1 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH1_M (DMA2D_IN_BURST_BLOCK_NUM_CH1_V << DMA2D_IN_BURST_BLOCK_NUM_CH1_S) -#define DMA2D_IN_BURST_BLOCK_NUM_CH1_V 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH1_S 13 - -/** DMA2D_IN_RO_PD_CONF_CH1_REG register - * Configures the rx reorder memory of channel 1 - */ -#define DMA2D_IN_RO_PD_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x648) -/** DMA2D_IN_RO_RAM_FORCE_PD_CH1 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ -#define DMA2D_IN_RO_RAM_FORCE_PD_CH1 (BIT(4)) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_M (DMA2D_IN_RO_RAM_FORCE_PD_CH1_V << DMA2D_IN_RO_RAM_FORCE_PD_CH1_S) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_S 4 -/** DMA2D_IN_RO_RAM_FORCE_PU_CH1 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ -#define DMA2D_IN_RO_RAM_FORCE_PU_CH1 (BIT(5)) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_M (DMA2D_IN_RO_RAM_FORCE_PU_CH1_V << DMA2D_IN_RO_RAM_FORCE_PU_CH1_S) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_S 5 -/** DMA2D_IN_RO_RAM_CLK_FO_CH1 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ -#define DMA2D_IN_RO_RAM_CLK_FO_CH1 (BIT(6)) -#define DMA2D_IN_RO_RAM_CLK_FO_CH1_M (DMA2D_IN_RO_RAM_CLK_FO_CH1_V << DMA2D_IN_RO_RAM_CLK_FO_CH1_S) -#define DMA2D_IN_RO_RAM_CLK_FO_CH1_V 0x00000001U -#define DMA2D_IN_RO_RAM_CLK_FO_CH1_S 6 - -/** DMA2D_IN_COLOR_CONVERT_CH1_REG register - * Configures the Rx color convert of channel 1 - */ -#define DMA2D_IN_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x64c) -/** DMA2D_IN_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 - */ -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_M (DMA2D_IN_COLOR_OUTPUT_SEL_CH1_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH1_S) -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_V 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_S 0 -/** DMA2D_IN_COLOR_3B_PROC_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_IN_COLOR_3B_PROC_EN_CH1 (BIT(2)) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_M (DMA2D_IN_COLOR_3B_PROC_EN_CH1_V << DMA2D_IN_COLOR_3B_PROC_EN_CH1_S) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_V 0x00000001U -#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_S 2 -/** DMA2D_IN_COLOR_INPUT_SEL_CH1 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: YUV422/420 to YUV444 - * 1: YUV422 2: YUV444/420 7: disable color space convert - */ -#define DMA2D_IN_COLOR_INPUT_SEL_CH1 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH1_M (DMA2D_IN_COLOR_INPUT_SEL_CH1_V << DMA2D_IN_COLOR_INPUT_SEL_CH1_S) -#define DMA2D_IN_COLOR_INPUT_SEL_CH1_V 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH1_S 3 - -/** DMA2D_IN_SCRAMBLE_CH1_REG register - * Configures the rx scramble of channel 1 - */ -#define DMA2D_IN_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x650) -/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_M (DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_S) -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_S 0 -/** DMA2D_IN_SCRAMBLE_SEL_POST_CH1 : R/W; bitpos: [5:3]; default: 0; - * Scramble data after color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : BYTE1-0-2 - * 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_M (DMA2D_IN_SCRAMBLE_SEL_POST_CH1_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH1_S) -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_S 3 - -/** DMA2D_IN_COLOR_PARAM0_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x654) -/** DMA2D_IN_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H0_CH1 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH1_M (DMA2D_IN_COLOR_PARAM_H0_CH1_V << DMA2D_IN_COLOR_PARAM_H0_CH1_S) -#define DMA2D_IN_COLOR_PARAM_H0_CH1_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM1_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x658) -/** DMA2D_IN_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H1_CH1 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH1_M (DMA2D_IN_COLOR_PARAM_H1_CH1_V << DMA2D_IN_COLOR_PARAM_H1_CH1_S) -#define DMA2D_IN_COLOR_PARAM_H1_CH1_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM2_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x65c) -/** DMA2D_IN_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M0_CH1 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH1_M (DMA2D_IN_COLOR_PARAM_M0_CH1_V << DMA2D_IN_COLOR_PARAM_M0_CH1_S) -#define DMA2D_IN_COLOR_PARAM_M0_CH1_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM3_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x660) -/** DMA2D_IN_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M1_CH1 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH1_M (DMA2D_IN_COLOR_PARAM_M1_CH1_V << DMA2D_IN_COLOR_PARAM_M1_CH1_S) -#define DMA2D_IN_COLOR_PARAM_M1_CH1_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM4_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x664) -/** DMA2D_IN_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L0_CH1 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH1_M (DMA2D_IN_COLOR_PARAM_L0_CH1_V << DMA2D_IN_COLOR_PARAM_L0_CH1_S) -#define DMA2D_IN_COLOR_PARAM_L0_CH1_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM5_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x668) -/** DMA2D_IN_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L1_CH1 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH1_M (DMA2D_IN_COLOR_PARAM_L1_CH1_V << DMA2D_IN_COLOR_PARAM_L1_CH1_S) -#define DMA2D_IN_COLOR_PARAM_L1_CH1_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH1_S 0 - -/** DMA2D_IN_ETM_CONF_CH1_REG register - * Configures the rx etm of channel 1 - */ -#define DMA2D_IN_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x66c) -/** DMA2D_IN_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_EN_CH1 (BIT(0)) -#define DMA2D_IN_ETM_EN_CH1_M (DMA2D_IN_ETM_EN_CH1_V << DMA2D_IN_ETM_EN_CH1_S) -#define DMA2D_IN_ETM_EN_CH1_V 0x00000001U -#define DMA2D_IN_ETM_EN_CH1_S 0 -/** DMA2D_IN_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_LOOP_EN_CH1 (BIT(1)) -#define DMA2D_IN_ETM_LOOP_EN_CH1_M (DMA2D_IN_ETM_LOOP_EN_CH1_V << DMA2D_IN_ETM_LOOP_EN_CH1_S) -#define DMA2D_IN_ETM_LOOP_EN_CH1_V 0x00000001U -#define DMA2D_IN_ETM_LOOP_EN_CH1_S 1 -/** DMA2D_IN_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_IN_DSCR_TASK_MAK_CH1 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH1_M (DMA2D_IN_DSCR_TASK_MAK_CH1_V << DMA2D_IN_DSCR_TASK_MAK_CH1_S) -#define DMA2D_IN_DSCR_TASK_MAK_CH1_V 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH1_S 2 - -/** DMA2D_IN_CONF0_CH2_REG register - * Configures the rx direction of channel 2 - */ -#define DMA2D_IN_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x700) -/** DMA2D_IN_MEM_TRANS_EN_CH2 : R/W; bitpos: [0]; default: 0; - * enable memory trans of the same channel - */ -#define DMA2D_IN_MEM_TRANS_EN_CH2 (BIT(0)) -#define DMA2D_IN_MEM_TRANS_EN_CH2_M (DMA2D_IN_MEM_TRANS_EN_CH2_V << DMA2D_IN_MEM_TRANS_EN_CH2_S) -#define DMA2D_IN_MEM_TRANS_EN_CH2_V 0x00000001U -#define DMA2D_IN_MEM_TRANS_EN_CH2_S 0 -/** DMA2D_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ -#define DMA2D_INDSCR_BURST_EN_CH2 (BIT(2)) -#define DMA2D_INDSCR_BURST_EN_CH2_M (DMA2D_INDSCR_BURST_EN_CH2_V << DMA2D_INDSCR_BURST_EN_CH2_S) -#define DMA2D_INDSCR_BURST_EN_CH2_V 0x00000001U -#define DMA2D_INDSCR_BURST_EN_CH2_S 2 -/** DMA2D_IN_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_IN_ECC_AES_EN_CH2 (BIT(3)) -#define DMA2D_IN_ECC_AES_EN_CH2_M (DMA2D_IN_ECC_AES_EN_CH2_V << DMA2D_IN_ECC_AES_EN_CH2_S) -#define DMA2D_IN_ECC_AES_EN_CH2_V 0x00000001U -#define DMA2D_IN_ECC_AES_EN_CH2_S 3 -/** DMA2D_IN_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_IN_CHECK_OWNER_CH2 (BIT(4)) -#define DMA2D_IN_CHECK_OWNER_CH2_M (DMA2D_IN_CHECK_OWNER_CH2_V << DMA2D_IN_CHECK_OWNER_CH2_S) -#define DMA2D_IN_CHECK_OWNER_CH2_V 0x00000001U -#define DMA2D_IN_CHECK_OWNER_CH2_S 4 -/** DMA2D_IN_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_IN_LOOP_TEST_CH2 (BIT(5)) -#define DMA2D_IN_LOOP_TEST_CH2_M (DMA2D_IN_LOOP_TEST_CH2_V << DMA2D_IN_LOOP_TEST_CH2_S) -#define DMA2D_IN_LOOP_TEST_CH2_V 0x00000001U -#define DMA2D_IN_LOOP_TEST_CH2_S 5 -/** DMA2D_IN_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_IN_MEM_BURST_LENGTH_CH2 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH2_M (DMA2D_IN_MEM_BURST_LENGTH_CH2_V << DMA2D_IN_MEM_BURST_LENGTH_CH2_S) -#define DMA2D_IN_MEM_BURST_LENGTH_CH2_V 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH2_S 6 -/** DMA2D_IN_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0; - * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S) -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S 9 -/** DMA2D_IN_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_IN_DSCR_PORT_EN_CH2 (BIT(11)) -#define DMA2D_IN_DSCR_PORT_EN_CH2_M (DMA2D_IN_DSCR_PORT_EN_CH2_V << DMA2D_IN_DSCR_PORT_EN_CH2_S) -#define DMA2D_IN_DSCR_PORT_EN_CH2_V 0x00000001U -#define DMA2D_IN_DSCR_PORT_EN_CH2_S 11 -/** DMA2D_IN_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ -#define DMA2D_IN_PAGE_BOUND_EN_CH2 (BIT(12)) -#define DMA2D_IN_PAGE_BOUND_EN_CH2_M (DMA2D_IN_PAGE_BOUND_EN_CH2_V << DMA2D_IN_PAGE_BOUND_EN_CH2_S) -#define DMA2D_IN_PAGE_BOUND_EN_CH2_V 0x00000001U -#define DMA2D_IN_PAGE_BOUND_EN_CH2_S 12 -/** DMA2D_IN_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0; - * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_IN_REORDER_EN_CH2 (BIT(16)) -#define DMA2D_IN_REORDER_EN_CH2_M (DMA2D_IN_REORDER_EN_CH2_V << DMA2D_IN_REORDER_EN_CH2_S) -#define DMA2D_IN_REORDER_EN_CH2_V 0x00000001U -#define DMA2D_IN_REORDER_EN_CH2_S 16 -/** DMA2D_IN_RST_CH2 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ -#define DMA2D_IN_RST_CH2 (BIT(24)) -#define DMA2D_IN_RST_CH2_M (DMA2D_IN_RST_CH2_V << DMA2D_IN_RST_CH2_S) -#define DMA2D_IN_RST_CH2_V 0x00000001U -#define DMA2D_IN_RST_CH2_S 24 -/** DMA2D_IN_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_IN_CMD_DISABLE_CH2 (BIT(25)) -#define DMA2D_IN_CMD_DISABLE_CH2_M (DMA2D_IN_CMD_DISABLE_CH2_V << DMA2D_IN_CMD_DISABLE_CH2_S) -#define DMA2D_IN_CMD_DISABLE_CH2_V 0x00000001U -#define DMA2D_IN_CMD_DISABLE_CH2_S 25 -/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 (BIT(26)) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V 0x00000001U -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S 26 - -/** DMA2D_IN_INT_RAW_CH2_REG register - * Raw interrupt status of RX channel 2 - */ -#define DMA2D_IN_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x704) -/** DMA2D_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 0. - */ -#define DMA2D_IN_DONE_CH2_INT_RAW (BIT(0)) -#define DMA2D_IN_DONE_CH2_INT_RAW_M (DMA2D_IN_DONE_CH2_INT_RAW_V << DMA2D_IN_DONE_CH2_INT_RAW_S) -#define DMA2D_IN_DONE_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_DONE_CH2_INT_RAW_S 0 -/** DMA2D_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 0. - */ -#define DMA2D_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_M (DMA2D_IN_SUC_EOF_CH2_INT_RAW_V << DMA2D_IN_SUC_EOF_CH2_INT_RAW_S) -#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_S 1 -/** DMA2D_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ -#define DMA2D_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_M (DMA2D_IN_ERR_EOF_CH2_INT_RAW_V << DMA2D_IN_ERR_EOF_CH2_INT_RAW_S) -#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_S 2 -/** DMA2D_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 0. - */ -#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S) -#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S 3 -/** DMA2D_INFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S 4 -/** DMA2D_INFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S 5 -/** DMA2D_INFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S 6 -/** DMA2D_INFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S 7 -/** DMA2D_INFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S 8 -/** DMA2D_INFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S 10 -/** DMA2D_INFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S 11 -/** DMA2D_INFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S 13 - -/** DMA2D_IN_INT_ENA_CH2_REG register - * Interrupt enable bits of RX channel 2 - */ -#define DMA2D_IN_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x708) -/** DMA2D_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH2_INT_ENA (BIT(0)) -#define DMA2D_IN_DONE_CH2_INT_ENA_M (DMA2D_IN_DONE_CH2_INT_ENA_V << DMA2D_IN_DONE_CH2_INT_ENA_S) -#define DMA2D_IN_DONE_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_DONE_CH2_INT_ENA_S 0 -/** DMA2D_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_M (DMA2D_IN_SUC_EOF_CH2_INT_ENA_V << DMA2D_IN_SUC_EOF_CH2_INT_ENA_S) -#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_S 1 -/** DMA2D_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_M (DMA2D_IN_ERR_EOF_CH2_INT_ENA_V << DMA2D_IN_ERR_EOF_CH2_INT_ENA_S) -#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_S 2 -/** DMA2D_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S) -#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S 3 -/** DMA2D_INFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S 4 -/** DMA2D_INFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S 5 -/** DMA2D_INFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S 6 -/** DMA2D_INFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S 7 -/** DMA2D_INFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S 8 -/** DMA2D_INFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S 10 -/** DMA2D_INFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S 11 -/** DMA2D_INFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S 13 - -/** DMA2D_IN_INT_ST_CH2_REG register - * Masked interrupt status of RX channel 2 - */ -#define DMA2D_IN_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x70c) -/** DMA2D_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH2_INT_ST (BIT(0)) -#define DMA2D_IN_DONE_CH2_INT_ST_M (DMA2D_IN_DONE_CH2_INT_ST_V << DMA2D_IN_DONE_CH2_INT_ST_S) -#define DMA2D_IN_DONE_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_DONE_CH2_INT_ST_S 0 -/** DMA2D_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH2_INT_ST (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH2_INT_ST_M (DMA2D_IN_SUC_EOF_CH2_INT_ST_V << DMA2D_IN_SUC_EOF_CH2_INT_ST_S) -#define DMA2D_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH2_INT_ST_S 1 -/** DMA2D_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH2_INT_ST (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH2_INT_ST_M (DMA2D_IN_ERR_EOF_CH2_INT_ST_V << DMA2D_IN_ERR_EOF_CH2_INT_ST_S) -#define DMA2D_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH2_INT_ST_S 2 -/** DMA2D_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_M (DMA2D_IN_DSCR_ERR_CH2_INT_ST_V << DMA2D_IN_DSCR_ERR_CH2_INT_ST_S) -#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_S 3 -/** DMA2D_INFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S 4 -/** DMA2D_INFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S 5 -/** DMA2D_INFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S 6 -/** DMA2D_INFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S 7 -/** DMA2D_INFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S 8 -/** DMA2D_INFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S 10 -/** DMA2D_INFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S 11 -/** DMA2D_INFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S 13 - -/** DMA2D_IN_INT_CLR_CH2_REG register - * Interrupt clear bits of RX channel 2 - */ -#define DMA2D_IN_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x710) -/** DMA2D_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH2_INT_CLR (BIT(0)) -#define DMA2D_IN_DONE_CH2_INT_CLR_M (DMA2D_IN_DONE_CH2_INT_CLR_V << DMA2D_IN_DONE_CH2_INT_CLR_S) -#define DMA2D_IN_DONE_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_DONE_CH2_INT_CLR_S 0 -/** DMA2D_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_M (DMA2D_IN_SUC_EOF_CH2_INT_CLR_V << DMA2D_IN_SUC_EOF_CH2_INT_CLR_S) -#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_S 1 -/** DMA2D_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_M (DMA2D_IN_ERR_EOF_CH2_INT_CLR_V << DMA2D_IN_ERR_EOF_CH2_INT_CLR_S) -#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_S 2 -/** DMA2D_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S) -#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S 3 -/** DMA2D_INFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S 4 -/** DMA2D_INFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S 5 -/** DMA2D_INFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S 6 -/** DMA2D_INFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S 7 -/** DMA2D_INFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S 8 -/** DMA2D_INFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S 10 -/** DMA2D_INFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S 11 -/** DMA2D_INFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S 13 - -/** DMA2D_INFIFO_STATUS_CH2_REG register - * Represents the status of the rx fifo of channel 2 - */ -#define DMA2D_INFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x714) -/** DMA2D_INFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ -#define DMA2D_INFIFO_FULL_L2_CH2 (BIT(0)) -#define DMA2D_INFIFO_FULL_L2_CH2_M (DMA2D_INFIFO_FULL_L2_CH2_V << DMA2D_INFIFO_FULL_L2_CH2_S) -#define DMA2D_INFIFO_FULL_L2_CH2_V 0x00000001U -#define DMA2D_INFIFO_FULL_L2_CH2_S 0 -/** DMA2D_INFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ -#define DMA2D_INFIFO_EMPTY_L2_CH2 (BIT(1)) -#define DMA2D_INFIFO_EMPTY_L2_CH2_M (DMA2D_INFIFO_EMPTY_L2_CH2_V << DMA2D_INFIFO_EMPTY_L2_CH2_S) -#define DMA2D_INFIFO_EMPTY_L2_CH2_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L2_CH2_S 1 -/** DMA2D_INFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ -#define DMA2D_INFIFO_CNT_L2_CH2 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH2_M (DMA2D_INFIFO_CNT_L2_CH2_V << DMA2D_INFIFO_CNT_L2_CH2_S) -#define DMA2D_INFIFO_CNT_L2_CH2_V 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH2_S 2 -/** DMA2D_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_1B_CH2 (BIT(7)) -#define DMA2D_IN_REMAIN_UNDER_1B_CH2_M (DMA2D_IN_REMAIN_UNDER_1B_CH2_V << DMA2D_IN_REMAIN_UNDER_1B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_1B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_1B_CH2_S 7 -/** DMA2D_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_2B_CH2 (BIT(8)) -#define DMA2D_IN_REMAIN_UNDER_2B_CH2_M (DMA2D_IN_REMAIN_UNDER_2B_CH2_V << DMA2D_IN_REMAIN_UNDER_2B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_2B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_2B_CH2_S 8 -/** DMA2D_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_3B_CH2 (BIT(9)) -#define DMA2D_IN_REMAIN_UNDER_3B_CH2_M (DMA2D_IN_REMAIN_UNDER_3B_CH2_V << DMA2D_IN_REMAIN_UNDER_3B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_3B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_3B_CH2_S 9 -/** DMA2D_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_4B_CH2 (BIT(10)) -#define DMA2D_IN_REMAIN_UNDER_4B_CH2_M (DMA2D_IN_REMAIN_UNDER_4B_CH2_V << DMA2D_IN_REMAIN_UNDER_4B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_4B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_4B_CH2_S 10 -/** DMA2D_IN_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_5B_CH2 (BIT(11)) -#define DMA2D_IN_REMAIN_UNDER_5B_CH2_M (DMA2D_IN_REMAIN_UNDER_5B_CH2_V << DMA2D_IN_REMAIN_UNDER_5B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_5B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_5B_CH2_S 11 -/** DMA2D_IN_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_6B_CH2 (BIT(12)) -#define DMA2D_IN_REMAIN_UNDER_6B_CH2_M (DMA2D_IN_REMAIN_UNDER_6B_CH2_V << DMA2D_IN_REMAIN_UNDER_6B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_6B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_6B_CH2_S 12 -/** DMA2D_IN_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_7B_CH2 (BIT(13)) -#define DMA2D_IN_REMAIN_UNDER_7B_CH2_M (DMA2D_IN_REMAIN_UNDER_7B_CH2_V << DMA2D_IN_REMAIN_UNDER_7B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_7B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_7B_CH2_S 13 -/** DMA2D_IN_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_8B_CH2 (BIT(14)) -#define DMA2D_IN_REMAIN_UNDER_8B_CH2_M (DMA2D_IN_REMAIN_UNDER_8B_CH2_V << DMA2D_IN_REMAIN_UNDER_8B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_8B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_8B_CH2_S 14 -/** DMA2D_INFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L1_CH2 (BIT(15)) -#define DMA2D_INFIFO_FULL_L1_CH2_M (DMA2D_INFIFO_FULL_L1_CH2_V << DMA2D_INFIFO_FULL_L1_CH2_S) -#define DMA2D_INFIFO_FULL_L1_CH2_V 0x00000001U -#define DMA2D_INFIFO_FULL_L1_CH2_S 15 -/** DMA2D_INFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L1_CH2 (BIT(16)) -#define DMA2D_INFIFO_EMPTY_L1_CH2_M (DMA2D_INFIFO_EMPTY_L1_CH2_V << DMA2D_INFIFO_EMPTY_L1_CH2_S) -#define DMA2D_INFIFO_EMPTY_L1_CH2_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L1_CH2_S 16 -/** DMA2D_INFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L1_CH2 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH2_M (DMA2D_INFIFO_CNT_L1_CH2_V << DMA2D_INFIFO_CNT_L1_CH2_S) -#define DMA2D_INFIFO_CNT_L1_CH2_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH2_S 17 -/** DMA2D_INFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L3_CH2 (BIT(22)) -#define DMA2D_INFIFO_FULL_L3_CH2_M (DMA2D_INFIFO_FULL_L3_CH2_V << DMA2D_INFIFO_FULL_L3_CH2_S) -#define DMA2D_INFIFO_FULL_L3_CH2_V 0x00000001U -#define DMA2D_INFIFO_FULL_L3_CH2_S 22 -/** DMA2D_INFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L3_CH2 (BIT(23)) -#define DMA2D_INFIFO_EMPTY_L3_CH2_M (DMA2D_INFIFO_EMPTY_L3_CH2_V << DMA2D_INFIFO_EMPTY_L3_CH2_S) -#define DMA2D_INFIFO_EMPTY_L3_CH2_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L3_CH2_S 23 -/** DMA2D_INFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L3_CH2 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH2_M (DMA2D_INFIFO_CNT_L3_CH2_V << DMA2D_INFIFO_CNT_L3_CH2_S) -#define DMA2D_INFIFO_CNT_L3_CH2_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH2_S 24 - -/** DMA2D_IN_POP_CH2_REG register - * Configures the rx fifo of channel 2 - */ -#define DMA2D_IN_POP_CH2_REG (DR_REG_DMA2D_BASE + 0x718) -/** DMA2D_INFIFO_RDATA_CH2 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_RDATA_CH2 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH2_M (DMA2D_INFIFO_RDATA_CH2_V << DMA2D_INFIFO_RDATA_CH2_S) -#define DMA2D_INFIFO_RDATA_CH2_V 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH2_S 0 -/** DMA2D_INFIFO_POP_CH2 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_POP_CH2 (BIT(11)) -#define DMA2D_INFIFO_POP_CH2_M (DMA2D_INFIFO_POP_CH2_V << DMA2D_INFIFO_POP_CH2_S) -#define DMA2D_INFIFO_POP_CH2_V 0x00000001U -#define DMA2D_INFIFO_POP_CH2_S 11 - -/** DMA2D_IN_LINK_CONF_CH2_REG register - * Configures the rx descriptor operations of channel 2 - */ -#define DMA2D_IN_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x71c) -/** DMA2D_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ -#define DMA2D_INLINK_AUTO_RET_CH2 (BIT(20)) -#define DMA2D_INLINK_AUTO_RET_CH2_M (DMA2D_INLINK_AUTO_RET_CH2_V << DMA2D_INLINK_AUTO_RET_CH2_S) -#define DMA2D_INLINK_AUTO_RET_CH2_V 0x00000001U -#define DMA2D_INLINK_AUTO_RET_CH2_S 20 -/** DMA2D_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_STOP_CH2 (BIT(21)) -#define DMA2D_INLINK_STOP_CH2_M (DMA2D_INLINK_STOP_CH2_V << DMA2D_INLINK_STOP_CH2_S) -#define DMA2D_INLINK_STOP_CH2_V 0x00000001U -#define DMA2D_INLINK_STOP_CH2_S 21 -/** DMA2D_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_START_CH2 (BIT(22)) -#define DMA2D_INLINK_START_CH2_M (DMA2D_INLINK_START_CH2_V << DMA2D_INLINK_START_CH2_S) -#define DMA2D_INLINK_START_CH2_V 0x00000001U -#define DMA2D_INLINK_START_CH2_S 22 -/** DMA2D_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ -#define DMA2D_INLINK_RESTART_CH2 (BIT(23)) -#define DMA2D_INLINK_RESTART_CH2_M (DMA2D_INLINK_RESTART_CH2_V << DMA2D_INLINK_RESTART_CH2_S) -#define DMA2D_INLINK_RESTART_CH2_V 0x00000001U -#define DMA2D_INLINK_RESTART_CH2_S 23 -/** DMA2D_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ -#define DMA2D_INLINK_PARK_CH2 (BIT(24)) -#define DMA2D_INLINK_PARK_CH2_M (DMA2D_INLINK_PARK_CH2_V << DMA2D_INLINK_PARK_CH2_S) -#define DMA2D_INLINK_PARK_CH2_V 0x00000001U -#define DMA2D_INLINK_PARK_CH2_S 24 - -/** DMA2D_IN_LINK_ADDR_CH2_REG register - * Configures the rx descriptor address of channel 2 - */ -#define DMA2D_IN_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x720) -/** DMA2D_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ -#define DMA2D_INLINK_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH2_M (DMA2D_INLINK_ADDR_CH2_V << DMA2D_INLINK_ADDR_CH2_S) -#define DMA2D_INLINK_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH2_S 0 - -/** DMA2D_IN_STATE_CH2_REG register - * Represents the working status of the rx descriptor of channel 2 - */ -#define DMA2D_IN_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x724) -/** DMA2D_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ -#define DMA2D_INLINK_DSCR_ADDR_CH2 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH2_M (DMA2D_INLINK_DSCR_ADDR_CH2_V << DMA2D_INLINK_DSCR_ADDR_CH2_S) -#define DMA2D_INLINK_DSCR_ADDR_CH2_V 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH2_S 0 -/** DMA2D_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define DMA2D_IN_DSCR_STATE_CH2 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH2_M (DMA2D_IN_DSCR_STATE_CH2_V << DMA2D_IN_DSCR_STATE_CH2_S) -#define DMA2D_IN_DSCR_STATE_CH2_V 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH2_S 18 -/** DMA2D_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; - * reserved - */ -#define DMA2D_IN_STATE_CH2 0x00000007U -#define DMA2D_IN_STATE_CH2_M (DMA2D_IN_STATE_CH2_V << DMA2D_IN_STATE_CH2_S) -#define DMA2D_IN_STATE_CH2_V 0x00000007U -#define DMA2D_IN_STATE_CH2_S 20 -/** DMA2D_IN_RESET_AVAIL_CH2 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_IN_RESET_AVAIL_CH2 (BIT(23)) -#define DMA2D_IN_RESET_AVAIL_CH2_M (DMA2D_IN_RESET_AVAIL_CH2_V << DMA2D_IN_RESET_AVAIL_CH2_S) -#define DMA2D_IN_RESET_AVAIL_CH2_V 0x00000001U -#define DMA2D_IN_RESET_AVAIL_CH2_S 23 - -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x728) -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S) -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S 0 - -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x72c) -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S) -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S 0 - -/** DMA2D_IN_DSCR_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x730) -/** DMA2D_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ -#define DMA2D_INLINK_DSCR_CH2 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH2_M (DMA2D_INLINK_DSCR_CH2_V << DMA2D_INLINK_DSCR_CH2_S) -#define DMA2D_INLINK_DSCR_CH2_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH2_S 0 - -/** DMA2D_IN_DSCR_BF0_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x734) -/** DMA2D_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ -#define DMA2D_INLINK_DSCR_BF0_CH2 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH2_M (DMA2D_INLINK_DSCR_BF0_CH2_V << DMA2D_INLINK_DSCR_BF0_CH2_S) -#define DMA2D_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH2_S 0 - -/** DMA2D_IN_DSCR_BF1_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x738) -/** DMA2D_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ -#define DMA2D_INLINK_DSCR_BF1_CH2 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH2_M (DMA2D_INLINK_DSCR_BF1_CH2_V << DMA2D_INLINK_DSCR_BF1_CH2_S) -#define DMA2D_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH2_S 0 - -/** DMA2D_IN_PERI_SEL_CH2_REG register - * Configures the rx peripheral of channel 2 - */ -#define DMA2D_IN_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x73c) -/** DMA2D_IN_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Rx channel 0: jpeg 1: - * display-1 2: display-2 7: no choose - */ -#define DMA2D_IN_PERI_SEL_CH2 0x00000007U -#define DMA2D_IN_PERI_SEL_CH2_M (DMA2D_IN_PERI_SEL_CH2_V << DMA2D_IN_PERI_SEL_CH2_S) -#define DMA2D_IN_PERI_SEL_CH2_V 0x00000007U -#define DMA2D_IN_PERI_SEL_CH2_S 0 - -/** DMA2D_IN_ARB_CH2_REG register - * Configures the rx arbiter of channel 2 - */ -#define DMA2D_IN_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x740) -/** DMA2D_IN_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_IN_ARB_TOKEN_NUM_CH2 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH2_M (DMA2D_IN_ARB_TOKEN_NUM_CH2_V << DMA2D_IN_ARB_TOKEN_NUM_CH2_S) -#define DMA2D_IN_ARB_TOKEN_NUM_CH2_V 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH2_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH2 : R/W; bitpos: [4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_CH2 (BIT(4)) -#define DMA2D_IN_ARB_PRIORITY_CH2_M (DMA2D_IN_ARB_PRIORITY_CH2_V << DMA2D_IN_ARB_PRIORITY_CH2_S) -#define DMA2D_IN_ARB_PRIORITY_CH2_V 0x00000001U -#define DMA2D_IN_ARB_PRIORITY_CH2_S 4 -/** DMA2D_IN_ARB_PRIORITY_H_CH2 : R/W; bitpos: [7:5]; default: 0; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_H_CH2 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH2_M (DMA2D_IN_ARB_PRIORITY_H_CH2_V << DMA2D_IN_ARB_PRIORITY_H_CH2_S) -#define DMA2D_IN_ARB_PRIORITY_H_CH2_V 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH2_S 5 - -/** DMA2D_IN_RO_STATUS_CH2_REG register - * Represents the status of the rx reorder module of channel 2 - */ -#define DMA2D_IN_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x744) -/** DMA2D_INFIFO_RO_CNT_CH2 : RO; bitpos: [4:0]; default: 0; - * The register stores the byte number of the data in color convert Rx FIFO for - * channel 0. - */ -#define DMA2D_INFIFO_RO_CNT_CH2 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH2_M (DMA2D_INFIFO_RO_CNT_CH2_V << DMA2D_INFIFO_RO_CNT_CH2_S) -#define DMA2D_INFIFO_RO_CNT_CH2_V 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH2_S 0 -/** DMA2D_IN_RO_WR_STATE_CH2 : RO; bitpos: [6:5]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_IN_RO_WR_STATE_CH2 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH2_M (DMA2D_IN_RO_WR_STATE_CH2_V << DMA2D_IN_RO_WR_STATE_CH2_S) -#define DMA2D_IN_RO_WR_STATE_CH2_V 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH2_S 5 -/** DMA2D_IN_RO_RD_STATE_CH2 : RO; bitpos: [8:7]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_IN_RO_RD_STATE_CH2 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH2_M (DMA2D_IN_RO_RD_STATE_CH2_V << DMA2D_IN_RO_RD_STATE_CH2_S) -#define DMA2D_IN_RO_RD_STATE_CH2_V 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH2_S 7 -/** DMA2D_IN_PIXEL_BYTE_CH2 : RO; bitpos: [12:9]; default: 0; - * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_IN_PIXEL_BYTE_CH2 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH2_M (DMA2D_IN_PIXEL_BYTE_CH2_V << DMA2D_IN_PIXEL_BYTE_CH2_S) -#define DMA2D_IN_PIXEL_BYTE_CH2_V 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH2_S 9 -/** DMA2D_IN_BURST_BLOCK_NUM_CH2 : RO; bitpos: [16:13]; default: 0; - * the number of macro blocks contained in a burst of data at RX channel - */ -#define DMA2D_IN_BURST_BLOCK_NUM_CH2 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH2_M (DMA2D_IN_BURST_BLOCK_NUM_CH2_V << DMA2D_IN_BURST_BLOCK_NUM_CH2_S) -#define DMA2D_IN_BURST_BLOCK_NUM_CH2_V 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH2_S 13 - -/** DMA2D_IN_RO_PD_CONF_CH2_REG register - * Configures the rx reorder memory of channel 2 - */ -#define DMA2D_IN_RO_PD_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x748) -/** DMA2D_IN_RO_RAM_FORCE_PD_CH2 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ -#define DMA2D_IN_RO_RAM_FORCE_PD_CH2 (BIT(4)) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_M (DMA2D_IN_RO_RAM_FORCE_PD_CH2_V << DMA2D_IN_RO_RAM_FORCE_PD_CH2_S) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_S 4 -/** DMA2D_IN_RO_RAM_FORCE_PU_CH2 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ -#define DMA2D_IN_RO_RAM_FORCE_PU_CH2 (BIT(5)) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_M (DMA2D_IN_RO_RAM_FORCE_PU_CH2_V << DMA2D_IN_RO_RAM_FORCE_PU_CH2_S) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_S 5 -/** DMA2D_IN_RO_RAM_CLK_FO_CH2 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ -#define DMA2D_IN_RO_RAM_CLK_FO_CH2 (BIT(6)) -#define DMA2D_IN_RO_RAM_CLK_FO_CH2_M (DMA2D_IN_RO_RAM_CLK_FO_CH2_V << DMA2D_IN_RO_RAM_CLK_FO_CH2_S) -#define DMA2D_IN_RO_RAM_CLK_FO_CH2_V 0x00000001U -#define DMA2D_IN_RO_RAM_CLK_FO_CH2_S 6 - -/** DMA2D_IN_COLOR_CONVERT_CH2_REG register - * Configures the Rx color convert of channel 2 - */ -#define DMA2D_IN_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x74c) -/** DMA2D_IN_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 - */ -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_M (DMA2D_IN_COLOR_OUTPUT_SEL_CH2_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH2_S) -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_V 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_S 0 -/** DMA2D_IN_COLOR_3B_PROC_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_IN_COLOR_3B_PROC_EN_CH2 (BIT(2)) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_M (DMA2D_IN_COLOR_3B_PROC_EN_CH2_V << DMA2D_IN_COLOR_3B_PROC_EN_CH2_S) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_V 0x00000001U -#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_S 2 -/** DMA2D_IN_COLOR_INPUT_SEL_CH2 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: YUV422/420 to YUV444 - * 1: YUV422 2: YUV444/420 7: disable color space convert - */ -#define DMA2D_IN_COLOR_INPUT_SEL_CH2 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH2_M (DMA2D_IN_COLOR_INPUT_SEL_CH2_V << DMA2D_IN_COLOR_INPUT_SEL_CH2_S) -#define DMA2D_IN_COLOR_INPUT_SEL_CH2_V 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH2_S 3 - -/** DMA2D_IN_SCRAMBLE_CH2_REG register - * Configures the rx scramble of channel 2 - */ -#define DMA2D_IN_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x750) -/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_M (DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_S) -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_S 0 -/** DMA2D_IN_SCRAMBLE_SEL_POST_CH2 : R/W; bitpos: [5:3]; default: 0; - * Scramble data after color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : BYTE1-0-2 - * 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_M (DMA2D_IN_SCRAMBLE_SEL_POST_CH2_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH2_S) -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_S 3 - -/** DMA2D_IN_COLOR_PARAM0_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x754) -/** DMA2D_IN_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H0_CH2 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH2_M (DMA2D_IN_COLOR_PARAM_H0_CH2_V << DMA2D_IN_COLOR_PARAM_H0_CH2_S) -#define DMA2D_IN_COLOR_PARAM_H0_CH2_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM1_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x758) -/** DMA2D_IN_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H1_CH2 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH2_M (DMA2D_IN_COLOR_PARAM_H1_CH2_V << DMA2D_IN_COLOR_PARAM_H1_CH2_S) -#define DMA2D_IN_COLOR_PARAM_H1_CH2_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM2_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x75c) -/** DMA2D_IN_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M0_CH2 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH2_M (DMA2D_IN_COLOR_PARAM_M0_CH2_V << DMA2D_IN_COLOR_PARAM_M0_CH2_S) -#define DMA2D_IN_COLOR_PARAM_M0_CH2_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM3_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x760) -/** DMA2D_IN_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M1_CH2 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH2_M (DMA2D_IN_COLOR_PARAM_M1_CH2_V << DMA2D_IN_COLOR_PARAM_M1_CH2_S) -#define DMA2D_IN_COLOR_PARAM_M1_CH2_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM4_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x764) -/** DMA2D_IN_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L0_CH2 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH2_M (DMA2D_IN_COLOR_PARAM_L0_CH2_V << DMA2D_IN_COLOR_PARAM_L0_CH2_S) -#define DMA2D_IN_COLOR_PARAM_L0_CH2_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM5_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x768) -/** DMA2D_IN_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L1_CH2 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH2_M (DMA2D_IN_COLOR_PARAM_L1_CH2_V << DMA2D_IN_COLOR_PARAM_L1_CH2_S) -#define DMA2D_IN_COLOR_PARAM_L1_CH2_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH2_S 0 - -/** DMA2D_IN_ETM_CONF_CH2_REG register - * Configures the rx etm of channel 2 - */ -#define DMA2D_IN_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x76c) -/** DMA2D_IN_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_EN_CH2 (BIT(0)) -#define DMA2D_IN_ETM_EN_CH2_M (DMA2D_IN_ETM_EN_CH2_V << DMA2D_IN_ETM_EN_CH2_S) -#define DMA2D_IN_ETM_EN_CH2_V 0x00000001U -#define DMA2D_IN_ETM_EN_CH2_S 0 -/** DMA2D_IN_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_LOOP_EN_CH2 (BIT(1)) -#define DMA2D_IN_ETM_LOOP_EN_CH2_M (DMA2D_IN_ETM_LOOP_EN_CH2_V << DMA2D_IN_ETM_LOOP_EN_CH2_S) -#define DMA2D_IN_ETM_LOOP_EN_CH2_V 0x00000001U -#define DMA2D_IN_ETM_LOOP_EN_CH2_S 1 -/** DMA2D_IN_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_IN_DSCR_TASK_MAK_CH2 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH2_M (DMA2D_IN_DSCR_TASK_MAK_CH2_V << DMA2D_IN_DSCR_TASK_MAK_CH2_S) -#define DMA2D_IN_DSCR_TASK_MAK_CH2_V 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH2_S 2 - -/** DMA2D_AXI_ERR_REG register - * Represents the status of th axi bus - */ -#define DMA2D_AXI_ERR_REG (DR_REG_DMA2D_BASE + 0xa00) -/** DMA2D_RID_ERR_CNT : RO; bitpos: [3:0]; default: 0; - * AXI read id err cnt - */ -#define DMA2D_RID_ERR_CNT 0x0000000FU -#define DMA2D_RID_ERR_CNT_M (DMA2D_RID_ERR_CNT_V << DMA2D_RID_ERR_CNT_S) -#define DMA2D_RID_ERR_CNT_V 0x0000000FU -#define DMA2D_RID_ERR_CNT_S 0 -/** DMA2D_RRESP_ERR_CNT : RO; bitpos: [7:4]; default: 0; - * AXI read resp err cnt - */ -#define DMA2D_RRESP_ERR_CNT 0x0000000FU -#define DMA2D_RRESP_ERR_CNT_M (DMA2D_RRESP_ERR_CNT_V << DMA2D_RRESP_ERR_CNT_S) -#define DMA2D_RRESP_ERR_CNT_V 0x0000000FU -#define DMA2D_RRESP_ERR_CNT_S 4 -/** DMA2D_WRESP_ERR_CNT : RO; bitpos: [11:8]; default: 0; - * AXI write resp err cnt - */ -#define DMA2D_WRESP_ERR_CNT 0x0000000FU -#define DMA2D_WRESP_ERR_CNT_M (DMA2D_WRESP_ERR_CNT_V << DMA2D_WRESP_ERR_CNT_S) -#define DMA2D_WRESP_ERR_CNT_V 0x0000000FU -#define DMA2D_WRESP_ERR_CNT_S 8 -/** DMA2D_RD_FIFO_CNT : RO; bitpos: [14:12]; default: 0; - * AXI read cmd fifo remain cmd count - */ -#define DMA2D_RD_FIFO_CNT 0x00000007U -#define DMA2D_RD_FIFO_CNT_M (DMA2D_RD_FIFO_CNT_V << DMA2D_RD_FIFO_CNT_S) -#define DMA2D_RD_FIFO_CNT_V 0x00000007U -#define DMA2D_RD_FIFO_CNT_S 12 -/** DMA2D_RD_BAK_FIFO_CNT : RO; bitpos: [18:15]; default: 0; - * AXI read backup cmd fifo remain cmd count - */ -#define DMA2D_RD_BAK_FIFO_CNT 0x0000000FU -#define DMA2D_RD_BAK_FIFO_CNT_M (DMA2D_RD_BAK_FIFO_CNT_V << DMA2D_RD_BAK_FIFO_CNT_S) -#define DMA2D_RD_BAK_FIFO_CNT_V 0x0000000FU -#define DMA2D_RD_BAK_FIFO_CNT_S 15 -/** DMA2D_WR_FIFO_CNT : RO; bitpos: [21:19]; default: 0; - * AXI write cmd fifo remain cmd count - */ -#define DMA2D_WR_FIFO_CNT 0x00000007U -#define DMA2D_WR_FIFO_CNT_M (DMA2D_WR_FIFO_CNT_V << DMA2D_WR_FIFO_CNT_S) -#define DMA2D_WR_FIFO_CNT_V 0x00000007U -#define DMA2D_WR_FIFO_CNT_S 19 -/** DMA2D_WR_BAK_FIFO_CNT : RO; bitpos: [25:22]; default: 0; - * AXI write backup cmd fifo remain cmd count - */ -#define DMA2D_WR_BAK_FIFO_CNT 0x0000000FU -#define DMA2D_WR_BAK_FIFO_CNT_M (DMA2D_WR_BAK_FIFO_CNT_V << DMA2D_WR_BAK_FIFO_CNT_S) -#define DMA2D_WR_BAK_FIFO_CNT_V 0x0000000FU -#define DMA2D_WR_BAK_FIFO_CNT_S 22 - -/** DMA2D_RST_CONF_REG register - * Configures the reset of axi - */ -#define DMA2D_RST_CONF_REG (DR_REG_DMA2D_BASE + 0xa04) -/** DMA2D_AXIM_RD_RST : R/W; bitpos: [0]; default: 0; - * Write 1 then write 0 to this bit to reset axi master read data FIFO. - */ -#define DMA2D_AXIM_RD_RST (BIT(0)) -#define DMA2D_AXIM_RD_RST_M (DMA2D_AXIM_RD_RST_V << DMA2D_AXIM_RD_RST_S) -#define DMA2D_AXIM_RD_RST_V 0x00000001U -#define DMA2D_AXIM_RD_RST_S 0 -/** DMA2D_AXIM_WR_RST : R/W; bitpos: [1]; default: 0; - * Write 1 then write 0 to this bit to reset axi master write data FIFO. - */ -#define DMA2D_AXIM_WR_RST (BIT(1)) -#define DMA2D_AXIM_WR_RST_M (DMA2D_AXIM_WR_RST_V << DMA2D_AXIM_WR_RST_S) -#define DMA2D_AXIM_WR_RST_V 0x00000001U -#define DMA2D_AXIM_WR_RST_S 1 -/** DMA2D_CLK_EN : R/W; bitpos: [2]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. - */ -#define DMA2D_CLK_EN (BIT(2)) -#define DMA2D_CLK_EN_M (DMA2D_CLK_EN_V << DMA2D_CLK_EN_S) -#define DMA2D_CLK_EN_V 0x00000001U -#define DMA2D_CLK_EN_S 2 - -/** DMA2D_INTR_MEM_START_ADDR_REG register - * The start address of accessible address space. - */ -#define DMA2D_INTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa08) -/** DMA2D_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ -#define DMA2D_ACCESS_INTR_MEM_START_ADDR 0xFFFFFFFFU -#define DMA2D_ACCESS_INTR_MEM_START_ADDR_M (DMA2D_ACCESS_INTR_MEM_START_ADDR_V << DMA2D_ACCESS_INTR_MEM_START_ADDR_S) -#define DMA2D_ACCESS_INTR_MEM_START_ADDR_V 0xFFFFFFFFU -#define DMA2D_ACCESS_INTR_MEM_START_ADDR_S 0 - -/** DMA2D_INTR_MEM_END_ADDR_REG register - * The end address of accessible address space. - */ -#define DMA2D_INTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa0c) -/** DMA2D_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ -#define DMA2D_ACCESS_INTR_MEM_END_ADDR 0xFFFFFFFFU -#define DMA2D_ACCESS_INTR_MEM_END_ADDR_M (DMA2D_ACCESS_INTR_MEM_END_ADDR_V << DMA2D_ACCESS_INTR_MEM_END_ADDR_S) -#define DMA2D_ACCESS_INTR_MEM_END_ADDR_V 0xFFFFFFFFU -#define DMA2D_ACCESS_INTR_MEM_END_ADDR_S 0 - -/** DMA2D_EXTR_MEM_START_ADDR_REG register - * The start address of accessible address space. - */ -#define DMA2D_EXTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa10) -/** DMA2D_ACCESS_EXTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ -#define DMA2D_ACCESS_EXTR_MEM_START_ADDR 0xFFFFFFFFU -#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_M (DMA2D_ACCESS_EXTR_MEM_START_ADDR_V << DMA2D_ACCESS_EXTR_MEM_START_ADDR_S) -#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_V 0xFFFFFFFFU -#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_S 0 - -/** DMA2D_EXTR_MEM_END_ADDR_REG register - * The end address of accessible address space. - */ -#define DMA2D_EXTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa14) -/** DMA2D_ACCESS_EXTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ -#define DMA2D_ACCESS_EXTR_MEM_END_ADDR 0xFFFFFFFFU -#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_M (DMA2D_ACCESS_EXTR_MEM_END_ADDR_V << DMA2D_ACCESS_EXTR_MEM_END_ADDR_S) -#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_V 0xFFFFFFFFU -#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_S 0 - -/** DMA2D_OUT_ARB_CONFIG_REG register - * Configures the tx arbiter - */ -#define DMA2D_OUT_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa18) -/** DMA2D_OUT_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0; - * Set the max number of timeout count of arbiter - */ -#define DMA2D_OUT_ARB_TIMEOUT_NUM 0x0000FFFFU -#define DMA2D_OUT_ARB_TIMEOUT_NUM_M (DMA2D_OUT_ARB_TIMEOUT_NUM_V << DMA2D_OUT_ARB_TIMEOUT_NUM_S) -#define DMA2D_OUT_ARB_TIMEOUT_NUM_V 0x0000FFFFU -#define DMA2D_OUT_ARB_TIMEOUT_NUM_S 0 -/** DMA2D_OUT_WEIGHT_EN : R/W; bitpos: [16]; default: 0; - * reserved - */ -#define DMA2D_OUT_WEIGHT_EN (BIT(16)) -#define DMA2D_OUT_WEIGHT_EN_M (DMA2D_OUT_WEIGHT_EN_V << DMA2D_OUT_WEIGHT_EN_S) -#define DMA2D_OUT_WEIGHT_EN_V 0x00000001U -#define DMA2D_OUT_WEIGHT_EN_S 16 - -/** DMA2D_IN_ARB_CONFIG_REG register - * Configures the rx arbiter - */ -#define DMA2D_IN_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa1c) -/** DMA2D_IN_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0; - * Set the max number of timeout count of arbiter - */ -#define DMA2D_IN_ARB_TIMEOUT_NUM 0x0000FFFFU -#define DMA2D_IN_ARB_TIMEOUT_NUM_M (DMA2D_IN_ARB_TIMEOUT_NUM_V << DMA2D_IN_ARB_TIMEOUT_NUM_S) -#define DMA2D_IN_ARB_TIMEOUT_NUM_V 0x0000FFFFU -#define DMA2D_IN_ARB_TIMEOUT_NUM_S 0 -/** DMA2D_IN_WEIGHT_EN : R/W; bitpos: [16]; default: 0; - * reserved - */ -#define DMA2D_IN_WEIGHT_EN (BIT(16)) -#define DMA2D_IN_WEIGHT_EN_M (DMA2D_IN_WEIGHT_EN_V << DMA2D_IN_WEIGHT_EN_S) -#define DMA2D_IN_WEIGHT_EN_V 0x00000001U -#define DMA2D_IN_WEIGHT_EN_S 16 - -/** DMA2D_RDN_RESULT_REG register - * reserved - */ -#define DMA2D_RDN_RESULT_REG (DR_REG_DMA2D_BASE + 0xa20) -/** DMA2D_RDN_ENA : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define DMA2D_RDN_ENA (BIT(0)) -#define DMA2D_RDN_ENA_M (DMA2D_RDN_ENA_V << DMA2D_RDN_ENA_S) -#define DMA2D_RDN_ENA_V 0x00000001U -#define DMA2D_RDN_ENA_S 0 -/** DMA2D_RDN_RESULT : RO; bitpos: [1]; default: 0; - * reserved - */ -#define DMA2D_RDN_RESULT (BIT(1)) -#define DMA2D_RDN_RESULT_M (DMA2D_RDN_RESULT_V << DMA2D_RDN_RESULT_S) -#define DMA2D_RDN_RESULT_V 0x00000001U -#define DMA2D_RDN_RESULT_S 1 - -/** DMA2D_RDN_ECO_HIGH_REG register - * reserved - */ -#define DMA2D_RDN_ECO_HIGH_REG (DR_REG_DMA2D_BASE + 0xa24) -/** DMA2D_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; - * The start address of accessible address space. - */ -#define DMA2D_RDN_ECO_HIGH 0xFFFFFFFFU -#define DMA2D_RDN_ECO_HIGH_M (DMA2D_RDN_ECO_HIGH_V << DMA2D_RDN_ECO_HIGH_S) -#define DMA2D_RDN_ECO_HIGH_V 0xFFFFFFFFU -#define DMA2D_RDN_ECO_HIGH_S 0 - -/** DMA2D_RDN_ECO_LOW_REG register - * reserved - */ -#define DMA2D_RDN_ECO_LOW_REG (DR_REG_DMA2D_BASE + 0xa28) -/** DMA2D_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; - * The start address of accessible address space. - */ -#define DMA2D_RDN_ECO_LOW 0xFFFFFFFFU -#define DMA2D_RDN_ECO_LOW_M (DMA2D_RDN_ECO_LOW_V << DMA2D_RDN_ECO_LOW_S) -#define DMA2D_RDN_ECO_LOW_V 0xFFFFFFFFU -#define DMA2D_RDN_ECO_LOW_S 0 - -/** DMA2D_DATE_REG register - * register version. - */ -#define DMA2D_DATE_REG (DR_REG_DMA2D_BASE + 0xa2c) -/** DMA2D_DATE : R/W; bitpos: [31:0]; default: 37822864; - * register version. - */ -#define DMA2D_DATE 0xFFFFFFFFU -#define DMA2D_DATE_M (DMA2D_DATE_V << DMA2D_DATE_S) -#define DMA2D_DATE_V 0xFFFFFFFFU -#define DMA2D_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h deleted file mode 100644 index d637f6ecab..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h +++ /dev/null @@ -1,2085 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of out_conf0_chn register - * Configures the tx direction of channel n - */ -typedef union { - struct { - /** out_auto_wrback_chn : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ - uint32_t out_auto_wrback_chn:1; - /** out_eof_mode_chn : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_chn:1; - /** outdscr_burst_en_chn : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_chn:1; - /** out_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t out_ecc_aes_en_chn:1; - /** out_check_owner_chn : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t out_check_owner_chn:1; - /** out_loop_test_chn : R/W; bitpos: [5]; default: 0; - * reserved - */ - uint32_t out_loop_test_chn:1; - /** out_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t out_mem_burst_length_chn:3; - /** out_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ - uint32_t out_macro_block_size_chn:2; - /** out_dscr_port_en_chn : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ - uint32_t out_dscr_port_en_chn:1; - /** out_page_bound_en_chn : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ - uint32_t out_page_bound_en_chn:1; - uint32_t reserved_13:3; - /** out_reorder_en_chn : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ - uint32_t out_reorder_en_chn:1; - uint32_t reserved_17:7; - /** out_rst_chn : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ - uint32_t out_rst_chn:1; - /** out_cmd_disable_chn : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t out_cmd_disable_chn:1; - /** out_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t out_arb_weight_opt_dis_chn:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} dma2d_out_conf0_chn_reg_t; - -/** Type of out_push_chn register - * Configures the tx fifo of channel n - */ -typedef union { - struct { - /** outfifo_wdata_chn : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ - uint32_t outfifo_wdata_chn:10; - /** outfifo_push_chn : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ - uint32_t outfifo_push_chn:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} dma2d_out_push_chn_reg_t; - -/** Type of out_link_conf_chn register - * Configures the tx descriptor operations of channel n - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** outlink_stop_chn : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - uint32_t outlink_stop_chn:1; - /** outlink_start_chn : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - uint32_t outlink_start_chn:1; - /** outlink_restart_chn : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - uint32_t outlink_restart_chn:1; - /** outlink_park_chn : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ - uint32_t outlink_park_chn:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} dma2d_out_link_conf_chn_reg_t; - -/** Type of out_link_addr_chn register - * Configures the tx descriptor address of channel n - */ -typedef union { - struct { - /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ - uint32_t outlink_addr_chn:32; - }; - uint32_t val; -} dma2d_out_link_addr_chn_reg_t; - -/** Type of out_arb_chn register - * Configures the tx arbiter of channel n - */ -typedef union { - struct { - /** out_arb_token_num_chn : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t out_arb_token_num_chn:4; - /** out_arb_priority_chn : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ - uint32_t out_arb_priority_chn:2; - /** out_arb_priority_h_chn : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ - uint32_t out_arb_priority_h_chn:2; - uint32_t reserved_8:24; - }; - uint32_t val; -} dma2d_out_arb_chn_reg_t; - -/** Type of out_ro_pd_conf_chn register - * Configures the tx reorder memory of channel 0 - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** out_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ - uint32_t out_ro_ram_force_pd_chn:1; - /** out_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ - uint32_t out_ro_ram_force_pu_chn:1; - /** out_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ - uint32_t out_ro_ram_clk_fo_chn:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} dma2d_out_ro_pd_conf_chn_reg_t; - -/** Type of out_color_convert_chn register - * Configures the tx color convert of channel n - */ -typedef union { - struct { - /** out_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ - uint32_t out_color_output_sel_chn:2; - /** out_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ - uint32_t out_color_3b_proc_en_chn:1; - /** out_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ - uint32_t out_color_input_sel_chn:3; - uint32_t reserved_6:26; - }; - uint32_t val; -} dma2d_out_color_convert_chn_reg_t; - -/** Type of out_scramble_chn register - * Configures the tx scramble of channel n - */ -typedef union { - struct { - /** out_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ - uint32_t out_scramble_sel_pre_chn:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} dma2d_out_scramble_chn_reg_t; - -/** Type of out_color_param0_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_h0_chn : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ - uint32_t out_color_param_h0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_out_color_param0_chn_reg_t; - -/** Type of out_color_param1_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_h1_chn : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ - uint32_t out_color_param_h1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_out_color_param1_chn_reg_t; - -/** Type of out_color_param2_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_m0_chn : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ - uint32_t out_color_param_m0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_out_color_param2_chn_reg_t; - -/** Type of out_color_param3_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_m1_chn : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ - uint32_t out_color_param_m1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_out_color_param3_chn_reg_t; - -/** Type of out_color_param4_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_l0_chn : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ - uint32_t out_color_param_l0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_out_color_param4_chn_reg_t; - -/** Type of out_color_param5_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_l1_chn : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ - uint32_t out_color_param_l1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_out_color_param5_chn_reg_t; - -/** Type of out_etm_conf_chn register - * Configures the tx etm of channel n - */ -typedef union { - struct { - /** out_etm_en_chn : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ - uint32_t out_etm_en_chn:1; - /** out_etm_loop_en_chn : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ - uint32_t out_etm_loop_en_chn:1; - /** out_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ - uint32_t out_dscr_task_mak_chn:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} dma2d_out_etm_conf_chn_reg_t; - -/** Type of out_dscr_port_blk_chn register - * Configures the tx block size in dscr port mode - */ -typedef union { - struct { - /** out_dscr_port_blk_h_chn : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ - uint32_t out_dscr_port_blk_h_chn:14; - /** out_dscr_port_blk_v_chn : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ - uint32_t out_dscr_port_blk_v_chn:14; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_out_dscr_port_blk_chn_reg_t; - -/** Type of in_conf0_chn register - * Configures the rx direction of channel n - */ -typedef union { - struct { - /** in_mem_trans_en_chn : R/W; bitpos: [0]; default: 0; - * enable memory trans of the same channel - */ - uint32_t in_mem_trans_en_chn:1; - uint32_t reserved_1:1; - /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ - uint32_t indscr_burst_en_chn:1; - /** in_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t in_ecc_aes_en_chn:1; - /** in_check_owner_chn : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t in_check_owner_chn:1; - /** in_loop_test_chn : R/W; bitpos: [5]; default: 0; - * reserved - */ - uint32_t in_loop_test_chn:1; - /** in_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t in_mem_burst_length_chn:3; - /** in_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0; - * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ - uint32_t in_macro_block_size_chn:2; - /** in_dscr_port_en_chn : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ - uint32_t in_dscr_port_en_chn:1; - /** in_page_bound_en_chn : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ - uint32_t in_page_bound_en_chn:1; - uint32_t reserved_13:3; - /** in_reorder_en_chn : R/W; bitpos: [16]; default: 0; - * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ - uint32_t in_reorder_en_chn:1; - uint32_t reserved_17:7; - /** in_rst_chn : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ - uint32_t in_rst_chn:1; - /** in_cmd_disable_chn : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t in_cmd_disable_chn:1; - /** in_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t in_arb_weight_opt_dis_chn:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} dma2d_in_conf0_chn_reg_t; - -/** Type of in_pop_chn register - * Configures the rx fifo of channel n - */ -typedef union { - struct { - /** infifo_rdata_chn : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ - uint32_t infifo_rdata_chn:11; - /** infifo_pop_chn : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ - uint32_t infifo_pop_chn:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} dma2d_in_pop_chn_reg_t; - -/** Type of in_link_conf_chn register - * Configures the rx descriptor operations of channel n - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ - uint32_t inlink_auto_ret_chn:1; - /** inlink_stop_chn : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - uint32_t inlink_stop_chn:1; - /** inlink_start_chn : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - uint32_t inlink_start_chn:1; - /** inlink_restart_chn : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - uint32_t inlink_restart_chn:1; - /** inlink_park_chn : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ - uint32_t inlink_park_chn:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} dma2d_in_link_conf_chn_reg_t; - -/** Type of in_link_addr_chn register - * Configures the rx descriptor address of channel n - */ -typedef union { - struct { - /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ - uint32_t inlink_addr_chn:32; - }; - uint32_t val; -} dma2d_in_link_addr_chn_reg_t; - -/** Type of in_arb_chn register - * Configures the rx arbiter of channel n - */ -typedef union { - struct { - /** in_arb_token_num_chn : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t in_arb_token_num_chn:4; - /** in_arb_priority_chn : R/W; bitpos: [4]; default: 1; - * Set the priority of channel - */ - uint32_t in_arb_priority_chn:1; - /** in_arb_priority_h_chn : R/W; bitpos: [7:5]; default: 0; - * Set the priority of channel - */ - uint32_t in_arb_priority_h_chn:3; - uint32_t reserved_8:24; - }; - uint32_t val; -} dma2d_in_arb_chn_reg_t; - -/** Type of in_ro_pd_conf_chn register - * Configures the rx reorder memory of channel n - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** in_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ - uint32_t in_ro_ram_force_pd_chn:1; - /** in_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ - uint32_t in_ro_ram_force_pu_chn:1; - /** in_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ - uint32_t in_ro_ram_clk_fo_chn:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} dma2d_in_ro_pd_conf_chn_reg_t; - -/** Type of in_color_convert_chn register - * Configures the Rx color convert of channel n - */ -typedef union { - struct { - /** in_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 - */ - uint32_t in_color_output_sel_chn:2; - /** in_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ - uint32_t in_color_3b_proc_en_chn:1; - /** in_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: YUV422/420 to YUV444 - * 1: YUV422 2: YUV444/420 7: disable color space convert - */ - uint32_t in_color_input_sel_chn:3; - uint32_t reserved_6:26; - }; - uint32_t val; -} dma2d_in_color_convert_chn_reg_t; - -/** Type of in_scramble_chn register - * Configures the rx scramble of channel n - */ -typedef union { - struct { - /** in_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ - uint32_t in_scramble_sel_pre_chn:3; - /** in_scramble_sel_post_chn : R/W; bitpos: [5:3]; default: 0; - * Scramble data after color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : BYTE1-0-2 - * 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ - uint32_t in_scramble_sel_post_chn:3; - uint32_t reserved_6:26; - }; - uint32_t val; -} dma2d_in_scramble_chn_reg_t; - -/** Type of in_color_param0_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_h0_chn : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ - uint32_t in_color_param_h0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_in_color_param0_chn_reg_t; - -/** Type of in_color_param1_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_h1_chn : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ - uint32_t in_color_param_h1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_in_color_param1_chn_reg_t; - -/** Type of in_color_param2_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_m0_chn : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ - uint32_t in_color_param_m0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_in_color_param2_chn_reg_t; - -/** Type of in_color_param3_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_m1_chn : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ - uint32_t in_color_param_m1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_in_color_param3_chn_reg_t; - -/** Type of in_color_param4_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_l0_chn : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ - uint32_t in_color_param_l0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_in_color_param4_chn_reg_t; - -/** Type of in_color_param5_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_l1_chn : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ - uint32_t in_color_param_l1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_in_color_param5_chn_reg_t; - -/** Type of in_etm_conf_chn register - * Configures the rx etm of channel n - */ -typedef union { - struct { - /** in_etm_en_chn : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ - uint32_t in_etm_en_chn:1; - /** in_etm_loop_en_chn : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ - uint32_t in_etm_loop_en_chn:1; - /** in_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ - uint32_t in_dscr_task_mak_chn:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} dma2d_in_etm_conf_chn_reg_t; - -/** Type of rst_conf register - * Configures the reset of axi - */ -typedef union { - struct { - /** axim_rd_rst : R/W; bitpos: [0]; default: 0; - * Write 1 then write 0 to this bit to reset axi master read data FIFO. - */ - uint32_t axim_rd_rst:1; - /** axim_wr_rst : R/W; bitpos: [1]; default: 0; - * Write 1 then write 0 to this bit to reset axi master write data FIFO. - */ - uint32_t axim_wr_rst:1; - /** clk_en : R/W; bitpos: [2]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. - */ - uint32_t clk_en:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} dma2d_rst_conf_reg_t; - -/** Type of intr_mem_start_addr register - * The start address of accessible address space. - */ -typedef union { - struct { - /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ - uint32_t access_intr_mem_start_addr:32; - }; - uint32_t val; -} dma2d_intr_mem_start_addr_reg_t; - -/** Type of intr_mem_end_addr register - * The end address of accessible address space. - */ -typedef union { - struct { - /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ - uint32_t access_intr_mem_end_addr:32; - }; - uint32_t val; -} dma2d_intr_mem_end_addr_reg_t; - -/** Type of extr_mem_start_addr register - * The start address of accessible address space. - */ -typedef union { - struct { - /** access_extr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ - uint32_t access_extr_mem_start_addr:32; - }; - uint32_t val; -} dma2d_extr_mem_start_addr_reg_t; - -/** Type of extr_mem_end_addr register - * The end address of accessible address space. - */ -typedef union { - struct { - /** access_extr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ - uint32_t access_extr_mem_end_addr:32; - }; - uint32_t val; -} dma2d_extr_mem_end_addr_reg_t; - -/** Type of out_arb_config register - * Configures the tx arbiter - */ -typedef union { - struct { - /** out_arb_timeout_num : R/W; bitpos: [15:0]; default: 0; - * Set the max number of timeout count of arbiter - */ - uint32_t out_arb_timeout_num:16; - /** out_weight_en : R/W; bitpos: [16]; default: 0; - * reserved - */ - uint32_t out_weight_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dma2d_out_arb_config_reg_t; - -/** Type of in_arb_config register - * Configures the rx arbiter - */ -typedef union { - struct { - /** in_arb_timeout_num : R/W; bitpos: [15:0]; default: 0; - * Set the max number of timeout count of arbiter - */ - uint32_t in_arb_timeout_num:16; - /** in_weight_en : R/W; bitpos: [16]; default: 0; - * reserved - */ - uint32_t in_weight_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dma2d_in_arb_config_reg_t; - -/** Type of rdn_result register - * reserved - */ -typedef union { - struct { - /** rdn_ena : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t rdn_ena:1; - /** rdn_result : RO; bitpos: [1]; default: 0; - * reserved - */ - uint32_t rdn_result:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dma2d_rdn_result_reg_t; - -/** Type of rdn_eco_high register - * reserved - */ -typedef union { - struct { - /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; - * The start address of accessible address space. - */ - uint32_t rdn_eco_high:32; - }; - uint32_t val; -} dma2d_rdn_eco_high_reg_t; - -/** Type of rdn_eco_low register - * reserved - */ -typedef union { - struct { - /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; - * The start address of accessible address space. - */ - uint32_t rdn_eco_low:32; - }; - uint32_t val; -} dma2d_rdn_eco_low_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of out_int_raw_chn register - * Raw interrupt status of TX channel n - */ -typedef union { - struct { - /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ - uint32_t out_done_chn_int_raw:1; - /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ - uint32_t out_eof_chn_int_raw:1; - /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ - uint32_t out_dscr_err_chn_int_raw:1; - /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ - uint32_t out_total_eof_chn_int_raw:1; - /** outfifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l1_chn_int_raw:1; - /** outfifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l1_chn_int_raw:1; - /** outfifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l2_chn_int_raw:1; - /** outfifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l2_chn_int_raw:1; - /** outfifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l3_chn_int_raw:1; - /** outfifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l3_chn_int_raw:1; - /** outfifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ - uint32_t outfifo_ro_ovf_chn_int_raw:1; - /** outfifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ - uint32_t outfifo_ro_udf_chn_int_raw:1; - /** out_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t out_dscr_task_ovf_chn_int_raw:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} dma2d_out_int_raw_chn_reg_t; - -/** Type of out_int_ena_chn register - * Interrupt enable bits of TX channel n - */ -typedef union { - struct { - /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_chn_int_ena:1; - /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_chn_int_ena:1; - /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_chn_int_ena:1; - /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_chn_int_ena:1; - /** outfifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_chn_int_ena:1; - /** outfifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_chn_int_ena:1; - /** outfifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_chn_int_ena:1; - /** outfifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_chn_int_ena:1; - /** outfifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l3_chn_int_ena:1; - /** outfifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t outfifo_udf_l3_chn_int_ena:1; - /** outfifo_ro_ovf_chn_int_ena : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t outfifo_ro_ovf_chn_int_ena:1; - /** outfifo_ro_udf_chn_int_ena : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t outfifo_ro_udf_chn_int_ena:1; - /** out_dscr_task_ovf_chn_int_ena : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_chn_int_ena:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} dma2d_out_int_ena_chn_reg_t; - -/** Type of out_int_st_chn register - * Masked interrupt status of TX channel n - */ -typedef union { - struct { - /** out_done_chn_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_chn_int_st:1; - /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_chn_int_st:1; - /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_chn_int_st:1; - /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_chn_int_st:1; - /** outfifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_chn_int_st:1; - /** outfifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_chn_int_st:1; - /** outfifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_chn_int_st:1; - /** outfifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_chn_int_st:1; - /** outfifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l3_chn_int_st:1; - /** outfifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t outfifo_udf_l3_chn_int_st:1; - /** outfifo_ro_ovf_chn_int_st : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t outfifo_ro_ovf_chn_int_st:1; - /** outfifo_ro_udf_chn_int_st : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t outfifo_ro_udf_chn_int_st:1; - /** out_dscr_task_ovf_chn_int_st : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_chn_int_st:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} dma2d_out_int_st_chn_reg_t; - -/** Type of out_int_clr_chn register - * Interrupt clear bits of TX channel n - */ -typedef union { - struct { - /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_chn_int_clr:1; - /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_chn_int_clr:1; - /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_chn_int_clr:1; - /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_chn_int_clr:1; - /** outfifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_chn_int_clr:1; - /** outfifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_chn_int_clr:1; - /** outfifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_chn_int_clr:1; - /** outfifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_chn_int_clr:1; - /** outfifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l3_chn_int_clr:1; - /** outfifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t outfifo_udf_l3_chn_int_clr:1; - /** outfifo_ro_ovf_chn_int_clr : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t outfifo_ro_ovf_chn_int_clr:1; - /** outfifo_ro_udf_chn_int_clr : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t outfifo_ro_udf_chn_int_clr:1; - /** out_dscr_task_ovf_chn_int_clr : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_chn_int_clr:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} dma2d_out_int_clr_chn_reg_t; - -/** Type of in_int_raw_chn register - * Raw interrupt status of RX channel n - */ -typedef union { - struct { - /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 0. - */ - uint32_t in_done_chn_int_raw:1; - /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 0. - */ - uint32_t in_suc_eof_chn_int_raw:1; - /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ - uint32_t in_err_eof_chn_int_raw:1; - /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 0. - */ - uint32_t in_dscr_err_chn_int_raw:1; - /** infifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l1_chn_int_raw:1; - /** infifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l1_chn_int_raw:1; - /** infifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l2_chn_int_raw:1; - /** infifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l2_chn_int_raw:1; - /** infifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l3_chn_int_raw:1; - /** infifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l3_chn_int_raw:1; - /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ - uint32_t in_dscr_empty_chn_int_raw:1; - /** infifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ - uint32_t infifo_ro_ovf_chn_int_raw:1; - /** infifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ - uint32_t infifo_ro_udf_chn_int_raw:1; - /** in_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t in_dscr_task_ovf_chn_int_raw:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} dma2d_in_int_raw_chn_reg_t; - -/** Type of in_int_ena_chn register - * Interrupt enable bits of RX channel n - */ -typedef union { - struct { - /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_chn_int_ena:1; - /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_chn_int_ena:1; - /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_chn_int_ena:1; - /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_chn_int_ena:1; - /** infifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_chn_int_ena:1; - /** infifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_chn_int_ena:1; - /** infifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_chn_int_ena:1; - /** infifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_chn_int_ena:1; - /** infifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t infifo_ovf_l3_chn_int_ena:1; - /** infifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t infifo_udf_l3_chn_int_ena:1; - /** in_dscr_empty_chn_int_ena : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_chn_int_ena:1; - /** infifo_ro_ovf_chn_int_ena : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t infifo_ro_ovf_chn_int_ena:1; - /** infifo_ro_udf_chn_int_ena : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t infifo_ro_udf_chn_int_ena:1; - /** in_dscr_task_ovf_chn_int_ena : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_chn_int_ena:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} dma2d_in_int_ena_chn_reg_t; - -/** Type of in_int_st_chn register - * Masked interrupt status of RX channel n - */ -typedef union { - struct { - /** in_done_chn_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_chn_int_st:1; - /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_chn_int_st:1; - /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_chn_int_st:1; - /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_chn_int_st:1; - /** infifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_chn_int_st:1; - /** infifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_chn_int_st:1; - /** infifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_chn_int_st:1; - /** infifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_chn_int_st:1; - /** infifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t infifo_ovf_l3_chn_int_st:1; - /** infifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t infifo_udf_l3_chn_int_st:1; - /** in_dscr_empty_chn_int_st : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_chn_int_st:1; - /** infifo_ro_ovf_chn_int_st : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t infifo_ro_ovf_chn_int_st:1; - /** infifo_ro_udf_chn_int_st : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t infifo_ro_udf_chn_int_st:1; - /** in_dscr_task_ovf_chn_int_st : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_chn_int_st:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} dma2d_in_int_st_chn_reg_t; - -/** Type of in_int_clr_chn register - * Interrupt clear bits of RX channel n - */ -typedef union { - struct { - /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_chn_int_clr:1; - /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_chn_int_clr:1; - /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_chn_int_clr:1; - /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_chn_int_clr:1; - /** infifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_chn_int_clr:1; - /** infifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_chn_int_clr:1; - /** infifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_chn_int_clr:1; - /** infifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_chn_int_clr:1; - /** infifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t infifo_ovf_l3_chn_int_clr:1; - /** infifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t infifo_udf_l3_chn_int_clr:1; - /** in_dscr_empty_chn_int_clr : WT; bitpos: [10]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_chn_int_clr:1; - /** infifo_ro_ovf_chn_int_clr : WT; bitpos: [11]; default: 0; - * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t infifo_ro_ovf_chn_int_clr:1; - /** infifo_ro_udf_chn_int_clr : WT; bitpos: [12]; default: 0; - * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t infifo_ro_udf_chn_int_clr:1; - /** in_dscr_task_ovf_chn_int_clr : WT; bitpos: [13]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_chn_int_clr:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} dma2d_in_int_clr_chn_reg_t; - - -/** Group: Status Registers */ -/** Type of outfifo_status_chn register - * Represents the status of the tx fifo of channel n - */ -typedef union { - struct { - /** outfifo_full_l2_chn : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ - uint32_t outfifo_full_l2_chn:1; - /** outfifo_empty_l2_chn : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ - uint32_t outfifo_empty_l2_chn:1; - /** outfifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ - uint32_t outfifo_cnt_l2_chn:4; - uint32_t reserved_6:1; - /** out_remain_under_1b_chn : RO; bitpos: [7]; default: 1; - * reserved - */ - uint32_t out_remain_under_1b_chn:1; - /** out_remain_under_2b_chn : RO; bitpos: [8]; default: 1; - * reserved - */ - uint32_t out_remain_under_2b_chn:1; - /** out_remain_under_3b_chn : RO; bitpos: [9]; default: 1; - * reserved - */ - uint32_t out_remain_under_3b_chn:1; - /** out_remain_under_4b_chn : RO; bitpos: [10]; default: 1; - * reserved - */ - uint32_t out_remain_under_4b_chn:1; - /** out_remain_under_5b_chn : RO; bitpos: [11]; default: 1; - * reserved - */ - uint32_t out_remain_under_5b_chn:1; - /** out_remain_under_6b_chn : RO; bitpos: [12]; default: 1; - * reserved - */ - uint32_t out_remain_under_6b_chn:1; - /** out_remain_under_7b_chn : RO; bitpos: [13]; default: 1; - * reserved - */ - uint32_t out_remain_under_7b_chn:1; - /** out_remain_under_8b_chn : RO; bitpos: [14]; default: 1; - * reserved - */ - uint32_t out_remain_under_8b_chn:1; - /** outfifo_full_l1_chn : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ - uint32_t outfifo_full_l1_chn:1; - /** outfifo_empty_l1_chn : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ - uint32_t outfifo_empty_l1_chn:1; - /** outfifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ - uint32_t outfifo_cnt_l1_chn:5; - /** outfifo_full_l3_chn : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ - uint32_t outfifo_full_l3_chn:1; - /** outfifo_empty_l3_chn : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ - uint32_t outfifo_empty_l3_chn:1; - /** outfifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ - uint32_t outfifo_cnt_l3_chn:5; - uint32_t reserved_29:3; - }; - uint32_t val; -} dma2d_outfifo_status_chn_reg_t; - -/** Type of out_state_chn register - * Represents the working status of the tx descriptor of channel n - */ -typedef union { - struct { - /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - uint32_t outlink_dscr_addr_chn:18; - /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t out_dscr_state_chn:2; - /** out_state_chn : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t out_state_chn:4; - /** out_reset_avail_chn : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t out_reset_avail_chn:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} dma2d_out_state_chn_reg_t; - -/** Type of out_eof_des_addr_chn register - * Represents the address associated with the outlink descriptor of channel n - */ -typedef union { - struct { - /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_chn:32; - }; - uint32_t val; -} dma2d_out_eof_des_addr_chn_reg_t; - -/** Type of out_dscr_chn register - * Represents the address associated with the outlink descriptor of channel n - */ -typedef union { - struct { - /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ - uint32_t outlink_dscr_chn:32; - }; - uint32_t val; -} dma2d_out_dscr_chn_reg_t; - -/** Type of out_dscr_bf0_chn register - * Represents the address associated with the outlink descriptor of channel n - */ -typedef union { - struct { - /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ - uint32_t outlink_dscr_bf0_chn:32; - }; - uint32_t val; -} dma2d_out_dscr_bf0_chn_reg_t; - -/** Type of out_dscr_bf1_chn register - * Represents the address associated with the outlink descriptor of channel n - */ -typedef union { - struct { - /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ - uint32_t outlink_dscr_bf1_chn:32; - }; - uint32_t val; -} dma2d_out_dscr_bf1_chn_reg_t; - -/** Type of out_ro_status_chn register - * Represents the status of the tx reorder module of channel n - */ -typedef union { - struct { - /** outfifo_ro_cnt_chn : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ - uint32_t outfifo_ro_cnt_chn:6; - /** out_ro_wr_state_chn : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ - uint32_t out_ro_wr_state_chn:2; - /** out_ro_rd_state_chn : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ - uint32_t out_ro_rd_state_chn:2; - /** out_pixel_byte_chn : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ - uint32_t out_pixel_byte_chn:4; - /** out_burst_block_num_chn : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ - uint32_t out_burst_block_num_chn:4; - uint32_t reserved_18:14; - }; - uint32_t val; -} dma2d_out_ro_status_chn_reg_t; - -/** Type of infifo_status_chn register - * Represents the status of the rx fifo of channel n - */ -typedef union { - struct { - /** infifo_full_l2_chn : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ - uint32_t infifo_full_l2_chn:1; - /** infifo_empty_l2_chn : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ - uint32_t infifo_empty_l2_chn:1; - /** infifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ - uint32_t infifo_cnt_l2_chn:4; - uint32_t reserved_6:1; - /** in_remain_under_1b_chn : RO; bitpos: [7]; default: 0; - * reserved - */ - uint32_t in_remain_under_1b_chn:1; - /** in_remain_under_2b_chn : RO; bitpos: [8]; default: 0; - * reserved - */ - uint32_t in_remain_under_2b_chn:1; - /** in_remain_under_3b_chn : RO; bitpos: [9]; default: 0; - * reserved - */ - uint32_t in_remain_under_3b_chn:1; - /** in_remain_under_4b_chn : RO; bitpos: [10]; default: 0; - * reserved - */ - uint32_t in_remain_under_4b_chn:1; - /** in_remain_under_5b_chn : RO; bitpos: [11]; default: 0; - * reserved - */ - uint32_t in_remain_under_5b_chn:1; - /** in_remain_under_6b_chn : RO; bitpos: [12]; default: 0; - * reserved - */ - uint32_t in_remain_under_6b_chn:1; - /** in_remain_under_7b_chn : RO; bitpos: [13]; default: 0; - * reserved - */ - uint32_t in_remain_under_7b_chn:1; - /** in_remain_under_8b_chn : RO; bitpos: [14]; default: 0; - * reserved - */ - uint32_t in_remain_under_8b_chn:1; - /** infifo_full_l1_chn : RO; bitpos: [15]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ - uint32_t infifo_full_l1_chn:1; - /** infifo_empty_l1_chn : RO; bitpos: [16]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ - uint32_t infifo_empty_l1_chn:1; - /** infifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ - uint32_t infifo_cnt_l1_chn:5; - /** infifo_full_l3_chn : RO; bitpos: [22]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ - uint32_t infifo_full_l3_chn:1; - /** infifo_empty_l3_chn : RO; bitpos: [23]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ - uint32_t infifo_empty_l3_chn:1; - /** infifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ - uint32_t infifo_cnt_l3_chn:5; - uint32_t reserved_29:3; - }; - uint32_t val; -} dma2d_infifo_status_chn_reg_t; - -/** Type of in_state_chn register - * Represents the working status of the rx descriptor of channel n - */ -typedef union { - struct { - /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - uint32_t inlink_dscr_addr_chn:18; - /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t in_dscr_state_chn:2; - /** in_state_chn : RO; bitpos: [22:20]; default: 0; - * reserved - */ - uint32_t in_state_chn:3; - /** in_reset_avail_chn : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t in_reset_avail_chn:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} dma2d_in_state_chn_reg_t; - -/** Type of in_suc_eof_des_addr_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_chn:32; - }; - uint32_t val; -} dma2d_in_suc_eof_des_addr_chn_reg_t; - -/** Type of in_err_eof_des_addr_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ - uint32_t in_err_eof_des_addr_chn:32; - }; - uint32_t val; -} dma2d_in_err_eof_des_addr_chn_reg_t; - -/** Type of in_dscr_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ - uint32_t inlink_dscr_chn:32; - }; - uint32_t val; -} dma2d_in_dscr_chn_reg_t; - -/** Type of in_dscr_bf0_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ - uint32_t inlink_dscr_bf0_chn:32; - }; - uint32_t val; -} dma2d_in_dscr_bf0_chn_reg_t; - -/** Type of in_dscr_bf1_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ - uint32_t inlink_dscr_bf1_chn:32; - }; - uint32_t val; -} dma2d_in_dscr_bf1_chn_reg_t; - -/** Type of in_ro_status_chn register - * Represents the status of the rx reorder module of channel n - */ -typedef union { - struct { - /** infifo_ro_cnt_chn : RO; bitpos: [4:0]; default: 0; - * The register stores the byte number of the data in color convert Rx FIFO for - * channel 0. - */ - uint32_t infifo_ro_cnt_chn:5; - /** in_ro_wr_state_chn : RO; bitpos: [6:5]; default: 0; - * The register stores the state of read ram of reorder - */ - uint32_t in_ro_wr_state_chn:2; - /** in_ro_rd_state_chn : RO; bitpos: [8:7]; default: 0; - * The register stores the state of write ram of reorder - */ - uint32_t in_ro_rd_state_chn:2; - /** in_pixel_byte_chn : RO; bitpos: [12:9]; default: 0; - * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ - uint32_t in_pixel_byte_chn:4; - /** in_burst_block_num_chn : RO; bitpos: [16:13]; default: 0; - * the number of macro blocks contained in a burst of data at RX channel - */ - uint32_t in_burst_block_num_chn:4; - uint32_t reserved_17:15; - }; - uint32_t val; -} dma2d_in_ro_status_chn_reg_t; - -/** Type of axi_err register - * Represents the status of th axi bus - */ -typedef union { - struct { - /** rid_err_cnt : RO; bitpos: [3:0]; default: 0; - * AXI read id err cnt - */ - uint32_t rid_err_cnt:4; - /** rresp_err_cnt : RO; bitpos: [7:4]; default: 0; - * AXI read resp err cnt - */ - uint32_t rresp_err_cnt:4; - /** wresp_err_cnt : RO; bitpos: [11:8]; default: 0; - * AXI write resp err cnt - */ - uint32_t wresp_err_cnt:4; - /** rd_fifo_cnt : RO; bitpos: [14:12]; default: 0; - * AXI read cmd fifo remain cmd count - */ - uint32_t rd_fifo_cnt:3; - /** rd_bak_fifo_cnt : RO; bitpos: [18:15]; default: 0; - * AXI read backup cmd fifo remain cmd count - */ - uint32_t rd_bak_fifo_cnt:4; - /** wr_fifo_cnt : RO; bitpos: [21:19]; default: 0; - * AXI write cmd fifo remain cmd count - */ - uint32_t wr_fifo_cnt:3; - /** wr_bak_fifo_cnt : RO; bitpos: [25:22]; default: 0; - * AXI write backup cmd fifo remain cmd count - */ - uint32_t wr_bak_fifo_cnt:4; - uint32_t reserved_26:6; - }; - uint32_t val; -} dma2d_axi_err_reg_t; - -/** Type of date register - * register version. - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 37822864; - * register version. - */ - uint32_t date:32; - }; - uint32_t val; -} dma2d_date_reg_t; - - -/** Group: Peripheral Select Registers */ -/** Type of out_peri_sel_chn register - * Configures the tx peripheral of channel n - */ -typedef union { - struct { - /** out_peri_sel_chn : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ - uint32_t out_peri_sel_chn:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} dma2d_out_peri_sel_chn_reg_t; - -/** Type of in_peri_sel_chn register - * Configures the rx peripheral of channel n - */ -typedef union { - struct { - /** in_peri_sel_chn : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Rx channel 0: jpeg 1: - * display-1 2: display-2 7: no choose - */ - uint32_t in_peri_sel_chn:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} dma2d_in_peri_sel_chn_reg_t; - - -typedef struct { - volatile dma2d_out_conf0_chn_reg_t out_conf0_ch0; - volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch0; - volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch0; - volatile dma2d_out_int_st_chn_reg_t out_int_st_ch0; - volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch0; - volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch0; - volatile dma2d_out_push_chn_reg_t out_push_ch0; - volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch0; - volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch0; - volatile dma2d_out_state_chn_reg_t out_state_ch0; - volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0; - volatile dma2d_out_dscr_chn_reg_t out_dscr_ch0; - volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0; - volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0; - volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch0; - volatile dma2d_out_arb_chn_reg_t out_arb_ch0; - volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch0; - volatile dma2d_out_ro_pd_conf_chn_reg_t out_ro_pd_conf_ch0; - volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch0; - volatile dma2d_out_scramble_chn_reg_t out_scramble_ch0; - volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch0; - volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch0; - volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch0; - volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch0; - volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch0; - volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch0; - volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch0; - volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch0; - uint32_t reserved_070[36]; - volatile dma2d_out_conf0_chn_reg_t out_conf0_ch1; - volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch1; - volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch1; - volatile dma2d_out_int_st_chn_reg_t out_int_st_ch1; - volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch1; - volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch1; - volatile dma2d_out_push_chn_reg_t out_push_ch1; - volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch1; - volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch1; - volatile dma2d_out_state_chn_reg_t out_state_ch1; - volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1; - volatile dma2d_out_dscr_chn_reg_t out_dscr_ch1; - volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1; - volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1; - volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch1; - volatile dma2d_out_arb_chn_reg_t out_arb_ch1; - volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch1; - uint32_t reserved_144; - volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch1; - volatile dma2d_out_scramble_chn_reg_t out_scramble_ch1; - volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch1; - volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch1; - volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch1; - volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch1; - volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch1; - volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch1; - volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch1; - volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch1; - uint32_t reserved_170[36]; - volatile dma2d_out_conf0_chn_reg_t out_conf0_ch2; - volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch2; - volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch2; - volatile dma2d_out_int_st_chn_reg_t out_int_st_ch2; - volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch2; - volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch2; - volatile dma2d_out_push_chn_reg_t out_push_ch2; - volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch2; - volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch2; - volatile dma2d_out_state_chn_reg_t out_state_ch2; - volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2; - volatile dma2d_out_dscr_chn_reg_t out_dscr_ch2; - volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2; - volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2; - volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch2; - volatile dma2d_out_arb_chn_reg_t out_arb_ch2; - volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch2; - uint32_t reserved_244; - volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch2; - volatile dma2d_out_scramble_chn_reg_t out_scramble_ch2; - volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch2; - volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch2; - volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch2; - volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch2; - volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch2; - volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch2; - volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch2; - volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch2; - uint32_t reserved_270[36]; - volatile dma2d_out_conf0_chn_reg_t out_conf0_ch3; - volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch3; - volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch3; - volatile dma2d_out_int_st_chn_reg_t out_int_st_ch3; - volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch3; - volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch3; - volatile dma2d_out_push_chn_reg_t out_push_ch3; - volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch3; - volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch3; - volatile dma2d_out_state_chn_reg_t out_state_ch3; - volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch3; - volatile dma2d_out_dscr_chn_reg_t out_dscr_ch3; - volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch3; - volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch3; - volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch3; - volatile dma2d_out_arb_chn_reg_t out_arb_ch3; - volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch3; - uint32_t reserved_344; - volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch3; - volatile dma2d_out_scramble_chn_reg_t out_scramble_ch3; - volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch3; - volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch3; - volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch3; - volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch3; - volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch3; - volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch3; - volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch3; - volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch3; - uint32_t reserved_370[100]; - volatile dma2d_in_conf0_chn_reg_t in_conf0_ch0; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch0; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch0; - volatile dma2d_in_int_st_chn_reg_t in_int_st_ch0; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch0; - volatile dma2d_infifo_status_chn_reg_t infifo_status_ch0; - volatile dma2d_in_pop_chn_reg_t in_pop_ch0; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch0; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch0; - volatile dma2d_in_state_chn_reg_t in_state_ch0; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0; - volatile dma2d_in_dscr_chn_reg_t in_dscr_ch0; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch0; - volatile dma2d_in_arb_chn_reg_t in_arb_ch0; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch0; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch0; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch0; - volatile dma2d_in_scramble_chn_reg_t in_scramble_ch0; - volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch0; - volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch0; - volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch0; - volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch0; - volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch0; - volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch0; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch0; - uint32_t reserved_570[36]; - volatile dma2d_in_conf0_chn_reg_t in_conf0_ch1; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch1; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch1; - volatile dma2d_in_int_st_chn_reg_t in_int_st_ch1; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch1; - volatile dma2d_infifo_status_chn_reg_t infifo_status_ch1; - volatile dma2d_in_pop_chn_reg_t in_pop_ch1; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch1; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch1; - volatile dma2d_in_state_chn_reg_t in_state_ch1; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1; - volatile dma2d_in_dscr_chn_reg_t in_dscr_ch1; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch1; - volatile dma2d_in_arb_chn_reg_t in_arb_ch1; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch1; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch1; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch1; - volatile dma2d_in_scramble_chn_reg_t in_scramble_ch1; - volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch1; - volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch1; - volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch1; - volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch1; - volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch1; - volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch1; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch1; - uint32_t reserved_670[36]; - volatile dma2d_in_conf0_chn_reg_t in_conf0_ch2; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch2; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch2; - volatile dma2d_in_int_st_chn_reg_t in_int_st_ch2; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch2; - volatile dma2d_infifo_status_chn_reg_t infifo_status_ch2; - volatile dma2d_in_pop_chn_reg_t in_pop_ch2; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch2; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch2; - volatile dma2d_in_state_chn_reg_t in_state_ch2; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2; - volatile dma2d_in_dscr_chn_reg_t in_dscr_ch2; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch2; - volatile dma2d_in_arb_chn_reg_t in_arb_ch2; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch2; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch2; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch2; - volatile dma2d_in_scramble_chn_reg_t in_scramble_ch2; - volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch2; - volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch2; - volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch2; - volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch2; - volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch2; - volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch2; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch2; - uint32_t reserved_770[164]; - volatile dma2d_axi_err_reg_t axi_err; - volatile dma2d_rst_conf_reg_t rst_conf; - volatile dma2d_intr_mem_start_addr_reg_t intr_mem_start_addr; - volatile dma2d_intr_mem_end_addr_reg_t intr_mem_end_addr; - volatile dma2d_extr_mem_start_addr_reg_t extr_mem_start_addr; - volatile dma2d_extr_mem_end_addr_reg_t extr_mem_end_addr; - volatile dma2d_out_arb_config_reg_t out_arb_config; - volatile dma2d_in_arb_config_reg_t in_arb_config; - volatile dma2d_rdn_result_reg_t rdn_result; - volatile dma2d_rdn_eco_high_reg_t rdn_eco_high; - volatile dma2d_rdn_eco_low_reg_t rdn_eco_low; - volatile dma2d_date_reg_t date; -} dma2d_dev_t; - -extern dma2d_dev_t DMA2D; - -#ifndef __cplusplus -_Static_assert(sizeof(dma2d_dev_t) == 0xa30, "Invalid size of dma2d_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h index b16c0654e9..861ee70e05 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h @@ -11,8 +11,6 @@ extern "C" { #endif -//TODO: IDF-13427 - /** DMA2D_OUT_CONF0_CH0_REG register * Configures the tx direction of channel 0 */ @@ -811,12 +809,12 @@ extern "C" { #define DMA2D_OUT_ARB_TOKEN_NUM_CH0_M (DMA2D_OUT_ARB_TOKEN_NUM_CH0_V << DMA2D_OUT_ARB_TOKEN_NUM_CH0_S) #define DMA2D_OUT_ARB_TOKEN_NUM_CH0_V 0x0000000FU #define DMA2D_OUT_ARB_TOKEN_NUM_CH0_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [5:4]; default: 1; +/** DMA2D_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_OUT_ARB_PRIORITY_CH0 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH0 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH0_M (DMA2D_OUT_ARB_PRIORITY_CH0_V << DMA2D_OUT_ARB_PRIORITY_CH0_S) -#define DMA2D_OUT_ARB_PRIORITY_CH0_V 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH0_V 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH0_S 4 /** DMA2D_OUT_RO_STATUS_CH0_REG register @@ -1049,7 +1047,7 @@ extern "C" { #define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S 14 /** DMA2D_OUT_CONF0_CH1_REG register - * Configures the tx direction of channel 0 + * Configures the tx direction of channel 1 */ #define DMA2D_OUT_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x100) /** DMA2D_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [0]; default: 0; @@ -1162,7 +1160,7 @@ extern "C" { #define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S 26 /** DMA2D_OUT_INT_RAW_CH1_REG register - * Raw interrupt status of TX channel 0 + * Raw interrupt status of TX channel 1 */ #define DMA2D_OUT_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x104) /** DMA2D_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -1264,7 +1262,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S 12 /** DMA2D_OUT_INT_ENA_CH1_REG register - * Interrupt enable bits of TX channel 0 + * Interrupt enable bits of TX channel 1 */ #define DMA2D_OUT_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x108) /** DMA2D_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -1360,7 +1358,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S 12 /** DMA2D_OUT_INT_ST_CH1_REG register - * Masked interrupt status of TX channel 0 + * Masked interrupt status of TX channel 1 */ #define DMA2D_OUT_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x10c) /** DMA2D_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; @@ -1456,7 +1454,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S 12 /** DMA2D_OUT_INT_CLR_CH1_REG register - * Interrupt clear bits of TX channel 0 + * Interrupt clear bits of TX channel 1 */ #define DMA2D_OUT_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x110) /** DMA2D_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; @@ -1552,7 +1550,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S 12 /** DMA2D_OUTFIFO_STATUS_CH1_REG register - * Represents the status of the tx fifo of channel 0 + * Represents the status of the tx fifo of channel 1 */ #define DMA2D_OUTFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x114) /** DMA2D_OUTFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0; @@ -1676,7 +1674,7 @@ extern "C" { #define DMA2D_OUTFIFO_CNT_L3_CH1_S 24 /** DMA2D_OUT_PUSH_CH1_REG register - * Configures the tx fifo of channel 0 + * Configures the tx fifo of channel 1 */ #define DMA2D_OUT_PUSH_CH1_REG (DR_REG_DMA2D_BASE + 0x118) /** DMA2D_OUTFIFO_WDATA_CH1 : R/W; bitpos: [9:0]; default: 0; @@ -1695,7 +1693,7 @@ extern "C" { #define DMA2D_OUTFIFO_PUSH_CH1_S 10 /** DMA2D_OUT_LINK_CONF_CH1_REG register - * Configures the tx descriptor operations of channel 0 + * Configures the tx descriptor operations of channel 1 */ #define DMA2D_OUT_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x11c) /** DMA2D_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0; @@ -1729,7 +1727,7 @@ extern "C" { #define DMA2D_OUTLINK_PARK_CH1_S 23 /** DMA2D_OUT_LINK_ADDR_CH1_REG register - * Configures the tx descriptor address of channel 0 + * Configures the tx descriptor address of channel 1 */ #define DMA2D_OUT_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x120) /** DMA2D_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; @@ -1741,7 +1739,7 @@ extern "C" { #define DMA2D_OUTLINK_ADDR_CH1_S 0 /** DMA2D_OUT_STATE_CH1_REG register - * Represents the working status of the tx descriptor of channel 0 + * Represents the working status of the tx descriptor of channel 1 */ #define DMA2D_OUT_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x124) /** DMA2D_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; @@ -1774,7 +1772,7 @@ extern "C" { #define DMA2D_OUT_RESET_AVAIL_CH1_S 24 /** DMA2D_OUT_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 1 */ #define DMA2D_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x128) /** DMA2D_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -1787,7 +1785,7 @@ extern "C" { #define DMA2D_OUT_EOF_DES_ADDR_CH1_S 0 /** DMA2D_OUT_DSCR_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 1 */ #define DMA2D_OUT_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x12c) /** DMA2D_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -1799,7 +1797,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_CH1_S 0 /** DMA2D_OUT_DSCR_BF0_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 1 */ #define DMA2D_OUT_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x130) /** DMA2D_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; @@ -1811,7 +1809,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_BF0_CH1_S 0 /** DMA2D_OUT_DSCR_BF1_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 1 */ #define DMA2D_OUT_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x134) /** DMA2D_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; @@ -1823,7 +1821,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_BF1_CH1_S 0 /** DMA2D_OUT_PERI_SEL_CH1_REG register - * Configures the tx peripheral of channel 0 + * Configures the tx peripheral of channel 1 */ #define DMA2D_OUT_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x138) /** DMA2D_OUT_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7; @@ -1836,7 +1834,7 @@ extern "C" { #define DMA2D_OUT_PERI_SEL_CH1_S 0 /** DMA2D_OUT_ARB_CH1_REG register - * Configures the tx arbiter of channel 0 + * Configures the tx arbiter of channel 1 */ #define DMA2D_OUT_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x13c) /** DMA2D_OUT_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1; @@ -1846,16 +1844,16 @@ extern "C" { #define DMA2D_OUT_ARB_TOKEN_NUM_CH1_M (DMA2D_OUT_ARB_TOKEN_NUM_CH1_V << DMA2D_OUT_ARB_TOKEN_NUM_CH1_S) #define DMA2D_OUT_ARB_TOKEN_NUM_CH1_V 0x0000000FU #define DMA2D_OUT_ARB_TOKEN_NUM_CH1_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [5:4]; default: 1; +/** DMA2D_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_OUT_ARB_PRIORITY_CH1 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH1 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH1_M (DMA2D_OUT_ARB_PRIORITY_CH1_V << DMA2D_OUT_ARB_PRIORITY_CH1_S) -#define DMA2D_OUT_ARB_PRIORITY_CH1_V 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH1_V 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH1_S 4 /** DMA2D_OUT_RO_STATUS_CH1_REG register - * Represents the status of the tx reorder module of channel 0 + * Represents the status of the tx reorder module of channel 1 */ #define DMA2D_OUT_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x140) /** DMA2D_OUTFIFO_RO_CNT_CH1 : RO; bitpos: [5:0]; default: 0; @@ -1897,7 +1895,7 @@ extern "C" { #define DMA2D_OUT_BURST_BLOCK_NUM_CH1_S 14 /** DMA2D_OUT_COLOR_CONVERT_CH1_REG register - * Configures the tx color convert of channel 0 + * Configures the tx color convert of channel 1 */ #define DMA2D_OUT_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x148) /** DMA2D_OUT_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; @@ -1927,7 +1925,7 @@ extern "C" { #define DMA2D_OUT_COLOR_INPUT_SEL_CH1_S 3 /** DMA2D_OUT_SCRAMBLE_CH1_REG register - * Configures the tx scramble of channel 0 + * Configures the tx scramble of channel 1 */ #define DMA2D_OUT_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x14c) /** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0; @@ -1940,7 +1938,7 @@ extern "C" { #define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM0_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x150) /** DMA2D_OUT_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298; @@ -1952,7 +1950,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_H0_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM1_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x154) /** DMA2D_OUT_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121; @@ -1964,7 +1962,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_H1_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM2_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x158) /** DMA2D_OUT_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050; @@ -1976,7 +1974,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_M0_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM3_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x15c) /** DMA2D_OUT_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784; @@ -1988,7 +1986,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_M1_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM4_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x160) /** DMA2D_OUT_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682; @@ -2000,7 +1998,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_L0_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM5_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x164) /** DMA2D_OUT_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392; @@ -2012,7 +2010,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_L1_CH1_S 0 /** DMA2D_OUT_ETM_CONF_CH1_REG register - * Configures the tx etm of channel 0 + * Configures the tx etm of channel 1 */ #define DMA2D_OUT_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x168) /** DMA2D_OUT_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0; @@ -2057,7 +2055,7 @@ extern "C" { #define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S 14 /** DMA2D_OUT_CONF0_CH2_REG register - * Configures the tx direction of channel 0 + * Configures the tx direction of channel 2 */ #define DMA2D_OUT_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x200) /** DMA2D_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [0]; default: 0; @@ -2170,7 +2168,7 @@ extern "C" { #define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S 26 /** DMA2D_OUT_INT_RAW_CH2_REG register - * Raw interrupt status of TX channel 0 + * Raw interrupt status of TX channel 2 */ #define DMA2D_OUT_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x204) /** DMA2D_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -2272,7 +2270,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S 12 /** DMA2D_OUT_INT_ENA_CH2_REG register - * Interrupt enable bits of TX channel 0 + * Interrupt enable bits of TX channel 2 */ #define DMA2D_OUT_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x208) /** DMA2D_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -2368,7 +2366,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S 12 /** DMA2D_OUT_INT_ST_CH2_REG register - * Masked interrupt status of TX channel 0 + * Masked interrupt status of TX channel 2 */ #define DMA2D_OUT_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x20c) /** DMA2D_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; @@ -2464,7 +2462,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S 12 /** DMA2D_OUT_INT_CLR_CH2_REG register - * Interrupt clear bits of TX channel 0 + * Interrupt clear bits of TX channel 2 */ #define DMA2D_OUT_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x210) /** DMA2D_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; @@ -2560,7 +2558,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S 12 /** DMA2D_OUTFIFO_STATUS_CH2_REG register - * Represents the status of the tx fifo of channel 0 + * Represents the status of the tx fifo of channel 2 */ #define DMA2D_OUTFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x214) /** DMA2D_OUTFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0; @@ -2684,7 +2682,7 @@ extern "C" { #define DMA2D_OUTFIFO_CNT_L3_CH2_S 24 /** DMA2D_OUT_PUSH_CH2_REG register - * Configures the tx fifo of channel 0 + * Configures the tx fifo of channel 2 */ #define DMA2D_OUT_PUSH_CH2_REG (DR_REG_DMA2D_BASE + 0x218) /** DMA2D_OUTFIFO_WDATA_CH2 : R/W; bitpos: [9:0]; default: 0; @@ -2703,7 +2701,7 @@ extern "C" { #define DMA2D_OUTFIFO_PUSH_CH2_S 10 /** DMA2D_OUT_LINK_CONF_CH2_REG register - * Configures the tx descriptor operations of channel 0 + * Configures the tx descriptor operations of channel 2 */ #define DMA2D_OUT_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x21c) /** DMA2D_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0; @@ -2737,7 +2735,7 @@ extern "C" { #define DMA2D_OUTLINK_PARK_CH2_S 23 /** DMA2D_OUT_LINK_ADDR_CH2_REG register - * Configures the tx descriptor address of channel 0 + * Configures the tx descriptor address of channel 2 */ #define DMA2D_OUT_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x220) /** DMA2D_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; @@ -2749,7 +2747,7 @@ extern "C" { #define DMA2D_OUTLINK_ADDR_CH2_S 0 /** DMA2D_OUT_STATE_CH2_REG register - * Represents the working status of the tx descriptor of channel 0 + * Represents the working status of the tx descriptor of channel 2 */ #define DMA2D_OUT_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x224) /** DMA2D_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; @@ -2782,7 +2780,7 @@ extern "C" { #define DMA2D_OUT_RESET_AVAIL_CH2_S 24 /** DMA2D_OUT_EOF_DES_ADDR_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 2 */ #define DMA2D_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x228) /** DMA2D_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2795,7 +2793,7 @@ extern "C" { #define DMA2D_OUT_EOF_DES_ADDR_CH2_S 0 /** DMA2D_OUT_DSCR_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 2 */ #define DMA2D_OUT_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x22c) /** DMA2D_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2807,7 +2805,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_CH2_S 0 /** DMA2D_OUT_DSCR_BF0_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 2 */ #define DMA2D_OUT_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x230) /** DMA2D_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2819,7 +2817,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_BF0_CH2_S 0 /** DMA2D_OUT_DSCR_BF1_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 2 */ #define DMA2D_OUT_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x234) /** DMA2D_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2831,7 +2829,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_BF1_CH2_S 0 /** DMA2D_OUT_PERI_SEL_CH2_REG register - * Configures the tx peripheral of channel 0 + * Configures the tx peripheral of channel 2 */ #define DMA2D_OUT_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x238) /** DMA2D_OUT_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7; @@ -2844,7 +2842,7 @@ extern "C" { #define DMA2D_OUT_PERI_SEL_CH2_S 0 /** DMA2D_OUT_ARB_CH2_REG register - * Configures the tx arbiter of channel 0 + * Configures the tx arbiter of channel 2 */ #define DMA2D_OUT_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x23c) /** DMA2D_OUT_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1; @@ -2854,16 +2852,16 @@ extern "C" { #define DMA2D_OUT_ARB_TOKEN_NUM_CH2_M (DMA2D_OUT_ARB_TOKEN_NUM_CH2_V << DMA2D_OUT_ARB_TOKEN_NUM_CH2_S) #define DMA2D_OUT_ARB_TOKEN_NUM_CH2_V 0x0000000FU #define DMA2D_OUT_ARB_TOKEN_NUM_CH2_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [5:4]; default: 1; +/** DMA2D_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_OUT_ARB_PRIORITY_CH2 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH2 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH2_M (DMA2D_OUT_ARB_PRIORITY_CH2_V << DMA2D_OUT_ARB_PRIORITY_CH2_S) -#define DMA2D_OUT_ARB_PRIORITY_CH2_V 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH2_V 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH2_S 4 /** DMA2D_OUT_RO_STATUS_CH2_REG register - * Represents the status of the tx reorder module of channel 0 + * Represents the status of the tx reorder module of channel 2 */ #define DMA2D_OUT_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x240) /** DMA2D_OUTFIFO_RO_CNT_CH2 : RO; bitpos: [5:0]; default: 0; @@ -2905,7 +2903,7 @@ extern "C" { #define DMA2D_OUT_BURST_BLOCK_NUM_CH2_S 14 /** DMA2D_OUT_COLOR_CONVERT_CH2_REG register - * Configures the tx color convert of channel 0 + * Configures the tx color convert of channel 2 */ #define DMA2D_OUT_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x248) /** DMA2D_OUT_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; @@ -2935,7 +2933,7 @@ extern "C" { #define DMA2D_OUT_COLOR_INPUT_SEL_CH2_S 3 /** DMA2D_OUT_SCRAMBLE_CH2_REG register - * Configures the tx scramble of channel 0 + * Configures the tx scramble of channel 2 */ #define DMA2D_OUT_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x24c) /** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0; @@ -2948,7 +2946,7 @@ extern "C" { #define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM0_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x250) /** DMA2D_OUT_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298; @@ -2960,7 +2958,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_H0_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM1_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x254) /** DMA2D_OUT_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121; @@ -2972,7 +2970,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_H1_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM2_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x258) /** DMA2D_OUT_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050; @@ -2984,7 +2982,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_M0_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM3_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x25c) /** DMA2D_OUT_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784; @@ -2996,7 +2994,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_M1_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM4_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x260) /** DMA2D_OUT_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682; @@ -3008,7 +3006,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_L0_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM5_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x264) /** DMA2D_OUT_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392; @@ -3020,7 +3018,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_L1_CH2_S 0 /** DMA2D_OUT_ETM_CONF_CH2_REG register - * Configures the tx etm of channel 0 + * Configures the tx etm of channel 2 */ #define DMA2D_OUT_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x268) /** DMA2D_OUT_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0; @@ -3064,6 +3062,1014 @@ extern "C" { #define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V 0x00003FFFU #define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S 14 +/** DMA2D_OUT_CONF0_CH3_REG register + * Configures the tx direction of channel 3 + */ +#define DMA2D_OUT_CONF0_CH3_REG (DR_REG_DMA2D_BASE + 0x300) +/** DMA2D_OUT_AUTO_WRBACK_CH3 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data pointed by + * outlink descriptor has been received. + */ +#define DMA2D_OUT_AUTO_WRBACK_CH3 (BIT(0)) +#define DMA2D_OUT_AUTO_WRBACK_CH3_M (DMA2D_OUT_AUTO_WRBACK_CH3_V << DMA2D_OUT_AUTO_WRBACK_CH3_S) +#define DMA2D_OUT_AUTO_WRBACK_CH3_V 0x00000001U +#define DMA2D_OUT_AUTO_WRBACK_CH3_S 0 +/** DMA2D_OUT_EOF_MODE_CH3 : R/W; bitpos: [1]; default: 1; + * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is + * generated when data need to read has been popped from FIFO in DMA + */ +#define DMA2D_OUT_EOF_MODE_CH3 (BIT(1)) +#define DMA2D_OUT_EOF_MODE_CH3_M (DMA2D_OUT_EOF_MODE_CH3_V << DMA2D_OUT_EOF_MODE_CH3_S) +#define DMA2D_OUT_EOF_MODE_CH3_V 0x00000001U +#define DMA2D_OUT_EOF_MODE_CH3_S 1 +/** DMA2D_OUTDSCR_BURST_EN_CH3 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define DMA2D_OUTDSCR_BURST_EN_CH3 (BIT(2)) +#define DMA2D_OUTDSCR_BURST_EN_CH3_M (DMA2D_OUTDSCR_BURST_EN_CH3_V << DMA2D_OUTDSCR_BURST_EN_CH3_S) +#define DMA2D_OUTDSCR_BURST_EN_CH3_V 0x00000001U +#define DMA2D_OUTDSCR_BURST_EN_CH3_S 2 +/** DMA2D_OUT_ECC_AES_EN_CH3 : R/W; bitpos: [3]; default: 0; + * When access address space is ecc/aes area, this bit should be set to 1. In this + * case, the start address of square should be 16-bit aligned. The width of square + * multiply byte number of one pixel should be 16-bit aligned. + */ +#define DMA2D_OUT_ECC_AES_EN_CH3 (BIT(3)) +#define DMA2D_OUT_ECC_AES_EN_CH3_M (DMA2D_OUT_ECC_AES_EN_CH3_V << DMA2D_OUT_ECC_AES_EN_CH3_S) +#define DMA2D_OUT_ECC_AES_EN_CH3_V 0x00000001U +#define DMA2D_OUT_ECC_AES_EN_CH3_S 3 +/** DMA2D_OUT_CHECK_OWNER_CH3 : R/W; bitpos: [4]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define DMA2D_OUT_CHECK_OWNER_CH3 (BIT(4)) +#define DMA2D_OUT_CHECK_OWNER_CH3_M (DMA2D_OUT_CHECK_OWNER_CH3_V << DMA2D_OUT_CHECK_OWNER_CH3_S) +#define DMA2D_OUT_CHECK_OWNER_CH3_V 0x00000001U +#define DMA2D_OUT_CHECK_OWNER_CH3_S 4 +/** DMA2D_OUT_LOOP_TEST_CH3 : R/W; bitpos: [5]; default: 0; + * reserved + */ +#define DMA2D_OUT_LOOP_TEST_CH3 (BIT(5)) +#define DMA2D_OUT_LOOP_TEST_CH3_M (DMA2D_OUT_LOOP_TEST_CH3_V << DMA2D_OUT_LOOP_TEST_CH3_S) +#define DMA2D_OUT_LOOP_TEST_CH3_V 0x00000001U +#define DMA2D_OUT_LOOP_TEST_CH3_S 5 +/** DMA2D_OUT_MEM_BURST_LENGTH_CH3 : R/W; bitpos: [8:6]; default: 0; + * Block size of Tx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 + * bytes 4: 128 bytes + */ +#define DMA2D_OUT_MEM_BURST_LENGTH_CH3 0x00000007U +#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_M (DMA2D_OUT_MEM_BURST_LENGTH_CH3_V << DMA2D_OUT_MEM_BURST_LENGTH_CH3_S) +#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_V 0x00000007U +#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_S 6 +/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 : R/W; bitpos: [10:9]; default: 0; + * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: + * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link + * descriptor + */ +#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 0x00000003U +#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S) +#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V 0x00000003U +#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S 9 +/** DMA2D_OUT_DSCR_PORT_EN_CH3 : R/W; bitpos: [11]; default: 0; + * Set this bit to 1 to obtain descriptor from IP port + */ +#define DMA2D_OUT_DSCR_PORT_EN_CH3 (BIT(11)) +#define DMA2D_OUT_DSCR_PORT_EN_CH3_M (DMA2D_OUT_DSCR_PORT_EN_CH3_V << DMA2D_OUT_DSCR_PORT_EN_CH3_S) +#define DMA2D_OUT_DSCR_PORT_EN_CH3_V 0x00000001U +#define DMA2D_OUT_DSCR_PORT_EN_CH3_S 11 +/** DMA2D_OUT_PAGE_BOUND_EN_CH3 : R/W; bitpos: [12]; default: 0; + * Set this bit to 1 to make sure AXI read data don't cross the address boundary which + * define by mem_burst_length + */ +#define DMA2D_OUT_PAGE_BOUND_EN_CH3 (BIT(12)) +#define DMA2D_OUT_PAGE_BOUND_EN_CH3_M (DMA2D_OUT_PAGE_BOUND_EN_CH3_V << DMA2D_OUT_PAGE_BOUND_EN_CH3_S) +#define DMA2D_OUT_PAGE_BOUND_EN_CH3_V 0x00000001U +#define DMA2D_OUT_PAGE_BOUND_EN_CH3_S 12 +/** DMA2D_OUT_REORDER_EN_CH3 : R/W; bitpos: [16]; default: 0; + * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this + * selection + */ +#define DMA2D_OUT_REORDER_EN_CH3 (BIT(16)) +#define DMA2D_OUT_REORDER_EN_CH3_M (DMA2D_OUT_REORDER_EN_CH3_V << DMA2D_OUT_REORDER_EN_CH3_S) +#define DMA2D_OUT_REORDER_EN_CH3_V 0x00000001U +#define DMA2D_OUT_REORDER_EN_CH3_S 16 +/** DMA2D_OUT_RST_CH3 : R/W; bitpos: [24]; default: 0; + * Write 1 then write 0 to this bit to reset TX channel + */ +#define DMA2D_OUT_RST_CH3 (BIT(24)) +#define DMA2D_OUT_RST_CH3_M (DMA2D_OUT_RST_CH3_V << DMA2D_OUT_RST_CH3_S) +#define DMA2D_OUT_RST_CH3_V 0x00000001U +#define DMA2D_OUT_RST_CH3_S 24 +/** DMA2D_OUT_CMD_DISABLE_CH3 : R/W; bitpos: [25]; default: 0; + * Write 1 before reset and write 0 after reset + */ +#define DMA2D_OUT_CMD_DISABLE_CH3 (BIT(25)) +#define DMA2D_OUT_CMD_DISABLE_CH3_M (DMA2D_OUT_CMD_DISABLE_CH3_V << DMA2D_OUT_CMD_DISABLE_CH3_S) +#define DMA2D_OUT_CMD_DISABLE_CH3_V 0x00000001U +#define DMA2D_OUT_CMD_DISABLE_CH3_S 25 +/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 : R/W; bitpos: [26]; default: 0; + * Set this bit to 1 to disable arbiter optimum weight function. + */ +#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 (BIT(26)) +#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S) +#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V 0x00000001U +#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S 26 + +/** DMA2D_OUT_INT_RAW_CH3_REG register + * Raw interrupt status of TX channel 3 + */ +#define DMA2D_OUT_INT_RAW_CH3_REG (DR_REG_DMA2D_BASE + 0x304) +/** DMA2D_OUT_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ +#define DMA2D_OUT_DONE_CH3_INT_RAW (BIT(0)) +#define DMA2D_OUT_DONE_CH3_INT_RAW_M (DMA2D_OUT_DONE_CH3_INT_RAW_V << DMA2D_OUT_DONE_CH3_INT_RAW_S) +#define DMA2D_OUT_DONE_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_DONE_CH3_INT_RAW_S 0 +/** DMA2D_OUT_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ +#define DMA2D_OUT_EOF_CH3_INT_RAW (BIT(1)) +#define DMA2D_OUT_EOF_CH3_INT_RAW_M (DMA2D_OUT_EOF_CH3_INT_RAW_V << DMA2D_OUT_EOF_CH3_INT_RAW_S) +#define DMA2D_OUT_EOF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_EOF_CH3_INT_RAW_S 1 +/** DMA2D_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error, + * including owner error, the second and third word error of outlink descriptor for Tx + * channel 0. + */ +#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW (BIT(2)) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S 2 +/** DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW (BIT(3)) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S 3 +/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when fifo is overflow. + */ +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW (BIT(4)) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S 4 +/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when fifo is underflow. + */ +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW (BIT(5)) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S 5 +/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when fifo is overflow. + */ +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW (BIT(6)) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S 6 +/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when fifo is underflow. + */ +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW (BIT(7)) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S 7 +/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when fifo is overflow. + */ +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW (BIT(8)) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S 8 +/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when fifo is underflow. + */ +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW (BIT(9)) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S 9 +/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when reorder fifo is overflow. + */ +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW (BIT(10)) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S 10 +/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when reorder fifo is underflow. + */ +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW (BIT(11)) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S 11 +/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + */ +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW (BIT(12)) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S 12 + +/** DMA2D_OUT_INT_ENA_CH3_REG register + * Interrupt enable bits of TX channel 3 + */ +#define DMA2D_OUT_INT_ENA_CH3_REG (DR_REG_DMA2D_BASE + 0x308) +/** DMA2D_OUT_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define DMA2D_OUT_DONE_CH3_INT_ENA (BIT(0)) +#define DMA2D_OUT_DONE_CH3_INT_ENA_M (DMA2D_OUT_DONE_CH3_INT_ENA_V << DMA2D_OUT_DONE_CH3_INT_ENA_S) +#define DMA2D_OUT_DONE_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_DONE_CH3_INT_ENA_S 0 +/** DMA2D_OUT_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define DMA2D_OUT_EOF_CH3_INT_ENA (BIT(1)) +#define DMA2D_OUT_EOF_CH3_INT_ENA_M (DMA2D_OUT_EOF_CH3_INT_ENA_V << DMA2D_OUT_EOF_CH3_INT_ENA_S) +#define DMA2D_OUT_EOF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_EOF_CH3_INT_ENA_S 1 +/** DMA2D_OUT_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA (BIT(2)) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S 2 +/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA (BIT(3)) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S 3 +/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA (BIT(4)) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S 4 +/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA (BIT(5)) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S 5 +/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA (BIT(6)) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S 6 +/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA (BIT(7)) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S 7 +/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA (BIT(8)) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S 8 +/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA (BIT(9)) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S 9 +/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA (BIT(10)) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S 10 +/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA (BIT(11)) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S 11 +/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA (BIT(12)) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S 12 + +/** DMA2D_OUT_INT_ST_CH3_REG register + * Masked interrupt status of TX channel 3 + */ +#define DMA2D_OUT_INT_ST_CH3_REG (DR_REG_DMA2D_BASE + 0x30c) +/** DMA2D_OUT_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define DMA2D_OUT_DONE_CH3_INT_ST (BIT(0)) +#define DMA2D_OUT_DONE_CH3_INT_ST_M (DMA2D_OUT_DONE_CH3_INT_ST_V << DMA2D_OUT_DONE_CH3_INT_ST_S) +#define DMA2D_OUT_DONE_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_DONE_CH3_INT_ST_S 0 +/** DMA2D_OUT_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define DMA2D_OUT_EOF_CH3_INT_ST (BIT(1)) +#define DMA2D_OUT_EOF_CH3_INT_ST_M (DMA2D_OUT_EOF_CH3_INT_ST_V << DMA2D_OUT_EOF_CH3_INT_ST_S) +#define DMA2D_OUT_EOF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_EOF_CH3_INT_ST_S 1 +/** DMA2D_OUT_DSCR_ERR_CH3_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST (BIT(2)) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S 2 +/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST (BIT(3)) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S 3 +/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST (BIT(4)) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S 4 +/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST (BIT(5)) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S 5 +/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST (BIT(6)) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S 6 +/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST (BIT(7)) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S 7 +/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST (BIT(8)) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S 8 +/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST (BIT(9)) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S 9 +/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST (BIT(10)) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S 10 +/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST (BIT(11)) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S 11 +/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST (BIT(12)) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S 12 + +/** DMA2D_OUT_INT_CLR_CH3_REG register + * Interrupt clear bits of TX channel 3 + */ +#define DMA2D_OUT_INT_CLR_CH3_REG (DR_REG_DMA2D_BASE + 0x310) +/** DMA2D_OUT_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define DMA2D_OUT_DONE_CH3_INT_CLR (BIT(0)) +#define DMA2D_OUT_DONE_CH3_INT_CLR_M (DMA2D_OUT_DONE_CH3_INT_CLR_V << DMA2D_OUT_DONE_CH3_INT_CLR_S) +#define DMA2D_OUT_DONE_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_DONE_CH3_INT_CLR_S 0 +/** DMA2D_OUT_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define DMA2D_OUT_EOF_CH3_INT_CLR (BIT(1)) +#define DMA2D_OUT_EOF_CH3_INT_CLR_M (DMA2D_OUT_EOF_CH3_INT_CLR_V << DMA2D_OUT_EOF_CH3_INT_CLR_S) +#define DMA2D_OUT_EOF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_EOF_CH3_INT_CLR_S 1 +/** DMA2D_OUT_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR (BIT(2)) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S 2 +/** DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR (BIT(3)) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S 3 +/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR (BIT(4)) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S 4 +/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR (BIT(5)) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S 5 +/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR (BIT(6)) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S 6 +/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR (BIT(7)) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S 7 +/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR (BIT(8)) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S 8 +/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR (BIT(9)) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S 9 +/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR (BIT(10)) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S 10 +/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR (BIT(11)) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S 11 +/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR (BIT(12)) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S 12 + +/** DMA2D_OUTFIFO_STATUS_CH3_REG register + * Represents the status of the tx fifo of channel 3 + */ +#define DMA2D_OUTFIFO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x314) +/** DMA2D_OUTFIFO_FULL_L2_CH3 : RO; bitpos: [0]; default: 0; + * Tx FIFO full signal for Tx channel 0. + */ +#define DMA2D_OUTFIFO_FULL_L2_CH3 (BIT(0)) +#define DMA2D_OUTFIFO_FULL_L2_CH3_M (DMA2D_OUTFIFO_FULL_L2_CH3_V << DMA2D_OUTFIFO_FULL_L2_CH3_S) +#define DMA2D_OUTFIFO_FULL_L2_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_FULL_L2_CH3_S 0 +/** DMA2D_OUTFIFO_EMPTY_L2_CH3 : RO; bitpos: [1]; default: 1; + * Tx FIFO empty signal for Tx channel 0. + */ +#define DMA2D_OUTFIFO_EMPTY_L2_CH3 (BIT(1)) +#define DMA2D_OUTFIFO_EMPTY_L2_CH3_M (DMA2D_OUTFIFO_EMPTY_L2_CH3_V << DMA2D_OUTFIFO_EMPTY_L2_CH3_S) +#define DMA2D_OUTFIFO_EMPTY_L2_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_EMPTY_L2_CH3_S 1 +/** DMA2D_OUTFIFO_CNT_L2_CH3 : RO; bitpos: [5:2]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + */ +#define DMA2D_OUTFIFO_CNT_L2_CH3 0x0000000FU +#define DMA2D_OUTFIFO_CNT_L2_CH3_M (DMA2D_OUTFIFO_CNT_L2_CH3_V << DMA2D_OUTFIFO_CNT_L2_CH3_S) +#define DMA2D_OUTFIFO_CNT_L2_CH3_V 0x0000000FU +#define DMA2D_OUTFIFO_CNT_L2_CH3_S 2 +/** DMA2D_OUT_REMAIN_UNDER_1B_CH3 : RO; bitpos: [7]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_1B_CH3 (BIT(7)) +#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_M (DMA2D_OUT_REMAIN_UNDER_1B_CH3_V << DMA2D_OUT_REMAIN_UNDER_1B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_S 7 +/** DMA2D_OUT_REMAIN_UNDER_2B_CH3 : RO; bitpos: [8]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_2B_CH3 (BIT(8)) +#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_M (DMA2D_OUT_REMAIN_UNDER_2B_CH3_V << DMA2D_OUT_REMAIN_UNDER_2B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_S 8 +/** DMA2D_OUT_REMAIN_UNDER_3B_CH3 : RO; bitpos: [9]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_3B_CH3 (BIT(9)) +#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_M (DMA2D_OUT_REMAIN_UNDER_3B_CH3_V << DMA2D_OUT_REMAIN_UNDER_3B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_S 9 +/** DMA2D_OUT_REMAIN_UNDER_4B_CH3 : RO; bitpos: [10]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_4B_CH3 (BIT(10)) +#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_M (DMA2D_OUT_REMAIN_UNDER_4B_CH3_V << DMA2D_OUT_REMAIN_UNDER_4B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_S 10 +/** DMA2D_OUT_REMAIN_UNDER_5B_CH3 : RO; bitpos: [11]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_5B_CH3 (BIT(11)) +#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_M (DMA2D_OUT_REMAIN_UNDER_5B_CH3_V << DMA2D_OUT_REMAIN_UNDER_5B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_S 11 +/** DMA2D_OUT_REMAIN_UNDER_6B_CH3 : RO; bitpos: [12]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_6B_CH3 (BIT(12)) +#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_M (DMA2D_OUT_REMAIN_UNDER_6B_CH3_V << DMA2D_OUT_REMAIN_UNDER_6B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_S 12 +/** DMA2D_OUT_REMAIN_UNDER_7B_CH3 : RO; bitpos: [13]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_7B_CH3 (BIT(13)) +#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_M (DMA2D_OUT_REMAIN_UNDER_7B_CH3_V << DMA2D_OUT_REMAIN_UNDER_7B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_S 13 +/** DMA2D_OUT_REMAIN_UNDER_8B_CH3 : RO; bitpos: [14]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_8B_CH3 (BIT(14)) +#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_M (DMA2D_OUT_REMAIN_UNDER_8B_CH3_V << DMA2D_OUT_REMAIN_UNDER_8B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_S 14 +/** DMA2D_OUTFIFO_FULL_L1_CH3 : RO; bitpos: [15]; default: 0; + * Tx FIFO full signal for Tx channel 0. + */ +#define DMA2D_OUTFIFO_FULL_L1_CH3 (BIT(15)) +#define DMA2D_OUTFIFO_FULL_L1_CH3_M (DMA2D_OUTFIFO_FULL_L1_CH3_V << DMA2D_OUTFIFO_FULL_L1_CH3_S) +#define DMA2D_OUTFIFO_FULL_L1_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_FULL_L1_CH3_S 15 +/** DMA2D_OUTFIFO_EMPTY_L1_CH3 : RO; bitpos: [16]; default: 1; + * Tx FIFO empty signal for Tx channel 0. + */ +#define DMA2D_OUTFIFO_EMPTY_L1_CH3 (BIT(16)) +#define DMA2D_OUTFIFO_EMPTY_L1_CH3_M (DMA2D_OUTFIFO_EMPTY_L1_CH3_V << DMA2D_OUTFIFO_EMPTY_L1_CH3_S) +#define DMA2D_OUTFIFO_EMPTY_L1_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_EMPTY_L1_CH3_S 16 +/** DMA2D_OUTFIFO_CNT_L1_CH3 : RO; bitpos: [21:17]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + */ +#define DMA2D_OUTFIFO_CNT_L1_CH3 0x0000001FU +#define DMA2D_OUTFIFO_CNT_L1_CH3_M (DMA2D_OUTFIFO_CNT_L1_CH3_V << DMA2D_OUTFIFO_CNT_L1_CH3_S) +#define DMA2D_OUTFIFO_CNT_L1_CH3_V 0x0000001FU +#define DMA2D_OUTFIFO_CNT_L1_CH3_S 17 +/** DMA2D_OUTFIFO_FULL_L3_CH3 : RO; bitpos: [22]; default: 0; + * Tx FIFO full signal for Tx channel 0. + */ +#define DMA2D_OUTFIFO_FULL_L3_CH3 (BIT(22)) +#define DMA2D_OUTFIFO_FULL_L3_CH3_M (DMA2D_OUTFIFO_FULL_L3_CH3_V << DMA2D_OUTFIFO_FULL_L3_CH3_S) +#define DMA2D_OUTFIFO_FULL_L3_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_FULL_L3_CH3_S 22 +/** DMA2D_OUTFIFO_EMPTY_L3_CH3 : RO; bitpos: [23]; default: 1; + * Tx FIFO empty signal for Tx channel 0. + */ +#define DMA2D_OUTFIFO_EMPTY_L3_CH3 (BIT(23)) +#define DMA2D_OUTFIFO_EMPTY_L3_CH3_M (DMA2D_OUTFIFO_EMPTY_L3_CH3_V << DMA2D_OUTFIFO_EMPTY_L3_CH3_S) +#define DMA2D_OUTFIFO_EMPTY_L3_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_EMPTY_L3_CH3_S 23 +/** DMA2D_OUTFIFO_CNT_L3_CH3 : RO; bitpos: [28:24]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + */ +#define DMA2D_OUTFIFO_CNT_L3_CH3 0x0000001FU +#define DMA2D_OUTFIFO_CNT_L3_CH3_M (DMA2D_OUTFIFO_CNT_L3_CH3_V << DMA2D_OUTFIFO_CNT_L3_CH3_S) +#define DMA2D_OUTFIFO_CNT_L3_CH3_V 0x0000001FU +#define DMA2D_OUTFIFO_CNT_L3_CH3_S 24 + +/** DMA2D_OUT_PUSH_CH3_REG register + * Configures the tx fifo of channel 3 + */ +#define DMA2D_OUT_PUSH_CH3_REG (DR_REG_DMA2D_BASE + 0x318) +/** DMA2D_OUTFIFO_WDATA_CH3 : R/W; bitpos: [9:0]; default: 0; + * This register stores the data that need to be pushed into DMA Tx FIFO. + */ +#define DMA2D_OUTFIFO_WDATA_CH3 0x000003FFU +#define DMA2D_OUTFIFO_WDATA_CH3_M (DMA2D_OUTFIFO_WDATA_CH3_V << DMA2D_OUTFIFO_WDATA_CH3_S) +#define DMA2D_OUTFIFO_WDATA_CH3_V 0x000003FFU +#define DMA2D_OUTFIFO_WDATA_CH3_S 0 +/** DMA2D_OUTFIFO_PUSH_CH3 : R/W/SC; bitpos: [10]; default: 0; + * Set this bit to push data into DMA Tx FIFO. + */ +#define DMA2D_OUTFIFO_PUSH_CH3 (BIT(10)) +#define DMA2D_OUTFIFO_PUSH_CH3_M (DMA2D_OUTFIFO_PUSH_CH3_V << DMA2D_OUTFIFO_PUSH_CH3_S) +#define DMA2D_OUTFIFO_PUSH_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_PUSH_CH3_S 10 + +/** DMA2D_OUT_LINK_CONF_CH3_REG register + * Configures the tx descriptor operations of channel 3 + */ +#define DMA2D_OUT_LINK_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x31c) +/** DMA2D_OUTLINK_STOP_CH3 : R/W/SC; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define DMA2D_OUTLINK_STOP_CH3 (BIT(20)) +#define DMA2D_OUTLINK_STOP_CH3_M (DMA2D_OUTLINK_STOP_CH3_V << DMA2D_OUTLINK_STOP_CH3_S) +#define DMA2D_OUTLINK_STOP_CH3_V 0x00000001U +#define DMA2D_OUTLINK_STOP_CH3_S 20 +/** DMA2D_OUTLINK_START_CH3 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define DMA2D_OUTLINK_START_CH3 (BIT(21)) +#define DMA2D_OUTLINK_START_CH3_M (DMA2D_OUTLINK_START_CH3_V << DMA2D_OUTLINK_START_CH3_S) +#define DMA2D_OUTLINK_START_CH3_V 0x00000001U +#define DMA2D_OUTLINK_START_CH3_S 21 +/** DMA2D_OUTLINK_RESTART_CH3 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define DMA2D_OUTLINK_RESTART_CH3 (BIT(22)) +#define DMA2D_OUTLINK_RESTART_CH3_M (DMA2D_OUTLINK_RESTART_CH3_V << DMA2D_OUTLINK_RESTART_CH3_S) +#define DMA2D_OUTLINK_RESTART_CH3_V 0x00000001U +#define DMA2D_OUTLINK_RESTART_CH3_S 22 +/** DMA2D_OUTLINK_PARK_CH3 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define DMA2D_OUTLINK_PARK_CH3 (BIT(23)) +#define DMA2D_OUTLINK_PARK_CH3_M (DMA2D_OUTLINK_PARK_CH3_V << DMA2D_OUTLINK_PARK_CH3_S) +#define DMA2D_OUTLINK_PARK_CH3_V 0x00000001U +#define DMA2D_OUTLINK_PARK_CH3_S 23 + +/** DMA2D_OUT_LINK_ADDR_CH3_REG register + * Configures the tx descriptor address of channel 3 + */ +#define DMA2D_OUT_LINK_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x320) +/** DMA2D_OUTLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0; + * This register stores the first outlink descriptor's address. + */ +#define DMA2D_OUTLINK_ADDR_CH3 0xFFFFFFFFU +#define DMA2D_OUTLINK_ADDR_CH3_M (DMA2D_OUTLINK_ADDR_CH3_V << DMA2D_OUTLINK_ADDR_CH3_S) +#define DMA2D_OUTLINK_ADDR_CH3_V 0xFFFFFFFFU +#define DMA2D_OUTLINK_ADDR_CH3_S 0 + +/** DMA2D_OUT_STATE_CH3_REG register + * Represents the working status of the tx descriptor of channel 3 + */ +#define DMA2D_OUT_STATE_CH3_REG (DR_REG_DMA2D_BASE + 0x324) +/** DMA2D_OUTLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define DMA2D_OUTLINK_DSCR_ADDR_CH3 0x0003FFFFU +#define DMA2D_OUTLINK_DSCR_ADDR_CH3_M (DMA2D_OUTLINK_DSCR_ADDR_CH3_V << DMA2D_OUTLINK_DSCR_ADDR_CH3_S) +#define DMA2D_OUTLINK_DSCR_ADDR_CH3_V 0x0003FFFFU +#define DMA2D_OUTLINK_DSCR_ADDR_CH3_S 0 +/** DMA2D_OUT_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0; + * This register stores the current descriptor state machine state. + */ +#define DMA2D_OUT_DSCR_STATE_CH3 0x00000003U +#define DMA2D_OUT_DSCR_STATE_CH3_M (DMA2D_OUT_DSCR_STATE_CH3_V << DMA2D_OUT_DSCR_STATE_CH3_S) +#define DMA2D_OUT_DSCR_STATE_CH3_V 0x00000003U +#define DMA2D_OUT_DSCR_STATE_CH3_S 18 +/** DMA2D_OUT_STATE_CH3 : RO; bitpos: [23:20]; default: 0; + * This register stores the current control module state machine state. + */ +#define DMA2D_OUT_STATE_CH3 0x0000000FU +#define DMA2D_OUT_STATE_CH3_M (DMA2D_OUT_STATE_CH3_V << DMA2D_OUT_STATE_CH3_S) +#define DMA2D_OUT_STATE_CH3_V 0x0000000FU +#define DMA2D_OUT_STATE_CH3_S 20 +/** DMA2D_OUT_RESET_AVAIL_CH3 : RO; bitpos: [24]; default: 1; + * This register indicate that if the channel reset is safety. + */ +#define DMA2D_OUT_RESET_AVAIL_CH3 (BIT(24)) +#define DMA2D_OUT_RESET_AVAIL_CH3_M (DMA2D_OUT_RESET_AVAIL_CH3_V << DMA2D_OUT_RESET_AVAIL_CH3_S) +#define DMA2D_OUT_RESET_AVAIL_CH3_V 0x00000001U +#define DMA2D_OUT_RESET_AVAIL_CH3_S 24 + +/** DMA2D_OUT_EOF_DES_ADDR_CH3_REG register + * Represents the address associated with the outlink descriptor of channel 3 + */ +#define DMA2D_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x328) +/** DMA2D_OUT_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define DMA2D_OUT_EOF_DES_ADDR_CH3 0xFFFFFFFFU +#define DMA2D_OUT_EOF_DES_ADDR_CH3_M (DMA2D_OUT_EOF_DES_ADDR_CH3_V << DMA2D_OUT_EOF_DES_ADDR_CH3_S) +#define DMA2D_OUT_EOF_DES_ADDR_CH3_V 0xFFFFFFFFU +#define DMA2D_OUT_EOF_DES_ADDR_CH3_S 0 + +/** DMA2D_OUT_DSCR_CH3_REG register + * Represents the address associated with the outlink descriptor of channel 3 + */ +#define DMA2D_OUT_DSCR_CH3_REG (DR_REG_DMA2D_BASE + 0x32c) +/** DMA2D_OUTLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0; + * The address of the next outlink descriptor address y. + */ +#define DMA2D_OUTLINK_DSCR_CH3 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_CH3_M (DMA2D_OUTLINK_DSCR_CH3_V << DMA2D_OUTLINK_DSCR_CH3_S) +#define DMA2D_OUTLINK_DSCR_CH3_V 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_CH3_S 0 + +/** DMA2D_OUT_DSCR_BF0_CH3_REG register + * Represents the address associated with the outlink descriptor of channel 3 + */ +#define DMA2D_OUT_DSCR_BF0_CH3_REG (DR_REG_DMA2D_BASE + 0x330) +/** DMA2D_OUTLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor's next address y-1. + */ +#define DMA2D_OUTLINK_DSCR_BF0_CH3 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_BF0_CH3_M (DMA2D_OUTLINK_DSCR_BF0_CH3_V << DMA2D_OUTLINK_DSCR_BF0_CH3_S) +#define DMA2D_OUTLINK_DSCR_BF0_CH3_V 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_BF0_CH3_S 0 + +/** DMA2D_OUT_DSCR_BF1_CH3_REG register + * Represents the address associated with the outlink descriptor of channel 3 + */ +#define DMA2D_OUT_DSCR_BF1_CH3_REG (DR_REG_DMA2D_BASE + 0x334) +/** DMA2D_OUTLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last outlink descriptor's next address y-2. + */ +#define DMA2D_OUTLINK_DSCR_BF1_CH3 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_BF1_CH3_M (DMA2D_OUTLINK_DSCR_BF1_CH3_V << DMA2D_OUTLINK_DSCR_BF1_CH3_S) +#define DMA2D_OUTLINK_DSCR_BF1_CH3_V 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_BF1_CH3_S 0 + +/** DMA2D_OUT_PERI_SEL_CH3_REG register + * Configures the tx peripheral of channel 3 + */ +#define DMA2D_OUT_PERI_SEL_CH3_REG (DR_REG_DMA2D_BASE + 0x338) +/** DMA2D_OUT_PERI_SEL_CH3 : R/W; bitpos: [2:0]; default: 7; + * This register is used to select peripheral for Tx channel 0: jpeg 1: + * display-1 2: display-2 3: display-3 7: no choose + */ +#define DMA2D_OUT_PERI_SEL_CH3 0x00000007U +#define DMA2D_OUT_PERI_SEL_CH3_M (DMA2D_OUT_PERI_SEL_CH3_V << DMA2D_OUT_PERI_SEL_CH3_S) +#define DMA2D_OUT_PERI_SEL_CH3_V 0x00000007U +#define DMA2D_OUT_PERI_SEL_CH3_S 0 + +/** DMA2D_OUT_ARB_CH3_REG register + * Configures the tx arbiter of channel 3 + */ +#define DMA2D_OUT_ARB_CH3_REG (DR_REG_DMA2D_BASE + 0x33c) +/** DMA2D_OUT_ARB_TOKEN_NUM_CH3 : R/W; bitpos: [3:0]; default: 1; + * Set the max number of token count of arbiter + */ +#define DMA2D_OUT_ARB_TOKEN_NUM_CH3 0x0000000FU +#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_M (DMA2D_OUT_ARB_TOKEN_NUM_CH3_V << DMA2D_OUT_ARB_TOKEN_NUM_CH3_S) +#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_V 0x0000000FU +#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_S 0 +/** DMA2D_OUT_ARB_PRIORITY_CH3 : R/W; bitpos: [7:4]; default: 1; + * Set the priority of channel + */ +#define DMA2D_OUT_ARB_PRIORITY_CH3 0x0000000FU +#define DMA2D_OUT_ARB_PRIORITY_CH3_M (DMA2D_OUT_ARB_PRIORITY_CH3_V << DMA2D_OUT_ARB_PRIORITY_CH3_S) +#define DMA2D_OUT_ARB_PRIORITY_CH3_V 0x0000000FU +#define DMA2D_OUT_ARB_PRIORITY_CH3_S 4 + +/** DMA2D_OUT_RO_STATUS_CH3_REG register + * Represents the status of the tx reorder module of channel 3 + */ +#define DMA2D_OUT_RO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x340) +/** DMA2D_OUTFIFO_RO_CNT_CH3 : RO; bitpos: [5:0]; default: 0; + * The register stores the byte number of the data in color convert Tx FIFO for + * channel 0. + */ +#define DMA2D_OUTFIFO_RO_CNT_CH3 0x0000003FU +#define DMA2D_OUTFIFO_RO_CNT_CH3_M (DMA2D_OUTFIFO_RO_CNT_CH3_V << DMA2D_OUTFIFO_RO_CNT_CH3_S) +#define DMA2D_OUTFIFO_RO_CNT_CH3_V 0x0000003FU +#define DMA2D_OUTFIFO_RO_CNT_CH3_S 0 +/** DMA2D_OUT_RO_WR_STATE_CH3 : RO; bitpos: [7:6]; default: 0; + * The register stores the state of read ram of reorder + */ +#define DMA2D_OUT_RO_WR_STATE_CH3 0x00000003U +#define DMA2D_OUT_RO_WR_STATE_CH3_M (DMA2D_OUT_RO_WR_STATE_CH3_V << DMA2D_OUT_RO_WR_STATE_CH3_S) +#define DMA2D_OUT_RO_WR_STATE_CH3_V 0x00000003U +#define DMA2D_OUT_RO_WR_STATE_CH3_S 6 +/** DMA2D_OUT_RO_RD_STATE_CH3 : RO; bitpos: [9:8]; default: 0; + * The register stores the state of write ram of reorder + */ +#define DMA2D_OUT_RO_RD_STATE_CH3 0x00000003U +#define DMA2D_OUT_RO_RD_STATE_CH3_M (DMA2D_OUT_RO_RD_STATE_CH3_V << DMA2D_OUT_RO_RD_STATE_CH3_S) +#define DMA2D_OUT_RO_RD_STATE_CH3_V 0x00000003U +#define DMA2D_OUT_RO_RD_STATE_CH3_S 8 +/** DMA2D_OUT_PIXEL_BYTE_CH3 : RO; bitpos: [13:10]; default: 0; + * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes + * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes + */ +#define DMA2D_OUT_PIXEL_BYTE_CH3 0x0000000FU +#define DMA2D_OUT_PIXEL_BYTE_CH3_M (DMA2D_OUT_PIXEL_BYTE_CH3_V << DMA2D_OUT_PIXEL_BYTE_CH3_S) +#define DMA2D_OUT_PIXEL_BYTE_CH3_V 0x0000000FU +#define DMA2D_OUT_PIXEL_BYTE_CH3_S 10 +/** DMA2D_OUT_BURST_BLOCK_NUM_CH3 : RO; bitpos: [17:14]; default: 0; + * the number of macro blocks contained in a burst of data at TX channel + */ +#define DMA2D_OUT_BURST_BLOCK_NUM_CH3 0x0000000FU +#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_M (DMA2D_OUT_BURST_BLOCK_NUM_CH3_V << DMA2D_OUT_BURST_BLOCK_NUM_CH3_S) +#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_V 0x0000000FU +#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_S 14 + +/** DMA2D_OUT_COLOR_CONVERT_CH3_REG register + * Configures the tx color convert of channel 3 + */ +#define DMA2D_OUT_COLOR_CONVERT_CH3_REG (DR_REG_DMA2D_BASE + 0x348) +/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; + * Set final color convert process and output type 0: RGB888 to RGB565 1: + * YUV444 to YUV422 2: output directly + */ +#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 0x00000003U +#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S) +#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V 0x00000003U +#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S 0 +/** DMA2D_OUT_COLOR_3B_PROC_EN_CH3 : R/W; bitpos: [2]; default: 0; + * Enable generic color convert module between color input & color output, need to + * configure parameter. + */ +#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3 (BIT(2)) +#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S) +#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V 0x00000001U +#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S 2 +/** DMA2D_OUT_COLOR_INPUT_SEL_CH3 : R/W; bitpos: [5:3]; default: 7; + * Set first color convert process and input color type 0: RGB565 to RGB888 1: + * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: + * disable color space convert + */ +#define DMA2D_OUT_COLOR_INPUT_SEL_CH3 0x00000007U +#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_M (DMA2D_OUT_COLOR_INPUT_SEL_CH3_V << DMA2D_OUT_COLOR_INPUT_SEL_CH3_S) +#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_V 0x00000007U +#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_S 3 + +/** DMA2D_OUT_SCRAMBLE_CH3_REG register + * Configures the tx scramble of channel 3 + */ +#define DMA2D_OUT_SCRAMBLE_CH3_REG (DR_REG_DMA2D_BASE + 0x34c) +/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 : R/W; bitpos: [2:0]; default: 0; + * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : + * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 + */ +#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 0x00000007U +#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S) +#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V 0x00000007U +#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM0_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM0_CH3_REG (DR_REG_DMA2D_BASE + 0x350) +/** DMA2D_OUT_COLOR_PARAM_H0_CH3 : R/W; bitpos: [20:0]; default: 298; + * Set first 2 parameter of most significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_H0_CH3 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_H0_CH3_M (DMA2D_OUT_COLOR_PARAM_H0_CH3_V << DMA2D_OUT_COLOR_PARAM_H0_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_H0_CH3_V 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_H0_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM1_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM1_CH3_REG (DR_REG_DMA2D_BASE + 0x354) +/** DMA2D_OUT_COLOR_PARAM_H1_CH3 : R/W; bitpos: [27:0]; default: 210164121; + * Set last 2 parameter of most significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_H1_CH3 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_H1_CH3_M (DMA2D_OUT_COLOR_PARAM_H1_CH3_V << DMA2D_OUT_COLOR_PARAM_H1_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_H1_CH3_V 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_H1_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM2_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM2_CH3_REG (DR_REG_DMA2D_BASE + 0x358) +/** DMA2D_OUT_COLOR_PARAM_M0_CH3 : R/W; bitpos: [20:0]; default: 1995050; + * Set first 2 parameter of midium significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_M0_CH3 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_M0_CH3_M (DMA2D_OUT_COLOR_PARAM_M0_CH3_V << DMA2D_OUT_COLOR_PARAM_M0_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_M0_CH3_V 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_M0_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM3_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM3_CH3_REG (DR_REG_DMA2D_BASE + 0x35c) +/** DMA2D_OUT_COLOR_PARAM_M1_CH3 : R/W; bitpos: [27:0]; default: 35540784; + * Set last 2 parameter of midium significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_M1_CH3 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_M1_CH3_M (DMA2D_OUT_COLOR_PARAM_M1_CH3_V << DMA2D_OUT_COLOR_PARAM_M1_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_M1_CH3_V 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_M1_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM4_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM4_CH3_REG (DR_REG_DMA2D_BASE + 0x360) +/** DMA2D_OUT_COLOR_PARAM_L0_CH3 : R/W; bitpos: [20:0]; default: 528682; + * Set first 2 parameter of least significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_L0_CH3 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_L0_CH3_M (DMA2D_OUT_COLOR_PARAM_L0_CH3_V << DMA2D_OUT_COLOR_PARAM_L0_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_L0_CH3_V 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_L0_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM5_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM5_CH3_REG (DR_REG_DMA2D_BASE + 0x364) +/** DMA2D_OUT_COLOR_PARAM_L1_CH3 : R/W; bitpos: [27:0]; default: 195899392; + * Set last 2 parameter of least significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_L1_CH3 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_L1_CH3_M (DMA2D_OUT_COLOR_PARAM_L1_CH3_V << DMA2D_OUT_COLOR_PARAM_L1_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_L1_CH3_V 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_L1_CH3_S 0 + +/** DMA2D_OUT_ETM_CONF_CH3_REG register + * Configures the tx etm of channel 3 + */ +#define DMA2D_OUT_ETM_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x368) +/** DMA2D_OUT_ETM_EN_CH3 : R/W; bitpos: [0]; default: 0; + * Configures the enable of the etm function, 1 is enable. + */ +#define DMA2D_OUT_ETM_EN_CH3 (BIT(0)) +#define DMA2D_OUT_ETM_EN_CH3_M (DMA2D_OUT_ETM_EN_CH3_V << DMA2D_OUT_ETM_EN_CH3_S) +#define DMA2D_OUT_ETM_EN_CH3_V 0x00000001U +#define DMA2D_OUT_ETM_EN_CH3_S 0 +/** DMA2D_OUT_ETM_LOOP_EN_CH3 : R/W; bitpos: [1]; default: 0; + * Configures the enable of the descriptors loop etm function, 1 is enable. + */ +#define DMA2D_OUT_ETM_LOOP_EN_CH3 (BIT(1)) +#define DMA2D_OUT_ETM_LOOP_EN_CH3_M (DMA2D_OUT_ETM_LOOP_EN_CH3_V << DMA2D_OUT_ETM_LOOP_EN_CH3_S) +#define DMA2D_OUT_ETM_LOOP_EN_CH3_V 0x00000001U +#define DMA2D_OUT_ETM_LOOP_EN_CH3_S 1 +/** DMA2D_OUT_DSCR_TASK_MAK_CH3 : R/W; bitpos: [3:2]; default: 1; + * Configures the maximum number of cacheable descriptors. + */ +#define DMA2D_OUT_DSCR_TASK_MAK_CH3 0x00000003U +#define DMA2D_OUT_DSCR_TASK_MAK_CH3_M (DMA2D_OUT_DSCR_TASK_MAK_CH3_V << DMA2D_OUT_DSCR_TASK_MAK_CH3_S) +#define DMA2D_OUT_DSCR_TASK_MAK_CH3_V 0x00000003U +#define DMA2D_OUT_DSCR_TASK_MAK_CH3_S 2 + +/** DMA2D_OUT_DSCR_PORT_BLK_CH3_REG register + * Configures the tx block size in dscr port mode + */ +#define DMA2D_OUT_DSCR_PORT_BLK_CH3_REG (DR_REG_DMA2D_BASE + 0x36c) +/** DMA2D_OUT_DSCR_PORT_BLK_H_CH3 : R/W; bitpos: [13:0]; default: 18; + * Set the horizontal width of tx block size in dscr port mode + */ +#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3 0x00003FFFU +#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S) +#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V 0x00003FFFU +#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S 0 +/** DMA2D_OUT_DSCR_PORT_BLK_V_CH3 : R/W; bitpos: [27:14]; default: 18; + * Set the vertical height of tx block size in dscr port mode + */ +#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3 0x00003FFFU +#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S) +#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V 0x00003FFFU +#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S 14 + /** DMA2D_IN_CONF0_CH0_REG register * Configures the rx direction of channel 0 */ @@ -3668,42 +4674,42 @@ extern "C" { #define DMA2D_IN_REMAIN_UNDER_8B_CH0_V 0x00000001U #define DMA2D_IN_REMAIN_UNDER_8B_CH0_S 14 /** DMA2D_INFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Rx FIFO full signal for Rx channel 0. */ #define DMA2D_INFIFO_FULL_L1_CH0 (BIT(15)) #define DMA2D_INFIFO_FULL_L1_CH0_M (DMA2D_INFIFO_FULL_L1_CH0_V << DMA2D_INFIFO_FULL_L1_CH0_S) #define DMA2D_INFIFO_FULL_L1_CH0_V 0x00000001U #define DMA2D_INFIFO_FULL_L1_CH0_S 15 /** DMA2D_INFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Rx FIFO empty signal for Rx channel 0. */ #define DMA2D_INFIFO_EMPTY_L1_CH0 (BIT(16)) #define DMA2D_INFIFO_EMPTY_L1_CH0_M (DMA2D_INFIFO_EMPTY_L1_CH0_V << DMA2D_INFIFO_EMPTY_L1_CH0_S) #define DMA2D_INFIFO_EMPTY_L1_CH0_V 0x00000001U #define DMA2D_INFIFO_EMPTY_L1_CH0_S 16 /** DMA2D_INFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. */ #define DMA2D_INFIFO_CNT_L1_CH0 0x0000001FU #define DMA2D_INFIFO_CNT_L1_CH0_M (DMA2D_INFIFO_CNT_L1_CH0_V << DMA2D_INFIFO_CNT_L1_CH0_S) #define DMA2D_INFIFO_CNT_L1_CH0_V 0x0000001FU #define DMA2D_INFIFO_CNT_L1_CH0_S 17 /** DMA2D_INFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Rx FIFO full signal for Rx channel 0. */ #define DMA2D_INFIFO_FULL_L3_CH0 (BIT(22)) #define DMA2D_INFIFO_FULL_L3_CH0_M (DMA2D_INFIFO_FULL_L3_CH0_V << DMA2D_INFIFO_FULL_L3_CH0_S) #define DMA2D_INFIFO_FULL_L3_CH0_V 0x00000001U #define DMA2D_INFIFO_FULL_L3_CH0_S 22 /** DMA2D_INFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Rx FIFO empty signal for Rx channel 0. */ #define DMA2D_INFIFO_EMPTY_L3_CH0 (BIT(23)) #define DMA2D_INFIFO_EMPTY_L3_CH0_M (DMA2D_INFIFO_EMPTY_L3_CH0_V << DMA2D_INFIFO_EMPTY_L3_CH0_S) #define DMA2D_INFIFO_EMPTY_L3_CH0_V 0x00000001U #define DMA2D_INFIFO_EMPTY_L3_CH0_S 23 /** DMA2D_INFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. */ #define DMA2D_INFIFO_CNT_L3_CH0 0x0000001FU #define DMA2D_INFIFO_CNT_L3_CH0_M (DMA2D_INFIFO_CNT_L3_CH0_V << DMA2D_INFIFO_CNT_L3_CH0_S) @@ -3902,12 +4908,12 @@ extern "C" { #define DMA2D_IN_ARB_TOKEN_NUM_CH0_M (DMA2D_IN_ARB_TOKEN_NUM_CH0_V << DMA2D_IN_ARB_TOKEN_NUM_CH0_S) #define DMA2D_IN_ARB_TOKEN_NUM_CH0_V 0x0000000FU #define DMA2D_IN_ARB_TOKEN_NUM_CH0_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [4]; default: 1; +/** DMA2D_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_IN_ARB_PRIORITY_CH0 (BIT(4)) +#define DMA2D_IN_ARB_PRIORITY_CH0 0x0000000FU #define DMA2D_IN_ARB_PRIORITY_CH0_M (DMA2D_IN_ARB_PRIORITY_CH0_V << DMA2D_IN_ARB_PRIORITY_CH0_S) -#define DMA2D_IN_ARB_PRIORITY_CH0_V 0x00000001U +#define DMA2D_IN_ARB_PRIORITY_CH0_V 0x0000000FU #define DMA2D_IN_ARB_PRIORITY_CH0_S 4 /** DMA2D_IN_RO_STATUS_CH0_REG register @@ -3980,12 +4986,12 @@ extern "C" { #define DMA2D_IN_RO_RAM_CLK_FO_CH0_S 6 /** DMA2D_IN_COLOR_CONVERT_CH0_REG register - * Configures the tx color convert of channel 0 + * Configures the Rx color convert of channel 0 */ #define DMA2D_IN_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x54c) /** DMA2D_IN_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly + * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 */ #define DMA2D_IN_COLOR_OUTPUT_SEL_CH0 0x00000003U #define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_M (DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S) @@ -4128,7 +5134,7 @@ extern "C" { #define DMA2D_IN_DSCR_TASK_MAK_CH0_S 2 /** DMA2D_IN_CONF0_CH1_REG register - * Configures the rx direction of channel 0 + * Configures the rx direction of channel 1 */ #define DMA2D_IN_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x600) /** DMA2D_IN_MEM_TRANS_EN_CH1 : R/W; bitpos: [0]; default: 0; @@ -4232,7 +5238,7 @@ extern "C" { #define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S 26 /** DMA2D_IN_INT_RAW_CH1_REG register - * Raw interrupt status of RX channel 0 + * Raw interrupt status of RX channel 1 */ #define DMA2D_IN_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x604) /** DMA2D_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -4341,7 +5347,7 @@ extern "C" { #define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S 13 /** DMA2D_IN_INT_ENA_CH1_REG register - * Interrupt enable bits of RX channel 0 + * Interrupt enable bits of RX channel 1 */ #define DMA2D_IN_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x608) /** DMA2D_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -4444,7 +5450,7 @@ extern "C" { #define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S 13 /** DMA2D_IN_INT_ST_CH1_REG register - * Masked interrupt status of RX channel 0 + * Masked interrupt status of RX channel 1 */ #define DMA2D_IN_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x60c) /** DMA2D_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; @@ -4547,7 +5553,7 @@ extern "C" { #define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S 13 /** DMA2D_IN_INT_CLR_CH1_REG register - * Interrupt clear bits of RX channel 0 + * Interrupt clear bits of RX channel 1 */ #define DMA2D_IN_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x610) /** DMA2D_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; @@ -4650,7 +5656,7 @@ extern "C" { #define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S 13 /** DMA2D_INFIFO_STATUS_CH1_REG register - * Represents the status of the rx fifo of channel 0 + * Represents the status of the rx fifo of channel 1 */ #define DMA2D_INFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x614) /** DMA2D_INFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0; @@ -4731,42 +5737,42 @@ extern "C" { #define DMA2D_IN_REMAIN_UNDER_8B_CH1_V 0x00000001U #define DMA2D_IN_REMAIN_UNDER_8B_CH1_S 14 /** DMA2D_INFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Rx FIFO full signal for Rx channel 0. */ #define DMA2D_INFIFO_FULL_L1_CH1 (BIT(15)) #define DMA2D_INFIFO_FULL_L1_CH1_M (DMA2D_INFIFO_FULL_L1_CH1_V << DMA2D_INFIFO_FULL_L1_CH1_S) #define DMA2D_INFIFO_FULL_L1_CH1_V 0x00000001U #define DMA2D_INFIFO_FULL_L1_CH1_S 15 /** DMA2D_INFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Rx FIFO empty signal for Rx channel 0. */ #define DMA2D_INFIFO_EMPTY_L1_CH1 (BIT(16)) #define DMA2D_INFIFO_EMPTY_L1_CH1_M (DMA2D_INFIFO_EMPTY_L1_CH1_V << DMA2D_INFIFO_EMPTY_L1_CH1_S) #define DMA2D_INFIFO_EMPTY_L1_CH1_V 0x00000001U #define DMA2D_INFIFO_EMPTY_L1_CH1_S 16 /** DMA2D_INFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. */ #define DMA2D_INFIFO_CNT_L1_CH1 0x0000001FU #define DMA2D_INFIFO_CNT_L1_CH1_M (DMA2D_INFIFO_CNT_L1_CH1_V << DMA2D_INFIFO_CNT_L1_CH1_S) #define DMA2D_INFIFO_CNT_L1_CH1_V 0x0000001FU #define DMA2D_INFIFO_CNT_L1_CH1_S 17 /** DMA2D_INFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Rx FIFO full signal for Rx channel 0. */ #define DMA2D_INFIFO_FULL_L3_CH1 (BIT(22)) #define DMA2D_INFIFO_FULL_L3_CH1_M (DMA2D_INFIFO_FULL_L3_CH1_V << DMA2D_INFIFO_FULL_L3_CH1_S) #define DMA2D_INFIFO_FULL_L3_CH1_V 0x00000001U #define DMA2D_INFIFO_FULL_L3_CH1_S 22 /** DMA2D_INFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Rx FIFO empty signal for Rx channel 0. */ #define DMA2D_INFIFO_EMPTY_L3_CH1 (BIT(23)) #define DMA2D_INFIFO_EMPTY_L3_CH1_M (DMA2D_INFIFO_EMPTY_L3_CH1_V << DMA2D_INFIFO_EMPTY_L3_CH1_S) #define DMA2D_INFIFO_EMPTY_L3_CH1_V 0x00000001U #define DMA2D_INFIFO_EMPTY_L3_CH1_S 23 /** DMA2D_INFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. */ #define DMA2D_INFIFO_CNT_L3_CH1 0x0000001FU #define DMA2D_INFIFO_CNT_L3_CH1_M (DMA2D_INFIFO_CNT_L3_CH1_V << DMA2D_INFIFO_CNT_L3_CH1_S) @@ -4774,7 +5780,7 @@ extern "C" { #define DMA2D_INFIFO_CNT_L3_CH1_S 24 /** DMA2D_IN_POP_CH1_REG register - * Configures the rx fifo of channel 0 + * Configures the rx fifo of channel 1 */ #define DMA2D_IN_POP_CH1_REG (DR_REG_DMA2D_BASE + 0x618) /** DMA2D_INFIFO_RDATA_CH1 : RO; bitpos: [10:0]; default: 1024; @@ -4793,7 +5799,7 @@ extern "C" { #define DMA2D_INFIFO_POP_CH1_S 11 /** DMA2D_IN_LINK_CONF_CH1_REG register - * Configures the rx descriptor operations of channel 0 + * Configures the rx descriptor operations of channel 1 */ #define DMA2D_IN_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x61c) /** DMA2D_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; @@ -4835,7 +5841,7 @@ extern "C" { #define DMA2D_INLINK_PARK_CH1_S 24 /** DMA2D_IN_LINK_ADDR_CH1_REG register - * Configures the rx descriptor address of channel 0 + * Configures the rx descriptor address of channel 1 */ #define DMA2D_IN_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x620) /** DMA2D_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; @@ -4847,7 +5853,7 @@ extern "C" { #define DMA2D_INLINK_ADDR_CH1_S 0 /** DMA2D_IN_STATE_CH1_REG register - * Represents the working status of the rx descriptor of channel 0 + * Represents the working status of the rx descriptor of channel 1 */ #define DMA2D_IN_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x624) /** DMA2D_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; @@ -4880,7 +5886,7 @@ extern "C" { #define DMA2D_IN_RESET_AVAIL_CH1_S 23 /** DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel 1 */ #define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x628) /** DMA2D_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -4893,7 +5899,7 @@ extern "C" { #define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S 0 /** DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel 1 */ #define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x62c) /** DMA2D_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -4906,7 +5912,7 @@ extern "C" { #define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S 0 /** DMA2D_IN_DSCR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel 1 */ #define DMA2D_IN_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x630) /** DMA2D_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -4918,7 +5924,7 @@ extern "C" { #define DMA2D_INLINK_DSCR_CH1_S 0 /** DMA2D_IN_DSCR_BF0_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel 1 */ #define DMA2D_IN_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x634) /** DMA2D_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; @@ -4930,7 +5936,7 @@ extern "C" { #define DMA2D_INLINK_DSCR_BF0_CH1_S 0 /** DMA2D_IN_DSCR_BF1_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel 1 */ #define DMA2D_IN_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x638) /** DMA2D_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; @@ -4942,7 +5948,7 @@ extern "C" { #define DMA2D_INLINK_DSCR_BF1_CH1_S 0 /** DMA2D_IN_PERI_SEL_CH1_REG register - * Configures the rx peripheral of channel 0 + * Configures the rx peripheral of channel 1 */ #define DMA2D_IN_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x63c) /** DMA2D_IN_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7; @@ -4955,7 +5961,7 @@ extern "C" { #define DMA2D_IN_PERI_SEL_CH1_S 0 /** DMA2D_IN_ARB_CH1_REG register - * Configures the rx arbiter of channel 0 + * Configures the rx arbiter of channel 1 */ #define DMA2D_IN_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x640) /** DMA2D_IN_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1; @@ -4965,16 +5971,16 @@ extern "C" { #define DMA2D_IN_ARB_TOKEN_NUM_CH1_M (DMA2D_IN_ARB_TOKEN_NUM_CH1_V << DMA2D_IN_ARB_TOKEN_NUM_CH1_S) #define DMA2D_IN_ARB_TOKEN_NUM_CH1_V 0x0000000FU #define DMA2D_IN_ARB_TOKEN_NUM_CH1_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [4]; default: 1; +/** DMA2D_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_IN_ARB_PRIORITY_CH1 (BIT(4)) +#define DMA2D_IN_ARB_PRIORITY_CH1 0x0000000FU #define DMA2D_IN_ARB_PRIORITY_CH1_M (DMA2D_IN_ARB_PRIORITY_CH1_V << DMA2D_IN_ARB_PRIORITY_CH1_S) -#define DMA2D_IN_ARB_PRIORITY_CH1_V 0x00000001U +#define DMA2D_IN_ARB_PRIORITY_CH1_V 0x0000000FU #define DMA2D_IN_ARB_PRIORITY_CH1_S 4 /** DMA2D_IN_RO_STATUS_CH1_REG register - * Represents the status of the rx reorder module of channel 0 + * Represents the status of the rx reorder module of channel 1 */ #define DMA2D_IN_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x644) /** DMA2D_INFIFO_RO_CNT_CH1 : RO; bitpos: [4:0]; default: 0; @@ -5016,9 +6022,9 @@ extern "C" { #define DMA2D_IN_BURST_BLOCK_NUM_CH1_S 13 /** DMA2D_IN_ETM_CONF_CH1_REG register - * Configures the rx etm of channel 0 + * Configures the rx etm of channel 1 */ -#define DMA2D_IN_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x648) +#define DMA2D_IN_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x66c) /** DMA2D_IN_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0; * Configures the enable of the etm function, 1 is enable. */ @@ -5041,6 +6047,920 @@ extern "C" { #define DMA2D_IN_DSCR_TASK_MAK_CH1_V 0x00000003U #define DMA2D_IN_DSCR_TASK_MAK_CH1_S 2 +/** DMA2D_IN_CONF0_CH2_REG register + * Configures the rx direction of channel 2 + */ +#define DMA2D_IN_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x700) +/** DMA2D_IN_MEM_TRANS_EN_CH2 : R/W; bitpos: [0]; default: 0; + * enable memory trans of the same channel + */ +#define DMA2D_IN_MEM_TRANS_EN_CH2 (BIT(0)) +#define DMA2D_IN_MEM_TRANS_EN_CH2_M (DMA2D_IN_MEM_TRANS_EN_CH2_V << DMA2D_IN_MEM_TRANS_EN_CH2_S) +#define DMA2D_IN_MEM_TRANS_EN_CH2_V 0x00000001U +#define DMA2D_IN_MEM_TRANS_EN_CH2_S 0 +/** DMA2D_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor + * when accessing SRAM. + */ +#define DMA2D_INDSCR_BURST_EN_CH2 (BIT(2)) +#define DMA2D_INDSCR_BURST_EN_CH2_M (DMA2D_INDSCR_BURST_EN_CH2_V << DMA2D_INDSCR_BURST_EN_CH2_S) +#define DMA2D_INDSCR_BURST_EN_CH2_V 0x00000001U +#define DMA2D_INDSCR_BURST_EN_CH2_S 2 +/** DMA2D_IN_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0; + * When access address space is ecc/aes area, this bit should be set to 1. In this + * case, the start address of square should be 16-bit aligned. The width of square + * multiply byte number of one pixel should be 16-bit aligned. + */ +#define DMA2D_IN_ECC_AES_EN_CH2 (BIT(3)) +#define DMA2D_IN_ECC_AES_EN_CH2_M (DMA2D_IN_ECC_AES_EN_CH2_V << DMA2D_IN_ECC_AES_EN_CH2_S) +#define DMA2D_IN_ECC_AES_EN_CH2_V 0x00000001U +#define DMA2D_IN_ECC_AES_EN_CH2_S 3 +/** DMA2D_IN_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define DMA2D_IN_CHECK_OWNER_CH2 (BIT(4)) +#define DMA2D_IN_CHECK_OWNER_CH2_M (DMA2D_IN_CHECK_OWNER_CH2_V << DMA2D_IN_CHECK_OWNER_CH2_S) +#define DMA2D_IN_CHECK_OWNER_CH2_V 0x00000001U +#define DMA2D_IN_CHECK_OWNER_CH2_S 4 +/** DMA2D_IN_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0; + * reserved + */ +#define DMA2D_IN_LOOP_TEST_CH2 (BIT(5)) +#define DMA2D_IN_LOOP_TEST_CH2_M (DMA2D_IN_LOOP_TEST_CH2_V << DMA2D_IN_LOOP_TEST_CH2_S) +#define DMA2D_IN_LOOP_TEST_CH2_V 0x00000001U +#define DMA2D_IN_LOOP_TEST_CH2_S 5 +/** DMA2D_IN_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0; + * Block size of Rx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 + * bytes 4: 128 bytes + */ +#define DMA2D_IN_MEM_BURST_LENGTH_CH2 0x00000007U +#define DMA2D_IN_MEM_BURST_LENGTH_CH2_M (DMA2D_IN_MEM_BURST_LENGTH_CH2_V << DMA2D_IN_MEM_BURST_LENGTH_CH2_S) +#define DMA2D_IN_MEM_BURST_LENGTH_CH2_V 0x00000007U +#define DMA2D_IN_MEM_BURST_LENGTH_CH2_S 6 +/** DMA2D_IN_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0; + * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: + * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link + * descriptor + */ +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2 0x00000003U +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S) +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V 0x00000003U +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S 9 +/** DMA2D_IN_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0; + * Set this bit to 1 to obtain descriptor from IP port + */ +#define DMA2D_IN_DSCR_PORT_EN_CH2 (BIT(11)) +#define DMA2D_IN_DSCR_PORT_EN_CH2_M (DMA2D_IN_DSCR_PORT_EN_CH2_V << DMA2D_IN_DSCR_PORT_EN_CH2_S) +#define DMA2D_IN_DSCR_PORT_EN_CH2_V 0x00000001U +#define DMA2D_IN_DSCR_PORT_EN_CH2_S 11 +/** DMA2D_IN_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to 1 to make sure AXI write data don't cross the address boundary + * which define by mem_burst_length + */ +#define DMA2D_IN_PAGE_BOUND_EN_CH2 (BIT(12)) +#define DMA2D_IN_PAGE_BOUND_EN_CH2_M (DMA2D_IN_PAGE_BOUND_EN_CH2_V << DMA2D_IN_PAGE_BOUND_EN_CH2_S) +#define DMA2D_IN_PAGE_BOUND_EN_CH2_V 0x00000001U +#define DMA2D_IN_PAGE_BOUND_EN_CH2_S 12 +/** DMA2D_IN_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0; + * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this + * selection + */ +#define DMA2D_IN_REORDER_EN_CH2 (BIT(16)) +#define DMA2D_IN_REORDER_EN_CH2_M (DMA2D_IN_REORDER_EN_CH2_V << DMA2D_IN_REORDER_EN_CH2_S) +#define DMA2D_IN_REORDER_EN_CH2_V 0x00000001U +#define DMA2D_IN_REORDER_EN_CH2_S 16 +/** DMA2D_IN_RST_CH2 : R/W; bitpos: [24]; default: 0; + * Write 1 then write 0 to this bit to reset Rx channel + */ +#define DMA2D_IN_RST_CH2 (BIT(24)) +#define DMA2D_IN_RST_CH2_M (DMA2D_IN_RST_CH2_V << DMA2D_IN_RST_CH2_S) +#define DMA2D_IN_RST_CH2_V 0x00000001U +#define DMA2D_IN_RST_CH2_S 24 +/** DMA2D_IN_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0; + * Write 1 before reset and write 0 after reset + */ +#define DMA2D_IN_CMD_DISABLE_CH2 (BIT(25)) +#define DMA2D_IN_CMD_DISABLE_CH2_M (DMA2D_IN_CMD_DISABLE_CH2_V << DMA2D_IN_CMD_DISABLE_CH2_S) +#define DMA2D_IN_CMD_DISABLE_CH2_V 0x00000001U +#define DMA2D_IN_CMD_DISABLE_CH2_S 25 +/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0; + * Set this bit to 1 to disable arbiter optimum weight function. + */ +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 (BIT(26)) +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S) +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V 0x00000001U +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S 26 + +/** DMA2D_IN_INT_RAW_CH2_REG register + * Raw interrupt status of RX channel 2 + */ +#define DMA2D_IN_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x704) +/** DMA2D_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been transmitted to peripherals for Rx channel 0. + */ +#define DMA2D_IN_DONE_CH2_INT_RAW (BIT(0)) +#define DMA2D_IN_DONE_CH2_INT_RAW_M (DMA2D_IN_DONE_CH2_INT_RAW_V << DMA2D_IN_DONE_CH2_INT_RAW_S) +#define DMA2D_IN_DONE_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_DONE_CH2_INT_RAW_S 0 +/** DMA2D_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received and no data error is detected for Rx channel 0. + */ +#define DMA2D_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_M (DMA2D_IN_SUC_EOF_CH2_INT_RAW_V << DMA2D_IN_SUC_EOF_CH2_INT_RAW_S) +#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_S 1 +/** DMA2D_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received and data error is detected + */ +#define DMA2D_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_M (DMA2D_IN_ERR_EOF_CH2_INT_RAW_V << DMA2D_IN_ERR_EOF_CH2_INT_RAW_S) +#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_S 2 +/** DMA2D_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error, + * including owner error, the second and third word error of inlink descriptor for Rx + * channel 0. + */ +#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S) +#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S 3 +/** DMA2D_INFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + */ +#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S 4 +/** DMA2D_INFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + */ +#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S 5 +/** DMA2D_INFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + */ +#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S 6 +/** DMA2D_INFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + */ +#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S 7 +/** DMA2D_INFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + */ +#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S 8 +/** DMA2D_INFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + */ +#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when the last descriptor is done but fifo + * also remain data. + */ +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S 10 +/** DMA2D_INFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when reorder fifo is overflow. + */ +#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S 11 +/** DMA2D_INFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when reorder fifo is underflow. + */ +#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S 13 + +/** DMA2D_IN_INT_ENA_CH2_REG register + * Interrupt enable bits of RX channel 2 + */ +#define DMA2D_IN_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x708) +/** DMA2D_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define DMA2D_IN_DONE_CH2_INT_ENA (BIT(0)) +#define DMA2D_IN_DONE_CH2_INT_ENA_M (DMA2D_IN_DONE_CH2_INT_ENA_V << DMA2D_IN_DONE_CH2_INT_ENA_S) +#define DMA2D_IN_DONE_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_DONE_CH2_INT_ENA_S 0 +/** DMA2D_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_M (DMA2D_IN_SUC_EOF_CH2_INT_ENA_V << DMA2D_IN_SUC_EOF_CH2_INT_ENA_S) +#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_S 1 +/** DMA2D_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_M (DMA2D_IN_ERR_EOF_CH2_INT_ENA_V << DMA2D_IN_ERR_EOF_CH2_INT_ENA_S) +#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_S 2 +/** DMA2D_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S) +#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S 3 +/** DMA2D_INFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S 4 +/** DMA2D_INFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S 5 +/** DMA2D_INFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S 6 +/** DMA2D_INFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S 7 +/** DMA2D_INFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S 8 +/** DMA2D_INFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S 10 +/** DMA2D_INFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S 11 +/** DMA2D_INFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S 13 + +/** DMA2D_IN_INT_ST_CH2_REG register + * Masked interrupt status of RX channel 2 + */ +#define DMA2D_IN_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x70c) +/** DMA2D_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define DMA2D_IN_DONE_CH2_INT_ST (BIT(0)) +#define DMA2D_IN_DONE_CH2_INT_ST_M (DMA2D_IN_DONE_CH2_INT_ST_V << DMA2D_IN_DONE_CH2_INT_ST_S) +#define DMA2D_IN_DONE_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_DONE_CH2_INT_ST_S 0 +/** DMA2D_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH2_INT_ST_M (DMA2D_IN_SUC_EOF_CH2_INT_ST_V << DMA2D_IN_SUC_EOF_CH2_INT_ST_S) +#define DMA2D_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH2_INT_ST_S 1 +/** DMA2D_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH2_INT_ST_M (DMA2D_IN_ERR_EOF_CH2_INT_ST_V << DMA2D_IN_ERR_EOF_CH2_INT_ST_S) +#define DMA2D_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH2_INT_ST_S 2 +/** DMA2D_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_M (DMA2D_IN_DSCR_ERR_CH2_INT_ST_V << DMA2D_IN_DSCR_ERR_CH2_INT_ST_S) +#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_S 3 +/** DMA2D_INFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S 4 +/** DMA2D_INFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S 5 +/** DMA2D_INFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S 6 +/** DMA2D_INFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S 7 +/** DMA2D_INFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S 8 +/** DMA2D_INFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S 10 +/** DMA2D_INFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S 11 +/** DMA2D_INFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S 13 + +/** DMA2D_IN_INT_CLR_CH2_REG register + * Interrupt clear bits of RX channel 2 + */ +#define DMA2D_IN_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x710) +/** DMA2D_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define DMA2D_IN_DONE_CH2_INT_CLR (BIT(0)) +#define DMA2D_IN_DONE_CH2_INT_CLR_M (DMA2D_IN_DONE_CH2_INT_CLR_V << DMA2D_IN_DONE_CH2_INT_CLR_S) +#define DMA2D_IN_DONE_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_DONE_CH2_INT_CLR_S 0 +/** DMA2D_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_M (DMA2D_IN_SUC_EOF_CH2_INT_CLR_V << DMA2D_IN_SUC_EOF_CH2_INT_CLR_S) +#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_S 1 +/** DMA2D_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_M (DMA2D_IN_ERR_EOF_CH2_INT_CLR_V << DMA2D_IN_ERR_EOF_CH2_INT_CLR_S) +#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_S 2 +/** DMA2D_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S) +#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S 3 +/** DMA2D_INFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S 4 +/** DMA2D_INFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S 5 +/** DMA2D_INFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S 6 +/** DMA2D_INFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S 7 +/** DMA2D_INFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S 8 +/** DMA2D_INFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S 10 +/** DMA2D_INFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S 11 +/** DMA2D_INFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S 13 + +/** DMA2D_INFIFO_STATUS_CH2_REG register + * Represents the status of the rx fifo of channel 2 + */ +#define DMA2D_INFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x714) +/** DMA2D_INFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0; + * Rx FIFO full signal for Rx channel. + */ +#define DMA2D_INFIFO_FULL_L2_CH2 (BIT(0)) +#define DMA2D_INFIFO_FULL_L2_CH2_M (DMA2D_INFIFO_FULL_L2_CH2_V << DMA2D_INFIFO_FULL_L2_CH2_S) +#define DMA2D_INFIFO_FULL_L2_CH2_V 0x00000001U +#define DMA2D_INFIFO_FULL_L2_CH2_S 0 +/** DMA2D_INFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1; + * Rx FIFO empty signal for Rx channel. + */ +#define DMA2D_INFIFO_EMPTY_L2_CH2 (BIT(1)) +#define DMA2D_INFIFO_EMPTY_L2_CH2_M (DMA2D_INFIFO_EMPTY_L2_CH2_V << DMA2D_INFIFO_EMPTY_L2_CH2_S) +#define DMA2D_INFIFO_EMPTY_L2_CH2_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L2_CH2_S 1 +/** DMA2D_INFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel. + */ +#define DMA2D_INFIFO_CNT_L2_CH2 0x0000000FU +#define DMA2D_INFIFO_CNT_L2_CH2_M (DMA2D_INFIFO_CNT_L2_CH2_V << DMA2D_INFIFO_CNT_L2_CH2_S) +#define DMA2D_INFIFO_CNT_L2_CH2_V 0x0000000FU +#define DMA2D_INFIFO_CNT_L2_CH2_S 2 +/** DMA2D_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_1B_CH2 (BIT(7)) +#define DMA2D_IN_REMAIN_UNDER_1B_CH2_M (DMA2D_IN_REMAIN_UNDER_1B_CH2_V << DMA2D_IN_REMAIN_UNDER_1B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_1B_CH2_S 7 +/** DMA2D_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_2B_CH2 (BIT(8)) +#define DMA2D_IN_REMAIN_UNDER_2B_CH2_M (DMA2D_IN_REMAIN_UNDER_2B_CH2_V << DMA2D_IN_REMAIN_UNDER_2B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_2B_CH2_S 8 +/** DMA2D_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_3B_CH2 (BIT(9)) +#define DMA2D_IN_REMAIN_UNDER_3B_CH2_M (DMA2D_IN_REMAIN_UNDER_3B_CH2_V << DMA2D_IN_REMAIN_UNDER_3B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_3B_CH2_S 9 +/** DMA2D_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_4B_CH2 (BIT(10)) +#define DMA2D_IN_REMAIN_UNDER_4B_CH2_M (DMA2D_IN_REMAIN_UNDER_4B_CH2_V << DMA2D_IN_REMAIN_UNDER_4B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_4B_CH2_S 10 +/** DMA2D_IN_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_5B_CH2 (BIT(11)) +#define DMA2D_IN_REMAIN_UNDER_5B_CH2_M (DMA2D_IN_REMAIN_UNDER_5B_CH2_V << DMA2D_IN_REMAIN_UNDER_5B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_5B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_5B_CH2_S 11 +/** DMA2D_IN_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_6B_CH2 (BIT(12)) +#define DMA2D_IN_REMAIN_UNDER_6B_CH2_M (DMA2D_IN_REMAIN_UNDER_6B_CH2_V << DMA2D_IN_REMAIN_UNDER_6B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_6B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_6B_CH2_S 12 +/** DMA2D_IN_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_7B_CH2 (BIT(13)) +#define DMA2D_IN_REMAIN_UNDER_7B_CH2_M (DMA2D_IN_REMAIN_UNDER_7B_CH2_V << DMA2D_IN_REMAIN_UNDER_7B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_7B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_7B_CH2_S 13 +/** DMA2D_IN_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_8B_CH2 (BIT(14)) +#define DMA2D_IN_REMAIN_UNDER_8B_CH2_M (DMA2D_IN_REMAIN_UNDER_8B_CH2_V << DMA2D_IN_REMAIN_UNDER_8B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_8B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_8B_CH2_S 14 +/** DMA2D_INFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0; + * Rx FIFO full signal for Rx channel 0. + */ +#define DMA2D_INFIFO_FULL_L1_CH2 (BIT(15)) +#define DMA2D_INFIFO_FULL_L1_CH2_M (DMA2D_INFIFO_FULL_L1_CH2_V << DMA2D_INFIFO_FULL_L1_CH2_S) +#define DMA2D_INFIFO_FULL_L1_CH2_V 0x00000001U +#define DMA2D_INFIFO_FULL_L1_CH2_S 15 +/** DMA2D_INFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1; + * Rx FIFO empty signal for Rx channel 0. + */ +#define DMA2D_INFIFO_EMPTY_L1_CH2 (BIT(16)) +#define DMA2D_INFIFO_EMPTY_L1_CH2_M (DMA2D_INFIFO_EMPTY_L1_CH2_V << DMA2D_INFIFO_EMPTY_L1_CH2_S) +#define DMA2D_INFIFO_EMPTY_L1_CH2_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L1_CH2_S 16 +/** DMA2D_INFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. + */ +#define DMA2D_INFIFO_CNT_L1_CH2 0x0000001FU +#define DMA2D_INFIFO_CNT_L1_CH2_M (DMA2D_INFIFO_CNT_L1_CH2_V << DMA2D_INFIFO_CNT_L1_CH2_S) +#define DMA2D_INFIFO_CNT_L1_CH2_V 0x0000001FU +#define DMA2D_INFIFO_CNT_L1_CH2_S 17 +/** DMA2D_INFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0; + * Rx FIFO full signal for Rx channel 0. + */ +#define DMA2D_INFIFO_FULL_L3_CH2 (BIT(22)) +#define DMA2D_INFIFO_FULL_L3_CH2_M (DMA2D_INFIFO_FULL_L3_CH2_V << DMA2D_INFIFO_FULL_L3_CH2_S) +#define DMA2D_INFIFO_FULL_L3_CH2_V 0x00000001U +#define DMA2D_INFIFO_FULL_L3_CH2_S 22 +/** DMA2D_INFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1; + * Rx FIFO empty signal for Rx channel 0. + */ +#define DMA2D_INFIFO_EMPTY_L3_CH2 (BIT(23)) +#define DMA2D_INFIFO_EMPTY_L3_CH2_M (DMA2D_INFIFO_EMPTY_L3_CH2_V << DMA2D_INFIFO_EMPTY_L3_CH2_S) +#define DMA2D_INFIFO_EMPTY_L3_CH2_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L3_CH2_S 23 +/** DMA2D_INFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. + */ +#define DMA2D_INFIFO_CNT_L3_CH2 0x0000001FU +#define DMA2D_INFIFO_CNT_L3_CH2_M (DMA2D_INFIFO_CNT_L3_CH2_V << DMA2D_INFIFO_CNT_L3_CH2_S) +#define DMA2D_INFIFO_CNT_L3_CH2_V 0x0000001FU +#define DMA2D_INFIFO_CNT_L3_CH2_S 24 + +/** DMA2D_IN_POP_CH2_REG register + * Configures the rx fifo of channel 2 + */ +#define DMA2D_IN_POP_CH2_REG (DR_REG_DMA2D_BASE + 0x718) +/** DMA2D_INFIFO_RDATA_CH2 : RO; bitpos: [10:0]; default: 1024; + * This register stores the data popping from DMA Rx FIFO. + */ +#define DMA2D_INFIFO_RDATA_CH2 0x000007FFU +#define DMA2D_INFIFO_RDATA_CH2_M (DMA2D_INFIFO_RDATA_CH2_V << DMA2D_INFIFO_RDATA_CH2_S) +#define DMA2D_INFIFO_RDATA_CH2_V 0x000007FFU +#define DMA2D_INFIFO_RDATA_CH2_S 0 +/** DMA2D_INFIFO_POP_CH2 : R/W/SC; bitpos: [11]; default: 0; + * Set this bit to pop data from DMA Rx FIFO. + */ +#define DMA2D_INFIFO_POP_CH2 (BIT(11)) +#define DMA2D_INFIFO_POP_CH2_M (DMA2D_INFIFO_POP_CH2_V << DMA2D_INFIFO_POP_CH2_S) +#define DMA2D_INFIFO_POP_CH2_V 0x00000001U +#define DMA2D_INFIFO_POP_CH2_S 11 + +/** DMA2D_IN_LINK_CONF_CH2_REG register + * Configures the rx descriptor operations of channel 2 + */ +#define DMA2D_IN_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x71c) +/** DMA2D_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; + * Configure the value of the owner field written back to the inlink descriptor. + * 1: Write back 1. 0: Write back 0. + */ +#define DMA2D_INLINK_AUTO_RET_CH2 (BIT(20)) +#define DMA2D_INLINK_AUTO_RET_CH2_M (DMA2D_INLINK_AUTO_RET_CH2_V << DMA2D_INLINK_AUTO_RET_CH2_S) +#define DMA2D_INLINK_AUTO_RET_CH2_V 0x00000001U +#define DMA2D_INLINK_AUTO_RET_CH2_S 20 +/** DMA2D_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define DMA2D_INLINK_STOP_CH2 (BIT(21)) +#define DMA2D_INLINK_STOP_CH2_M (DMA2D_INLINK_STOP_CH2_V << DMA2D_INLINK_STOP_CH2_S) +#define DMA2D_INLINK_STOP_CH2_V 0x00000001U +#define DMA2D_INLINK_STOP_CH2_S 21 +/** DMA2D_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define DMA2D_INLINK_START_CH2 (BIT(22)) +#define DMA2D_INLINK_START_CH2_M (DMA2D_INLINK_START_CH2_V << DMA2D_INLINK_START_CH2_S) +#define DMA2D_INLINK_START_CH2_V 0x00000001U +#define DMA2D_INLINK_START_CH2_S 22 +/** DMA2D_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define DMA2D_INLINK_RESTART_CH2 (BIT(23)) +#define DMA2D_INLINK_RESTART_CH2_M (DMA2D_INLINK_RESTART_CH2_V << DMA2D_INLINK_RESTART_CH2_S) +#define DMA2D_INLINK_RESTART_CH2_V 0x00000001U +#define DMA2D_INLINK_RESTART_CH2_S 23 +/** DMA2D_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define DMA2D_INLINK_PARK_CH2 (BIT(24)) +#define DMA2D_INLINK_PARK_CH2_M (DMA2D_INLINK_PARK_CH2_V << DMA2D_INLINK_PARK_CH2_S) +#define DMA2D_INLINK_PARK_CH2_V 0x00000001U +#define DMA2D_INLINK_PARK_CH2_S 24 + +/** DMA2D_IN_LINK_ADDR_CH2_REG register + * Configures the rx descriptor address of channel 2 + */ +#define DMA2D_IN_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x720) +/** DMA2D_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; + * This register stores the first inlink descriptor's address. + */ +#define DMA2D_INLINK_ADDR_CH2 0xFFFFFFFFU +#define DMA2D_INLINK_ADDR_CH2_M (DMA2D_INLINK_ADDR_CH2_V << DMA2D_INLINK_ADDR_CH2_S) +#define DMA2D_INLINK_ADDR_CH2_V 0xFFFFFFFFU +#define DMA2D_INLINK_ADDR_CH2_S 0 + +/** DMA2D_IN_STATE_CH2_REG register + * Represents the working status of the rx descriptor of channel 2 + */ +#define DMA2D_IN_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x724) +/** DMA2D_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define DMA2D_INLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define DMA2D_INLINK_DSCR_ADDR_CH2_M (DMA2D_INLINK_DSCR_ADDR_CH2_V << DMA2D_INLINK_DSCR_ADDR_CH2_S) +#define DMA2D_INLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define DMA2D_INLINK_DSCR_ADDR_CH2_S 0 +/** DMA2D_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define DMA2D_IN_DSCR_STATE_CH2 0x00000003U +#define DMA2D_IN_DSCR_STATE_CH2_M (DMA2D_IN_DSCR_STATE_CH2_V << DMA2D_IN_DSCR_STATE_CH2_S) +#define DMA2D_IN_DSCR_STATE_CH2_V 0x00000003U +#define DMA2D_IN_DSCR_STATE_CH2_S 18 +/** DMA2D_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define DMA2D_IN_STATE_CH2 0x00000007U +#define DMA2D_IN_STATE_CH2_M (DMA2D_IN_STATE_CH2_V << DMA2D_IN_STATE_CH2_S) +#define DMA2D_IN_STATE_CH2_V 0x00000007U +#define DMA2D_IN_STATE_CH2_S 20 +/** DMA2D_IN_RESET_AVAIL_CH2 : RO; bitpos: [23]; default: 1; + * This register indicate that if the channel reset is safety. + */ +#define DMA2D_IN_RESET_AVAIL_CH2 (BIT(23)) +#define DMA2D_IN_RESET_AVAIL_CH2_M (DMA2D_IN_RESET_AVAIL_CH2_V << DMA2D_IN_RESET_AVAIL_CH2_S) +#define DMA2D_IN_RESET_AVAIL_CH2_V 0x00000001U +#define DMA2D_IN_RESET_AVAIL_CH2_S 23 + +/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 + */ +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x728) +/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S) +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S 0 + +/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 + */ +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x72c) +/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. + */ +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S) +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S 0 + +/** DMA2D_IN_DSCR_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 + */ +#define DMA2D_IN_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x730) +/** DMA2D_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the next inlink descriptor address x. + */ +#define DMA2D_INLINK_DSCR_CH2 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_CH2_M (DMA2D_INLINK_DSCR_CH2_V << DMA2D_INLINK_DSCR_CH2_S) +#define DMA2D_INLINK_DSCR_CH2_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_CH2_S 0 + +/** DMA2D_IN_DSCR_BF0_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 + */ +#define DMA2D_IN_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x734) +/** DMA2D_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor's next address x-1. + */ +#define DMA2D_INLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF0_CH2_M (DMA2D_INLINK_DSCR_BF0_CH2_V << DMA2D_INLINK_DSCR_BF0_CH2_S) +#define DMA2D_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF0_CH2_S 0 + +/** DMA2D_IN_DSCR_BF1_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 + */ +#define DMA2D_IN_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x738) +/** DMA2D_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor's next address x-2. + */ +#define DMA2D_INLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF1_CH2_M (DMA2D_INLINK_DSCR_BF1_CH2_V << DMA2D_INLINK_DSCR_BF1_CH2_S) +#define DMA2D_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF1_CH2_S 0 + +/** DMA2D_IN_PERI_SEL_CH2_REG register + * Configures the rx peripheral of channel 2 + */ +#define DMA2D_IN_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x73c) +/** DMA2D_IN_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7; + * This register is used to select peripheral for Rx channel 0: jpeg 1: + * display-1 2: display-2 7: no choose + */ +#define DMA2D_IN_PERI_SEL_CH2 0x00000007U +#define DMA2D_IN_PERI_SEL_CH2_M (DMA2D_IN_PERI_SEL_CH2_V << DMA2D_IN_PERI_SEL_CH2_S) +#define DMA2D_IN_PERI_SEL_CH2_V 0x00000007U +#define DMA2D_IN_PERI_SEL_CH2_S 0 + +/** DMA2D_IN_ARB_CH2_REG register + * Configures the rx arbiter of channel 2 + */ +#define DMA2D_IN_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x740) +/** DMA2D_IN_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1; + * Set the max number of token count of arbiter + */ +#define DMA2D_IN_ARB_TOKEN_NUM_CH2 0x0000000FU +#define DMA2D_IN_ARB_TOKEN_NUM_CH2_M (DMA2D_IN_ARB_TOKEN_NUM_CH2_V << DMA2D_IN_ARB_TOKEN_NUM_CH2_S) +#define DMA2D_IN_ARB_TOKEN_NUM_CH2_V 0x0000000FU +#define DMA2D_IN_ARB_TOKEN_NUM_CH2_S 0 +/** DMA2D_IN_ARB_PRIORITY_CH2 : R/W; bitpos: [7:4]; default: 1; + * Set the priority of channel + */ +#define DMA2D_IN_ARB_PRIORITY_CH2 0x0000000FU +#define DMA2D_IN_ARB_PRIORITY_CH2_M (DMA2D_IN_ARB_PRIORITY_CH2_V << DMA2D_IN_ARB_PRIORITY_CH2_S) +#define DMA2D_IN_ARB_PRIORITY_CH2_V 0x0000000FU +#define DMA2D_IN_ARB_PRIORITY_CH2_S 4 + +/** DMA2D_IN_RO_STATUS_CH2_REG register + * Represents the status of the rx reorder module of channel 2 + */ +#define DMA2D_IN_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x744) +/** DMA2D_INFIFO_RO_CNT_CH2 : RO; bitpos: [4:0]; default: 0; + * The register stores the byte number of the data in color convert Rx FIFO for + * channel 0. + */ +#define DMA2D_INFIFO_RO_CNT_CH2 0x0000001FU +#define DMA2D_INFIFO_RO_CNT_CH2_M (DMA2D_INFIFO_RO_CNT_CH2_V << DMA2D_INFIFO_RO_CNT_CH2_S) +#define DMA2D_INFIFO_RO_CNT_CH2_V 0x0000001FU +#define DMA2D_INFIFO_RO_CNT_CH2_S 0 +/** DMA2D_IN_RO_WR_STATE_CH2 : RO; bitpos: [6:5]; default: 0; + * The register stores the state of read ram of reorder + */ +#define DMA2D_IN_RO_WR_STATE_CH2 0x00000003U +#define DMA2D_IN_RO_WR_STATE_CH2_M (DMA2D_IN_RO_WR_STATE_CH2_V << DMA2D_IN_RO_WR_STATE_CH2_S) +#define DMA2D_IN_RO_WR_STATE_CH2_V 0x00000003U +#define DMA2D_IN_RO_WR_STATE_CH2_S 5 +/** DMA2D_IN_RO_RD_STATE_CH2 : RO; bitpos: [8:7]; default: 0; + * The register stores the state of write ram of reorder + */ +#define DMA2D_IN_RO_RD_STATE_CH2 0x00000003U +#define DMA2D_IN_RO_RD_STATE_CH2_M (DMA2D_IN_RO_RD_STATE_CH2_V << DMA2D_IN_RO_RD_STATE_CH2_S) +#define DMA2D_IN_RO_RD_STATE_CH2_V 0x00000003U +#define DMA2D_IN_RO_RD_STATE_CH2_S 7 +/** DMA2D_IN_PIXEL_BYTE_CH2 : RO; bitpos: [12:9]; default: 0; + * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes + * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes + */ +#define DMA2D_IN_PIXEL_BYTE_CH2 0x0000000FU +#define DMA2D_IN_PIXEL_BYTE_CH2_M (DMA2D_IN_PIXEL_BYTE_CH2_V << DMA2D_IN_PIXEL_BYTE_CH2_S) +#define DMA2D_IN_PIXEL_BYTE_CH2_V 0x0000000FU +#define DMA2D_IN_PIXEL_BYTE_CH2_S 9 +/** DMA2D_IN_BURST_BLOCK_NUM_CH2 : RO; bitpos: [16:13]; default: 0; + * the number of macro blocks contained in a burst of data at RX channel + */ +#define DMA2D_IN_BURST_BLOCK_NUM_CH2 0x0000000FU +#define DMA2D_IN_BURST_BLOCK_NUM_CH2_M (DMA2D_IN_BURST_BLOCK_NUM_CH2_V << DMA2D_IN_BURST_BLOCK_NUM_CH2_S) +#define DMA2D_IN_BURST_BLOCK_NUM_CH2_V 0x0000000FU +#define DMA2D_IN_BURST_BLOCK_NUM_CH2_S 13 + +/** DMA2D_IN_ETM_CONF_CH2_REG register + * Configures the rx etm of channel 2 + */ +#define DMA2D_IN_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x76c) +/** DMA2D_IN_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0; + * Configures the enable of the etm function, 1 is enable. + */ +#define DMA2D_IN_ETM_EN_CH2 (BIT(0)) +#define DMA2D_IN_ETM_EN_CH2_M (DMA2D_IN_ETM_EN_CH2_V << DMA2D_IN_ETM_EN_CH2_S) +#define DMA2D_IN_ETM_EN_CH2_V 0x00000001U +#define DMA2D_IN_ETM_EN_CH2_S 0 +/** DMA2D_IN_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0; + * Configures the enable of the descriptors loop etm function, 1 is enable. + */ +#define DMA2D_IN_ETM_LOOP_EN_CH2 (BIT(1)) +#define DMA2D_IN_ETM_LOOP_EN_CH2_M (DMA2D_IN_ETM_LOOP_EN_CH2_V << DMA2D_IN_ETM_LOOP_EN_CH2_S) +#define DMA2D_IN_ETM_LOOP_EN_CH2_V 0x00000001U +#define DMA2D_IN_ETM_LOOP_EN_CH2_S 1 +/** DMA2D_IN_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1; + * Configures the maximum number of cacheable descriptors. + */ +#define DMA2D_IN_DSCR_TASK_MAK_CH2 0x00000003U +#define DMA2D_IN_DSCR_TASK_MAK_CH2_M (DMA2D_IN_DSCR_TASK_MAK_CH2_V << DMA2D_IN_DSCR_TASK_MAK_CH2_S) +#define DMA2D_IN_DSCR_TASK_MAK_CH2_V 0x00000003U +#define DMA2D_IN_DSCR_TASK_MAK_CH2_S 2 + /** DMA2D_AXI_ERR_REG register * Represents the status of th axi bus */ @@ -5257,7 +7177,7 @@ extern "C" { * register version. */ #define DMA2D_DATE_REG (DR_REG_DMA2D_BASE + 0xa2c) -/** DMA2D_DATE : R/W; bitpos: [31:0]; default: 36716816; +/** DMA2D_DATE : R/W; bitpos: [31:0]; default: 37822864; * register version. */ #define DMA2D_DATE 0xFFFFFFFFU diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h index 30fef532db..7105d670bc 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h @@ -10,11 +10,8 @@ extern "C" { #endif -//TODO: IDF-13427 - -/** Group: out */ /** Type of out_conf0_chn register - * Configures the tx direction of channel 0 + * Configures the tx direction of channel n */ typedef union { struct { @@ -48,7 +45,7 @@ typedef union { */ uint32_t out_loop_test_chn:1; /** out_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 + * Block size of Tx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 * bytes 4: 128 bytes */ uint32_t out_mem_burst_length_chn:3; @@ -92,7 +89,7 @@ typedef union { } dma2d_out_conf0_chn_reg_t; /** Type of out_int_raw_chn register - * Raw interrupt status of TX channel 0 + * Raw interrupt status of TX channel n */ typedef union { struct { @@ -160,7 +157,7 @@ typedef union { } dma2d_out_int_raw_chn_reg_t; /** Type of out_int_ena_chn register - * Interrupt enable bits of TX channel 0 + * Interrupt enable bits of TX channel n */ typedef union { struct { @@ -222,7 +219,7 @@ typedef union { } dma2d_out_int_ena_chn_reg_t; /** Type of out_int_st_chn register - * Masked interrupt status of TX channel 0 + * Masked interrupt status of TX channel n */ typedef union { struct { @@ -284,7 +281,7 @@ typedef union { } dma2d_out_int_st_chn_reg_t; /** Type of out_int_clr_chn register - * Interrupt clear bits of TX channel 0 + * Interrupt clear bits of TX channel n */ typedef union { struct { @@ -346,20 +343,20 @@ typedef union { } dma2d_out_int_clr_chn_reg_t; /** Type of outfifo_status_chn register - * Represents the status of the tx fifo of channel 0 + * Represents the status of the tx fifo of channel n */ typedef union { struct { /** outfifo_full_l2_chn : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Tx FIFO full signal for Tx channel n. */ uint32_t outfifo_full_l2_chn:1; /** outfifo_empty_l2_chn : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Tx FIFO empty signal for Tx channel n. */ uint32_t outfifo_empty_l2_chn:1; /** outfifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Tx FIFO for Tx channel n. */ uint32_t outfifo_cnt_l2_chn:4; uint32_t reserved_6:1; @@ -396,27 +393,27 @@ typedef union { */ uint32_t out_remain_under_8b_chn:1; /** outfifo_full_l1_chn : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Tx FIFO full signal for Tx channel n. */ uint32_t outfifo_full_l1_chn:1; /** outfifo_empty_l1_chn : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Tx FIFO empty signal for Tx channel n. */ uint32_t outfifo_empty_l1_chn:1; /** outfifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Tx FIFO for Tx channel n. */ uint32_t outfifo_cnt_l1_chn:5; /** outfifo_full_l3_chn : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Tx FIFO full signal for Tx channel n. */ uint32_t outfifo_full_l3_chn:1; /** outfifo_empty_l3_chn : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Tx FIFO empty signal for Tx channel n. */ uint32_t outfifo_empty_l3_chn:1; /** outfifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Tx FIFO for Tx channel n. */ uint32_t outfifo_cnt_l3_chn:5; uint32_t reserved_29:3; @@ -425,7 +422,7 @@ typedef union { } dma2d_outfifo_status_chn_reg_t; /** Type of out_push_chn register - * Configures the tx fifo of channel 0 + * Configures the tx fifo of channel n */ typedef union { struct { @@ -443,7 +440,7 @@ typedef union { } dma2d_out_push_chn_reg_t; /** Type of out_link_conf_chn register - * Configures the tx descriptor operations of channel 0 + * Configures the tx descriptor operations of channel n */ typedef union { struct { @@ -471,7 +468,7 @@ typedef union { } dma2d_out_link_conf_chn_reg_t; /** Type of out_link_addr_chn register - * Configures the tx descriptor address of channel 0 + * Configures the tx descriptor address of channel n */ typedef union { struct { @@ -484,7 +481,7 @@ typedef union { } dma2d_out_link_addr_chn_reg_t; /** Type of out_state_chn register - * Represents the working status of the tx descriptor of channel 0 + * Represents the working status of the tx descriptor of channel n */ typedef union { struct { @@ -510,7 +507,7 @@ typedef union { } dma2d_out_state_chn_reg_t; /** Type of out_eof_des_addr_chn register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel n */ typedef union { struct { @@ -524,7 +521,7 @@ typedef union { } dma2d_out_eof_des_addr_chn_reg_t; /** Type of out_dscr_chn register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel n */ typedef union { struct { @@ -537,7 +534,7 @@ typedef union { } dma2d_out_dscr_chn_reg_t; /** Type of out_dscr_bf0_chn register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel n */ typedef union { struct { @@ -550,7 +547,7 @@ typedef union { } dma2d_out_dscr_bf0_chn_reg_t; /** Type of out_dscr_bf1_chn register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel n */ typedef union { struct { @@ -563,7 +560,7 @@ typedef union { } dma2d_out_dscr_bf1_chn_reg_t; /** Type of out_peri_sel_chn register - * Configures the tx peripheral of channel 0 + * Configures the tx peripheral of channel n */ typedef union { struct { @@ -578,7 +575,7 @@ typedef union { } dma2d_out_peri_sel_chn_reg_t; /** Type of out_arb_chn register - * Configures the tx arbiter of channel 0 + * Configures the tx arbiter of channel n */ typedef union { struct { @@ -586,17 +583,17 @@ typedef union { * Set the max number of token count of arbiter */ uint32_t out_arb_token_num_chn:4; - /** out_arb_priority_chn : R/W; bitpos: [5:4]; default: 1; + /** out_arb_priority_chn : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ - uint32_t out_arb_priority_chn:2; - uint32_t reserved_6:26; + uint32_t out_arb_priority_chn:4; + uint32_t reserved_8:24; }; uint32_t val; } dma2d_out_arb_chn_reg_t; /** Type of out_ro_status_chn register - * Represents the status of the tx reorder module of channel 0 + * Represents the status of the tx reorder module of channel n */ typedef union { struct { @@ -628,7 +625,7 @@ typedef union { } dma2d_out_ro_status_chn_reg_t; /** Type of out_ro_pd_conf_chn register - * Configures the tx reorder memory of channel 0 + * Configures the tx reorder memory of channel n */ typedef union { struct { @@ -652,7 +649,7 @@ typedef union { } dma2d_out_ro_pd_conf_chn_reg_t; /** Type of out_color_convert_chn register - * Configures the tx color convert of channel 0 + * Configures the tx color convert of channel n */ typedef union { struct { @@ -678,7 +675,7 @@ typedef union { } dma2d_out_color_convert_chn_reg_t; /** Type of out_scramble_chn register - * Configures the tx scramble of channel 0 + * Configures the tx scramble of channel n */ typedef union { struct { @@ -693,7 +690,7 @@ typedef union { } dma2d_out_scramble_chn_reg_t; /** Type of out_etm_conf_chn register - * Configures the tx etm of channel 0 + * Configures the tx etm of channel n */ typedef union { struct { @@ -732,10 +729,8 @@ typedef union { uint32_t val; } dma2d_out_dscr_port_blk_chn_reg_t; - -/** Group: in */ /** Type of in_conf0_chn register - * Configures the rx direction of channel 0 + * Configures the rx direction of channel n */ typedef union { struct { @@ -808,7 +803,7 @@ typedef union { } dma2d_in_conf0_chn_reg_t; /** Type of in_int_raw_chn register - * Raw interrupt status of RX channel 0 + * Raw interrupt status of RX channel n */ typedef union { struct { @@ -880,7 +875,7 @@ typedef union { } dma2d_in_int_raw_chn_reg_t; /** Type of in_int_ena_chn register - * Interrupt enable bits of RX channel 0 + * Interrupt enable bits of RX channel n */ typedef union { struct { @@ -946,7 +941,7 @@ typedef union { } dma2d_in_int_ena_chn_reg_t; /** Type of in_int_st_chn register - * Masked interrupt status of RX channel 0 + * Masked interrupt status of RX channel n */ typedef union { struct { @@ -1012,7 +1007,7 @@ typedef union { } dma2d_in_int_st_chn_reg_t; /** Type of in_int_clr_chn register - * Interrupt clear bits of RX channel 0 + * Interrupt clear bits of RX channel n */ typedef union { struct { @@ -1078,20 +1073,20 @@ typedef union { } dma2d_in_int_clr_chn_reg_t; /** Type of infifo_status_chn register - * Represents the status of the rx fifo of channel 0 + * Represents the status of the rx fifo of channel n */ typedef union { struct { /** infifo_full_l2_chn : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. + * Rx FIFO full signal for Rx channel n. */ uint32_t infifo_full_l2_chn:1; /** infifo_empty_l2_chn : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. + * Rx FIFO empty signal for Rx channel n. */ uint32_t infifo_empty_l2_chn:1; /** infifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. + * The register stores the byte number of the data in Rx FIFO for Rx channel n. */ uint32_t infifo_cnt_l2_chn:4; uint32_t reserved_6:1; @@ -1128,27 +1123,27 @@ typedef union { */ uint32_t in_remain_under_8b_chn:1; /** infifo_full_l1_chn : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Rx FIFO full signal for Tx channel n. */ uint32_t infifo_full_l1_chn:1; /** infifo_empty_l1_chn : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Rx FIFO empty signal for Tx channel n. */ uint32_t infifo_empty_l1_chn:1; /** infifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Rx FIFO for Rx channel n. */ uint32_t infifo_cnt_l1_chn:5; /** infifo_full_l3_chn : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Rx FIFO full signal for Rx channel n. */ uint32_t infifo_full_l3_chn:1; /** infifo_empty_l3_chn : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Rx FIFO empty signal for Rx channel n. */ uint32_t infifo_empty_l3_chn:1; /** infifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Rx FIFO for Rx channel n. */ uint32_t infifo_cnt_l3_chn:5; uint32_t reserved_29:3; @@ -1157,7 +1152,7 @@ typedef union { } dma2d_infifo_status_chn_reg_t; /** Type of in_pop_chn register - * Configures the rx fifo of channel 0 + * Configures the rx fifo of channel n */ typedef union { struct { @@ -1175,7 +1170,7 @@ typedef union { } dma2d_in_pop_chn_reg_t; /** Type of in_link_conf_chn register - * Configures the rx descriptor operations of channel 0 + * Configures the rx descriptor operations of channel n */ typedef union { struct { @@ -1208,7 +1203,7 @@ typedef union { } dma2d_in_link_conf_chn_reg_t; /** Type of in_link_addr_chn register - * Configures the rx descriptor address of channel 0 + * Configures the rx descriptor address of channel n */ typedef union { struct { @@ -1221,7 +1216,7 @@ typedef union { } dma2d_in_link_addr_chn_reg_t; /** Type of in_state_chn register - * Represents the working status of the rx descriptor of channel 0 + * Represents the working status of the rx descriptor of channel n */ typedef union { struct { @@ -1247,7 +1242,7 @@ typedef union { } dma2d_in_state_chn_reg_t; /** Type of in_suc_eof_des_addr_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1261,7 +1256,7 @@ typedef union { } dma2d_in_suc_eof_des_addr_chn_reg_t; /** Type of in_err_eof_des_addr_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1275,7 +1270,7 @@ typedef union { } dma2d_in_err_eof_des_addr_chn_reg_t; /** Type of in_dscr_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1288,7 +1283,7 @@ typedef union { } dma2d_in_dscr_chn_reg_t; /** Type of in_dscr_bf0_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1301,7 +1296,7 @@ typedef union { } dma2d_in_dscr_bf0_chn_reg_t; /** Type of in_dscr_bf1_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1314,7 +1309,7 @@ typedef union { } dma2d_in_dscr_bf1_chn_reg_t; /** Type of in_peri_sel_chn register - * Configures the rx peripheral of channel 0 + * Configures the rx peripheral of channel n */ typedef union { struct { @@ -1329,7 +1324,7 @@ typedef union { } dma2d_in_peri_sel_chn_reg_t; /** Type of in_arb_chn register - * Configures the rx arbiter of channel 0 + * Configures the rx arbiter of channel n */ typedef union { struct { @@ -1337,17 +1332,17 @@ typedef union { * Set the max number of token count of arbiter */ uint32_t in_arb_token_num_chn:4; - /** in_arb_priority_chn : R/W; bitpos: [4]; default: 1; + /** in_arb_priority_chn : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ - uint32_t in_arb_priority_chn:1; - uint32_t reserved_5:27; + uint32_t in_arb_priority_chn:4; + uint32_t reserved_8:24; }; uint32_t val; } dma2d_in_arb_chn_reg_t; /** Type of in_ro_status_chn register - * Represents the status of the rx reorder module of channel 0 + * Represents the status of the rx reorder module of channel n */ typedef union { struct { @@ -1379,7 +1374,7 @@ typedef union { } dma2d_in_ro_status_chn_reg_t; /** Type of in_ro_pd_conf_chn register - * Configures the rx reorder memory of channel 0 + * Configures the rx reorder memory of channel n */ typedef union { struct { @@ -1403,13 +1398,13 @@ typedef union { } dma2d_in_ro_pd_conf_chn_reg_t; /** Type of in_color_convert_chn register - * Configures the tx color convert of channel 0 + * Configures the Rx color convert of channel n */ typedef union { struct { /** in_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0; * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly + * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 */ uint32_t in_color_output_sel_chn:2; /** in_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0; @@ -1428,7 +1423,7 @@ typedef union { } dma2d_in_color_convert_chn_reg_t; /** Type of in_scramble_chn register - * Configures the rx scramble of channel 0 + * Configures the rx scramble of channel n */ typedef union { struct { @@ -1448,7 +1443,7 @@ typedef union { } dma2d_in_scramble_chn_reg_t; /** Type of in_etm_conf_chn register - * Configures the rx etm of channel 0 + * Configures the rx etm of channel n */ typedef union { struct { @@ -1469,8 +1464,6 @@ typedef union { uint32_t val; } dma2d_in_etm_conf_chn_reg_t; - -/** Group: Status Registers */ /** Type of axi_err register * Represents the status of th axi bus */ @@ -1514,7 +1507,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [31:0]; default: 36716816; + /** date : R/W; bitpos: [31:0]; default: 37822864; * register version. */ uint32_t date:32; @@ -1522,8 +1515,6 @@ typedef union { uint32_t val; } dma2d_date_reg_t; - -/** Group: Configuration Registers */ /** Type of rst_conf register * Configures the reset of axi */ @@ -1681,7 +1672,6 @@ typedef union { uint32_t val; } dma2d_rdn_eco_low_reg_t; - /** Type of in/out_color_param_h/m/l_chn register * Configures the rx/tx color convert parameter of channel n */ @@ -1713,12 +1703,14 @@ typedef union { uint32_t val[2]; } dma2d_color_param_reg_t; + typedef struct { volatile dma2d_color_param_reg_t param_h; volatile dma2d_color_param_reg_t param_m; volatile dma2d_color_param_reg_t param_l; } dma2d_color_param_group_chn_reg_t; + typedef struct { volatile dma2d_out_conf0_chn_reg_t out_conf0; volatile dma2d_out_int_raw_chn_reg_t out_int_raw; @@ -1746,32 +1738,6 @@ typedef struct { uint32_t reserved_out[36]; } dma2d_out_chn_reg_t; -typedef struct { - volatile dma2d_in_conf0_chn_reg_t in_conf0; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena; - volatile dma2d_in_int_st_chn_reg_t in_int_st; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr; - volatile dma2d_infifo_status_chn_reg_t infifo_status; - volatile dma2d_in_pop_chn_reg_t in_pop; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr; - volatile dma2d_in_state_chn_reg_t in_state; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr; - volatile dma2d_in_dscr_chn_reg_t in_dscr; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel; - volatile dma2d_in_arb_chn_reg_t in_arb; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert; - volatile dma2d_in_scramble_chn_reg_t in_scramble; - volatile dma2d_color_param_group_chn_reg_t in_color_param_group; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; - uint32_t reserved_570[36]; -} dma2d_in_ch0_reg_t; typedef struct { volatile dma2d_in_conf0_chn_reg_t in_conf0; @@ -1792,16 +1758,20 @@ typedef struct { volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel; volatile dma2d_in_arb_chn_reg_t in_arb; volatile dma2d_in_ro_status_chn_reg_t in_ro_status; + volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; /* only exist on channel0 */ + volatile dma2d_in_color_convert_chn_reg_t in_color_convert; /* only exist on channel0 */ + volatile dma2d_in_scramble_chn_reg_t in_scramble; /* only exist on channel0 */ + volatile dma2d_color_param_group_chn_reg_t in_color_param_group; /* only exist on channel0 */ volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; - uint32_t reserved_64c[45]; -} dma2d_in_ch1_reg_t; + uint32_t reserved_in[36]; +} dma2d_in_chn_reg_t; + typedef struct dma2d_dev_t { - volatile dma2d_out_chn_reg_t out_channel[3]; - uint32_t reserved_300[128]; - volatile dma2d_in_ch0_reg_t in_channel0; - volatile dma2d_in_ch1_reg_t in_channel1; - uint32_t reserved_700[192]; + volatile dma2d_out_chn_reg_t out_channel[4]; + uint32_t reserved_400[64]; + volatile dma2d_in_chn_reg_t in_channel[3]; + uint32_t reserved_800[128]; volatile dma2d_axi_err_reg_t axi_err; volatile dma2d_rst_conf_reg_t rst_conf; volatile dma2d_intr_mem_start_addr_reg_t intr_mem_start_addr; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/interrupts.h b/components/soc/esp32p4/register/hw_ver3/soc/interrupts.h deleted file mode 100644 index 2b03a849a4..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/interrupts.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include - -#ifdef __cplusplus -extern "C" -{ -#endif - -//Interrupt hardware source table -//This table is decided by hardware, don't touch this. -typedef enum { - ETS_LP_RTC_INT_SOURCE, - ETS_LP_WDT_INT_SOURCE, - ETS_LP_TIMER_REG_0_INT_SOURCE, - ETS_LP_TIMER_REG_1_INT_SOURCE, - ETS_MB_HP_INT_SOURCE, - ETS_MB_LP_INT_SOURCE, - ETS_PMU_REG_0_INT_SOURCE, - ETS_PMU_REG_1_INT_SOURCE, - ETS_LP_ANAPERI_INT_SOURCE, - ETS_LP_ADC_INT_SOURCE, - ETS_LP_GPIO_INT_SOURCE, - ETS_LP_I2C_INT_SOURCE, - ETS_LP_I2S_INT_SOURCE, - ETS_LP_SPI_INT_SOURCE, - ETS_LP_TOUCH_INT_SOURCE, - ETS_LP_TSENS_INT_SOURCE, - ETS_LP_UART_INT_SOURCE, - ETS_LP_EFUSE_INT_SOURCE, - ETS_LP_SW_INT_SOURCE, - ETS_LP_SYSREG_INT_SOURCE, - ETS_LP_HUK_INT_SOURCE, - ETS_SYS_ICM_INT_SOURCE, - ETS_USB_DEVICE_INT_SOURCE, - ETS_SDIO_HOST_INT_SOURCE, - ETS_GDMA_INT_SOURCE, - ETS_SPI2_INT_SOURCE, - ETS_SPI3_INT_SOURCE, - ETS_I2S0_INT_SOURCE, - ETS_I2S1_INT_SOURCE, - ETS_I2S2_INT_SOURCE, - ETS_UHCI0_INT_SOURCE, - ETS_UART0_INT_SOURCE, - ETS_UART1_INT_SOURCE, - ETS_UART2_INT_SOURCE, - ETS_UART3_INT_SOURCE, - ETS_UART4_INT_SOURCE, - ETS_LCD_CAM_INT_SOURCE, - ETS_ADC_INT_SOURCE, - ETS_PWM0_INT_SOURCE, - ETS_PWM1_INT_SOURCE, - ETS_TWAI0_INT_SOURCE, - ETS_TWAI1_INT_SOURCE, - ETS_TWAI2_INT_SOURCE, - ETS_RMT_INT_SOURCE, - ETS_I2C0_INT_SOURCE, - ETS_I2C1_INT_SOURCE, - ETS_TIMERGRP0_T0_INT_SOURCE, - ETS_TIMERGRP0_T1_INT_SOURCE, - ETS_TIMERGRP0_WDT_INT_SOURCE, - ETS_TIMERGRP1_T0_INT_SOURCE, - ETS_TIMERGRP1_T1_INT_SOURCE, - ETS_TIMERGRP1_WDT_INT_SOURCE, - ETS_LEDC_INT_SOURCE, - ETS_SYSTIMER_TARGET0_INT_SOURCE, - ETS_SYSTIMER_TARGET1_INT_SOURCE, - ETS_SYSTIMER_TARGET2_INT_SOURCE, - ETS_AHB_PDMA_IN_CH0_INT_SOURCE, - ETS_AHB_PDMA_IN_CH1_INT_SOURCE, - ETS_AHB_PDMA_IN_CH2_INT_SOURCE, - ETS_AHB_PDMA_OUT_CH0_INT_SOURCE, - ETS_AHB_PDMA_OUT_CH1_INT_SOURCE, - ETS_AHB_PDMA_OUT_CH2_INT_SOURCE, - ETS_AXI_PDMA_IN_CH0_INT_SOURCE, - ETS_AXI_PDMA_IN_CH1_INT_SOURCE, - ETS_AXI_PDMA_IN_CH2_INT_SOURCE, - ETS_AXI_PDMA_OUT_CH0_INT_SOURCE, - ETS_AXI_PDMA_OUT_CH1_INT_SOURCE, - ETS_AXI_PDMA_OUT_CH2_INT_SOURCE, - ETS_RSA_INT_SOURCE, - ETS_AES_INT_SOURCE, - ETS_SHA_INT_SOURCE, - ETS_ECC_INT_SOURCE, - ETS_ECDSA_INT_SOURCE, - ETS_KM_INT_SOURCE, - ETS_GPIO_INT0_SOURCE, - ETS_GPIO_INT1_SOURCE, - ETS_GPIO_INT2_SOURCE, - ETS_GPIO_INT3_SOURCE, - ETS_GPIO_PAD_COMP_INT_SOURCE, - ETS_CPU_INT_FROM_CPU_0_SOURCE, - ETS_CPU_INT_FROM_CPU_1_SOURCE, - ETS_CPU_INT_FROM_CPU_2_SOURCE, - ETS_CPU_INT_FROM_CPU_3_SOURCE, - ETS_CACHE_INT_SOURCE, - ETS_FLASH_MSPI_INT_SOURCE, - ETS_CSI_BRIDGE_INT_SOURCE, - ETS_DSI_BRIDGE_INT_SOURCE, - ETS_CSI_INT_SOURCE, - ETS_DSI_INT_SOURCE, - ETS_GMII_PHY_INT_SOURCE, - ETS_LPI_INT_SOURCE, - ETS_PMT_INT_SOURCE, - ETS_SBD_INT_SOURCE, - ETS_USB_OTG_INT_SOURCE, - ETS_USB_OTG_ENDP_MULTI_PROC_INT_SOURCE, - ETS_JPEG_INT_SOURCE, - ETS_PPA_INT_SOURCE, - ETS_CORE0_TRACE_INT_SOURCE, - ETS_CORE1_TRACE_INT_SOURCE, - ETS_HP_CORE_CTRL_INT_SOURCE, - ETS_ISP_INT_SOURCE, - ETS_I3C_MST_INT_SOURCE, - ETS_I3C_SLV_INT_SOURCE, - ETS_USB_OTG11_INT_SOURCE, - ETS_DMA2D_IN_CH0_INT_SOURCE, - ETS_DMA2D_IN_CH1_INT_SOURCE, - ETS_DMA2D_OUT_CH0_INT_SOURCE, - ETS_DMA2D_OUT_CH1_INT_SOURCE, - ETS_DMA2D_OUT_CH2_INT_SOURCE, - ETS_PSRAM_MSPI_INT_SOURCE, - ETS_HP_SYSREG_INT_SOURCE, - ETS_PCNT_INT_SOURCE, - ETS_HP_PAU_INT_SOURCE, - ETS_HP_PARLIO_RX_INT_SOURCE, - ETS_HP_PARLIO_TX_INT_SOURCE, - ETS_H264_DMA2D_OUT_CH0_INT_SOURCE, - ETS_H264_DMA2D_OUT_CH1_INT_SOURCE, - ETS_H264_DMA2D_OUT_CH2_INT_SOURCE, - ETS_H264_DMA2D_OUT_CH3_INT_SOURCE, - ETS_H264_DMA2D_OUT_CH4_INT_SOURCE, - ETS_H264_DMA2D_IN_CH0_INT_SOURCE, - ETS_H264_DMA2D_IN_CH1_INT_SOURCE, - ETS_H264_DMA2D_IN_CH2_INT_SOURCE, - ETS_H264_DMA2D_IN_CH3_INT_SOURCE, - ETS_H264_DMA2D_IN_CH4_INT_SOURCE, - ETS_H264_DMA2D_IN_CH5_INT_SOURCE, - ETS_H264_REG_INT_SOURCE, - ETS_ASSIST_DEBUG_INT_SOURCE, - ETS_DMA2D_IN_CH2_INT_SOURCE, - ETS_DMA2D_OUT_CH3_INT_SOURCE, - ETS_AXI_PERF_MON_INT_SOURCE, - ETS_MAX_INTR_SOURCE, -} periph_interrupt_t; - -extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_reg.h deleted file mode 100644 index b10ff9f379..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_reg.h +++ /dev/null @@ -1,3116 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** LEDC_CH0_CONF0_REG register - * Configuration register 0 for channel 0 - */ -#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) -/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 0 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH0 0x00000003U -#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) -#define LEDC_TIMER_SEL_CH0_V 0x00000003U -#define LEDC_TIMER_SEL_CH0_S 0 -/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 0. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) -#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH0_S 2 -/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 0 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH0 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH0 (BIT(3)) -#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) -#define LEDC_IDLE_LV_CH0_V 0x00000001U -#define LEDC_IDLE_LV_CH0_S 3 -/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0, - * LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0, - * LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel - * 0, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH0 (BIT(4)) -#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) -#define LEDC_PARA_UP_CH0_V 0x00000001U -#define LEDC_PARA_UP_CH0_S 4 -/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH0_INT interrupt - * will be triggered when channel 0 overflows for (LEDC_OVF_NUM_CH0 + 1) times. - */ -#define LEDC_OVF_NUM_CH0 0x000003FFU -#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) -#define LEDC_OVF_NUM_CH0_V 0x000003FFU -#define LEDC_OVF_NUM_CH0_S 5 -/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 0. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) -#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH0_S 15 -/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 0. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) -#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH0_S 16 - -/** LEDC_CH0_HPOINT_REG register - * High point register for channel 0 - */ -#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4) -/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 0. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH0 0x000FFFFFU -#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) -#define LEDC_HPOINT_CH0_V 0x000FFFFFU -#define LEDC_HPOINT_CH0_S 0 - -/** LEDC_CH0_DUTY_REG register - * Initial duty cycle register for channel 0 - */ -#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8) -/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 0. - */ -#define LEDC_DUTY_CH0 0x01FFFFFFU -#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) -#define LEDC_DUTY_CH0_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_S 0 - -/** LEDC_CH0_CONF1_REG register - * Configuration register 1 for channel 0 - */ -#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) -/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH0 (BIT(31)) -#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) -#define LEDC_DUTY_START_CH0_V 0x00000001U -#define LEDC_DUTY_START_CH0_S 31 - -/** LEDC_CH0_DUTY_R_REG register - * Current duty cycle register for channel 0 - */ -#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10) -/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 0. - */ -#define LEDC_DUTY_CH0_R 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) -#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_S 0 - -/** LEDC_CH1_CONF0_REG register - * Configuration register 0 for channel 1 - */ -#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) -/** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 1 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH1 0x00000003U -#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) -#define LEDC_TIMER_SEL_CH1_V 0x00000003U -#define LEDC_TIMER_SEL_CH1_S 0 -/** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 1. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH1 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) -#define LEDC_SIG_OUT_EN_CH1_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH1_S 2 -/** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 1 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH1 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH1 (BIT(3)) -#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) -#define LEDC_IDLE_LV_CH1_V 0x00000001U -#define LEDC_IDLE_LV_CH1_S 3 -/** LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1, - * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1, - * LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel - * 1, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH1 (BIT(4)) -#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) -#define LEDC_PARA_UP_CH1_V 0x00000001U -#define LEDC_PARA_UP_CH1_S 4 -/** LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH1_INT interrupt - * will be triggered when channel 1 overflows for (LEDC_OVF_NUM_CH1 + 1) times. - */ -#define LEDC_OVF_NUM_CH1 0x000003FFU -#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S) -#define LEDC_OVF_NUM_CH1_V 0x000003FFU -#define LEDC_OVF_NUM_CH1_S 5 -/** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 1. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH1 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) -#define LEDC_OVF_CNT_EN_CH1_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH1_S 15 -/** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 1. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) -#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH1_S 16 - -/** LEDC_CH1_HPOINT_REG register - * High point register for channel 1 - */ -#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18) -/** LEDC_HPOINT_CH1 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 1. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH1 0x000FFFFFU -#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S) -#define LEDC_HPOINT_CH1_V 0x000FFFFFU -#define LEDC_HPOINT_CH1_S 0 - -/** LEDC_CH1_DUTY_REG register - * Initial duty cycle register for channel 1 - */ -#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c) -/** LEDC_DUTY_CH1 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 1. - */ -#define LEDC_DUTY_CH1 0x01FFFFFFU -#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S) -#define LEDC_DUTY_CH1_V 0x01FFFFFFU -#define LEDC_DUTY_CH1_S 0 - -/** LEDC_CH1_CONF1_REG register - * Configuration register 1 for channel 1 - */ -#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) -/** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH1 (BIT(31)) -#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) -#define LEDC_DUTY_START_CH1_V 0x00000001U -#define LEDC_DUTY_START_CH1_S 31 - -/** LEDC_CH1_DUTY_R_REG register - * Current duty cycle register for channel 1 - */ -#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24) -/** LEDC_DUTY_CH1_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 1. - */ -#define LEDC_DUTY_CH1_R 0x01FFFFFFU -#define LEDC_DUTY_CH1_R_M (LEDC_DUTY_CH1_R_V << LEDC_DUTY_CH1_R_S) -#define LEDC_DUTY_CH1_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH1_R_S 0 - -/** LEDC_CH2_CONF0_REG register - * Configuration register 0 for channel 2 - */ -#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) -/** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 2 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH2 0x00000003U -#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) -#define LEDC_TIMER_SEL_CH2_V 0x00000003U -#define LEDC_TIMER_SEL_CH2_S 0 -/** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 2. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH2 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) -#define LEDC_SIG_OUT_EN_CH2_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH2_S 2 -/** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 2 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH2 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH2 (BIT(3)) -#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) -#define LEDC_IDLE_LV_CH2_V 0x00000001U -#define LEDC_IDLE_LV_CH2_S 3 -/** LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2, - * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2, - * LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel - * 2, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH2 (BIT(4)) -#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) -#define LEDC_PARA_UP_CH2_V 0x00000001U -#define LEDC_PARA_UP_CH2_S 4 -/** LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH2_INT interrupt - * will be triggered when channel 2 overflows for (LEDC_OVF_NUM_CH2 + 1) times. - */ -#define LEDC_OVF_NUM_CH2 0x000003FFU -#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S) -#define LEDC_OVF_NUM_CH2_V 0x000003FFU -#define LEDC_OVF_NUM_CH2_S 5 -/** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 2. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH2 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) -#define LEDC_OVF_CNT_EN_CH2_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH2_S 15 -/** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 2. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) -#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH2_S 16 - -/** LEDC_CH2_HPOINT_REG register - * High point register for channel 2 - */ -#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c) -/** LEDC_HPOINT_CH2 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 2. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH2 0x000FFFFFU -#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S) -#define LEDC_HPOINT_CH2_V 0x000FFFFFU -#define LEDC_HPOINT_CH2_S 0 - -/** LEDC_CH2_DUTY_REG register - * Initial duty cycle register for channel 2 - */ -#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30) -/** LEDC_DUTY_CH2 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 2. - */ -#define LEDC_DUTY_CH2 0x01FFFFFFU -#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S) -#define LEDC_DUTY_CH2_V 0x01FFFFFFU -#define LEDC_DUTY_CH2_S 0 - -/** LEDC_CH2_CONF1_REG register - * Configuration register 1 for channel 2 - */ -#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) -/** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH2 (BIT(31)) -#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) -#define LEDC_DUTY_START_CH2_V 0x00000001U -#define LEDC_DUTY_START_CH2_S 31 - -/** LEDC_CH2_DUTY_R_REG register - * Current duty cycle register for channel 2 - */ -#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38) -/** LEDC_DUTY_CH2_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 2. - */ -#define LEDC_DUTY_CH2_R 0x01FFFFFFU -#define LEDC_DUTY_CH2_R_M (LEDC_DUTY_CH2_R_V << LEDC_DUTY_CH2_R_S) -#define LEDC_DUTY_CH2_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH2_R_S 0 - -/** LEDC_CH3_CONF0_REG register - * Configuration register 0 for channel 3 - */ -#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) -/** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 3 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH3 0x00000003U -#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) -#define LEDC_TIMER_SEL_CH3_V 0x00000003U -#define LEDC_TIMER_SEL_CH3_S 0 -/** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 3. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH3 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) -#define LEDC_SIG_OUT_EN_CH3_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH3_S 2 -/** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 3 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH3 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH3 (BIT(3)) -#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) -#define LEDC_IDLE_LV_CH3_V 0x00000001U -#define LEDC_IDLE_LV_CH3_S 3 -/** LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3, - * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3, - * LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel - * 3, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH3 (BIT(4)) -#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) -#define LEDC_PARA_UP_CH3_V 0x00000001U -#define LEDC_PARA_UP_CH3_S 4 -/** LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH3_INT interrupt - * will be triggered when channel 3 overflows for (LEDC_OVF_NUM_CH3 + 1) times. - */ -#define LEDC_OVF_NUM_CH3 0x000003FFU -#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S) -#define LEDC_OVF_NUM_CH3_V 0x000003FFU -#define LEDC_OVF_NUM_CH3_S 5 -/** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 3. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH3 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) -#define LEDC_OVF_CNT_EN_CH3_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH3_S 15 -/** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 3. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) -#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH3_S 16 - -/** LEDC_CH3_HPOINT_REG register - * High point register for channel 3 - */ -#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40) -/** LEDC_HPOINT_CH3 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 3. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH3 0x000FFFFFU -#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S) -#define LEDC_HPOINT_CH3_V 0x000FFFFFU -#define LEDC_HPOINT_CH3_S 0 - -/** LEDC_CH3_DUTY_REG register - * Initial duty cycle register for channel 3 - */ -#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44) -/** LEDC_DUTY_CH3 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 3. - */ -#define LEDC_DUTY_CH3 0x01FFFFFFU -#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S) -#define LEDC_DUTY_CH3_V 0x01FFFFFFU -#define LEDC_DUTY_CH3_S 0 - -/** LEDC_CH3_CONF1_REG register - * Configuration register 1 for channel 3 - */ -#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) -/** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH3 (BIT(31)) -#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) -#define LEDC_DUTY_START_CH3_V 0x00000001U -#define LEDC_DUTY_START_CH3_S 31 - -/** LEDC_CH3_DUTY_R_REG register - * Current duty cycle register for channel 3 - */ -#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c) -/** LEDC_DUTY_CH3_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 3. - */ -#define LEDC_DUTY_CH3_R 0x01FFFFFFU -#define LEDC_DUTY_CH3_R_M (LEDC_DUTY_CH3_R_V << LEDC_DUTY_CH3_R_S) -#define LEDC_DUTY_CH3_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH3_R_S 0 - -/** LEDC_CH4_CONF0_REG register - * Configuration register 0 for channel 4 - */ -#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) -/** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 4 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH4 0x00000003U -#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) -#define LEDC_TIMER_SEL_CH4_V 0x00000003U -#define LEDC_TIMER_SEL_CH4_S 0 -/** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 4. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH4 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) -#define LEDC_SIG_OUT_EN_CH4_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH4_S 2 -/** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 4 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH4 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH4 (BIT(3)) -#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) -#define LEDC_IDLE_LV_CH4_V 0x00000001U -#define LEDC_IDLE_LV_CH4_S 3 -/** LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4, - * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4, - * LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel - * 4, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH4 (BIT(4)) -#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) -#define LEDC_PARA_UP_CH4_V 0x00000001U -#define LEDC_PARA_UP_CH4_S 4 -/** LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH4_INT interrupt - * will be triggered when channel 4 overflows for (LEDC_OVF_NUM_CH4 + 1) times. - */ -#define LEDC_OVF_NUM_CH4 0x000003FFU -#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S) -#define LEDC_OVF_NUM_CH4_V 0x000003FFU -#define LEDC_OVF_NUM_CH4_S 5 -/** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 4. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH4 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) -#define LEDC_OVF_CNT_EN_CH4_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH4_S 15 -/** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 4. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) -#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH4_S 16 - -/** LEDC_CH4_HPOINT_REG register - * High point register for channel 4 - */ -#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54) -/** LEDC_HPOINT_CH4 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 4. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH4 0x000FFFFFU -#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S) -#define LEDC_HPOINT_CH4_V 0x000FFFFFU -#define LEDC_HPOINT_CH4_S 0 - -/** LEDC_CH4_DUTY_REG register - * Initial duty cycle register for channel 4 - */ -#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58) -/** LEDC_DUTY_CH4 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 4. - */ -#define LEDC_DUTY_CH4 0x01FFFFFFU -#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S) -#define LEDC_DUTY_CH4_V 0x01FFFFFFU -#define LEDC_DUTY_CH4_S 0 - -/** LEDC_CH4_CONF1_REG register - * Configuration register 1 for channel 4 - */ -#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) -/** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH4 (BIT(31)) -#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) -#define LEDC_DUTY_START_CH4_V 0x00000001U -#define LEDC_DUTY_START_CH4_S 31 - -/** LEDC_CH4_DUTY_R_REG register - * Current duty cycle register for channel 4 - */ -#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60) -/** LEDC_DUTY_CH4_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 4. - */ -#define LEDC_DUTY_CH4_R 0x01FFFFFFU -#define LEDC_DUTY_CH4_R_M (LEDC_DUTY_CH4_R_V << LEDC_DUTY_CH4_R_S) -#define LEDC_DUTY_CH4_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH4_R_S 0 - -/** LEDC_CH5_CONF0_REG register - * Configuration register 0 for channel 5 - */ -#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) -/** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 5 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH5 0x00000003U -#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) -#define LEDC_TIMER_SEL_CH5_V 0x00000003U -#define LEDC_TIMER_SEL_CH5_S 0 -/** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 5. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH5 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) -#define LEDC_SIG_OUT_EN_CH5_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH5_S 2 -/** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 5 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH5 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH5 (BIT(3)) -#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) -#define LEDC_IDLE_LV_CH5_V 0x00000001U -#define LEDC_IDLE_LV_CH5_S 3 -/** LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5, - * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5, - * LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel - * 5, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH5 (BIT(4)) -#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) -#define LEDC_PARA_UP_CH5_V 0x00000001U -#define LEDC_PARA_UP_CH5_S 4 -/** LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH5_INT interrupt - * will be triggered when channel 5 overflows for (LEDC_OVF_NUM_CH5 + 1) times. - */ -#define LEDC_OVF_NUM_CH5 0x000003FFU -#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S) -#define LEDC_OVF_NUM_CH5_V 0x000003FFU -#define LEDC_OVF_NUM_CH5_S 5 -/** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 5. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH5 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) -#define LEDC_OVF_CNT_EN_CH5_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH5_S 15 -/** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 5. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) -#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH5_S 16 - -/** LEDC_CH5_HPOINT_REG register - * High point register for channel 5 - */ -#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68) -/** LEDC_HPOINT_CH5 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 5. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH5 0x000FFFFFU -#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S) -#define LEDC_HPOINT_CH5_V 0x000FFFFFU -#define LEDC_HPOINT_CH5_S 0 - -/** LEDC_CH5_DUTY_REG register - * Initial duty cycle register for channel 5 - */ -#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c) -/** LEDC_DUTY_CH5 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 5. - */ -#define LEDC_DUTY_CH5 0x01FFFFFFU -#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S) -#define LEDC_DUTY_CH5_V 0x01FFFFFFU -#define LEDC_DUTY_CH5_S 0 - -/** LEDC_CH5_CONF1_REG register - * Configuration register 1 for channel 5 - */ -#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) -/** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH5 (BIT(31)) -#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) -#define LEDC_DUTY_START_CH5_V 0x00000001U -#define LEDC_DUTY_START_CH5_S 31 - -/** LEDC_CH5_DUTY_R_REG register - * Current duty cycle register for channel 5 - */ -#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74) -/** LEDC_DUTY_CH5_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 5. - */ -#define LEDC_DUTY_CH5_R 0x01FFFFFFU -#define LEDC_DUTY_CH5_R_M (LEDC_DUTY_CH5_R_V << LEDC_DUTY_CH5_R_S) -#define LEDC_DUTY_CH5_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH5_R_S 0 - -/** LEDC_CH6_CONF0_REG register - * Configuration register 0 for channel 6 - */ -#define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78) -/** LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 6 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH6 0x00000003U -#define LEDC_TIMER_SEL_CH6_M (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S) -#define LEDC_TIMER_SEL_CH6_V 0x00000003U -#define LEDC_TIMER_SEL_CH6_S 0 -/** LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 6. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH6 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH6_M (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S) -#define LEDC_SIG_OUT_EN_CH6_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH6_S 2 -/** LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 6 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH6 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH6 (BIT(3)) -#define LEDC_IDLE_LV_CH6_M (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S) -#define LEDC_IDLE_LV_CH6_V 0x00000001U -#define LEDC_IDLE_LV_CH6_S 3 -/** LEDC_PARA_UP_CH6 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH6, LEDC_DUTY_START_CH6, - * LEDC_SIG_OUT_EN_CH6, LEDC_TIMER_SEL_CH6, LEDC_DUTY_NUM_CH6, LEDC_DUTY_CYCLE_CH6, - * LEDC_DUTY_SCALE_CH6, LEDC_DUTY_INC_CH6, and LEDC_OVF_CNT_EN_CH6 fields for channel - * 6, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH6 (BIT(4)) -#define LEDC_PARA_UP_CH6_M (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S) -#define LEDC_PARA_UP_CH6_V 0x00000001U -#define LEDC_PARA_UP_CH6_S 4 -/** LEDC_OVF_NUM_CH6 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH6_INT interrupt - * will be triggered when channel 6 overflows for (LEDC_OVF_NUM_CH6 + 1) times. - */ -#define LEDC_OVF_NUM_CH6 0x000003FFU -#define LEDC_OVF_NUM_CH6_M (LEDC_OVF_NUM_CH6_V << LEDC_OVF_NUM_CH6_S) -#define LEDC_OVF_NUM_CH6_V 0x000003FFU -#define LEDC_OVF_NUM_CH6_S 5 -/** LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 6. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH6 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH6_M (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S) -#define LEDC_OVF_CNT_EN_CH6_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH6_S 15 -/** LEDC_OVF_CNT_RESET_CH6 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 6. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH6 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH6_M (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S) -#define LEDC_OVF_CNT_RESET_CH6_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH6_S 16 - -/** LEDC_CH6_HPOINT_REG register - * High point register for channel 6 - */ -#define LEDC_CH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x7c) -/** LEDC_HPOINT_CH6 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 6. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH6 0x000FFFFFU -#define LEDC_HPOINT_CH6_M (LEDC_HPOINT_CH6_V << LEDC_HPOINT_CH6_S) -#define LEDC_HPOINT_CH6_V 0x000FFFFFU -#define LEDC_HPOINT_CH6_S 0 - -/** LEDC_CH6_DUTY_REG register - * Initial duty cycle register for channel 6 - */ -#define LEDC_CH6_DUTY_REG (DR_REG_LEDC_BASE + 0x80) -/** LEDC_DUTY_CH6 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 6. - */ -#define LEDC_DUTY_CH6 0x01FFFFFFU -#define LEDC_DUTY_CH6_M (LEDC_DUTY_CH6_V << LEDC_DUTY_CH6_S) -#define LEDC_DUTY_CH6_V 0x01FFFFFFU -#define LEDC_DUTY_CH6_S 0 - -/** LEDC_CH6_CONF1_REG register - * Configuration register 1 for channel 6 - */ -#define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84) -/** LEDC_DUTY_START_CH6 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH6 (BIT(31)) -#define LEDC_DUTY_START_CH6_M (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S) -#define LEDC_DUTY_START_CH6_V 0x00000001U -#define LEDC_DUTY_START_CH6_S 31 - -/** LEDC_CH6_DUTY_R_REG register - * Current duty cycle register for channel 6 - */ -#define LEDC_CH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x88) -/** LEDC_DUTY_CH6_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 6. - */ -#define LEDC_DUTY_CH6_R 0x01FFFFFFU -#define LEDC_DUTY_CH6_R_M (LEDC_DUTY_CH6_R_V << LEDC_DUTY_CH6_R_S) -#define LEDC_DUTY_CH6_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH6_R_S 0 - -/** LEDC_CH7_CONF0_REG register - * Configuration register 0 for channel 7 - */ -#define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c) -/** LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 7 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH7 0x00000003U -#define LEDC_TIMER_SEL_CH7_M (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S) -#define LEDC_TIMER_SEL_CH7_V 0x00000003U -#define LEDC_TIMER_SEL_CH7_S 0 -/** LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 7. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH7 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH7_M (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S) -#define LEDC_SIG_OUT_EN_CH7_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH7_S 2 -/** LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 7 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH7 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH7 (BIT(3)) -#define LEDC_IDLE_LV_CH7_M (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S) -#define LEDC_IDLE_LV_CH7_V 0x00000001U -#define LEDC_IDLE_LV_CH7_S 3 -/** LEDC_PARA_UP_CH7 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH7, LEDC_DUTY_START_CH7, - * LEDC_SIG_OUT_EN_CH7, LEDC_TIMER_SEL_CH7, LEDC_DUTY_NUM_CH7, LEDC_DUTY_CYCLE_CH7, - * LEDC_DUTY_SCALE_CH7, LEDC_DUTY_INC_CH7, and LEDC_OVF_CNT_EN_CH7 fields for channel - * 7, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH7 (BIT(4)) -#define LEDC_PARA_UP_CH7_M (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S) -#define LEDC_PARA_UP_CH7_V 0x00000001U -#define LEDC_PARA_UP_CH7_S 4 -/** LEDC_OVF_NUM_CH7 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH7_INT interrupt - * will be triggered when channel 7 overflows for (LEDC_OVF_NUM_CH7 + 1) times. - */ -#define LEDC_OVF_NUM_CH7 0x000003FFU -#define LEDC_OVF_NUM_CH7_M (LEDC_OVF_NUM_CH7_V << LEDC_OVF_NUM_CH7_S) -#define LEDC_OVF_NUM_CH7_V 0x000003FFU -#define LEDC_OVF_NUM_CH7_S 5 -/** LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 7. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH7 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH7_M (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S) -#define LEDC_OVF_CNT_EN_CH7_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH7_S 15 -/** LEDC_OVF_CNT_RESET_CH7 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 7. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH7 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH7_M (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S) -#define LEDC_OVF_CNT_RESET_CH7_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH7_S 16 - -/** LEDC_CH7_HPOINT_REG register - * High point register for channel 7 - */ -#define LEDC_CH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x90) -/** LEDC_HPOINT_CH7 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 7. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH7 0x000FFFFFU -#define LEDC_HPOINT_CH7_M (LEDC_HPOINT_CH7_V << LEDC_HPOINT_CH7_S) -#define LEDC_HPOINT_CH7_V 0x000FFFFFU -#define LEDC_HPOINT_CH7_S 0 - -/** LEDC_CH7_DUTY_REG register - * Initial duty cycle register for channel 7 - */ -#define LEDC_CH7_DUTY_REG (DR_REG_LEDC_BASE + 0x94) -/** LEDC_DUTY_CH7 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 7. - */ -#define LEDC_DUTY_CH7 0x01FFFFFFU -#define LEDC_DUTY_CH7_M (LEDC_DUTY_CH7_V << LEDC_DUTY_CH7_S) -#define LEDC_DUTY_CH7_V 0x01FFFFFFU -#define LEDC_DUTY_CH7_S 0 - -/** LEDC_CH7_CONF1_REG register - * Configuration register 1 for channel 7 - */ -#define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98) -/** LEDC_DUTY_START_CH7 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH7 (BIT(31)) -#define LEDC_DUTY_START_CH7_M (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S) -#define LEDC_DUTY_START_CH7_V 0x00000001U -#define LEDC_DUTY_START_CH7_S 31 - -/** LEDC_CH7_DUTY_R_REG register - * Current duty cycle register for channel 7 - */ -#define LEDC_CH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x9c) -/** LEDC_DUTY_CH7_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 7. - */ -#define LEDC_DUTY_CH7_R 0x01FFFFFFU -#define LEDC_DUTY_CH7_R_M (LEDC_DUTY_CH7_R_V << LEDC_DUTY_CH7_R_S) -#define LEDC_DUTY_CH7_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH7_R_S 0 - -/** LEDC_TIMER0_CONF_REG register - * Timer 0 configuration register - */ -#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0) -/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer 0. - */ -#define LEDC_TIMER0_DUTY_RES 0x0000001FU -#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) -#define LEDC_TIMER0_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER0_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer 0.The least significant eight bits - * represent the fractional part. - */ -#define LEDC_CLK_DIV_TIMER0 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) -#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER0_S 5 -/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 0. - * 0: Normal - * 1: Pause - */ -#define LEDC_TIMER0_PAUSE (BIT(23)) -#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) -#define LEDC_TIMER0_PAUSE_V 0x00000001U -#define LEDC_TIMER0_PAUSE_S 23 -/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 0. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ -#define LEDC_TIMER0_RST (BIT(24)) -#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) -#define LEDC_TIMER0_RST_V 0x00000001U -#define LEDC_TIMER0_RST_S 24 -/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER0 and LEDC_TIMER0_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_TIMER0_PARA_UP (BIT(26)) -#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) -#define LEDC_TIMER0_PARA_UP_V 0x00000001U -#define LEDC_TIMER0_PARA_UP_S 26 - -/** LEDC_TIMER0_VALUE_REG register - * Timer 0 current counter value register - */ -#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4) -/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer 0. - */ -#define LEDC_TIMER0_CNT 0x000FFFFFU -#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) -#define LEDC_TIMER0_CNT_V 0x000FFFFFU -#define LEDC_TIMER0_CNT_S 0 - -/** LEDC_TIMER1_CONF_REG register - * Timer 1 configuration register - */ -#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8) -/** LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer 1. - */ -#define LEDC_TIMER1_DUTY_RES 0x0000001FU -#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S) -#define LEDC_TIMER1_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER1_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer 1.The least significant eight bits - * represent the fractional part. - */ -#define LEDC_CLK_DIV_TIMER1 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S) -#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER1_S 5 -/** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 1. - * 0: Normal - * 1: Pause - */ -#define LEDC_TIMER1_PAUSE (BIT(23)) -#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) -#define LEDC_TIMER1_PAUSE_V 0x00000001U -#define LEDC_TIMER1_PAUSE_S 23 -/** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 1. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ -#define LEDC_TIMER1_RST (BIT(24)) -#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) -#define LEDC_TIMER1_RST_V 0x00000001U -#define LEDC_TIMER1_RST_S 24 -/** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and LEDC_TIMER1_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_TIMER1_PARA_UP (BIT(26)) -#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) -#define LEDC_TIMER1_PARA_UP_V 0x00000001U -#define LEDC_TIMER1_PARA_UP_S 26 - -/** LEDC_TIMER1_VALUE_REG register - * Timer 1 current counter value register - */ -#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac) -/** LEDC_TIMER1_CNT : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer 1. - */ -#define LEDC_TIMER1_CNT 0x000FFFFFU -#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S) -#define LEDC_TIMER1_CNT_V 0x000FFFFFU -#define LEDC_TIMER1_CNT_S 0 - -/** LEDC_TIMER2_CONF_REG register - * Timer 2 configuration register - */ -#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0) -/** LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer 2. - */ -#define LEDC_TIMER2_DUTY_RES 0x0000001FU -#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S) -#define LEDC_TIMER2_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER2_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer 2.The least significant eight bits - * represent the fractional part. - */ -#define LEDC_CLK_DIV_TIMER2 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S) -#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER2_S 5 -/** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 2. - * 0: Normal - * 1: Pause - */ -#define LEDC_TIMER2_PAUSE (BIT(23)) -#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) -#define LEDC_TIMER2_PAUSE_V 0x00000001U -#define LEDC_TIMER2_PAUSE_S 23 -/** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 2. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ -#define LEDC_TIMER2_RST (BIT(24)) -#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) -#define LEDC_TIMER2_RST_V 0x00000001U -#define LEDC_TIMER2_RST_S 24 -/** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and LEDC_TIMER2_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_TIMER2_PARA_UP (BIT(26)) -#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) -#define LEDC_TIMER2_PARA_UP_V 0x00000001U -#define LEDC_TIMER2_PARA_UP_S 26 - -/** LEDC_TIMER2_VALUE_REG register - * Timer 2 current counter value register - */ -#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4) -/** LEDC_TIMER2_CNT : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer 2. - */ -#define LEDC_TIMER2_CNT 0x000FFFFFU -#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S) -#define LEDC_TIMER2_CNT_V 0x000FFFFFU -#define LEDC_TIMER2_CNT_S 0 - -/** LEDC_TIMER3_CONF_REG register - * Timer 3 configuration register - */ -#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8) -/** LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer 3. - */ -#define LEDC_TIMER3_DUTY_RES 0x0000001FU -#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S) -#define LEDC_TIMER3_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER3_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer 3.The least significant eight bits - * represent the fractional part. - */ -#define LEDC_CLK_DIV_TIMER3 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S) -#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER3_S 5 -/** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 3. - * 0: Normal - * 1: Pause - */ -#define LEDC_TIMER3_PAUSE (BIT(23)) -#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) -#define LEDC_TIMER3_PAUSE_V 0x00000001U -#define LEDC_TIMER3_PAUSE_S 23 -/** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 3. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ -#define LEDC_TIMER3_RST (BIT(24)) -#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) -#define LEDC_TIMER3_RST_V 0x00000001U -#define LEDC_TIMER3_RST_S 24 -/** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and LEDC_TIMER3_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_TIMER3_PARA_UP (BIT(26)) -#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) -#define LEDC_TIMER3_PARA_UP_V 0x00000001U -#define LEDC_TIMER3_PARA_UP_S 26 - -/** LEDC_TIMER3_VALUE_REG register - * Timer 3 current counter value register - */ -#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc) -/** LEDC_TIMER3_CNT : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer 3. - */ -#define LEDC_TIMER3_CNT 0x000FFFFFU -#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S) -#define LEDC_TIMER3_CNT_V 0x000FFFFFU -#define LEDC_TIMER3_CNT_S 0 - -/** LEDC_INT_RAW_REG register - * Interrupt raw status register - */ -#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0) -/** LEDC_TIMER0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the - * timer0 has reached its maximum counter value. - */ -#define LEDC_TIMER0_OVF_INT_RAW (BIT(0)) -#define LEDC_TIMER0_OVF_INT_RAW_M (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S) -#define LEDC_TIMER0_OVF_INT_RAW_V 0x00000001U -#define LEDC_TIMER0_OVF_INT_RAW_S 0 -/** LEDC_TIMER1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the - * timer1 has reached its maximum counter value. - */ -#define LEDC_TIMER1_OVF_INT_RAW (BIT(1)) -#define LEDC_TIMER1_OVF_INT_RAW_M (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S) -#define LEDC_TIMER1_OVF_INT_RAW_V 0x00000001U -#define LEDC_TIMER1_OVF_INT_RAW_S 1 -/** LEDC_TIMER2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the - * timer2 has reached its maximum counter value. - */ -#define LEDC_TIMER2_OVF_INT_RAW (BIT(2)) -#define LEDC_TIMER2_OVF_INT_RAW_M (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S) -#define LEDC_TIMER2_OVF_INT_RAW_V 0x00000001U -#define LEDC_TIMER2_OVF_INT_RAW_S 2 -/** LEDC_TIMER3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the - * timer3 has reached its maximum counter value. - */ -#define LEDC_TIMER3_OVF_INT_RAW (BIT(3)) -#define LEDC_TIMER3_OVF_INT_RAW_M (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S) -#define LEDC_TIMER3_OVF_INT_RAW_V 0x00000001U -#define LEDC_TIMER3_OVF_INT_RAW_S 3 -/** LEDC_DUTY_CHNG_END_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S 4 -/** LEDC_DUTY_CHNG_END_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S 5 -/** LEDC_DUTY_CHNG_END_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S 6 -/** LEDC_DUTY_CHNG_END_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S 7 -/** LEDC_DUTY_CHNG_END_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S 8 -/** LEDC_DUTY_CHNG_END_CH5_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S 9 -/** LEDC_DUTY_CHNG_END_CH6_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_M (LEDC_DUTY_CHNG_END_CH6_INT_RAW_V << LEDC_DUTY_CHNG_END_CH6_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_S 10 -/** LEDC_DUTY_CHNG_END_CH7_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_M (LEDC_DUTY_CHNG_END_CH7_INT_RAW_V << LEDC_DUTY_CHNG_END_CH7_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_S 11 -/** LEDC_OVF_CNT_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. - */ -#define LEDC_OVF_CNT_CH0_INT_RAW (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_RAW_M (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S) -#define LEDC_OVF_CNT_CH0_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH0_INT_RAW_S 12 -/** LEDC_OVF_CNT_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. - */ -#define LEDC_OVF_CNT_CH1_INT_RAW (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_RAW_M (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S) -#define LEDC_OVF_CNT_CH1_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH1_INT_RAW_S 13 -/** LEDC_OVF_CNT_CH2_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. - */ -#define LEDC_OVF_CNT_CH2_INT_RAW (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_RAW_M (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S) -#define LEDC_OVF_CNT_CH2_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH2_INT_RAW_S 14 -/** LEDC_OVF_CNT_CH3_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. - */ -#define LEDC_OVF_CNT_CH3_INT_RAW (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_RAW_M (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S) -#define LEDC_OVF_CNT_CH3_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH3_INT_RAW_S 15 -/** LEDC_OVF_CNT_CH4_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. - */ -#define LEDC_OVF_CNT_CH4_INT_RAW (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_RAW_M (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S) -#define LEDC_OVF_CNT_CH4_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH4_INT_RAW_S 16 -/** LEDC_OVF_CNT_CH5_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. - */ -#define LEDC_OVF_CNT_CH5_INT_RAW (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_RAW_M (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S) -#define LEDC_OVF_CNT_CH5_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH5_INT_RAW_S 17 -/** LEDC_OVF_CNT_CH6_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. - */ -#define LEDC_OVF_CNT_CH6_INT_RAW (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_RAW_M (LEDC_OVF_CNT_CH6_INT_RAW_V << LEDC_OVF_CNT_CH6_INT_RAW_S) -#define LEDC_OVF_CNT_CH6_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH6_INT_RAW_S 18 -/** LEDC_OVF_CNT_CH7_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. - */ -#define LEDC_OVF_CNT_CH7_INT_RAW (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_RAW_M (LEDC_OVF_CNT_CH7_INT_RAW_V << LEDC_OVF_CNT_CH7_INT_RAW_S) -#define LEDC_OVF_CNT_CH7_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH7_INT_RAW_S 19 - -/** LEDC_INT_ST_REG register - * Interrupt masked status register - */ -#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4) -/** LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only - * when LEDC_TIMER0_OVF_INT_ENA is set to 1. - */ -#define LEDC_TIMER0_OVF_INT_ST (BIT(0)) -#define LEDC_TIMER0_OVF_INT_ST_M (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S) -#define LEDC_TIMER0_OVF_INT_ST_V 0x00000001U -#define LEDC_TIMER0_OVF_INT_ST_S 0 -/** LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only - * when LEDC_TIMER1_OVF_INT_ENA is set to 1. - */ -#define LEDC_TIMER1_OVF_INT_ST (BIT(1)) -#define LEDC_TIMER1_OVF_INT_ST_M (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S) -#define LEDC_TIMER1_OVF_INT_ST_V 0x00000001U -#define LEDC_TIMER1_OVF_INT_ST_S 1 -/** LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only - * when LEDC_TIMER2_OVF_INT_ENA is set to 1. - */ -#define LEDC_TIMER2_OVF_INT_ST (BIT(2)) -#define LEDC_TIMER2_OVF_INT_ST_M (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S) -#define LEDC_TIMER2_OVF_INT_ST_V 0x00000001U -#define LEDC_TIMER2_OVF_INT_ST_S 2 -/** LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only - * when LEDC_TIMER3_OVF_INT_ENA is set to 1. - */ -#define LEDC_TIMER3_OVF_INT_ST (BIT(3)) -#define LEDC_TIMER3_OVF_INT_ST_M (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S) -#define LEDC_TIMER3_OVF_INT_ST_V 0x00000001U -#define LEDC_TIMER3_OVF_INT_ST_S 3 -/** LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH0_INT_ST (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S 4 -/** LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH1_INT_ST (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S 5 -/** LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH2_INT_ST (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S 6 -/** LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH3_INT_ST (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S 7 -/** LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH4_INT_ST (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S 8 -/** LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH5_INT_ST (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S 9 -/** LEDC_DUTY_CHNG_END_CH6_INT_ST : RO; bitpos: [10]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH6_INT_ST (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_ST_M (LEDC_DUTY_CHNG_END_CH6_INT_ST_V << LEDC_DUTY_CHNG_END_CH6_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH6_INT_ST_S 10 -/** LEDC_DUTY_CHNG_END_CH7_INT_ST : RO; bitpos: [11]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH7_INT_ST (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_ST_M (LEDC_DUTY_CHNG_END_CH7_INT_ST_V << LEDC_DUTY_CHNG_END_CH7_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH7_INT_ST_S 11 -/** LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only - * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH0_INT_ST (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_ST_M (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S) -#define LEDC_OVF_CNT_CH0_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH0_INT_ST_S 12 -/** LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only - * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH1_INT_ST (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_ST_M (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S) -#define LEDC_OVF_CNT_CH1_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH1_INT_ST_S 13 -/** LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only - * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH2_INT_ST (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_ST_M (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S) -#define LEDC_OVF_CNT_CH2_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH2_INT_ST_S 14 -/** LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only - * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH3_INT_ST (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_ST_M (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S) -#define LEDC_OVF_CNT_CH3_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH3_INT_ST_S 15 -/** LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only - * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH4_INT_ST (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_ST_M (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S) -#define LEDC_OVF_CNT_CH4_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH4_INT_ST_S 16 -/** LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only - * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH5_INT_ST (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_ST_M (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S) -#define LEDC_OVF_CNT_CH5_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH5_INT_ST_S 17 -/** LEDC_OVF_CNT_CH6_INT_ST : RO; bitpos: [18]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only - * when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH6_INT_ST (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_ST_M (LEDC_OVF_CNT_CH6_INT_ST_V << LEDC_OVF_CNT_CH6_INT_ST_S) -#define LEDC_OVF_CNT_CH6_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH6_INT_ST_S 18 -/** LEDC_OVF_CNT_CH7_INT_ST : RO; bitpos: [19]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only - * when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH7_INT_ST (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_ST_M (LEDC_OVF_CNT_CH7_INT_ST_V << LEDC_OVF_CNT_CH7_INT_ST_S) -#define LEDC_OVF_CNT_CH7_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH7_INT_ST_S 19 - -/** LEDC_INT_ENA_REG register - * Interrupt enable register - */ -#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8) -/** LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. - */ -#define LEDC_TIMER0_OVF_INT_ENA (BIT(0)) -#define LEDC_TIMER0_OVF_INT_ENA_M (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S) -#define LEDC_TIMER0_OVF_INT_ENA_V 0x00000001U -#define LEDC_TIMER0_OVF_INT_ENA_S 0 -/** LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. - */ -#define LEDC_TIMER1_OVF_INT_ENA (BIT(1)) -#define LEDC_TIMER1_OVF_INT_ENA_M (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S) -#define LEDC_TIMER1_OVF_INT_ENA_V 0x00000001U -#define LEDC_TIMER1_OVF_INT_ENA_S 1 -/** LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. - */ -#define LEDC_TIMER2_OVF_INT_ENA (BIT(2)) -#define LEDC_TIMER2_OVF_INT_ENA_M (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S) -#define LEDC_TIMER2_OVF_INT_ENA_V 0x00000001U -#define LEDC_TIMER2_OVF_INT_ENA_S 2 -/** LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. - */ -#define LEDC_TIMER3_OVF_INT_ENA (BIT(3)) -#define LEDC_TIMER3_OVF_INT_ENA_M (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S) -#define LEDC_TIMER3_OVF_INT_ENA_V 0x00000001U -#define LEDC_TIMER3_OVF_INT_ENA_S 3 -/** LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. - */ -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S 4 -/** LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. - */ -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S 5 -/** LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. - */ -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S 6 -/** LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. - */ -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S 7 -/** LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. - */ -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S 8 -/** LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. - */ -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S 9 -/** LEDC_DUTY_CHNG_END_CH6_INT_ENA : R/W; bitpos: [10]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. - */ -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_M (LEDC_DUTY_CHNG_END_CH6_INT_ENA_V << LEDC_DUTY_CHNG_END_CH6_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_S 10 -/** LEDC_DUTY_CHNG_END_CH7_INT_ENA : R/W; bitpos: [11]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. - */ -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_M (LEDC_DUTY_CHNG_END_CH7_INT_ENA_V << LEDC_DUTY_CHNG_END_CH7_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_S 11 -/** LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. - */ -#define LEDC_OVF_CNT_CH0_INT_ENA (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_ENA_M (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S) -#define LEDC_OVF_CNT_CH0_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH0_INT_ENA_S 12 -/** LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. - */ -#define LEDC_OVF_CNT_CH1_INT_ENA (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_ENA_M (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S) -#define LEDC_OVF_CNT_CH1_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH1_INT_ENA_S 13 -/** LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. - */ -#define LEDC_OVF_CNT_CH2_INT_ENA (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_ENA_M (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S) -#define LEDC_OVF_CNT_CH2_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH2_INT_ENA_S 14 -/** LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. - */ -#define LEDC_OVF_CNT_CH3_INT_ENA (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_ENA_M (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S) -#define LEDC_OVF_CNT_CH3_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH3_INT_ENA_S 15 -/** LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. - */ -#define LEDC_OVF_CNT_CH4_INT_ENA (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_ENA_M (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S) -#define LEDC_OVF_CNT_CH4_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH4_INT_ENA_S 16 -/** LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. - */ -#define LEDC_OVF_CNT_CH5_INT_ENA (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_ENA_M (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S) -#define LEDC_OVF_CNT_CH5_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH5_INT_ENA_S 17 -/** LEDC_OVF_CNT_CH6_INT_ENA : R/W; bitpos: [18]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. - */ -#define LEDC_OVF_CNT_CH6_INT_ENA (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_ENA_M (LEDC_OVF_CNT_CH6_INT_ENA_V << LEDC_OVF_CNT_CH6_INT_ENA_S) -#define LEDC_OVF_CNT_CH6_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH6_INT_ENA_S 18 -/** LEDC_OVF_CNT_CH7_INT_ENA : R/W; bitpos: [19]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. - */ -#define LEDC_OVF_CNT_CH7_INT_ENA (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_ENA_M (LEDC_OVF_CNT_CH7_INT_ENA_V << LEDC_OVF_CNT_CH7_INT_ENA_S) -#define LEDC_OVF_CNT_CH7_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH7_INT_ENA_S 19 - -/** LEDC_INT_CLR_REG register - * Interrupt clear register - */ -#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc) -/** LEDC_TIMER0_OVF_INT_CLR : WT; bitpos: [0]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. - */ -#define LEDC_TIMER0_OVF_INT_CLR (BIT(0)) -#define LEDC_TIMER0_OVF_INT_CLR_M (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S) -#define LEDC_TIMER0_OVF_INT_CLR_V 0x00000001U -#define LEDC_TIMER0_OVF_INT_CLR_S 0 -/** LEDC_TIMER1_OVF_INT_CLR : WT; bitpos: [1]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. - */ -#define LEDC_TIMER1_OVF_INT_CLR (BIT(1)) -#define LEDC_TIMER1_OVF_INT_CLR_M (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S) -#define LEDC_TIMER1_OVF_INT_CLR_V 0x00000001U -#define LEDC_TIMER1_OVF_INT_CLR_S 1 -/** LEDC_TIMER2_OVF_INT_CLR : WT; bitpos: [2]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. - */ -#define LEDC_TIMER2_OVF_INT_CLR (BIT(2)) -#define LEDC_TIMER2_OVF_INT_CLR_M (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S) -#define LEDC_TIMER2_OVF_INT_CLR_V 0x00000001U -#define LEDC_TIMER2_OVF_INT_CLR_S 2 -/** LEDC_TIMER3_OVF_INT_CLR : WT; bitpos: [3]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. - */ -#define LEDC_TIMER3_OVF_INT_CLR (BIT(3)) -#define LEDC_TIMER3_OVF_INT_CLR_M (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S) -#define LEDC_TIMER3_OVF_INT_CLR_V 0x00000001U -#define LEDC_TIMER3_OVF_INT_CLR_S 3 -/** LEDC_DUTY_CHNG_END_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. - */ -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S 4 -/** LEDC_DUTY_CHNG_END_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. - */ -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S 5 -/** LEDC_DUTY_CHNG_END_CH2_INT_CLR : WT; bitpos: [6]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. - */ -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S 6 -/** LEDC_DUTY_CHNG_END_CH3_INT_CLR : WT; bitpos: [7]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. - */ -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S 7 -/** LEDC_DUTY_CHNG_END_CH4_INT_CLR : WT; bitpos: [8]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. - */ -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S 8 -/** LEDC_DUTY_CHNG_END_CH5_INT_CLR : WT; bitpos: [9]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. - */ -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S 9 -/** LEDC_DUTY_CHNG_END_CH6_INT_CLR : WT; bitpos: [10]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. - */ -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_M (LEDC_DUTY_CHNG_END_CH6_INT_CLR_V << LEDC_DUTY_CHNG_END_CH6_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_S 10 -/** LEDC_DUTY_CHNG_END_CH7_INT_CLR : WT; bitpos: [11]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. - */ -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_M (LEDC_DUTY_CHNG_END_CH7_INT_CLR_V << LEDC_DUTY_CHNG_END_CH7_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_S 11 -/** LEDC_OVF_CNT_CH0_INT_CLR : WT; bitpos: [12]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. - */ -#define LEDC_OVF_CNT_CH0_INT_CLR (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_CLR_M (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S) -#define LEDC_OVF_CNT_CH0_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH0_INT_CLR_S 12 -/** LEDC_OVF_CNT_CH1_INT_CLR : WT; bitpos: [13]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. - */ -#define LEDC_OVF_CNT_CH1_INT_CLR (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_CLR_M (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S) -#define LEDC_OVF_CNT_CH1_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH1_INT_CLR_S 13 -/** LEDC_OVF_CNT_CH2_INT_CLR : WT; bitpos: [14]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. - */ -#define LEDC_OVF_CNT_CH2_INT_CLR (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_CLR_M (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S) -#define LEDC_OVF_CNT_CH2_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH2_INT_CLR_S 14 -/** LEDC_OVF_CNT_CH3_INT_CLR : WT; bitpos: [15]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. - */ -#define LEDC_OVF_CNT_CH3_INT_CLR (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_CLR_M (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S) -#define LEDC_OVF_CNT_CH3_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH3_INT_CLR_S 15 -/** LEDC_OVF_CNT_CH4_INT_CLR : WT; bitpos: [16]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. - */ -#define LEDC_OVF_CNT_CH4_INT_CLR (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_CLR_M (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S) -#define LEDC_OVF_CNT_CH4_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH4_INT_CLR_S 16 -/** LEDC_OVF_CNT_CH5_INT_CLR : WT; bitpos: [17]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. - */ -#define LEDC_OVF_CNT_CH5_INT_CLR (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_CLR_M (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S) -#define LEDC_OVF_CNT_CH5_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH5_INT_CLR_S 17 -/** LEDC_OVF_CNT_CH6_INT_CLR : WT; bitpos: [18]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. - */ -#define LEDC_OVF_CNT_CH6_INT_CLR (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_CLR_M (LEDC_OVF_CNT_CH6_INT_CLR_V << LEDC_OVF_CNT_CH6_INT_CLR_S) -#define LEDC_OVF_CNT_CH6_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH6_INT_CLR_S 18 -/** LEDC_OVF_CNT_CH7_INT_CLR : WT; bitpos: [19]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. - */ -#define LEDC_OVF_CNT_CH7_INT_CLR (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_CLR_M (LEDC_OVF_CNT_CH7_INT_CLR_V << LEDC_OVF_CNT_CH7_INT_CLR_S) -#define LEDC_OVF_CNT_CH7_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH7_INT_CLR_S 19 - -/** LEDC_CH0_GAMMA_CONF_REG register - * Ledc ch0 gamma config register. - */ -#define LEDC_CH0_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x100) -/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch0. - */ -#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) -#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch0. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) -#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH0_GAMMA_PAUSE_S 5 -/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch0. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH0_GAMMA_RESUME (BIT(6)) -#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) -#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH0_GAMMA_RESUME_S 6 - -/** LEDC_CH1_GAMMA_CONF_REG register - * Ledc ch1 gamma config register. - */ -#define LEDC_CH1_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x104) -/** LEDC_CH1_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch1. - */ -#define LEDC_CH1_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH1_GAMMA_ENTRY_NUM_M (LEDC_CH1_GAMMA_ENTRY_NUM_V << LEDC_CH1_GAMMA_ENTRY_NUM_S) -#define LEDC_CH1_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH1_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch1. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH1_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH1_GAMMA_PAUSE_M (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S) -#define LEDC_CH1_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH1_GAMMA_PAUSE_S 5 -/** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch1. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH1_GAMMA_RESUME (BIT(6)) -#define LEDC_CH1_GAMMA_RESUME_M (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S) -#define LEDC_CH1_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH1_GAMMA_RESUME_S 6 - -/** LEDC_CH2_GAMMA_CONF_REG register - * Ledc ch2 gamma config register. - */ -#define LEDC_CH2_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x108) -/** LEDC_CH2_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch2. - */ -#define LEDC_CH2_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH2_GAMMA_ENTRY_NUM_M (LEDC_CH2_GAMMA_ENTRY_NUM_V << LEDC_CH2_GAMMA_ENTRY_NUM_S) -#define LEDC_CH2_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH2_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch2. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH2_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH2_GAMMA_PAUSE_M (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S) -#define LEDC_CH2_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH2_GAMMA_PAUSE_S 5 -/** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch2. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH2_GAMMA_RESUME (BIT(6)) -#define LEDC_CH2_GAMMA_RESUME_M (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S) -#define LEDC_CH2_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH2_GAMMA_RESUME_S 6 - -/** LEDC_CH3_GAMMA_CONF_REG register - * Ledc ch3 gamma config register. - */ -#define LEDC_CH3_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x10c) -/** LEDC_CH3_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch3. - */ -#define LEDC_CH3_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH3_GAMMA_ENTRY_NUM_M (LEDC_CH3_GAMMA_ENTRY_NUM_V << LEDC_CH3_GAMMA_ENTRY_NUM_S) -#define LEDC_CH3_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH3_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch3. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH3_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH3_GAMMA_PAUSE_M (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S) -#define LEDC_CH3_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH3_GAMMA_PAUSE_S 5 -/** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch3. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH3_GAMMA_RESUME (BIT(6)) -#define LEDC_CH3_GAMMA_RESUME_M (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S) -#define LEDC_CH3_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH3_GAMMA_RESUME_S 6 - -/** LEDC_CH4_GAMMA_CONF_REG register - * Ledc ch4 gamma config register. - */ -#define LEDC_CH4_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x110) -/** LEDC_CH4_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch4. - */ -#define LEDC_CH4_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH4_GAMMA_ENTRY_NUM_M (LEDC_CH4_GAMMA_ENTRY_NUM_V << LEDC_CH4_GAMMA_ENTRY_NUM_S) -#define LEDC_CH4_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH4_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch4. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH4_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH4_GAMMA_PAUSE_M (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S) -#define LEDC_CH4_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH4_GAMMA_PAUSE_S 5 -/** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch4. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH4_GAMMA_RESUME (BIT(6)) -#define LEDC_CH4_GAMMA_RESUME_M (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S) -#define LEDC_CH4_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH4_GAMMA_RESUME_S 6 - -/** LEDC_CH5_GAMMA_CONF_REG register - * Ledc ch5 gamma config register. - */ -#define LEDC_CH5_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x114) -/** LEDC_CH5_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch5. - */ -#define LEDC_CH5_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH5_GAMMA_ENTRY_NUM_M (LEDC_CH5_GAMMA_ENTRY_NUM_V << LEDC_CH5_GAMMA_ENTRY_NUM_S) -#define LEDC_CH5_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH5_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch5. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH5_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH5_GAMMA_PAUSE_M (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S) -#define LEDC_CH5_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH5_GAMMA_PAUSE_S 5 -/** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch5. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH5_GAMMA_RESUME (BIT(6)) -#define LEDC_CH5_GAMMA_RESUME_M (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S) -#define LEDC_CH5_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH5_GAMMA_RESUME_S 6 - -/** LEDC_CH6_GAMMA_CONF_REG register - * Ledc ch6 gamma config register. - */ -#define LEDC_CH6_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x118) -/** LEDC_CH6_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch6. - */ -#define LEDC_CH6_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH6_GAMMA_ENTRY_NUM_M (LEDC_CH6_GAMMA_ENTRY_NUM_V << LEDC_CH6_GAMMA_ENTRY_NUM_S) -#define LEDC_CH6_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH6_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH6_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch6. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH6_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH6_GAMMA_PAUSE_M (LEDC_CH6_GAMMA_PAUSE_V << LEDC_CH6_GAMMA_PAUSE_S) -#define LEDC_CH6_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH6_GAMMA_PAUSE_S 5 -/** LEDC_CH6_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch6. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH6_GAMMA_RESUME (BIT(6)) -#define LEDC_CH6_GAMMA_RESUME_M (LEDC_CH6_GAMMA_RESUME_V << LEDC_CH6_GAMMA_RESUME_S) -#define LEDC_CH6_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH6_GAMMA_RESUME_S 6 - -/** LEDC_CH7_GAMMA_CONF_REG register - * Ledc ch7 gamma config register. - */ -#define LEDC_CH7_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x11c) -/** LEDC_CH7_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch7. - */ -#define LEDC_CH7_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH7_GAMMA_ENTRY_NUM_M (LEDC_CH7_GAMMA_ENTRY_NUM_V << LEDC_CH7_GAMMA_ENTRY_NUM_S) -#define LEDC_CH7_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH7_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH7_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch7. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH7_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH7_GAMMA_PAUSE_M (LEDC_CH7_GAMMA_PAUSE_V << LEDC_CH7_GAMMA_PAUSE_S) -#define LEDC_CH7_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH7_GAMMA_PAUSE_S 5 -/** LEDC_CH7_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch7. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH7_GAMMA_RESUME (BIT(6)) -#define LEDC_CH7_GAMMA_RESUME_M (LEDC_CH7_GAMMA_RESUME_V << LEDC_CH7_GAMMA_RESUME_S) -#define LEDC_CH7_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH7_GAMMA_RESUME_S 6 - -/** LEDC_EVT_TASK_EN0_REG register - * Ledc event task enable bit register0. - */ -#define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x120) -/** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH0_EN (BIT(0)) -#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S 0 -/** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH1_EN (BIT(1)) -#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S 1 -/** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH2_EN (BIT(2)) -#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S 2 -/** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH3_EN (BIT(3)) -#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S 3 -/** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH4_EN (BIT(4)) -#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S 4 -/** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH5_EN (BIT(5)) -#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S 5 -/** LEDC_EVT_DUTY_CHNG_END_CH6_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH6_EN (BIT(6)) -#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_M (LEDC_EVT_DUTY_CHNG_END_CH6_EN_V << LEDC_EVT_DUTY_CHNG_END_CH6_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_S 6 -/** LEDC_EVT_DUTY_CHNG_END_CH7_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH7_EN (BIT(7)) -#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_M (LEDC_EVT_DUTY_CHNG_END_CH7_EN_V << LEDC_EVT_DUTY_CHNG_END_CH7_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_S 7 -/** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH0_EN (BIT(8)) -#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S 8 -/** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH1_EN (BIT(9)) -#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S 9 -/** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH2_EN (BIT(10)) -#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S 10 -/** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH3_EN (BIT(11)) -#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S 11 -/** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH4_EN (BIT(12)) -#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S 12 -/** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH5_EN (BIT(13)) -#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S 13 -/** LEDC_EVT_OVF_CNT_PLS_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH6_EN (BIT(14)) -#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_M (LEDC_EVT_OVF_CNT_PLS_CH6_EN_V << LEDC_EVT_OVF_CNT_PLS_CH6_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_S 14 -/** LEDC_EVT_OVF_CNT_PLS_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH7_EN (BIT(15)) -#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_M (LEDC_EVT_OVF_CNT_PLS_CH7_EN_V << LEDC_EVT_OVF_CNT_PLS_CH7_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_S 15 -/** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the ledc_timer0_ovf event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME_OVF_TIMER0_EN (BIT(16)) -#define LEDC_EVT_TIME_OVF_TIMER0_EN_M (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S) -#define LEDC_EVT_TIME_OVF_TIMER0_EN_V 0x00000001U -#define LEDC_EVT_TIME_OVF_TIMER0_EN_S 16 -/** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable the ledc_timer1_ovf event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME_OVF_TIMER1_EN (BIT(17)) -#define LEDC_EVT_TIME_OVF_TIMER1_EN_M (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S) -#define LEDC_EVT_TIME_OVF_TIMER1_EN_V 0x00000001U -#define LEDC_EVT_TIME_OVF_TIMER1_EN_S 17 -/** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable the ledc_timer2_ovf event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME_OVF_TIMER2_EN (BIT(18)) -#define LEDC_EVT_TIME_OVF_TIMER2_EN_M (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S) -#define LEDC_EVT_TIME_OVF_TIMER2_EN_V 0x00000001U -#define LEDC_EVT_TIME_OVF_TIMER2_EN_S 18 -/** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable the ledc_timer3_ovf event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME_OVF_TIMER3_EN (BIT(19)) -#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S) -#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U -#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19 -/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable the ledc_timer0_cmp event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME0_CMP_EN (BIT(20)) -#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S) -#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIME0_CMP_EN_S 20 -/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable the ledc_timer1_cmp event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME1_CMP_EN (BIT(21)) -#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S) -#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIME1_CMP_EN_S 21 -/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable the ledc_timer2_cmp event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME2_CMP_EN (BIT(22)) -#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S) -#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIME2_CMP_EN_S 22 -/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable the ledc_timer3_cmp event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME3_CMP_EN (BIT(23)) -#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S) -#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIME3_CMP_EN_S 23 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN (BIT(24)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S 24 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN (BIT(25)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S 25 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN (BIT(26)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S 26 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN (BIT(27)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S 27 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN (BIT(28)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S 28 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN (BIT(29)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S 29 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN (BIT(30)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S 30 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN (BIT(31)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S 31 - -/** LEDC_EVT_TASK_EN1_REG register - * Ledc event task enable bit register1. - */ -#define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x124) -/** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_timer0_res_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER0_RES_UPDATE_EN (BIT(0)) -#define LEDC_TASK_TIMER0_RES_UPDATE_EN_M (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S) -#define LEDC_TASK_TIMER0_RES_UPDATE_EN_V 0x00000001U -#define LEDC_TASK_TIMER0_RES_UPDATE_EN_S 0 -/** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_timer1_res_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER1_RES_UPDATE_EN (BIT(1)) -#define LEDC_TASK_TIMER1_RES_UPDATE_EN_M (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S) -#define LEDC_TASK_TIMER1_RES_UPDATE_EN_V 0x00000001U -#define LEDC_TASK_TIMER1_RES_UPDATE_EN_S 1 -/** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_timer2_res_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER2_RES_UPDATE_EN (BIT(2)) -#define LEDC_TASK_TIMER2_RES_UPDATE_EN_M (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S) -#define LEDC_TASK_TIMER2_RES_UPDATE_EN_V 0x00000001U -#define LEDC_TASK_TIMER2_RES_UPDATE_EN_S 2 -/** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_timer3_res_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER3_RES_UPDATE_EN (BIT(3)) -#define LEDC_TASK_TIMER3_RES_UPDATE_EN_M (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S) -#define LEDC_TASK_TIMER3_RES_UPDATE_EN_V 0x00000001U -#define LEDC_TASK_TIMER3_RES_UPDATE_EN_S 3 -/** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_timer0_cap task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER0_CAP_EN (BIT(4)) -#define LEDC_TASK_TIMER0_CAP_EN_M (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S) -#define LEDC_TASK_TIMER0_CAP_EN_V 0x00000001U -#define LEDC_TASK_TIMER0_CAP_EN_S 4 -/** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_timer1_cap task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER1_CAP_EN (BIT(5)) -#define LEDC_TASK_TIMER1_CAP_EN_M (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S) -#define LEDC_TASK_TIMER1_CAP_EN_V 0x00000001U -#define LEDC_TASK_TIMER1_CAP_EN_S 5 -/** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_timer2_cap task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER2_CAP_EN (BIT(6)) -#define LEDC_TASK_TIMER2_CAP_EN_M (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S) -#define LEDC_TASK_TIMER2_CAP_EN_V 0x00000001U -#define LEDC_TASK_TIMER2_CAP_EN_S 6 -/** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_timer3_cap task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER3_CAP_EN (BIT(7)) -#define LEDC_TASK_TIMER3_CAP_EN_M (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S) -#define LEDC_TASK_TIMER3_CAP_EN_V 0x00000001U -#define LEDC_TASK_TIMER3_CAP_EN_S 7 -/** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH0_EN (BIT(8)) -#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S 8 -/** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH1_EN (BIT(9)) -#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S 9 -/** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH2_EN (BIT(10)) -#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S 10 -/** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH3_EN (BIT(11)) -#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S 11 -/** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH4_EN (BIT(12)) -#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S 12 -/** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH5_EN (BIT(13)) -#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S 13 -/** LEDC_TASK_SIG_OUT_DIS_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH6_EN (BIT(14)) -#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_M (LEDC_TASK_SIG_OUT_DIS_CH6_EN_V << LEDC_TASK_SIG_OUT_DIS_CH6_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_S 14 -/** LEDC_TASK_SIG_OUT_DIS_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH7_EN (BIT(15)) -#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_M (LEDC_TASK_SIG_OUT_DIS_CH7_EN_V << LEDC_TASK_SIG_OUT_DIS_CH7_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_S 15 -/** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH0_EN (BIT(16)) -#define LEDC_TASK_OVF_CNT_RST_CH0_EN_M (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH0_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH0_EN_S 16 -/** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH1_EN (BIT(17)) -#define LEDC_TASK_OVF_CNT_RST_CH1_EN_M (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH1_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH1_EN_S 17 -/** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH2_EN (BIT(18)) -#define LEDC_TASK_OVF_CNT_RST_CH2_EN_M (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH2_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH2_EN_S 18 -/** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH3_EN (BIT(19)) -#define LEDC_TASK_OVF_CNT_RST_CH3_EN_M (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH3_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH3_EN_S 19 -/** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH4_EN (BIT(20)) -#define LEDC_TASK_OVF_CNT_RST_CH4_EN_M (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH4_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH4_EN_S 20 -/** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH5_EN (BIT(21)) -#define LEDC_TASK_OVF_CNT_RST_CH5_EN_M (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH5_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH5_EN_S 21 -/** LEDC_TASK_OVF_CNT_RST_CH6_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH6_EN (BIT(22)) -#define LEDC_TASK_OVF_CNT_RST_CH6_EN_M (LEDC_TASK_OVF_CNT_RST_CH6_EN_V << LEDC_TASK_OVF_CNT_RST_CH6_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH6_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH6_EN_S 22 -/** LEDC_TASK_OVF_CNT_RST_CH7_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH7_EN (BIT(23)) -#define LEDC_TASK_OVF_CNT_RST_CH7_EN_M (LEDC_TASK_OVF_CNT_RST_CH7_EN_V << LEDC_TASK_OVF_CNT_RST_CH7_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH7_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH7_EN_S 23 -/** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable ledc_timer0_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER0_RST_EN (BIT(24)) -#define LEDC_TASK_TIMER0_RST_EN_M (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S) -#define LEDC_TASK_TIMER0_RST_EN_V 0x00000001U -#define LEDC_TASK_TIMER0_RST_EN_S 24 -/** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable ledc_timer1_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER1_RST_EN (BIT(25)) -#define LEDC_TASK_TIMER1_RST_EN_M (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S) -#define LEDC_TASK_TIMER1_RST_EN_V 0x00000001U -#define LEDC_TASK_TIMER1_RST_EN_S 25 -/** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable ledc_timer2_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER2_RST_EN (BIT(26)) -#define LEDC_TASK_TIMER2_RST_EN_M (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S) -#define LEDC_TASK_TIMER2_RST_EN_V 0x00000001U -#define LEDC_TASK_TIMER2_RST_EN_S 26 -/** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable ledc_timer3_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER3_RST_EN (BIT(27)) -#define LEDC_TASK_TIMER3_RST_EN_M (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S) -#define LEDC_TASK_TIMER3_RST_EN_V 0x00000001U -#define LEDC_TASK_TIMER3_RST_EN_S 27 -/** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable ledc_timer0_pause_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN (BIT(28)) -#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S) -#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V 0x00000001U -#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S 28 -/** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable ledc_timer1_pause_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN (BIT(29)) -#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S) -#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V 0x00000001U -#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S 29 -/** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable ledc_timer2_pause_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN (BIT(30)) -#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S) -#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V 0x00000001U -#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S 30 -/** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable ledc_timer3_pause_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN (BIT(31)) -#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S) -#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V 0x00000001U -#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S 31 - -/** LEDC_EVT_TASK_EN2_REG register - * Ledc event task enable bit register2. - */ -#define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x128) -/** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH0_EN (BIT(0)) -#define LEDC_TASK_GAMMA_RESTART_CH0_EN_M (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH0_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH0_EN_S 0 -/** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH1_EN (BIT(1)) -#define LEDC_TASK_GAMMA_RESTART_CH1_EN_M (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH1_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH1_EN_S 1 -/** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH2_EN (BIT(2)) -#define LEDC_TASK_GAMMA_RESTART_CH2_EN_M (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH2_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH2_EN_S 2 -/** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH3_EN (BIT(3)) -#define LEDC_TASK_GAMMA_RESTART_CH3_EN_M (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH3_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH3_EN_S 3 -/** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH4_EN (BIT(4)) -#define LEDC_TASK_GAMMA_RESTART_CH4_EN_M (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH4_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH4_EN_S 4 -/** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH5_EN (BIT(5)) -#define LEDC_TASK_GAMMA_RESTART_CH5_EN_M (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH5_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH5_EN_S 5 -/** LEDC_TASK_GAMMA_RESTART_CH6_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH6_EN (BIT(6)) -#define LEDC_TASK_GAMMA_RESTART_CH6_EN_M (LEDC_TASK_GAMMA_RESTART_CH6_EN_V << LEDC_TASK_GAMMA_RESTART_CH6_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH6_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH6_EN_S 6 -/** LEDC_TASK_GAMMA_RESTART_CH7_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH7_EN (BIT(7)) -#define LEDC_TASK_GAMMA_RESTART_CH7_EN_M (LEDC_TASK_GAMMA_RESTART_CH7_EN_V << LEDC_TASK_GAMMA_RESTART_CH7_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH7_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH7_EN_S 7 -/** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH0_EN (BIT(8)) -#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S 8 -/** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH1_EN (BIT(9)) -#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S 9 -/** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH2_EN (BIT(10)) -#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S 10 -/** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH3_EN (BIT(11)) -#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S 11 -/** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH4_EN (BIT(12)) -#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S 12 -/** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH5_EN (BIT(13)) -#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S 13 -/** LEDC_TASK_GAMMA_PAUSE_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH6_EN (BIT(14)) -#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_M (LEDC_TASK_GAMMA_PAUSE_CH6_EN_V << LEDC_TASK_GAMMA_PAUSE_CH6_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_S 14 -/** LEDC_TASK_GAMMA_PAUSE_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH7_EN (BIT(15)) -#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_M (LEDC_TASK_GAMMA_PAUSE_CH7_EN_V << LEDC_TASK_GAMMA_PAUSE_CH7_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_S 15 -/** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH0_EN (BIT(16)) -#define LEDC_TASK_GAMMA_RESUME_CH0_EN_M (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH0_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH0_EN_S 16 -/** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH1_EN (BIT(17)) -#define LEDC_TASK_GAMMA_RESUME_CH1_EN_M (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH1_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH1_EN_S 17 -/** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH2_EN (BIT(18)) -#define LEDC_TASK_GAMMA_RESUME_CH2_EN_M (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH2_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH2_EN_S 18 -/** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH3_EN (BIT(19)) -#define LEDC_TASK_GAMMA_RESUME_CH3_EN_M (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH3_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH3_EN_S 19 -/** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH4_EN (BIT(20)) -#define LEDC_TASK_GAMMA_RESUME_CH4_EN_M (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH4_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH4_EN_S 20 -/** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH5_EN (BIT(21)) -#define LEDC_TASK_GAMMA_RESUME_CH5_EN_M (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH5_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH5_EN_S 21 -/** LEDC_TASK_GAMMA_RESUME_CH6_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH6_EN (BIT(22)) -#define LEDC_TASK_GAMMA_RESUME_CH6_EN_M (LEDC_TASK_GAMMA_RESUME_CH6_EN_V << LEDC_TASK_GAMMA_RESUME_CH6_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH6_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH6_EN_S 22 -/** LEDC_TASK_GAMMA_RESUME_CH7_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH7_EN (BIT(23)) -#define LEDC_TASK_GAMMA_RESUME_CH7_EN_M (LEDC_TASK_GAMMA_RESUME_CH7_EN_V << LEDC_TASK_GAMMA_RESUME_CH7_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH7_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH7_EN_S 23 - -/** LEDC_TIMER0_CMP_REG register - * Ledc timer0 compare value register. - */ -#define LEDC_TIMER0_CMP_REG (DR_REG_LEDC_BASE + 0x140) -/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timer0. - */ -#define LEDC_TIMER0_CMP 0x000FFFFFU -#define LEDC_TIMER0_CMP_M (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S) -#define LEDC_TIMER0_CMP_V 0x000FFFFFU -#define LEDC_TIMER0_CMP_S 0 - -/** LEDC_TIMER1_CMP_REG register - * Ledc timer1 compare value register. - */ -#define LEDC_TIMER1_CMP_REG (DR_REG_LEDC_BASE + 0x144) -/** LEDC_TIMER1_CMP : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timer1. - */ -#define LEDC_TIMER1_CMP 0x000FFFFFU -#define LEDC_TIMER1_CMP_M (LEDC_TIMER1_CMP_V << LEDC_TIMER1_CMP_S) -#define LEDC_TIMER1_CMP_V 0x000FFFFFU -#define LEDC_TIMER1_CMP_S 0 - -/** LEDC_TIMER2_CMP_REG register - * Ledc timer2 compare value register. - */ -#define LEDC_TIMER2_CMP_REG (DR_REG_LEDC_BASE + 0x148) -/** LEDC_TIMER2_CMP : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timer2. - */ -#define LEDC_TIMER2_CMP 0x000FFFFFU -#define LEDC_TIMER2_CMP_M (LEDC_TIMER2_CMP_V << LEDC_TIMER2_CMP_S) -#define LEDC_TIMER2_CMP_V 0x000FFFFFU -#define LEDC_TIMER2_CMP_S 0 - -/** LEDC_TIMER3_CMP_REG register - * Ledc timer3 compare value register. - */ -#define LEDC_TIMER3_CMP_REG (DR_REG_LEDC_BASE + 0x14c) -/** LEDC_TIMER3_CMP : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timer3. - */ -#define LEDC_TIMER3_CMP 0x000FFFFFU -#define LEDC_TIMER3_CMP_M (LEDC_TIMER3_CMP_V << LEDC_TIMER3_CMP_S) -#define LEDC_TIMER3_CMP_V 0x000FFFFFU -#define LEDC_TIMER3_CMP_S 0 - -/** LEDC_TIMER0_CNT_CAP_REG register - * Ledc timer0 captured count value register. - */ -#define LEDC_TIMER0_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x150) -/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timer0 count value. - */ -#define LEDC_TIMER0_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER0_CNT_CAP_M (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S) -#define LEDC_TIMER0_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER0_CNT_CAP_S 0 - -/** LEDC_TIMER1_CNT_CAP_REG register - * Ledc timer1 captured count value register. - */ -#define LEDC_TIMER1_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x154) -/** LEDC_TIMER1_CNT_CAP : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timer1 count value. - */ -#define LEDC_TIMER1_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER1_CNT_CAP_M (LEDC_TIMER1_CNT_CAP_V << LEDC_TIMER1_CNT_CAP_S) -#define LEDC_TIMER1_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER1_CNT_CAP_S 0 - -/** LEDC_TIMER2_CNT_CAP_REG register - * Ledc timer2 captured count value register. - */ -#define LEDC_TIMER2_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x158) -/** LEDC_TIMER2_CNT_CAP : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timer2 count value. - */ -#define LEDC_TIMER2_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER2_CNT_CAP_M (LEDC_TIMER2_CNT_CAP_V << LEDC_TIMER2_CNT_CAP_S) -#define LEDC_TIMER2_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER2_CNT_CAP_S 0 - -/** LEDC_TIMER3_CNT_CAP_REG register - * Ledc timer3 captured count value register. - */ -#define LEDC_TIMER3_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x15c) -/** LEDC_TIMER3_CNT_CAP : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timer3 count value. - */ -#define LEDC_TIMER3_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER3_CNT_CAP_M (LEDC_TIMER3_CNT_CAP_V << LEDC_TIMER3_CNT_CAP_S) -#define LEDC_TIMER3_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER3_CNT_CAP_S 0 - -/** LEDC_CONF_REG register - * LEDC global configuration register - */ -#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x170) -/** LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0; - * Configures the clock source for the four timers. - * 0: APB_CLK - * 1: RC_FAST_CLK - * 2: XTAL_CLK - * 3: Invalid. No clock - */ -#define LEDC_APB_CLK_SEL 0x00000003U -#define LEDC_APB_CLK_SEL_M (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S) -#define LEDC_APB_CLK_SEL_V 0x00000003U -#define LEDC_APB_CLK_SEL_S 0 -/** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to open LEDC ch0 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram - * 1: Force open the clock gate for LEDC ch0 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH0 (BIT(2)) -#define LEDC_GAMMA_RAM_CLK_EN_CH0_M (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH0_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH0_S 2 -/** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0; - * Configures whether or not to open LEDC ch1 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram - * 1: Force open the clock gate for LEDC ch1 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH1 (BIT(3)) -#define LEDC_GAMMA_RAM_CLK_EN_CH1_M (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH1_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH1_S 3 -/** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to open LEDC ch2 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram - * 1: Force open the clock gate for LEDC ch2 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH2 (BIT(4)) -#define LEDC_GAMMA_RAM_CLK_EN_CH2_M (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH2_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH2_S 4 -/** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to open LEDC ch3 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram - * 1: Force open the clock gate for LEDC ch3 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH3 (BIT(5)) -#define LEDC_GAMMA_RAM_CLK_EN_CH3_M (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH3_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH3_S 5 -/** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to open LEDC ch4 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram - * 1: Force open the clock gate for LEDC ch4 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH4 (BIT(6)) -#define LEDC_GAMMA_RAM_CLK_EN_CH4_M (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH4_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH4_S 6 -/** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0; - * Configures whether or not to open LEDC ch5 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram - * 1: Force open the clock gate for LEDC ch5 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH5 (BIT(7)) -#define LEDC_GAMMA_RAM_CLK_EN_CH5_M (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH5_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH5_S 7 -/** LEDC_GAMMA_RAM_CLK_EN_CH6 : R/W; bitpos: [8]; default: 0; - * Configures whether or not to open LEDC ch6 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram - * 1: Force open the clock gate for LEDC ch6 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH6 (BIT(8)) -#define LEDC_GAMMA_RAM_CLK_EN_CH6_M (LEDC_GAMMA_RAM_CLK_EN_CH6_V << LEDC_GAMMA_RAM_CLK_EN_CH6_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH6_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH6_S 8 -/** LEDC_GAMMA_RAM_CLK_EN_CH7 : R/W; bitpos: [9]; default: 0; - * Configures whether or not to open LEDC ch7 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram - * 1: Force open the clock gate for LEDC ch7 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH7 (BIT(9)) -#define LEDC_GAMMA_RAM_CLK_EN_CH7_M (LEDC_GAMMA_RAM_CLK_EN_CH7_V << LEDC_GAMMA_RAM_CLK_EN_CH7_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH7_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH7_S 9 -/** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to open register clock gate. - * 0: Open the clock gate only when application writes registers - * 1: Force open the clock gate for register - */ -#define LEDC_CLK_EN (BIT(31)) -#define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) -#define LEDC_CLK_EN_V 0x00000001U -#define LEDC_CLK_EN_S 31 - -/** LEDC_DATE_REG register - * Version control register - */ -#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x174) -/** LEDC_LEDC_DATE : R/W; bitpos: [27:0]; default: 37765152; - * Configures the version. - */ -#define LEDC_LEDC_DATE 0x0FFFFFFFU -#define LEDC_LEDC_DATE_M (LEDC_LEDC_DATE_V << LEDC_LEDC_DATE_S) -#define LEDC_LEDC_DATE_V 0x0FFFFFFFU -#define LEDC_LEDC_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_struct.h deleted file mode 100644 index ef59597ded..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_struct.h +++ /dev/null @@ -1,1359 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Register */ -/** Type of chn_conf0 register - * Configuration register 0 for channel n - */ -typedef union { - struct { - /** timer_sel_chn : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel n selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ - uint32_t timer_sel_chn:2; - /** sig_out_en_chn : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel n. - * 0: Signal output disable - * 1: Signal output enable - */ - uint32_t sig_out_en_chn:1; - /** idle_lv_chn : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel n is inactive. Valid only when - * LEDC_SIG_OUT_EN_CHn is 0. - * 0: Output level is low - * 1: Output level is high - */ - uint32_t idle_lv_chn:1; - /** para_up_chn : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, - * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn, - * LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel - * n, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ - uint32_t para_up_chn:1; - /** ovf_num_chn : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt - * will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times. - */ - uint32_t ovf_num_chn:10; - /** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel n. - * 0: Disable - * 1: Enable - */ - uint32_t ovf_cnt_en_chn:1; - /** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel n. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ - uint32_t ovf_cnt_reset_chn:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} ledc_chn_conf0_reg_t; - -/** Type of chn_hpoint register - * High point register for channel n - */ -typedef union { - struct { - /** hpoint_chn : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel n. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ - uint32_t hpoint_chn:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_chn_hpoint_reg_t; - -/** Type of chn_duty register - * Initial duty cycle register for channel n - */ -typedef union { - struct { - /** duty_chn : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel n. - */ - uint32_t duty_chn:25; - uint32_t reserved_25:7; - }; - uint32_t val; -} ledc_chn_duty_reg_t; - -/** Type of chn_conf1 register - * Configuration register 1 for channel n - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** duty_start_chn : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ - uint32_t duty_start_chn:1; - }; - uint32_t val; -} ledc_chn_conf1_reg_t; - -/** Type of timern_conf register - * Timer n configuration register - */ -typedef union { - struct { - /** timern_duty_res : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer n. - */ - uint32_t timern_duty_res:5; - /** clk_div_timern : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer n.The least significant eight bits - * represent the fractional part. - */ - uint32_t clk_div_timern:18; - /** timern_pause : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer n. - * 0: Normal - * 1: Pause - */ - uint32_t timern_pause:1; - /** timern_rst : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer n. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ - uint32_t timern_rst:1; - uint32_t reserved_25:1; - /** timern_para_up : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMERn and LEDC_TIMERn_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ - uint32_t timern_para_up:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} ledc_timern_conf_reg_t; - -/** Type of chn_gamma_conf register - * Ledc chn gamma config register. - */ -typedef union { - struct { - /** chn_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC chn. - */ - uint32_t chn_gamma_entry_num:5; - /** chn_gamma_pause : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC chn. - * 0: Invalid. No effect - * 1: Pause - */ - uint32_t chn_gamma_pause:1; - /** chn_gamma_resume : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC chn. - * 0: Invalid. No effect - * 1: Resume - */ - uint32_t chn_gamma_resume:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ledc_chn_gamma_conf_reg_t; - -/** Type of evt_task_en0 register - * Ledc event task enable bit register0. - */ -typedef union { - struct { - /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch0_en:1; - /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch1_en:1; - /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch2_en:1; - /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch3_en:1; - /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch4_en:1; - /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch5_en:1; - /** evt_duty_chng_end_ch6_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch6_en:1; - /** evt_duty_chng_end_ch7_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch7_en:1; - /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch0_en:1; - /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch1_en:1; - /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch2_en:1; - /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch3_en:1; - /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch4_en:1; - /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch5_en:1; - /** evt_ovf_cnt_pls_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch6_en:1; - /** evt_ovf_cnt_pls_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch7_en:1; - /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the ledc_timer0_ovf event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time_ovf_timer0_en:1; - /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable the ledc_timer1_ovf event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time_ovf_timer1_en:1; - /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable the ledc_timer2_ovf event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time_ovf_timer2_en:1; - /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable the ledc_timer3_ovf event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time_ovf_timer3_en:1; - /** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable the ledc_timer0_cmp event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time0_cmp_en:1; - /** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable the ledc_timer1_cmp event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time1_cmp_en:1; - /** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable the ledc_timer2_cmp event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time2_cmp_en:1; - /** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable the ledc_timer3_cmp event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time3_cmp_en:1; - /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch0_en:1; - /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch1_en:1; - /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch2_en:1; - /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch3_en:1; - /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch4_en:1; - /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch5_en:1; - /** task_duty_scale_update_ch6_en : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch6_en:1; - /** task_duty_scale_update_ch7_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch7_en:1; - }; - uint32_t val; -} ledc_evt_task_en0_reg_t; - -/** Type of evt_task_en1 register - * Ledc event task enable bit register1. - */ -typedef union { - struct { - /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_timer0_res_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer0_res_update_en:1; - /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_timer1_res_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer1_res_update_en:1; - /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_timer2_res_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer2_res_update_en:1; - /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_timer3_res_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer3_res_update_en:1; - /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_timer0_cap task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer0_cap_en:1; - /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_timer1_cap task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer1_cap_en:1; - /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_timer2_cap task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer2_cap_en:1; - /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_timer3_cap task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer3_cap_en:1; - /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch0_en:1; - /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch1_en:1; - /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch2_en:1; - /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch3_en:1; - /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch4_en:1; - /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch5_en:1; - /** task_sig_out_dis_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch6_en:1; - /** task_sig_out_dis_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch7_en:1; - /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch0_en:1; - /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch1_en:1; - /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch2_en:1; - /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch3_en:1; - /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch4_en:1; - /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch5_en:1; - /** task_ovf_cnt_rst_ch6_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch6_en:1; - /** task_ovf_cnt_rst_ch7_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch7_en:1; - /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable ledc_timer0_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer0_rst_en:1; - /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable ledc_timer1_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer1_rst_en:1; - /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable ledc_timer2_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer2_rst_en:1; - /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable ledc_timer3_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer3_rst_en:1; - /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable ledc_timer0_pause_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer0_pause_resume_en:1; - /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable ledc_timer1_pause_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer1_pause_resume_en:1; - /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable ledc_timer2_pause_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer2_pause_resume_en:1; - /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable ledc_timer3_pause_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer3_pause_resume_en:1; - }; - uint32_t val; -} ledc_evt_task_en1_reg_t; - -/** Type of evt_task_en2 register - * Ledc event task enable bit register2. - */ -typedef union { - struct { - /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch0_en:1; - /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch1_en:1; - /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch2_en:1; - /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch3_en:1; - /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch4_en:1; - /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch5_en:1; - /** task_gamma_restart_ch6_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch6_en:1; - /** task_gamma_restart_ch7_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch7_en:1; - /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch0_en:1; - /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch1_en:1; - /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch2_en:1; - /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch3_en:1; - /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch4_en:1; - /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch5_en:1; - /** task_gamma_pause_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch6_en:1; - /** task_gamma_pause_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch7_en:1; - /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch0_en:1; - /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch1_en:1; - /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch2_en:1; - /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch3_en:1; - /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch4_en:1; - /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch5_en:1; - /** task_gamma_resume_ch6_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch6_en:1; - /** task_gamma_resume_ch7_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch7_en:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} ledc_evt_task_en2_reg_t; - -/** Type of timern_cmp register - * Ledc timern compare value register. - */ -typedef union { - struct { - /** timern_cmp : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timern. - */ - uint32_t timern_cmp:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_timern_cmp_reg_t; - -/** Type of conf register - * LEDC global configuration register - */ -typedef union { - struct { - /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0; - * Configures the clock source for the four timers. - * 0: APB_CLK - * 1: RC_FAST_CLK - * 2: XTAL_CLK - * 3: Invalid. No clock - */ - uint32_t apb_clk_sel:2; - /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to open LEDC ch0 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram - * 1: Force open the clock gate for LEDC ch0 gamma ram - */ - uint32_t gamma_ram_clk_en_ch0:1; - /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; - * Configures whether or not to open LEDC ch1 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram - * 1: Force open the clock gate for LEDC ch1 gamma ram - */ - uint32_t gamma_ram_clk_en_ch1:1; - /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to open LEDC ch2 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram - * 1: Force open the clock gate for LEDC ch2 gamma ram - */ - uint32_t gamma_ram_clk_en_ch2:1; - /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to open LEDC ch3 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram - * 1: Force open the clock gate for LEDC ch3 gamma ram - */ - uint32_t gamma_ram_clk_en_ch3:1; - /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to open LEDC ch4 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram - * 1: Force open the clock gate for LEDC ch4 gamma ram - */ - uint32_t gamma_ram_clk_en_ch4:1; - /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; - * Configures whether or not to open LEDC ch5 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram - * 1: Force open the clock gate for LEDC ch5 gamma ram - */ - uint32_t gamma_ram_clk_en_ch5:1; - /** gamma_ram_clk_en_ch6 : R/W; bitpos: [8]; default: 0; - * Configures whether or not to open LEDC ch6 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram - * 1: Force open the clock gate for LEDC ch6 gamma ram - */ - uint32_t gamma_ram_clk_en_ch6:1; - /** gamma_ram_clk_en_ch7 : R/W; bitpos: [9]; default: 0; - * Configures whether or not to open LEDC ch7 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram - * 1: Force open the clock gate for LEDC ch7 gamma ram - */ - uint32_t gamma_ram_clk_en_ch7:1; - uint32_t reserved_10:21; - /** clk_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to open register clock gate. - * 0: Open the clock gate only when application writes registers - * 1: Force open the clock gate for register - */ - uint32_t clk_en:1; - }; - uint32_t val; -} ledc_conf_reg_t; - - -/** Group: Status Register */ -/** Type of chn_duty_r register - * Current duty cycle register for channel n - */ -typedef union { - struct { - /** duty_chn_r : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel n. - */ - uint32_t duty_chn_r:25; - uint32_t reserved_25:7; - }; - uint32_t val; -} ledc_chn_duty_r_reg_t; - -/** Type of timern_value register - * Timer n current counter value register - */ -typedef union { - struct { - /** timern_cnt : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer n. - */ - uint32_t timern_cnt:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_timern_value_reg_t; - -/** Type of timern_cnt_cap register - * Ledc timern captured count value register. - */ -typedef union { - struct { - /** timern_cnt_cap : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timern count value. - */ - uint32_t timern_cnt_cap:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_timern_cnt_cap_reg_t; - - -/** Group: Interrupt Register */ -/** Type of int_raw register - * Interrupt raw status register - */ -typedef union { - struct { - /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the - * timer0 has reached its maximum counter value. - */ - uint32_t timer0_ovf_int_raw:1; - /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the - * timer1 has reached its maximum counter value. - */ - uint32_t timer1_ovf_int_raw:1; - /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the - * timer2 has reached its maximum counter value. - */ - uint32_t timer2_ovf_int_raw:1; - /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the - * timer3 has reached its maximum counter value. - */ - uint32_t timer3_ovf_int_raw:1; - /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch0_int_raw:1; - /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch1_int_raw:1; - /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch2_int_raw:1; - /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch3_int_raw:1; - /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch4_int_raw:1; - /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch5_int_raw:1; - /** duty_chng_end_ch6_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch6_int_raw:1; - /** duty_chng_end_ch7_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch7_int_raw:1; - /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. - */ - uint32_t ovf_cnt_ch0_int_raw:1; - /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. - */ - uint32_t ovf_cnt_ch1_int_raw:1; - /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. - */ - uint32_t ovf_cnt_ch2_int_raw:1; - /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. - */ - uint32_t ovf_cnt_ch3_int_raw:1; - /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. - */ - uint32_t ovf_cnt_ch4_int_raw:1; - /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. - */ - uint32_t ovf_cnt_ch5_int_raw:1; - /** ovf_cnt_ch6_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. - */ - uint32_t ovf_cnt_ch6_int_raw:1; - /** ovf_cnt_ch7_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. - */ - uint32_t ovf_cnt_ch7_int_raw:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_int_raw_reg_t; - -/** Type of int_st register - * Interrupt masked status register - */ -typedef union { - struct { - /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only - * when LEDC_TIMER0_OVF_INT_ENA is set to 1. - */ - uint32_t timer0_ovf_int_st:1; - /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only - * when LEDC_TIMER1_OVF_INT_ENA is set to 1. - */ - uint32_t timer1_ovf_int_st:1; - /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only - * when LEDC_TIMER2_OVF_INT_ENA is set to 1. - */ - uint32_t timer2_ovf_int_st:1; - /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only - * when LEDC_TIMER3_OVF_INT_ENA is set to 1. - */ - uint32_t timer3_ovf_int_st:1; - /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch0_int_st:1; - /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch1_int_st:1; - /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch2_int_st:1; - /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch3_int_st:1; - /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch4_int_st:1; - /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch5_int_st:1; - /** duty_chng_end_ch6_int_st : RO; bitpos: [10]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch6_int_st:1; - /** duty_chng_end_ch7_int_st : RO; bitpos: [11]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch7_int_st:1; - /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only - * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch0_int_st:1; - /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only - * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch1_int_st:1; - /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only - * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch2_int_st:1; - /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only - * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch3_int_st:1; - /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only - * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch4_int_st:1; - /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only - * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch5_int_st:1; - /** ovf_cnt_ch6_int_st : RO; bitpos: [18]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only - * when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch6_int_st:1; - /** ovf_cnt_ch7_int_st : RO; bitpos: [19]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only - * when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch7_int_st:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_int_st_reg_t; - -/** Type of int_ena register - * Interrupt enable register - */ -typedef union { - struct { - /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. - */ - uint32_t timer0_ovf_int_ena:1; - /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. - */ - uint32_t timer1_ovf_int_ena:1; - /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. - */ - uint32_t timer2_ovf_int_ena:1; - /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. - */ - uint32_t timer3_ovf_int_ena:1; - /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. - */ - uint32_t duty_chng_end_ch0_int_ena:1; - /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. - */ - uint32_t duty_chng_end_ch1_int_ena:1; - /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. - */ - uint32_t duty_chng_end_ch2_int_ena:1; - /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. - */ - uint32_t duty_chng_end_ch3_int_ena:1; - /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. - */ - uint32_t duty_chng_end_ch4_int_ena:1; - /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. - */ - uint32_t duty_chng_end_ch5_int_ena:1; - /** duty_chng_end_ch6_int_ena : R/W; bitpos: [10]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. - */ - uint32_t duty_chng_end_ch6_int_ena:1; - /** duty_chng_end_ch7_int_ena : R/W; bitpos: [11]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. - */ - uint32_t duty_chng_end_ch7_int_ena:1; - /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. - */ - uint32_t ovf_cnt_ch0_int_ena:1; - /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. - */ - uint32_t ovf_cnt_ch1_int_ena:1; - /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. - */ - uint32_t ovf_cnt_ch2_int_ena:1; - /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. - */ - uint32_t ovf_cnt_ch3_int_ena:1; - /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. - */ - uint32_t ovf_cnt_ch4_int_ena:1; - /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. - */ - uint32_t ovf_cnt_ch5_int_ena:1; - /** ovf_cnt_ch6_int_ena : R/W; bitpos: [18]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. - */ - uint32_t ovf_cnt_ch6_int_ena:1; - /** ovf_cnt_ch7_int_ena : R/W; bitpos: [19]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. - */ - uint32_t ovf_cnt_ch7_int_ena:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_int_ena_reg_t; - -/** Type of int_clr register - * Interrupt clear register - */ -typedef union { - struct { - /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. - */ - uint32_t timer0_ovf_int_clr:1; - /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. - */ - uint32_t timer1_ovf_int_clr:1; - /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. - */ - uint32_t timer2_ovf_int_clr:1; - /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. - */ - uint32_t timer3_ovf_int_clr:1; - /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. - */ - uint32_t duty_chng_end_ch0_int_clr:1; - /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. - */ - uint32_t duty_chng_end_ch1_int_clr:1; - /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. - */ - uint32_t duty_chng_end_ch2_int_clr:1; - /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. - */ - uint32_t duty_chng_end_ch3_int_clr:1; - /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. - */ - uint32_t duty_chng_end_ch4_int_clr:1; - /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. - */ - uint32_t duty_chng_end_ch5_int_clr:1; - /** duty_chng_end_ch6_int_clr : WT; bitpos: [10]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. - */ - uint32_t duty_chng_end_ch6_int_clr:1; - /** duty_chng_end_ch7_int_clr : WT; bitpos: [11]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. - */ - uint32_t duty_chng_end_ch7_int_clr:1; - /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. - */ - uint32_t ovf_cnt_ch0_int_clr:1; - /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. - */ - uint32_t ovf_cnt_ch1_int_clr:1; - /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. - */ - uint32_t ovf_cnt_ch2_int_clr:1; - /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. - */ - uint32_t ovf_cnt_ch3_int_clr:1; - /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. - */ - uint32_t ovf_cnt_ch4_int_clr:1; - /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. - */ - uint32_t ovf_cnt_ch5_int_clr:1; - /** ovf_cnt_ch6_int_clr : WT; bitpos: [18]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. - */ - uint32_t ovf_cnt_ch6_int_clr:1; - /** ovf_cnt_ch7_int_clr : WT; bitpos: [19]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. - */ - uint32_t ovf_cnt_ch7_int_clr:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_int_clr_reg_t; - - -/** Group: Version Register */ -/** Type of date register - * Version control register - */ -typedef union { - struct { - /** ledc_date : R/W; bitpos: [27:0]; default: 37765152; - * Configures the version. - */ - uint32_t ledc_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} ledc_date_reg_t; - - -typedef struct { - volatile ledc_chn_conf0_reg_t ch0_conf0; - volatile ledc_chn_hpoint_reg_t ch0_hpoint; - volatile ledc_chn_duty_reg_t ch0_duty; - volatile ledc_chn_conf1_reg_t ch0_conf1; - volatile ledc_chn_duty_r_reg_t ch0_duty_r; - volatile ledc_chn_conf0_reg_t ch1_conf0; - volatile ledc_chn_hpoint_reg_t ch1_hpoint; - volatile ledc_chn_duty_reg_t ch1_duty; - volatile ledc_chn_conf1_reg_t ch1_conf1; - volatile ledc_chn_duty_r_reg_t ch1_duty_r; - volatile ledc_chn_conf0_reg_t ch2_conf0; - volatile ledc_chn_hpoint_reg_t ch2_hpoint; - volatile ledc_chn_duty_reg_t ch2_duty; - volatile ledc_chn_conf1_reg_t ch2_conf1; - volatile ledc_chn_duty_r_reg_t ch2_duty_r; - volatile ledc_chn_conf0_reg_t ch3_conf0; - volatile ledc_chn_hpoint_reg_t ch3_hpoint; - volatile ledc_chn_duty_reg_t ch3_duty; - volatile ledc_chn_conf1_reg_t ch3_conf1; - volatile ledc_chn_duty_r_reg_t ch3_duty_r; - volatile ledc_chn_conf0_reg_t ch4_conf0; - volatile ledc_chn_hpoint_reg_t ch4_hpoint; - volatile ledc_chn_duty_reg_t ch4_duty; - volatile ledc_chn_conf1_reg_t ch4_conf1; - volatile ledc_chn_duty_r_reg_t ch4_duty_r; - volatile ledc_chn_conf0_reg_t ch5_conf0; - volatile ledc_chn_hpoint_reg_t ch5_hpoint; - volatile ledc_chn_duty_reg_t ch5_duty; - volatile ledc_chn_conf1_reg_t ch5_conf1; - volatile ledc_chn_duty_r_reg_t ch5_duty_r; - volatile ledc_chn_conf0_reg_t ch6_conf0; - volatile ledc_chn_hpoint_reg_t ch6_hpoint; - volatile ledc_chn_duty_reg_t ch6_duty; - volatile ledc_chn_conf1_reg_t ch6_conf1; - volatile ledc_chn_duty_r_reg_t ch6_duty_r; - volatile ledc_chn_conf0_reg_t ch7_conf0; - volatile ledc_chn_hpoint_reg_t ch7_hpoint; - volatile ledc_chn_duty_reg_t ch7_duty; - volatile ledc_chn_conf1_reg_t ch7_conf1; - volatile ledc_chn_duty_r_reg_t ch7_duty_r; - volatile ledc_timern_conf_reg_t timer0_conf; - volatile ledc_timern_value_reg_t timer0_value; - volatile ledc_timern_conf_reg_t timer1_conf; - volatile ledc_timern_value_reg_t timer1_value; - volatile ledc_timern_conf_reg_t timer2_conf; - volatile ledc_timern_value_reg_t timer2_value; - volatile ledc_timern_conf_reg_t timer3_conf; - volatile ledc_timern_value_reg_t timer3_value; - volatile ledc_int_raw_reg_t int_raw; - volatile ledc_int_st_reg_t int_st; - volatile ledc_int_ena_reg_t int_ena; - volatile ledc_int_clr_reg_t int_clr; - uint32_t reserved_0d0[12]; - volatile ledc_chn_gamma_conf_reg_t chn_gamma_conf[8]; - volatile ledc_evt_task_en0_reg_t evt_task_en0; - volatile ledc_evt_task_en1_reg_t evt_task_en1; - volatile ledc_evt_task_en2_reg_t evt_task_en2; - uint32_t reserved_12c[5]; - volatile ledc_timern_cmp_reg_t timern_cmp[4]; - volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4]; - uint32_t reserved_160[4]; - volatile ledc_conf_reg_t conf; - volatile ledc_date_reg_t date; -} ledc_dev_t; - -extern ledc_dev_t LEDC; - -#ifndef __cplusplus -_Static_assert(sizeof(ledc_dev_t) == 0x178, "Invalid size of ledc_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h index 05d7e02bbc..6599e1dab0 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h @@ -16,16 +16,20 @@ extern "C" { */ #define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) /** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 0 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 0 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH0 0x00000003U #define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) #define LEDC_TIMER_SEL_CH0_V 0x00000003U #define LEDC_TIMER_SEL_CH0_S 0 /** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 0.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 0. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH0 (BIT(2)) #define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) @@ -33,7 +37,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH0_S 2 /** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 0 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH0 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH0 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH0 (BIT(3)) #define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) @@ -43,7 +49,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0, * LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0, * LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel - * 0, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 0, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH0 (BIT(4)) #define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) @@ -58,15 +66,18 @@ extern "C" { #define LEDC_OVF_NUM_CH0_V 0x000003FFU #define LEDC_OVF_NUM_CH0_S 5 /** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 0.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 0. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH0 (BIT(15)) #define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) #define LEDC_OVF_CNT_EN_CH0_V 0x00000001U #define LEDC_OVF_CNT_EN_CH0_S 15 /** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 0.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 0. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) @@ -103,8 +114,9 @@ extern "C" { */ #define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) /** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH0 (BIT(31)) #define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) @@ -128,16 +140,20 @@ extern "C" { */ #define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) /** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 1 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 1 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH1 0x00000003U #define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) #define LEDC_TIMER_SEL_CH1_V 0x00000003U #define LEDC_TIMER_SEL_CH1_S 0 /** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 1.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 1. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH1 (BIT(2)) #define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) @@ -145,7 +161,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH1_S 2 /** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 1 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH1 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH1 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH1 (BIT(3)) #define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) @@ -155,7 +173,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1, * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1, * LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel - * 1, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 1, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH1 (BIT(4)) #define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) @@ -170,15 +190,18 @@ extern "C" { #define LEDC_OVF_NUM_CH1_V 0x000003FFU #define LEDC_OVF_NUM_CH1_S 5 /** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 1.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 1. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH1 (BIT(15)) #define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) #define LEDC_OVF_CNT_EN_CH1_V 0x00000001U #define LEDC_OVF_CNT_EN_CH1_S 15 /** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 1.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 1. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) @@ -215,8 +238,9 @@ extern "C" { */ #define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) /** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH1 (BIT(31)) #define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) @@ -240,16 +264,20 @@ extern "C" { */ #define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) /** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 2 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 2 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH2 0x00000003U #define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) #define LEDC_TIMER_SEL_CH2_V 0x00000003U #define LEDC_TIMER_SEL_CH2_S 0 /** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 2.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 2. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH2 (BIT(2)) #define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) @@ -257,7 +285,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH2_S 2 /** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 2 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH2 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH2 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH2 (BIT(3)) #define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) @@ -267,7 +297,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2, * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2, * LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel - * 2, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 2, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH2 (BIT(4)) #define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) @@ -282,15 +314,18 @@ extern "C" { #define LEDC_OVF_NUM_CH2_V 0x000003FFU #define LEDC_OVF_NUM_CH2_S 5 /** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 2.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 2. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH2 (BIT(15)) #define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) #define LEDC_OVF_CNT_EN_CH2_V 0x00000001U #define LEDC_OVF_CNT_EN_CH2_S 15 /** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 2.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 2. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) @@ -327,8 +362,9 @@ extern "C" { */ #define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) /** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH2 (BIT(31)) #define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) @@ -352,16 +388,20 @@ extern "C" { */ #define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) /** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 3 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 3 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH3 0x00000003U #define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) #define LEDC_TIMER_SEL_CH3_V 0x00000003U #define LEDC_TIMER_SEL_CH3_S 0 /** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 3.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 3. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH3 (BIT(2)) #define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) @@ -369,7 +409,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH3_S 2 /** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 3 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH3 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH3 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH3 (BIT(3)) #define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) @@ -379,7 +421,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3, * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3, * LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel - * 3, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 3, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH3 (BIT(4)) #define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) @@ -394,15 +438,18 @@ extern "C" { #define LEDC_OVF_NUM_CH3_V 0x000003FFU #define LEDC_OVF_NUM_CH3_S 5 /** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 3.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 3. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH3 (BIT(15)) #define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) #define LEDC_OVF_CNT_EN_CH3_V 0x00000001U #define LEDC_OVF_CNT_EN_CH3_S 15 /** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 3.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 3. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) @@ -439,8 +486,9 @@ extern "C" { */ #define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) /** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH3 (BIT(31)) #define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) @@ -464,16 +512,20 @@ extern "C" { */ #define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) /** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 4 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 4 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH4 0x00000003U #define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) #define LEDC_TIMER_SEL_CH4_V 0x00000003U #define LEDC_TIMER_SEL_CH4_S 0 /** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 4.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 4. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH4 (BIT(2)) #define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) @@ -481,7 +533,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH4_S 2 /** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 4 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH4 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH4 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH4 (BIT(3)) #define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) @@ -491,7 +545,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4, * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4, * LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel - * 4, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 4, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH4 (BIT(4)) #define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) @@ -506,15 +562,18 @@ extern "C" { #define LEDC_OVF_NUM_CH4_V 0x000003FFU #define LEDC_OVF_NUM_CH4_S 5 /** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 4.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 4. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH4 (BIT(15)) #define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) #define LEDC_OVF_CNT_EN_CH4_V 0x00000001U #define LEDC_OVF_CNT_EN_CH4_S 15 /** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 4.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 4. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) @@ -551,8 +610,9 @@ extern "C" { */ #define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) /** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH4 (BIT(31)) #define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) @@ -576,16 +636,20 @@ extern "C" { */ #define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) /** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 5 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 5 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH5 0x00000003U #define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) #define LEDC_TIMER_SEL_CH5_V 0x00000003U #define LEDC_TIMER_SEL_CH5_S 0 /** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 5.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 5. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH5 (BIT(2)) #define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) @@ -593,7 +657,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH5_S 2 /** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 5 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH5 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH5 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH5 (BIT(3)) #define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) @@ -603,7 +669,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5, * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5, * LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel - * 5, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 5, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH5 (BIT(4)) #define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) @@ -618,15 +686,18 @@ extern "C" { #define LEDC_OVF_NUM_CH5_V 0x000003FFU #define LEDC_OVF_NUM_CH5_S 5 /** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 5.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 5. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH5 (BIT(15)) #define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) #define LEDC_OVF_CNT_EN_CH5_V 0x00000001U #define LEDC_OVF_CNT_EN_CH5_S 15 /** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 5.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 5. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) @@ -663,8 +734,9 @@ extern "C" { */ #define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) /** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH5 (BIT(31)) #define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) @@ -688,16 +760,20 @@ extern "C" { */ #define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78) /** LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 6 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 6 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH6 0x00000003U #define LEDC_TIMER_SEL_CH6_M (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S) #define LEDC_TIMER_SEL_CH6_V 0x00000003U #define LEDC_TIMER_SEL_CH6_S 0 /** LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 6.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 6. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH6 (BIT(2)) #define LEDC_SIG_OUT_EN_CH6_M (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S) @@ -705,7 +781,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH6_S 2 /** LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 6 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH6 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH6 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH6 (BIT(3)) #define LEDC_IDLE_LV_CH6_M (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S) @@ -715,7 +793,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH6, LEDC_DUTY_START_CH6, * LEDC_SIG_OUT_EN_CH6, LEDC_TIMER_SEL_CH6, LEDC_DUTY_NUM_CH6, LEDC_DUTY_CYCLE_CH6, * LEDC_DUTY_SCALE_CH6, LEDC_DUTY_INC_CH6, and LEDC_OVF_CNT_EN_CH6 fields for channel - * 6, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 6, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH6 (BIT(4)) #define LEDC_PARA_UP_CH6_M (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S) @@ -730,15 +810,18 @@ extern "C" { #define LEDC_OVF_NUM_CH6_V 0x000003FFU #define LEDC_OVF_NUM_CH6_S 5 /** LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 6.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 6. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH6 (BIT(15)) #define LEDC_OVF_CNT_EN_CH6_M (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S) #define LEDC_OVF_CNT_EN_CH6_V 0x00000001U #define LEDC_OVF_CNT_EN_CH6_S 15 /** LEDC_OVF_CNT_RESET_CH6 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 6.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 6. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH6 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH6_M (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S) @@ -775,8 +858,9 @@ extern "C" { */ #define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84) /** LEDC_DUTY_START_CH6 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH6 (BIT(31)) #define LEDC_DUTY_START_CH6_M (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S) @@ -800,16 +884,20 @@ extern "C" { */ #define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c) /** LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 7 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 7 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH7 0x00000003U #define LEDC_TIMER_SEL_CH7_M (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S) #define LEDC_TIMER_SEL_CH7_V 0x00000003U #define LEDC_TIMER_SEL_CH7_S 0 /** LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 7.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 7. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH7 (BIT(2)) #define LEDC_SIG_OUT_EN_CH7_M (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S) @@ -817,7 +905,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH7_S 2 /** LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 7 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH7 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH7 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH7 (BIT(3)) #define LEDC_IDLE_LV_CH7_M (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S) @@ -827,7 +917,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH7, LEDC_DUTY_START_CH7, * LEDC_SIG_OUT_EN_CH7, LEDC_TIMER_SEL_CH7, LEDC_DUTY_NUM_CH7, LEDC_DUTY_CYCLE_CH7, * LEDC_DUTY_SCALE_CH7, LEDC_DUTY_INC_CH7, and LEDC_OVF_CNT_EN_CH7 fields for channel - * 7, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 7, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH7 (BIT(4)) #define LEDC_PARA_UP_CH7_M (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S) @@ -842,15 +934,18 @@ extern "C" { #define LEDC_OVF_NUM_CH7_V 0x000003FFU #define LEDC_OVF_NUM_CH7_S 5 /** LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 7.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 7. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH7 (BIT(15)) #define LEDC_OVF_CNT_EN_CH7_M (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S) #define LEDC_OVF_CNT_EN_CH7_V 0x00000001U #define LEDC_OVF_CNT_EN_CH7_S 15 /** LEDC_OVF_CNT_RESET_CH7 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 7.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 7. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH7 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH7_M (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S) @@ -887,8 +982,9 @@ extern "C" { */ #define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98) /** LEDC_DUTY_START_CH7 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH7 (BIT(31)) #define LEDC_DUTY_START_CH7_M (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S) @@ -927,30 +1023,27 @@ extern "C" { #define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU #define LEDC_CLK_DIV_TIMER0_S 5 /** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 0.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer 0. + * 0: Normal + * 1: Pause */ #define LEDC_TIMER0_PAUSE (BIT(23)) #define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) #define LEDC_TIMER0_PAUSE_V 0x00000001U #define LEDC_TIMER0_PAUSE_S 23 /** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 0. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer 0. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ #define LEDC_TIMER0_RST (BIT(24)) #define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) #define LEDC_TIMER0_RST_V 0x00000001U #define LEDC_TIMER0_RST_S 24 -/** LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer 0 selected. Unused. - */ -#define LEDC_TICK_SEL_TIMER0 (BIT(25)) -#define LEDC_TICK_SEL_TIMER0_M (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S) -#define LEDC_TICK_SEL_TIMER0_V 0x00000001U -#define LEDC_TICK_SEL_TIMER0_S 25 /** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER0 and - * LEDC_TIMER0_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMER0 and LEDC_TIMER0_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_TIMER0_PARA_UP (BIT(26)) #define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) @@ -989,30 +1082,27 @@ extern "C" { #define LEDC_CLK_DIV_TIMER1_V 0x0003FFFFU #define LEDC_CLK_DIV_TIMER1_S 5 /** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 1.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer 1. + * 0: Normal + * 1: Pause */ #define LEDC_TIMER1_PAUSE (BIT(23)) #define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) #define LEDC_TIMER1_PAUSE_V 0x00000001U #define LEDC_TIMER1_PAUSE_S 23 /** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 1. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer 1. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ #define LEDC_TIMER1_RST (BIT(24)) #define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) #define LEDC_TIMER1_RST_V 0x00000001U #define LEDC_TIMER1_RST_S 24 -/** LEDC_TICK_SEL_TIMER1 : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer 1 selected. Unused. - */ -#define LEDC_TICK_SEL_TIMER1 (BIT(25)) -#define LEDC_TICK_SEL_TIMER1_M (LEDC_TICK_SEL_TIMER1_V << LEDC_TICK_SEL_TIMER1_S) -#define LEDC_TICK_SEL_TIMER1_V 0x00000001U -#define LEDC_TICK_SEL_TIMER1_S 25 /** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and - * LEDC_TIMER1_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and LEDC_TIMER1_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_TIMER1_PARA_UP (BIT(26)) #define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) @@ -1051,30 +1141,27 @@ extern "C" { #define LEDC_CLK_DIV_TIMER2_V 0x0003FFFFU #define LEDC_CLK_DIV_TIMER2_S 5 /** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 2.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer 2. + * 0: Normal + * 1: Pause */ #define LEDC_TIMER2_PAUSE (BIT(23)) #define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) #define LEDC_TIMER2_PAUSE_V 0x00000001U #define LEDC_TIMER2_PAUSE_S 23 /** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 2. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer 2. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ #define LEDC_TIMER2_RST (BIT(24)) #define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) #define LEDC_TIMER2_RST_V 0x00000001U #define LEDC_TIMER2_RST_S 24 -/** LEDC_TICK_SEL_TIMER2 : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer 2 selected. Unused. - */ -#define LEDC_TICK_SEL_TIMER2 (BIT(25)) -#define LEDC_TICK_SEL_TIMER2_M (LEDC_TICK_SEL_TIMER2_V << LEDC_TICK_SEL_TIMER2_S) -#define LEDC_TICK_SEL_TIMER2_V 0x00000001U -#define LEDC_TICK_SEL_TIMER2_S 25 /** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and - * LEDC_TIMER2_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and LEDC_TIMER2_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_TIMER2_PARA_UP (BIT(26)) #define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) @@ -1113,30 +1200,27 @@ extern "C" { #define LEDC_CLK_DIV_TIMER3_V 0x0003FFFFU #define LEDC_CLK_DIV_TIMER3_S 5 /** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 3.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer 3. + * 0: Normal + * 1: Pause */ #define LEDC_TIMER3_PAUSE (BIT(23)) #define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) #define LEDC_TIMER3_PAUSE_V 0x00000001U #define LEDC_TIMER3_PAUSE_S 23 /** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 3. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer 3. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ #define LEDC_TIMER3_RST (BIT(24)) #define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) #define LEDC_TIMER3_RST_V 0x00000001U #define LEDC_TIMER3_RST_S 24 -/** LEDC_TICK_SEL_TIMER3 : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer 3 selected. Unused. - */ -#define LEDC_TICK_SEL_TIMER3 (BIT(25)) -#define LEDC_TICK_SEL_TIMER3_M (LEDC_TICK_SEL_TIMER3_V << LEDC_TICK_SEL_TIMER3_S) -#define LEDC_TICK_SEL_TIMER3_V 0x00000001U -#define LEDC_TICK_SEL_TIMER3_S 25 /** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and - * LEDC_TIMER3_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and LEDC_TIMER3_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_TIMER3_PARA_UP (BIT(26)) #define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) @@ -1787,16 +1871,18 @@ extern "C" { #define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch0.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch0. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH0_GAMMA_PAUSE (BIT(5)) #define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) #define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH0_GAMMA_PAUSE_S 5 /** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch0.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch0. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH0_GAMMA_RESUME (BIT(6)) #define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) @@ -1815,16 +1901,18 @@ extern "C" { #define LEDC_CH1_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH1_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch1.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch1. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH1_GAMMA_PAUSE (BIT(5)) #define LEDC_CH1_GAMMA_PAUSE_M (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S) #define LEDC_CH1_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH1_GAMMA_PAUSE_S 5 /** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch1.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch1. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH1_GAMMA_RESUME (BIT(6)) #define LEDC_CH1_GAMMA_RESUME_M (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S) @@ -1843,16 +1931,18 @@ extern "C" { #define LEDC_CH2_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH2_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch2.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch2. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH2_GAMMA_PAUSE (BIT(5)) #define LEDC_CH2_GAMMA_PAUSE_M (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S) #define LEDC_CH2_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH2_GAMMA_PAUSE_S 5 /** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch2.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch2. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH2_GAMMA_RESUME (BIT(6)) #define LEDC_CH2_GAMMA_RESUME_M (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S) @@ -1871,16 +1961,18 @@ extern "C" { #define LEDC_CH3_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH3_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch3.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch3. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH3_GAMMA_PAUSE (BIT(5)) #define LEDC_CH3_GAMMA_PAUSE_M (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S) #define LEDC_CH3_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH3_GAMMA_PAUSE_S 5 /** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch3.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch3. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH3_GAMMA_RESUME (BIT(6)) #define LEDC_CH3_GAMMA_RESUME_M (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S) @@ -1899,16 +1991,18 @@ extern "C" { #define LEDC_CH4_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH4_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch4.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch4. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH4_GAMMA_PAUSE (BIT(5)) #define LEDC_CH4_GAMMA_PAUSE_M (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S) #define LEDC_CH4_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH4_GAMMA_PAUSE_S 5 /** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch4.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch4. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH4_GAMMA_RESUME (BIT(6)) #define LEDC_CH4_GAMMA_RESUME_M (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S) @@ -1927,16 +2021,18 @@ extern "C" { #define LEDC_CH5_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH5_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch5.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch5. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH5_GAMMA_PAUSE (BIT(5)) #define LEDC_CH5_GAMMA_PAUSE_M (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S) #define LEDC_CH5_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH5_GAMMA_PAUSE_S 5 /** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch5.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch5. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH5_GAMMA_RESUME (BIT(6)) #define LEDC_CH5_GAMMA_RESUME_M (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S) @@ -1955,16 +2051,18 @@ extern "C" { #define LEDC_CH6_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH6_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH6_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch6.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch6. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH6_GAMMA_PAUSE (BIT(5)) #define LEDC_CH6_GAMMA_PAUSE_M (LEDC_CH6_GAMMA_PAUSE_V << LEDC_CH6_GAMMA_PAUSE_S) #define LEDC_CH6_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH6_GAMMA_PAUSE_S 5 /** LEDC_CH6_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch6.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch6. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH6_GAMMA_RESUME (BIT(6)) #define LEDC_CH6_GAMMA_RESUME_M (LEDC_CH6_GAMMA_RESUME_V << LEDC_CH6_GAMMA_RESUME_S) @@ -1983,16 +2081,18 @@ extern "C" { #define LEDC_CH7_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH7_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH7_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch7.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch7. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH7_GAMMA_PAUSE (BIT(5)) #define LEDC_CH7_GAMMA_PAUSE_M (LEDC_CH7_GAMMA_PAUSE_V << LEDC_CH7_GAMMA_PAUSE_S) #define LEDC_CH7_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH7_GAMMA_PAUSE_S 5 /** LEDC_CH7_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch7.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch7. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH7_GAMMA_RESUME (BIT(6)) #define LEDC_CH7_GAMMA_RESUME_M (LEDC_CH7_GAMMA_RESUME_V << LEDC_CH7_GAMMA_RESUME_S) @@ -2004,256 +2104,288 @@ extern "C" { */ #define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x120) /** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch0_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH0_EN (BIT(0)) #define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S 0 /** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch1_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH1_EN (BIT(1)) #define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S 1 /** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch2_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH2_EN (BIT(2)) #define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S 2 /** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch3_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH3_EN (BIT(3)) #define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S 3 /** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch4_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH4_EN (BIT(4)) #define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S 4 /** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch5_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH5_EN (BIT(5)) #define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S 5 /** LEDC_EVT_DUTY_CHNG_END_CH6_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch6_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH6_EN (BIT(6)) #define LEDC_EVT_DUTY_CHNG_END_CH6_EN_M (LEDC_EVT_DUTY_CHNG_END_CH6_EN_V << LEDC_EVT_DUTY_CHNG_END_CH6_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH6_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH6_EN_S 6 /** LEDC_EVT_DUTY_CHNG_END_CH7_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch7_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH7_EN (BIT(7)) #define LEDC_EVT_DUTY_CHNG_END_CH7_EN_M (LEDC_EVT_DUTY_CHNG_END_CH7_EN_V << LEDC_EVT_DUTY_CHNG_END_CH7_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH7_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH7_EN_S 7 /** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH0_EN (BIT(8)) #define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S 8 /** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH1_EN (BIT(9)) #define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S 9 /** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH2_EN (BIT(10)) #define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S 10 /** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH3_EN (BIT(11)) #define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S 11 /** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH4_EN (BIT(12)) #define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S 12 /** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH5_EN (BIT(13)) #define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S 13 /** LEDC_EVT_OVF_CNT_PLS_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH6_EN (BIT(14)) #define LEDC_EVT_OVF_CNT_PLS_CH6_EN_M (LEDC_EVT_OVF_CNT_PLS_CH6_EN_V << LEDC_EVT_OVF_CNT_PLS_CH6_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH6_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH6_EN_S 14 /** LEDC_EVT_OVF_CNT_PLS_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH7_EN (BIT(15)) #define LEDC_EVT_OVF_CNT_PLS_CH7_EN_M (LEDC_EVT_OVF_CNT_PLS_CH7_EN_V << LEDC_EVT_OVF_CNT_PLS_CH7_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH7_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH7_EN_S 15 /** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_timer0_ovf event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_TIME_OVF_TIMER0_EN (BIT(16)) #define LEDC_EVT_TIME_OVF_TIMER0_EN_M (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S) #define LEDC_EVT_TIME_OVF_TIMER0_EN_V 0x00000001U #define LEDC_EVT_TIME_OVF_TIMER0_EN_S 16 /** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_timer1_ovf event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_TIME_OVF_TIMER1_EN (BIT(17)) #define LEDC_EVT_TIME_OVF_TIMER1_EN_M (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S) #define LEDC_EVT_TIME_OVF_TIMER1_EN_V 0x00000001U #define LEDC_EVT_TIME_OVF_TIMER1_EN_S 17 /** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_timer2_ovf event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_TIME_OVF_TIMER2_EN (BIT(18)) #define LEDC_EVT_TIME_OVF_TIMER2_EN_M (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S) #define LEDC_EVT_TIME_OVF_TIMER2_EN_V 0x00000001U #define LEDC_EVT_TIME_OVF_TIMER2_EN_S 18 /** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_timer3_ovf event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_TIME_OVF_TIMER3_EN (BIT(19)) #define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S) #define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U #define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19 -/** LEDC_EVT_TIMER0_CMP_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: - * Enable +/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the ledc_timer0_cmp event. + * 0: Disable + * 1: Enable */ -#define LEDC_EVT_TIMER0_CMP_EN (BIT(20)) -#define LEDC_EVT_TIMER0_CMP_EN_M (LEDC_EVT_TIMER0_CMP_EN_V << LEDC_EVT_TIMER0_CMP_EN_S) -#define LEDC_EVT_TIMER0_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIMER0_CMP_EN_S 20 -/** LEDC_EVT_TIMER1_CMP_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: - * Enable +#define LEDC_EVT_TIME0_CMP_EN (BIT(20)) +#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S) +#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME0_CMP_EN_S 20 +/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the ledc_timer1_cmp event. + * 0: Disable + * 1: Enable */ -#define LEDC_EVT_TIMER1_CMP_EN (BIT(21)) -#define LEDC_EVT_TIMER1_CMP_EN_M (LEDC_EVT_TIMER1_CMP_EN_V << LEDC_EVT_TIMER1_CMP_EN_S) -#define LEDC_EVT_TIMER1_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIMER1_CMP_EN_S 21 -/** LEDC_EVT_TIMER2_CMP_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: - * Enable +#define LEDC_EVT_TIME1_CMP_EN (BIT(21)) +#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S) +#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME1_CMP_EN_S 21 +/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the ledc_timer2_cmp event. + * 0: Disable + * 1: Enable */ -#define LEDC_EVT_TIMER2_CMP_EN (BIT(22)) -#define LEDC_EVT_TIMER2_CMP_EN_M (LEDC_EVT_TIMER2_CMP_EN_V << LEDC_EVT_TIMER2_CMP_EN_S) -#define LEDC_EVT_TIMER2_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIMER2_CMP_EN_S 22 -/** LEDC_EVT_TIMER3_CMP_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: - * Enable +#define LEDC_EVT_TIME2_CMP_EN (BIT(22)) +#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S) +#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME2_CMP_EN_S 22 +/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the ledc_timer3_cmp event. + * 0: Disable + * 1: Enable */ -#define LEDC_EVT_TIMER3_CMP_EN (BIT(23)) -#define LEDC_EVT_TIMER3_CMP_EN_M (LEDC_EVT_TIMER3_CMP_EN_V << LEDC_EVT_TIMER3_CMP_EN_S) -#define LEDC_EVT_TIMER3_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIMER3_CMP_EN_S 23 +#define LEDC_EVT_TIME3_CMP_EN (BIT(23)) +#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S) +#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME3_CMP_EN_S 23 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch0_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN (BIT(24)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S 24 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch1_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN (BIT(25)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S 25 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch2_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN (BIT(26)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S 26 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch3_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN (BIT(27)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S 27 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch4_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN (BIT(28)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S 28 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch5_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN (BIT(29)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S 29 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch6_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN (BIT(30)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S 30 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch7_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN (BIT(31)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S) @@ -2265,248 +2397,288 @@ extern "C" { */ #define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x124) /** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer0_res_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER0_RES_UPDATE_EN (BIT(0)) #define LEDC_TASK_TIMER0_RES_UPDATE_EN_M (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S) #define LEDC_TASK_TIMER0_RES_UPDATE_EN_V 0x00000001U #define LEDC_TASK_TIMER0_RES_UPDATE_EN_S 0 /** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer1_res_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER1_RES_UPDATE_EN (BIT(1)) #define LEDC_TASK_TIMER1_RES_UPDATE_EN_M (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S) #define LEDC_TASK_TIMER1_RES_UPDATE_EN_V 0x00000001U #define LEDC_TASK_TIMER1_RES_UPDATE_EN_S 1 /** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer2_res_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER2_RES_UPDATE_EN (BIT(2)) #define LEDC_TASK_TIMER2_RES_UPDATE_EN_M (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S) #define LEDC_TASK_TIMER2_RES_UPDATE_EN_V 0x00000001U #define LEDC_TASK_TIMER2_RES_UPDATE_EN_S 2 /** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer3_res_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER3_RES_UPDATE_EN (BIT(3)) #define LEDC_TASK_TIMER3_RES_UPDATE_EN_M (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S) #define LEDC_TASK_TIMER3_RES_UPDATE_EN_V 0x00000001U #define LEDC_TASK_TIMER3_RES_UPDATE_EN_S 3 /** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer0_cap task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER0_CAP_EN (BIT(4)) #define LEDC_TASK_TIMER0_CAP_EN_M (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S) #define LEDC_TASK_TIMER0_CAP_EN_V 0x00000001U #define LEDC_TASK_TIMER0_CAP_EN_S 4 /** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer1_cap task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER1_CAP_EN (BIT(5)) #define LEDC_TASK_TIMER1_CAP_EN_M (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S) #define LEDC_TASK_TIMER1_CAP_EN_V 0x00000001U #define LEDC_TASK_TIMER1_CAP_EN_S 5 /** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer2_cap task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER2_CAP_EN (BIT(6)) #define LEDC_TASK_TIMER2_CAP_EN_M (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S) #define LEDC_TASK_TIMER2_CAP_EN_V 0x00000001U #define LEDC_TASK_TIMER2_CAP_EN_S 6 /** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer3_cap task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER3_CAP_EN (BIT(7)) #define LEDC_TASK_TIMER3_CAP_EN_M (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S) #define LEDC_TASK_TIMER3_CAP_EN_V 0x00000001U #define LEDC_TASK_TIMER3_CAP_EN_S 7 /** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH0_EN (BIT(8)) #define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S 8 /** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH1_EN (BIT(9)) #define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S 9 /** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH2_EN (BIT(10)) #define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S 10 /** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH3_EN (BIT(11)) #define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S 11 /** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH4_EN (BIT(12)) #define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S 12 /** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH5_EN (BIT(13)) #define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S 13 /** LEDC_TASK_SIG_OUT_DIS_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH6_EN (BIT(14)) #define LEDC_TASK_SIG_OUT_DIS_CH6_EN_M (LEDC_TASK_SIG_OUT_DIS_CH6_EN_V << LEDC_TASK_SIG_OUT_DIS_CH6_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH6_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH6_EN_S 14 /** LEDC_TASK_SIG_OUT_DIS_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH7_EN (BIT(15)) #define LEDC_TASK_SIG_OUT_DIS_CH7_EN_M (LEDC_TASK_SIG_OUT_DIS_CH7_EN_V << LEDC_TASK_SIG_OUT_DIS_CH7_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH7_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH7_EN_S 15 /** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH0_EN (BIT(16)) #define LEDC_TASK_OVF_CNT_RST_CH0_EN_M (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH0_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH0_EN_S 16 /** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH1_EN (BIT(17)) #define LEDC_TASK_OVF_CNT_RST_CH1_EN_M (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH1_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH1_EN_S 17 /** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH2_EN (BIT(18)) #define LEDC_TASK_OVF_CNT_RST_CH2_EN_M (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH2_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH2_EN_S 18 /** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH3_EN (BIT(19)) #define LEDC_TASK_OVF_CNT_RST_CH3_EN_M (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH3_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH3_EN_S 19 /** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH4_EN (BIT(20)) #define LEDC_TASK_OVF_CNT_RST_CH4_EN_M (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH4_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH4_EN_S 20 /** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH5_EN (BIT(21)) #define LEDC_TASK_OVF_CNT_RST_CH5_EN_M (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH5_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH5_EN_S 21 /** LEDC_TASK_OVF_CNT_RST_CH6_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH6_EN (BIT(22)) #define LEDC_TASK_OVF_CNT_RST_CH6_EN_M (LEDC_TASK_OVF_CNT_RST_CH6_EN_V << LEDC_TASK_OVF_CNT_RST_CH6_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH6_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH6_EN_S 22 /** LEDC_TASK_OVF_CNT_RST_CH7_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH7_EN (BIT(23)) #define LEDC_TASK_OVF_CNT_RST_CH7_EN_M (LEDC_TASK_OVF_CNT_RST_CH7_EN_V << LEDC_TASK_OVF_CNT_RST_CH7_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH7_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH7_EN_S 23 /** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer0_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER0_RST_EN (BIT(24)) #define LEDC_TASK_TIMER0_RST_EN_M (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S) #define LEDC_TASK_TIMER0_RST_EN_V 0x00000001U #define LEDC_TASK_TIMER0_RST_EN_S 24 /** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer1_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER1_RST_EN (BIT(25)) #define LEDC_TASK_TIMER1_RST_EN_M (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S) #define LEDC_TASK_TIMER1_RST_EN_V 0x00000001U #define LEDC_TASK_TIMER1_RST_EN_S 25 /** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer2_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER2_RST_EN (BIT(26)) #define LEDC_TASK_TIMER2_RST_EN_M (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S) #define LEDC_TASK_TIMER2_RST_EN_V 0x00000001U #define LEDC_TASK_TIMER2_RST_EN_S 26 /** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer3_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER3_RST_EN (BIT(27)) #define LEDC_TASK_TIMER3_RST_EN_M (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S) #define LEDC_TASK_TIMER3_RST_EN_V 0x00000001U #define LEDC_TASK_TIMER3_RST_EN_S 27 /** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer0_pause_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER0_PAUSE_RESUME_EN (BIT(28)) #define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S) #define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V 0x00000001U #define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S 28 /** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer1_pause_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER1_PAUSE_RESUME_EN (BIT(29)) #define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S) #define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V 0x00000001U #define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S 29 /** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer2_pause_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER2_PAUSE_RESUME_EN (BIT(30)) #define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S) #define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V 0x00000001U #define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S 30 /** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer3_pause_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER3_PAUSE_RESUME_EN (BIT(31)) #define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S) @@ -2518,192 +2690,216 @@ extern "C" { */ #define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x128) /** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH0_EN (BIT(0)) #define LEDC_TASK_GAMMA_RESTART_CH0_EN_M (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH0_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH0_EN_S 0 /** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH1_EN (BIT(1)) #define LEDC_TASK_GAMMA_RESTART_CH1_EN_M (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH1_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH1_EN_S 1 /** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH2_EN (BIT(2)) #define LEDC_TASK_GAMMA_RESTART_CH2_EN_M (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH2_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH2_EN_S 2 /** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH3_EN (BIT(3)) #define LEDC_TASK_GAMMA_RESTART_CH3_EN_M (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH3_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH3_EN_S 3 /** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH4_EN (BIT(4)) #define LEDC_TASK_GAMMA_RESTART_CH4_EN_M (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH4_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH4_EN_S 4 /** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH5_EN (BIT(5)) #define LEDC_TASK_GAMMA_RESTART_CH5_EN_M (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH5_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH5_EN_S 5 /** LEDC_TASK_GAMMA_RESTART_CH6_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH6_EN (BIT(6)) #define LEDC_TASK_GAMMA_RESTART_CH6_EN_M (LEDC_TASK_GAMMA_RESTART_CH6_EN_V << LEDC_TASK_GAMMA_RESTART_CH6_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH6_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH6_EN_S 6 /** LEDC_TASK_GAMMA_RESTART_CH7_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH7_EN (BIT(7)) #define LEDC_TASK_GAMMA_RESTART_CH7_EN_M (LEDC_TASK_GAMMA_RESTART_CH7_EN_V << LEDC_TASK_GAMMA_RESTART_CH7_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH7_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH7_EN_S 7 /** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH0_EN (BIT(8)) #define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S 8 /** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH1_EN (BIT(9)) #define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S 9 /** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH2_EN (BIT(10)) #define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S 10 /** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH3_EN (BIT(11)) #define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S 11 /** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH4_EN (BIT(12)) #define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S 12 /** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH5_EN (BIT(13)) #define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S 13 /** LEDC_TASK_GAMMA_PAUSE_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH6_EN (BIT(14)) #define LEDC_TASK_GAMMA_PAUSE_CH6_EN_M (LEDC_TASK_GAMMA_PAUSE_CH6_EN_V << LEDC_TASK_GAMMA_PAUSE_CH6_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH6_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH6_EN_S 14 /** LEDC_TASK_GAMMA_PAUSE_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH7_EN (BIT(15)) #define LEDC_TASK_GAMMA_PAUSE_CH7_EN_M (LEDC_TASK_GAMMA_PAUSE_CH7_EN_V << LEDC_TASK_GAMMA_PAUSE_CH7_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH7_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH7_EN_S 15 /** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH0_EN (BIT(16)) #define LEDC_TASK_GAMMA_RESUME_CH0_EN_M (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH0_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH0_EN_S 16 /** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH1_EN (BIT(17)) #define LEDC_TASK_GAMMA_RESUME_CH1_EN_M (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH1_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH1_EN_S 17 /** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH2_EN (BIT(18)) #define LEDC_TASK_GAMMA_RESUME_CH2_EN_M (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH2_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH2_EN_S 18 /** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH3_EN (BIT(19)) #define LEDC_TASK_GAMMA_RESUME_CH3_EN_M (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH3_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH3_EN_S 19 /** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH4_EN (BIT(20)) #define LEDC_TASK_GAMMA_RESUME_CH4_EN_M (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH4_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH4_EN_S 20 /** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH5_EN (BIT(21)) #define LEDC_TASK_GAMMA_RESUME_CH5_EN_M (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH5_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH5_EN_S 21 /** LEDC_TASK_GAMMA_RESUME_CH6_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH6_EN (BIT(22)) #define LEDC_TASK_GAMMA_RESUME_CH6_EN_M (LEDC_TASK_GAMMA_RESUME_CH6_EN_V << LEDC_TASK_GAMMA_RESUME_CH6_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH6_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH6_EN_S 22 /** LEDC_TASK_GAMMA_RESUME_CH7_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH7_EN (BIT(23)) #define LEDC_TASK_GAMMA_RESUME_CH7_EN_M (LEDC_TASK_GAMMA_RESUME_CH7_EN_V << LEDC_TASK_GAMMA_RESUME_CH7_EN_S) @@ -2811,88 +3007,92 @@ extern "C" { */ #define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x170) /** LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0; - * Configures the clock source for the four timers.\\0: APB_CLK\\1: RC_FAST_CLK\\2: - * XTAL_CLK\\3: Invalid. No clock + * Configures the clock source for the four timers. + * 0: APB_CLK + * 1: RC_FAST_CLK + * 2: XTAL_CLK + * 3: Invalid. No clock */ #define LEDC_APB_CLK_SEL 0x00000003U #define LEDC_APB_CLK_SEL_M (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S) #define LEDC_APB_CLK_SEL_V 0x00000003U #define LEDC_APB_CLK_SEL_S 0 /** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the - * clock gate for LEDC ch0 gamma ram + * Configures whether or not to open LEDC ch0 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram + * 1: Force open the clock gate for LEDC ch0 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH0 (BIT(2)) #define LEDC_GAMMA_RAM_CLK_EN_CH0_M (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S) #define LEDC_GAMMA_RAM_CLK_EN_CH0_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH0_S 2 /** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0; - * Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the - * clock gate for LEDC ch1 gamma ram + * Configures whether or not to open LEDC ch1 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram + * 1: Force open the clock gate for LEDC ch1 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH1 (BIT(3)) #define LEDC_GAMMA_RAM_CLK_EN_CH1_M (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S) #define LEDC_GAMMA_RAM_CLK_EN_CH1_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH1_S 3 /** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the - * clock gate for LEDC ch2 gamma ram + * Configures whether or not to open LEDC ch2 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram + * 1: Force open the clock gate for LEDC ch2 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH2 (BIT(4)) #define LEDC_GAMMA_RAM_CLK_EN_CH2_M (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S) #define LEDC_GAMMA_RAM_CLK_EN_CH2_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH2_S 4 /** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the - * clock gate for LEDC ch3 gamma ram + * Configures whether or not to open LEDC ch3 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram + * 1: Force open the clock gate for LEDC ch3 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH3 (BIT(5)) #define LEDC_GAMMA_RAM_CLK_EN_CH3_M (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S) #define LEDC_GAMMA_RAM_CLK_EN_CH3_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH3_S 5 /** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the - * clock gate for LEDC ch4 gamma ram + * Configures whether or not to open LEDC ch4 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram + * 1: Force open the clock gate for LEDC ch4 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH4 (BIT(6)) #define LEDC_GAMMA_RAM_CLK_EN_CH4_M (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S) #define LEDC_GAMMA_RAM_CLK_EN_CH4_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH4_S 6 /** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0; - * Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the - * clock gate for LEDC ch5 gamma ram + * Configures whether or not to open LEDC ch5 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram + * 1: Force open the clock gate for LEDC ch5 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH5 (BIT(7)) #define LEDC_GAMMA_RAM_CLK_EN_CH5_M (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S) #define LEDC_GAMMA_RAM_CLK_EN_CH5_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH5_S 7 /** LEDC_GAMMA_RAM_CLK_EN_CH6 : R/W; bitpos: [8]; default: 0; - * Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch6 gamma ram\\1: Force open the - * clock gate for LEDC ch6 gamma ram + * Configures whether or not to open LEDC ch6 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram + * 1: Force open the clock gate for LEDC ch6 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH6 (BIT(8)) #define LEDC_GAMMA_RAM_CLK_EN_CH6_M (LEDC_GAMMA_RAM_CLK_EN_CH6_V << LEDC_GAMMA_RAM_CLK_EN_CH6_S) #define LEDC_GAMMA_RAM_CLK_EN_CH6_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH6_S 8 /** LEDC_GAMMA_RAM_CLK_EN_CH7 : R/W; bitpos: [9]; default: 0; - * Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch7 gamma ram\\1: Force open the - * clock gate for LEDC ch7 gamma ram + * Configures whether or not to open LEDC ch7 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram + * 1: Force open the clock gate for LEDC ch7 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH7 (BIT(9)) #define LEDC_GAMMA_RAM_CLK_EN_CH7_M (LEDC_GAMMA_RAM_CLK_EN_CH7_V << LEDC_GAMMA_RAM_CLK_EN_CH7_S) #define LEDC_GAMMA_RAM_CLK_EN_CH7_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH7_S 9 /** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to open register clock gate.\\0: Open the clock gate only - * when application writes registers\\1: Force open the clock gate for register + * Configures whether or not to open register clock gate. + * 0: Open the clock gate only when application writes registers + * 1: Force open the clock gate for register */ #define LEDC_CLK_EN (BIT(31)) #define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h index 23029726e8..668767aa68 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h @@ -10,32 +10,40 @@ extern "C" { #endif -/** Group: conf0 */ +/** Group: Configuration Register */ /** Type of chn_conf0 register * Configuration register 0 for channel n */ typedef union { struct { /** timer_sel : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel n selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel n selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ uint32_t timer_sel:2; /** sig_out_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel n.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel n. + * 0: Signal output disable + * 1: Signal output enable */ uint32_t sig_out_en:1; /** idle_lv : R/W; bitpos: [3]; default: 0; * Configures the output value when channel n is inactive. Valid only when - * LEDC_SIG_OUT_EN_CHn is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CHn is 0. + * 0: Output level is low + * 1: Output level is high */ uint32_t idle_lv:1; /** para_up : WT; bitpos: [4]; default: 0; * Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn, * LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel - * n, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * n, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ uint32_t para_up:1; /** ovf_num : R/W; bitpos: [14:5]; default: 0; @@ -44,12 +52,15 @@ typedef union { */ uint32_t ovf_num:10; /** ovf_cnt_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel n.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel n. + * 0: Disable + * 1: Enable */ uint32_t ovf_cnt_en:1; /** ovf_cnt_reset : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel n.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel n. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ uint32_t ovf_cnt_reset:1; uint32_t reserved_17:15; @@ -93,30 +104,30 @@ typedef union { struct { uint32_t reserved_0:31; /** duty_start : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ uint32_t duty_start:1; }; uint32_t val; } ledc_chn_conf1_reg_t; +/** Group: Status Register */ /** Type of chn_duty_r register * Current duty cycle register for channel n */ typedef union { struct { - /** duty_ch0_r : RO; bitpos: [24:0]; default: 0; + /** duty_r : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel n. */ - uint32_t duty:25; + uint32_t duty_r:25; uint32_t reserved_25:7; }; uint32_t val; } ledc_chn_duty_r_reg_t; - -/** Group: conf1 */ /** Type of timern_conf register * Timer n configuration register */ @@ -132,21 +143,22 @@ typedef union { */ uint32_t clk_div:18; /** pause : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer n.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer n. + * 0: Normal + * 1: Pause */ uint32_t pause:1; /** rst : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer n. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer n. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ uint32_t rst:1; - /** tick_sel : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer n selected. Unused. - */ - uint32_t tick_sel:1; + uint32_t reserved_25:1; /** para_up : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMERn and - * LEDC_TIMERn_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMERn and LEDC_TIMERn_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ uint32_t para_up:1; uint32_t reserved_27:5; @@ -168,6 +180,688 @@ typedef union { uint32_t val; } ledc_timern_value_reg_t; +/** Type of conf register + * LEDC global configuration register + */ +typedef union { + struct { + /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0; + * Configures the clock source for the four timers. + * 0: APB_CLK + * 1: RC_FAST_CLK + * 2: XTAL_CLK + * 3: Invalid. No clock + */ + uint32_t apb_clk_sel:2; + /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to open LEDC ch0 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram + * 1: Force open the clock gate for LEDC ch0 gamma ram + */ + uint32_t gamma_ram_clk_en_ch0:1; + /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; + * Configures whether or not to open LEDC ch1 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram + * 1: Force open the clock gate for LEDC ch1 gamma ram + */ + uint32_t gamma_ram_clk_en_ch1:1; + /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to open LEDC ch2 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram + * 1: Force open the clock gate for LEDC ch2 gamma ram + */ + uint32_t gamma_ram_clk_en_ch2:1; + /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to open LEDC ch3 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram + * 1: Force open the clock gate for LEDC ch3 gamma ram + */ + uint32_t gamma_ram_clk_en_ch3:1; + /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to open LEDC ch4 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram + * 1: Force open the clock gate for LEDC ch4 gamma ram + */ + uint32_t gamma_ram_clk_en_ch4:1; + /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; + * Configures whether or not to open LEDC ch5 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram + * 1: Force open the clock gate for LEDC ch5 gamma ram + */ + uint32_t gamma_ram_clk_en_ch5:1; + /** gamma_ram_clk_en_ch6 : R/W; bitpos: [8]; default: 0; + * Configures whether or not to open LEDC ch6 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram + * 1: Force open the clock gate for LEDC ch6 gamma ram + */ + uint32_t gamma_ram_clk_en_ch6:1; + /** gamma_ram_clk_en_ch7 : R/W; bitpos: [9]; default: 0; + * Configures whether or not to open LEDC ch7 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram + * 1: Force open the clock gate for LEDC ch7 gamma ram + */ + uint32_t gamma_ram_clk_en_ch7:1; + uint32_t reserved_10:21; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to open register clock gate. + * 0: Open the clock gate only when application writes registers + * 1: Force open the clock gate for register + */ + uint32_t clk_en:1; + }; + uint32_t val; +} ledc_conf_reg_t; + +/** Type of chn_gamma_conf register + * Ledc chn gamma config register. + */ +typedef union { + struct { + /** gamma_entry_num : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC chn. + */ + uint32_t gamma_entry_num:5; + /** gamma_pause : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC chn. + * 0: Invalid. No effect + * 1: Pause + */ + uint32_t gamma_pause:1; + /** gamma_resume : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC chn. + * 0: Invalid. No effect + * 1: Resume + */ + uint32_t gamma_resume:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ledc_chn_gamma_conf_reg_t; + +/** Type of evt_task_en0 register + * Ledc event task enable bit register0. + */ +typedef union { + struct { + /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch0_en:1; + /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch1_en:1; + /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch2_en:1; + /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch3_en:1; + /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch4_en:1; + /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch5_en:1; + /** evt_duty_chng_end_ch6_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable the ledc_ch6_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch6_en:1; + /** evt_duty_chng_end_ch7_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable the ledc_ch7_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch7_en:1; + /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch0_en:1; + /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch1_en:1; + /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch2_en:1; + /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch3_en:1; + /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch4_en:1; + /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch5_en:1; + /** evt_ovf_cnt_pls_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch6_en:1; + /** evt_ovf_cnt_pls_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch7_en:1; + /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the ledc_timer0_ovf event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time_ovf_timer0_en:1; + /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable the ledc_timer1_ovf event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time_ovf_timer1_en:1; + /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable the ledc_timer2_ovf event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time_ovf_timer2_en:1; + /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable the ledc_timer3_ovf event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time_ovf_timer3_en:1; + /** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the ledc_timer0_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time0_cmp_en:1; + /** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the ledc_timer1_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time1_cmp_en:1; + /** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the ledc_timer2_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time2_cmp_en:1; + /** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the ledc_timer3_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time3_cmp_en:1; + /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch0_en:1; + /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch1_en:1; + /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch2_en:1; + /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch3_en:1; + /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch4_en:1; + /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch5_en:1; + /** task_duty_scale_update_ch6_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable the ledc_ch6_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch6_en:1; + /** task_duty_scale_update_ch7_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable the ledc_ch7_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch7_en:1; + }; + uint32_t val; +} ledc_evt_task_en0_reg_t; + +/** Type of evt_task_en1 register + * Ledc event task enable bit register1. + */ +typedef union { + struct { + /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_timer0_res_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer0_res_update_en:1; + /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_timer1_res_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer1_res_update_en:1; + /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_timer2_res_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer2_res_update_en:1; + /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_timer3_res_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer3_res_update_en:1; + /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_timer0_cap task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer0_cap_en:1; + /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_timer1_cap task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer1_cap_en:1; + /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_timer2_cap task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer2_cap_en:1; + /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_timer3_cap task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer3_cap_en:1; + /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch0_en:1; + /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch1_en:1; + /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch2_en:1; + /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch3_en:1; + /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch4_en:1; + /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch5_en:1; + /** task_sig_out_dis_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable ledc_ch6_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch6_en:1; + /** task_sig_out_dis_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable ledc_ch7_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch7_en:1; + /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch0_en:1; + /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch1_en:1; + /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch2_en:1; + /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch3_en:1; + /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch4_en:1; + /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch5_en:1; + /** task_ovf_cnt_rst_ch6_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch6_en:1; + /** task_ovf_cnt_rst_ch7_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch7_en:1; + /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable ledc_timer0_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer0_rst_en:1; + /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable ledc_timer1_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer1_rst_en:1; + /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable ledc_timer2_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer2_rst_en:1; + /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable ledc_timer3_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer3_rst_en:1; + /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable ledc_timer0_pause_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer0_pause_resume_en:1; + /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable ledc_timer1_pause_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer1_pause_resume_en:1; + /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable ledc_timer2_pause_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer2_pause_resume_en:1; + /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable ledc_timer3_pause_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer3_pause_resume_en:1; + }; + uint32_t val; +} ledc_evt_task_en1_reg_t; + +/** Type of evt_task_en2 register + * Ledc event task enable bit register2. + */ +typedef union { + struct { + /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch0_en:1; + /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch1_en:1; + /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch2_en:1; + /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch3_en:1; + /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch4_en:1; + /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch5_en:1; + /** task_gamma_restart_ch6_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch6_en:1; + /** task_gamma_restart_ch7_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch7_en:1; + /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch0_en:1; + /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch1_en:1; + /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch2_en:1; + /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch3_en:1; + /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch4_en:1; + /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch5_en:1; + /** task_gamma_pause_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch6_en:1; + /** task_gamma_pause_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch7_en:1; + /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch0_en:1; + /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch1_en:1; + /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch2_en:1; + /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch3_en:1; + /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch4_en:1; + /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch5_en:1; + /** task_gamma_resume_ch6_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch6_en:1; + /** task_gamma_resume_ch7_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch7_en:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} ledc_evt_task_en2_reg_t; + +/** Type of timern_cmp register + * Ledc timern compare value register. + */ +typedef union { + struct { + /** timer_cmp : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timern. + */ + uint32_t timer_cmp:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cmp_reg_t; + +/** Type of timern_cnt_cap register + * Ledc timern captured count value register. + */ +typedef union { + struct { + /** timer_cnt_cap : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timern count value. + */ + uint32_t timer_cnt_cap:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cnt_cap_reg_t; + /** Group: Interrupt Register */ /** Type of int_raw register @@ -571,607 +1265,13 @@ typedef union { } ledc_int_clr_reg_t; -/** Group: gamma */ -/** Type of chn_gamma_conf register - * Ledc chn gamma config register. - */ -typedef union { - struct { - /** ch0_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC chn. - */ - uint32_t ch0_gamma_entry_num:5; - /** ch0_gamma_pause : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No - * effect\\1: Pause - */ - uint32_t ch0_gamma_pause:1; - /** ch0_gamma_resume : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No - * effect\\1: Resume - */ - uint32_t ch0_gamma_resume:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ledc_chn_gamma_conf_reg_t; - - -/** Group: en0 */ -/** Type of evt_task_en0 register - * Ledc event task enable bit register0. - */ -typedef union { - struct { - /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch0_en:1; - /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch1_en:1; - /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch2_en:1; - /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch3_en:1; - /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch4_en:1; - /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch5_en:1; - /** evt_duty_chng_end_ch6_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch6_en:1; - /** evt_duty_chng_end_ch7_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch7_en:1; - /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch0_en:1; - /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch1_en:1; - /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch2_en:1; - /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch3_en:1; - /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch4_en:1; - /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch5_en:1; - /** evt_ovf_cnt_pls_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch6_en:1; - /** evt_ovf_cnt_pls_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_ovf_cnt_pls_ch7_en:1; - /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_time_ovf_timer0_en:1; - /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_time_ovf_timer1_en:1; - /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_time_ovf_timer2_en:1; - /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_time_ovf_timer3_en:1; - /** evt_timer0_cmp_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer0_cmp_en:1; - /** evt_timer1_cmp_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer1_cmp_en:1; - /** evt_timer2_cmp_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer2_cmp_en:1; - /** evt_timer3_cmp_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer3_cmp_en:1; - /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch0_en:1; - /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch1_en:1; - /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch2_en:1; - /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch3_en:1; - /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch4_en:1; - /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch5_en:1; - /** task_duty_scale_update_ch6_en : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch6_en:1; - /** task_duty_scale_update_ch7_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\0: - * Disable\\1: Enable - */ - uint32_t task_duty_scale_update_ch7_en:1; - }; - uint32_t val; -} ledc_evt_task_en0_reg_t; - - -/** Group: en1 */ -/** Type of evt_task_en1 register - * Ledc event task enable bit register1. - */ -typedef union { - struct { - /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer0_res_update_en:1; - /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer1_res_update_en:1; - /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer2_res_update_en:1; - /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer3_res_update_en:1; - /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable - */ - uint32_t task_timer0_cap_en:1; - /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable - */ - uint32_t task_timer1_cap_en:1; - /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable - */ - uint32_t task_timer2_cap_en:1; - /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable - */ - uint32_t task_timer3_cap_en:1; - /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch0_en:1; - /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch1_en:1; - /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch2_en:1; - /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch3_en:1; - /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch4_en:1; - /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch5_en:1; - /** task_sig_out_dis_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch6_en:1; - /** task_sig_out_dis_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: Disable\\1: - * Enable - */ - uint32_t task_sig_out_dis_ch7_en:1; - /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch0_en:1; - /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch1_en:1; - /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch2_en:1; - /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch3_en:1; - /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch4_en:1; - /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch5_en:1; - /** task_ovf_cnt_rst_ch6_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch6_en:1; - /** task_ovf_cnt_rst_ch7_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: Disable\\1: - * Enable - */ - uint32_t task_ovf_cnt_rst_ch7_en:1; - /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable - */ - uint32_t task_timer0_rst_en:1; - /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable - */ - uint32_t task_timer1_rst_en:1; - /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable - */ - uint32_t task_timer2_rst_en:1; - /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable - */ - uint32_t task_timer3_rst_en:1; - /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer0_pause_resume_en:1; - /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer1_pause_resume_en:1; - /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer2_pause_resume_en:1; - /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_timer3_pause_resume_en:1; - }; - uint32_t val; -} ledc_evt_task_en1_reg_t; - - -/** Group: en2 */ -/** Type of evt_task_en2 register - * Ledc event task enable bit register2. - */ -typedef union { - struct { - /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch0_en:1; - /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch1_en:1; - /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch2_en:1; - /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch3_en:1; - /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch4_en:1; - /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch5_en:1; - /** task_gamma_restart_ch6_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch6_en:1; - /** task_gamma_restart_ch7_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch7_en:1; - /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch0_en:1; - /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch1_en:1; - /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch2_en:1; - /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch3_en:1; - /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch4_en:1; - /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch5_en:1; - /** task_gamma_pause_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch6_en:1; - /** task_gamma_pause_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_pause_ch7_en:1; - /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch0_en:1; - /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch1_en:1; - /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch2_en:1; - /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch3_en:1; - /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch4_en:1; - /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch5_en:1; - /** task_gamma_resume_ch6_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch6_en:1; - /** task_gamma_resume_ch7_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_resume_ch7_en:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} ledc_evt_task_en2_reg_t; - - -/** Group: cmp */ -/** Type of timern_cmp register - * Ledc timern compare value register. - */ -typedef union { - struct { - /** timer0_cmp : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timern. - */ - uint32_t timer0_cmp:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_timern_cmp_reg_t; - - -/** Group: cap */ -/** Type of timern_cnt_cap register - * Ledc timern captured count value register. - */ -typedef union { - struct { - /** timer0_cnt_cap : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timern count value. - */ - uint32_t timer_cnt_cap:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_timern_cnt_cap_reg_t; - - -/** Group: Configuration Register */ -/** Type of conf register - * LEDC global configuration register - */ -typedef union { - struct { - /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0; - * Configures the clock source for the four timers.\\0: APB_CLK\\1: RC_FAST_CLK\\2: - * XTAL_CLK\\3: Invalid. No clock - */ - uint32_t apb_clk_sel:2; - /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the - * clock gate for LEDC ch0 gamma ram - */ - uint32_t gamma_ram_clk_en_ch0:1; - /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; - * Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the - * clock gate for LEDC ch1 gamma ram - */ - uint32_t gamma_ram_clk_en_ch1:1; - /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the - * clock gate for LEDC ch2 gamma ram - */ - uint32_t gamma_ram_clk_en_ch2:1; - /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the - * clock gate for LEDC ch3 gamma ram - */ - uint32_t gamma_ram_clk_en_ch3:1; - /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the - * clock gate for LEDC ch4 gamma ram - */ - uint32_t gamma_ram_clk_en_ch4:1; - /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; - * Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the - * clock gate for LEDC ch5 gamma ram - */ - uint32_t gamma_ram_clk_en_ch5:1; - /** gamma_ram_clk_en_ch6 : R/W; bitpos: [8]; default: 0; - * Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch6 gamma ram\\1: Force open the - * clock gate for LEDC ch6 gamma ram - */ - uint32_t gamma_ram_clk_en_ch6:1; - /** gamma_ram_clk_en_ch7 : R/W; bitpos: [9]; default: 0; - * Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch7 gamma ram\\1: Force open the - * clock gate for LEDC ch7 gamma ram - */ - uint32_t gamma_ram_clk_en_ch7:1; - uint32_t reserved_10:21; - /** clk_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to open register clock gate.\\0: Open the clock gate only - * when application writes registers\\1: Force open the clock gate for register - */ - uint32_t clk_en:1; - }; - uint32_t val; -} ledc_conf_reg_t; - - /** Group: Version Register */ /** Type of date register * Version control register */ typedef union { struct { - /** ledc_date : R/W; bitpos: [27:0]; default: 36712560; + /** ledc_date : R/W; bitpos: [27:0]; default: 37765152; * Configures the version. */ uint32_t ledc_date:28; @@ -1180,6 +1280,7 @@ typedef union { uint32_t val; } ledc_date_reg_t; + typedef struct { volatile ledc_chn_conf0_reg_t conf0; volatile ledc_chn_hpoint_reg_t hpoint; @@ -1205,7 +1306,7 @@ typedef struct { volatile ledc_ch_group_reg_t channel_group[1]; volatile ledc_timer_group_reg_t timer_group[1]; volatile ledc_int_raw_reg_t int_raw; - volatile ledc_int_st_reg_t int_st; + volatile ledc_int_st_reg_t int_st; volatile ledc_int_ena_reg_t int_ena; volatile ledc_int_clr_reg_t int_clr; uint32_t reserved_0d0[12]; @@ -1221,7 +1322,6 @@ typedef struct { volatile ledc_date_reg_t date; } ledc_dev_t; - /** * Gamma fade param group ram type */ @@ -1244,7 +1344,6 @@ typedef struct { volatile ledc_gamma_channel_t channel[8]; } ledc_gamma_ram_t; - extern ledc_dev_t LEDC; extern ledc_gamma_ram_t LEDC_GAMMA_RAM; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ppa_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ppa_eco5_struct.h deleted file mode 100644 index 4d0f664733..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/ppa_eco5_struct.h +++ /dev/null @@ -1,1025 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of blend0_clut_data register - * CLUT sram data read/write register in background plane of blender - */ -typedef union { - struct { - /** rdwr_word_blend0_clut : R/W; bitpos: [31:0]; default: 0; - * Write and read data to/from CLUT RAM in background plane of blender engine through - * this field in fifo mode. - */ - uint32_t rdwr_word_blend0_clut:32; - }; - uint32_t val; -} ppa_blend0_clut_data_reg_t; - -/** Type of blend1_clut_data register - * CLUT sram data read/write register in foreground plane of blender - */ -typedef union { - struct { - /** rdwr_word_blend1_clut : R/W; bitpos: [31:0]; default: 0; - * Write and read data to/from CLUT RAM in foreground plane of blender engine through - * this field in fifo mode. - */ - uint32_t rdwr_word_blend1_clut:32; - }; - uint32_t val; -} ppa_blend1_clut_data_reg_t; - -/** Type of clut_conf register - * CLUT configure register - */ -typedef union { - struct { - /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; - * 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register - * PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: - * memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr - * should be 01 to access sr clut and should be 10 to access blend0 clut and should be - * 11 to access blend 1 clut in memory mode. - */ - uint32_t apb_fifo_mask:1; - /** blend0_clut_mem_rst : R/W; bitpos: [1]; default: 0; - * Write 1 then write 0 to this bit to reset BLEND0 CLUT. - */ - uint32_t blend0_clut_mem_rst:1; - /** blend1_clut_mem_rst : R/W; bitpos: [2]; default: 0; - * Write 1 then write 0 to this bit to reset BLEND1 CLUT. - */ - uint32_t blend1_clut_mem_rst:1; - /** blend0_clut_mem_rdaddr_rst : R/W; bitpos: [3]; default: 0; - * Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode. - */ - uint32_t blend0_clut_mem_rdaddr_rst:1; - /** blend1_clut_mem_rdaddr_rst : R/W; bitpos: [4]; default: 0; - * Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode. - */ - uint32_t blend1_clut_mem_rdaddr_rst:1; - /** blend0_clut_mem_force_pd : R/W; bitpos: [5]; default: 0; - * 1: force power down BLEND CLUT memory. - */ - uint32_t blend0_clut_mem_force_pd:1; - /** blend0_clut_mem_force_pu : R/W; bitpos: [6]; default: 0; - * 1: force power up BLEND CLUT memory. - */ - uint32_t blend0_clut_mem_force_pu:1; - /** blend0_clut_mem_clk_ena : R/W; bitpos: [7]; default: 0; - * 1: Force clock on for BLEND CLUT memory. - */ - uint32_t blend0_clut_mem_clk_ena:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ppa_clut_conf_reg_t; - -/** Type of sr_color_mode register - * Scaling and rotating engine color mode register - */ -typedef union { - struct { - /** sr_rx_cm : R/W; bitpos: [3:0]; default: 0; - * The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: - * RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. - */ - uint32_t sr_rx_cm:4; - /** sr_tx_cm : R/W; bitpos: [7:4]; default: 0; - * The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. - * 1: RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. - */ - uint32_t sr_tx_cm:4; - /** yuv_rx_range : R/W; bitpos: [8]; default: 0; - * YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range - */ - uint32_t yuv_rx_range:1; - /** yuv_tx_range : R/W; bitpos: [9]; default: 0; - * YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range - */ - uint32_t yuv_tx_range:1; - /** yuv2rgb_protocal : R/W; bitpos: [10]; default: 0; - * YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709 - */ - uint32_t yuv2rgb_protocal:1; - /** rgb2yuv_protocal : R/W; bitpos: [11]; default: 0; - * RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 - */ - uint32_t rgb2yuv_protocal:1; - /** yuv422_rx_byte_order : R/W; bitpos: [13:12]; default: 0; - * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY - */ - uint32_t yuv422_rx_byte_order:2; - uint32_t reserved_14:18; - }; - uint32_t val; -} ppa_sr_color_mode_reg_t; - -/** Type of blend_color_mode register - * blending engine color mode register - */ -typedef union { - struct { - /** blend0_rx_cm : R/W; bitpos: [3:0]; default: 0; - * The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved. 4: L8. 5: L4. 8: YUV420. 9: YUV422. 12:GRAY - */ - uint32_t blend0_rx_cm:4; - /** blend1_rx_cm : R/W; bitpos: [7:4]; default: 0; - * The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4. - */ - uint32_t blend1_rx_cm:4; - /** blend_tx_cm : R/W; bitpos: [11:8]; default: 0; - * The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved. 8: YUV420. 9: YUV422. 12:GRAY - */ - uint32_t blend_tx_cm:4; - /** blend0_rx_yuv_range : R/W; bitpos: [12]; default: 0; - * YUV input range when blend0 rx cm is yuv. 0: limit range. 1: full range - */ - uint32_t blend0_rx_yuv_range:1; - /** blend_tx_yuv_range : R/W; bitpos: [13]; default: 0; - * YUV output range when blend tx cm is yuv. 0: limit range. 1: full range - */ - uint32_t blend_tx_yuv_range:1; - /** blend0_rx_yuv2rgb_protocal : R/W; bitpos: [14]; default: 0; - * YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709 - */ - uint32_t blend0_rx_yuv2rgb_protocal:1; - /** blend_tx_rgb2yuv_protocal : R/W; bitpos: [15]; default: 0; - * RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709 - */ - uint32_t blend_tx_rgb2yuv_protocal:1; - /** blend0_rx_yuv422_byte_order : R/W; bitpos: [17:16]; default: 0; - * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY - */ - uint32_t blend0_rx_yuv422_byte_order:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} ppa_blend_color_mode_reg_t; - -/** Type of sr_byte_order register - * Scaling and rotating engine byte order register - */ -typedef union { - struct { - /** sr_rx_byte_swap_en : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 - * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. - */ - uint32_t sr_rx_byte_swap_en:1; - /** sr_rx_rgb_swap_en : R/W; bitpos: [1]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb - * would be swap to bgr. - */ - uint32_t sr_rx_rgb_swap_en:1; - /** sr_macro_bk_ro_bypass : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to bypass the macro block order function. This function is used - * to improve efficient accessing external memory. - */ - uint32_t sr_macro_bk_ro_bypass:1; - /** sr_bk_size_sel : R/W; bitpos: [3]; default: 0; - * sel srm pix_blk size, 0:32x32, 1:16x16 - */ - uint32_t sr_bk_size_sel:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_sr_byte_order_reg_t; - -/** Type of blend_byte_order register - * Blending engine byte order register - */ -typedef union { - struct { - /** blend0_rx_byte_swap_en : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 - * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. - */ - uint32_t blend0_rx_byte_swap_en:1; - /** blend1_rx_byte_swap_en : R/W; bitpos: [1]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 - * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. - */ - uint32_t blend1_rx_byte_swap_en:1; - /** blend0_rx_rgb_swap_en : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb - * would be swap to bgr. - */ - uint32_t blend0_rx_rgb_swap_en:1; - /** blend1_rx_rgb_swap_en : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb - * would be swap to bgr. - */ - uint32_t blend1_rx_rgb_swap_en:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_blend_byte_order_reg_t; - -/** Type of blend_trans_mode register - * Blending engine mode configure register - */ -typedef union { - struct { - /** blend_en : R/W; bitpos: [0]; default: 0; - * Set this bit to enable alpha blending. - */ - uint32_t blend_en:1; - /** blend_bypass : R/W; bitpos: [1]; default: 0; - * Set this bit to bypass blender. Then background date would be output. - */ - uint32_t blend_bypass:1; - /** blend_fix_pixel_fill_en : R/W; bitpos: [2]; default: 0; - * This bit is used to enable fix pixel filling. When this mode is enable only Tx - * channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL. - */ - uint32_t blend_fix_pixel_fill_en:1; - /** blend_trans_mode_update : WT; bitpos: [3]; default: 0; - * Set this bit to update the transfer mode. Only the bit is set the transfer mode is - * valid. - */ - uint32_t blend_trans_mode_update:1; - /** blend_rst : R/W; bitpos: [4]; default: 0; - * write 1 then write 0 to reset blending engine. - */ - uint32_t blend_rst:1; - /** blend_tx_inf_sel : R/W; bitpos: [6:5]; default: 0; - * unused ! Configures blend tx interface. 0: dma2d only, 1: le_enc only, 2: dma2d and - * ls_enc - */ - uint32_t blend_tx_inf_sel:2; - uint32_t reserved_7:25; - }; - uint32_t val; -} ppa_blend_trans_mode_reg_t; - -/** Type of sr_fix_alpha register - * Scaling and rotating engine alpha override register - */ -typedef union { - struct { - /** sr_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128; - * The value would replace the alpha value in received pixel for Scaling and Rotating - * engine when PPA_SR_RX_ALPHA_CONF_EN is enabled. - */ - uint32_t sr_rx_fix_alpha:8; - /** sr_rx_alpha_mod : R/W; bitpos: [9:8]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. - */ - uint32_t sr_rx_alpha_mod:2; - /** sr_rx_alpha_inv : R/W; bitpos: [10]; default: 0; - * Set this bit to invert the original alpha value. When RX color mode is - * RGB565/RGB88. The original alpha value is 255. - */ - uint32_t sr_rx_alpha_inv:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} ppa_sr_fix_alpha_reg_t; - -/** Type of blend_tx_size register - * Fix pixel filling mode image size register - */ -typedef union { - struct { - /** blend_hb : R/W; bitpos: [13:0]; default: 0; - * The horizontal width of image block that would be filled in fix pixel filling mode - * or blend mode. The unit is pixel. Must be even num when YUV422 or YUV420 - */ - uint32_t blend_hb:14; - /** blend_vb : R/W; bitpos: [27:14]; default: 0; - * The vertical width of image block that would be filled in fix pixel filling mode or - * blend mode. The unit is pixel. Must be even num when YUV420 - */ - uint32_t blend_vb:14; - uint32_t reserved_28:4; - }; - uint32_t val; -} ppa_blend_tx_size_reg_t; - -/** Type of blend_fix_alpha register - * Blending engine alpha override register - */ -typedef union { - struct { - /** blend0_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128; - * The value would replace the alpha value in received pixel for background plane of - * blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled. - */ - uint32_t blend0_rx_fix_alpha:8; - /** blend1_rx_fix_alpha : R/W; bitpos: [15:8]; default: 128; - * The value would replace the alpha value in received pixel for foreground plane of - * blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled. - */ - uint32_t blend1_rx_fix_alpha:8; - /** blend0_rx_alpha_mod : R/W; bitpos: [17:16]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. - */ - uint32_t blend0_rx_alpha_mod:2; - /** blend1_rx_alpha_mod : R/W; bitpos: [19:18]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. - */ - uint32_t blend1_rx_alpha_mod:2; - /** blend0_rx_alpha_inv : R/W; bitpos: [20]; default: 0; - * Set this bit to invert the original alpha value. When RX color mode is - * RGB565/RGB88. The original alpha value is 255. - */ - uint32_t blend0_rx_alpha_inv:1; - /** blend1_rx_alpha_inv : R/W; bitpos: [21]; default: 0; - * Set this bit to invert the original alpha value. When RX color mode is - * RGB565/RGB88. The original alpha value is 255. - */ - uint32_t blend1_rx_alpha_inv:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} ppa_blend_fix_alpha_reg_t; - -/** Type of blend_rgb register - * RGB color register - */ -typedef union { - struct { - /** blend1_rx_b : R/W; bitpos: [7:0]; default: 128; - * blue color for A4/A8 mode. - */ - uint32_t blend1_rx_b:8; - /** blend1_rx_g : R/W; bitpos: [15:8]; default: 128; - * green color for A4/A8 mode. - */ - uint32_t blend1_rx_g:8; - /** blend1_rx_r : R/W; bitpos: [23:16]; default: 128; - * red color for A4/A8 mode. - */ - uint32_t blend1_rx_r:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_blend_rgb_reg_t; - -/** Type of blend_fix_pixel register - * Blending engine fix pixel register - */ -typedef union { - struct { - /** blend_tx_fix_pixel : R/W; bitpos: [31:0]; default: 0; - * The configure fix pixel in fix pixel filling mode for blender engine. - */ - uint32_t blend_tx_fix_pixel:32; - }; - uint32_t val; -} ppa_blend_fix_pixel_reg_t; - -/** Type of ck_fg_low register - * foreground color key lower threshold - */ -typedef union { - struct { - /** colorkey_fg_b_low : R/W; bitpos: [7:0]; default: 255; - * color key lower threshold of foreground b channel - */ - uint32_t colorkey_fg_b_low:8; - /** colorkey_fg_g_low : R/W; bitpos: [15:8]; default: 255; - * color key lower threshold of foreground g channel - */ - uint32_t colorkey_fg_g_low:8; - /** colorkey_fg_r_low : R/W; bitpos: [23:16]; default: 255; - * color key lower threshold of foreground r channel - */ - uint32_t colorkey_fg_r_low:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_ck_fg_low_reg_t; - -/** Type of ck_fg_high register - * foreground color key higher threshold - */ -typedef union { - struct { - /** colorkey_fg_b_high : R/W; bitpos: [7:0]; default: 0; - * color key higher threshold of foreground b channel - */ - uint32_t colorkey_fg_b_high:8; - /** colorkey_fg_g_high : R/W; bitpos: [15:8]; default: 0; - * color key higher threshold of foreground g channel - */ - uint32_t colorkey_fg_g_high:8; - /** colorkey_fg_r_high : R/W; bitpos: [23:16]; default: 0; - * color key higher threshold of foreground r channel - */ - uint32_t colorkey_fg_r_high:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_ck_fg_high_reg_t; - -/** Type of ck_bg_low register - * background color key lower threshold - */ -typedef union { - struct { - /** colorkey_bg_b_low : R/W; bitpos: [7:0]; default: 255; - * color key lower threshold of background b channel - */ - uint32_t colorkey_bg_b_low:8; - /** colorkey_bg_g_low : R/W; bitpos: [15:8]; default: 255; - * color key lower threshold of background g channel - */ - uint32_t colorkey_bg_g_low:8; - /** colorkey_bg_r_low : R/W; bitpos: [23:16]; default: 255; - * color key lower threshold of background r channel - */ - uint32_t colorkey_bg_r_low:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_ck_bg_low_reg_t; - -/** Type of ck_bg_high register - * background color key higher threshold - */ -typedef union { - struct { - /** colorkey_bg_b_high : R/W; bitpos: [7:0]; default: 0; - * color key higher threshold of background b channel - */ - uint32_t colorkey_bg_b_high:8; - /** colorkey_bg_g_high : R/W; bitpos: [15:8]; default: 0; - * color key higher threshold of background g channel - */ - uint32_t colorkey_bg_g_high:8; - /** colorkey_bg_r_high : R/W; bitpos: [23:16]; default: 0; - * color key higher threshold of background r channel - */ - uint32_t colorkey_bg_r_high:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_ck_bg_high_reg_t; - -/** Type of ck_default register - * default value when foreground and background both in color key range - */ -typedef union { - struct { - /** colorkey_default_b : R/W; bitpos: [7:0]; default: 0; - * default B channel value of color key - */ - uint32_t colorkey_default_b:8; - /** colorkey_default_g : R/W; bitpos: [15:8]; default: 0; - * default G channel value of color key - */ - uint32_t colorkey_default_g:8; - /** colorkey_default_r : R/W; bitpos: [23:16]; default: 0; - * default R channel value of color key - */ - uint32_t colorkey_default_r:8; - /** colorkey_fg_bg_reverse : R/W; bitpos: [24]; default: 0; - * when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the - * result is fg - */ - uint32_t colorkey_fg_bg_reverse:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} ppa_ck_default_reg_t; - -/** Type of sr_scal_rotate register - * Scaling and rotating coefficient register - */ -typedef union { - struct { - /** sr_scal_x_int : R/W; bitpos: [7:0]; default: 1; - * The integrated part of scaling coefficient in X direction. - */ - uint32_t sr_scal_x_int:8; - /** sr_scal_x_frag : R/W; bitpos: [11:8]; default: 0; - * The fragment part of scaling coefficient in X direction. - */ - uint32_t sr_scal_x_frag:4; - /** sr_scal_y_int : R/W; bitpos: [19:12]; default: 1; - * The integrated part of scaling coefficient in Y direction. - */ - uint32_t sr_scal_y_int:8; - /** sr_scal_y_frag : R/W; bitpos: [23:20]; default: 0; - * The fragment part of scaling coefficient in Y direction. - */ - uint32_t sr_scal_y_frag:4; - /** sr_rotate_angle : R/W; bitpos: [25:24]; default: 0; - * The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree. - */ - uint32_t sr_rotate_angle:2; - /** scal_rotate_rst : R/W; bitpos: [26]; default: 0; - * Write 1 then write 0 to this bit to reset scaling and rotating engine. - */ - uint32_t scal_rotate_rst:1; - /** scal_rotate_start : WT; bitpos: [27]; default: 0; - * Write 1 to enable scaling and rotating engine after parameter is configured. - */ - uint32_t scal_rotate_start:1; - /** sr_mirror_x : R/W; bitpos: [28]; default: 0; - * Image mirror in X direction. 0: disable, 1: enable - */ - uint32_t sr_mirror_x:1; - /** sr_mirror_y : R/W; bitpos: [29]; default: 0; - * Image mirror in Y direction. 0: disable, 1: enable - */ - uint32_t sr_mirror_y:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} ppa_sr_scal_rotate_reg_t; - -/** Type of sr_mem_pd register - * SR memory power done register - */ -typedef union { - struct { - /** sr_mem_clk_ena : R/W; bitpos: [0]; default: 0; - * Set this bit to force clock enable of scaling and rotating engine's data memory. - */ - uint32_t sr_mem_clk_ena:1; - /** sr_mem_force_pd : R/W; bitpos: [1]; default: 0; - * Set this bit to force power down scaling and rotating engine's data memory. - */ - uint32_t sr_mem_force_pd:1; - /** sr_mem_force_pu : R/W; bitpos: [2]; default: 0; - * Set this bit to force power up scaling and rotating engine's data memory. - */ - uint32_t sr_mem_force_pu:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} ppa_sr_mem_pd_reg_t; - -/** Type of reg_conf register - * Register clock enable register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * PPA register clock gate enable signal. - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ppa_reg_conf_reg_t; - -/** Type of eco_low register - * Reserved. - */ -typedef union { - struct { - /** rnd_eco_low : R/W; bitpos: [31:0]; default: 0; - * Reserved. - */ - uint32_t rnd_eco_low:32; - }; - uint32_t val; -} ppa_eco_low_reg_t; - -/** Type of eco_high register - * Reserved. - */ -typedef union { - struct { - /** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295; - * Reserved. - */ - uint32_t rnd_eco_high:32; - }; - uint32_t val; -} ppa_eco_high_reg_t; - -/** Type of sram_ctrl register - * PPA SRAM Control Register - */ -typedef union { - struct { - /** mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; - * Control signals - */ - uint32_t mem_aux_ctrl:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} ppa_sram_ctrl_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of int_raw register - * Raw status interrupt - */ -typedef union { - struct { - /** sr_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when scaling and rotating engine - * calculate one frame image. - */ - uint32_t sr_eof_int_raw:1; - /** blend_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when blending engine calculate one frame - * image. - */ - uint32_t blend_eof_int_raw:1; - /** sr_param_cfg_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the configured scaling and rotating - * coefficient is wrong. User can check the reasons through register - * PPA_SR_PARAM_ERR_ST_REG. - */ - uint32_t sr_param_cfg_err_int_raw:1; - /** blend_param_cfg_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when the configured blending coefficient - * is wrong. User can check the reasons through register PPA_BLEND_ST_REG. - */ - uint32_t blend_param_cfg_err_int_raw:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_int_raw_reg_t; - -/** Type of int_st register - * Masked interrupt - */ -typedef union { - struct { - /** sr_eof_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the PPA_SR_EOF_INT interrupt. - */ - uint32_t sr_eof_int_st:1; - /** blend_eof_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt. - */ - uint32_t blend_eof_int_st:1; - /** sr_param_cfg_err_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t sr_param_cfg_err_int_st:1; - /** blend_param_cfg_err_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t blend_param_cfg_err_int_st:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_int_st_reg_t; - -/** Type of int_ena register - * Interrupt enable bits - */ -typedef union { - struct { - /** sr_eof_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the PPA_SR_EOF_INT interrupt. - */ - uint32_t sr_eof_int_ena:1; - /** blend_eof_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt. - */ - uint32_t blend_eof_int_ena:1; - /** sr_param_cfg_err_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t sr_param_cfg_err_int_ena:1; - /** blend_param_cfg_err_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t blend_param_cfg_err_int_ena:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_int_ena_reg_t; - -/** Type of int_clr register - * Interrupt clear bits - */ -typedef union { - struct { - /** sr_eof_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the PPA_SR_EOF_INT interrupt. - */ - uint32_t sr_eof_int_clr:1; - /** blend_eof_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the PPA_BLEND_EOF_INT interrupt. - */ - uint32_t blend_eof_int_clr:1; - /** sr_param_cfg_err_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. - */ - uint32_t sr_param_cfg_err_int_clr:1; - /** blend_param_cfg_err_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t blend_param_cfg_err_int_clr:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_int_clr_reg_t; - - -/** Group: Status Registers */ -/** Type of clut_cnt register - * BLEND CLUT write counter register - */ -typedef union { - struct { - /** blend0_clut_cnt : RO; bitpos: [8:0]; default: 0; - * The write data counter of BLEND0 CLUT in fifo mode. - */ - uint32_t blend0_clut_cnt:9; - /** blend1_clut_cnt : RO; bitpos: [17:9]; default: 0; - * The write data counter of BLEND1 CLUT in fifo mode. - */ - uint32_t blend1_clut_cnt:9; - uint32_t reserved_18:14; - }; - uint32_t val; -} ppa_clut_cnt_reg_t; - -/** Type of blend_st register - * Blending engine status register - */ -typedef union { - struct { - /** blend_size_diff_st : RO; bitpos: [0]; default: 0; - * 1: indicate the size of two image is different. - */ - uint32_t blend_size_diff_st:1; - /** blend_yuv_x_scale_err_st : RO; bitpos: [1]; default: 0; - * Represents that x param is an odd num when enable yuv422 or yuv420 - */ - uint32_t blend_yuv_x_scale_err_st:1; - /** blend_yuv_y_scale_err_st : RO; bitpos: [2]; default: 0; - * Represents that y param is an odd num when enable yuv420 - */ - uint32_t blend_yuv_y_scale_err_st:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} ppa_blend_st_reg_t; - -/** Type of sr_param_err_st register - * Scaling and rotating coefficient error register - */ -typedef union { - struct { - /** tx_dscr_vb_err_st : RO; bitpos: [0]; default: 0; - * The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive - * descriptor is larger than VA in 2DDMA receive descriptor. - */ - uint32_t tx_dscr_vb_err_st:1; - /** tx_dscr_hb_err_st : RO; bitpos: [1]; default: 0; - * The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive - * descriptor is larger than HA in 2DDMA receive descriptor. - */ - uint32_t tx_dscr_hb_err_st:1; - /** y_rx_scal_equal_0_err_st : RO; bitpos: [2]; default: 0; - * The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0. - */ - uint32_t y_rx_scal_equal_0_err_st:1; - /** rx_dscr_vb_err_st : RO; bitpos: [3]; default: 0; - * The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in - * 2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor - */ - uint32_t rx_dscr_vb_err_st:1; - /** ydst_len_too_samll_err_st : RO; bitpos: [4]; default: 0; - * The error is that the scaled image width is 0. For example. when source width is - * 14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as - * the result would be floored. - */ - uint32_t ydst_len_too_samll_err_st:1; - /** ydst_len_too_large_err_st : RO; bitpos: [5]; default: 0; - * The error is that the scaled width is larger than (2^13 - 1). - */ - uint32_t ydst_len_too_large_err_st:1; - /** x_rx_scal_equal_0_err_st : RO; bitpos: [6]; default: 0; - * The error is that the scaled image height is 0. - */ - uint32_t x_rx_scal_equal_0_err_st:1; - /** rx_dscr_hb_err_st : RO; bitpos: [7]; default: 0; - * The error is that the HB in 2DDMA transmit descriptor plus the offset of X - * coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit - * descriptor. - */ - uint32_t rx_dscr_hb_err_st:1; - /** xdst_len_too_samll_err_st : RO; bitpos: [8]; default: 0; - * The error is that the scaled image height is 0. For example. when source height is - * 14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as - * the result would be floored. - */ - uint32_t xdst_len_too_samll_err_st:1; - /** xdst_len_too_large_err_st : RO; bitpos: [9]; default: 0; - * The error is that the scaled image height is larger than (2^13 - 1). - */ - uint32_t xdst_len_too_large_err_st:1; - /** x_yuv420_rx_scale_err_st : RO; bitpos: [10]; default: 0; - * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable - * yuv422 or yuv420 rx - */ - uint32_t x_yuv420_rx_scale_err_st:1; - /** y_yuv420_rx_scale_err_st : RO; bitpos: [11]; default: 0; - * The error is that the va/vb/y param in dma2d descriptor is an odd num when enable - * yuv420 rx - */ - uint32_t y_yuv420_rx_scale_err_st:1; - /** x_yuv420_tx_scale_err_st : RO; bitpos: [12]; default: 0; - * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable - * yuv422 or yuv420 tx - */ - uint32_t x_yuv420_tx_scale_err_st:1; - /** y_yuv420_tx_scale_err_st : RO; bitpos: [13]; default: 0; - * The error is that the va/vb/y param in dma2d descriptor is an odd num when enable - * yuv420 tx - */ - uint32_t y_yuv420_tx_scale_err_st:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} ppa_sr_param_err_st_reg_t; - -/** Type of sr_status register - * SR FSM register - */ -typedef union { - struct { - /** sr_rx_dscr_sample_state : RO; bitpos: [1:0]; default: 0; - * Reserved. - */ - uint32_t sr_rx_dscr_sample_state:2; - /** sr_rx_scan_state : RO; bitpos: [3:2]; default: 0; - * Reserved. - */ - uint32_t sr_rx_scan_state:2; - /** sr_tx_dscr_sample_state : RO; bitpos: [5:4]; default: 0; - * Reserved. - */ - uint32_t sr_tx_dscr_sample_state:2; - /** sr_tx_scan_state : RO; bitpos: [8:6]; default: 0; - * Reserved. - */ - uint32_t sr_tx_scan_state:3; - uint32_t reserved_9:23; - }; - uint32_t val; -} ppa_sr_status_reg_t; - -/** Type of eco_cell_ctrl register - * Reserved. - */ -typedef union { - struct { - /** rdn_result : RO; bitpos: [0]; default: 0; - * Reserved. - */ - uint32_t rdn_result:1; - /** rdn_ena : R/W; bitpos: [1]; default: 0; - * Reserved. - */ - uint32_t rdn_ena:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} ppa_eco_cell_ctrl_reg_t; - - -/** Group: Debug Register */ -/** Type of debug_ctrl0 register - * debug register - */ -typedef union { - struct { - /** dbg_replace_sel : R/W; bitpos: [2:0]; default: 0; - * Configures the data replace location. 0: not replace, 1: srm rx input, 2: srm rx - * bilin interpolation, 3: srm tx output, 4: blend fg input, 5: blend bg input, 6: - * blend output - */ - uint32_t dbg_replace_sel:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} ppa_debug_ctrl0_reg_t; - -/** Type of debug_ctrl1 register - * debug register - */ -typedef union { - struct { - /** dbg_replace_data : R/W; bitpos: [31:0]; default: 0; - * Configures the replace data - */ - uint32_t dbg_replace_data:32; - }; - uint32_t val; -} ppa_debug_ctrl1_reg_t; - - -/** Group: Configuration Register */ -/** Type of rgb2gray register - * rgb2gray register - */ -typedef union { - struct { - /** rgb2gray_b : R/W; bitpos: [7:0]; default: 85; - * Configures the b parameter for rgb2gray - */ - uint32_t rgb2gray_b:8; - /** rgb2gray_g : R/W; bitpos: [15:8]; default: 86; - * Configures the g parameter for rgb2gray - */ - uint32_t rgb2gray_g:8; - /** rgb2gray_r : R/W; bitpos: [23:16]; default: 85; - * Configures the r parameter for rgb2gray - */ - uint32_t rgb2gray_r:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_rgb2gray_reg_t; - - -/** Group: Version Register */ -/** Type of date register - * PPA Version register - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 539234848; - * register version. - */ - uint32_t date:32; - }; - uint32_t val; -} ppa_date_reg_t; - - -typedef struct ppa_dev_t { - volatile ppa_blend0_clut_data_reg_t blend0_clut_data; - volatile ppa_blend1_clut_data_reg_t blend1_clut_data; - uint32_t reserved_008; - volatile ppa_clut_conf_reg_t clut_conf; - volatile ppa_int_raw_reg_t int_raw; - volatile ppa_int_st_reg_t int_st; - volatile ppa_int_ena_reg_t int_ena; - volatile ppa_int_clr_reg_t int_clr; - volatile ppa_sr_color_mode_reg_t sr_color_mode; - volatile ppa_blend_color_mode_reg_t blend_color_mode; - volatile ppa_sr_byte_order_reg_t sr_byte_order; - volatile ppa_blend_byte_order_reg_t blend_byte_order; - uint32_t reserved_030; - volatile ppa_blend_trans_mode_reg_t blend_trans_mode; - volatile ppa_sr_fix_alpha_reg_t sr_fix_alpha; - volatile ppa_blend_tx_size_reg_t blend_tx_size; - volatile ppa_blend_fix_alpha_reg_t blend_fix_alpha; - uint32_t reserved_044; - volatile ppa_blend_rgb_reg_t blend_rgb; - volatile ppa_blend_fix_pixel_reg_t blend_fix_pixel; - volatile ppa_ck_fg_low_reg_t ck_fg_low; - volatile ppa_ck_fg_high_reg_t ck_fg_high; - volatile ppa_ck_bg_low_reg_t ck_bg_low; - volatile ppa_ck_bg_high_reg_t ck_bg_high; - volatile ppa_ck_default_reg_t ck_default; - volatile ppa_sr_scal_rotate_reg_t sr_scal_rotate; - volatile ppa_sr_mem_pd_reg_t sr_mem_pd; - volatile ppa_reg_conf_reg_t reg_conf; - volatile ppa_clut_cnt_reg_t clut_cnt; - volatile ppa_blend_st_reg_t blend_st; - volatile ppa_sr_param_err_st_reg_t sr_param_err_st; - volatile ppa_sr_status_reg_t sr_status; - volatile ppa_eco_low_reg_t eco_low; - volatile ppa_eco_high_reg_t eco_high; - volatile ppa_eco_cell_ctrl_reg_t eco_cell_ctrl; - volatile ppa_sram_ctrl_reg_t sram_ctrl; - volatile ppa_debug_ctrl0_reg_t debug_ctrl0; - volatile ppa_debug_ctrl1_reg_t debug_ctrl1; - volatile ppa_rgb2gray_reg_t rgb2gray; - uint32_t reserved_09c[25]; - volatile ppa_date_reg_t date; -} ppa_dev_t; - -extern ppa_dev_t PPA; - -#ifndef __cplusplus -_Static_assert(sizeof(ppa_dev_t) == 0x104, "Invalid size of ppa_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h index f843b5b49d..baa0dbb88d 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h @@ -43,10 +43,9 @@ extern "C" { #define PPA_CLUT_CONF_REG (DR_REG_PPA_BASE + 0xc) /** PPA_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0; * 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register - * PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: - * memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr - * should be 01 to access sr clut and should be 10 to access blend0 clut and should be - * 11 to access blend 1 clut in memory mode. + * PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: + * memory mode to wr/rd blend0/blend1 clut RAM. The bit 11 and 10 of the waddr + * should be 01 to access blend0 clut and should be 10 to access blend1 clut in memory mode. */ #define PPA_APB_FIFO_MASK (BIT(0)) #define PPA_APB_FIFO_MASK_M (PPA_APB_FIFO_MASK_V << PPA_APB_FIFO_MASK_S) @@ -225,7 +224,7 @@ extern "C" { #define PPA_BLEND_EOF_INT_CLR_V 0x00000001U #define PPA_BLEND_EOF_INT_CLR_S 1 /** PPA_SR_PARAM_CFG_ERR_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. + * Set this bit to clear the PPA_SR_PARAM_CFG_ERR_INT interrupt. */ #define PPA_SR_PARAM_CFG_ERR_INT_CLR (BIT(2)) #define PPA_SR_PARAM_CFG_ERR_INT_CLR_M (PPA_SR_PARAM_CFG_ERR_INT_CLR_V << PPA_SR_PARAM_CFG_ERR_INT_CLR_S) @@ -273,20 +272,20 @@ extern "C" { #define PPA_YUV_TX_RANGE_M (PPA_YUV_TX_RANGE_V << PPA_YUV_TX_RANGE_S) #define PPA_YUV_TX_RANGE_V 0x00000001U #define PPA_YUV_TX_RANGE_S 9 -/** PPA_YUV2RGB_PROTOCAL : R/W; bitpos: [10]; default: 0; +/** PPA_YUV2RGB_PROTOCOL : R/W; bitpos: [10]; default: 0; * YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709 */ -#define PPA_YUV2RGB_PROTOCAL (BIT(10)) -#define PPA_YUV2RGB_PROTOCAL_M (PPA_YUV2RGB_PROTOCAL_V << PPA_YUV2RGB_PROTOCAL_S) -#define PPA_YUV2RGB_PROTOCAL_V 0x00000001U -#define PPA_YUV2RGB_PROTOCAL_S 10 -/** PPA_RGB2YUV_PROTOCAL : R/W; bitpos: [11]; default: 0; +#define PPA_YUV2RGB_PROTOCOL (BIT(10)) +#define PPA_YUV2RGB_PROTOCOL_M (PPA_YUV2RGB_PROTOCOL_V << PPA_YUV2RGB_PROTOCOL_S) +#define PPA_YUV2RGB_PROTOCOL_V 0x00000001U +#define PPA_YUV2RGB_PROTOCOL_S 10 +/** PPA_RGB2YUV_PROTOCOL : R/W; bitpos: [11]; default: 0; * RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 */ -#define PPA_RGB2YUV_PROTOCAL (BIT(11)) -#define PPA_RGB2YUV_PROTOCAL_M (PPA_RGB2YUV_PROTOCAL_V << PPA_RGB2YUV_PROTOCAL_S) -#define PPA_RGB2YUV_PROTOCAL_V 0x00000001U -#define PPA_RGB2YUV_PROTOCAL_S 11 +#define PPA_RGB2YUV_PROTOCOL (BIT(11)) +#define PPA_RGB2YUV_PROTOCOL_M (PPA_RGB2YUV_PROTOCOL_V << PPA_RGB2YUV_PROTOCOL_S) +#define PPA_RGB2YUV_PROTOCOL_V 0x00000001U +#define PPA_RGB2YUV_PROTOCOL_S 11 /** PPA_YUV422_RX_BYTE_ORDER : R/W; bitpos: [13:12]; default: 0; * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY */ @@ -337,20 +336,20 @@ extern "C" { #define PPA_BLEND_TX_YUV_RANGE_M (PPA_BLEND_TX_YUV_RANGE_V << PPA_BLEND_TX_YUV_RANGE_S) #define PPA_BLEND_TX_YUV_RANGE_V 0x00000001U #define PPA_BLEND_TX_YUV_RANGE_S 13 -/** PPA_BLEND0_RX_YUV2RGB_PROTOCAL : R/W; bitpos: [14]; default: 0; +/** PPA_BLEND0_RX_YUV2RGB_PROTOCOL : R/W; bitpos: [14]; default: 0; * YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709 */ -#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL (BIT(14)) -#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_M (PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V << PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S) -#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V 0x00000001U -#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S 14 -/** PPA_BLEND_TX_RGB2YUV_PROTOCAL : R/W; bitpos: [15]; default: 0; +#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL (BIT(14)) +#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_M (PPA_BLEND0_RX_YUV2RGB_PROTOCOL_V << PPA_BLEND0_RX_YUV2RGB_PROTOCOL_S) +#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_V 0x00000001U +#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_S 14 +/** PPA_BLEND_TX_RGB2YUV_PROTOCOL : R/W; bitpos: [15]; default: 0; * RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709 */ -#define PPA_BLEND_TX_RGB2YUV_PROTOCAL (BIT(15)) -#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_M (PPA_BLEND_TX_RGB2YUV_PROTOCAL_V << PPA_BLEND_TX_RGB2YUV_PROTOCAL_S) -#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_V 0x00000001U -#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_S 15 +#define PPA_BLEND_TX_RGB2YUV_PROTOCOL (BIT(15)) +#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_M (PPA_BLEND_TX_RGB2YUV_PROTOCOL_V << PPA_BLEND_TX_RGB2YUV_PROTOCOL_S) +#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_V 0x00000001U +#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_S 15 /** PPA_BLEND0_RX_YUV422_BYTE_ORDER : R/W; bitpos: [17:16]; default: 0; * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY */ @@ -554,7 +553,7 @@ extern "C" { #define PPA_BLEND1_RX_FIX_ALPHA_S 8 /** PPA_BLEND0_RX_ALPHA_MOD : R/W; bitpos: [17:16]; default: 0; * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + * Original alpha multiply with PPA_SR_BLEND0_ALPHA/256. */ #define PPA_BLEND0_RX_ALPHA_MOD 0x00000003U #define PPA_BLEND0_RX_ALPHA_MOD_M (PPA_BLEND0_RX_ALPHA_MOD_V << PPA_BLEND0_RX_ALPHA_MOD_S) @@ -562,7 +561,7 @@ extern "C" { #define PPA_BLEND0_RX_ALPHA_MOD_S 16 /** PPA_BLEND1_RX_ALPHA_MOD : R/W; bitpos: [19:18]; default: 0; * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + * Original alpha multiply with PPA_SR_BLEND1_ALPHA/256. */ #define PPA_BLEND1_RX_ALPHA_MOD 0x00000003U #define PPA_BLEND1_RX_ALPHA_MOD_M (PPA_BLEND1_RX_ALPHA_MOD_V << PPA_BLEND1_RX_ALPHA_MOD_S) diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h index fe85942a62..855a9df1e9 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h @@ -91,12 +91,12 @@ typedef union { struct { /** sr_rx_cm : R/W; bitpos: [3:0]; default: 0; * The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: - * RGB888. 2: RGB565. 8: YUV420. others: Reserved. + * RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. */ uint32_t sr_rx_cm:4; /** sr_tx_cm : R/W; bitpos: [7:4]; default: 0; * The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. - * 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved. + * 1: RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. */ uint32_t sr_tx_cm:4; /** yuv_rx_range : R/W; bitpos: [8]; default: 0; @@ -115,7 +115,11 @@ typedef union { * RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 */ uint32_t rgb2yuv_protocol:1; - uint32_t reserved_12:20; + /** yuv422_rx_byte_order : R/W; bitpos: [13:12]; default: 0; + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY + */ + uint32_t yuv422_rx_byte_order:2; + uint32_t reserved_14:18; }; uint32_t val; } ppa_sr_color_mode_reg_t; @@ -127,7 +131,7 @@ typedef union { struct { /** blend0_rx_cm : R/W; bitpos: [3:0]; default: 0; * The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved. 4: L8. 5: L4. + * RGB565. 3: Reserved. 4: L8. 5: L4. 8: YUV420. 9: YUV422. 12:GRAY */ uint32_t blend0_rx_cm:4; /** blend1_rx_cm : R/W; bitpos: [7:4]; default: 0; @@ -137,10 +141,30 @@ typedef union { uint32_t blend1_rx_cm:4; /** blend_tx_cm : R/W; bitpos: [11:8]; default: 0; * The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved.. + * RGB565. 3: Reserved. 8: YUV420. 9: YUV422. 12:GRAY */ uint32_t blend_tx_cm:4; - uint32_t reserved_12:20; + /** blend0_rx_yuv_range : R/W; bitpos: [12]; default: 0; + * YUV input range when blend0 rx cm is yuv. 0: limit range. 1: full range + */ + uint32_t blend0_rx_yuv_range:1; + /** blend_tx_yuv_range : R/W; bitpos: [13]; default: 0; + * YUV output range when blend tx cm is yuv. 0: limit range. 1: full range + */ + uint32_t blend_tx_yuv_range:1; + /** blend0_rx_yuv2rgb_protocol : R/W; bitpos: [14]; default: 0; + * YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709 + */ + uint32_t blend0_rx_yuv2rgb_protocol:1; + /** blend_tx_rgb2yuv_protocol : R/W; bitpos: [15]; default: 0; + * RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709 + */ + uint32_t blend_tx_rgb2yuv_protocol:1; + /** blend0_rx_yuv422_byte_order : R/W; bitpos: [17:16]; default: 0; + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY + */ + uint32_t blend0_rx_yuv422_byte_order:2; + uint32_t reserved_18:14; }; uint32_t val; } ppa_blend_color_mode_reg_t; @@ -165,7 +189,11 @@ typedef union { * to improve efficient accessing external memory. */ uint32_t sr_macro_bk_ro_bypass:1; - uint32_t reserved_3:29; + /** sr_bk_size_sel : R/W; bitpos: [3]; default: 0; + * sel srm pix_blk size, 0:32x32, 1:16x16 + */ + uint32_t sr_bk_size_sel:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_sr_byte_order_reg_t; @@ -227,7 +255,12 @@ typedef union { * write 1 then write 0 to reset blending engine. */ uint32_t blend_rst:1; - uint32_t reserved_5:27; + /** blend_tx_inf_sel : R/W; bitpos: [6:5]; default: 0; + * unused ! Configures blend tx interface. 0: dma2d only, 1: le_enc only, 2: dma2d and + * ls_enc + */ + uint32_t blend_tx_inf_sel:2; + uint32_t reserved_7:25; }; uint32_t val; } ppa_blend_trans_mode_reg_t; @@ -263,13 +296,13 @@ typedef union { typedef union { struct { /** blend_hb : R/W; bitpos: [13:0]; default: 0; - * The horizontal width of image block that would be filled in fix pixel filling mode. - * The unit is pixel + * The horizontal width of image block that would be filled in fix pixel filling mode + * or blend mode. The unit is pixel. Must be even num when YUV422 or YUV420 */ uint32_t blend_hb:14; /** blend_vb : R/W; bitpos: [27:14]; default: 0; - * The vertical width of image block that would be filled in fix pixel filling mode. - * The unit is pixel + * The vertical width of image block that would be filled in fix pixel filling mode or + * blend mode. The unit is pixel. Must be even num when YUV420 */ uint32_t blend_vb:14; uint32_t reserved_28:4; @@ -293,13 +326,13 @@ typedef union { */ uint32_t blend1_rx_fix_alpha:8; /** blend0_rx_alpha_mod : R/W; bitpos: [17:16]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2: + * Original alpha multiply with PPA_BLEND0_FIX_ALPHA/256. */ uint32_t blend0_rx_alpha_mod:2; /** blend1_rx_alpha_mod : R/W; bitpos: [19:18]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2: + * Original alpha multiply with PPA_BLEND1_FIX_ALPHA/256. */ uint32_t blend1_rx_alpha_mod:2; /** blend0_rx_alpha_inv : R/W; bitpos: [20]; default: 0; @@ -612,7 +645,12 @@ typedef union { * PPA_SR_PARAM_ERR_ST_REG. */ uint32_t sr_param_cfg_err_int_raw:1; - uint32_t reserved_3:29; + /** blend_param_cfg_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when the configured blending coefficient + * is wrong. User can check the reasons through register PPA_BLEND_ST_REG. + */ + uint32_t blend_param_cfg_err_int_raw:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_int_raw_reg_t; @@ -631,10 +669,14 @@ typedef union { */ uint32_t blend_eof_int_st:1; /** sr_param_cfg_err_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + * The raw interrupt status bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. */ uint32_t sr_param_cfg_err_int_st:1; - uint32_t reserved_3:29; + /** blend_param_cfg_err_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ + uint32_t blend_param_cfg_err_int_st:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_int_st_reg_t; @@ -653,10 +695,14 @@ typedef union { */ uint32_t blend_eof_int_ena:1; /** sr_param_cfg_err_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + * The interrupt enable bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. */ uint32_t sr_param_cfg_err_int_ena:1; - uint32_t reserved_3:29; + /** blend_param_cfg_err_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ + uint32_t blend_param_cfg_err_int_ena:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_int_ena_reg_t; @@ -675,10 +721,14 @@ typedef union { */ uint32_t blend_eof_int_clr:1; /** sr_param_cfg_err_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. + * Set this bit to clear the PPA_SR_PARAM_CFG_ERR_INT interrupt. */ uint32_t sr_param_cfg_err_int_clr:1; - uint32_t reserved_3:29; + /** blend_param_cfg_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ + uint32_t blend_param_cfg_err_int_clr:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_int_clr_reg_t; @@ -712,7 +762,15 @@ typedef union { * 1: indicate the size of two image is different. */ uint32_t blend_size_diff_st:1; - uint32_t reserved_1:31; + /** blend_yuv_x_scale_err_st : RO; bitpos: [1]; default: 0; + * Represents that x param is an odd num when enable yuv422 or yuv420 + */ + uint32_t blend_yuv_x_scale_err_st:1; + /** blend_yuv_y_scale_err_st : RO; bitpos: [2]; default: 0; + * Represents that y param is an odd num when enable yuv420 + */ + uint32_t blend_yuv_y_scale_err_st:1; + uint32_t reserved_3:29; }; uint32_t val; } ppa_blend_st_reg_t; @@ -773,7 +831,7 @@ typedef union { uint32_t xdst_len_too_large_err_st:1; /** x_yuv420_rx_scale_err_st : RO; bitpos: [10]; default: 0; * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable - * yuv420 rx + * yuv422 or yuv420 rx */ uint32_t x_yuv420_rx_scale_err_st:1; /** y_yuv420_rx_scale_err_st : RO; bitpos: [11]; default: 0; @@ -783,7 +841,7 @@ typedef union { uint32_t y_yuv420_rx_scale_err_st:1; /** x_yuv420_tx_scale_err_st : RO; bitpos: [12]; default: 0; * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable - * yuv420 tx + * yuv422 or yuv420 tx */ uint32_t x_yuv420_tx_scale_err_st:1; /** y_yuv420_tx_scale_err_st : RO; bitpos: [13]; default: 0; @@ -841,13 +899,68 @@ typedef union { } ppa_eco_cell_ctrl_reg_t; +/** Group: Debug Register */ +/** Type of debug_ctrl0 register + * debug register + */ +typedef union { + struct { + /** dbg_replace_sel : R/W; bitpos: [2:0]; default: 0; + * Configures the data replace location. 0: not replace, 1: srm rx input, 2: srm rx + * bilin interpolation, 3: srm tx output, 4: blend fg input, 5: blend bg input, 6: + * blend output + */ + uint32_t dbg_replace_sel:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} ppa_debug_ctrl0_reg_t; + +/** Type of debug_ctrl1 register + * debug register + */ +typedef union { + struct { + /** dbg_replace_data : R/W; bitpos: [31:0]; default: 0; + * Configures the replace data + */ + uint32_t dbg_replace_data:32; + }; + uint32_t val; +} ppa_debug_ctrl1_reg_t; + + +/** Group: Configuration Register */ +/** Type of rgb2gray register + * rgb2gray register + */ +typedef union { + struct { + /** rgb2gray_b : R/W; bitpos: [7:0]; default: 85; + * Configures the b parameter for rgb2gray + */ + uint32_t rgb2gray_b:8; + /** rgb2gray_g : R/W; bitpos: [15:8]; default: 86; + * Configures the g parameter for rgb2gray + */ + uint32_t rgb2gray_g:8; + /** rgb2gray_r : R/W; bitpos: [23:16]; default: 85; + * Configures the r parameter for rgb2gray + */ + uint32_t rgb2gray_r:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} ppa_rgb2gray_reg_t; + + /** Group: Version Register */ /** Type of date register * PPA Version register */ typedef union { struct { - /** date : R/W; bitpos: [31:0]; default: 36716609; + /** date : R/W; bitpos: [31:0]; default: 539234848; * register version. */ uint32_t date:32; @@ -893,7 +1006,10 @@ typedef struct ppa_dev_t { volatile ppa_eco_high_reg_t eco_high; volatile ppa_eco_cell_ctrl_reg_t eco_cell_ctrl; volatile ppa_sram_ctrl_reg_t sram_ctrl; - uint32_t reserved_090[28]; + volatile ppa_debug_ctrl0_reg_t debug_ctrl0; + volatile ppa_debug_ctrl1_reg_t debug_ctrl1; + volatile ppa_rgb2gray_reg_t rgb2gray; + uint32_t reserved_09c[25]; volatile ppa_date_reg_t date; } ppa_dev_t; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_reg.h deleted file mode 100644 index c782014e86..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_reg.h +++ /dev/null @@ -1,1579 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** UART_FIFO_REG register - * FIFO data register - */ -#define UART_FIFO_REG(i) (DR_REG_UART_BASE(i) + 0x0) -/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; - * UART $n accesses FIFO via this register. - */ -#define UART_RXFIFO_RD_BYTE 0x000000FFU -#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) -#define UART_RXFIFO_RD_BYTE_V 0x000000FFU -#define UART_RXFIFO_RD_BYTE_S 0 - -/** UART_INT_RAW_REG register - * Raw interrupt status - */ -#define UART_INT_RAW_REG(i) (DR_REG_UART_BASE(i) + 0x4) -/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * This interrupt raw bit turns to high level when receiver receives more data than - * what rxfifo_full_thrhd specifies. - */ -#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) -#define UART_RXFIFO_FULL_INT_RAW_M (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S) -#define UART_RXFIFO_FULL_INT_RAW_V 0x00000001U -#define UART_RXFIFO_FULL_INT_RAW_S 0 -/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; - * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is - * less than what txfifo_empty_thrhd specifies . - */ -#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_RAW_M (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S) -#define UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001U -#define UART_TXFIFO_EMPTY_INT_RAW_S 1 -/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a parity error in - * the data. - */ -#define UART_PARITY_ERR_INT_RAW (BIT(2)) -#define UART_PARITY_ERR_INT_RAW_M (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S) -#define UART_PARITY_ERR_INT_RAW_V 0x00000001U -#define UART_PARITY_ERR_INT_RAW_S 2 -/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a data frame error - * . - */ -#define UART_FRM_ERR_INT_RAW (BIT(3)) -#define UART_FRM_ERR_INT_RAW_M (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S) -#define UART_FRM_ERR_INT_RAW_V 0x00000001U -#define UART_FRM_ERR_INT_RAW_S 3 -/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * This interrupt raw bit turns to high level when receiver receives more data than - * the FIFO can store. - */ -#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) -#define UART_RXFIFO_OVF_INT_RAW_M (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S) -#define UART_RXFIFO_OVF_INT_RAW_V 0x00000001U -#define UART_RXFIFO_OVF_INT_RAW_S 4 -/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the edge change of - * DSRn signal. - */ -#define UART_DSR_CHG_INT_RAW (BIT(5)) -#define UART_DSR_CHG_INT_RAW_M (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S) -#define UART_DSR_CHG_INT_RAW_V 0x00000001U -#define UART_DSR_CHG_INT_RAW_S 5 -/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the edge change of - * CTSn signal. - */ -#define UART_CTS_CHG_INT_RAW (BIT(6)) -#define UART_CTS_CHG_INT_RAW_M (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S) -#define UART_CTS_CHG_INT_RAW_V 0x00000001U -#define UART_CTS_CHG_INT_RAW_S 6 -/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a 0 after the stop - * bit. - */ -#define UART_BRK_DET_INT_RAW (BIT(7)) -#define UART_BRK_DET_INT_RAW_M (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S) -#define UART_BRK_DET_INT_RAW_V 0x00000001U -#define UART_BRK_DET_INT_RAW_S 7 -/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * This interrupt raw bit turns to high level when receiver takes more time than - * rx_tout_thrhd to receive a byte. - */ -#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) -#define UART_RXFIFO_TOUT_INT_RAW_M (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S) -#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U -#define UART_RXFIFO_TOUT_INT_RAW_S 8 -/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver receives Xon char when - * uart_sw_flow_con_en is set to 1. - */ -#define UART_SW_XON_INT_RAW (BIT(9)) -#define UART_SW_XON_INT_RAW_M (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S) -#define UART_SW_XON_INT_RAW_V 0x00000001U -#define UART_SW_XON_INT_RAW_S 9 -/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * This interrupt raw bit turns to high level when receiver receives Xoff char when - * uart_sw_flow_con_en is set to 1. - */ -#define UART_SW_XOFF_INT_RAW (BIT(10)) -#define UART_SW_XOFF_INT_RAW_M (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S) -#define UART_SW_XOFF_INT_RAW_V 0x00000001U -#define UART_SW_XOFF_INT_RAW_S 10 -/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a glitch in the - * middle of a start bit. - */ -#define UART_GLITCH_DET_INT_RAW (BIT(11)) -#define UART_GLITCH_DET_INT_RAW_M (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S) -#define UART_GLITCH_DET_INT_RAW_V 0x00000001U -#define UART_GLITCH_DET_INT_RAW_S 11 -/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * This interrupt raw bit turns to high level when transmitter completes sending - * NULL characters after all data in Tx-FIFO are sent. - */ -#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) -#define UART_TX_BRK_DONE_INT_RAW_M (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S) -#define UART_TX_BRK_DONE_INT_RAW_V 0x00000001U -#define UART_TX_BRK_DONE_INT_RAW_S 12 -/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * This interrupt raw bit turns to high level when transmitter has kept the shortest - * duration after sending the last data. - */ -#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S) -#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001U -#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 -/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; - * This interrupt raw bit turns to high level when transmitter has send out all data - * in FIFO. - */ -#define UART_TX_DONE_INT_RAW (BIT(14)) -#define UART_TX_DONE_INT_RAW_M (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S) -#define UART_TX_DONE_INT_RAW_V 0x00000001U -#define UART_TX_DONE_INT_RAW_S 14 -/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a parity error - * from the echo of transmitter in rs485 mode. - */ -#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_RAW_M (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S) -#define UART_RS485_PARITY_ERR_INT_RAW_V 0x00000001U -#define UART_RS485_PARITY_ERR_INT_RAW_S 15 -/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a data frame error - * from the echo of transmitter in rs485 mode. - */ -#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) -#define UART_RS485_FRM_ERR_INT_RAW_M (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S) -#define UART_RS485_FRM_ERR_INT_RAW_V 0x00000001U -#define UART_RS485_FRM_ERR_INT_RAW_S 16 -/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; - * This interrupt raw bit turns to high level when detects a clash between transmitter - * and receiver in rs485 mode. - */ -#define UART_RS485_CLASH_INT_RAW (BIT(17)) -#define UART_RS485_CLASH_INT_RAW_M (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S) -#define UART_RS485_CLASH_INT_RAW_V 0x00000001U -#define UART_RS485_CLASH_INT_RAW_S 17 -/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the configured - * at_cmd char. - */ -#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_RAW_M (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S) -#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001U -#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 -/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; - * This interrupt raw bit turns to high level when input rxd edge changes more times - * than what reg_active_threshold specifies in light sleeping mode. - */ -#define UART_WAKEUP_INT_RAW (BIT(19)) -#define UART_WAKEUP_INT_RAW_M (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S) -#define UART_WAKEUP_INT_RAW_V 0x00000001U -#define UART_WAKEUP_INT_RAW_S 19 - -/** UART_INT_ST_REG register - * Masked interrupt status - */ -#define UART_INT_ST_REG(i) (DR_REG_UART_BASE(i) + 0x8) -/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; - * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. - */ -#define UART_RXFIFO_FULL_INT_ST (BIT(0)) -#define UART_RXFIFO_FULL_INT_ST_M (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S) -#define UART_RXFIFO_FULL_INT_ST_V 0x00000001U -#define UART_RXFIFO_FULL_INT_ST_S 0 -/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; - * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set - * to 1. - */ -#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ST_M (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S) -#define UART_TXFIFO_EMPTY_INT_ST_V 0x00000001U -#define UART_TXFIFO_EMPTY_INT_ST_S 1 -/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; - * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. - */ -#define UART_PARITY_ERR_INT_ST (BIT(2)) -#define UART_PARITY_ERR_INT_ST_M (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S) -#define UART_PARITY_ERR_INT_ST_V 0x00000001U -#define UART_PARITY_ERR_INT_ST_S 2 -/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; - * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. - */ -#define UART_FRM_ERR_INT_ST (BIT(3)) -#define UART_FRM_ERR_INT_ST_M (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S) -#define UART_FRM_ERR_INT_ST_V 0x00000001U -#define UART_FRM_ERR_INT_ST_S 3 -/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; - * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. - */ -#define UART_RXFIFO_OVF_INT_ST (BIT(4)) -#define UART_RXFIFO_OVF_INT_ST_M (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S) -#define UART_RXFIFO_OVF_INT_ST_V 0x00000001U -#define UART_RXFIFO_OVF_INT_ST_S 4 -/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; - * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. - */ -#define UART_DSR_CHG_INT_ST (BIT(5)) -#define UART_DSR_CHG_INT_ST_M (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S) -#define UART_DSR_CHG_INT_ST_V 0x00000001U -#define UART_DSR_CHG_INT_ST_S 5 -/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; - * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. - */ -#define UART_CTS_CHG_INT_ST (BIT(6)) -#define UART_CTS_CHG_INT_ST_M (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S) -#define UART_CTS_CHG_INT_ST_V 0x00000001U -#define UART_CTS_CHG_INT_ST_S 6 -/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; - * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. - */ -#define UART_BRK_DET_INT_ST (BIT(7)) -#define UART_BRK_DET_INT_ST_M (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S) -#define UART_BRK_DET_INT_ST_V 0x00000001U -#define UART_BRK_DET_INT_ST_S 7 -/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; - * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. - */ -#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ST_M (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S) -#define UART_RXFIFO_TOUT_INT_ST_V 0x00000001U -#define UART_RXFIFO_TOUT_INT_ST_S 8 -/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; - * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. - */ -#define UART_SW_XON_INT_ST (BIT(9)) -#define UART_SW_XON_INT_ST_M (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S) -#define UART_SW_XON_INT_ST_V 0x00000001U -#define UART_SW_XON_INT_ST_S 9 -/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; - * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. - */ -#define UART_SW_XOFF_INT_ST (BIT(10)) -#define UART_SW_XOFF_INT_ST_M (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S) -#define UART_SW_XOFF_INT_ST_V 0x00000001U -#define UART_SW_XOFF_INT_ST_S 10 -/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; - * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. - */ -#define UART_GLITCH_DET_INT_ST (BIT(11)) -#define UART_GLITCH_DET_INT_ST_M (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S) -#define UART_GLITCH_DET_INT_ST_V 0x00000001U -#define UART_GLITCH_DET_INT_ST_S 11 -/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; - * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. - */ -#define UART_TX_BRK_DONE_INT_ST (BIT(12)) -#define UART_TX_BRK_DONE_INT_ST_M (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S) -#define UART_TX_BRK_DONE_INT_ST_V 0x00000001U -#define UART_TX_BRK_DONE_INT_ST_S 12 -/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; - * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena - * is set to 1. - */ -#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ST_M (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S) -#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001U -#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 -/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; - * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. - */ -#define UART_TX_DONE_INT_ST (BIT(14)) -#define UART_TX_DONE_INT_ST_M (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S) -#define UART_TX_DONE_INT_ST_V 0x00000001U -#define UART_TX_DONE_INT_ST_S 14 -/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0; - * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is - * set to 1. - */ -#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ST_M (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S) -#define UART_RS485_PARITY_ERR_INT_ST_V 0x00000001U -#define UART_RS485_PARITY_ERR_INT_ST_S 15 -/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0; - * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set - * to 1. - */ -#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ST_M (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S) -#define UART_RS485_FRM_ERR_INT_ST_V 0x00000001U -#define UART_RS485_FRM_ERR_INT_ST_S 16 -/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0; - * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. - */ -#define UART_RS485_CLASH_INT_ST (BIT(17)) -#define UART_RS485_CLASH_INT_ST_M (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S) -#define UART_RS485_CLASH_INT_ST_V 0x00000001U -#define UART_RS485_CLASH_INT_ST_S 17 -/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; - * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set - * to 1. - */ -#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ST_M (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S) -#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001U -#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 -/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; - * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. - */ -#define UART_WAKEUP_INT_ST (BIT(19)) -#define UART_WAKEUP_INT_ST_M (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S) -#define UART_WAKEUP_INT_ST_V 0x00000001U -#define UART_WAKEUP_INT_ST_S 19 - -/** UART_INT_ENA_REG register - * Interrupt enable bits - */ -#define UART_INT_ENA_REG(i) (DR_REG_UART_BASE(i) + 0xc) -/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; - * This is the enable bit for rxfifo_full_int_st register. - */ -#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) -#define UART_RXFIFO_FULL_INT_ENA_M (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S) -#define UART_RXFIFO_FULL_INT_ENA_V 0x00000001U -#define UART_RXFIFO_FULL_INT_ENA_S 0 -/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; - * This is the enable bit for txfifo_empty_int_st register. - */ -#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ENA_M (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S) -#define UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001U -#define UART_TXFIFO_EMPTY_INT_ENA_S 1 -/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; - * This is the enable bit for parity_err_int_st register. - */ -#define UART_PARITY_ERR_INT_ENA (BIT(2)) -#define UART_PARITY_ERR_INT_ENA_M (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S) -#define UART_PARITY_ERR_INT_ENA_V 0x00000001U -#define UART_PARITY_ERR_INT_ENA_S 2 -/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; - * This is the enable bit for frm_err_int_st register. - */ -#define UART_FRM_ERR_INT_ENA (BIT(3)) -#define UART_FRM_ERR_INT_ENA_M (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S) -#define UART_FRM_ERR_INT_ENA_V 0x00000001U -#define UART_FRM_ERR_INT_ENA_S 3 -/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; - * This is the enable bit for rxfifo_ovf_int_st register. - */ -#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) -#define UART_RXFIFO_OVF_INT_ENA_M (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S) -#define UART_RXFIFO_OVF_INT_ENA_V 0x00000001U -#define UART_RXFIFO_OVF_INT_ENA_S 4 -/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; - * This is the enable bit for dsr_chg_int_st register. - */ -#define UART_DSR_CHG_INT_ENA (BIT(5)) -#define UART_DSR_CHG_INT_ENA_M (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S) -#define UART_DSR_CHG_INT_ENA_V 0x00000001U -#define UART_DSR_CHG_INT_ENA_S 5 -/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; - * This is the enable bit for cts_chg_int_st register. - */ -#define UART_CTS_CHG_INT_ENA (BIT(6)) -#define UART_CTS_CHG_INT_ENA_M (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S) -#define UART_CTS_CHG_INT_ENA_V 0x00000001U -#define UART_CTS_CHG_INT_ENA_S 6 -/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; - * This is the enable bit for brk_det_int_st register. - */ -#define UART_BRK_DET_INT_ENA (BIT(7)) -#define UART_BRK_DET_INT_ENA_M (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S) -#define UART_BRK_DET_INT_ENA_V 0x00000001U -#define UART_BRK_DET_INT_ENA_S 7 -/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; - * This is the enable bit for rxfifo_tout_int_st register. - */ -#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ENA_M (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S) -#define UART_RXFIFO_TOUT_INT_ENA_V 0x00000001U -#define UART_RXFIFO_TOUT_INT_ENA_S 8 -/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; - * This is the enable bit for sw_xon_int_st register. - */ -#define UART_SW_XON_INT_ENA (BIT(9)) -#define UART_SW_XON_INT_ENA_M (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S) -#define UART_SW_XON_INT_ENA_V 0x00000001U -#define UART_SW_XON_INT_ENA_S 9 -/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; - * This is the enable bit for sw_xoff_int_st register. - */ -#define UART_SW_XOFF_INT_ENA (BIT(10)) -#define UART_SW_XOFF_INT_ENA_M (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S) -#define UART_SW_XOFF_INT_ENA_V 0x00000001U -#define UART_SW_XOFF_INT_ENA_S 10 -/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; - * This is the enable bit for glitch_det_int_st register. - */ -#define UART_GLITCH_DET_INT_ENA (BIT(11)) -#define UART_GLITCH_DET_INT_ENA_M (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S) -#define UART_GLITCH_DET_INT_ENA_V 0x00000001U -#define UART_GLITCH_DET_INT_ENA_S 11 -/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; - * This is the enable bit for tx_brk_done_int_st register. - */ -#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) -#define UART_TX_BRK_DONE_INT_ENA_M (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S) -#define UART_TX_BRK_DONE_INT_ENA_V 0x00000001U -#define UART_TX_BRK_DONE_INT_ENA_S 12 -/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; - * This is the enable bit for tx_brk_idle_done_int_st register. - */ -#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S) -#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001U -#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 -/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; - * This is the enable bit for tx_done_int_st register. - */ -#define UART_TX_DONE_INT_ENA (BIT(14)) -#define UART_TX_DONE_INT_ENA_M (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S) -#define UART_TX_DONE_INT_ENA_V 0x00000001U -#define UART_TX_DONE_INT_ENA_S 14 -/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; - * This is the enable bit for rs485_parity_err_int_st register. - */ -#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ENA_M (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S) -#define UART_RS485_PARITY_ERR_INT_ENA_V 0x00000001U -#define UART_RS485_PARITY_ERR_INT_ENA_S 15 -/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; - * This is the enable bit for rs485_parity_err_int_st register. - */ -#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ENA_M (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S) -#define UART_RS485_FRM_ERR_INT_ENA_V 0x00000001U -#define UART_RS485_FRM_ERR_INT_ENA_S 16 -/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0; - * This is the enable bit for rs485_clash_int_st register. - */ -#define UART_RS485_CLASH_INT_ENA (BIT(17)) -#define UART_RS485_CLASH_INT_ENA_M (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S) -#define UART_RS485_CLASH_INT_ENA_V 0x00000001U -#define UART_RS485_CLASH_INT_ENA_S 17 -/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; - * This is the enable bit for at_cmd_char_det_int_st register. - */ -#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ENA_M (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S) -#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001U -#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 -/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; - * This is the enable bit for uart_wakeup_int_st register. - */ -#define UART_WAKEUP_INT_ENA (BIT(19)) -#define UART_WAKEUP_INT_ENA_M (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S) -#define UART_WAKEUP_INT_ENA_V 0x00000001U -#define UART_WAKEUP_INT_ENA_S 19 - -/** UART_INT_CLR_REG register - * Interrupt clear bits - */ -#define UART_INT_CLR_REG(i) (DR_REG_UART_BASE(i) + 0x10) -/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the rxfifo_full_int_raw interrupt. - */ -#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) -#define UART_RXFIFO_FULL_INT_CLR_M (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S) -#define UART_RXFIFO_FULL_INT_CLR_V 0x00000001U -#define UART_RXFIFO_FULL_INT_CLR_S 0 -/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear txfifo_empty_int_raw interrupt. - */ -#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_CLR_M (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S) -#define UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001U -#define UART_TXFIFO_EMPTY_INT_CLR_S 1 -/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear parity_err_int_raw interrupt. - */ -#define UART_PARITY_ERR_INT_CLR (BIT(2)) -#define UART_PARITY_ERR_INT_CLR_M (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S) -#define UART_PARITY_ERR_INT_CLR_V 0x00000001U -#define UART_PARITY_ERR_INT_CLR_S 2 -/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear frm_err_int_raw interrupt. - */ -#define UART_FRM_ERR_INT_CLR (BIT(3)) -#define UART_FRM_ERR_INT_CLR_M (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S) -#define UART_FRM_ERR_INT_CLR_V 0x00000001U -#define UART_FRM_ERR_INT_CLR_S 3 -/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear rxfifo_ovf_int_raw interrupt. - */ -#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) -#define UART_RXFIFO_OVF_INT_CLR_M (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S) -#define UART_RXFIFO_OVF_INT_CLR_V 0x00000001U -#define UART_RXFIFO_OVF_INT_CLR_S 4 -/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the dsr_chg_int_raw interrupt. - */ -#define UART_DSR_CHG_INT_CLR (BIT(5)) -#define UART_DSR_CHG_INT_CLR_M (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S) -#define UART_DSR_CHG_INT_CLR_V 0x00000001U -#define UART_DSR_CHG_INT_CLR_S 5 -/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the cts_chg_int_raw interrupt. - */ -#define UART_CTS_CHG_INT_CLR (BIT(6)) -#define UART_CTS_CHG_INT_CLR_M (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S) -#define UART_CTS_CHG_INT_CLR_V 0x00000001U -#define UART_CTS_CHG_INT_CLR_S 6 -/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the brk_det_int_raw interrupt. - */ -#define UART_BRK_DET_INT_CLR (BIT(7)) -#define UART_BRK_DET_INT_CLR_M (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S) -#define UART_BRK_DET_INT_CLR_V 0x00000001U -#define UART_BRK_DET_INT_CLR_S 7 -/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the rxfifo_tout_int_raw interrupt. - */ -#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) -#define UART_RXFIFO_TOUT_INT_CLR_M (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S) -#define UART_RXFIFO_TOUT_INT_CLR_V 0x00000001U -#define UART_RXFIFO_TOUT_INT_CLR_S 8 -/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the sw_xon_int_raw interrupt. - */ -#define UART_SW_XON_INT_CLR (BIT(9)) -#define UART_SW_XON_INT_CLR_M (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S) -#define UART_SW_XON_INT_CLR_V 0x00000001U -#define UART_SW_XON_INT_CLR_S 9 -/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the sw_xoff_int_raw interrupt. - */ -#define UART_SW_XOFF_INT_CLR (BIT(10)) -#define UART_SW_XOFF_INT_CLR_M (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S) -#define UART_SW_XOFF_INT_CLR_V 0x00000001U -#define UART_SW_XOFF_INT_CLR_S 10 -/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the glitch_det_int_raw interrupt. - */ -#define UART_GLITCH_DET_INT_CLR (BIT(11)) -#define UART_GLITCH_DET_INT_CLR_M (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S) -#define UART_GLITCH_DET_INT_CLR_V 0x00000001U -#define UART_GLITCH_DET_INT_CLR_S 11 -/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the tx_brk_done_int_raw interrupt.. - */ -#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) -#define UART_TX_BRK_DONE_INT_CLR_M (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S) -#define UART_TX_BRK_DONE_INT_CLR_V 0x00000001U -#define UART_TX_BRK_DONE_INT_CLR_S 12 -/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. - */ -#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S) -#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001U -#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 -/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; - * Set this bit to clear the tx_done_int_raw interrupt. - */ -#define UART_TX_DONE_INT_CLR (BIT(14)) -#define UART_TX_DONE_INT_CLR_M (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S) -#define UART_TX_DONE_INT_CLR_V 0x00000001U -#define UART_TX_DONE_INT_CLR_S 14 -/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0; - * Set this bit to clear the rs485_parity_err_int_raw interrupt. - */ -#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_CLR_M (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S) -#define UART_RS485_PARITY_ERR_INT_CLR_V 0x00000001U -#define UART_RS485_PARITY_ERR_INT_CLR_S 15 -/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0; - * Set this bit to clear the rs485_frm_err_int_raw interrupt. - */ -#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) -#define UART_RS485_FRM_ERR_INT_CLR_M (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S) -#define UART_RS485_FRM_ERR_INT_CLR_V 0x00000001U -#define UART_RS485_FRM_ERR_INT_CLR_S 16 -/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0; - * Set this bit to clear the rs485_clash_int_raw interrupt. - */ -#define UART_RS485_CLASH_INT_CLR (BIT(17)) -#define UART_RS485_CLASH_INT_CLR_M (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S) -#define UART_RS485_CLASH_INT_CLR_V 0x00000001U -#define UART_RS485_CLASH_INT_CLR_S 17 -/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; - * Set this bit to clear the at_cmd_char_det_int_raw interrupt. - */ -#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_CLR_M (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S) -#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001U -#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 -/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; - * Set this bit to clear the uart_wakeup_int_raw interrupt. - */ -#define UART_WAKEUP_INT_CLR (BIT(19)) -#define UART_WAKEUP_INT_CLR_M (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S) -#define UART_WAKEUP_INT_CLR_V 0x00000001U -#define UART_WAKEUP_INT_CLR_S 19 - -/** UART_CLKDIV_SYNC_REG register - * Clock divider configuration - */ -#define UART_CLKDIV_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x14) -/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; - * The integral part of the frequency divider factor. - */ -#define UART_CLKDIV 0x00000FFFU -#define UART_CLKDIV_M (UART_CLKDIV_V << UART_CLKDIV_S) -#define UART_CLKDIV_V 0x00000FFFU -#define UART_CLKDIV_S 0 -/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; - * The decimal part of the frequency divider factor. - */ -#define UART_CLKDIV_FRAG 0x0000000FU -#define UART_CLKDIV_FRAG_M (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S) -#define UART_CLKDIV_FRAG_V 0x0000000FU -#define UART_CLKDIV_FRAG_S 20 - -/** UART_RX_FILT_REG register - * Rx Filter configuration - */ -#define UART_RX_FILT_REG(i) (DR_REG_UART_BASE(i) + 0x18) -/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; - * when input pulse width is lower than this value the pulse is ignored. - */ -#define UART_GLITCH_FILT 0x000000FFU -#define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S) -#define UART_GLITCH_FILT_V 0x000000FFU -#define UART_GLITCH_FILT_S 0 -/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; - * Set this bit to enable Rx signal filter. - */ -#define UART_GLITCH_FILT_EN (BIT(8)) -#define UART_GLITCH_FILT_EN_M (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S) -#define UART_GLITCH_FILT_EN_V 0x00000001U -#define UART_GLITCH_FILT_EN_S 8 - -/** UART_STATUS_REG register - * UART status register - */ -#define UART_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x1c) -/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0; - * Stores the byte number of valid data in Rx-FIFO. - */ -#define UART_RXFIFO_CNT 0x000000FFU -#define UART_RXFIFO_CNT_M (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S) -#define UART_RXFIFO_CNT_V 0x000000FFU -#define UART_RXFIFO_CNT_S 0 -/** UART_DSRN : RO; bitpos: [13]; default: 0; - * The register represent the level value of the internal uart dsr signal. - */ -#define UART_DSRN (BIT(13)) -#define UART_DSRN_M (UART_DSRN_V << UART_DSRN_S) -#define UART_DSRN_V 0x00000001U -#define UART_DSRN_S 13 -/** UART_CTSN : RO; bitpos: [14]; default: 1; - * This register represent the level value of the internal uart cts signal. - */ -#define UART_CTSN (BIT(14)) -#define UART_CTSN_M (UART_CTSN_V << UART_CTSN_S) -#define UART_CTSN_V 0x00000001U -#define UART_CTSN_S 14 -/** UART_RXD : RO; bitpos: [15]; default: 1; - * This register represent the level value of the internal uart rxd signal. - */ -#define UART_RXD (BIT(15)) -#define UART_RXD_M (UART_RXD_V << UART_RXD_S) -#define UART_RXD_V 0x00000001U -#define UART_RXD_S 15 -/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0; - * Stores the byte number of data in Tx-FIFO. - */ -#define UART_TXFIFO_CNT 0x000000FFU -#define UART_TXFIFO_CNT_M (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S) -#define UART_TXFIFO_CNT_V 0x000000FFU -#define UART_TXFIFO_CNT_S 16 -/** UART_DTRN : RO; bitpos: [29]; default: 1; - * This bit represents the level of the internal uart dtr signal. - */ -#define UART_DTRN (BIT(29)) -#define UART_DTRN_M (UART_DTRN_V << UART_DTRN_S) -#define UART_DTRN_V 0x00000001U -#define UART_DTRN_S 29 -/** UART_RTSN : RO; bitpos: [30]; default: 1; - * This bit represents the level of the internal uart rts signal. - */ -#define UART_RTSN (BIT(30)) -#define UART_RTSN_M (UART_RTSN_V << UART_RTSN_S) -#define UART_RTSN_V 0x00000001U -#define UART_RTSN_S 30 -/** UART_TXD : RO; bitpos: [31]; default: 1; - * This bit represents the level of the internal uart txd signal. - */ -#define UART_TXD (BIT(31)) -#define UART_TXD_M (UART_TXD_V << UART_TXD_S) -#define UART_TXD_V 0x00000001U -#define UART_TXD_S 31 - -/** UART_CONF0_SYNC_REG register - * a - */ -#define UART_CONF0_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x20) -/** UART_PARITY : R/W; bitpos: [0]; default: 0; - * This register is used to configure the parity check mode. - */ -#define UART_PARITY (BIT(0)) -#define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S) -#define UART_PARITY_V 0x00000001U -#define UART_PARITY_S 0 -/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0; - * Set this bit to enable uart parity check. - */ -#define UART_PARITY_EN (BIT(1)) -#define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S) -#define UART_PARITY_EN_V 0x00000001U -#define UART_PARITY_EN_S 1 -/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; - * This register is used to set the length of data. - */ -#define UART_BIT_NUM 0x00000003U -#define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S) -#define UART_BIT_NUM_V 0x00000003U -#define UART_BIT_NUM_S 2 -/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; - * This register is used to set the length of stop bit. - */ -#define UART_STOP_BIT_NUM 0x00000003U -#define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S) -#define UART_STOP_BIT_NUM_V 0x00000003U -#define UART_STOP_BIT_NUM_S 4 -/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0; - * Set this bit to enable transmitter to send NULL when the process of sending data - * is done. - */ -#define UART_TXD_BRK (BIT(6)) -#define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S) -#define UART_TXD_BRK_V 0x00000001U -#define UART_TXD_BRK_S 6 -/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0; - * Set this bit to enable IrDA loopback mode. - */ -#define UART_IRDA_DPLX (BIT(7)) -#define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S) -#define UART_IRDA_DPLX_V 0x00000001U -#define UART_IRDA_DPLX_S 7 -/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0; - * This is the start enable bit for IrDA transmitter. - */ -#define UART_IRDA_TX_EN (BIT(8)) -#define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S) -#define UART_IRDA_TX_EN_V 0x00000001U -#define UART_IRDA_TX_EN_S 8 -/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0; - * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA - * transmitter's 11th bit to 0. - */ -#define UART_IRDA_WCTL (BIT(9)) -#define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S) -#define UART_IRDA_WCTL_V 0x00000001U -#define UART_IRDA_WCTL_S 9 -/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0; - * Set this bit to invert the level of IrDA transmitter. - */ -#define UART_IRDA_TX_INV (BIT(10)) -#define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S) -#define UART_IRDA_TX_INV_V 0x00000001U -#define UART_IRDA_TX_INV_S 10 -/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0; - * Set this bit to invert the level of IrDA receiver. - */ -#define UART_IRDA_RX_INV (BIT(11)) -#define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S) -#define UART_IRDA_RX_INV_V 0x00000001U -#define UART_IRDA_RX_INV_S 11 -/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0; - * Set this bit to enable uart loopback test mode. - */ -#define UART_LOOPBACK (BIT(12)) -#define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S) -#define UART_LOOPBACK_V 0x00000001U -#define UART_LOOPBACK_S 12 -/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; - * Set this bit to enable flow control function for transmitter. - */ -#define UART_TX_FLOW_EN (BIT(13)) -#define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S) -#define UART_TX_FLOW_EN_V 0x00000001U -#define UART_TX_FLOW_EN_S 13 -/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0; - * Set this bit to enable IrDA protocol. - */ -#define UART_IRDA_EN (BIT(14)) -#define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S) -#define UART_IRDA_EN_V 0x00000001U -#define UART_IRDA_EN_S 14 -/** UART_RXD_INV : R/W; bitpos: [15]; default: 0; - * Set this bit to inverse the level value of uart rxd signal. - */ -#define UART_RXD_INV (BIT(15)) -#define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S) -#define UART_RXD_INV_V 0x00000001U -#define UART_RXD_INV_S 15 -/** UART_TXD_INV : R/W; bitpos: [16]; default: 0; - * Set this bit to inverse the level value of uart txd signal. - */ -#define UART_TXD_INV (BIT(16)) -#define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S) -#define UART_TXD_INV_V 0x00000001U -#define UART_TXD_INV_S 16 -/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; - * Disable UART Rx data overflow detect. - */ -#define UART_DIS_RX_DAT_OVF (BIT(17)) -#define UART_DIS_RX_DAT_OVF_M (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S) -#define UART_DIS_RX_DAT_OVF_V 0x00000001U -#define UART_DIS_RX_DAT_OVF_S 17 -/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; - * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver - * stores the data even if the received data is wrong. - */ -#define UART_ERR_WR_MASK (BIT(18)) -#define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S) -#define UART_ERR_WR_MASK_V 0x00000001U -#define UART_ERR_WR_MASK_S 18 -/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0; - * This is the enable bit for detecting baudrate. - */ -#define UART_AUTOBAUD_EN (BIT(19)) -#define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S) -#define UART_AUTOBAUD_EN_V 0x00000001U -#define UART_AUTOBAUD_EN_S 19 -/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0; - * UART memory clock gate enable signal. - */ -#define UART_MEM_CLK_EN (BIT(20)) -#define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S) -#define UART_MEM_CLK_EN_V 0x00000001U -#define UART_MEM_CLK_EN_S 20 -/** UART_SW_RTS : R/W; bitpos: [21]; default: 0; - * This register is used to configure the software rts signal which is used in - * software flow control. - */ -#define UART_SW_RTS (BIT(21)) -#define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S) -#define UART_SW_RTS_V 0x00000001U -#define UART_SW_RTS_S 21 -/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; - * Set this bit to reset the uart receive-FIFO. - */ -#define UART_RXFIFO_RST (BIT(22)) -#define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S) -#define UART_RXFIFO_RST_V 0x00000001U -#define UART_RXFIFO_RST_S 22 -/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; - * Set this bit to reset the uart transmit-FIFO. - */ -#define UART_TXFIFO_RST (BIT(23)) -#define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S) -#define UART_TXFIFO_RST_V 0x00000001U -#define UART_TXFIFO_RST_S 23 - -/** UART_CONF1_REG register - * Configuration register 1 - */ -#define UART_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x24) -/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; - * It will produce rxfifo_full_int interrupt when receiver receives more data than - * this register value. - */ -#define UART_RXFIFO_FULL_THRHD 0x000000FFU -#define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S) -#define UART_RXFIFO_FULL_THRHD_V 0x000000FFU -#define UART_RXFIFO_FULL_THRHD_S 0 -/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96; - * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less - * than this register value. - */ -#define UART_TXFIFO_EMPTY_THRHD 0x000000FFU -#define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S) -#define UART_TXFIFO_EMPTY_THRHD_V 0x000000FFU -#define UART_TXFIFO_EMPTY_THRHD_S 8 -/** UART_CTS_INV : R/W; bitpos: [16]; default: 0; - * Set this bit to inverse the level value of uart cts signal. - */ -#define UART_CTS_INV (BIT(16)) -#define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S) -#define UART_CTS_INV_V 0x00000001U -#define UART_CTS_INV_S 16 -/** UART_DSR_INV : R/W; bitpos: [17]; default: 0; - * Set this bit to inverse the level value of uart dsr signal. - */ -#define UART_DSR_INV (BIT(17)) -#define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S) -#define UART_DSR_INV_V 0x00000001U -#define UART_DSR_INV_S 17 -/** UART_RTS_INV : R/W; bitpos: [18]; default: 0; - * Set this bit to inverse the level value of uart rts signal. - */ -#define UART_RTS_INV (BIT(18)) -#define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S) -#define UART_RTS_INV_V 0x00000001U -#define UART_RTS_INV_S 18 -/** UART_DTR_INV : R/W; bitpos: [19]; default: 0; - * Set this bit to inverse the level value of uart dtr signal. - */ -#define UART_DTR_INV (BIT(19)) -#define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S) -#define UART_DTR_INV_V 0x00000001U -#define UART_DTR_INV_S 19 -/** UART_SW_DTR : R/W; bitpos: [20]; default: 0; - * This register is used to configure the software dtr signal which is used in - * software flow control. - */ -#define UART_SW_DTR (BIT(20)) -#define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S) -#define UART_SW_DTR_V 0x00000001U -#define UART_SW_DTR_S 20 -/** UART_CLK_EN : R/W; bitpos: [21]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. - */ -#define UART_CLK_EN (BIT(21)) -#define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S) -#define UART_CLK_EN_V 0x00000001U -#define UART_CLK_EN_S 21 - -/** UART_HWFC_CONF_SYNC_REG register - * Hardware flow-control configuration - */ -#define UART_HWFC_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x2c) -/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; - * This register is used to configure the maximum amount of data that can be received - * when hardware flow control works. - */ -#define UART_RX_FLOW_THRHD 0x000000FFU -#define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S) -#define UART_RX_FLOW_THRHD_V 0x000000FFU -#define UART_RX_FLOW_THRHD_S 0 -/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; - * This is the flow enable bit for UART receiver. - */ -#define UART_RX_FLOW_EN (BIT(8)) -#define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S) -#define UART_RX_FLOW_EN_V 0x00000001U -#define UART_RX_FLOW_EN_S 8 - -/** UART_SLEEP_CONF0_REG register - * UART sleep configure register 0 - */ -#define UART_SLEEP_CONF0_REG(i) (DR_REG_UART_BASE(i) + 0x30) -/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; - * This register restores the specified wake up char1 to wake up - */ -#define UART_WK_CHAR1 0x000000FFU -#define UART_WK_CHAR1_M (UART_WK_CHAR1_V << UART_WK_CHAR1_S) -#define UART_WK_CHAR1_V 0x000000FFU -#define UART_WK_CHAR1_S 0 -/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; - * This register restores the specified wake up char2 to wake up - */ -#define UART_WK_CHAR2 0x000000FFU -#define UART_WK_CHAR2_M (UART_WK_CHAR2_V << UART_WK_CHAR2_S) -#define UART_WK_CHAR2_V 0x000000FFU -#define UART_WK_CHAR2_S 8 -/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; - * This register restores the specified wake up char3 to wake up - */ -#define UART_WK_CHAR3 0x000000FFU -#define UART_WK_CHAR3_M (UART_WK_CHAR3_V << UART_WK_CHAR3_S) -#define UART_WK_CHAR3_V 0x000000FFU -#define UART_WK_CHAR3_S 16 -/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; - * This register restores the specified wake up char4 to wake up - */ -#define UART_WK_CHAR4 0x000000FFU -#define UART_WK_CHAR4_M (UART_WK_CHAR4_V << UART_WK_CHAR4_S) -#define UART_WK_CHAR4_V 0x000000FFU -#define UART_WK_CHAR4_S 24 - -/** UART_SLEEP_CONF1_REG register - * UART sleep configure register 1 - */ -#define UART_SLEEP_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x34) -/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; - * This register restores the specified char0 to wake up - */ -#define UART_WK_CHAR0 0x000000FFU -#define UART_WK_CHAR0_M (UART_WK_CHAR0_V << UART_WK_CHAR0_S) -#define UART_WK_CHAR0_V 0x000000FFU -#define UART_WK_CHAR0_S 0 - -/** UART_SLEEP_CONF2_REG register - * UART sleep configure register 2 - */ -#define UART_SLEEP_CONF2_REG(i) (DR_REG_UART_BASE(i) + 0x38) -/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; - * The uart is activated from light sleeping mode when the input rxd edge changes more - * times than this register value. - */ -#define UART_ACTIVE_THRESHOLD 0x000003FFU -#define UART_ACTIVE_THRESHOLD_M (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S) -#define UART_ACTIVE_THRESHOLD_V 0x000003FFU -#define UART_ACTIVE_THRESHOLD_S 0 -/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1; - * In wake up mode 1 this field is used to set the received data number threshold to - * wake up chip. - */ -#define UART_RX_WAKE_UP_THRHD 0x000000FFU -#define UART_RX_WAKE_UP_THRHD_M (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S) -#define UART_RX_WAKE_UP_THRHD_V 0x000000FFU -#define UART_RX_WAKE_UP_THRHD_S 10 -/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; - * This register is used to select number of wake up char. - */ -#define UART_WK_CHAR_NUM 0x00000007U -#define UART_WK_CHAR_NUM_M (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S) -#define UART_WK_CHAR_NUM_V 0x00000007U -#define UART_WK_CHAR_NUM_S 18 -/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; - * This register is used to mask wake up char. - */ -#define UART_WK_CHAR_MASK 0x0000001FU -#define UART_WK_CHAR_MASK_M (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S) -#define UART_WK_CHAR_MASK_V 0x0000001FU -#define UART_WK_CHAR_MASK_S 21 -/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; - * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: - * received data number larger than - */ -#define UART_WK_MODE_SEL 0x00000003U -#define UART_WK_MODE_SEL_M (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S) -#define UART_WK_MODE_SEL_V 0x00000003U -#define UART_WK_MODE_SEL_S 26 - -/** UART_SWFC_CONF0_SYNC_REG register - * Software flow-control character configuration - */ -#define UART_SWFC_CONF0_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x3c) -/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; - * This register stores the Xon flow control char. - */ -#define UART_XON_CHAR 0x000000FFU -#define UART_XON_CHAR_M (UART_XON_CHAR_V << UART_XON_CHAR_S) -#define UART_XON_CHAR_V 0x000000FFU -#define UART_XON_CHAR_S 0 -/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; - * This register stores the Xoff flow control char. - */ -#define UART_XOFF_CHAR 0x000000FFU -#define UART_XOFF_CHAR_M (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S) -#define UART_XOFF_CHAR_V 0x000000FFU -#define UART_XOFF_CHAR_S 8 -/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; - * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In - * this status, UART Tx can not transmit XOFF even the received data number is larger - * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when - * UART Tx is disabled. - */ -#define UART_XON_XOFF_STILL_SEND (BIT(16)) -#define UART_XON_XOFF_STILL_SEND_M (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S) -#define UART_XON_XOFF_STILL_SEND_V 0x00000001U -#define UART_XON_XOFF_STILL_SEND_S 16 -/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; - * Set this bit to enable software flow control. It is used with register sw_xon or - * sw_xoff. - */ -#define UART_SW_FLOW_CON_EN (BIT(17)) -#define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S) -#define UART_SW_FLOW_CON_EN_V 0x00000001U -#define UART_SW_FLOW_CON_EN_S 17 -/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; - * Set this bit to remove flow control char from the received data. - */ -#define UART_XONOFF_DEL (BIT(18)) -#define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S) -#define UART_XONOFF_DEL_V 0x00000001U -#define UART_XONOFF_DEL_S 18 -/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0; - * Set this bit to enable the transmitter to go on sending data. - */ -#define UART_FORCE_XON (BIT(19)) -#define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S) -#define UART_FORCE_XON_V 0x00000001U -#define UART_FORCE_XON_S 19 -/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; - * Set this bit to stop the transmitter from sending data. - */ -#define UART_FORCE_XOFF (BIT(20)) -#define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S) -#define UART_FORCE_XOFF_V 0x00000001U -#define UART_FORCE_XOFF_S 20 -/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; - * Set this bit to send Xon char. It is cleared by hardware automatically. - */ -#define UART_SEND_XON (BIT(21)) -#define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S) -#define UART_SEND_XON_V 0x00000001U -#define UART_SEND_XON_S 21 -/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; - * Set this bit to send Xoff char. It is cleared by hardware automatically. - */ -#define UART_SEND_XOFF (BIT(22)) -#define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S) -#define UART_SEND_XOFF_V 0x00000001U -#define UART_SEND_XOFF_S 22 - -/** UART_SWFC_CONF1_REG register - * Software flow-control character configuration - */ -#define UART_SWFC_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x40) -/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; - * When the data amount in Rx-FIFO is less than this register value with - * uart_sw_flow_con_en set to 1 it will send a Xon char. - */ -#define UART_XON_THRESHOLD 0x000000FFU -#define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S) -#define UART_XON_THRESHOLD_V 0x000000FFU -#define UART_XON_THRESHOLD_S 0 -/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224; - * When the data amount in Rx-FIFO is more than this register value with - * uart_sw_flow_con_en set to 1 it will send a Xoff char. - */ -#define UART_XOFF_THRESHOLD 0x000000FFU -#define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S) -#define UART_XOFF_THRESHOLD_V 0x000000FFU -#define UART_XOFF_THRESHOLD_S 8 - -/** UART_TXBRK_CONF_SYNC_REG register - * Tx Break character configuration - */ -#define UART_TXBRK_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x44) -/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; - * This register is used to configure the number of 0 to be sent after the process of - * sending data is done. It is active when txd_brk is set to 1. - */ -#define UART_TX_BRK_NUM 0x000000FFU -#define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S) -#define UART_TX_BRK_NUM_V 0x000000FFU -#define UART_TX_BRK_NUM_S 0 - -/** UART_IDLE_CONF_SYNC_REG register - * Frame-end idle configuration - */ -#define UART_IDLE_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x48) -/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; - * It will produce frame end signal when receiver takes more time to receive one byte - * data than this register value. - */ -#define UART_RX_IDLE_THRHD 0x000003FFU -#define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S) -#define UART_RX_IDLE_THRHD_V 0x000003FFU -#define UART_RX_IDLE_THRHD_S 0 -/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; - * This register is used to configure the duration time between transfers. - */ -#define UART_TX_IDLE_NUM 0x000003FFU -#define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S) -#define UART_TX_IDLE_NUM_V 0x000003FFU -#define UART_TX_IDLE_NUM_S 10 - -/** UART_RS485_CONF_SYNC_REG register - * RS485 mode configuration - */ -#define UART_RS485_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x4c) -/** UART_RS485_EN : R/W; bitpos: [0]; default: 0; - * Set this bit to choose the rs485 mode. - */ -#define UART_RS485_EN (BIT(0)) -#define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S) -#define UART_RS485_EN_V 0x00000001U -#define UART_RS485_EN_S 0 -/** UART_DL0_EN : R/W; bitpos: [1]; default: 0; - * Set this bit to delay the stop bit by 1 bit. - */ -#define UART_DL0_EN (BIT(1)) -#define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S) -#define UART_DL0_EN_V 0x00000001U -#define UART_DL0_EN_S 1 -/** UART_DL1_EN : R/W; bitpos: [2]; default: 0; - * Set this bit to delay the stop bit by 1 bit. - */ -#define UART_DL1_EN (BIT(2)) -#define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S) -#define UART_DL1_EN_V 0x00000001U -#define UART_DL1_EN_S 2 -/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0; - * Set this bit to enable receiver could receive data when the transmitter is - * transmitting data in rs485 mode. - */ -#define UART_RS485TX_RX_EN (BIT(3)) -#define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S) -#define UART_RS485TX_RX_EN_V 0x00000001U -#define UART_RS485TX_RX_EN_S 3 -/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0; - * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. - */ -#define UART_RS485RXBY_TX_EN (BIT(4)) -#define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S) -#define UART_RS485RXBY_TX_EN_V 0x00000001U -#define UART_RS485RXBY_TX_EN_S 4 -/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0; - * This register is used to delay the receiver's internal data signal. - */ -#define UART_RS485_RX_DLY_NUM (BIT(5)) -#define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S) -#define UART_RS485_RX_DLY_NUM_V 0x00000001U -#define UART_RS485_RX_DLY_NUM_S 5 -/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0; - * This register is used to delay the transmitter's internal data signal. - */ -#define UART_RS485_TX_DLY_NUM 0x0000000FU -#define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S) -#define UART_RS485_TX_DLY_NUM_V 0x0000000FU -#define UART_RS485_TX_DLY_NUM_S 6 - -/** UART_AT_CMD_PRECNT_SYNC_REG register - * Pre-sequence timing configuration - */ -#define UART_AT_CMD_PRECNT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x50) -/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; - * This register is used to configure the idle duration time before the first at_cmd - * is received by receiver. - */ -#define UART_PRE_IDLE_NUM 0x0000FFFFU -#define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S) -#define UART_PRE_IDLE_NUM_V 0x0000FFFFU -#define UART_PRE_IDLE_NUM_S 0 - -/** UART_AT_CMD_POSTCNT_SYNC_REG register - * Post-sequence timing configuration - */ -#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x54) -/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; - * This register is used to configure the duration time between the last at_cmd and - * the next data. - */ -#define UART_POST_IDLE_NUM 0x0000FFFFU -#define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S) -#define UART_POST_IDLE_NUM_V 0x0000FFFFU -#define UART_POST_IDLE_NUM_S 0 - -/** UART_AT_CMD_GAPTOUT_SYNC_REG register - * Timeout configuration - */ -#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x58) -/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; - * This register is used to configure the duration time between the at_cmd chars. - */ -#define UART_RX_GAP_TOUT 0x0000FFFFU -#define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S) -#define UART_RX_GAP_TOUT_V 0x0000FFFFU -#define UART_RX_GAP_TOUT_S 0 - -/** UART_AT_CMD_CHAR_SYNC_REG register - * AT escape sequence detection configuration - */ -#define UART_AT_CMD_CHAR_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x5c) -/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; - * This register is used to configure the content of at_cmd char. - */ -#define UART_AT_CMD_CHAR 0x000000FFU -#define UART_AT_CMD_CHAR_M (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S) -#define UART_AT_CMD_CHAR_V 0x000000FFU -#define UART_AT_CMD_CHAR_S 0 -/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; - * This register is used to configure the num of continuous at_cmd chars received by - * receiver. - */ -#define UART_CHAR_NUM 0x000000FFU -#define UART_CHAR_NUM_M (UART_CHAR_NUM_V << UART_CHAR_NUM_S) -#define UART_CHAR_NUM_V 0x000000FFU -#define UART_CHAR_NUM_S 8 - -/** UART_MEM_CONF_REG register - * UART memory power configuration - */ -#define UART_MEM_CONF_REG(i) (DR_REG_UART_BASE(i) + 0x60) -/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; - * Set this bit to force power down UART memory. - */ -#define UART_MEM_FORCE_PD (BIT(25)) -#define UART_MEM_FORCE_PD_M (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S) -#define UART_MEM_FORCE_PD_V 0x00000001U -#define UART_MEM_FORCE_PD_S 25 -/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; - * Set this bit to force power up UART memory. - */ -#define UART_MEM_FORCE_PU (BIT(26)) -#define UART_MEM_FORCE_PU_M (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S) -#define UART_MEM_FORCE_PU_V 0x00000001U -#define UART_MEM_FORCE_PU_S 26 - -/** UART_TOUT_CONF_SYNC_REG register - * UART threshold and allocation configuration - */ -#define UART_TOUT_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x64) -/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; - * This is the enable bit for uart receiver's timeout function. - */ -#define UART_RX_TOUT_EN (BIT(0)) -#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) -#define UART_RX_TOUT_EN_V 0x00000001U -#define UART_RX_TOUT_EN_S 0 -/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; - * Set this bit to stop accumulating idle_cnt when hardware flow control works. - */ -#define UART_RX_TOUT_FLOW_DIS (BIT(1)) -#define UART_RX_TOUT_FLOW_DIS_M (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S) -#define UART_RX_TOUT_FLOW_DIS_V 0x00000001U -#define UART_RX_TOUT_FLOW_DIS_S 1 -/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; - * This register is used to configure the threshold time that receiver takes to - * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver - * takes more time to receive one byte with rx_tout_en set to 1. - */ -#define UART_RX_TOUT_THRHD 0x000003FFU -#define UART_RX_TOUT_THRHD_M (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S) -#define UART_RX_TOUT_THRHD_V 0x000003FFU -#define UART_RX_TOUT_THRHD_S 2 - -/** UART_MEM_TX_STATUS_REG register - * Tx-SRAM write and read offset address. - */ -#define UART_MEM_TX_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x68) -/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0; - * This register stores the offset write address in Tx-SRAM. - */ -#define UART_TX_SRAM_WADDR 0x000000FFU -#define UART_TX_SRAM_WADDR_M (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S) -#define UART_TX_SRAM_WADDR_V 0x000000FFU -#define UART_TX_SRAM_WADDR_S 0 -/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0; - * This register stores the offset read address in Tx-SRAM. - */ -#define UART_TX_SRAM_RADDR 0x000000FFU -#define UART_TX_SRAM_RADDR_M (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S) -#define UART_TX_SRAM_RADDR_V 0x000000FFU -#define UART_TX_SRAM_RADDR_S 9 - -/** UART_MEM_RX_STATUS_REG register - * Rx-SRAM write and read offset address. - */ -#define UART_MEM_RX_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x6c) -/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128; - * This register stores the offset read address in RX-SRAM. - */ -#define UART_RX_SRAM_RADDR 0x000000FFU -#define UART_RX_SRAM_RADDR_M (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S) -#define UART_RX_SRAM_RADDR_V 0x000000FFU -#define UART_RX_SRAM_RADDR_S 0 -/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128; - * This register stores the offset write address in Rx-SRAM. - */ -#define UART_RX_SRAM_WADDR 0x000000FFU -#define UART_RX_SRAM_WADDR_M (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S) -#define UART_RX_SRAM_WADDR_V 0x000000FFU -#define UART_RX_SRAM_WADDR_S 9 - -/** UART_FSM_STATUS_REG register - * UART transmit and receive status. - */ -#define UART_FSM_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x70) -/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; - * This is the status register of receiver. - */ -#define UART_ST_URX_OUT 0x0000000FU -#define UART_ST_URX_OUT_M (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S) -#define UART_ST_URX_OUT_V 0x0000000FU -#define UART_ST_URX_OUT_S 0 -/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; - * This is the status register of transmitter. - */ -#define UART_ST_UTX_OUT 0x0000000FU -#define UART_ST_UTX_OUT_M (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S) -#define UART_ST_UTX_OUT_V 0x0000000FU -#define UART_ST_UTX_OUT_S 4 - -/** UART_POSPULSE_REG register - * Autobaud high pulse register - */ -#define UART_POSPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x74) -/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the minimal input clock count between two positive edges. It - * is used in boudrate-detect process. - */ -#define UART_POSEDGE_MIN_CNT 0x00000FFFU -#define UART_POSEDGE_MIN_CNT_M (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S) -#define UART_POSEDGE_MIN_CNT_V 0x00000FFFU -#define UART_POSEDGE_MIN_CNT_S 0 - -/** UART_NEGPULSE_REG register - * Autobaud low pulse register - */ -#define UART_NEGPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x78) -/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the minimal input clock count between two negative edges. It - * is used in boudrate-detect process. - */ -#define UART_NEGEDGE_MIN_CNT 0x00000FFFU -#define UART_NEGEDGE_MIN_CNT_M (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S) -#define UART_NEGEDGE_MIN_CNT_V 0x00000FFFU -#define UART_NEGEDGE_MIN_CNT_S 0 - -/** UART_LOWPULSE_REG register - * Autobaud minimum low pulse duration register - */ -#define UART_LOWPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x7c) -/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the minimum duration time of the low level pulse. - * It is used in baud rate-detect process. - */ -#define UART_LOWPULSE_MIN_CNT 0x00000FFFU -#define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S) -#define UART_LOWPULSE_MIN_CNT_V 0x00000FFFU -#define UART_LOWPULSE_MIN_CNT_S 0 - -/** UART_HIGHPULSE_REG register - * Autobaud minimum high pulse duration register - */ -#define UART_HIGHPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x80) -/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maximum duration time for the high level - * pulse. It is used in baud rate-detect process. - */ -#define UART_HIGHPULSE_MIN_CNT 0x00000FFFU -#define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S) -#define UART_HIGHPULSE_MIN_CNT_V 0x00000FFFU -#define UART_HIGHPULSE_MIN_CNT_S 0 - -/** UART_RXD_CNT_REG register - * Autobaud edge change count register - */ -#define UART_RXD_CNT_REG(i) (DR_REG_UART_BASE(i) + 0x84) -/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; - * This register stores the count of rxd edge change. It is used in baud rate-detect - * process. - */ -#define UART_RXD_EDGE_CNT 0x000003FFU -#define UART_RXD_EDGE_CNT_M (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S) -#define UART_RXD_EDGE_CNT_V 0x000003FFU -#define UART_RXD_EDGE_CNT_S 0 - -/** UART_CLK_CONF_REG register - * UART core clock configuration - */ -#define UART_CLK_CONF_REG(i) (DR_REG_UART_BASE(i) + 0x88) -/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; - * Set this bit to enable UART Tx clock. - */ -#define UART_TX_SCLK_EN (BIT(24)) -#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) -#define UART_TX_SCLK_EN_V 0x00000001U -#define UART_TX_SCLK_EN_S 24 -/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; - * Set this bit to enable UART Rx clock. - */ -#define UART_RX_SCLK_EN (BIT(25)) -#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) -#define UART_RX_SCLK_EN_V 0x00000001U -#define UART_RX_SCLK_EN_S 25 -/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx. - */ -#define UART_TX_RST_CORE (BIT(26)) -#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S) -#define UART_TX_RST_CORE_V 0x00000001U -#define UART_TX_RST_CORE_S 26 -/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; - * Write 1 then write 0 to this bit to reset UART Rx. - */ -#define UART_RX_RST_CORE (BIT(27)) -#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S) -#define UART_RX_RST_CORE_V 0x00000001U -#define UART_RX_RST_CORE_S 27 - -/** UART_DATE_REG register - * UART Version register - */ -#define UART_DATE_REG(i) (DR_REG_UART_BASE(i) + 0x8c) -/** UART_DATE : R/W; bitpos: [31:0]; default: 36720720; - * This is the version register. - */ -#define UART_DATE 0xFFFFFFFFU -#define UART_DATE_M (UART_DATE_V << UART_DATE_S) -#define UART_DATE_V 0xFFFFFFFFU -#define UART_DATE_S 0 - -/** UART_AFIFO_STATUS_REG register - * UART AFIFO Status - */ -#define UART_AFIFO_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x90) -/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; - * Full signal of APB TX AFIFO. - */ -#define UART_TX_AFIFO_FULL (BIT(0)) -#define UART_TX_AFIFO_FULL_M (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S) -#define UART_TX_AFIFO_FULL_V 0x00000001U -#define UART_TX_AFIFO_FULL_S 0 -/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; - * Empty signal of APB TX AFIFO. - */ -#define UART_TX_AFIFO_EMPTY (BIT(1)) -#define UART_TX_AFIFO_EMPTY_M (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S) -#define UART_TX_AFIFO_EMPTY_V 0x00000001U -#define UART_TX_AFIFO_EMPTY_S 1 -/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; - * Full signal of APB RX AFIFO. - */ -#define UART_RX_AFIFO_FULL (BIT(2)) -#define UART_RX_AFIFO_FULL_M (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S) -#define UART_RX_AFIFO_FULL_V 0x00000001U -#define UART_RX_AFIFO_FULL_S 2 -/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; - * Empty signal of APB RX AFIFO. - */ -#define UART_RX_AFIFO_EMPTY (BIT(3)) -#define UART_RX_AFIFO_EMPTY_M (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S) -#define UART_RX_AFIFO_EMPTY_V 0x00000001U -#define UART_RX_AFIFO_EMPTY_S 3 - -/** UART_REG_UPDATE_REG register - * UART Registers Configuration Update register - */ -#define UART_REG_UPDATE_REG(i) (DR_REG_UART_BASE(i) + 0x98) -/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; - * Software write 1 would synchronize registers into UART Core clock domain and would - * be cleared by hardware after synchronization is done. - */ -#define UART_REG_UPDATE (BIT(0)) -#define UART_REG_UPDATE_M (UART_REG_UPDATE_V << UART_REG_UPDATE_S) -#define UART_REG_UPDATE_V 0x00000001U -#define UART_REG_UPDATE_S 0 - -/** UART_ID_REG register - * UART ID register - */ -#define UART_ID_REG(i) (DR_REG_UART_BASE(i) + 0x9c) -/** UART_ID : R/W; bitpos: [31:0]; default: 1280; - * This register is used to configure the uart_id. - */ -#define UART_ID 0xFFFFFFFFU -#define UART_ID_M (UART_ID_V << UART_ID_S) -#define UART_ID_V 0xFFFFFFFFU -#define UART_ID_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_struct.h deleted file mode 100644 index c49c9b58ba..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_struct.h +++ /dev/null @@ -1,1274 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: FIFO Configuration */ -/** Type of fifo register - * FIFO data register - */ -typedef union { - struct { - /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; - * UART $n accesses FIFO via this register. - */ - uint32_t rxfifo_rd_byte:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} uart_fifo_reg_t; - -/** Type of mem_conf register - * UART memory power configuration - */ -typedef union { - struct { - uint32_t reserved_0:25; - /** mem_force_pd : R/W; bitpos: [25]; default: 0; - * Set this bit to force power down UART memory. - */ - uint32_t mem_force_pd:1; - /** mem_force_pu : R/W; bitpos: [26]; default: 0; - * Set this bit to force power up UART memory. - */ - uint32_t mem_force_pu:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} uart_mem_conf_reg_t; - -/** Type of tout_conf_sync register - * UART threshold and allocation configuration - */ -typedef union { - struct { - /** rx_tout_en : R/W; bitpos: [0]; default: 0; - * This is the enable bit for uart receiver's timeout function. - */ - uint32_t rx_tout_en:1; - /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; - * Set this bit to stop accumulating idle_cnt when hardware flow control works. - */ - uint32_t rx_tout_flow_dis:1; - /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; - * This register is used to configure the threshold time that receiver takes to - * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver - * takes more time to receive one byte with rx_tout_en set to 1. - */ - uint32_t rx_tout_thrhd:10; - uint32_t reserved_12:20; - }; - uint32_t val; -} uart_tout_conf_sync_reg_t; - - -/** Group: Interrupt Register */ -/** Type of int_raw register - * Raw interrupt status - */ -typedef union { - struct { - /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * This interrupt raw bit turns to high level when receiver receives more data than - * what rxfifo_full_thrhd specifies. - */ - uint32_t rxfifo_full_int_raw:1; - /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1; - * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is - * less than what txfifo_empty_thrhd specifies . - */ - uint32_t txfifo_empty_int_raw:1; - /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a parity error in - * the data. - */ - uint32_t parity_err_int_raw:1; - /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a data frame error - * . - */ - uint32_t frm_err_int_raw:1; - /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * This interrupt raw bit turns to high level when receiver receives more data than - * the FIFO can store. - */ - uint32_t rxfifo_ovf_int_raw:1; - /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the edge change of - * DSRn signal. - */ - uint32_t dsr_chg_int_raw:1; - /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the edge change of - * CTSn signal. - */ - uint32_t cts_chg_int_raw:1; - /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a 0 after the stop - * bit. - */ - uint32_t brk_det_int_raw:1; - /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * This interrupt raw bit turns to high level when receiver takes more time than - * rx_tout_thrhd to receive a byte. - */ - uint32_t rxfifo_tout_int_raw:1; - /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver receives Xon char when - * uart_sw_flow_con_en is set to 1. - */ - uint32_t sw_xon_int_raw:1; - /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * This interrupt raw bit turns to high level when receiver receives Xoff char when - * uart_sw_flow_con_en is set to 1. - */ - uint32_t sw_xoff_int_raw:1; - /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a glitch in the - * middle of a start bit. - */ - uint32_t glitch_det_int_raw:1; - /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * This interrupt raw bit turns to high level when transmitter completes sending - * NULL characters after all data in Tx-FIFO are sent. - */ - uint32_t tx_brk_done_int_raw:1; - /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * This interrupt raw bit turns to high level when transmitter has kept the shortest - * duration after sending the last data. - */ - uint32_t tx_brk_idle_done_int_raw:1; - /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * This interrupt raw bit turns to high level when transmitter has send out all data - * in FIFO. - */ - uint32_t tx_done_int_raw:1; - /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a parity error - * from the echo of transmitter in rs485 mode. - */ - uint32_t rs485_parity_err_int_raw:1; - /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a data frame error - * from the echo of transmitter in rs485 mode. - */ - uint32_t rs485_frm_err_int_raw:1; - /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * This interrupt raw bit turns to high level when detects a clash between transmitter - * and receiver in rs485 mode. - */ - uint32_t rs485_clash_int_raw:1; - /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the configured - * at_cmd char. - */ - uint32_t at_cmd_char_det_int_raw:1; - /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * This interrupt raw bit turns to high level when input rxd edge changes more times - * than what reg_active_threshold specifies in light sleeping mode. - */ - uint32_t wakeup_int_raw:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} uart_int_raw_reg_t; - -/** Type of int_st register - * Masked interrupt status - */ -typedef union { - struct { - /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0; - * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. - */ - uint32_t rxfifo_full_int_st:1; - /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0; - * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set - * to 1. - */ - uint32_t txfifo_empty_int_st:1; - /** parity_err_int_st : RO; bitpos: [2]; default: 0; - * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. - */ - uint32_t parity_err_int_st:1; - /** frm_err_int_st : RO; bitpos: [3]; default: 0; - * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. - */ - uint32_t frm_err_int_st:1; - /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0; - * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. - */ - uint32_t rxfifo_ovf_int_st:1; - /** dsr_chg_int_st : RO; bitpos: [5]; default: 0; - * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. - */ - uint32_t dsr_chg_int_st:1; - /** cts_chg_int_st : RO; bitpos: [6]; default: 0; - * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. - */ - uint32_t cts_chg_int_st:1; - /** brk_det_int_st : RO; bitpos: [7]; default: 0; - * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. - */ - uint32_t brk_det_int_st:1; - /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0; - * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. - */ - uint32_t rxfifo_tout_int_st:1; - /** sw_xon_int_st : RO; bitpos: [9]; default: 0; - * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. - */ - uint32_t sw_xon_int_st:1; - /** sw_xoff_int_st : RO; bitpos: [10]; default: 0; - * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. - */ - uint32_t sw_xoff_int_st:1; - /** glitch_det_int_st : RO; bitpos: [11]; default: 0; - * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. - */ - uint32_t glitch_det_int_st:1; - /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0; - * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. - */ - uint32_t tx_brk_done_int_st:1; - /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; - * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena - * is set to 1. - */ - uint32_t tx_brk_idle_done_int_st:1; - /** tx_done_int_st : RO; bitpos: [14]; default: 0; - * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. - */ - uint32_t tx_done_int_st:1; - /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0; - * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is - * set to 1. - */ - uint32_t rs485_parity_err_int_st:1; - /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0; - * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set - * to 1. - */ - uint32_t rs485_frm_err_int_st:1; - /** rs485_clash_int_st : RO; bitpos: [17]; default: 0; - * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. - */ - uint32_t rs485_clash_int_st:1; - /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0; - * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set - * to 1. - */ - uint32_t at_cmd_char_det_int_st:1; - /** wakeup_int_st : RO; bitpos: [19]; default: 0; - * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. - */ - uint32_t wakeup_int_st:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} uart_int_st_reg_t; - -/** Type of int_ena register - * Interrupt enable bits - */ -typedef union { - struct { - /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0; - * This is the enable bit for rxfifo_full_int_st register. - */ - uint32_t rxfifo_full_int_ena:1; - /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0; - * This is the enable bit for txfifo_empty_int_st register. - */ - uint32_t txfifo_empty_int_ena:1; - /** parity_err_int_ena : R/W; bitpos: [2]; default: 0; - * This is the enable bit for parity_err_int_st register. - */ - uint32_t parity_err_int_ena:1; - /** frm_err_int_ena : R/W; bitpos: [3]; default: 0; - * This is the enable bit for frm_err_int_st register. - */ - uint32_t frm_err_int_ena:1; - /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; - * This is the enable bit for rxfifo_ovf_int_st register. - */ - uint32_t rxfifo_ovf_int_ena:1; - /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0; - * This is the enable bit for dsr_chg_int_st register. - */ - uint32_t dsr_chg_int_ena:1; - /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0; - * This is the enable bit for cts_chg_int_st register. - */ - uint32_t cts_chg_int_ena:1; - /** brk_det_int_ena : R/W; bitpos: [7]; default: 0; - * This is the enable bit for brk_det_int_st register. - */ - uint32_t brk_det_int_ena:1; - /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0; - * This is the enable bit for rxfifo_tout_int_st register. - */ - uint32_t rxfifo_tout_int_ena:1; - /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0; - * This is the enable bit for sw_xon_int_st register. - */ - uint32_t sw_xon_int_ena:1; - /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0; - * This is the enable bit for sw_xoff_int_st register. - */ - uint32_t sw_xoff_int_ena:1; - /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0; - * This is the enable bit for glitch_det_int_st register. - */ - uint32_t glitch_det_int_ena:1; - /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0; - * This is the enable bit for tx_brk_done_int_st register. - */ - uint32_t tx_brk_done_int_ena:1; - /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0; - * This is the enable bit for tx_brk_idle_done_int_st register. - */ - uint32_t tx_brk_idle_done_int_ena:1; - /** tx_done_int_ena : R/W; bitpos: [14]; default: 0; - * This is the enable bit for tx_done_int_st register. - */ - uint32_t tx_done_int_ena:1; - /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0; - * This is the enable bit for rs485_parity_err_int_st register. - */ - uint32_t rs485_parity_err_int_ena:1; - /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0; - * This is the enable bit for rs485_parity_err_int_st register. - */ - uint32_t rs485_frm_err_int_ena:1; - /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0; - * This is the enable bit for rs485_clash_int_st register. - */ - uint32_t rs485_clash_int_ena:1; - /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0; - * This is the enable bit for at_cmd_char_det_int_st register. - */ - uint32_t at_cmd_char_det_int_ena:1; - /** wakeup_int_ena : R/W; bitpos: [19]; default: 0; - * This is the enable bit for uart_wakeup_int_st register. - */ - uint32_t wakeup_int_ena:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} uart_int_ena_reg_t; - -/** Type of int_clr register - * Interrupt clear bits - */ -typedef union { - struct { - /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the rxfifo_full_int_raw interrupt. - */ - uint32_t rxfifo_full_int_clr:1; - /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear txfifo_empty_int_raw interrupt. - */ - uint32_t txfifo_empty_int_clr:1; - /** parity_err_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear parity_err_int_raw interrupt. - */ - uint32_t parity_err_int_clr:1; - /** frm_err_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear frm_err_int_raw interrupt. - */ - uint32_t frm_err_int_clr:1; - /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear rxfifo_ovf_int_raw interrupt. - */ - uint32_t rxfifo_ovf_int_clr:1; - /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the dsr_chg_int_raw interrupt. - */ - uint32_t dsr_chg_int_clr:1; - /** cts_chg_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the cts_chg_int_raw interrupt. - */ - uint32_t cts_chg_int_clr:1; - /** brk_det_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the brk_det_int_raw interrupt. - */ - uint32_t brk_det_int_clr:1; - /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the rxfifo_tout_int_raw interrupt. - */ - uint32_t rxfifo_tout_int_clr:1; - /** sw_xon_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the sw_xon_int_raw interrupt. - */ - uint32_t sw_xon_int_clr:1; - /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0; - * Set this bit to clear the sw_xoff_int_raw interrupt. - */ - uint32_t sw_xoff_int_clr:1; - /** glitch_det_int_clr : WT; bitpos: [11]; default: 0; - * Set this bit to clear the glitch_det_int_raw interrupt. - */ - uint32_t glitch_det_int_clr:1; - /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0; - * Set this bit to clear the tx_brk_done_int_raw interrupt.. - */ - uint32_t tx_brk_done_int_clr:1; - /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0; - * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. - */ - uint32_t tx_brk_idle_done_int_clr:1; - /** tx_done_int_clr : WT; bitpos: [14]; default: 0; - * Set this bit to clear the tx_done_int_raw interrupt. - */ - uint32_t tx_done_int_clr:1; - /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0; - * Set this bit to clear the rs485_parity_err_int_raw interrupt. - */ - uint32_t rs485_parity_err_int_clr:1; - /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0; - * Set this bit to clear the rs485_frm_err_int_raw interrupt. - */ - uint32_t rs485_frm_err_int_clr:1; - /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0; - * Set this bit to clear the rs485_clash_int_raw interrupt. - */ - uint32_t rs485_clash_int_clr:1; - /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0; - * Set this bit to clear the at_cmd_char_det_int_raw interrupt. - */ - uint32_t at_cmd_char_det_int_clr:1; - /** wakeup_int_clr : WT; bitpos: [19]; default: 0; - * Set this bit to clear the uart_wakeup_int_raw interrupt. - */ - uint32_t wakeup_int_clr:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} uart_int_clr_reg_t; - - -/** Group: Configuration Register */ -/** Type of clkdiv_sync register - * Clock divider configuration - */ -typedef union { - struct { - /** clkdiv : R/W; bitpos: [11:0]; default: 694; - * The integral part of the frequency divider factor. - */ - uint32_t clkdiv:12; - uint32_t reserved_12:8; - /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; - * The decimal part of the frequency divider factor. - */ - uint32_t clkdiv_frag:4; - uint32_t reserved_24:8; - }; - uint32_t val; -} uart_clkdiv_sync_reg_t; - -/** Type of rx_filt register - * Rx Filter configuration - */ -typedef union { - struct { - /** glitch_filt : R/W; bitpos: [7:0]; default: 8; - * when input pulse width is lower than this value the pulse is ignored. - */ - uint32_t glitch_filt:8; - /** glitch_filt_en : R/W; bitpos: [8]; default: 0; - * Set this bit to enable Rx signal filter. - */ - uint32_t glitch_filt_en:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} uart_rx_filt_reg_t; - -/** Type of conf0_sync register - * a - */ -typedef union { - struct { - /** parity : R/W; bitpos: [0]; default: 0; - * This register is used to configure the parity check mode. - */ - uint32_t parity:1; - /** parity_en : R/W; bitpos: [1]; default: 0; - * Set this bit to enable uart parity check. - */ - uint32_t parity_en:1; - /** bit_num : R/W; bitpos: [3:2]; default: 3; - * This register is used to set the length of data. - */ - uint32_t bit_num:2; - /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; - * This register is used to set the length of stop bit. - */ - uint32_t stop_bit_num:2; - /** txd_brk : R/W; bitpos: [6]; default: 0; - * Set this bit to enable transmitter to send NULL when the process of sending data - * is done. - */ - uint32_t txd_brk:1; - /** irda_dplx : R/W; bitpos: [7]; default: 0; - * Set this bit to enable IrDA loopback mode. - */ - uint32_t irda_dplx:1; - /** irda_tx_en : R/W; bitpos: [8]; default: 0; - * This is the start enable bit for IrDA transmitter. - */ - uint32_t irda_tx_en:1; - /** irda_wctl : R/W; bitpos: [9]; default: 0; - * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA - * transmitter's 11th bit to 0. - */ - uint32_t irda_wctl:1; - /** irda_tx_inv : R/W; bitpos: [10]; default: 0; - * Set this bit to invert the level of IrDA transmitter. - */ - uint32_t irda_tx_inv:1; - /** irda_rx_inv : R/W; bitpos: [11]; default: 0; - * Set this bit to invert the level of IrDA receiver. - */ - uint32_t irda_rx_inv:1; - /** loopback : R/W; bitpos: [12]; default: 0; - * Set this bit to enable uart loopback test mode. - */ - uint32_t loopback:1; - /** tx_flow_en : R/W; bitpos: [13]; default: 0; - * Set this bit to enable flow control function for transmitter. - */ - uint32_t tx_flow_en:1; - /** irda_en : R/W; bitpos: [14]; default: 0; - * Set this bit to enable IrDA protocol. - */ - uint32_t irda_en:1; - /** rxd_inv : R/W; bitpos: [15]; default: 0; - * Set this bit to inverse the level value of uart rxd signal. - */ - uint32_t rxd_inv:1; - /** txd_inv : R/W; bitpos: [16]; default: 0; - * Set this bit to inverse the level value of uart txd signal. - */ - uint32_t txd_inv:1; - /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; - * Disable UART Rx data overflow detect. - */ - uint32_t dis_rx_dat_ovf:1; - /** err_wr_mask : R/W; bitpos: [18]; default: 0; - * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver - * stores the data even if the received data is wrong. - */ - uint32_t err_wr_mask:1; - /** autobaud_en : R/W; bitpos: [19]; default: 0; - * This is the enable bit for detecting baudrate. - */ - uint32_t autobaud_en:1; - /** mem_clk_en : R/W; bitpos: [20]; default: 0; - * UART memory clock gate enable signal. - */ - uint32_t mem_clk_en:1; - /** sw_rts : R/W; bitpos: [21]; default: 0; - * This register is used to configure the software rts signal which is used in - * software flow control. - */ - uint32_t sw_rts:1; - /** rxfifo_rst : R/W; bitpos: [22]; default: 0; - * Set this bit to reset the uart receive-FIFO. - */ - uint32_t rxfifo_rst:1; - /** txfifo_rst : R/W; bitpos: [23]; default: 0; - * Set this bit to reset the uart transmit-FIFO. - */ - uint32_t txfifo_rst:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} uart_conf0_sync_reg_t; - -/** Type of conf1 register - * Configuration register 1 - */ -typedef union { - struct { - /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96; - * It will produce rxfifo_full_int interrupt when receiver receives more data than - * this register value. - */ - uint32_t rxfifo_full_thrhd:8; - /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96; - * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less - * than this register value. - */ - uint32_t txfifo_empty_thrhd:8; - /** cts_inv : R/W; bitpos: [16]; default: 0; - * Set this bit to inverse the level value of uart cts signal. - */ - uint32_t cts_inv:1; - /** dsr_inv : R/W; bitpos: [17]; default: 0; - * Set this bit to inverse the level value of uart dsr signal. - */ - uint32_t dsr_inv:1; - /** rts_inv : R/W; bitpos: [18]; default: 0; - * Set this bit to inverse the level value of uart rts signal. - */ - uint32_t rts_inv:1; - /** dtr_inv : R/W; bitpos: [19]; default: 0; - * Set this bit to inverse the level value of uart dtr signal. - */ - uint32_t dtr_inv:1; - /** sw_dtr : R/W; bitpos: [20]; default: 0; - * This register is used to configure the software dtr signal which is used in - * software flow control. - */ - uint32_t sw_dtr:1; - /** clk_en : R/W; bitpos: [21]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. - */ - uint32_t clk_en:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} uart_conf1_reg_t; - -/** Type of hwfc_conf_sync register - * Hardware flow-control configuration - */ -typedef union { - struct { - /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0; - * This register is used to configure the maximum amount of data that can be received - * when hardware flow control works. - */ - uint32_t rx_flow_thrhd:8; - /** rx_flow_en : R/W; bitpos: [8]; default: 0; - * This is the flow enable bit for UART receiver. - */ - uint32_t rx_flow_en:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} uart_hwfc_conf_sync_reg_t; - -/** Type of sleep_conf0 register - * UART sleep configure register 0 - */ -typedef union { - struct { - /** wk_char1 : R/W; bitpos: [7:0]; default: 0; - * This register restores the specified wake up char1 to wake up - */ - uint32_t wk_char1:8; - /** wk_char2 : R/W; bitpos: [15:8]; default: 0; - * This register restores the specified wake up char2 to wake up - */ - uint32_t wk_char2:8; - /** wk_char3 : R/W; bitpos: [23:16]; default: 0; - * This register restores the specified wake up char3 to wake up - */ - uint32_t wk_char3:8; - /** wk_char4 : R/W; bitpos: [31:24]; default: 0; - * This register restores the specified wake up char4 to wake up - */ - uint32_t wk_char4:8; - }; - uint32_t val; -} uart_sleep_conf0_reg_t; - -/** Type of sleep_conf1 register - * UART sleep configure register 1 - */ -typedef union { - struct { - /** wk_char0 : R/W; bitpos: [7:0]; default: 0; - * This register restores the specified char0 to wake up - */ - uint32_t wk_char0:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} uart_sleep_conf1_reg_t; - -/** Type of sleep_conf2 register - * UART sleep configure register 2 - */ -typedef union { - struct { - /** active_threshold : R/W; bitpos: [9:0]; default: 240; - * The uart is activated from light sleeping mode when the input rxd edge changes more - * times than this register value. - */ - uint32_t active_threshold:10; - /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1; - * In wake up mode 1 this field is used to set the received data number threshold to - * wake up chip. - */ - uint32_t rx_wake_up_thrhd:8; - /** wk_char_num : R/W; bitpos: [20:18]; default: 5; - * This register is used to select number of wake up char. - */ - uint32_t wk_char_num:3; - /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; - * This register is used to mask wake up char. - */ - uint32_t wk_char_mask:5; - /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; - * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: - * received data number larger than - */ - uint32_t wk_mode_sel:2; - uint32_t reserved_28:4; - }; - uint32_t val; -} uart_sleep_conf2_reg_t; - -/** Type of swfc_conf0_sync register - * Software flow-control character configuration - */ -typedef union { - struct { - /** xon_char : R/W; bitpos: [7:0]; default: 17; - * This register stores the Xon flow control char. - */ - uint32_t xon_char:8; - /** xoff_char : R/W; bitpos: [15:8]; default: 19; - * This register stores the Xoff flow control char. - */ - uint32_t xoff_char:8; - /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; - * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In - * this status, UART Tx can not transmit XOFF even the received data number is larger - * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when - * UART Tx is disabled. - */ - uint32_t xon_xoff_still_send:1; - /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; - * Set this bit to enable software flow control. It is used with register sw_xon or - * sw_xoff. - */ - uint32_t sw_flow_con_en:1; - /** xonoff_del : R/W; bitpos: [18]; default: 0; - * Set this bit to remove flow control char from the received data. - */ - uint32_t xonoff_del:1; - /** force_xon : R/W; bitpos: [19]; default: 0; - * Set this bit to enable the transmitter to go on sending data. - */ - uint32_t force_xon:1; - /** force_xoff : R/W; bitpos: [20]; default: 0; - * Set this bit to stop the transmitter from sending data. - */ - uint32_t force_xoff:1; - /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; - * Set this bit to send Xon char. It is cleared by hardware automatically. - */ - uint32_t send_xon:1; - /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; - * Set this bit to send Xoff char. It is cleared by hardware automatically. - */ - uint32_t send_xoff:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} uart_swfc_conf0_sync_reg_t; - -/** Type of swfc_conf1 register - * Software flow-control character configuration - */ -typedef union { - struct { - /** xon_threshold : R/W; bitpos: [7:0]; default: 0; - * When the data amount in Rx-FIFO is less than this register value with - * uart_sw_flow_con_en set to 1 it will send a Xon char. - */ - uint32_t xon_threshold:8; - /** xoff_threshold : R/W; bitpos: [15:8]; default: 224; - * When the data amount in Rx-FIFO is more than this register value with - * uart_sw_flow_con_en set to 1 it will send a Xoff char. - */ - uint32_t xoff_threshold:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} uart_swfc_conf1_reg_t; - -/** Type of txbrk_conf_sync register - * Tx Break character configuration - */ -typedef union { - struct { - /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; - * This register is used to configure the number of 0 to be sent after the process of - * sending data is done. It is active when txd_brk is set to 1. - */ - uint32_t tx_brk_num:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} uart_txbrk_conf_sync_reg_t; - -/** Type of idle_conf_sync register - * Frame-end idle configuration - */ -typedef union { - struct { - /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; - * It will produce frame end signal when receiver takes more time to receive one byte - * data than this register value. - */ - uint32_t rx_idle_thrhd:10; - /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; - * This register is used to configure the duration time between transfers. - */ - uint32_t tx_idle_num:10; - uint32_t reserved_20:12; - }; - uint32_t val; -} uart_idle_conf_sync_reg_t; - -/** Type of rs485_conf_sync register - * RS485 mode configuration - */ -typedef union { - struct { - /** rs485_en : R/W; bitpos: [0]; default: 0; - * Set this bit to choose the rs485 mode. - */ - uint32_t rs485_en:1; - /** dl0_en : R/W; bitpos: [1]; default: 0; - * Set this bit to delay the stop bit by 1 bit. - */ - uint32_t dl0_en:1; - /** dl1_en : R/W; bitpos: [2]; default: 0; - * Set this bit to delay the stop bit by 1 bit. - */ - uint32_t dl1_en:1; - /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0; - * Set this bit to enable receiver could receive data when the transmitter is - * transmitting data in rs485 mode. - */ - uint32_t rs485tx_rx_en:1; - /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0; - * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. - */ - uint32_t rs485rxby_tx_en:1; - /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0; - * This register is used to delay the receiver's internal data signal. - */ - uint32_t rs485_rx_dly_num:1; - /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0; - * This register is used to delay the transmitter's internal data signal. - */ - uint32_t rs485_tx_dly_num:4; - uint32_t reserved_10:22; - }; - uint32_t val; -} uart_rs485_conf_sync_reg_t; - -/** Type of clk_conf register - * UART core clock configuration - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** tx_sclk_en : R/W; bitpos: [24]; default: 1; - * Set this bit to enable UART Tx clock. - */ - uint32_t tx_sclk_en:1; - /** rx_sclk_en : R/W; bitpos: [25]; default: 1; - * Set this bit to enable UART Rx clock. - */ - uint32_t rx_sclk_en:1; - /** tx_rst_core : R/W; bitpos: [26]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx. - */ - uint32_t tx_rst_core:1; - /** rx_rst_core : R/W; bitpos: [27]; default: 0; - * Write 1 then write 0 to this bit to reset UART Rx. - */ - uint32_t rx_rst_core:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} uart_clk_conf_reg_t; - - -/** Group: Status Register */ -/** Type of status register - * UART status register - */ -typedef union { - struct { - /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0; - * Stores the byte number of valid data in Rx-FIFO. - */ - uint32_t rxfifo_cnt:8; - uint32_t reserved_8:5; - /** dsrn : RO; bitpos: [13]; default: 0; - * The register represent the level value of the internal uart dsr signal. - */ - uint32_t dsrn:1; - /** ctsn : RO; bitpos: [14]; default: 1; - * This register represent the level value of the internal uart cts signal. - */ - uint32_t ctsn:1; - /** rxd : RO; bitpos: [15]; default: 1; - * This register represent the level value of the internal uart rxd signal. - */ - uint32_t rxd:1; - /** txfifo_cnt : RO; bitpos: [23:16]; default: 0; - * Stores the byte number of data in Tx-FIFO. - */ - uint32_t txfifo_cnt:8; - uint32_t reserved_24:5; - /** dtrn : RO; bitpos: [29]; default: 1; - * This bit represents the level of the internal uart dtr signal. - */ - uint32_t dtrn:1; - /** rtsn : RO; bitpos: [30]; default: 1; - * This bit represents the level of the internal uart rts signal. - */ - uint32_t rtsn:1; - /** txd : RO; bitpos: [31]; default: 1; - * This bit represents the level of the internal uart txd signal. - */ - uint32_t txd:1; - }; - uint32_t val; -} uart_status_reg_t; - -/** Type of mem_tx_status register - * Tx-SRAM write and read offset address. - */ -typedef union { - struct { - /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0; - * This register stores the offset write address in Tx-SRAM. - */ - uint32_t tx_sram_waddr:8; - uint32_t reserved_8:1; - /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0; - * This register stores the offset read address in Tx-SRAM. - */ - uint32_t tx_sram_raddr:8; - uint32_t reserved_17:15; - }; - uint32_t val; -} uart_mem_tx_status_reg_t; - -/** Type of mem_rx_status register - * Rx-SRAM write and read offset address. - */ -typedef union { - struct { - /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128; - * This register stores the offset read address in RX-SRAM. - */ - uint32_t rx_sram_raddr:8; - uint32_t reserved_8:1; - /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128; - * This register stores the offset write address in Rx-SRAM. - */ - uint32_t rx_sram_waddr:8; - uint32_t reserved_17:15; - }; - uint32_t val; -} uart_mem_rx_status_reg_t; - -/** Type of fsm_status register - * UART transmit and receive status. - */ -typedef union { - struct { - /** st_urx_out : RO; bitpos: [3:0]; default: 0; - * This is the status register of receiver. - */ - uint32_t st_urx_out:4; - /** st_utx_out : RO; bitpos: [7:4]; default: 0; - * This is the status register of transmitter. - */ - uint32_t st_utx_out:4; - uint32_t reserved_8:24; - }; - uint32_t val; -} uart_fsm_status_reg_t; - -/** Type of afifo_status register - * UART AFIFO Status - */ -typedef union { - struct { - /** tx_afifo_full : RO; bitpos: [0]; default: 0; - * Full signal of APB TX AFIFO. - */ - uint32_t tx_afifo_full:1; - /** tx_afifo_empty : RO; bitpos: [1]; default: 1; - * Empty signal of APB TX AFIFO. - */ - uint32_t tx_afifo_empty:1; - /** rx_afifo_full : RO; bitpos: [2]; default: 0; - * Full signal of APB RX AFIFO. - */ - uint32_t rx_afifo_full:1; - /** rx_afifo_empty : RO; bitpos: [3]; default: 1; - * Empty signal of APB RX AFIFO. - */ - uint32_t rx_afifo_empty:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} uart_afifo_status_reg_t; - - -/** Group: AT Escape Sequence Selection Configuration */ -/** Type of at_cmd_precnt_sync register - * Pre-sequence timing configuration - */ -typedef union { - struct { - /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; - * This register is used to configure the idle duration time before the first at_cmd - * is received by receiver. - */ - uint32_t pre_idle_num:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} uart_at_cmd_precnt_sync_reg_t; - -/** Type of at_cmd_postcnt_sync register - * Post-sequence timing configuration - */ -typedef union { - struct { - /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; - * This register is used to configure the duration time between the last at_cmd and - * the next data. - */ - uint32_t post_idle_num:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} uart_at_cmd_postcnt_sync_reg_t; - -/** Type of at_cmd_gaptout_sync register - * Timeout configuration - */ -typedef union { - struct { - /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; - * This register is used to configure the duration time between the at_cmd chars. - */ - uint32_t rx_gap_tout:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} uart_at_cmd_gaptout_sync_reg_t; - -/** Type of at_cmd_char_sync register - * AT escape sequence detection configuration - */ -typedef union { - struct { - /** at_cmd_char : R/W; bitpos: [7:0]; default: 43; - * This register is used to configure the content of at_cmd char. - */ - uint32_t at_cmd_char:8; - /** char_num : R/W; bitpos: [15:8]; default: 3; - * This register is used to configure the num of continuous at_cmd chars received by - * receiver. - */ - uint32_t char_num:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} uart_at_cmd_char_sync_reg_t; - - -/** Group: Autobaud Register */ -/** Type of pospulse register - * Autobaud high pulse register - */ -typedef union { - struct { - /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095; - * This register stores the minimal input clock count between two positive edges. It - * is used in boudrate-detect process. - */ - uint32_t posedge_min_cnt:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} uart_pospulse_reg_t; - -/** Type of negpulse register - * Autobaud low pulse register - */ -typedef union { - struct { - /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095; - * This register stores the minimal input clock count between two negative edges. It - * is used in boudrate-detect process. - */ - uint32_t negedge_min_cnt:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} uart_negpulse_reg_t; - -/** Type of lowpulse register - * Autobaud minimum low pulse duration register - */ -typedef union { - struct { - /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the minimum duration time of the low level pulse. - * It is used in baud rate-detect process. - */ - uint32_t lowpulse_min_cnt:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} uart_lowpulse_reg_t; - -/** Type of highpulse register - * Autobaud minimum high pulse duration register - */ -typedef union { - struct { - /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maximum duration time for the high level - * pulse. It is used in baud rate-detect process. - */ - uint32_t highpulse_min_cnt:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} uart_highpulse_reg_t; - -/** Type of rxd_cnt register - * Autobaud edge change count register - */ -typedef union { - struct { - /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0; - * This register stores the count of rxd edge change. It is used in baud rate-detect - * process. - */ - uint32_t rxd_edge_cnt:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} uart_rxd_cnt_reg_t; - - -/** Group: Version Register */ -/** Type of date register - * UART Version register - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 36720720; - * This is the version register. - */ - uint32_t date:32; - }; - uint32_t val; -} uart_date_reg_t; - -/** Type of reg_update register - * UART Registers Configuration Update register - */ -typedef union { - struct { - /** reg_update : R/W/SC; bitpos: [0]; default: 0; - * Software write 1 would synchronize registers into UART Core clock domain and would - * be cleared by hardware after synchronization is done. - */ - uint32_t reg_update:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} uart_reg_update_reg_t; - -/** Type of id register - * UART ID register - */ -typedef union { - struct { - /** id : R/W; bitpos: [31:0]; default: 1280; - * This register is used to configure the uart_id. - */ - uint32_t id:32; - }; - uint32_t val; -} uart_id_reg_t; - - -typedef struct { - volatile uart_fifo_reg_t fifo; - volatile uart_int_raw_reg_t int_raw; - volatile uart_int_st_reg_t int_st; - volatile uart_int_ena_reg_t int_ena; - volatile uart_int_clr_reg_t int_clr; - volatile uart_clkdiv_sync_reg_t clkdiv_sync; - volatile uart_rx_filt_reg_t rx_filt; - volatile uart_status_reg_t status; - volatile uart_conf0_sync_reg_t conf0_sync; - volatile uart_conf1_reg_t conf1; - uint32_t reserved_028; - volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync; - volatile uart_sleep_conf0_reg_t sleep_conf0; - volatile uart_sleep_conf1_reg_t sleep_conf1; - volatile uart_sleep_conf2_reg_t sleep_conf2; - volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync; - volatile uart_swfc_conf1_reg_t swfc_conf1; - volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync; - volatile uart_idle_conf_sync_reg_t idle_conf_sync; - volatile uart_rs485_conf_sync_reg_t rs485_conf_sync; - volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; - volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; - volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; - volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync; - volatile uart_mem_conf_reg_t mem_conf; - volatile uart_tout_conf_sync_reg_t tout_conf_sync; - volatile uart_mem_tx_status_reg_t mem_tx_status; - volatile uart_mem_rx_status_reg_t mem_rx_status; - volatile uart_fsm_status_reg_t fsm_status; - volatile uart_pospulse_reg_t pospulse; - volatile uart_negpulse_reg_t negpulse; - volatile uart_lowpulse_reg_t lowpulse; - volatile uart_highpulse_reg_t highpulse; - volatile uart_rxd_cnt_reg_t rxd_cnt; - volatile uart_clk_conf_reg_t clk_conf; - volatile uart_date_reg_t date; - volatile uart_afifo_status_reg_t afifo_status; - uint32_t reserved_094; - volatile uart_reg_update_reg_t reg_update; - volatile uart_id_reg_t id; -} uart_dev_t; - -extern uart_dev_t UART0; -extern uart_dev_t UART1; -extern uart_dev_t UART2; -extern uart_dev_t UART3; -extern uart_dev_t UART4; - -#ifndef __cplusplus -_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/uart_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/uart_reg.h index 66c4081a96..ba938dfb8b 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/uart_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/uart_reg.h @@ -11,8 +11,6 @@ extern "C" { #endif -// TODO: IDF-13425 - /** UART_FIFO_REG register * FIFO data register */ diff --git a/components/soc/esp32p4/register/hw_ver3/soc/uart_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/uart_struct.h index 5b98af7ceb..3fc2f5ed87 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/uart_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/uart_struct.h @@ -10,8 +10,6 @@ extern "C" { #endif -// TODO: IDF-13425 - /** Group: FIFO Configuration */ /** Type of fifo register * FIFO data register @@ -21,7 +19,8 @@ typedef union { /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; * UART $n accesses FIFO via this register. */ - uint32_t rxfifo_rd_byte:32; + uint32_t rxfifo_rd_byte:8; + uint32_t reserved_8:24; }; uint32_t val; } uart_fifo_reg_t; diff --git a/docs/en/api-reference/peripherals/ledc.rst b/docs/en/api-reference/peripherals/ledc.rst index 733caf8361..8e6ebb6df8 100644 --- a/docs/en/api-reference/peripherals/ledc.rst +++ b/docs/en/api-reference/peripherals/ledc.rst @@ -279,6 +279,10 @@ The range of the duty cycle values passed to functions depends on selected ``dut The hardware limitation above only applies to chip revision before v1.2. + .. only:: esp32p4 + + The hardware limitation above only applies to chip revision before v3.0. + Change PWM Duty Cycle Using Hardware """""""""""""""""""""""""""""""""""" diff --git a/docs/zh_CN/api-reference/peripherals/ledc.rst b/docs/zh_CN/api-reference/peripherals/ledc.rst index 35bc239bc8..e0f90125e2 100644 --- a/docs/zh_CN/api-reference/peripherals/ledc.rst +++ b/docs/zh_CN/api-reference/peripherals/ledc.rst @@ -279,6 +279,10 @@ LEDC 驱动提供了一个辅助函数 :cpp:func:`ledc_find_suitable_duty_resolu 以上硬件限制仅在芯片版本低于 v1.2 的 ESP32H2 上存在。 + .. only:: esp32p4 + + 以上硬件限制仅在芯片版本低于 v3.0 的 ESP32P4 上存在。 + 使用硬件改变 PWM 占空比 """""""""""""""""""""""""""""""""""" diff --git a/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c b/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c index c3ce8d240f..60ba69b059 100644 --- a/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c +++ b/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c @@ -19,7 +19,7 @@ #define LEDC_FREQUENCY (4000) // Frequency in Hertz. Set frequency at 4 kHz /* Warning: - * For ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4 targets, + * For ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4 (rev < 3.0) targets, * when LEDC_DUTY_RES selects the maximum duty resolution (i.e. value equal to SOC_LEDC_TIMER_BIT_WIDTH), * 100% duty cycle is not reachable (duty cannot be set to (2 ** SOC_LEDC_TIMER_BIT_WIDTH)). */