diff --git a/components/esp_adc/test_apps/.build-test-rules.yml b/components/esp_adc/test_apps/.build-test-rules.yml index 920d6b3a7d..42741cd863 100644 --- a/components/esp_adc/test_apps/.build-test-rules.yml +++ b/components/esp_adc/test_apps/.build-test-rules.yml @@ -13,3 +13,8 @@ components/esp_adc/test_apps/adc: - esp_hw_support - esp_hal_ana_conv - soc + + disable_test: + - if: IDF_TARGET in ["esp32h4"] + temporary: true + reason: no runners for esp32h4 ADC test diff --git a/components/esp_adc/test_apps/adc/README.md b/components/esp_adc/test_apps/adc/README.md index 7b96141437..fe0a409792 100644 --- a/components/esp_adc/test_apps/adc/README.md +++ b/components/esp_adc/test_apps/adc/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_adc/test_apps/adc/include/adc_performance.h b/components/esp_adc/test_apps/adc/include/adc_performance.h index a6d5f94f39..2d819238a7 100644 --- a/components/esp_adc/test_apps/adc/include/adc_performance.h +++ b/components/esp_adc/test_apps/adc/include/adc_performance.h @@ -1,4 +1,4 @@ -/* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +/* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -84,4 +84,12 @@ #define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_64 10 #define IDF_PERFORMANCE_MAX_ADC_ONESHOT_STD_ATTEN3 10 +#elif CONFIG_IDF_TARGET_ESP32H4 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_NO_FILTER 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_2 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_4 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_8 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_16 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_64 10 +#define IDF_PERFORMANCE_MAX_ADC_ONESHOT_STD_ATTEN3 10 #endif diff --git a/components/esp_adc/test_apps/adc/main/test_common_adc.h b/components/esp_adc/test_apps/adc/main/test_common_adc.h index f8f29eeee1..b0f697c565 100644 --- a/components/esp_adc/test_apps/adc/main/test_common_adc.h +++ b/components/esp_adc/test_apps/adc/main/test_common_adc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -111,6 +111,14 @@ extern "C" { #define ADC_TEST_HIGH_VAL_DMA 4095 #define ADC_TEST_HIGH_THRESH 200 +#elif CONFIG_IDF_TARGET_ESP32H4 +#define ADC_TEST_LOW_VAL 2100 +#define ADC_TEST_LOW_THRESH 200 + +#define ADC_TEST_HIGH_VAL 4095 +#define ADC_TEST_HIGH_VAL_DMA 4095 +#define ADC_TEST_HIGH_THRESH 200 + #endif /*--------------------------------------------------------------- diff --git a/components/esp_hal_ana_conv/esp32h4/adc_periph.c b/components/esp_hal_ana_conv/esp32h4/adc_periph.c new file mode 100644 index 0000000000..1774f703c6 --- /dev/null +++ b/components/esp_hal_ana_conv/esp32h4/adc_periph.c @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "hal/adc_periph.h" + +/* Store IO number corresponding to the ADC channel number. */ +const int adc_channel_io_map[1][5] = { + /* ADC1 */ + { + ADC1_CHANNEL_0_GPIO_NUM, + ADC1_CHANNEL_1_GPIO_NUM, + ADC1_CHANNEL_2_GPIO_NUM, + ADC1_CHANNEL_3_GPIO_NUM, + ADC1_CHANNEL_4_GPIO_NUM, + }, +}; diff --git a/components/esp_hal_ana_conv/esp32h4/include/hal/adc_ll.h b/components/esp_hal_ana_conv/esp32h4/include/hal/adc_ll.h new file mode 100644 index 0000000000..28086f7276 --- /dev/null +++ b/components/esp_hal_ana_conv/esp32h4/include/hal/adc_ll.h @@ -0,0 +1,933 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "esp_attr.h" + +#include "hal/adc_periph.h" +#include "soc/apb_saradc_struct.h" +#include "soc/apb_saradc_reg.h" +#include "soc/pmu_reg.h" +#include "soc/clk_tree_defs.h" +#include "soc/pcr_struct.h" +#include "hal/misc.h" +#include "hal/assert.h" +#include "hal/adc_types.h" +#include "hal/adc_types_private.h" +#include "hal/regi2c_ctrl.h" +#include "hal/sar_ctrl_ll.h" + +#include "soc/regi2c_saradc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31) +#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30) + +#define ADC_LL_THRES_ALL_INTR_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M | \ + APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M | \ + APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M | \ + APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M) +#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M) +#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M) + +#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (1) +#define ADC_LL_ADC_FE_ON_MODEM_DOMAIN (1) + +#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0 +/*--------------------------------------------------------------- + Oneshot +---------------------------------------------------------------*/ +#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) +#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (5) + +/*--------------------------------------------------------------- + DMA +---------------------------------------------------------------*/ +#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) +#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8) +#define ADC_LL_FSM_START_WAIT_DEFAULT (5) +#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100) +#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2) +#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1) + +/* Use 32 MHz XTAL / (5 + 2 / 5 + 1) = 5 MHz ADC_CTRL_CLK on H4. */ +#define ADC_LL_CLKM_DIV_NUM_DEFAULT 5 +#define ADC_LL_CLKM_DIV_B_DEFAULT 5 +#define ADC_LL_CLKM_DIV_A_DEFAULT 2 +#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 +#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255 + +#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32H4 supported to manage power mode +/*--------------------------------------------------------------- + PWDET (Power Detect) +---------------------------------------------------------------*/ +#define ADC_LL_PWDET_CCT_DEFAULT (4) + +typedef enum { + ADC_LL_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ + ADC_LL_POWER_SW_ON = SAR_CTRL_LL_POWER_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ + ADC_LL_POWER_SW_OFF = SAR_CTRL_LL_POWER_OFF, /*!< ADC XPD controlled by SW. power off. */ +} adc_ll_power_t; + +typedef enum { + ADC_LL_CTRL_DIG = 0, ///< ADC digital controller +} adc_ll_controller_t; + +/** + * @brief ADC digital controller (DMA mode) work mode. + * + * @note The conversion mode affects the sampling frequency: + * ESP32H4 only support ONLY_ADC1 mode + * SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once. + */ +typedef enum { + ADC_LL_DIGI_CONV_ONLY_ADC1 = 0, // Only use ADC1 for conversion +} adc_ll_digi_convert_mode_t; + +typedef struct { + union { + struct { + uint8_t atten: 2; + uint8_t channel: 3; + uint8_t unit: 1; + uint8_t reserved: 2; + }; + uint8_t val; + }; +} __attribute__((packed)) adc_ll_digi_pattern_table_t; + +/*--------------------------------------------------------------- + Digital controller setting +---------------------------------------------------------------*/ + +/** + * Set adc fsm interval parameter for digital controller. These values are fixed for same platforms. + * + * @param rst_wait cycles between DIG ADC controller reset ADC sensor and start ADC sensor. + * @param start_wait Delay time after open xpd. + * @param standby_wait Delay time to close xpd. + */ +static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait) +{ + //For compatibility +} + +/** + * Set adc sample cycle for digital controller. + * + * @note Normally, please use default value. + * @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor. + * Range: 2 ~ 0xFF. + */ +static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle) +{ + /* Analog i2c master clock needs to be enabled for regi2c operations (done inside REGI2C_WRITE_MASK) */ + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle); +} + +/** + * Set SAR ADC module clock division factor. + * SAR ADC clock divided from digital controller clock. + * + * @param div Division factor. + */ +__attribute__((always_inline)) +static inline void adc_ll_digi_set_clk_div(uint32_t div) +{ + /* ADC clock divided from digital controller clock clk */ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.sar_clk_div, sar1_clk_div_num, div); +} + +/** + * Set adc max conversion number for digital controller. + * If the number of ADC conversion is equal to the maximum, the conversion is stopped. + * + * @param meas_num Max conversion number. Range: 0 ~ 255. + */ +static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_ctrl2, saradc_saradc_max_meas_num, meas_num); +} + +/** + * Enable max conversion number detection for digital controller. + * If the number of ADC conversion is equal to the maximum, the conversion is stopped. + * + * @param enable true: enable; false: disable + */ +static inline void adc_ll_digi_convert_limit_enable(bool enable) +{ + APB_SARADC.saradc_ctrl2.saradc_saradc_meas_num_limit = enable; +} + +/** + * Set adc conversion mode for digital controller. + * + * @note ESP32H4 only support ADC1 single mode. + * + * @param mode Conversion mode select. + */ +static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode) +{ + //ESP32H4 only supports ADC_LL_DIGI_CONV_ONLY_ADC1 mode +} + +/** + * Set pattern table length for digital controller. + * The pattern table that defines the conversion rules for each SAR ADC. Each table has 4 items, in which channel selection, + * and attenuation are stored. When the conversion is started, the controller reads conversion rules from the + * pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself. + * + * @param adc_n ADC unit. + * @param patt_len Items range: 1 ~ 8. + */ +__attribute__((always_inline)) +static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len) +{ + APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1; +} + +/** + * Set pattern table for digital controller. + * The pattern table that defines the conversion rules for each SAR ADC. Each table has 4 items, in which channel selection, + * resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the + * pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself. + * + * @param adc_n ADC unit. + * @param pattern_index Items index. Range: 0 ~ 7. + * @param pattern Stored conversion rules. + */ +__attribute__((always_inline)) +static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table) +{ + uint32_t tab; + uint8_t index = pattern_index / 4; + uint8_t offset = (pattern_index % 4) * 6; + adc_ll_digi_pattern_table_t pattern = {0}; + + pattern.val = (table.atten & 0x3) | ((table.channel & 0x7) << 2) | ((table.unit & 0x1) << 5); + if (index == 0) { + tab = APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1; // Read old register value + tab &= (~(0xFC0000 >> offset)); // Clear old data + tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data + APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1 = tab; // Write back + } else { + tab = APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2; // Read old register value + tab &= (~(0xFC0000 >> offset)); // Clear old data + tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data + APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2 = tab; // Write back + } +} + +/** + * Rest pattern table to default value + */ +static inline void adc_ll_digi_reset_pattern_table(void) +{ + APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1 = 0xffffff; + APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2 = 0xffffff; +} + +/** + * Reset the pattern table pointer, then take the measurement rule from table header in next measurement. + * + * @param adc_n ADC unit. + */ +static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n) +{ + APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_p_clear = 1; + APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_p_clear = 0; +} + +/** + * Sets the number of cycles required for the conversion to complete and wait for the arbiter to stabilize. + * + * @note Only ADC2 have arbiter function. + * @param cycle range: 0 ~ 4. + */ +static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle) +{ + APB_SARADC.saradc_ctrl.saradc_saradc_wait_arb_cycle = cycle; +} + +/** + * ADC Digital controller output data invert or not. + * + * @param adc_n ADC unit. + * @param inv_en data invert or not. + */ +static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en) +{ + if (adc_n == ADC_UNIT_1) { + APB_SARADC.saradc_ctrl2.saradc_saradc_sar1_inv = inv_en; // Enable / Disable ADC data invert + } +} + +/** + * Set the interval clock cycle for the digital controller to trigger the measurement. + * Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. + * + * @note The trigger interval should not be smaller than the sampling time of the SAR ADC. + * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095. + */ +__attribute__((always_inline)) +static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle) +{ + APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle; +} + +/** + * Enable digital controller timer to trigger the measurement. + */ +__attribute__((always_inline)) +static inline void adc_ll_digi_trigger_enable(void) +{ + APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1; +} + +/** + * Disable digital controller timer to trigger the measurement. + */ +__attribute__((always_inline)) +static inline void adc_ll_digi_trigger_disable(void) +{ + APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0; +} + +/** + * Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock. + * Expression: controller_clk = (APLL or APB) / (div_num + div_a / div_b + 1). + * + * @param div_num Division factor. Range: 0 ~ 255. + * @param div_b Division factor. Range: 1 ~ 63. + * @param div_a Division factor. Range: 0 ~ 63. + */ +__attribute__((always_inline)) +static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num); + PCR.saradc_clkm_conf.saradc_clkm_div_b = div_b; + PCR.saradc_clkm_conf.saradc_clkm_div_a = div_a; +} + +/** + * Enable clock and select clock source for ADC digital controller. + * + * @param clk_src clock source for ADC digital controller. + */ +__attribute__((always_inline)) +static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src) +{ + switch (clk_src) { + case ADC_DIGI_CLK_SRC_XTAL: + PCR.saradc_clkm_conf.saradc_clkm_sel = 0; + break; + case ADC_DIGI_CLK_SRC_RC_FAST: + PCR.saradc_clkm_conf.saradc_clkm_sel = 1; + break; + default: + HAL_ASSERT(false && "unsupported clock"); + } + // Enable ADC_CTRL_CLK (i.e. digital domain clock) + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; +} + +/** + * Disable clock for ADC digital controller. + */ +static inline void adc_ll_digi_controller_clk_disable(void) +{ + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0; +} + +/** + * Reset adc digital controller filter. + * + * @param idx Filter index + * @param adc_n ADC unit. + */ +static inline void adc_ll_digi_filter_reset(adc_digi_iir_filter_t idx, adc_unit_t adc_n) +{ + (void)adc_n; + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_reset = 1; + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_reset = 0; +} + +/** + * Set adc digital controller filter coeff. + * + * @param idx filter index + * @param adc_n adc unit + * @param channel adc channel + * @param coeff filter coeff + */ +static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_unit_t adc_n, adc_channel_t channel, adc_digi_iir_filter_coeff_t coeff) +{ + uint32_t factor_reg_val = 0; + switch (coeff) { + case ADC_DIGI_IIR_FILTER_COEFF_2: + factor_reg_val = 1; + break; + case ADC_DIGI_IIR_FILTER_COEFF_4: + factor_reg_val = 2; + break; + case ADC_DIGI_IIR_FILTER_COEFF_8: + factor_reg_val = 3; + break; + case ADC_DIGI_IIR_FILTER_COEFF_16: + factor_reg_val = 4; + break; + case ADC_DIGI_IIR_FILTER_COEFF_64: + factor_reg_val = 6; + break; + default: + HAL_ASSERT(false); + } + + if (idx == ADC_DIGI_IIR_FILTER_0) { + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_channel0 = ((adc_n + 1) << 3) | (channel & 0x7); + APB_SARADC.saradc_filter_ctrl1.saradc_apb_saradc_filter_factor0 = factor_reg_val; + } else if (idx == ADC_DIGI_IIR_FILTER_1) { + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_channel1 = ((adc_n + 1) << 3) | (channel & 0x7); + APB_SARADC.saradc_filter_ctrl1.saradc_apb_saradc_filter_factor1 = factor_reg_val; + } +} + +/** + * Enable adc digital controller filter. + * Filtering the ADC data to obtain smooth data at higher sampling rates. + * + * @param idx filter index + * @param adc_n ADC unit + * @param enable Enable / Disable + */ +static inline void adc_ll_digi_filter_enable(adc_digi_iir_filter_t idx, adc_unit_t adc_n, bool enable) +{ + (void)adc_n; + if (!enable) { + if (idx == ADC_DIGI_IIR_FILTER_0) { + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_channel0 = 0xF; + APB_SARADC.saradc_filter_ctrl1.saradc_apb_saradc_filter_factor0 = 0; + } else if (idx == ADC_DIGI_IIR_FILTER_1) { + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_channel1 = 0xF; + APB_SARADC.saradc_filter_ctrl1.saradc_apb_saradc_filter_factor1 = 0; + } + } + //nothing to do to enable, after adc_ll_digi_filter_set_factor, it's enabled. +} + +/** + * Set monitor threshold of adc digital controller on specific channel. + * + * @param monitor_id ADC digi monitor unit index. + * @param adc_n Which adc unit the channel belong to. + * @param channel Which channel of adc want to be monitored. + * @param h_thresh High threshold of this monitor. + * @param l_thresh Low threshold of this monitor. + */ +static inline void adc_ll_digi_monitor_set_thres(adc_monitor_id_t monitor_id, adc_unit_t adc_n, uint8_t channel, int32_t h_thresh, int32_t l_thresh) +{ + if (monitor_id == ADC_MONITOR_0) { + APB_SARADC.saradc_thres0_ctrl.saradc_apb_saradc_thres0_channel = (adc_n << 3) | (channel & 0x7); + APB_SARADC.saradc_thres0_ctrl.saradc_apb_saradc_thres0_high = h_thresh; + APB_SARADC.saradc_thres0_ctrl.saradc_apb_saradc_thres0_low = l_thresh; + } else { // ADC_MONITOR_1 + APB_SARADC.saradc_thres1_ctrl.saradc_apb_saradc_thres1_channel = (adc_n << 3) | (channel & 0x7); + APB_SARADC.saradc_thres1_ctrl.saradc_apb_saradc_thres1_high = h_thresh; + APB_SARADC.saradc_thres1_ctrl.saradc_apb_saradc_thres1_low = l_thresh; + } +} + +/** + * Start/Stop monitor of adc digital controller. + * + * @param monitor_id ADC digi monitor unit index. + * @param start 1 for start, 0 for stop + */ +static inline void adc_ll_digi_monitor_user_start(adc_monitor_id_t monitor_id, bool start) +{ + if (monitor_id == ADC_MONITOR_0) { + APB_SARADC.saradc_thres_ctrl.saradc_apb_saradc_thres0_en = start; + } else { + APB_SARADC.saradc_thres_ctrl.saradc_apb_saradc_thres1_en = start; + } +} + +/** + * Enable/disable a intr of adc digital monitor. + * + * @param monitor_id ADC digi monitor unit index. + * @param mode monit mode to enable/disable intr. + * @param enable enable or disable. + */ +static inline void adc_ll_digi_monitor_enable_intr(adc_monitor_id_t monitor_id, adc_monitor_mode_t mode, bool enable) +{ + if (monitor_id == ADC_MONITOR_0) { + if (mode == ADC_MONITOR_MODE_HIGH) { + APB_SARADC.saradc_int_ena.saradc_apb_saradc_thres0_high_int_ena = enable; + } else { + APB_SARADC.saradc_int_ena.saradc_apb_saradc_thres0_low_int_ena = enable; + } + } + if (monitor_id == ADC_MONITOR_1) { + if (mode == ADC_MONITOR_MODE_HIGH) { + APB_SARADC.saradc_int_ena.saradc_apb_saradc_thres1_high_int_ena = enable; + } else { + APB_SARADC.saradc_int_ena.saradc_apb_saradc_thres1_low_int_ena = enable; + } + } +} + +/** + * Clear intr raw for adc digi monitors. + */ +__attribute__((always_inline)) +static inline void adc_ll_digi_monitor_clear_intr(void) +{ + APB_SARADC.saradc_int_clr.val |= ADC_LL_THRES_ALL_INTR_ST_M; +} + +/** + * Get the address of digi monitor intr statue register. + * + * @return address of register. + */ +__attribute__((always_inline)) +static inline volatile const void *adc_ll_digi_monitor_get_intr_status_addr(void) +{ + return &APB_SARADC.saradc_int_st.val; +} + +/** + * Set DMA eof num of adc digital controller. + * If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated. + * + * @param num eof num of DMA. + */ +static inline void adc_ll_digi_dma_set_eof_num(uint32_t num) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_dma_conf, saradc_apb_adc_eof_num, num); +} + +/** + * Enable output data to DMA from adc digital controller. + */ +static inline void adc_ll_digi_dma_enable(void) +{ + APB_SARADC.saradc_dma_conf.saradc_apb_adc_trans = 1; +} + +/** + * Disable output data to DMA from adc digital controller. + */ +static inline void adc_ll_digi_dma_disable(void) +{ + APB_SARADC.saradc_dma_conf.saradc_apb_adc_trans = 0; +} + +/** + * Reset adc digital controller. + */ +static inline void adc_ll_digi_reset(void) +{ + APB_SARADC.saradc_dma_conf.saradc_apb_adc_reset_fsm = 1; + APB_SARADC.saradc_dma_conf.saradc_apb_adc_reset_fsm = 0; +} + +/*--------------------------------------------------------------- + PWDET(Power detect) controller setting +---------------------------------------------------------------*/ +/** + * Set adc cct for PWDET controller. + * + * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY. + * @param cct Range: 0 ~ 7. + */ +static inline void adc_ll_pwdet_set_cct(uint32_t cct) +{ + (void)cct; +} + +/** + * Get adc cct for PWDET controller. + * + * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY. + * @return cct Range: 0 ~ 7. + */ +static inline uint32_t adc_ll_pwdet_get_cct(void) +{ + return 0; +} + +/*--------------------------------------------------------------- + Common setting +---------------------------------------------------------------*/ + +/** + * @brief Enable the ADC clock + * @param enable true to enable, false to disable + */ +__attribute__((always_inline)) +static inline void adc_ll_enable_bus_clock(bool enable) +{ + PCR.saradc_conf.saradc_reg_clk_en = enable; +} + +/** + * @brief Enable the ADC function clock + * @param enable true to enable, false to disable + */ +__attribute__((always_inline)) +static inline void adc_ll_enable_func_clock(bool enable) +{ + PCR.saradc_clkm_conf.saradc_clkm_en = enable; +} + +/** + * @brief Reset ADC module + */ +__attribute__((always_inline)) +static inline void adc_ll_reset_register(void) +{ + PCR.saradc_conf.saradc_rst_en = 1; + PCR.saradc_conf.saradc_rst_en = 0; + PCR.saradc_conf.saradc_reg_rst_en = 1; + PCR.saradc_conf.saradc_reg_rst_en = 0; +} +/** + * Set ADC module power management. + * + * @param manage Set ADC power status. + */ +static inline void adc_ll_set_power_manage(adc_unit_t adc_n, adc_ll_power_t manage) +{ + (void) adc_n; + /* Bit1 0:Fsm 1: SW mode + Bit0 0:SW mode power down 1: SW mode power on */ + if (manage == ADC_LL_POWER_SW_ON) { + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; + APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 3; + } else if (manage == ADC_LL_POWER_BY_FSM) { + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; + APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 0; + } else if (manage == ADC_LL_POWER_SW_OFF) { + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0; + APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 2; + } +} + +__attribute__((always_inline)) +static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl) +{ + //Not used on ESP32H4 +} + +/* ADC calibration code. */ +/** + * @brief Set common calibration configuration. Should be shared with other parts (PWDET). + */ +__attribute__((always_inline)) +static inline void adc_ll_calibration_init(adc_unit_t adc_n) +{ + (void)adc_n; + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1); +} + +/** + * Configure the registers for ADC calibration. You need to call the ``adc_ll_calibration_finish`` interface to resume after calibration. + * + * @note Different ADC units and different attenuation options use different calibration data (initial data). + * + * @param adc_n ADC index number. + * @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage. + * false: Use IO external voltage as calibration voltage. + */ +static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, bool internal_gnd) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + /* Enable/disable internal connect GND (for calibration). */ + if (internal_gnd) { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); + } else { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); + } +} + +/** + * Resume register status after calibration. + * + * @param adc_n ADC index number. + */ +static inline void adc_ll_calibration_finish(adc_unit_t adc_n) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); +} + +/** + * Set the calibration result to ADC. + * + * @note Different ADC units and different attenuation options use different calibration data (initial data). + * + * @param adc_n ADC index number. + * @param param calibration param + */ +__attribute__((always_inline)) +static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param) +{ + uint8_t msb = param >> 8; + uint8_t lsb = param & 0xFF; + + if (adc_n == ADC_UNIT_1) { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); + } else { + //H4 doesn't support ADC2, here is for backward compatibility for RNG + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb); + } +} + +/** + * Set the SAR DTEST param + * + * @param param DTEST value + */ +__attribute__((always_inline)) +static inline void adc_ll_set_dtest_param(uint32_t param) +{ + REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, param); +} + +/** + * Set the SAR ENT param + * + * @param param ENT value + */ +__attribute__((always_inline)) +static inline void adc_ll_set_ent_param(uint32_t param) +{ + REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, param); +} + +/** + * Enable the SAR TOUT bus + * + * @param adc_n ADC index number. + * @param en true for enable + */ +__attribute__((always_inline)) +static inline void adc_ll_enable_tout_bus(adc_unit_t adc_n, bool en) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, en); +} + +/** + * Init regi2c SARADC registers + */ +__attribute__((always_inline)) +static inline void adc_ll_regi2c_init(void) +{ + adc_ll_set_dtest_param(0); + adc_ll_set_ent_param(1); + adc_ll_enable_tout_bus(ADC_UNIT_1, true); +} + +/** + * Deinit regi2c SARADC registers + */ +__attribute__((always_inline)) +static inline void adc_ll_regi2c_adc_deinit(void) +{ + adc_ll_set_dtest_param(0); + adc_ll_set_ent_param(0); + adc_ll_enable_tout_bus(ADC_UNIT_1, false); +} + +/*--------------------------------------------------------------- + Oneshot Read +---------------------------------------------------------------*/ +/** + * Set adc output data format for oneshot mode + * + * @note ESP32H4 Oneshot mode only supports 12bit. + * @param adc_n ADC unit. + * @param bits Output data bits width option. + */ +static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth_t bits) +{ + //ESP32H4 only supports 12bit, leave here for compatibility + HAL_ASSERT(bits == ADC_BITWIDTH_12 || bits == ADC_BITWIDTH_DEFAULT); +} + +/** + * Enable adc channel to start convert. + * + * @note Only one channel can be selected for measurement. + * + * @param adc_n ADC unit. + * @param channel ADC channel number for each ADCn. + */ +static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_n, adc_channel_t channel) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | channel); +} + +/** + * Disable adc channel to start convert. + * + * @note Only one channel can be selected in once measurement. + * + * @param adc_n ADC unit. + */ +static inline void adc_oneshot_ll_disable_channel(adc_unit_t adc_n) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | 0xF); +} + +/** + * Start oneshot conversion by software + * + * @param val Usage: set to 1 to start the ADC conversion. The step signal should at least keep 3 ADC digital controller clock cycle, + * otherwise the step signal may not be captured by the ADC digital controller when its frequency is slow. + * This hardware limitation will be removed in future versions. + */ +static inline void adc_oneshot_ll_start(bool val) +{ + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_start = val; +} + +/** + * Clear the event for each ADCn for Oneshot mode + * + * @param event ADC event + */ +static inline void adc_oneshot_ll_clear_event(uint32_t event_mask) +{ + APB_SARADC.saradc_int_clr.val |= event_mask; +} + +/** + * Check the event for each ADCn for Oneshot mode + * + * @param event ADC event + * + * @return + * -true : The conversion process is finish. + * -false : The conversion process is not finish. + */ +static inline bool adc_oneshot_ll_get_event(uint32_t event_mask) +{ + return (APB_SARADC.saradc_int_raw.val & event_mask); +} + +/** + * Get the converted value for each ADCn for controller. + * + * @param adc_n ADC unit. + * @return + * - Converted value. + */ +static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + uint32_t ret_val = 0; + ret_val = APB_SARADC.saradc_sar1data_status.saradc_apb_saradc1_data & 0xfff; + return ret_val; +} + +/** + * Analyze whether the obtained raw data is correct. + * ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data. + * + * @param adc_n ADC unit. + * @param raw_data ADC raw data input (convert value). + * @return + * - 1: The data is correct to use. + * - 0: The data is invalid. + */ +static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw_data) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + return true; +} + +/** + * ADC module RTC output data invert or not. + * + * @param adc_n ADC unit. + * @param inv_en data invert or not. + */ +static inline void adc_oneshot_ll_output_invert(adc_unit_t adc_n, bool inv_en) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + (void)inv_en; + //For compatibility +} + +/** + * Enable oneshot conversion trigger + * + * @param adc_n ADC unit + */ +static inline void adc_oneshot_ll_enable(adc_unit_t adc_n) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 1; +} + +/** + * Disable oneshot conversion trigger for all the ADC units + */ +static inline void adc_oneshot_ll_disable_all_unit(void) +{ + APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 0; + APB_SARADC.saradc_onetime_sample.saradc_saradc2_onetime_sample = 0; +} + +/** + * Set attenuation + * + * @note Attenuation is for all channels + * + * @param adc_n ADC unit + * @param channel ADC channel + * @param atten ADC attenuation + */ +static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + (void)channel; + // Attenuation is for all channels, unit and channel are for compatibility + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten = atten; +} + +/** + * Get the attenuation of a particular channel on ADCn. + * + * @param adc_n ADC unit. + * @param channel ADCn channel number. + * @return atten The attenuation option. + */ +__attribute__((always_inline)) +static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + (void)channel; + return (adc_atten_t)APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_ana_conv/include/hal/adc_types.h b/components/esp_hal_ana_conv/include/hal/adc_types.h index 2408980cc6..07f9280035 100644 --- a/components/esp_hal_ana_conv/include/hal/adc_types.h +++ b/components/esp_hal_ana_conv/include/hal/adc_types.h @@ -223,7 +223,7 @@ typedef struct { }; } adc_digi_output_data_t; -#elif SOC_IS(ESP32C6) || SOC_IS(ESP32H2) || SOC_IS(ESP32C5) || SOC_IS(ESP32C61) +#elif SOC_IS(ESP32C6) || SOC_IS(ESP32H2) || SOC_IS(ESP32C5) || SOC_IS(ESP32C61) || SOC_IS(ESP32H4) /** * @brief ADC digital controller (DMA mode) output data format. * Used to analyze the acquired ADC (DMA) data. diff --git a/components/esp_hw_support/port/esp32h4/CMakeLists.txt b/components/esp_hw_support/port/esp32h4/CMakeLists.txt index 8c824225ec..822ae371df 100644 --- a/components/esp_hw_support/port/esp32h4/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32h4/CMakeLists.txt @@ -13,7 +13,7 @@ if(CONFIG_SOC_PMU_SUPPORTED) endif() if(NOT BOOTLOADER_BUILD) - # list(APPEND srcs "sar_periph_ctrl.c") // TODO: [ESP32H4] IDF-12368 + list(APPEND srcs "sar_periph_ctrl.c") endif() add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") diff --git a/components/esp_hw_support/port/esp32h4/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32h4/sar_periph_ctrl.c new file mode 100644 index 0000000000..1bd1b871b9 --- /dev/null +++ b/components/esp_hw_support/port/esp32h4/sar_periph_ctrl.c @@ -0,0 +1,147 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * SAR related peripherals are interdependent. This file + * provides a united control to these registers, as multiple + * components require these controls. + * + * Related peripherals are: + * - ADC + * - PWDET + */ + + #include + #include "esp_log.h" + #include "freertos/FreeRTOS.h" + #include "esp_private/sar_periph_ctrl.h" + #include "esp_private/regi2c_ctrl.h" + #include "esp_private/esp_modem_clock.h" + #include "esp_private/critical_section.h" + #include "esp_private/adc_share_hw_ctrl.h" + #include "hal/sar_ctrl_ll.h" + #include "hal/adc_ll.h" + + ESP_LOG_ATTR_TAG(TAG, "sar_periph_ctrl"); + extern portMUX_TYPE rtc_spinlock; + static _lock_t adc_reset_lock; + + + void sar_periph_ctrl_init(void) + { + sar_ctrl_ll_force_power_ctrl_from_pwdet(true); + + //Add other periph power control initialisation here + } + + void sar_periph_ctrl_power_enable(void) + { + esp_os_enter_critical_safe(&rtc_spinlock); + sar_ctrl_ll_force_power_ctrl_from_pwdet(true); + esp_os_exit_critical_safe(&rtc_spinlock); + } + + void sar_periph_ctrl_power_disable(void) + { + esp_os_enter_critical_safe(&rtc_spinlock); + sar_ctrl_ll_force_power_ctrl_from_pwdet(false); + esp_os_exit_critical_safe(&rtc_spinlock); + } + + /** + * This gets incremented when s_sar_power_acquire() is called, + * and decremented when s_sar_power_release() is called. + * PWDET and REG_I2C are powered down when the value reaches zero. + * Should be modified within critical section. + */ + static int s_sar_power_on_cnt; + + static void s_sar_power_acquire(void) + { + modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE); + regi2c_saradc_enable(); + esp_os_enter_critical_safe(&rtc_spinlock); + s_sar_power_on_cnt++; + if (s_sar_power_on_cnt == 1) { + sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON); + } + esp_os_exit_critical_safe(&rtc_spinlock); + } + + static void s_sar_power_release(void) + { + esp_os_enter_critical_safe(&rtc_spinlock); + s_sar_power_on_cnt--; + if (s_sar_power_on_cnt < 0) { + esp_os_exit_critical_safe(&rtc_spinlock); + ESP_LOGE(TAG, "%s called, but s_sar_power_on_cnt == 0", __func__); + abort(); + } else if (s_sar_power_on_cnt == 0) { + sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM); + } + esp_os_exit_critical_safe(&rtc_spinlock); + regi2c_saradc_disable(); + modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE); + } + + + /*------------------------------------------------------------------------------ + * PWDET Power + *----------------------------------------------------------------------------*/ + void sar_periph_ctrl_pwdet_power_acquire(void) + { + s_sar_power_acquire(); + } + + void sar_periph_ctrl_pwdet_power_release(void) + { + s_sar_power_release(); + } + + + /*------------------------------------------------------------------------------ + * ADC Power + *----------------------------------------------------------------------------*/ + void sar_periph_ctrl_adc_oneshot_power_acquire(void) + { + s_sar_power_acquire(); + } + + void sar_periph_ctrl_adc_oneshot_power_release(void) + { + s_sar_power_release(); + } + + void sar_periph_ctrl_adc_continuous_power_acquire(void) + { + s_sar_power_acquire(); + } + + void sar_periph_ctrl_adc_continuous_power_release(void) + { + s_sar_power_release(); + } + + /*------------------------------------------------------------------------------ + * ADC Reset + *----------------------------------------------------------------------------*/ + void sar_periph_ctrl_adc_reset(void) + { + adc_reset_lock_acquire(); + // TODO: [ESP32H4] IDF-12404 + adc_ll_reset_register(); + adc_reset_lock_release(); + } + + void adc_reset_lock_acquire(void) + { + _lock_acquire(&adc_reset_lock); + } + + void adc_reset_lock_release(void) + { + _lock_release(&adc_reset_lock); + } diff --git a/components/hal/esp32h4/include/hal/sar_ctrl_ll.h b/components/hal/esp32h4/include/hal/sar_ctrl_ll.h new file mode 100644 index 0000000000..dfd5786b2d --- /dev/null +++ b/components/hal/esp32h4/include/hal/sar_ctrl_ll.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * SAR related peripherals are interdependent. + * Related peripherals are: + * - ADC + * - PWDET + * + * All of above peripherals require SAR to work correctly. + * As SAR has some registers that will influence above mentioned peripherals. + * This file gives an abstraction for such registers + */ + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "soc/apb_saradc_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24) +#define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23) + + +typedef enum { + SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM + SAR_CTRL_LL_POWER_ON, //SAR power on + SAR_CTRL_LL_POWER_OFF, //SAR power off +} sar_ctrl_ll_power_t; + +/*--------------------------------------------------------------- + SAR power control +---------------------------------------------------------------*/ +/** + * @brief Set SAR power mode when controlled by PWDET + * + * @param[in] mode See `sar_ctrl_ll_power_t` + */ +__attribute__((always_inline)) +static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode) +{ + if (mode == SAR_CTRL_LL_POWER_FSM) { + REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT); + } else if (mode == SAR_CTRL_LL_POWER_ON) { + REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT); + REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT); + } else if (mode == SAR_CTRL_LL_POWER_OFF) { + REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT); + REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT); + } +} + +/** + * @brief Set SAR power ctrl source + * + * @param[in] force set PWDET as SAR power ctrl source when force is true + */ +static inline void sar_ctrl_ll_force_power_ctrl_from_pwdet(bool force) +{ + APB_SARADC.saradc_ctrl.saradc_saradc2_pwdet_drv = force; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index c97a20edaa..7b6f3403ac 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -3,6 +3,10 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### +config SOC_ADC_SUPPORTED + bool + default y + config SOC_DEDICATED_GPIO_SUPPORTED bool default y @@ -231,18 +235,90 @@ config SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION bool default y +config SOC_ADC_DIG_CTRL_SUPPORTED + bool + default y + +config SOC_ADC_DIG_IIR_FILTER_SUPPORTED + bool + default y + +config SOC_ADC_MONITOR_SUPPORTED + bool + default y + +config SOC_ADC_DMA_SUPPORTED + bool + default y + config SOC_ADC_PERIPH_NUM int default 1 config SOC_ADC_MAX_CHANNEL_NUM int - default 7 + default 5 config SOC_ADC_ATTEN_NUM int default 4 +config SOC_ADC_DIGI_CONTROLLER_NUM + int + default 1 + +config SOC_ADC_PATT_LEN_MAX + int + default 8 + +config SOC_ADC_DIGI_MAX_BITWIDTH + int + default 12 + +config SOC_ADC_DIGI_MIN_BITWIDTH + int + default 12 + +config SOC_ADC_DIGI_IIR_FILTER_NUM + int + default 2 + +config SOC_ADC_DIGI_MONITOR_NUM + int + default 2 + +config SOC_ADC_DIGI_RESULT_BYTES + int + default 4 + +config SOC_ADC_DIGI_DATA_BYTES_PER_CONV + int + default 4 + +config SOC_ADC_SAMPLE_FREQ_THRES_HIGH + int + default 83333 + +config SOC_ADC_SAMPLE_FREQ_THRES_LOW + int + default 611 + +config SOC_ADC_RTC_MIN_BITWIDTH + int + default 12 + +config SOC_ADC_RTC_MAX_BITWIDTH + int + default 12 + +config SOC_ADC_TEMPERATURE_SHARE_INTR + bool + default y + +config SOC_ADC_SHARED_POWER + bool + default y + config SOC_APB_BACKUP_DMA bool default n diff --git a/components/soc/esp32h4/include/soc/clk_tree_defs.h b/components/soc/esp32h4/include/soc/clk_tree_defs.h index 2298555289..756d9d72b7 100644 --- a/components/soc/esp32h4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h4/include/soc/clk_tree_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -508,6 +508,22 @@ typedef enum { PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */ } soc_periph_parlio_clk_src_t; +//////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of ADC digital controller + */ +#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief ADC digital controller clock source + */ +typedef enum { + ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ +} soc_periph_adc_digi_clk_src_t; + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h4/include/soc/reg_base.h b/components/soc/esp32h4/include/soc/reg_base.h index 657aaf410f..cd9c4653e9 100644 --- a/components/soc/esp32h4/include/soc/reg_base.h +++ b/components/soc/esp32h4/include/soc/reg_base.h @@ -79,3 +79,4 @@ #define DR_REG_CLINT_M_BASE 0x20000000 // TODO: [ESP32H4] IDF-12303 inherit from verify code, need check #define IEEE802154_REG_BASE 0x600C3000 +#define PWDET_CONF_REG 0x600C0808 diff --git a/components/soc/esp32h4/include/soc/regi2c_saradc.h b/components/soc/esp32h4/include/soc/regi2c_saradc.h index a57384e833..f5049292d3 100644 --- a/components/soc/esp32h4/include/soc/regi2c_saradc.h +++ b/components/soc/esp32h4/include/soc/regi2c_saradc.h @@ -1,42 +1,54 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ #pragma once -#define I2C_SARADC 0x69 -#define I2C_SARADC_HOSTID 0 +#define I2C_SAR_ADC 0x69 +#define I2C_SAR_ADC_HOSTID 0 -#define I2C_SARADC_SAR1_INIT_CODE_LSB 0 -#define I2C_SARADC_SAR1_INIT_CODE_LSB_MSB 7 -#define I2C_SARADC_SAR1_INIT_CODE_LSB_LSB 0 +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0 +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7 +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0 -#define I2C_SARADC_SAR1_INIT_CODE_MSB 1 -#define I2C_SARADC_SAR1_INIT_CODE_MSB_MSB 3 -#define I2C_SARADC_SAR1_INIT_CODE_MSB_LSB 0 +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1 +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3 +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0 -#define I2C_SARADC_SAR2_INIT_CODE_LSB 3 -#define I2C_SARADC_SAR2_INIT_CODE_LSB_MSB 7 -#define I2C_SARADC_SAR2_INIT_CODE_LSB_LSB 0 +#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2 +#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2 +#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0 -#define I2C_SARADC_SAR2_INIT_CODE_MSB 4 -#define I2C_SARADC_SAR2_INIT_CODE_MSB_MSB 3 -#define I2C_SARADC_SAR2_INIT_CODE_MSB_LSB 0 +#define ADC_SAR1_DREF_ADDR 0x2 +#define ADC_SAR1_DREF_ADDR_MSB 0x6 +#define ADC_SAR1_DREF_ADDR_LSB 0x4 -#define I2C_SARADC_DTEST 7 -#define I2C_SARADC_DTEST_MSB 1 -#define I2C_SARADC_DTEST_LSB 0 +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3 +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7 +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0 -#define I2C_SARADC_ENT_SAR 7 -#define I2C_SARADC_ENT_SAR_MSB 3 -#define I2C_SARADC_ENT_SAR_LSB 2 +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4 +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3 +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0 -#define I2C_SARADC_EN_TOUT_SAR1_BUS 7 -#define I2C_SARADC_EN_TOUT_SAR1_BUS_MSB 5 -#define I2C_SARADC_EN_TOUT_SAR1_BUS_LSB 5 +#define I2C_SARADC_DTEST 0x7 +#define I2C_SARADC_DTEST_MSB 0x1 +#define I2C_SARADC_DTEST_LSB 0x0 -#define I2C_SARADC_EN_TOUT_SAR2_BUS 7 -#define I2C_SARADC_EN_TOUT_SAR2_BUS_MSB 6 -#define I2C_SARADC_EN_TOUT_SAR2_BUS_LSB 6 +#define I2C_SARADC_ENT_SAR 0x7 +#define I2C_SARADC_ENT_SAR_MSB 0x3 +#define I2C_SARADC_ENT_SAR_LSB 0x2 + +#define I2C_SARADC_EN_TOUT_SAR1_BUS 0x7 +#define I2C_SARADC_EN_TOUT_SAR1_BUS_MSB 0x5 +#define I2C_SARADC_EN_TOUT_SAR1_BUS_LSB 0x5 + +#define I2C_SARADC_EN_TOUT_SAR2_BUS 0x7 +#define I2C_SARADC_EN_TOUT_SAR2_BUS_MSB 0x6 +#define I2C_SARADC_EN_TOUT_SAR2_BUS_LSB 0x6 + +#define ADC_SAR1_ENCAL_GND_ADDR 0x8 +#define ADC_SAR1_ENCAL_GND_ADDR_MSB 0x1 +#define ADC_SAR1_ENCAL_GND_ADDR_LSB 0x1 diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index f81103e9f3..3fdce4fc07 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -31,7 +31,7 @@ #define _SOC_CAPS_TARGET_IS_ESP32H4 1 // [gen_soc_caps:ignore] /*-------------------------- COMMON CAPS ---------------------------------------*/ -// #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32H4] IDF-12368 IDF-12370 +#define SOC_ADC_SUPPORTED 1 // #define SOC_ANA_CMPR_SUPPORTED 1 // TODO: [ESP32H4] IDF-12395 big change!! #define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_UART_SUPPORTED 1 @@ -110,32 +110,32 @@ /*-------------------------- ADC CAPS -------------------------------*/ /*!< SAR ADC Module*/ -// #define SOC_ADC_DIG_CTRL_SUPPORTED 1 -// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 -// #define SOC_ADC_MONITOR_SUPPORTED 1 -// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit -// #define SOC_ADC_DMA_SUPPORTED 1 +#define SOC_ADC_DIG_CTRL_SUPPORTED 1 +#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 +#define SOC_ADC_MONITOR_SUPPORTED 1 +#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit +#define SOC_ADC_DMA_SUPPORTED 1 #define SOC_ADC_PERIPH_NUM (1U) -#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7) -#define SOC_ADC_MAX_CHANNEL_NUM (7) +#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (5) +#define SOC_ADC_MAX_CHANNEL_NUM (5) #define SOC_ADC_ATTEN_NUM (4) /*!< Digital */ -// #define SOC_ADC_DIGI_CONTROLLER_NUM (1U) -// #define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */ -// #define SOC_ADC_DIGI_MAX_BITWIDTH (12) -// #define SOC_ADC_DIGI_MIN_BITWIDTH (12) -// #define SOC_ADC_DIGI_IIR_FILTER_NUM (2) -// #define SOC_ADC_DIGI_MONITOR_NUM (2) -// #define SOC_ADC_DIGI_RESULT_BYTES (4) -// #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) +#define SOC_ADC_DIGI_CONTROLLER_NUM (1U) +#define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */ +#define SOC_ADC_DIGI_MAX_BITWIDTH (12) +#define SOC_ADC_DIGI_MIN_BITWIDTH (12) +#define SOC_ADC_DIGI_IIR_FILTER_NUM (2) +#define SOC_ADC_DIGI_MONITOR_NUM (2) +#define SOC_ADC_DIGI_RESULT_BYTES (4) +#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */ -// #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 -// #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 +#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 /*!< RTC */ -// #define SOC_ADC_RTC_MIN_BITWIDTH (12) -// #define SOC_ADC_RTC_MAX_BITWIDTH (12) +#define SOC_ADC_RTC_MIN_BITWIDTH (12) +#define SOC_ADC_RTC_MAX_BITWIDTH (12) /*!< Calibration */ // #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ @@ -143,10 +143,10 @@ // #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */ /*!< Interrupt */ -// #define SOC_ADC_TEMPERATURE_SHARE_INTR (1) +#define SOC_ADC_TEMPERATURE_SHARE_INTR (1) /*!< ADC power control is shared by PWDET */ -// #define SOC_ADC_SHARED_POWER 1 +#define SOC_ADC_SHARED_POWER 1 /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ #define SOC_APB_BACKUP_DMA (0) diff --git a/components/soc/esp32h4/ld/esp32h4.peripherals.ld b/components/soc/esp32h4/ld/esp32h4.peripherals.ld index de11ca0064..0ffc86d5bb 100644 --- a/components/soc/esp32h4/ld/esp32h4.peripherals.ld +++ b/components/soc/esp32h4/ld/esp32h4.peripherals.ld @@ -28,7 +28,7 @@ PROVIDE ( RMTMEM = 0x6001E400 ); PROVIDE ( AHB_DMA = 0x6001F000 ); PROVIDE ( PAU = 0x60020000 ); PROVIDE ( SOC_ETM = 0x60021000 ); -PROVIDE ( ADC = 0x60022000 ); +PROVIDE ( APB_SARADC = 0x60022000 ); PROVIDE ( SYSTIMER = 0x60023000 ); PROVIDE ( PSRAM_ACS_MONITOR = 0x60024000 ); /* TODO: IDF-12491 [ESP32H4] inherit from verify code, need check */ PROVIDE ( MEM_MONITOR = 0x60025000 ); diff --git a/docs/docs_not_updated/esp32h4.txt b/docs/docs_not_updated/esp32h4.txt index 7a262689c1..dd70ef8f4c 100644 --- a/docs/docs_not_updated/esp32h4.txt +++ b/docs/docs_not_updated/esp32h4.txt @@ -106,10 +106,8 @@ api-reference/peripherals/index.rst api-reference/peripherals/sdio_slave.rst api-reference/peripherals/temp_sensor.rst api-reference/peripherals/camera_driver.rst -api-reference/peripherals/adc_oneshot.rst api-reference/peripherals/sdspi_share.rst api-reference/peripherals/ana_cmpr.rst -api-reference/peripherals/adc_continuous.rst api-reference/peripherals/hmac.rst api-reference/peripherals/key_manager.rst api-reference/peripherals/sdspi_host.rst diff --git a/examples/peripherals/.build-test-rules.yml b/examples/peripherals/.build-test-rules.yml index 1ec490056e..98cee3b46a 100644 --- a/examples/peripherals/.build-test-rules.yml +++ b/examples/peripherals/.build-test-rules.yml @@ -13,11 +13,19 @@ examples/peripherals/adc/continuous_read: disable: - if: SOC_ADC_DMA_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET in ["esp32h4"] + temporary: true + reason: no runners for esp32h4 ADC test <<: *adc_dependencies examples/peripherals/adc/oneshot_read: disable: - if: SOC_ADC_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET in ["esp32h4"] + temporary: true + reason: no runners for esp32h4 ADC test <<: *adc_dependencies examples/peripherals/analog_comparator: diff --git a/examples/peripherals/adc/continuous_read/README.md b/examples/peripherals/adc/continuous_read/README.md index 8e7861d7de..157441aec7 100644 --- a/examples/peripherals/adc/continuous_read/README.md +++ b/examples/peripherals/adc/continuous_read/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- | # ADC DMA Example diff --git a/examples/peripherals/adc/oneshot_read/README.md b/examples/peripherals/adc/oneshot_read/README.md index 491964fb0b..fa8ec63fd7 100644 --- a/examples/peripherals/adc/oneshot_read/README.md +++ b/examples/peripherals/adc/oneshot_read/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- | # ADC Single Read Example