diff --git a/components/esp_driver_dma/src/gdma.c b/components/esp_driver_dma/src/gdma.c
index c49b378d0e..6da88e44c3 100644
--- a/components/esp_driver_dma/src/gdma.c
+++ b/components/esp_driver_dma/src/gdma.c
@@ -412,22 +412,9 @@ esp_err_t gdma_config_transfer(gdma_channel_handle_t dma_chan, const gdma_transf
     }
     uint32_t max_data_burst_size = config->max_data_burst_size;
     if (max_data_burst_size) {
-#if defined(GDMA_LL_SUPPORTED_BURST_SIZES_ARRAY)
-        uint32_t supported_burst_sizes[] = GDMA_LL_SUPPORTED_BURST_SIZES_ARRAY;
-        bool valid = false;
-        for (size_t i = 0; i < sizeof(supported_burst_sizes) / sizeof(supported_burst_sizes[0]); i++) {
-            if (supported_burst_sizes[i] == max_data_burst_size) {
-                valid = true;
-                break;
-            }
-        }
-        ESP_RETURN_ON_FALSE(valid, ESP_ERR_INVALID_ARG, TAG,
-                            "invalid max_data_burst_size (%" PRIu32 "), supported: %s", max_data_burst_size, GDMA_LL_SUPPORTED_BURST_SIZES_STR);
-#else
         // burst size must be power of 2
         ESP_RETURN_ON_FALSE((max_data_burst_size & (max_data_burst_size - 1)) == 0, ESP_ERR_INVALID_ARG,
-                            TAG, "invalid max_data_burst_size: %" PRIu32, max_data_burst_size);
-#endif
+                            TAG, "invalid max_data_burst_size: %"PRIu32, max_data_burst_size);
 #if GDMA_LL_GET(AHB_PSRAM_CAPABLE) || GDMA_LL_GET(AXI_PSRAM_CAPABLE) || GDMA_LL_GET(LP_AHB_PSRAM_CAPABLE)
         if (config->access_ext_mem) {
             ESP_RETURN_ON_FALSE(max_data_burst_size <= GDMA_LL_MAX_BURST_SIZE_PSRAM, ESP_ERR_INVALID_ARG,
diff --git a/components/esp_hal_dma/esp32c5/include/hal/gdma_ll.h b/components/esp_hal_dma/esp32c5/include/hal/gdma_ll.h
index b2322d248c..3d76d015a0 100644
--- a/components/esp_hal_dma/esp32c5/include/hal/gdma_ll.h
+++ b/components/esp_hal_dma/esp32c5/include/hal/gdma_ll.h
@@ -18,10 +18,6 @@
 #define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1  // AHB GDMA supports adjustable burst size
 #define GDMA_LL_MAX_BURST_SIZE_PSRAM      32 // PSRAM controller doesn't support burst access with size > 32 bytes
 
-// GDMA supported burst sizes
-#define GDMA_LL_SUPPORTED_BURST_SIZES_ARRAY  { 4, 16, 32, 64 }
-#define GDMA_LL_SUPPORTED_BURST_SIZES_STR    "4, 16, 32, 64"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/esp_hal_dma/esp32c61/include/hal/gdma_ll.h b/components/esp_hal_dma/esp32c61/include/hal/gdma_ll.h
index 37549310eb..3d76d015a0 100644
--- a/components/esp_hal_dma/esp32c61/include/hal/gdma_ll.h
+++ b/components/esp_hal_dma/esp32c61/include/hal/gdma_ll.h
@@ -18,10 +18,6 @@
 #define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1  // AHB GDMA supports adjustable burst size
 #define GDMA_LL_MAX_BURST_SIZE_PSRAM      32 // PSRAM controller doesn't support burst access with size > 32 bytes
 
-// SPI DMA supported burst sizes
-#define GDMA_LL_SUPPORTED_BURST_SIZES_ARRAY  { 4, 16, 32, 64 }
-#define GDMA_LL_SUPPORTED_BURST_SIZES_STR    "4, 16, 32, 64"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/esp_hal_dma/esp32h4/include/hal/gdma_ll.h b/components/esp_hal_dma/esp32h4/include/hal/gdma_ll.h
index 94072bc569..eab7b8fe60 100644
--- a/components/esp_hal_dma/esp32h4/include/hal/gdma_ll.h
+++ b/components/esp_hal_dma/esp32h4/include/hal/gdma_ll.h
@@ -18,10 +18,6 @@
 #define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1  // AHB GDMA supports adjustable burst size
 #define GDMA_LL_MAX_BURST_SIZE_PSRAM      64 // PSRAM support INCR16
 
-// SPI DMA supported burst sizes
-#define GDMA_LL_SUPPORTED_BURST_SIZES_ARRAY  { 4, 16, 32, 64 }
-#define GDMA_LL_SUPPORTED_BURST_SIZES_STR    "4, 16, 32, 64"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/esp_hal_dma/esp32p4/include/hal/gdma_ll.h b/components/esp_hal_dma/esp32p4/include/hal/gdma_ll.h
index 21cdf37880..b6c8e7494f 100644
--- a/components/esp_hal_dma/esp32p4/include/hal/gdma_ll.h
+++ b/components/esp_hal_dma/esp32p4/include/hal/gdma_ll.h
@@ -71,10 +71,6 @@
 
 #define GDMA_LL_AXI_M2M_CAPABLE_PAIR_MASK   0x07  // pair 0,1,2 are M2M capable
 
-// SPI DMA supported burst sizes
-#define GDMA_LL_SUPPORTED_BURST_SIZES_ARRAY  { 8, 16, 32, 64, 128 }
-#define GDMA_LL_SUPPORTED_BURST_SIZES_STR    "8, 16, 32, 64, 128"
-
 #define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event)                \
     (uint32_t[2][GDMA_ETM_EVENT_MAX]){                                \
         {                                                             \
diff --git a/components/esp_hal_dma/esp32s3/include/hal/gdma_ll.h b/components/esp_hal_dma/esp32s3/include/hal/gdma_ll.h
index 52ddfe7b05..43af26638e 100644
--- a/components/esp_hal_dma/esp32s3/include/hal/gdma_ll.h
+++ b/components/esp_hal_dma/esp32s3/include/hal/gdma_ll.h
@@ -74,10 +74,6 @@ extern "C" {
 
 #define GDMA_LL_AHB_M2M_CAPABLE_PAIR_MASK   0x1F  // pair 0,1,2,3,4 are M2M capable
 
-// SPI DMA supported burst sizes
-#define GDMA_LL_SUPPORTED_BURST_SIZES_ARRAY  { 16, 32, 64 }
-#define GDMA_LL_SUPPORTED_BURST_SIZES_STR    "16, 32, 64"
-
 ///////////////////////////////////// Common /////////////////////////////////////////
 
 /**
diff --git a/components/esp_hal_dma/esp32s31/include/hal/gdma_ll.h b/components/esp_hal_dma/esp32s31/include/hal/gdma_ll.h
index 6052342b41..089a74167e 100644
--- a/components/esp_hal_dma/esp32s31/include/hal/gdma_ll.h
+++ b/components/esp_hal_dma/esp32s31/include/hal/gdma_ll.h
@@ -63,10 +63,6 @@
 #define GDMA_LL_AXI_M2M_CAPABLE_PAIR_MASK   0x07  // pair 0,1,2 are M2M capable
 #define GDMA_LL_LP_AHB_M2M_CAPABLE_PAIR_MASK 0x03 // pair 0,1 are M2M capable
 
-// SPI DMA supported burst sizes
-#define GDMA_LL_SUPPORTED_BURST_SIZES_ARRAY  { 8, 16, 32, 64, 128 }
-#define GDMA_LL_SUPPORTED_BURST_SIZES_STR    "8, 16, 32, 64, 128"
-
 #define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event)                   \
     (uint32_t[GDMA_LL_INST_NUM][GDMA_ETM_EVENT_MAX]){                    \
         {                                                                \