From b6fcdb1f48d6a5c1700e6e4f67c3f2e3c6d1b8bc Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Mon, 9 Mar 2026 11:18:15 +0800 Subject: [PATCH] feat(esp_hw_support): support GPIO wakeup deepsleep on esp32/esp32s2/esp32s3 and expand gpio_wakeup_mask/gpio_trigger_mode to 64bit --- components/esp_driver_gpio/src/gpio.c | 4 +- .../esp32/include/hal/rtc_io_ll.h | 43 ++++++++++++++++++- .../esp32s2/include/hal/rtc_io_ll.h | 43 ++++++++++++++++++- .../esp32s3/include/hal/rtc_io_ll.h | 43 ++++++++++++++++++- components/esp_hw_support/sleep_gpio.c | 8 ++-- components/esp_hw_support/sleep_modes.c | 27 ++++++------ .../soc/esp32/include/soc/Kconfig.soc_caps.in | 8 ++++ components/soc/esp32/include/soc/soc_caps.h | 4 ++ .../esp32c2/include/soc/Kconfig.soc_caps.in | 4 -- components/soc/esp32c2/include/soc/soc_caps.h | 1 - .../esp32c3/include/soc/Kconfig.soc_caps.in | 4 -- components/soc/esp32c3/include/soc/soc_caps.h | 1 - .../esp32c5/include/soc/Kconfig.soc_caps.in | 4 -- components/soc/esp32c5/include/soc/soc_caps.h | 1 - .../esp32c6/include/soc/Kconfig.soc_caps.in | 4 -- components/soc/esp32c6/include/soc/soc_caps.h | 1 - .../esp32c61/include/soc/Kconfig.soc_caps.in | 4 -- .../soc/esp32c61/include/soc/soc_caps.h | 1 - .../esp32h4/include/soc/Kconfig.soc_caps.in | 4 -- components/soc/esp32h4/include/soc/soc_caps.h | 1 - .../esp32p4/include/soc/Kconfig.soc_caps.in | 4 -- components/soc/esp32p4/include/soc/soc_caps.h | 1 - .../esp32s2/include/soc/Kconfig.soc_caps.in | 8 ++++ components/soc/esp32s2/include/soc/soc_caps.h | 5 +++ .../esp32s3/include/soc/Kconfig.soc_caps.in | 8 ++++ components/soc/esp32s3/include/soc/soc_caps.h | 5 +++ examples/system/deep_sleep/main/gpio_wakeup.c | 2 +- 27 files changed, 183 insertions(+), 60 deletions(-) diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c index 11eca7aee0..51db4a0079 100644 --- a/components/esp_driver_gpio/src/gpio.c +++ b/components/esp_driver_gpio/src/gpio.c @@ -777,7 +777,6 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren esp_err_t gpio_hold_en(gpio_num_t gpio_num) { - GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Only output-capable GPIO support this function", ESP_ERR_NOT_SUPPORTED); int ret = ESP_OK; if (rtc_gpio_is_valid_gpio(gpio_num)) { @@ -785,6 +784,7 @@ esp_err_t gpio_hold_en(gpio_num_t gpio_num) ret = rtc_gpio_hold_en(gpio_num); #endif } else if (GPIO_HOLD_MASK[gpio_num]) { + GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Only output-capable GPIO support this function", ESP_ERR_NOT_SUPPORTED); portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_hold_en(gpio_context.gpio_hal, gpio_num); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); @@ -797,7 +797,6 @@ esp_err_t gpio_hold_en(gpio_num_t gpio_num) esp_err_t gpio_hold_dis(gpio_num_t gpio_num) { - GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Only output-capable GPIO support this function", ESP_ERR_NOT_SUPPORTED); int ret = ESP_OK; if (rtc_gpio_is_valid_gpio(gpio_num)) { @@ -805,6 +804,7 @@ esp_err_t gpio_hold_dis(gpio_num_t gpio_num) ret = rtc_gpio_hold_dis(gpio_num); #endif } else if (GPIO_HOLD_MASK[gpio_num]) { + GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Only output-capable GPIO support this function", ESP_ERR_NOT_SUPPORTED); portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_hold_dis(gpio_context.gpio_hal, gpio_num); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); diff --git a/components/esp_hal_gpio/esp32/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32/include/hal/rtc_io_ll.h index 6c4863ea3a..463e2d8a0b 100644 --- a/components/esp_hal_gpio/esp32/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32/include/hal/rtc_io_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -330,6 +330,17 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num) RTCIO.pin[rtcio_num].int_type = 0; } +/** + * Enable interrupt function and set interrupt type for RTC IO. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param type Interrupt type (disable, edge, or level). Matches gpio_int_type_t encoding. + */ +static inline void rtcio_ll_intr_enable(int rtcio_num, gpio_int_type_t type) +{ + RTCIO.pin[rtcio_num].int_type = type; +} + /** * Enable rtc io output in deep sleep. * @@ -407,6 +418,36 @@ static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level) SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, level, RTC_CNTL_EXT_WAKEUP0_LV_S); } +/** + * @brief Get the status of whether an IO is used for sleep wake-up. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return True if the pin is enabled to wake up from deep-sleep + */ +static inline bool rtcio_ll_wakeup_is_enabled(int rtcio_num) +{ + HAL_ASSERT(rtcio_num >= 0 && rtcio_num < SOC_RTCIO_PIN_COUNT && "io does not support deep sleep wake-up function"); + return RTCIO.pin[rtcio_num].wakeup_enable; +} + +/** + * @brief Get the rtc io interrupt status + * + * @return bit 0~17 corresponding to 0 ~ SOC_RTCIO_PIN_COUNT. + */ +static inline uint32_t rtcio_ll_get_interrupt_status(void) +{ + return RTCIO.status.status; +} + +/** + * @brief Clear all LP IO pads status + */ +static inline void rtcio_ll_clear_interrupt_status(void) +{ + RTCIO.status_w1tc.w1tc = 0x3FFFF; // Clear all 18 RTCIO pins +} + #ifdef __cplusplus } #endif diff --git a/components/esp_hal_gpio/esp32s2/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32s2/include/hal/rtc_io_ll.h index 8ee834fa5b..17ff0a31eb 100644 --- a/components/esp_hal_gpio/esp32s2/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32s2/include/hal/rtc_io_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -335,6 +335,17 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num) RTCIO.pin[rtcio_num].int_type = 0; } +/** + * Enable interrupt function and set interrupt type for RTC IO. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param type Interrupt type (disable, edge, or level). Matches gpio_int_type_t encoding. + */ +static inline void rtcio_ll_intr_enable(int rtcio_num, gpio_int_type_t type) +{ + RTCIO.pin[rtcio_num].int_type = type; +} + /** * Enable rtc io output in deep sleep. * @@ -412,6 +423,36 @@ static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level) SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, level, RTC_CNTL_EXT_WAKEUP0_LV_S); } +/** + * @brief Get the status of whether an IO is used for sleep wake-up. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return True if the pin is enabled to wake up from deep-sleep + */ +static inline bool rtcio_ll_wakeup_is_enabled(int rtcio_num) +{ + HAL_ASSERT(rtcio_num >= 0 && rtcio_num < SOC_RTCIO_PIN_COUNT && "io does not support deep sleep wake-up function"); + return RTCIO.pin[rtcio_num].wakeup_enable; +} + +/** + * @brief Get the rtc io interrupt status + * + * @return bit 0~21 corresponding to 0 ~ SOC_RTCIO_PIN_COUNT. + */ +static inline uint32_t rtcio_ll_get_interrupt_status(void) +{ + return RTCIO.status.status; +} + +/** + * @brief Clear all LP IO pads status + */ +static inline void rtcio_ll_clear_interrupt_status(void) +{ + RTCIO.status_w1tc.w1tc = 0x3FFFFF; // Clear all 22 RTCIO pins +} + #ifdef __cplusplus } #endif diff --git a/components/esp_hal_gpio/esp32s3/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32s3/include/hal/rtc_io_ll.h index 65ea59a43a..c6d6dc0212 100644 --- a/components/esp_hal_gpio/esp32s3/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32s3/include/hal/rtc_io_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -363,6 +363,17 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num) RTCIO.pin[rtcio_num].int_type = 0; } +/** + * Enable interrupt function and set interrupt type for RTC IO. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param type Interrupt type (disable, edge, or level). Matches gpio_int_type_t encoding. + */ +static inline void rtcio_ll_intr_enable(int rtcio_num, gpio_int_type_t type) +{ + RTCIO.pin[rtcio_num].int_type = type; +} + /** * Enable rtc io output in deep sleep. * @@ -440,6 +451,36 @@ static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level) SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, level, RTC_CNTL_EXT_WAKEUP0_LV_S); } +/** + * @brief Get the status of whether an IO is used for sleep wake-up. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return True if the pin is enabled to wake up from deep-sleep + */ +static inline bool rtcio_ll_wakeup_is_enabled(int rtcio_num) +{ + HAL_ASSERT(rtcio_num >= 0 && rtcio_num < SOC_RTCIO_PIN_COUNT && "io does not support deep sleep wake-up function"); + return RTCIO.pin[rtcio_num].wakeup_enable; +} + +/** + * @brief Get the rtc io interrupt status + * + * @return bit 0~21 corresponding to 0 ~ SOC_RTCIO_PIN_COUNT. + */ +static inline uint32_t rtcio_ll_get_interrupt_status(void) +{ + return RTCIO.status.status; +} + +/** + * @brief Clear all LP IO pads status + */ +static inline void rtcio_ll_clear_interrupt_status(void) +{ + RTCIO.status_w1tc.w1tc = 0x3FFFFF; // Clear all 22 RTCIO pins +} + #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/sleep_gpio.c b/components/esp_hw_support/sleep_gpio.c index 739449fc14..b609eae148 100644 --- a/components/esp_hw_support/sleep_gpio.c +++ b/components/esp_hw_support/sleep_gpio.c @@ -250,19 +250,19 @@ static void esp_deep_sleep_wakeup_io_reset(void) #endif #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP - uint32_t dl_io_mask = SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK; + uint64_t dslp_io_mask = SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK; gpio_hal_context_t gpio_hal = { .dev = GPIO_HAL_GET_HW(GPIO_PORT_0) }; - while (dl_io_mask) { - int gpio_num = __builtin_ffs(dl_io_mask) - 1; + while (dslp_io_mask) { + int gpio_num = __builtin_ctzll(dslp_io_mask); bool wakeup_io_enabled = gpio_hal_wakeup_is_enabled_on_hp_periph_powerdown_sleep(&gpio_hal, gpio_num); if (wakeup_io_enabled) { // Disable the wakeup before releasing hold, such that wakeup status can reflect the correct wakeup pin gpio_hal_wakeup_disable_on_hp_periph_powerdown_sleep(&gpio_hal, gpio_num); gpio_hal_hold_dis(&gpio_hal, gpio_num); } - dl_io_mask &= ~BIT(gpio_num); + dslp_io_mask &= dslp_io_mask - 1; } #endif } diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index a332ae92dc..4cac60e92c 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -293,8 +293,8 @@ typedef struct { uint32_t ext0_rtc_gpio_num : 5; #endif #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP - uint32_t gpio_wakeup_mask : SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT; - uint32_t gpio_trigger_mode : SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT; + uint64_t gpio_wakeup_mask; + uint64_t gpio_trigger_mode; #endif uint32_t sleep_time_adjustment; uint32_t ccount_ticks_record; @@ -2252,11 +2252,9 @@ uint64_t esp_sleep_get_gpio_wakeup_status(void) static void esp_sleep_gpio_wakeup_prepare_on_hp_periph_powerdown(void) { - uint32_t valid_wake_io_mask = SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK; - for (gpio_num_t gpio_idx = __builtin_ctz(valid_wake_io_mask); valid_wake_io_mask >> gpio_idx; gpio_idx++) { - if ((s_config.gpio_wakeup_mask & BIT64(gpio_idx)) == 0) { - continue; - } + uint64_t valid_wake_io_mask = s_config.gpio_wakeup_mask & SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK; + while (valid_wake_io_mask) { + int gpio_idx = __builtin_ctzll(valid_wake_io_mask); #if SOC_LP_IO_CLOCK_IS_INDEPENDENT // To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); @@ -2272,6 +2270,7 @@ static void esp_sleep_gpio_wakeup_prepare_on_hp_periph_powerdown(void) } #endif ESP_ERROR_CHECK(gpio_hold_en(gpio_idx)); + valid_wake_io_mask &= valid_wake_io_mask - 1; } // Clear state from previous wakeup rtc_hal_gpio_clear_wakeup_status(); @@ -2298,19 +2297,17 @@ esp_err_t esp_sleep_enable_gpio_wakeup_on_hp_periph_powerdown(uint64_t gpio_pin_ } } } - - for (gpio_num_t gpio_idx = __builtin_ctzll(gpio_pin_mask); gpio_pin_mask >> gpio_idx; gpio_idx++) { - if ((gpio_pin_mask & BIT64(gpio_idx)) == 0) { - continue; - } + while (gpio_pin_mask) { + int gpio_idx = __builtin_ctzll(gpio_pin_mask); err = gpio_wakeup_enable_on_hp_periph_powerdown_sleep(gpio_idx, intr_type); if (err != ESP_OK) return err; - s_config.gpio_wakeup_mask |= BIT(gpio_idx); + s_config.gpio_wakeup_mask |= BIT64(gpio_idx); if (mode == ESP_GPIO_WAKEUP_GPIO_HIGH) { - s_config.gpio_trigger_mode |= BIT(gpio_idx); + s_config.gpio_trigger_mode |= BIT64(gpio_idx); } else { - s_config.gpio_trigger_mode &= ~BIT(gpio_idx); + s_config.gpio_trigger_mode &= ~BIT64(gpio_idx); } + gpio_pin_mask &= gpio_pin_mask - 1; } s_config.wakeup_triggers |= RTC_GPIO_TRIG_EN; return err; diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index b11aaada74..328a422c74 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -339,6 +339,14 @@ config SOC_GPIO_PIN_COUNT int default 40 +config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP + bool + default y + +config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK + int + default 0 + config SOC_GPIO_VALID_GPIO_MASK hex default 0xFFFFFFFFFF diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 44964fa3b2..43d8dc62d9 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -182,6 +182,10 @@ #define SOC_GPIO_PORT (1U) #define SOC_GPIO_PIN_COUNT 40 +#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1) +#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP +#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT2 | BIT4 | BIT12 | BIT13 | BIT14 | BIT15 | BIT25 | BIT26 | BIT27 | BIT32 | BIT33 | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39) + // 0~39 valid except 24, 28~31 #define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT24 | BIT28 | BIT29 | BIT30 | BIT31)) // GPIO >= 34 are input only diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index bd7d6682cb..ac30173326 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -311,10 +311,6 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK int default 0 -config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT - int - default 6 - config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x00000000001FFFC0 diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index 47e993f56a..19b391fc0d 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -141,7 +141,6 @@ #define SOC_GPIO_OUT_RANGE_MAX 20 #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5) -#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (6) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_20) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000001FFFC0ULL diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index c8e39fbc07..5dcfa56f53 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -407,10 +407,6 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK int default 0 -config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT - int - default 6 - config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x00000000003FFFC0 diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index 190b0ffc96..a3cdaaa7af 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -180,7 +180,6 @@ #define SOC_GPIO_OUT_RANGE_MAX 21 #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5) -#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (6) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_21) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFFC0ULL diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 5e93bf615c..8092098124 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -587,10 +587,6 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK int default 0 -config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT - int - default 7 - config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x0000000001FFFF80 diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 0d7799e786..6c0af0ba90 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -235,7 +235,6 @@ #define SOC_GPIO_OUT_RANGE_MAX 28 #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6) -#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (7) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_28) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF80ULL diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 2d88f28cbb..ed7c16d00f 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -503,10 +503,6 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK int default 0 -config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT - int - default 8 - config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x000000007FFFFF00 diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index e16a298696..8579812a63 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -208,7 +208,6 @@ #define SOC_GPIO_OUT_RANGE_MAX 30 #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7) -#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (8) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 12ddc4a8a1..11a7b7e438 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -459,10 +459,6 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK int default 0 -config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT - int - default 7 - config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x3FFFFF80 diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 46f5e8f91b..413c931631 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -191,7 +191,6 @@ #define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1) #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6) -#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (7) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_29) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x3FFFFF80ULL diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index b2bf42562f..ff0444453f 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -411,10 +411,6 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK int default 0 -config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT - int - default 6 - config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index 1e3f7160eb..48dd617c63 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -226,7 +226,6 @@ #define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1) #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5) -#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (6) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_39) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK (SOC_GPIO_VALID_GPIO_MASK & ~((1ULL<<6) - 1)) diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index c30ff9a349..0fa6252f8a 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -711,10 +711,6 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK int default 0 -config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT - int - default 16 - config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x007FFFFFFFFF0000 diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 8a150fe99c..3b88d26b80 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -269,7 +269,6 @@ #define SOC_GPIO_OUT_RANGE_MAX 54 #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | 0xFFFF) -#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (16) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index 025c969f9b..16ad13e867 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -431,6 +431,14 @@ config SOC_RTC_CNTL_NEEDS_ATOMIC_ACCESS bool default y +config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP + bool + default y + +config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK + int + default 0 + config SOC_DEDIC_GPIO_HAS_INTERRUPT bool default y diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index c6cf4fade4..738db4fc18 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -203,6 +203,11 @@ * (e.g., spinlocks) when accessed from multiple cores or threads. */ #define SOC_RTC_CNTL_NEEDS_ATOMIC_ACCESS 1 +// GPIO0~21 on ESP32-S2 can support chip deep sleep wakeup +#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1) +#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP +#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12 | BIT13 | BIT14 | BIT15 | BIT16 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21) + /*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/ #define SOC_DEDIC_GPIO_HAS_INTERRUPT (1) /*!< Dedicated GPIO has its own interrupt source */ diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index 7063dbe2d4..0383773a61 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -479,6 +479,14 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 +config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP + bool + default y + +config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK + int + default 0 + config SOC_I2C_NUM int default 2 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index c3ac93303e..3d3ee95e64 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -200,6 +200,11 @@ #define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) +// GPIO0~21 on ESP32-S3 can support chip deep sleep wakeup +#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1) +#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP +#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12 | BIT13 | BIT14 | BIT15 | BIT16 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21) + /*-------------------------- I2C CAPS ----------------------------------------*/ #define SOC_I2C_NUM (2U) #define SOC_HP_I2C_NUM (2U) diff --git a/examples/system/deep_sleep/main/gpio_wakeup.c b/examples/system/deep_sleep/main/gpio_wakeup.c index fd9f889b00..5b0b4c5bba 100644 --- a/examples/system/deep_sleep/main/gpio_wakeup.c +++ b/examples/system/deep_sleep/main/gpio_wakeup.c @@ -20,7 +20,7 @@ void example_deep_sleep_register_gpio_wakeup(void) { const gpio_config_t config = { - .pin_bit_mask = BIT(DEFAULT_WAKEUP_PIN), + .pin_bit_mask = BIT64(DEFAULT_WAKEUP_PIN), .mode = GPIO_MODE_INPUT, };