From 1313aebeafb9c12202735d9a4cce2768dea305ef Mon Sep 17 00:00:00 2001 From: zlq Date: Tue, 10 Sep 2024 10:59:58 +0800 Subject: [PATCH 1/3] feat(esp32c6): auto adjust LDO voltage using pvt function --- components/esp_hw_support/Kconfig | 1 + components/esp_hw_support/linker.lf | 2 +- .../port/esp32c6/CMakeLists.txt | 4 + .../port/esp32c6/include/soc/rtc.h | 48 + .../esp_hw_support/port/esp32c6/pmu_init.c | 23 +- .../esp_hw_support/port/esp32c6/pmu_param.c | 2 +- .../esp_hw_support/port/esp32c6/pmu_pvt.c | 170 + .../esp_hw_support/port/esp32c6/pmu_sleep.c | 4 + .../port/esp32c6/private_include/pmu_param.h | 2 +- .../esp_hw_support/port/esp32c6/rtc_clk.c | 16 +- .../port/esp32c6/rtc_clk_init.c | 2 + components/esp_hw_support/sleep_modes.c | 4 +- .../esp_hw_support/sleep_system_peripheral.c | 2 +- components/esp_system/port/soc/esp32c6/clk.c | 2 + .../esp32c6/include/soc/Kconfig.soc_caps.in | 4 + components/soc/esp32c6/include/soc/pvt_reg.h | 2834 +++++++++++++++++ components/soc/esp32c6/include/soc/soc_caps.h | 1 + .../include/soc/system_periph_retention.h | 10 + .../soc/esp32c6/system_retention_periph.c | 8 + .../esp32p4/include/soc/Kconfig.soc_caps.in | 8 + components/soc/esp32p4/include/soc/soc_caps.h | 2 + 21 files changed, 3141 insertions(+), 8 deletions(-) create mode 100644 components/esp_hw_support/port/esp32c6/pmu_pvt.c create mode 100644 components/soc/esp32c6/include/soc/pvt_reg.h diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig index 31b58e95ac..af5c83e9c9 100644 --- a/components/esp_hw_support/Kconfig +++ b/components/esp_hw_support/Kconfig @@ -383,6 +383,7 @@ menu "Hardware Settings" config ESP_ENABLE_PVT bool "Auto adjust hp & lp voltage using pvt function (MUST ENABLE FOR MP)" depends on SOC_PMU_PVT_SUPPORTED + default n if IDF_TARGET_ESP32C6 default y help If enabled, hp & lp voltage can be auto adjust by PVT characteristic. diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index cef2beefcc..bd3b2754fc 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -25,7 +25,7 @@ entries: if SPIRAM_FLASH_LOAD_TO_PSRAM = y: pmu_init (noflash) pmu_param (noflash) - if SOC_PMU_PVT_SUPPORTED = y: + if SOC_PMU_PVT_SUPPORTED = y && ESP_ENABLE_PVT = y: pmu_pvt (noflash) if SOC_USB_SERIAL_JTAG_SUPPORTED = y: sleep_console (noflash) diff --git a/components/esp_hw_support/port/esp32c6/CMakeLists.txt b/components/esp_hw_support/port/esp32c6/CMakeLists.txt index d0057e2ec1..56d3265918 100644 --- a/components/esp_hw_support/port/esp32c6/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32c6/CMakeLists.txt @@ -14,6 +14,10 @@ if(NOT BOOTLOADER_BUILD) endif() +if(NOT BOOTLOADER_BUILD AND CONFIG_ESP_ENABLE_PVT) + list(APPEND srcs "pmu_pvt.c") +endif() + add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") diff --git a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h index 404d0d68a9..69317fa748 100644 --- a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h @@ -96,6 +96,54 @@ set sleep_init default param #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 +#if CONFIG_ESP_ENABLE_PVT +/* +set pvt default param +*/ +#define PVT_CHANNEL0_SEL 34 +#define PVT_CHANNEL1_SEL 38 +#define PVT_CHANNEL0_CFG 0x1033e +#define PVT_CHANNEL1_CFG 0x1033e +#define PVT_CHANNEL2_CFG 0x10000 +#define PVT_CMD0 0x24 +#define PVT_CMD1 0x5 +#define PVT_CMD2 0x427 +#define PVT_TARGET 0xffff +#define PVT_CLK_DIV 1 +#define PVT_EDG_MODE 1 +#define PVT_DELAY_NUM_HIGH 108 +#define PVT_DELAY_NUM_LOW 98 +#define PVT_PUMP_CHANNEL_CODE 1 +#define PVT_PUMP_BITMAP 21 +#define PVT_PUMP_DRV 0 +#define PVT_DELAY_NUM_PUMP 95 + +/** + * @brief Initialize PVT related parameters + */ +void pvt_auto_dbias_init(void); + +/** + * @brief Enable or disable PVT functions + * + * @param enable true to enable, false to disable + */ +void pvt_func_enable(bool enable); + +/** + * @brief Initialize charge pump related parameters + */ +void charge_pump_init(void); + +/** + * @brief Enable or disable charge pump functions + * + * @param enable true to enable, false to disable + */ +void charge_pump_enable(bool enable); + +#endif //#if CONFIG_ESP_ENABLE_PVT + /* The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value storing in efuse (based on ATE 5k ECO3 chips) diff --git a/components/esp_hw_support/port/esp32c6/pmu_init.c b/components/esp_hw_support/port/esp32c6/pmu_init.c index e64111e19b..f34678b5f2 100644 --- a/components/esp_hw_support/port/esp32c6/pmu_init.c +++ b/components/esp_hw_support/port/esp32c6/pmu_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,6 +16,11 @@ #include "esp_private/esp_pmu.h" #include "soc/regi2c_dig_reg.h" #include "regi2c_ctrl.h" +#include "esp_rom_sys.h" +#include "soc/rtc.h" +#include "hal/efuse_ll.h" +#include "hal/efuse_hal.h" +#include "esp_hw_log.h" static __attribute__((unused)) const char *TAG = "pmu_init"; @@ -220,4 +225,20 @@ void pmu_init(void) pmu_lp_system_init_default(PMU_instance()); pmu_power_domain_force_default(PMU_instance()); + +#if CONFIG_ESP_ENABLE_PVT + /*setup pvt function*/ + uint32_t blk_version = efuse_hal_blk_version(); + if (blk_version >= 3) { + pvt_auto_dbias_init(); + charge_pump_init(); + + pvt_func_enable(true); + charge_pump_enable(true); + esp_rom_delay_us(1000); + } + else { + ESP_HW_LOGW(TAG, "blk_version is less than 3, pvt function not supported in efuse."); + } +#endif } diff --git a/components/esp_hw_support/port/esp32c6/pmu_param.c b/components/esp_hw_support/port/esp32c6/pmu_param.c index 90c1fddf9a..374380bc33 100644 --- a/components/esp_hw_support/port/esp32c6/pmu_param.c +++ b/components/esp_hw_support/port/esp32c6/pmu_param.c @@ -350,7 +350,7 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm #define PMU_LP_SLEEP_POWER_CONFIG_DEFAULT() { \ .dig_power = { \ - .mem_dslp = 1, \ + .mem_dslp = 0, \ .peri_pd_en = 0, \ }, \ .clk_power = { \ diff --git a/components/esp_hw_support/port/esp32c6/pmu_pvt.c b/components/esp_hw_support/port/esp32c6/pmu_pvt.c new file mode 100644 index 0000000000..c8a28616f7 --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/pmu_pvt.c @@ -0,0 +1,170 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "sdkconfig.h" +#include "esp_attr.h" +#include "soc/soc.h" +#include "soc/pmu_struct.h" +#include "soc/pvt_reg.h" +#include "soc/pmu_reg.h" +#include "soc/pcr_reg.h" +#include "hal/pmu_hal.h" +#include "pmu_param.h" +#include "esp_rom_sys.h" +#include "esp_private/esp_pmu.h" +#include "soc/regi2c_dig_reg.h" +#include "regi2c_ctrl.h" +#include "soc/rtc.h" +#include "hal/efuse_ll.h" +#include "hal/efuse_hal.h" +#include "esp_hw_log.h" + +static __attribute__((unused)) const char *TAG = "pmu_pvt"; + +#if CONFIG_ESP_ENABLE_PVT + +static uint8_t get_lp_hp_gap(void) +{ + int8_t pvt_offset = 0; + uint32_t blk_version = efuse_hal_blk_version(); + if (blk_version >= 3) { + uint8_t offset_read = efuse_ll_get_dbias_vol_gap(); + bool offset_flag = offset_read >> 4; + uint8_t offset_value = offset_read & 0xf; + int8_t pvt_offset = 0; + if (offset_flag) { + pvt_offset = -1 * offset_value; + } else { + pvt_offset = offset_value; + } + pvt_offset = pvt_offset - 2; + assert((pvt_offset >= -15) && (pvt_offset <= 13)); + if (pvt_offset < 0 ) { + pvt_offset = 16 - pvt_offset; + } + } + return pvt_offset; +} + +static void set_pvt_hp_lp_gap(uint8_t value) +{ + bool flag = value >> 4; + uint8_t abs_value = value & 0xf; + + SET_PERI_REG_BITS(PVT_DBIAS_CMD0_REG, PVT_DBIAS_CMD0_OFFSET_FLAG, flag, PVT_DBIAS_CMD0_OFFSET_FLAG_S); + SET_PERI_REG_BITS(PVT_DBIAS_CMD0_REG, PVT_DBIAS_CMD0_OFFSET_VALUE, abs_value, PVT_DBIAS_CMD0_OFFSET_VALUE_S); + SET_PERI_REG_BITS(PVT_DBIAS_CMD1_REG, PVT_DBIAS_CMD1_OFFSET_FLAG, flag, PVT_DBIAS_CMD1_OFFSET_FLAG_S); + SET_PERI_REG_BITS(PVT_DBIAS_CMD1_REG, PVT_DBIAS_CMD1_OFFSET_VALUE, abs_value, PVT_DBIAS_CMD1_OFFSET_VALUE_S); + SET_PERI_REG_BITS(PVT_DBIAS_CMD2_REG, PVT_DBIAS_CMD2_OFFSET_FLAG, flag, PVT_DBIAS_CMD2_OFFSET_FLAG_S); + SET_PERI_REG_BITS(PVT_DBIAS_CMD2_REG, PVT_DBIAS_CMD2_OFFSET_VALUE, abs_value, PVT_DBIAS_CMD2_OFFSET_VALUE_S); +} + +FORCE_INLINE_ATTR uint32_t get_pvt_hp_dbias(void) +{ + return REG_GET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_DBIAS_VOL); +} + +FORCE_INLINE_ATTR uint32_t get_pvt_lp_dbias(void) +{ + return REG_GET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_LP_DBIAS_VOL); +} + +void pvt_auto_dbias_init(void) +{ + uint32_t blk_version = efuse_hal_blk_version(); + if (blk_version >= 3) { + SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN); + SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN); + /*config for dbias func*/ + CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); + esp_rom_delay_us(1); + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL0_SEL, PVT_CHANNEL0_SEL, PVT_DBIAS_CHANNEL0_SEL_S); + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL1_SEL, PVT_CHANNEL1_SEL, PVT_DBIAS_CHANNEL1_SEL_S); // Select monitor cell ,which used to monitor PVT situation + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL0_SEL_REG, PVT_DBIAS_CHANNEL0_CFG, PVT_CHANNEL0_CFG, PVT_DBIAS_CHANNEL0_CFG_S); + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL1_SEL_REG, PVT_DBIAS_CHANNEL1_CFG, PVT_CHANNEL1_CFG, PVT_DBIAS_CHANNEL1_CFG_S); + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL2_SEL_REG, PVT_DBIAS_CHANNEL2_CFG, PVT_CHANNEL2_CFG, PVT_DBIAS_CHANNEL2_CFG_S); // Configure filter threshold for avoiding auto-dbias overly sensitive regulation + SET_PERI_REG_BITS(PVT_DBIAS_CMD0_REG, PVT_DBIAS_CMD0_PVT, PVT_CMD0, PVT_DBIAS_CMD0_PVT_S); + SET_PERI_REG_BITS(PVT_DBIAS_CMD1_REG, PVT_DBIAS_CMD1_PVT, PVT_CMD1, PVT_DBIAS_CMD1_PVT_S); + SET_PERI_REG_BITS(PVT_DBIAS_CMD2_REG, PVT_DBIAS_CMD2_PVT, PVT_CMD2, PVT_DBIAS_CMD2_PVT_S); // Configure auto-dbias adjust property, such as adjusting step + SET_PERI_REG_BITS(PVT_DBIAS_TIMER_REG, PVT_TIMER_TARGET, PVT_TARGET, PVT_TIMER_TARGET_S); // Configure auto-dbias voltage regulation cycle + + SET_PERI_REG_BITS(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM, PVT_CLK_DIV, PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S); //pvt function clock divider number + + /*config for pvt cell: unit0; site2; vt2*/ + SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_SEL); //pvt function clock source select + SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG, PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0, PVT_EDG_MODE, PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S); // Select edge_mode + SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0, PVT_DELAY_NUM_HIGH, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S); // The threshold for determining whether the voltage is too high + SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1, PVT_DELAY_NUM_LOW, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S); // The threshold for determining whether the voltage is too low + SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2, PVT_DELAY_NUM_PUMP, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S); // The threshold for chargepump + + /*config lp offset for pvt func*/ + uint8_t lp_hp_gap = get_lp_hp_gap(); + set_pvt_hp_lp_gap(lp_hp_gap); + } else { + ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt auto dbias init not supported in efuse."); + } +} + +void IRAM_ATTR pvt_func_enable(bool enable) +{ + uint32_t blk_version = efuse_hal_blk_version(); + if (blk_version >= 3) { + if (enable) { + SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // start calibration @HP_CALI_DBIAS_DEFAUL + SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN); + SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN); + SET_PERI_REG_MASK(PVT_CLK_CFG_REG, PVT_MONITOR_CLK_PVT_EN); + SET_PERI_REG_MASK(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG, PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0); // enable pvt clk + esp_rom_delay_us(10); + CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pvt + CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // must clear @HP_CALI_DBIAS_DEFAULT + SET_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); // enable auto dbias + } else { + uint32_t pvt_hp_dbias = get_pvt_hp_dbias(); + uint32_t pvt_lp_dbias = get_pvt_lp_dbias(); // update pvt_cali_dbias + SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, pvt_hp_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S); + SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, pvt_lp_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S); + CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); //disable auto dbias + SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pmu + CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN); + CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN); + } + } else { + ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt enable not supported in efuse."); + } +} + +void charge_pump_init(void) +{ + uint32_t blk_version = efuse_hal_blk_version(); + if (blk_version >= 3) { + /*config for charge pump*/ + SET_PERI_REG_BITS(PVT_PMUP_CHANNEL_CFG_REG, PVT_PUMP_CHANNEL_CODE0, PVT_PUMP_CHANNEL_CODE, PVT_PUMP_CHANNEL_CODE0_S); //Set channel code + WRITE_PERI_REG(PVT_PMUP_BITMAP_LOW0_REG, (1 << PVT_PUMP_BITMAP)); // Select monitor cell for charge pump + SET_PERI_REG_BITS(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_DRV0, PVT_PUMP_DRV, PVT_PUMP_DRV0_S); //Configure the charging intensity + } else { + ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt charge_pump init not supported in efuse."); + } +} + +void IRAM_ATTR charge_pump_enable(bool enable) +{ + uint32_t blk_version = efuse_hal_blk_version(); + if (blk_version >= 3) { + if (enable) { + SET_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); // enable charge pump + } else { + CLEAR_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); //disable charge pump + } + } else { + ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt charge_pump enable not supported in efuse."); + } +} + +#endif diff --git a/components/esp_hw_support/port/esp32c6/pmu_sleep.c b/components/esp_hw_support/port/esp32c6/pmu_sleep.c index 4c850a36f9..89e3e901fe 100644 --- a/components/esp_hw_support/port/esp32c6/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32c6/pmu_sleep.c @@ -293,6 +293,10 @@ static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_con pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd); pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias); pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b); +#if CONFIG_ESP_ENABLE_PVT + uint32_t pvt_hp_dbias = GET_PERI_REG_BITS2(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_DBIAS_VOL_V, PMU_HP_DBIAS_VOL_S); + pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(MODEM), pvt_hp_dbias); +#endif pmu_ll_lp_set_dbg_atten (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbg_atten); pmu_ll_lp_set_current_power_off (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur); diff --git a/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h index 775d5e00b8..25a1df3d39 100644 --- a/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h @@ -305,7 +305,7 @@ typedef struct { .lp_sys[PMU_MODE_LP_SLEEP] = { \ .dig_power = { \ .peri_pd_en = ((pd_flags) & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \ - .mem_dslp = 1 \ + .mem_dslp = 0 \ }, \ .clk_power = { \ .xpd_xtal32k = ((pd_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1, \ diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c index 0565b12763..edbf97e451 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -193,6 +193,10 @@ static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div) clk_ll_cpu_set_ls_divider(div); clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL); esp_rom_set_cpu_ticks_per_us(cpu_freq); +#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD) + charge_pump_enable(false); + pvt_func_enable(false); +#endif } static void rtc_clk_cpu_freq_to_8m(void) @@ -201,6 +205,10 @@ static void rtc_clk_cpu_freq_to_8m(void) clk_ll_cpu_set_ls_divider(1); clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST); esp_rom_set_cpu_ticks_per_us(20); +#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD) + charge_pump_enable(false); + pvt_func_enable(false); +#endif } /** @@ -210,6 +218,12 @@ static void rtc_clk_cpu_freq_to_8m(void) */ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) { +#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD) + pvt_auto_dbias_init(); + charge_pump_init(); + pvt_func_enable(true); + charge_pump_enable(true); +#endif clk_ll_cpu_set_hs_divider(CLK_LL_PLL_480M_FREQ_MHZ / cpu_freq_mhz); clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL); esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz); diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk_init.c b/components/esp_hw_support/port/esp32c6/rtc_clk_init.c index 70c275a1f9..3b509d7ddf 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c6/rtc_clk_init.c @@ -80,6 +80,8 @@ void rtc_clk_init(rtc_clk_config_t cfg) uint32_t hp_cali_dbias = get_act_hp_dbias(); uint32_t lp_cali_dbias = get_act_lp_dbias(); + SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // Hand over control of dbias to pmu + SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S); SET_PERI_REG_BITS(PMU_HP_MODEM_HP_REGULATOR0_REG, PMU_HP_MODEM_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_MODEM_HP_REGULATOR_DBIAS_S); SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, lp_cali_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S); diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 3e8ff0c0fb..ecbfea4b0a 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -684,7 +684,7 @@ FORCE_INLINE_ATTR void misc_modules_sleep_prepare(bool deep_sleep, uint32_t pd_f regi2c_analog_cali_reg_read(); #endif } -#if CONFIG_ESP_ENABLE_PVT +#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_EN_WITH_SLEEP pvt_func_enable(false); #endif @@ -699,7 +699,7 @@ FORCE_INLINE_ATTR void misc_modules_sleep_prepare(bool deep_sleep, uint32_t pd_f */ FORCE_INLINE_ATTR void misc_modules_wake_prepare(uint32_t pd_flags) { -#if CONFIG_ESP_ENABLE_PVT +#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_EN_WITH_SLEEP pvt_func_enable(true); #endif diff --git a/components/esp_hw_support/sleep_system_peripheral.c b/components/esp_hw_support/sleep_system_peripheral.c index 7b43137731..6830492444 100644 --- a/components/esp_hw_support/sleep_system_peripheral.c +++ b/components/esp_hw_support/sleep_system_peripheral.c @@ -162,7 +162,7 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_retention_init(void *a err = sleep_pau_retention_init(); if(err) goto error; #endif -#if CONFIG_ESP_ENABLE_PVT +#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_RETENTION_BY_REGDMA err = sleep_pvt_retention_init(); if(err) goto error; #endif diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c index c778b2cdb6..9ada437410 100644 --- a/components/esp_system/port/soc/esp32c6/clk.c +++ b/components/esp_system/port/soc/esp32c6/clk.c @@ -313,8 +313,10 @@ __attribute__((weak)) void esp_perip_clk_init(void) REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN); REG_CLR_BIT(PCR_RETENTION_CONF_REG, PCR_RETENTION_CLK_EN); REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN); +#if !CONFIG_ESP_ENABLE_PVT REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN); REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN); +#endif WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0); #if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index f506a5afc5..1c976d257e 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -191,6 +191,10 @@ config SOC_PMU_SUPPORTED bool default y +config SOC_PMU_PVT_SUPPORTED + bool + default y + config SOC_PAU_SUPPORTED bool default y diff --git a/components/soc/esp32c6/include/soc/pvt_reg.h b/components/soc/esp32c6/include/soc/pvt_reg.h new file mode 100644 index 0000000000..cbc2b92a76 --- /dev/null +++ b/components/soc/esp32c6/include/soc/pvt_reg.h @@ -0,0 +1,2834 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PVT_PMUP_BITMAP_HIGH0_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH0_REG (DR_REG_PVT_MONITOR_BASE + 0x0) +/** PVT_PUMP_BITMAP_HIGH0 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel0 + */ +#define PVT_PUMP_BITMAP_HIGH0 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH0_M (PVT_PUMP_BITMAP_HIGH0_V << PVT_PUMP_BITMAP_HIGH0_S) +#define PVT_PUMP_BITMAP_HIGH0_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH0_S 0 + +/** PVT_PMUP_BITMAP_HIGH1_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH1_REG (DR_REG_PVT_MONITOR_BASE + 0x4) +/** PVT_PUMP_BITMAP_HIGH1 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel1 + */ +#define PVT_PUMP_BITMAP_HIGH1 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH1_M (PVT_PUMP_BITMAP_HIGH1_V << PVT_PUMP_BITMAP_HIGH1_S) +#define PVT_PUMP_BITMAP_HIGH1_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH1_S 0 + +/** PVT_PMUP_BITMAP_HIGH2_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH2_REG (DR_REG_PVT_MONITOR_BASE + 0x8) +/** PVT_PUMP_BITMAP_HIGH2 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel2 + */ +#define PVT_PUMP_BITMAP_HIGH2 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH2_M (PVT_PUMP_BITMAP_HIGH2_V << PVT_PUMP_BITMAP_HIGH2_S) +#define PVT_PUMP_BITMAP_HIGH2_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH2_S 0 + +/** PVT_PMUP_BITMAP_HIGH3_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH3_REG (DR_REG_PVT_MONITOR_BASE + 0xc) +/** PVT_PUMP_BITMAP_HIGH3 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel3 + */ +#define PVT_PUMP_BITMAP_HIGH3 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH3_M (PVT_PUMP_BITMAP_HIGH3_V << PVT_PUMP_BITMAP_HIGH3_S) +#define PVT_PUMP_BITMAP_HIGH3_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH3_S 0 + +/** PVT_PMUP_BITMAP_HIGH4_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH4_REG (DR_REG_PVT_MONITOR_BASE + 0x10) +/** PVT_PUMP_BITMAP_HIGH4 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel4 + */ +#define PVT_PUMP_BITMAP_HIGH4 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH4_M (PVT_PUMP_BITMAP_HIGH4_V << PVT_PUMP_BITMAP_HIGH4_S) +#define PVT_PUMP_BITMAP_HIGH4_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH4_S 0 + +/** PVT_PMUP_BITMAP_LOW0_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW0_REG (DR_REG_PVT_MONITOR_BASE + 0x14) +/** PVT_PUMP_BITMAP_LOW0 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel0 + */ +#define PVT_PUMP_BITMAP_LOW0 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW0_M (PVT_PUMP_BITMAP_LOW0_V << PVT_PUMP_BITMAP_LOW0_S) +#define PVT_PUMP_BITMAP_LOW0_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW0_S 0 + +/** PVT_PMUP_BITMAP_LOW1_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW1_REG (DR_REG_PVT_MONITOR_BASE + 0x18) +/** PVT_PUMP_BITMAP_LOW1 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel1 + */ +#define PVT_PUMP_BITMAP_LOW1 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW1_M (PVT_PUMP_BITMAP_LOW1_V << PVT_PUMP_BITMAP_LOW1_S) +#define PVT_PUMP_BITMAP_LOW1_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW1_S 0 + +/** PVT_PMUP_BITMAP_LOW2_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW2_REG (DR_REG_PVT_MONITOR_BASE + 0x1c) +/** PVT_PUMP_BITMAP_LOW2 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel2 + */ +#define PVT_PUMP_BITMAP_LOW2 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW2_M (PVT_PUMP_BITMAP_LOW2_V << PVT_PUMP_BITMAP_LOW2_S) +#define PVT_PUMP_BITMAP_LOW2_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW2_S 0 + +/** PVT_PMUP_BITMAP_LOW3_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW3_REG (DR_REG_PVT_MONITOR_BASE + 0x20) +/** PVT_PUMP_BITMAP_LOW3 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel3 + */ +#define PVT_PUMP_BITMAP_LOW3 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW3_M (PVT_PUMP_BITMAP_LOW3_V << PVT_PUMP_BITMAP_LOW3_S) +#define PVT_PUMP_BITMAP_LOW3_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW3_S 0 + +/** PVT_PMUP_BITMAP_LOW4_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW4_REG (DR_REG_PVT_MONITOR_BASE + 0x24) +/** PVT_PUMP_BITMAP_LOW4 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel4 + */ +#define PVT_PUMP_BITMAP_LOW4 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW4_M (PVT_PUMP_BITMAP_LOW4_V << PVT_PUMP_BITMAP_LOW4_S) +#define PVT_PUMP_BITMAP_LOW4_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW4_S 0 + +/** PVT_PMUP_DRV_CFG_REG register + * configure pump drv + */ +#define PVT_PMUP_DRV_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x28) +/** PVT_PUMP_EN : R/W; bitpos: [9]; default: 0; + * configure pvt charge xpd + */ +#define PVT_PUMP_EN (BIT(9)) +#define PVT_PUMP_EN_M (PVT_PUMP_EN_V << PVT_PUMP_EN_S) +#define PVT_PUMP_EN_V 0x00000001U +#define PVT_PUMP_EN_S 9 +/** PVT_CLK_EN : R/W; bitpos: [10]; default: 0; + * force register clken + */ +#define PVT_CLK_EN (BIT(10)) +#define PVT_CLK_EN_M (PVT_CLK_EN_V << PVT_CLK_EN_S) +#define PVT_CLK_EN_V 0x00000001U +#define PVT_CLK_EN_S 10 +/** PVT_PUMP_DRV4 : R/W; bitpos: [14:11]; default: 0; + * configure cmd4 drv + */ +#define PVT_PUMP_DRV4 0x0000000FU +#define PVT_PUMP_DRV4_M (PVT_PUMP_DRV4_V << PVT_PUMP_DRV4_S) +#define PVT_PUMP_DRV4_V 0x0000000FU +#define PVT_PUMP_DRV4_S 11 +/** PVT_PUMP_DRV3 : R/W; bitpos: [18:15]; default: 0; + * configure cmd3 drv + */ +#define PVT_PUMP_DRV3 0x0000000FU +#define PVT_PUMP_DRV3_M (PVT_PUMP_DRV3_V << PVT_PUMP_DRV3_S) +#define PVT_PUMP_DRV3_V 0x0000000FU +#define PVT_PUMP_DRV3_S 15 +/** PVT_PUMP_DRV2 : R/W; bitpos: [22:19]; default: 0; + * configure cmd2 drv + */ +#define PVT_PUMP_DRV2 0x0000000FU +#define PVT_PUMP_DRV2_M (PVT_PUMP_DRV2_V << PVT_PUMP_DRV2_S) +#define PVT_PUMP_DRV2_V 0x0000000FU +#define PVT_PUMP_DRV2_S 19 +/** PVT_PUMP_DRV1 : R/W; bitpos: [26:23]; default: 0; + * configure cmd1 drv + */ +#define PVT_PUMP_DRV1 0x0000000FU +#define PVT_PUMP_DRV1_M (PVT_PUMP_DRV1_V << PVT_PUMP_DRV1_S) +#define PVT_PUMP_DRV1_V 0x0000000FU +#define PVT_PUMP_DRV1_S 23 +/** PVT_PUMP_DRV0 : R/W; bitpos: [30:27]; default: 0; + * configure cmd0 drv + */ +#define PVT_PUMP_DRV0 0x0000000FU +#define PVT_PUMP_DRV0_M (PVT_PUMP_DRV0_V << PVT_PUMP_DRV0_S) +#define PVT_PUMP_DRV0_V 0x0000000FU +#define PVT_PUMP_DRV0_S 27 + +/** PVT_PMUP_CHANNEL_CFG_REG register + * configure the code of valid pump channel code + */ +#define PVT_PMUP_CHANNEL_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x2c) +/** PVT_PUMP_CHANNEL_CODE4 : R/W; bitpos: [11:7]; default: 0; + * configure cmd4 code + */ +#define PVT_PUMP_CHANNEL_CODE4 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE4_M (PVT_PUMP_CHANNEL_CODE4_V << PVT_PUMP_CHANNEL_CODE4_S) +#define PVT_PUMP_CHANNEL_CODE4_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE4_S 7 +/** PVT_PUMP_CHANNEL_CODE3 : R/W; bitpos: [16:12]; default: 0; + * configure cmd3 code + */ +#define PVT_PUMP_CHANNEL_CODE3 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE3_M (PVT_PUMP_CHANNEL_CODE3_V << PVT_PUMP_CHANNEL_CODE3_S) +#define PVT_PUMP_CHANNEL_CODE3_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE3_S 12 +/** PVT_PUMP_CHANNEL_CODE2 : R/W; bitpos: [21:17]; default: 0; + * configure cmd2 code + */ +#define PVT_PUMP_CHANNEL_CODE2 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE2_M (PVT_PUMP_CHANNEL_CODE2_V << PVT_PUMP_CHANNEL_CODE2_S) +#define PVT_PUMP_CHANNEL_CODE2_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE2_S 17 +/** PVT_PUMP_CHANNEL_CODE1 : R/W; bitpos: [26:22]; default: 0; + * configure cmd1 code + */ +#define PVT_PUMP_CHANNEL_CODE1 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE1_M (PVT_PUMP_CHANNEL_CODE1_V << PVT_PUMP_CHANNEL_CODE1_S) +#define PVT_PUMP_CHANNEL_CODE1_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE1_S 22 +/** PVT_PUMP_CHANNEL_CODE0 : R/W; bitpos: [31:27]; default: 0; + * configure cmd0 code + */ +#define PVT_PUMP_CHANNEL_CODE0 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE0_M (PVT_PUMP_CHANNEL_CODE0_V << PVT_PUMP_CHANNEL_CODE0_S) +#define PVT_PUMP_CHANNEL_CODE0_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE0_S 27 + +/** PVT_CLK_CFG_REG register + * configure pvt clk + */ +#define PVT_CLK_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x30) +/** PVT_PUMP_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * needs field desc + */ +#define PVT_PUMP_CLK_DIV_NUM 0x000000FFU +#define PVT_PUMP_CLK_DIV_NUM_M (PVT_PUMP_CLK_DIV_NUM_V << PVT_PUMP_CLK_DIV_NUM_S) +#define PVT_PUMP_CLK_DIV_NUM_V 0x000000FFU +#define PVT_PUMP_CLK_DIV_NUM_S 0 +/** PVT_MONITOR_CLK_PVT_EN : R/W; bitpos: [8]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_CLK_PVT_EN (BIT(8)) +#define PVT_MONITOR_CLK_PVT_EN_M (PVT_MONITOR_CLK_PVT_EN_V << PVT_MONITOR_CLK_PVT_EN_S) +#define PVT_MONITOR_CLK_PVT_EN_V 0x00000001U +#define PVT_MONITOR_CLK_PVT_EN_S 8 +/** PVT_CLK_SEL : R/W; bitpos: [31]; default: 0; + * select pvt clk + */ +#define PVT_CLK_SEL (BIT(31)) +#define PVT_CLK_SEL_M (PVT_CLK_SEL_V << PVT_CLK_SEL_S) +#define PVT_CLK_SEL_V 0x00000001U +#define PVT_CLK_SEL_S 31 + +/** PVT_DBIAS_CHANNEL_SEL0_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL_SEL0_REG (DR_REG_PVT_MONITOR_BASE + 0x34) +/** PVT_DBIAS_CHANNEL3_SEL : R/W; bitpos: [10:4]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL3_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL3_SEL_M (PVT_DBIAS_CHANNEL3_SEL_V << PVT_DBIAS_CHANNEL3_SEL_S) +#define PVT_DBIAS_CHANNEL3_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL3_SEL_S 4 +/** PVT_DBIAS_CHANNEL2_SEL : R/W; bitpos: [17:11]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL2_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL2_SEL_M (PVT_DBIAS_CHANNEL2_SEL_V << PVT_DBIAS_CHANNEL2_SEL_S) +#define PVT_DBIAS_CHANNEL2_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL2_SEL_S 11 +/** PVT_DBIAS_CHANNEL1_SEL : R/W; bitpos: [24:18]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL1_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL1_SEL_M (PVT_DBIAS_CHANNEL1_SEL_V << PVT_DBIAS_CHANNEL1_SEL_S) +#define PVT_DBIAS_CHANNEL1_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL1_SEL_S 18 +/** PVT_DBIAS_CHANNEL0_SEL : R/W; bitpos: [31:25]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL0_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL0_SEL_M (PVT_DBIAS_CHANNEL0_SEL_V << PVT_DBIAS_CHANNEL0_SEL_S) +#define PVT_DBIAS_CHANNEL0_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL0_SEL_S 25 + +/** PVT_DBIAS_CHANNEL_SEL1_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL_SEL1_REG (DR_REG_PVT_MONITOR_BASE + 0x38) +/** PVT_DBIAS_CHANNEL4_SEL : R/W; bitpos: [31:25]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL4_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL4_SEL_M (PVT_DBIAS_CHANNEL4_SEL_V << PVT_DBIAS_CHANNEL4_SEL_S) +#define PVT_DBIAS_CHANNEL4_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL4_SEL_S 25 + +/** PVT_DBIAS_CHANNEL0_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL0_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x3c) +/** PVT_DBIAS_CHANNEL0_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL0_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL0_CFG_M (PVT_DBIAS_CHANNEL0_CFG_V << PVT_DBIAS_CHANNEL0_CFG_S) +#define PVT_DBIAS_CHANNEL0_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL0_CFG_S 0 + +/** PVT_DBIAS_CHANNEL1_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL1_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x40) +/** PVT_DBIAS_CHANNEL1_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL1_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL1_CFG_M (PVT_DBIAS_CHANNEL1_CFG_V << PVT_DBIAS_CHANNEL1_CFG_S) +#define PVT_DBIAS_CHANNEL1_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL1_CFG_S 0 + +/** PVT_DBIAS_CHANNEL2_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL2_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x44) +/** PVT_DBIAS_CHANNEL2_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL2_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL2_CFG_M (PVT_DBIAS_CHANNEL2_CFG_V << PVT_DBIAS_CHANNEL2_CFG_S) +#define PVT_DBIAS_CHANNEL2_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL2_CFG_S 0 + +/** PVT_DBIAS_CHANNEL3_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL3_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x48) +/** PVT_DBIAS_CHANNEL3_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL3_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL3_CFG_M (PVT_DBIAS_CHANNEL3_CFG_V << PVT_DBIAS_CHANNEL3_CFG_S) +#define PVT_DBIAS_CHANNEL3_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL3_CFG_S 0 + +/** PVT_DBIAS_CHANNEL4_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL4_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x4c) +/** PVT_DBIAS_CHANNEL4_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL4_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL4_CFG_M (PVT_DBIAS_CHANNEL4_CFG_V << PVT_DBIAS_CHANNEL4_CFG_S) +#define PVT_DBIAS_CHANNEL4_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL4_CFG_S 0 + +/** PVT_DBIAS_CMD0_REG register + * needs desc + */ +#define PVT_DBIAS_CMD0_REG (DR_REG_PVT_MONITOR_BASE + 0x50) +/** PVT_DBIAS_CMD0 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD0_OFFSET_FLAG 1 +#define PVT_DBIAS_CMD0_OFFSET_FLAG_S 16 +#define PVT_DBIAS_CMD0_OFFSET_VALUE 0x1F +#define PVT_DBIAS_CMD0_OFFSET_VALUE_S 11 +#define PVT_DBIAS_CMD0_PVT 0x7FF +#define PVT_DBIAS_CMD0_PVT_S 0 + +/** PVT_DBIAS_CMD1_REG register + * needs desc + */ +#define PVT_DBIAS_CMD1_REG (DR_REG_PVT_MONITOR_BASE + 0x54) +/** PVT_DBIAS_CMD1 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD1_OFFSET_FLAG 1 +#define PVT_DBIAS_CMD1_OFFSET_FLAG_S 16 +#define PVT_DBIAS_CMD1_OFFSET_VALUE 0x1F +#define PVT_DBIAS_CMD1_OFFSET_VALUE_S 11 +#define PVT_DBIAS_CMD1_PVT 0x7FF +#define PVT_DBIAS_CMD1_PVT_S 0 + +/** PVT_DBIAS_CMD2_REG register + * needs desc + */ +#define PVT_DBIAS_CMD2_REG (DR_REG_PVT_MONITOR_BASE + 0x58) +/** PVT_DBIAS_CMD2 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD2_OFFSET_FLAG 1 +#define PVT_DBIAS_CMD2_OFFSET_FLAG_S 16 +#define PVT_DBIAS_CMD2_OFFSET_VALUE 0x1F +#define PVT_DBIAS_CMD2_OFFSET_VALUE_S 11 +#define PVT_DBIAS_CMD2_PVT 0x7FF +#define PVT_DBIAS_CMD2_PVT_S 0 + +/** PVT_DBIAS_CMD3_REG register + * needs desc + */ +#define PVT_DBIAS_CMD3_REG (DR_REG_PVT_MONITOR_BASE + 0x5c) +/** PVT_DBIAS_CMD3 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD3 0x0001FFFFU +#define PVT_DBIAS_CMD3_M (PVT_DBIAS_CMD3_V << PVT_DBIAS_CMD3_S) +#define PVT_DBIAS_CMD3_V 0x0001FFFFU +#define PVT_DBIAS_CMD3_S 0 + +/** PVT_DBIAS_CMD4_REG register + * needs desc + */ +#define PVT_DBIAS_CMD4_REG (DR_REG_PVT_MONITOR_BASE + 0x60) +/** PVT_DBIAS_CMD4 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD4 0x0001FFFFU +#define PVT_DBIAS_CMD4_M (PVT_DBIAS_CMD4_V << PVT_DBIAS_CMD4_S) +#define PVT_DBIAS_CMD4_V 0x0001FFFFU +#define PVT_DBIAS_CMD4_S 0 + +/** PVT_DBIAS_TIMER_REG register + * needs desc + */ +#define PVT_DBIAS_TIMER_REG (DR_REG_PVT_MONITOR_BASE + 0x64) +/** PVT_TIMER_TARGET : R/W; bitpos: [30:15]; default: 65535; + * needs field desc + */ +#define PVT_TIMER_TARGET 0x0000FFFFU +#define PVT_TIMER_TARGET_M (PVT_TIMER_TARGET_V << PVT_TIMER_TARGET_S) +#define PVT_TIMER_TARGET_V 0x0000FFFFU +#define PVT_TIMER_TARGET_S 15 +/** PVT_TIMER_EN : R/W; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMER_EN (BIT(31)) +#define PVT_TIMER_EN_M (PVT_TIMER_EN_V << PVT_TIMER_EN_S) +#define PVT_TIMER_EN_V 0x00000001U +#define PVT_TIMER_EN_S 31 + +/** PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x68) +/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_M (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_M (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_M (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_S 31 + +/** PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x6c) +/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_M (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_M (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_M (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_S 31 + +/** PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x70) +/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_M (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_M (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_M (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_S 31 + +/** PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x74) +/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_M (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_M (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_M (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_S 31 + +/** PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x78) +/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_M (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_M (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_M (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_S 31 + +/** PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x7c) +/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_M (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_M (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_M (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_S 31 + +/** PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x80) +/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_M (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_M (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_M (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_S 31 + +/** PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x84) +/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_M (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_M (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_M (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_S 31 + +/** PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x88) +/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_M (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_M (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_M (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_S 31 + +/** PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x8c) +/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_M (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_M (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_M (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_S 31 + +/** PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x90) +/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_M (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_M (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_M (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_S 31 + +/** PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x94) +/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_M (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_M (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_M (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_S 31 + +/** PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x98) +/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_M (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_M (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_M (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_S 31 + +/** PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x9c) +/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_M (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_M (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_M (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_S 31 + +/** PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xa0) +/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_M (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_M (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_M (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_S 31 + +/** PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xa4) +/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_M (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_M (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_M (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_S 31 + +/** PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xa8) +/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_M (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_M (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_M (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_S 31 + +/** PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xac) +/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_M (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_M (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_M (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_S 31 + +/** PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xb0) +/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_M (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_M (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_M (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_S 31 + +/** PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xb4) +/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_M (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_M (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_M (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_S 31 + +/** PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xb8) +/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_M (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_M (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_M (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_S 31 + +/** PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xbc) +/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_M (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_M (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_M (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_S 31 + +/** PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xc0) +/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_M (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_M (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_M (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_S 31 + +/** PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xc4) +/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_M (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_M (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_M (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_S 31 + +/** PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xc8) +/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_M (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_M (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_M (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_S 31 + +/** PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xcc) +/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_M (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_M (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_M (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_S 31 + +/** PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xd0) +/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_M (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_M (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_M (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_S 31 + +/** PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xd4) +/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_M (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_M (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_M (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_S 31 + +/** PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xd8) +/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_M (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_M (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_M (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_S 31 + +/** PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xdc) +/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_M (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_M (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_M (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_S 31 + +/** PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xe0) +/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_M (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_M (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_M (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_S 31 + +/** PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xe4) +/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_M (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_M (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_M (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_S 31 + +/** PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xe8) +/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_M (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_M (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_M (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_S 31 + +/** PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xec) +/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_M (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_M (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_M (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_S 31 + +/** PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xf0) +/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_M (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_M (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_M (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_S 31 + +/** PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xf4) +/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_M (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_M (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_M (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_S 31 + +/** PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0xf8) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_M (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_S) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_S 16 + +/** PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0xfc) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_M (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_S) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_S 16 + +/** PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x100) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_M (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_S) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_S 16 + +/** PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x104) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_M (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_S) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_S 16 + +/** PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x108) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_M (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_S) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_S 16 + +/** PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x10c) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_M (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_S) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_S 16 + +/** PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x110) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_M (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_S) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_S 16 + +/** PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x114) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_M (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_S) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_S 16 + +/** PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x118) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_M (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_S) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_S 16 + +/** PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x11c) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_M (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_S) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_S 16 + +/** PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x120) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_M (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_S) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_S 16 + +/** PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x124) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_M (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_S) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_S 16 + +/** PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x128) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_M (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_S) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_S 16 + +/** PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x12c) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_M (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_S) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_S 16 + +/** PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x130) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_M (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_S) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_S 16 + +/** PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x134) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_M (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_S) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_S 16 + +/** PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x138) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_M (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_S) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_S 16 + +/** PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x13c) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_M (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_S) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_S 16 + +/** PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x140) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_M (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_S) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_S 16 + +/** PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x144) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_M (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_S) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_S 16 + +/** PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x148) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_M (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_S) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_S 16 + +/** PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x14c) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_M (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_S) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_S 16 + +/** PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x150) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_M (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_S) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_S 16 + +/** PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x154) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_M (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_S) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_S 16 + +/** PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x158) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_M (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_S) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_S 16 + +/** PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x15c) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_M (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_S) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_S 16 + +/** PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x160) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_M (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_S) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_S 16 + +/** PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x164) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_M (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_S) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_S 16 + +/** PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x168) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_M (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_S) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_S 16 + +/** PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x16c) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_M (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_S) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_S 16 + +/** PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x170) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_M (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_S) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_S 16 + +/** PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x174) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_M (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_S) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_S 16 + +/** PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x178) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_M (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_S) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_S 16 + +/** PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x17c) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_M (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_S) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_S 16 + +/** PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x180) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_M (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_S) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_S 16 + +/** PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x184) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_M (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_S) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_S 16 + +/** PVT_DATE_REG register + * version register + */ +#define PVT_DATE_REG (DR_REG_PVT_MONITOR_BASE + 0xffc) +/** PVT_DATE : R/W; bitpos: [31:0]; default: 34677040; + * version register + */ +#define PVT_DATE 0xFFFFFFFFU +#define PVT_DATE_M (PVT_DATE_V << PVT_DATE_S) +#define PVT_DATE_V 0xFFFFFFFFU +#define PVT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 44094ca80b..73e09f37b6 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -64,6 +64,7 @@ #define SOC_APM_SUPPORTED 1 #define SOC_APM_CTRL_FILTER_SUPPORTED 1 #define SOC_PMU_SUPPORTED 1 +#define SOC_PMU_PVT_SUPPORTED 1 #define SOC_PAU_SUPPORTED 1 #define SOC_LP_TIMER_SUPPORTED 1 #define SOC_LP_AON_SUPPORTED 1 diff --git a/components/soc/esp32c6/include/soc/system_periph_retention.h b/components/soc/esp32c6/include/soc/system_periph_retention.h index 54f7c3e205..57564800b9 100644 --- a/components/soc/esp32c6/include/soc/system_periph_retention.h +++ b/components/soc/esp32c6/include/soc/system_periph_retention.h @@ -87,6 +87,16 @@ extern const regdma_entries_config_t flash_spimem_regs_retention[SPIMEM_RETENTIO #define SYSTIMER_RETENTION_LINK_LEN 19 extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_LINK_LEN]; +/** + * @brief Provide access to pvt configuration registers retention + * context definition. + * + * This is an internal function of the sleep retention driver, and is not + * useful for external use. + */ +#define PVT_RETENTION_LINK_LEN 1 +extern const regdma_entries_config_t pvt_regs_retention[PVT_RETENTION_LINK_LEN]; + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c6/system_retention_periph.c b/components/soc/esp32c6/system_retention_periph.c index 2d9227575a..439366b3b4 100644 --- a/components/soc/esp32c6/system_retention_periph.c +++ b/components/soc/esp32c6/system_retention_periph.c @@ -17,6 +17,7 @@ #include "soc/gpio_reg.h" #include "soc/io_mux_reg.h" #include "soc/interrupt_matrix_reg.h" +#include "soc/pvt_reg.h" /* Interrupt Matrix Registers Context */ #define N_REGS_INTR_MATRIX() (((INTMTX_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_MATRIX_BASE) / 4) + 1) @@ -113,3 +114,10 @@ const regdma_entries_config_t systimer_regs_retention[] = { [18] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x12), SYSTIMER_INT_ENA_REG, SYSTIMER_INT_ENA_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* Systimer intr enable */ }; _Static_assert(ARRAY_SIZE(systimer_regs_retention) == SYSTIMER_RETENTION_LINK_LEN, "Inconsistent Systimer retention link length definitions"); + +/* PVT Registers Context */ +#define N_REGS_PVT (((PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG - DR_REG_PVT_MONITOR_BASE) / 4) + 1) +const regdma_entries_config_t pvt_regs_retention[] = { + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PVT_LINK(0x00), DR_REG_PVT_MONITOR_BASE, DR_REG_PVT_MONITOR_BASE, N_REGS_PVT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, +}; +_Static_assert(ARRAY_SIZE(pvt_regs_retention) == PVT_RETENTION_LINK_LEN, "Inconsistent PVT retention link length definitions"); diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index c14b0e739e..2243c3f582 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -231,6 +231,14 @@ config SOC_PMU_PVT_SUPPORTED bool default y +config SOC_PVT_EN_WITH_SLEEP + bool + default y + +config SOC_PVT_RETENTION_BY_REGDMA + bool + default y + config SOC_DCDC_SUPPORTED bool default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 38c3cac3b1..7e48709364 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -75,6 +75,8 @@ #define SOC_APM_SUPPORTED 1 #define SOC_PMU_SUPPORTED 1 #define SOC_PMU_PVT_SUPPORTED 1 +#define SOC_PVT_EN_WITH_SLEEP 1 +#define SOC_PVT_RETENTION_BY_REGDMA 1 #define SOC_DCDC_SUPPORTED 1 #define SOC_PAU_SUPPORTED 1 //TODO: IDF-7531 #define SOC_LP_TIMER_SUPPORTED 1 From 569752d2c9238ebfe1fae8590925eef650da1443 Mon Sep 17 00:00:00 2001 From: "yanzihan@espressif.com" Date: Mon, 19 Jan 2026 21:13:55 +0800 Subject: [PATCH 2/3] fix(esp_hw_support): adjust pvt prepare cost in sleep wakeup --- components/esp_hw_support/sleep_modes.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index ecbfea4b0a..cd2b985e7e 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -156,9 +156,11 @@ #elif CONFIG_IDF_TARGET_ESP32C6 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (318) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56) +#define PVT_REINIT_COST_US (60) #elif CONFIG_IDF_TARGET_ESP32C5 // TODO: [ESP32C5] IDF-8638 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (318) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56) +#define PVT_REINIT_COST_US (25) #elif CONFIG_IDF_TARGET_ESP32H2 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (118) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9) @@ -1361,9 +1363,9 @@ esp_err_t esp_light_sleep_start(void) // Re-calibrate the RTC clock sleep_low_power_clock_calibration(false); + uint32_t cur_cpu_freq = esp_clk_cpu_freq() / MHZ; + uint32_t xtal_freq = rtc_clk_xtal_freq_get(); if (s_config.overhead_out_need_remeasure) { - uint32_t cur_cpu_freq = esp_clk_cpu_freq() / MHZ; - uint32_t xtal_freq = rtc_clk_xtal_freq_get(); if (cur_cpu_freq < xtal_freq) { s_config.sleep_time_overhead_out = DEFAULT_SLEEP_OUT_OVERHEAD_US * xtal_freq / cur_cpu_freq; } else { @@ -1380,6 +1382,17 @@ esp_err_t esp_light_sleep_start(void) */ #if SOC_PMU_SUPPORTED int sleep_time_sw_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + sleep_time_overhead_in + s_config.sleep_time_overhead_out; +#if CONFIG_ESP_ENABLE_PVT && !SOC_PVT_EN_WITH_SLEEP + /* PVT will only be enabled during the wake-up process if the CPU's clock source is PLL when the CPU goes to sleep. */ + if ((cur_cpu_freq > xtal_freq) +#if CONFIG_IDF_TARGET_ESP32C5 + /* On esp32c5, CPU 40m is divided from PLL160/240M */ + || (xtal_freq == SOC_XTAL_FREQ_48M && cur_cpu_freq == 40) +#endif + ) { + sleep_time_sw_adjustment += PVT_REINIT_COST_US; + } +#endif int sleep_time_hw_adjustment = pmu_sleep_calculate_hw_wait_time(pd_flags, rtc_clk_slow_src_get(), s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period); s_config.sleep_time_adjustment = sleep_time_sw_adjustment + sleep_time_hw_adjustment; #else From 94838b4106939daa691c7cdcca3cd0b4c3258879 Mon Sep 17 00:00:00 2001 From: "yanzihan@espressif.com" Date: Mon, 19 Jan 2026 14:35:41 +0800 Subject: [PATCH 3/3] feat(esp_hw_support): fix pvt charge pump bug on chip761 --- components/esp_hw_support/port/esp32c6/pmu_pvt.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/components/esp_hw_support/port/esp32c6/pmu_pvt.c b/components/esp_hw_support/port/esp32c6/pmu_pvt.c index c8a28616f7..114db6d602 100644 --- a/components/esp_hw_support/port/esp32c6/pmu_pvt.c +++ b/components/esp_hw_support/port/esp32c6/pmu_pvt.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -101,13 +101,11 @@ void pvt_auto_dbias_init(void) SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG, PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0, PVT_EDG_MODE, PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S); // Select edge_mode SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0, PVT_DELAY_NUM_HIGH, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S); // The threshold for determining whether the voltage is too high SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1, PVT_DELAY_NUM_LOW, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S); // The threshold for determining whether the voltage is too low - SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2, PVT_DELAY_NUM_PUMP, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S); // The threshold for chargepump + SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG, PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2, PVT_DELAY_NUM_PUMP, PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S); // The threshold for chargepump /*config lp offset for pvt func*/ uint8_t lp_hp_gap = get_lp_hp_gap(); set_pvt_hp_lp_gap(lp_hp_gap); - } else { - ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt auto dbias init not supported in efuse."); } } @@ -135,8 +133,6 @@ void IRAM_ATTR pvt_func_enable(bool enable) CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN); CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN); } - } else { - ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt enable not supported in efuse."); } } @@ -148,8 +144,6 @@ void charge_pump_init(void) SET_PERI_REG_BITS(PVT_PMUP_CHANNEL_CFG_REG, PVT_PUMP_CHANNEL_CODE0, PVT_PUMP_CHANNEL_CODE, PVT_PUMP_CHANNEL_CODE0_S); //Set channel code WRITE_PERI_REG(PVT_PMUP_BITMAP_LOW0_REG, (1 << PVT_PUMP_BITMAP)); // Select monitor cell for charge pump SET_PERI_REG_BITS(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_DRV0, PVT_PUMP_DRV, PVT_PUMP_DRV0_S); //Configure the charging intensity - } else { - ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt charge_pump init not supported in efuse."); } } @@ -162,8 +156,6 @@ void IRAM_ATTR charge_pump_enable(bool enable) } else { CLEAR_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); //disable charge pump } - } else { - ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt charge_pump enable not supported in efuse."); } }