From ba29417ff4ce3d61d2d0a90319db76bd1a3e92d9 Mon Sep 17 00:00:00 2001 From: cjin Date: Fri, 17 Apr 2026 16:35:00 +0800 Subject: [PATCH] feat(bt): supported bt modem clock configuration on esp32s31 --- .../bt/porting_btdm/controller/btdm_common/src/btdm_lp.c | 6 +----- components/esp_phy/src/phy_init.c | 1 + 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/components/bt/porting_btdm/controller/btdm_common/src/btdm_lp.c b/components/bt/porting_btdm/controller/btdm_common/src/btdm_lp.c index 2c412ca3e1..a8b7171fc2 100644 --- a/components/bt/porting_btdm/controller/btdm_common/src/btdm_lp.c +++ b/components/bt/porting_btdm/controller/btdm_common/src/btdm_lp.c @@ -283,10 +283,6 @@ btdm_lp_enable_clock(esp_btdm_controller_config_t *cfg) { modem_clock_module_enable(PERIPH_BT_MODULE); modem_clock_module_mac_reset(PERIPH_BT_MODULE); -#if CONFIG_IDF_TARGET_ESP32S31 - // TODO: PM-704 - REG_WRITE(HP_SYS_CLKRST_MODEM_CONF_REG, 0x3d); -#endif btdm_lp_timer_clk_init(cfg); } @@ -379,8 +375,8 @@ btdm_lp_reset(bool enable_stage) esp_btbb_enable(); s_bt_active = true; } else { + esp_btbb_disable(); if (s_bt_active) { - esp_btbb_disable(); esp_phy_disable(PHY_MODEM_BT); #if CONFIG_PM_ENABLE esp_pm_lock_release(s_pm_lock); diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c index 1829881aa6..140ae0f9c8 100644 --- a/components/esp_phy/src/phy_init.c +++ b/components/esp_phy/src/phy_init.c @@ -370,6 +370,7 @@ void esp_phy_enable(esp_phy_modem_t modem) phy_ant_update(); phy_ant_clr_update_flag(); } + phy_module_disable(); } phy_set_modem_flag(modem); #if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_ESP_PHY_DISABLE_PLL_TRACK