diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/README.md b/components/esp_driver_mcpwm/test_apps/mcpwm/README.md index 24b8600b2e..9917b63055 100644 --- a/components/esp_driver_mcpwm/test_apps/mcpwm/README.md +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | diff --git a/components/esp_hal_mcpwm/esp32/include/hal/mcpwm_ll.h b/components/esp_hal_mcpwm/esp32/include/hal/mcpwm_ll.h index 5827e6d00a..cea462f333 100644 --- a/components/esp_hal_mcpwm/esp32/include/hal/mcpwm_ll.h +++ b/components/esp_hal_mcpwm/esp32/include/hal/mcpwm_ll.h @@ -4,12 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -/******************************************************************************* - * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in hal/include/hal/readme.md - ******************************************************************************/ - // The LL layer for ESP32 MCPWM register operations #pragma once diff --git a/components/esp_hal_mcpwm/esp32c5/include/hal/mcpwm_ll.h b/components/esp_hal_mcpwm/esp32c5/include/hal/mcpwm_ll.h index 02944ddc62..1a45d3ae6c 100644 --- a/components/esp_hal_mcpwm/esp32c5/include/hal/mcpwm_ll.h +++ b/components/esp_hal_mcpwm/esp32c5/include/hal/mcpwm_ll.h @@ -28,7 +28,7 @@ extern "C" { #define MCPWM_LL_GET_HW(ID) (((ID) == 0) ? &MCPWM0 : NULL) // MCPWM capabilities -#define MCPWM_LL_GROUP_NUM (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) +#define MCPWM_LL_GROUP_NUM (1) ///< 1 MCPWM group on the chip (i.e., the number of independent MCPWM peripherals) #define MCPWM_LL_TIMERS_PER_GROUP (3) ///< The number of timers that each group has #define MCPWM_LL_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has #define MCPWM_LL_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has diff --git a/components/esp_hal_mcpwm/esp32c6/include/hal/mcpwm_ll.h b/components/esp_hal_mcpwm/esp32c6/include/hal/mcpwm_ll.h index b83037e51e..62f9b4c053 100644 --- a/components/esp_hal_mcpwm/esp32c6/include/hal/mcpwm_ll.h +++ b/components/esp_hal_mcpwm/esp32c6/include/hal/mcpwm_ll.h @@ -4,12 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -/******************************************************************************* - * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in hal/include/hal/readme.md - ******************************************************************************/ - // The LL layer for ESP32-C6 MCPWM register operations #pragma once @@ -35,7 +29,7 @@ extern "C" { #define MCPWM_LL_GET_HW(ID) (((ID) == 0) ? &MCPWM0 : NULL) // MCPWM capabilities -#define MCPWM_LL_GROUP_NUM (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) +#define MCPWM_LL_GROUP_NUM (1) ///< 1 MCPWM group on the chip (i.e., the number of independent MCPWM peripherals) #define MCPWM_LL_TIMERS_PER_GROUP (3) ///< The number of timers that each group has #define MCPWM_LL_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has #define MCPWM_LL_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has diff --git a/components/esp_hal_mcpwm/esp32h2/include/hal/mcpwm_ll.h b/components/esp_hal_mcpwm/esp32h2/include/hal/mcpwm_ll.h index ce536a12e5..f600f854ce 100644 --- a/components/esp_hal_mcpwm/esp32h2/include/hal/mcpwm_ll.h +++ b/components/esp_hal_mcpwm/esp32h2/include/hal/mcpwm_ll.h @@ -4,12 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -/******************************************************************************* - * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in hal/include/hal/readme.md - ******************************************************************************/ - #pragma once #include @@ -33,7 +27,7 @@ extern "C" { #define MCPWM_LL_GET_HW(ID) (((ID) == 0) ? &MCPWM0 : NULL) // MCPWM capabilities -#define MCPWM_LL_GROUP_NUM (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) +#define MCPWM_LL_GROUP_NUM (1) ///< 1 MCPWM group on the chip (i.e., the number of independent MCPWM peripherals) #define MCPWM_LL_TIMERS_PER_GROUP (3) ///< The number of timers that each group has #define MCPWM_LL_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has #define MCPWM_LL_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has diff --git a/components/esp_hal_mcpwm/esp32h2/mcpwm_periph.c b/components/esp_hal_mcpwm/esp32h2/mcpwm_periph.c index c33ebe2a94..4f4feb5190 100644 --- a/components/esp_hal_mcpwm/esp32h2/mcpwm_periph.c +++ b/components/esp_hal_mcpwm/esp32h2/mcpwm_periph.c @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/soc.h" #include "hal/mcpwm_periph.h" #include "soc/mcpwm_reg.h" #include "soc/gpio_sig_map.h" diff --git a/components/esp_hal_mcpwm/esp32h21/include/hal/mcpwm_ll.h b/components/esp_hal_mcpwm/esp32h21/include/hal/mcpwm_ll.h new file mode 100644 index 0000000000..48d98086ed --- /dev/null +++ b/components/esp_hal_mcpwm/esp32h21/include/hal/mcpwm_ll.h @@ -0,0 +1,1656 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc/soc_caps.h" +#include "soc/mcpwm_struct.h" +#include "soc/clk_tree_defs.h" +#include "soc/pcr_struct.h" +#include "hal/mcpwm_types.h" +#include "hal/misc.h" +#include "hal/assert.h" +#include "soc/soc_etm_source.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// MCPWM LL get macro +#define MCPWM_LL_GET(attr) (MCPWM_LL_ ## attr) + +// Get MCPWM group register base address +#define MCPWM_LL_GET_HW(ID) (((ID) == 0) ? &MCPWM0 : NULL) + +// MCPWM capabilities +#define MCPWM_LL_GROUP_NUM (1) ///< 1 MCPWM group on the chip (i.e., the number of independent MCPWM peripherals) +#define MCPWM_LL_TIMERS_PER_GROUP (3) ///< The number of timers that each group has +#define MCPWM_LL_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has +#define MCPWM_LL_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has +#define MCPWM_LL_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has +#define MCPWM_LL_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has +#define MCPWM_LL_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has +#define MCPWM_LL_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has +#define MCPWM_LL_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has +#define MCPWM_LL_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has + +// MCPWM interrupt event mask +#define MCPWM_LL_EVENT_TIMER_STOP(timer) (1 << (timer)) +#define MCPWM_LL_EVENT_TIMER_EMPTY(timer) (1 << ((timer) + 3)) +#define MCPWM_LL_EVENT_TIMER_FULL(timer) (1 << ((timer) + 6)) +#define MCPWM_LL_EVENT_TIMER_MASK(timer) (MCPWM_LL_EVENT_TIMER_STOP(timer) | MCPWM_LL_EVENT_TIMER_EMPTY(timer) | MCPWM_LL_EVENT_TIMER_FULL(timer)) +#define MCPWM_LL_EVENT_FAULT_ENTER(fault) (1 << ((fault) + 9)) +#define MCPWM_LL_EVENT_FAULT_EXIT(fault) (1 << ((fault) + 12)) +#define MCPWM_LL_EVENT_FAULT_MASK(fault) (MCPWM_LL_EVENT_FAULT_ENTER(fault) | MCPWM_LL_EVENT_FAULT_EXIT(fault)) +#define MCPWM_LL_EVENT_CMP_EQUAL(oper, cmp) (1 << ((oper) + (cmp) * 3 + 15)) +#define MCPWM_LL_EVENT_OPER_BRAKE_CBC(oper) (1 << ((oper) + 21)) +#define MCPWM_LL_EVENT_OPER_BRAKE_OST(oper) (1 << ((oper) + 24)) +#define MCPWM_LL_EVENT_OPER_MASK(oper) (MCPWM_LL_EVENT_OPER_BRAKE_CBC(oper) | MCPWM_LL_EVENT_OPER_BRAKE_OST(oper)) +#define MCPWM_LL_EVENT_CAPTURE(cap) (1 << ((cap) + 27)) + +// Maximum values due to limited register bit width +#define MCPWM_LL_MAX_GROUP_PRESCALE 256 +#define MCPWM_LL_MAX_TIMER_PRESCALE 256 +#define MCPWM_LL_MAX_CARRIER_PRESCALE 16 +#define MCPWM_LL_MAX_CARRIER_ONESHOT 16 +#define MCPWM_LL_MAX_CAPTURE_PRESCALE 256 +#define MCPWM_LL_MAX_CAPTURE_TIMER_PRESCALE 1 +#define MCPWM_LL_MAX_DEAD_DELAY 65536 +#define MCPWM_LL_MAX_COUNT_VALUE 65536 + +// translate the HAL types into register values +#define MCPWM_LL_TIMER_EVENT_TO_REG_VAL(event) ((uint8_t[]) {0, 1}[(event)]) +#define MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) ((uint8_t[]) {0, 1, 2, 3}[(action)]) +#define MCPWM_LL_BRAKE_MODE_TO_REG_VAL(mode) ((uint8_t[]) {0, 1}[(mode)]) + +// MCPWM ETM comparator event table +#define MCPWM_LL_ETM_COMPARATOR_EVENT_TABLE(group, oper_id, cmpr_id, event) \ + (uint32_t [1][MCPWM_CMPR_ETM_EVENT_MAX]){{ \ + [MCPWM_CMPR_ETM_EVENT_EQUAL] = MCPWM_EVT_OP0_TEA + oper_id + 3 * cmpr_id, \ + }}[group][event] + +/** + * @brief The dead time module's clock source + */ +typedef enum { + MCPWM_LL_DEADTIME_CLK_SRC_GROUP, + MCPWM_LL_DEADTIME_CLK_SRC_TIMER, +} mcpwm_ll_deadtime_clock_src_t; + +////////////////////////////////////////MCPWM Group Specific//////////////////////////////////////////////////////////// + +/** + * @brief Enable the bus clock for MCPWM module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void mcpwm_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + PCR.pwm_conf.pwm_clk_en = enable; +} + +/** + * @brief Reset the MCPWM module + * + * @param group_id Group ID + */ +static inline void mcpwm_ll_reset_register(int group_id) +{ + (void)group_id; + PCR.pwm_conf.pwm_rst_en = 1; + PCR.pwm_conf.pwm_rst_en = 0; +} + +/** + * @brief Enable MCPWM function clock + * + * @param group_id Group ID + * @param en true to enable, false to disable + */ +static inline void mcpwm_ll_group_enable_clock(int group_id, bool en) +{ + (void)group_id; + PCR.pwm_clk_conf.pwm_clkm_en = en; +} + +/** + * @brief Set the clock source for MCPWM + * + * @param group_id Group ID + * @param clk_src Clock source for the MCPWM peripheral + */ +static inline void mcpwm_ll_group_set_clock_source(int group_id, soc_module_clk_t clk_src) +{ + (void)group_id; + switch (clk_src) { + case SOC_MOD_CLK_XTAL: + PCR.pwm_clk_conf.pwm_clkm_sel = 0; + break; + case SOC_MOD_CLK_PLL_F96M: + PCR.pwm_clk_conf.pwm_clkm_sel = 2; + break; + default: + HAL_ASSERT(false); + break; + } +} + +/** + * @brief Set the MCPWM group clock prescale + * + * @param group_id Group ID + * @param prescale Prescale value + */ +static inline void mcpwm_ll_group_set_clock_prescale(int group_id, int prescale) +{ + (void)group_id; + // group clock: PWM_clk = source_clock / (prescale) + HAL_ASSERT(prescale <= 256 && prescale > 0); + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.pwm_clk_conf, pwm_div_num, prescale - 1); +} + +/** + * @brief Enable update MCPWM active registers from shadow registers + * + * @param mcpwm Peripheral instance address + */ +static inline void mcpwm_ll_group_enable_shadow_mode(mcpwm_dev_t *mcpwm) +{ + mcpwm->update_cfg.global_up_en = 1; + mcpwm->update_cfg.op0_up_en = 1; + mcpwm->update_cfg.op1_up_en = 1; + mcpwm->update_cfg.op2_up_en = 1; +} + +/** + * @brief Flush shadow registers to active registers + * + * @param mcpwm Peripheral instance address + */ +static inline void mcpwm_ll_group_flush_shadow(mcpwm_dev_t *mcpwm) +{ + // a toggle can trigger a forced update of all active registers in MCPWM, i.e. shadow->active + mcpwm->update_cfg.global_force_up = 1; + mcpwm->update_cfg.global_force_up = 0; +} + +//////////////////////////////////////////Interrupt Specific//////////////////////////////////////////////////////////// + +/** + * @brief Get interrupt status register address + * + * @param mcpwm Peripheral instance address + * @return Register address + */ +static inline volatile void *mcpwm_ll_intr_get_status_reg(mcpwm_dev_t *mcpwm) +{ + return &mcpwm->int_st; +} + +/** + * @brief Enable MCPWM interrupt for specific event mask + * + * @param mcpwm Peripheral instance address + * @param mask Event mask + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_intr_enable(mcpwm_dev_t *mcpwm, uint32_t mask, bool enable) +{ + if (enable) { + mcpwm->int_ena.val |= mask; + } else { + mcpwm->int_ena.val &= ~mask; + } +} + +/** + * @brief Get MCPWM interrupt status + * + * @param mcpwm Peripheral instance address + * @return Interrupt status + */ +__attribute__((always_inline)) +static inline uint32_t mcpwm_ll_intr_get_status(mcpwm_dev_t *mcpwm) +{ + return mcpwm->int_st.val; +} + +/** + * @brief Clear MCPWM interrupt status by mask + * + * @param mcpwm Peripheral instance address + * @param mask Interrupt status mask + */ +__attribute__((always_inline)) +static inline void mcpwm_ll_intr_clear_status(mcpwm_dev_t *mcpwm, uint32_t mask) +{ + mcpwm->int_clr.val = mask; +} + +////////////////////////////////////////MCPWM Timer Specific//////////////////////////////////////////////////////////// + +/** + * @brief Set MCPWM timer prescale + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param prescale Prescale value + */ +static inline void mcpwm_ll_timer_set_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id, uint32_t prescale) +{ + HAL_ASSERT(prescale <= 256 && prescale > 0); + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_prescale, prescale - 1); +} + +/** + * @brief Set peak value for MCPWM timer + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param peak Peak value + * @param symmetric True to set symmetric peak value, False to set asymmetric peak value + */ +__attribute__((always_inline)) +static inline void mcpwm_ll_timer_set_peak(mcpwm_dev_t *mcpwm, int timer_id, uint32_t peak, bool symmetric) +{ + if (!symmetric) { // in asymmetric mode, period = [0,peak-1] + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period, peak - 1); + } else { // in symmetric mode, period = [0,peak-1] + [peak,1] + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period, peak); + } +} + +/** + * @brief Update MCPWM period immediately + * @note When period value is updated in the shadow register, it will be flushed to active register immediately. + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + */ +static inline void mcpwm_ll_timer_update_period_at_once(mcpwm_dev_t *mcpwm, int timer_id) +{ + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod = 0; +} + +/** + * @brief Enable to update MCPWM period upon TEZ event + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_timer_enable_update_period_on_tez(mcpwm_dev_t *mcpwm, int timer_id, bool enable) +{ + if (enable) { + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod |= 0x01; + } else { + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod &= ~0x01; + } +} + +/** + * @brief Enable to update MCPWM period upon sync event + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_timer_enable_update_period_on_sync(mcpwm_dev_t *mcpwm, int timer_id, bool enable) +{ + if (enable) { + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod |= 0x02; + } else { + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod &= ~0x02; + } +} + +/** + * @brief Set MCPWM timer count mode + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param mode Timer count mode + */ +static inline void mcpwm_ll_timer_set_count_mode(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_count_mode_t mode) +{ + switch (mode) { + case MCPWM_TIMER_COUNT_MODE_PAUSE: + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 0; + break; + case MCPWM_TIMER_COUNT_MODE_UP: + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 1; + break; + case MCPWM_TIMER_COUNT_MODE_DOWN: + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 2; + break; + case MCPWM_TIMER_COUNT_MODE_UP_DOWN: + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 3; + break; + default: + HAL_ASSERT(false); + break; + } +} + +/** + * @brief Execute MCPWM timer start/stop command + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param cmd Timer start/stop command + */ +static inline void mcpwm_ll_timer_set_start_stop_command(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_start_stop_cmd_t cmd) +{ + switch (cmd) { + case MCPWM_TIMER_STOP_EMPTY: + mcpwm->timer[timer_id].timer_cfg1.timer_start = 0; + break; + case MCPWM_TIMER_STOP_FULL: + mcpwm->timer[timer_id].timer_cfg1.timer_start = 1; + break; + case MCPWM_TIMER_START_NO_STOP: + mcpwm->timer[timer_id].timer_cfg1.timer_start = 2; + break; + case MCPWM_TIMER_START_STOP_EMPTY: + mcpwm->timer[timer_id].timer_cfg1.timer_start = 3; + break; + case MCPWM_TIMER_START_STOP_FULL: + mcpwm->timer[timer_id].timer_cfg1.timer_start = 4; + break; + default: + HAL_ASSERT(false); + break; + } +} + +/** + * @brief Get timer count value + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @return Timer count value + */ +__attribute__((always_inline)) +static inline uint32_t mcpwm_ll_timer_get_count_value(mcpwm_dev_t *mcpwm, int timer_id) +{ + // status.value saves the "next count value", so need an extra round up here to get the current count value according to count mode + // timer is paused + if (mcpwm->timer[timer_id].timer_cfg1.timer_mod == 0) { + return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_status, timer_value); + } + if (mcpwm->timer[timer_id].timer_status.timer_direction) { // down direction + return (HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_status, timer_value) + 1) % + (HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + 1); + } + // up direction + return (HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_status, timer_value) + + HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period)) % + (HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + 1); +} + +/** + * @brief Get timer count direction + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @return Timer count direction + */ +__attribute__((always_inline)) +static inline mcpwm_timer_direction_t mcpwm_ll_timer_get_count_direction(mcpwm_dev_t *mcpwm, int timer_id) +{ + return mcpwm->timer[timer_id].timer_status.timer_direction ? MCPWM_TIMER_DIRECTION_DOWN : MCPWM_TIMER_DIRECTION_UP; +} + +/** + * @brief Enable sync input for timer + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_timer_enable_sync_input(mcpwm_dev_t *mcpwm, int timer_id, bool enable) +{ + mcpwm->timer[timer_id].timer_sync.timer_synci_en = enable; +} + +/** + * @brief Use the input sync signal as the output sync signal (i.e. propagate the input sync signal) + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + */ +static inline void mcpwm_ll_timer_propagate_input_sync(mcpwm_dev_t *mcpwm, int timer_id) +{ + // sync_out is selected to sync_in + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 0; +} + +/** + * @brief Set the sync output signal to one of the timer event + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param event Timer event + */ +static inline void mcpwm_ll_timer_sync_out_on_timer_event(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_event_t event) +{ + switch (event) { + case MCPWM_TIMER_EVENT_EMPTY: + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 1; + break; + case MCPWM_TIMER_EVENT_FULL: + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 2; + break; + default: + HAL_ASSERT(false); + break; + } +} + +/** + * @brief Disable sync output for MCPWM timer + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + */ +static inline void mcpwm_ll_timer_disable_sync_out(mcpwm_dev_t *mcpwm, int timer_id) +{ + // sync_out will always be zero + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 3; +} + +/** + * @brief Trigger MCPWM timer software sync event + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + */ +static inline void mcpwm_ll_timer_trigger_soft_sync(mcpwm_dev_t *mcpwm, int timer_id) +{ + mcpwm->timer[timer_id].timer_sync.timer_sync_sw = ~mcpwm->timer[timer_id].timer_sync.timer_sync_sw; +} + +/** + * @brief Set sync count value for MCPWM timer + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param phase_value Sync phase value + */ +static inline void mcpwm_ll_timer_set_sync_phase_value(mcpwm_dev_t *mcpwm, int timer_id, uint32_t phase_value) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_sync, timer_phase, phase_value); +} + +/** + * @brief Set sync phase direction for MCPWM timer + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param direction Sync phase direction + */ +static inline void mcpwm_ll_timer_set_sync_phase_direction(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_direction_t direction) +{ + mcpwm->timer[timer_id].timer_sync.timer_phase_direction = direction; +} + +/** + * @brief Select which GPIO sync input to use + * + * @param mcpwm Peripheral instance address + * @param timer Timer ID, index from 0 to 2 + * @param gpio_sync_id GPIO sync ID, index from 0 to 2 + */ +static inline void mcpwm_ll_timer_set_gpio_sync_input(mcpwm_dev_t *mcpwm, int timer, int gpio_sync_id) +{ + mcpwm->timer_synci_cfg.val &= ~(0x07 << (timer * 3)); + mcpwm->timer_synci_cfg.val |= (gpio_sync_id + 4) << (timer * 3); +} + +/** + * @brief Select which timer sync input to use + * + * @param mcpwm Peripheral instance address + * @param timer Timer ID, index from 0 to 2 + * @param timer_sync_id Timer sync ID, index from 0 to 2 + */ +static inline void mcpwm_ll_timer_set_timer_sync_input(mcpwm_dev_t *mcpwm, int timer, int timer_sync_id) +{ + mcpwm->timer_synci_cfg.val &= ~(0x07 << (timer * 3)); + mcpwm->timer_synci_cfg.val |= (timer_sync_id + 1) << (timer * 3); +} + +/** + * @brief Clear timer sync input selection + * + * @param mcpwm Peripheral instance address + * @param timer Timer ID, index from 0 to 2 + */ +static inline void mcpwm_ll_timer_clear_sync_input(mcpwm_dev_t *mcpwm, int timer) +{ + // no sync input is selected, but software sync can still work + mcpwm->timer_synci_cfg.val &= ~(0x07 << (timer * 3)); +} + +/** + * @brief Invert the GPIO sync input signal + * + * @param mcpwm Peripheral instance address + * @param sync_id GPIO sync ID, index from 0 to 2 + * @param invert True to invert, False to not invert + */ +static inline void mcpwm_ll_invert_gpio_sync_input(mcpwm_dev_t *mcpwm, int sync_id, bool invert) +{ + if (invert) { + mcpwm->timer_synci_cfg.val |= 1 << (sync_id + 9); + } else { + mcpwm->timer_synci_cfg.val &= ~(1 << (sync_id + 9)); + } +} + +////////////////////////////////////////MCPWM Operator Specific///////////////////////////////////////////////////////// + +/** + * @brief Flush operator shadow registers to active registers + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + */ +static inline void mcpwm_ll_operator_flush_shadow(mcpwm_dev_t *mcpwm, int operator_id) +{ + mcpwm->update_cfg.val ^= (1 << (2 * operator_id + 3)); +} + +/** + * @brief Connect operator and timer by ID + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param timer_id Timer ID, index from 0 to 2 + */ +static inline void mcpwm_ll_operator_connect_timer(mcpwm_dev_t *mcpwm, int operator_id, int timer_id) +{ + mcpwm->operator_timersel.val &= ~(0x03 << (2 * operator_id)); + mcpwm->operator_timersel.val |= (timer_id << (2 * operator_id)); +} + +/** + * @brief Update the compare value immediately + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param compare_id Compare ID, index from 0 to 1 + */ +static inline void mcpwm_ll_operator_update_compare_at_once(mcpwm_dev_t *mcpwm, int operator_id, int compare_id) +{ + mcpwm->operators[operator_id].gen_stmp_cfg.val &= ~(0x0F << (4 * compare_id)); +} + +/** + * @brief Enable to update the compare value upon TEZ event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param compare_id Compare ID, index from 0 to 1 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_operator_enable_update_compare_on_tez(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].gen_stmp_cfg.val |= (1 << 0) << (4 * compare_id); + } else { + mcpwm->operators[operator_id].gen_stmp_cfg.val &= ~((1 << 0) << (4 * compare_id)); + } +} + +/** + * @brief Enable to update the compare value upon TEP event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param compare_id Compare ID, index from 0 to 1 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_operator_enable_update_compare_on_tep(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].gen_stmp_cfg.val |= (1 << 1) << (4 * compare_id); + } else { + mcpwm->operators[operator_id].gen_stmp_cfg.val &= ~((1 << 1) << (4 * compare_id)); + } +} + +/** + * @brief Enable to update the compare value upon sync event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param compare_id Compare ID, index from 0 to 1 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_operator_enable_update_compare_on_sync(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].gen_stmp_cfg.val |= (1 << 2) << (4 * compare_id); + } else { + mcpwm->operators[operator_id].gen_stmp_cfg.val &= ~((1 << 2) << (4 * compare_id)); + } +} + +/** + * @brief Stop updating the compare value + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param compare_id Compare ID, index from 0 to 1 + * @param stop_or_not True to stop, False to not stop + */ +static inline void mcpwm_ll_operator_stop_update_compare(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, bool stop_or_not) +{ + if (stop_or_not) { + mcpwm->operators[operator_id].gen_stmp_cfg.val |= (1 << 3) << (4 * compare_id); + } else { + mcpwm->operators[operator_id].gen_stmp_cfg.val &= ~((1 << 3) << (4 * compare_id)); + } +} + +/** + * @brief Set compare value for comparator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param compare_id Compare ID, index from 0 to 1 + * @param compare_value Compare value + */ +__attribute__((always_inline)) +static inline void mcpwm_ll_operator_set_compare_value(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, uint32_t compare_value) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->operators[operator_id].timestamp[compare_id], cmpr, compare_value); +} + +/** + * @brief Update operator actions immediately + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + */ +static inline void mcpwm_ll_operator_update_action_at_once(mcpwm_dev_t *mcpwm, int operator_id) +{ + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod = 0; +} + +/** + * @brief Enable update actions on TEZ event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_operator_enable_update_action_on_tez(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 << 0; + } else { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 << 0); + } +} + +/** + * @brief Enable update actions on TEP event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_operator_enable_update_action_on_tep(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 << 1; + } else { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 << 1); + } +} + +/** + * @brief Enable update actions on sync event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_operator_enable_update_action_on_sync(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 << 2; + } else { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 << 2); + } +} + +/** + * @brief Stop updating actions + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param stop_or_not True to stop, False to not stop + */ +static inline void mcpwm_ll_operator_stop_update_action(mcpwm_dev_t *mcpwm, int operator_id, bool stop_or_not) +{ + if (stop_or_not) { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 << 3; + } else { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 << 3); + } +} + +/** + * @brief Set trigger from GPIO (reuse the fault GPIO) + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param trig_id Trigger ID, index from 0 to 1 + * @param fault_gpio_id Fault GPIO ID, index from 0 to 3 + */ +static inline void mcpwm_ll_operator_set_trigger_from_gpio_fault(mcpwm_dev_t *mcpwm, int operator_id, int trig_id, int fault_gpio_id) +{ + mcpwm->operators[operator_id].gen_cfg0.val &= ~(0x07 << (4 + 3 * trig_id)); + mcpwm->operators[operator_id].gen_cfg0.val |= (fault_gpio_id << (4 + 3 * trig_id)); +} + +/** + * @brief Set trigger from sync event (when the timer/gpio/soft taken the sync signal) + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param trig_id Trigger ID, index from 0 to 1 + */ +static inline void mcpwm_ll_operator_set_trigger_from_sync(mcpwm_dev_t *mcpwm, int operator_id, int trig_id) +{ + // the timer here is not selectable, must be the one connected with the operator + mcpwm->operators[operator_id].gen_cfg0.val &= ~(0x07 << (4 + 3 * trig_id)); + mcpwm->operators[operator_id].gen_cfg0.val |= (3 << (4 + 3 * trig_id)); +} + +////////////////////////////////////////MCPWM Generator Specific//////////////////////////////////////////////////////// + +/** + * @brief Reset actions for the generator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + */ +static inline void mcpwm_ll_generator_reset_actions(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) +{ + mcpwm->operators[operator_id].generator[generator_id].val = 0; +} + +/** + * @brief Set generator action on timer event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + * @param direction Timer direction + * @param event Timer event + * @param action Action to set + */ +static inline void mcpwm_ll_generator_set_action_on_timer_event(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, + mcpwm_timer_direction_t direction, mcpwm_timer_event_t event, mcpwm_generator_action_t action) +{ + // empty: 0, full: 1 + if (direction == MCPWM_TIMER_DIRECTION_UP) { // utez, utep + mcpwm->operators[operator_id].generator[generator_id].val &= ~(0x03 << (MCPWM_LL_TIMER_EVENT_TO_REG_VAL(event) * 2)); + mcpwm->operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (MCPWM_LL_TIMER_EVENT_TO_REG_VAL(event) * 2); + } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { // dtez, dtep + mcpwm->operators[operator_id].generator[generator_id].val &= ~(0x03 << (MCPWM_LL_TIMER_EVENT_TO_REG_VAL(event) * 2 + 12)); + mcpwm->operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (MCPWM_LL_TIMER_EVENT_TO_REG_VAL(event) * 2 + 12); + } +} + +/** + * @brief Set generator action on compare event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + * @param direction Timer direction + * @param comp_id Compare ID, index from 0 to 1 + * @param action Action to set + */ +static inline void mcpwm_ll_generator_set_action_on_compare_event(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, + mcpwm_timer_direction_t direction, int cmp_id, int action) +{ + if (direction == MCPWM_TIMER_DIRECTION_UP) { // utea, uteb + mcpwm->operators[operator_id].generator[generator_id].val &= ~(0x03 << (cmp_id * 2 + 4)); + mcpwm->operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (cmp_id * 2 + 4); + } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { // dtea, dteb + mcpwm->operators[operator_id].generator[generator_id].val &= ~(0x03 << (cmp_id * 2 + 16)); + mcpwm->operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (cmp_id * 2 + 16); + } +} + +/** + * @brief Set generator action on trigger event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + * @param direction Timer direction + * @param trig_id Trigger ID, index from 0 to 1 + * @param action Action to set + */ +static inline void mcpwm_ll_generator_set_action_on_trigger_event(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, + mcpwm_timer_direction_t direction, int trig_id, int action) +{ + if (direction == MCPWM_TIMER_DIRECTION_UP) { // ut0, ut1 + mcpwm->operators[operator_id].generator[generator_id].val &= ~(0x03 << (trig_id * 2 + 8)); + mcpwm->operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (trig_id * 2 + 8); + } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { // dt0, dt1 + mcpwm->operators[operator_id].generator[generator_id].val &= ~(0x03 << (trig_id * 2 + 20)); + mcpwm->operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (trig_id * 2 + 20); + } +} + +/** + * @brief Set generator action on brake event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + * @param direction Timer direction + * @param brake_mode Brake mode + * @param action Action to set + */ +static inline void mcpwm_ll_generator_set_action_on_brake_event(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, + mcpwm_timer_direction_t direction, mcpwm_operator_brake_mode_t brake_mode, int action) +{ + // the following bit operation is highly depend on the register bit layout. + // the priority comes: generator ID > brake mode > direction + if (direction == MCPWM_TIMER_DIRECTION_UP) { + mcpwm->operators[operator_id].fh_cfg0.val &= ~(0x03 << (8 + 8 * generator_id + 4 * MCPWM_LL_BRAKE_MODE_TO_REG_VAL(brake_mode) + 2)); + mcpwm->operators[operator_id].fh_cfg0.val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (8 + 8 * generator_id + 4 * MCPWM_LL_BRAKE_MODE_TO_REG_VAL(brake_mode) + 2); + } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { + mcpwm->operators[operator_id].fh_cfg0.val &= ~(0x03 << (8 + 8 * generator_id + 4 * MCPWM_LL_BRAKE_MODE_TO_REG_VAL(brake_mode))); + mcpwm->operators[operator_id].fh_cfg0.val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (8 + 8 * generator_id + 4 * MCPWM_LL_BRAKE_MODE_TO_REG_VAL(brake_mode)); + } +} + +/** + * @brief Trigger non-continue forced action for generator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + */ +static inline void mcpwm_ll_gen_trigger_noncontinue_force_action(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) +{ + if (generator_id == 0) { + mcpwm->operators[operator_id].gen_force.gen_a_nciforce = ~mcpwm->operators[operator_id].gen_force.gen_a_nciforce; + } else { + mcpwm->operators[operator_id].gen_force.gen_b_nciforce = ~mcpwm->operators[operator_id].gen_force.gen_b_nciforce; + } +} + +/** + * @brief Disable continue forced action for generator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + */ +static inline void mcpwm_ll_gen_disable_continue_force_action(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) +{ + mcpwm->operators[operator_id].gen_force.gen_cntuforce_upmethod = 0; // update force method immediately + if (generator_id == 0) { + mcpwm->operators[operator_id].gen_force.gen_a_cntuforce_mode = 0; + } else { + mcpwm->operators[operator_id].gen_force.gen_b_cntuforce_mode = 0; + } +} + +/** + * @brief Disable non-continue forced action for generator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + */ +static inline void mcpwm_ll_gen_disable_noncontinue_force_action(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) +{ + if (generator_id == 0) { + mcpwm->operators[operator_id].gen_force.gen_a_nciforce_mode = 0; + } else { + mcpwm->operators[operator_id].gen_force.gen_b_nciforce_mode = 0; + } +} + +/** + * @brief Set continue force level for generator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + * @param level Force level to set + */ +static inline void mcpwm_ll_gen_set_continue_force_level(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, int level) +{ + mcpwm->operators[operator_id].gen_force.gen_cntuforce_upmethod = 0; // update force method immediately + if (generator_id == 0) { + mcpwm->operators[operator_id].gen_force.gen_a_cntuforce_mode = level + 1; + } else { + mcpwm->operators[operator_id].gen_force.gen_b_cntuforce_mode = level + 1; + } +} + +/** + * @brief Set non-continue force level for generator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + * @param level Force level to set + */ +static inline void mcpwm_ll_gen_set_noncontinue_force_level(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, int level) +{ + if (generator_id == 0) { + mcpwm->operators[operator_id].gen_force.gen_a_nciforce_mode = level + 1; + } else { + mcpwm->operators[operator_id].gen_force.gen_b_nciforce_mode = level + 1; + } +} + +////////////////////////////////////////MCPWM Dead Time Specific//////////////////////////////////////////////////////// + +/** + * @brief Set clock source for dead time submodule + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param src Clock source for dead time submodule + */ +static inline void mcpwm_ll_operator_set_deadtime_clock_src(mcpwm_dev_t *mcpwm, int operator_id, mcpwm_ll_deadtime_clock_src_t src) +{ + switch (src) { + case MCPWM_LL_DEADTIME_CLK_SRC_GROUP: + mcpwm->operators[operator_id].dt_cfg.db_clk_sel = 0; + break; + case MCPWM_LL_DEADTIME_CLK_SRC_TIMER: + mcpwm->operators[operator_id].dt_cfg.db_clk_sel = 1; + break; + default: + HAL_ASSERT(false); + } +} + +/** + * @brief Select the generator for RED block + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator Generator ID, index from 0 to 1 + */ +static inline void mcpwm_ll_deadtime_red_select_generator(mcpwm_dev_t *mcpwm, int operator_id, int generator) +{ + mcpwm->operators[operator_id].dt_cfg.db_red_insel = generator; +} + +/** + * @brief Select the generator for FED block + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator Generator ID, index from 0 to 1 + */ +static inline void mcpwm_ll_deadtime_fed_select_generator(mcpwm_dev_t *mcpwm, int operator_id, int generator) +{ + mcpwm->operators[operator_id].dt_cfg.db_fed_insel = generator; +} + +/** + * @brief Set which path to bypass in the deadtime submodule + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param path Path to bypass, index from 0 to 1 + * @param bypass True to bypass, False to not bypass + */ +static inline void mcpwm_ll_deadtime_bypass_path(mcpwm_dev_t *mcpwm, int operator_id, int path, bool bypass) +{ + if (bypass) { + mcpwm->operators[operator_id].dt_cfg.val |= 1 << (path + 15); + } else { + mcpwm->operators[operator_id].dt_cfg.val &= ~(1 << (path + 15)); + } +} + +/** + * @brief Invert the output path + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param path Path to invert, index from 0 to 1 + * @param invert True to invert, False to not invert + */ +static inline void mcpwm_ll_deadtime_invert_outpath(mcpwm_dev_t *mcpwm, int operator_id, int path, bool invert) +{ + if (invert) { + mcpwm->operators[operator_id].dt_cfg.val |= 1 << (path + 13); + } else { + mcpwm->operators[operator_id].dt_cfg.val &= ~(1 << (path + 13)); + } +} + +/** + * @brief Swap the output path + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param path Path to swap, index from 0 to 1 + * @param swap True to swap, False to not swap + */ +static inline void mcpwm_ll_deadtime_swap_out_path(mcpwm_dev_t *mcpwm, int operator_id, int path, bool swap) +{ + if (swap) { + mcpwm->operators[operator_id].dt_cfg.val |= 1 << (path + 9); + } else { + mcpwm->operators[operator_id].dt_cfg.val &= ~(1 << (path + 9)); + } +} + +/** + * @brief Enable the DEB block + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_deadtime_enable_deb(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + mcpwm->operators[operator_id].dt_cfg.db_deb_mode = enable; +} + +/** + * @brief Get the deadtime switch topology + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @return Dead time submodule's switch topology, each bit represents one switch on/off status + */ +static inline uint32_t mcpwm_ll_deadtime_get_switch_topology(mcpwm_dev_t *mcpwm, int operator_id) +{ + return (mcpwm->operators[operator_id].dt_cfg.db_deb_mode << 8) | (mcpwm->operators[operator_id].dt_cfg.db_b_outswap << 7) | + (mcpwm->operators[operator_id].dt_cfg.db_a_outswap << 6) | (mcpwm->operators[operator_id].dt_cfg.db_fed_insel << 5) | + (mcpwm->operators[operator_id].dt_cfg.db_red_insel << 4) | (mcpwm->operators[operator_id].dt_cfg.db_fed_outinvert << 3) | + (mcpwm->operators[operator_id].dt_cfg.db_red_outinvert << 2) | (mcpwm->operators[operator_id].dt_cfg.db_a_outbypass << 1) | + (mcpwm->operators[operator_id].dt_cfg.db_b_outbypass << 0); +} + +/** + * @brief Set falling edge delay duration + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param fed Delay duration, in deadtime submodule's clock cycles + */ +static inline void mcpwm_ll_deadtime_set_falling_delay(mcpwm_dev_t *mcpwm, int operator_id, uint32_t fed) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->operators[operator_id].dt_fed_cfg, db_fed, fed - 1); +} + +/** + * @brief Set rising edge delay duration + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param red Delay duration, in deadtime submodule's clock cycles + */ +static inline void mcpwm_ll_deadtime_set_rising_delay(mcpwm_dev_t *mcpwm, int operator_id, uint32_t red) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->operators[operator_id].dt_red_cfg, db_red, red - 1); +} + +/** + * @brief Update deadtime immediately + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + */ +static inline void mcpwm_ll_deadtime_update_delay_at_once(mcpwm_dev_t *mcpwm, int operator_id) +{ + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod = 0; + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod = 0; +} + +/** + * @brief Enable to update deadtime on TEZ event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_deadtime_enable_update_delay_on_tez(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod |= 1 << 0; + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod |= 1 << 0; + } else { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod &= ~(1 << 0); + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod &= ~(1 << 0); + } +} + +/** + * @brief Enable to update deadtime on TEP event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_deadtime_enable_update_delay_on_tep(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod |= 1 << 1; + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod |= 1 << 1; + } else { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod &= ~(1 << 1); + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod &= ~(1 << 1); + } +} + +/** + * @brief Enable to update deadtime on sync event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_deadtime_enable_update_delay_on_sync(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod |= 1 << 2; + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod |= 1 << 2; + } else { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod &= ~(1 << 2); + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod &= ~(1 << 2); + } +} + +/** + * @brief Stop updating deadtime + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param stop_or_not True to stop, False to continue + */ +static inline void mcpwm_ll_deadtime_stop_update_delay(mcpwm_dev_t *mcpwm, int operator_id, bool stop_or_not) +{ + if (stop_or_not) { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod |= 1 << 3; + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod |= 1 << 3; + } else { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod &= ~(1 << 3); + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod &= ~(1 << 3); + } +} + +////////////////////////////////////////MCPWM Carrier Specific////////////////////////////////////////////////////////// + +/** + * @brief Enable carrier for MCPWM operator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_carrier_enable(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + mcpwm->operators[operator_id].carrier_cfg.chopper_en = enable; +} + +/** + * @brief Set prescale for MCPWM carrier source clock + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param prescale Prescale value + */ +static inline void mcpwm_ll_carrier_set_prescale(mcpwm_dev_t *mcpwm, int operator_id, uint8_t prescale) +{ + HAL_ASSERT(prescale > 0 && prescale <= 16); + mcpwm->operators[operator_id].carrier_cfg.chopper_prescale = prescale - 1; +} + +/** + * @brief Set duty cycle of MCPWM carrier + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param carrier_duty Duty cycle value + */ +static inline void mcpwm_ll_carrier_set_duty(mcpwm_dev_t *mcpwm, int operator_id, uint8_t carrier_duty) +{ + mcpwm->operators[operator_id].carrier_cfg.chopper_duty = carrier_duty; +} + +/** + * @brief Invert the signal after the carrier is applied + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param invert True to invert, False to not invert + */ +static inline void mcpwm_ll_carrier_out_invert(mcpwm_dev_t *mcpwm, int operator_id, bool invert) +{ + mcpwm->operators[operator_id].carrier_cfg.chopper_out_invert = invert; +} + +/** + * @brief Invert the signal before applying the carrier + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param invert True to invert, False to not invert + */ +static inline void mcpwm_ll_carrier_in_invert(mcpwm_dev_t *mcpwm, int operator_id, bool invert) +{ + mcpwm->operators[operator_id].carrier_cfg.chopper_in_invert = invert; +} + +/** + * @brief Set the first pulse width of the carrier + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param pulse_width Pulse width + */ +static inline void mcpwm_ll_carrier_set_first_pulse_width(mcpwm_dev_t *mcpwm, int operator_id, uint8_t pulse_width) +{ + HAL_ASSERT(pulse_width >= 1); + mcpwm->operators[operator_id].carrier_cfg.chopper_oshtwth = pulse_width - 1; +} + +////////////////////////////////////////MCPWM Fault Specific//////////////////////////////////////////////////////////// + +/** + * @brief Enable GPIO fault detection + * + * @param mcpwm Peripheral instance address + * @param fault_sig GPIO fault ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_fault_enable_detection(mcpwm_dev_t *mcpwm, int fault_sig, bool enable) +{ + if (enable) { + mcpwm->fault_detect.val |= 1 << fault_sig; + } else { + mcpwm->fault_detect.val &= ~(1 << fault_sig); + } +} + +/** + * @brief Set fault polarity (i.e. which level is treated as an active fault) + * + * @param mcpwm Peripheral instance address + * @param fault_sig GPIO fault ID, index from 0 to 2 + * @param level Active level, 0 for low, 1 for high + */ +static inline void mcpwm_ll_fault_set_active_level(mcpwm_dev_t *mcpwm, int fault_sig, bool level) +{ + if (level) { + mcpwm->fault_detect.val |= 1 << (fault_sig + 3); + } else { + mcpwm->fault_detect.val &= ~(1 << (fault_sig + 3)); + } +} + +/** + * @brief Clear the OST brake + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + */ +static inline void mcpwm_ll_brake_clear_ost(mcpwm_dev_t *mcpwm, int operator_id) +{ + // a posedge can clear the ost fault status + mcpwm->operators[operator_id].fh_cfg1.tz_clr_ost = 0; + mcpwm->operators[operator_id].fh_cfg1.tz_clr_ost = 1; +} + +/** + * @brief Enable the OST brake + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param fault_sig GPIO fault ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_brake_enable_oneshot_mode(mcpwm_dev_t *mcpwm, int operator_id, int fault_sig, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].fh_cfg0.val |= (1 << (7 - fault_sig)); + } else { + mcpwm->operators[operator_id].fh_cfg0.val &= ~(1 << (7 - fault_sig)); + } +} + +/** + * @brief Enable the CBC brake + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param fault_sig GPIO fault ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_brake_enable_cbc_mode(mcpwm_dev_t *mcpwm, int operator_id, int fault_sig, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].fh_cfg0.val |= (enable << (3 - fault_sig)); + } else { + mcpwm->operators[operator_id].fh_cfg0.val &= ~(1 << (3 - fault_sig)); + } +} + +/** + * @brief Enable refresh the CBC brake on TEZ event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_brake_enable_cbc_refresh_on_tez(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].fh_cfg1.val |= 1 << 1; + } else { + mcpwm->operators[operator_id].fh_cfg1.val &= ~(1 << 1); + } +} + +/** + * @brief Enable refresh the CBC brake on TEP event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_fault_enable_cbc_refresh_on_tep(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].fh_cfg1.val |= 1 << 2; + } else { + mcpwm->operators[operator_id].fh_cfg1.val &= ~(1 << 2); + } +} + +/** + * @brief Enable software CBC brake + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_brake_enable_soft_cbc(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + mcpwm->operators[operator_id].fh_cfg0.tz_sw_cbc = enable; +} + +/** + * @brief Enable software OST brake + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_brake_enable_soft_ost(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + mcpwm->operators[operator_id].fh_cfg0.tz_sw_ost = enable; +} + +/** + * @brief Trigger software CBC brake for once + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + */ +static inline void mcpwm_ll_brake_trigger_soft_cbc(mcpwm_dev_t *mcpwm, int operator_id) +{ + mcpwm->operators[operator_id].fh_cfg1.tz_force_cbc = ~mcpwm->operators[operator_id].fh_cfg1.tz_force_cbc; +} + +/** + * @brief Trigger software OST brake for once + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + */ +static inline void mcpwm_ll_brake_trigger_soft_ost(mcpwm_dev_t *mcpwm, int operator_id) +{ + mcpwm->operators[operator_id].fh_cfg1.tz_force_ost = ~mcpwm->operators[operator_id].fh_cfg1.tz_force_ost; +} + +/** + * @brief Whether the OST brake is still active + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @return True if active, False if not + */ +static inline bool mcpwm_ll_ost_brake_active(mcpwm_dev_t *mcpwm, int operator_id) +{ + return mcpwm->operators[operator_id].fh_status.tz_ost_on; +} + +/** + * @brief Whether the CBC brake is still active + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @return True if active, False if not + */ +static inline bool mcpwm_ll_cbc_brake_active(mcpwm_dev_t *mcpwm, int operator_id) +{ + return mcpwm->operators[operator_id].fh_status.tz_cbc_on; +} + +////////////////////////////////////////MCPWM Capture Specific////////////////////////////////////////////////////////// + +/** + * @brief Enable capture timer + * + * @param mcpwm Peripheral instance address + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_capture_enable_timer(mcpwm_dev_t *mcpwm, bool enable) +{ + mcpwm->cap_timer_cfg.cap_timer_en = enable; +} + +/** + * @brief Enable capture channel + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_capture_enable_channel(mcpwm_dev_t *mcpwm, int channel, bool enable) +{ + mcpwm->cap_chn_cfg[channel].capn_en = enable; +} + +/** + * @brief Set sync phase for capture timer + * + * @param mcpwm Peripheral instance address + * @param phase_value Phase value + */ +static inline void mcpwm_ll_capture_set_sync_phase_value(mcpwm_dev_t *mcpwm, uint32_t phase_value) +{ + mcpwm->cap_timer_phase.cap_phase = phase_value; +} + +/** + * @brief Enable sync for capture timer + * + * @param mcpwm Peripheral instance address + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_capture_enable_timer_sync(mcpwm_dev_t *mcpwm, bool enable) +{ + mcpwm->cap_timer_cfg.cap_synci_en = enable; +} + +/** + * @brief Set the timer sync source for MCPWM capture timer + * + * @param mcpwm Peripheral instance address + * @param sync_out_timer MCPWM Timer ID, index from 0 to 2 + */ +static inline void mcpwm_ll_capture_set_timer_sync(mcpwm_dev_t *mcpwm, int sync_out_timer) +{ + mcpwm->cap_timer_cfg.cap_synci_sel = sync_out_timer + 1; +} + +/** + * @brief Set the GPIO sync source for MCPWM capture timer + * + * @param mcpwm Peripheral instance address + * @param gpio_sync GPIO sync ID, index from 0 to 2 + */ +static inline void mcpwm_ll_capture_set_gpio_sync(mcpwm_dev_t *mcpwm, int gpio_sync) +{ + mcpwm->cap_timer_cfg.cap_synci_sel = gpio_sync + 4; +} + +/** + * @brief Trigger a software sync for capture timer + * + * @param mcpwm Peripheral instance address + */ +static inline void mcpwm_ll_capture_trigger_sw_sync(mcpwm_dev_t *mcpwm) +{ + mcpwm->cap_timer_cfg.cap_sync_sw = 1; // auto clear +} + +/** + * @brief Enable capture on positive edge + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_capture_enable_posedge(mcpwm_dev_t *mcpwm, int channel, bool enable) +{ + if (enable) { + mcpwm->cap_chn_cfg[channel].val |= 1 << 2; + } else { + mcpwm->cap_chn_cfg[channel].val &= ~(1 << 2); + } +} + +/** + * @brief Enable capture on negative edge + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_capture_enable_negedge(mcpwm_dev_t *mcpwm, int channel, bool enable) +{ + if (enable) { + mcpwm->cap_chn_cfg[channel].val |= 1 << 1; + } else { + mcpwm->cap_chn_cfg[channel].val &= ~(1 << 1); + } +} + +/** + * @brief Invert the capture input signal + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + * @param invert True to invert, False to not invert + */ +static inline void mcpwm_ll_invert_input(mcpwm_dev_t *mcpwm, int channel, bool invert) +{ + mcpwm->cap_chn_cfg[channel].capn_in_invert = invert; +} + +/** + * @brief Trigger the software capture for once + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + */ +static inline void mcpwm_ll_trigger_soft_capture(mcpwm_dev_t *mcpwm, int channel) +{ + mcpwm->cap_chn_cfg[channel].capn_sw = 1; // auto clear +} + +/** + * @brief Get the captured value + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + * @return Captured value + */ +__attribute__((always_inline)) +static inline uint32_t mcpwm_ll_capture_get_value(mcpwm_dev_t *mcpwm, int channel) +{ + return mcpwm->cap_chn[channel].capn_value; +} + +/** + * @brief Get the captured edge + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + * @return Captured edge + */ +__attribute__((always_inline)) +static inline mcpwm_capture_edge_t mcpwm_ll_capture_get_edge(mcpwm_dev_t *mcpwm, int channel) +{ + return mcpwm->cap_status.val & (1 << channel) ? MCPWM_CAP_EDGE_NEG : MCPWM_CAP_EDGE_POS; +} + +/** + * @brief Set the prescale of the input capture signal + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + * @param prescale Prescale value + */ +static inline void mcpwm_ll_capture_set_prescale(mcpwm_dev_t *mcpwm, int channel, uint32_t prescale) +{ + HAL_ASSERT(prescale > 0); + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->cap_chn_cfg[channel], capn_prescale, prescale - 1); +} + +//////////////////////////////////////////MCPWM ETM Specific//////////////////////////////////////////////////////////// + +/** + * @brief Enable comparator ETM event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param cmpr_id Comparator ID, index from 0 to 2 + * @param en True: enable ETM module, False: disable ETM module + */ +static inline void mcpwm_ll_etm_enable_comparator_event(mcpwm_dev_t *mcpwm, int operator_id, int cmpr_id, bool en) +{ + if (en) { + mcpwm->evt_en.val |= 1 << (operator_id + 3 * cmpr_id + 9) ; + } else { + mcpwm->evt_en.val &= ~(1 << (operator_id + 3 * cmpr_id + 9)) ; + } +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_mcpwm/esp32h21/mcpwm_periph.c b/components/esp_hal_mcpwm/esp32h21/mcpwm_periph.c new file mode 100644 index 0000000000..bc8154d933 --- /dev/null +++ b/components/esp_hal_mcpwm/esp32h21/mcpwm_periph.c @@ -0,0 +1,129 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "hal/mcpwm_periph.h" +#include "soc/mcpwm_reg.h" +#include "soc/gpio_sig_map.h" + +const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = { + { + .module_name = "MCPWM0", + .irq_id = ETS_PWM_INTR_SOURCE, + .operators = { + [0] = { + .generators = { + [0] = { + .pwm_sig = PWM0_OUT0A_IDX + }, + [1] = { + .pwm_sig = PWM0_OUT0B_IDX + } + } + }, + [1] = { + .generators = { + [0] = { + .pwm_sig = PWM0_OUT1A_IDX + }, + [1] = { + .pwm_sig = PWM0_OUT1B_IDX + } + } + }, + [2] = { + .generators = { + [0] = { + .pwm_sig = PWM0_OUT2A_IDX + }, + [1] = { + .pwm_sig = PWM0_OUT2B_IDX + } + } + } + }, + .gpio_faults = { + [0] = { + .fault_sig = PWM0_F0_IN_IDX + }, + [1] = { + .fault_sig = PWM0_F1_IN_IDX + }, + [2] = { + .fault_sig = PWM0_F2_IN_IDX + } + }, + .captures = { + [0] = { + .cap_sig = PWM0_CAP0_IN_IDX + }, + [1] = { + .cap_sig = PWM0_CAP1_IN_IDX + }, + [2] = { + .cap_sig = PWM0_CAP2_IN_IDX + } + }, + .gpio_synchros = { + [0] = { + .sync_sig = PWM0_SYNC0_IN_IDX + }, + [1] = { + .sync_sig = PWM0_SYNC1_IN_IDX + }, + [2] = { + .sync_sig = PWM0_SYNC2_IN_IDX + } + } + } +}; + +/** + * MCPWM Registers to be saved during sleep retention + * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG + * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG + * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG + * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG + * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG + * â””- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG + * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG + * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG + * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG + * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG +*/ +#define MCPWM_RETENTION_REGS_CNT 60 +#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4) +static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x18c, 0x0}; +static const regdma_entries_config_t mcpwm_regs_retention[] = { + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), + MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE, + MCPWM_RETENTION_REGS_CNT, 0, 0, + mcpwm_regs_map[0], mcpwm_regs_map[1], + mcpwm_regs_map[2], mcpwm_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a forced update of all active registers + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), + MCPWM_UPDATE_CFG_REG, MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), + MCPWM_UPDATE_CFG_REG, 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[1] = { + [0] = { + .regdma_entry_array = mcpwm_regs_retention, + .array_size = ARRAY_SIZE(mcpwm_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 + }, +}; diff --git a/components/esp_hal_mcpwm/esp32h4/include/hal/mcpwm_ll.h b/components/esp_hal_mcpwm/esp32h4/include/hal/mcpwm_ll.h index ec0f1ba5a2..649b5d5369 100644 --- a/components/esp_hal_mcpwm/esp32h4/include/hal/mcpwm_ll.h +++ b/components/esp_hal_mcpwm/esp32h4/include/hal/mcpwm_ll.h @@ -28,7 +28,7 @@ extern "C" { #define MCPWM_LL_GET_HW(ID) (((ID) == 0) ? &MCPWM0 : &MCPWM1) // MCPWM capabilities -#define MCPWM_LL_GROUP_NUM (2U) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) +#define MCPWM_LL_GROUP_NUM (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) #define MCPWM_LL_TIMERS_PER_GROUP (3) ///< The number of timers that each group has #define MCPWM_LL_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has #define MCPWM_LL_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has diff --git a/components/esp_hal_mcpwm/esp32p4/include/hal/mcpwm_ll.h b/components/esp_hal_mcpwm/esp32p4/include/hal/mcpwm_ll.h index 311ae07d60..3c1888bbe2 100644 --- a/components/esp_hal_mcpwm/esp32p4/include/hal/mcpwm_ll.h +++ b/components/esp_hal_mcpwm/esp32p4/include/hal/mcpwm_ll.h @@ -4,12 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -/******************************************************************************* - * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in hal/include/hal/readme.md - ******************************************************************************/ - // The LL layer for ESP32-P4 MCPWM register operations #pragma once @@ -36,7 +30,7 @@ extern "C" { #define MCPWM_LL_GET_HW(ID) (((ID) == 0) ? &MCPWM0 : &MCPWM1) // MCPWM capabilities -#define MCPWM_LL_GROUP_NUM (2U) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) +#define MCPWM_LL_GROUP_NUM (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) #define MCPWM_LL_TIMERS_PER_GROUP (3) ///< The number of timers that each group has #define MCPWM_LL_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has #define MCPWM_LL_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has diff --git a/components/esp_hal_mcpwm/esp32s3/include/hal/mcpwm_ll.h b/components/esp_hal_mcpwm/esp32s3/include/hal/mcpwm_ll.h index e08bb71630..1eb8f926fb 100644 --- a/components/esp_hal_mcpwm/esp32s3/include/hal/mcpwm_ll.h +++ b/components/esp_hal_mcpwm/esp32s3/include/hal/mcpwm_ll.h @@ -4,12 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -/******************************************************************************* - * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in hal/include/hal/readme.md - ******************************************************************************/ - // The LL layer for ESP32-S3 MCPWM register operations #pragma once diff --git a/components/esp_hal_mcpwm/include/hal/mcpwm_hal.h b/components/esp_hal_mcpwm/include/hal/mcpwm_hal.h index 752603a568..1b9565bbdd 100644 --- a/components/esp_hal_mcpwm/include/hal/mcpwm_hal.h +++ b/components/esp_hal_mcpwm/include/hal/mcpwm_hal.h @@ -7,7 +7,7 @@ /******************************************************************************* * NOTICE * The hal is not public api, don't use in application code. - * See readme.md in hal/include/hal/readme.md + * See readme.md in esp_hal_mcpwm/readme.md ******************************************************************************/ #pragma once diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index ce5d5d21f9..273caa365e 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -143,6 +143,10 @@ config SOC_PCNT_SUPPORTED bool default y +config SOC_MCPWM_SUPPORTED + bool + default y + config SOC_TWAI_SUPPORTED bool default y @@ -643,6 +647,22 @@ config SOC_RMT_SUPPORT_SLEEP_RETENTION bool default y +config SOC_MCPWM_SWSYNC_CAN_PROPAGATE + bool + default y + +config SOC_MCPWM_SUPPORT_ETM + bool + default y + +config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP + bool + default y + +config SOC_MCPWM_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_MPI_MEM_BLOCKS_NUM int default 4 diff --git a/components/soc/esp32h21/include/soc/clk_tree_defs.h b/components/soc/esp32h21/include/soc/clk_tree_defs.h index f756d84d1a..ef2b80a2b4 100644 --- a/components/soc/esp32h21/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h21/include/soc/clk_tree_defs.h @@ -277,6 +277,50 @@ typedef enum { #endif } soc_periph_uart_clk_src_legacy_t; +//////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of MCPWM Timer + */ +#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM timer clock source + */ +typedef enum { + MCPWM_TIMER_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */ + MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */ +} soc_periph_mcpwm_timer_clk_src_t; + +/** + * @brief Array initializer for all supported clock sources of MCPWM Capture Timer + */ +#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM capture clock source + */ +typedef enum { + MCPWM_CAPTURE_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */ + MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */ +} soc_periph_mcpwm_capture_clk_src_t; + +/** + * @brief Array initializer for all supported clock sources of MCPWM Carrier + */ +#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM carrier clock source + */ +typedef enum { + MCPWM_CARRIER_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */ + MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */ +} soc_periph_mcpwm_carrier_clk_src_t; + /////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 903cfc69f2..0d957f97be 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -73,7 +73,7 @@ #define SOC_REG_I2C_SUPPORTED 1 // #define SOC_PHY_SUPPORTED 1 #define SOC_PCNT_SUPPORTED 1 -// #define SOC_MCPWM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11601 +#define SOC_MCPWM_SUPPORTED 1 #define SOC_TWAI_SUPPORTED 1 #define SOC_ETM_SUPPORTED 1 // #define SOC_PARLIO_SUPPORTED 1 //TODO: [ESP32H21] IDF-11570, IDF-11572 @@ -317,19 +317,11 @@ #define SOC_RMT_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up RMT registers before sleep */ /*-------------------------- MCPWM CAPS --------------------------------------*/ -// #define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) -// #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has -// #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has -// #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has -// #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has -// #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has -// #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has -// #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has -// #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has -// #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has -// #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output -// #define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix) -// #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers + +#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output +#define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix) +#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers +#define SOC_MCPWM_SUPPORT_SLEEP_RETENTION (1) ///< Support back up registers before sleep /*------------------------ USB SERIAL JTAG CAPS ------------------------------*/ // #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395 diff --git a/components/soc/esp32h21/register/soc/mcpwm_struct.h b/components/soc/esp32h21/register/soc/mcpwm_struct.h index a6d6b7cb6d..d0048cfd8c 100644 --- a/components/soc/esp32h21/register/soc/mcpwm_struct.h +++ b/components/soc/esp32h21/register/soc/mcpwm_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -26,295 +26,101 @@ typedef union { } mcpwm_clk_cfg_reg_t; -/** Group: MCPWM Timer 0 Configuration and status */ -/** Type of timer0_cfg0 register - * PWM timer0 period and update method configuration register. +/** Group: MCPWM Timer Configuration and status */ +/** Type of timer_cfg0 register + * PWM timer period and update method configuration register. */ typedef union { struct { - /** timer0_prescale : R/W; bitpos: [7:0]; default: 0; - * period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) + /** timer_prescale : R/W; bitpos: [7:0]; default: 0; + * period of PT0_clk = Period of PWM_clk * (PWM_TIMER_PRESCALE + 1) */ - uint32_t timer0_prescale:8; - /** timer0_period : R/W; bitpos: [23:8]; default: 255; - * period shadow register of PWM timer0 + uint32_t timer_prescale:8; + /** timer_period : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer */ - uint32_t timer0_period:16; - /** timer0_period_upmethod : R/W; bitpos: [25:24]; default: 0; - * Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: + uint32_t timer_period:16; + /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer period, 0: immediate, 1: TEZ, 2: * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event */ - uint32_t timer0_period_upmethod:2; + uint32_t timer_period_upmethod:2; uint32_t reserved_26:6; }; uint32_t val; -} mcpwm_timer0_cfg0_reg_t; +} mcpwm_timer_cfg0_reg_t; -/** Type of timer0_cfg1 register +/** Type of timer_cfg1 register * PWM timer0 working mode and start/stop control configuration register. */ typedef union { struct { - /** timer0_start : R/W/SC; bitpos: [2:0]; default: 0; - * PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: - * if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 - * starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP + /** timer_start : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer start and stop control. 0: if PWM timer starts, then stops at TEZ, 1: + * if timer0 starts, then stops at TEP, 2: PWM timer starts and runs on, 3: timer + * starts and stops at the next TEZ, 4: timer starts and stops at the next TEP. TEP * here and below means the event that happens when the timer equals to period */ - uint32_t timer0_start:3; - /** timer0_mod : R/W; bitpos: [4:3]; default: 0; - * PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + uint32_t timer_start:3; + /** timer_mod : R/W; bitpos: [4:3]; default: 0; + * PWM timer working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down * mode */ - uint32_t timer0_mod:2; + uint32_t timer_mod:2; uint32_t reserved_5:27; }; uint32_t val; -} mcpwm_timer0_cfg1_reg_t; +} mcpwm_timer_cfg1_reg_t; -/** Type of timer0_sync register - * PWM timer0 sync function configuration register. +/** Type of timer_sync register + * PWM timer sync function configuration register. */ typedef union { struct { - /** timer0_synci_en : R/W; bitpos: [0]; default: 0; + /** timer_synci_en : R/W; bitpos: [0]; default: 0; * When set, timer reloading with phase on sync input event is enabled. */ - uint32_t timer0_synci_en:1; - /** timer0_sync_sw : R/W; bitpos: [1]; default: 0; + uint32_t timer_synci_en:1; + /** timer_sync_sw : R/W; bitpos: [1]; default: 0; * Toggling this bit will trigger a software sync. */ - uint32_t timer0_sync_sw:1; - /** timer0_synco_sel : R/W; bitpos: [3:2]; default: 0; - * PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + uint32_t timer_sync_sw:1; + /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0; + * PWM timer sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always * generate when toggling the reg_timer0_sync_sw bit */ - uint32_t timer0_synco_sel:2; - /** timer0_phase : R/W; bitpos: [19:4]; default: 0; + uint32_t timer_synco_sel:2; + /** timer_phase : R/W; bitpos: [19:4]; default: 0; * phase for timer reload on sync event */ - uint32_t timer0_phase:16; - /** timer0_phase_direction : R/W; bitpos: [20]; default: 0; - * Configure the PWM timer0's direction when timer0 mode is up-down mode: + uint32_t timer_phase:16; + /** timer_phase_direction : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer0's direction when timer mode is up-down mode: * 0-increase,1-decrease */ - uint32_t timer0_phase_direction:1; + uint32_t timer_phase_direction:1; uint32_t reserved_21:11; }; uint32_t val; -} mcpwm_timer0_sync_reg_t; +} mcpwm_timer_sync_reg_t; -/** Type of timer0_status register - * PWM timer0 status register. +/** Type of timer_status register + * PWM timer status register. */ typedef union { struct { - /** timer0_value : RO; bitpos: [15:0]; default: 0; - * current PWM timer0 counter value + /** timer_value : RO; bitpos: [15:0]; default: 0; + * current PWM timer counter value */ - uint32_t timer0_value:16; - /** timer0_direction : RO; bitpos: [16]; default: 0; - * current PWM timer0 counter direction, 0: increment 1: decrement + uint32_t timer_value:16; + /** timer_direction : RO; bitpos: [16]; default: 0; + * current PWM timer counter direction, 0: increment 1: decrement */ - uint32_t timer0_direction:1; + uint32_t timer_direction:1; uint32_t reserved_17:15; }; uint32_t val; -} mcpwm_timer0_status_reg_t; - - -/** Group: MCPWM Timer 1 Configuration and Status */ -/** Type of timer1_cfg0 register - * PWM timer1 period and update method configuration register. - */ -typedef union { - struct { - /** timer1_prescale : R/W; bitpos: [7:0]; default: 0; - * period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1) - */ - uint32_t timer1_prescale:8; - /** timer1_period : R/W; bitpos: [23:8]; default: 255; - * period shadow register of PWM timer1 - */ - uint32_t timer1_period:16; - /** timer1_period_upmethod : R/W; bitpos: [25:24]; default: 0; - * Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: - * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event - */ - uint32_t timer1_period_upmethod:2; - uint32_t reserved_26:6; - }; - uint32_t val; -} mcpwm_timer1_cfg0_reg_t; - -/** Type of timer1_cfg1 register - * PWM timer1 working mode and start/stop control configuration register. - */ -typedef union { - struct { - /** timer1_start : R/W/SC; bitpos: [2:0]; default: 0; - * PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: - * if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 - * starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP - * here and below means the event that happens when the timer equals to period - */ - uint32_t timer1_start:3; - /** timer1_mod : R/W; bitpos: [4:3]; default: 0; - * PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down - * mode - */ - uint32_t timer1_mod:2; - uint32_t reserved_5:27; - }; - uint32_t val; -} mcpwm_timer1_cfg1_reg_t; - -/** Type of timer1_sync register - * PWM timer1 sync function configuration register. - */ -typedef union { - struct { - /** timer1_synci_en : R/W; bitpos: [0]; default: 0; - * When set, timer reloading with phase on sync input event is enabled. - */ - uint32_t timer1_synci_en:1; - /** timer1_sync_sw : R/W; bitpos: [1]; default: 0; - * Toggling this bit will trigger a software sync. - */ - uint32_t timer1_sync_sw:1; - /** timer1_synco_sel : R/W; bitpos: [3:2]; default: 0; - * PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always - * generate when toggling the reg_timer1_sync_sw bit - */ - uint32_t timer1_synco_sel:2; - /** timer1_phase : R/W; bitpos: [19:4]; default: 0; - * phase for timer reload on sync event - */ - uint32_t timer1_phase:16; - /** timer1_phase_direction : R/W; bitpos: [20]; default: 0; - * Configure the PWM timer1's direction when timer1 mode is up-down mode: - * 0-increase,1-decrease - */ - uint32_t timer1_phase_direction:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} mcpwm_timer1_sync_reg_t; - -/** Type of timer1_status register - * PWM timer1 status register. - */ -typedef union { - struct { - /** timer1_value : RO; bitpos: [15:0]; default: 0; - * current PWM timer1 counter value - */ - uint32_t timer1_value:16; - /** timer1_direction : RO; bitpos: [16]; default: 0; - * current PWM timer1 counter direction, 0: increment 1: decrement - */ - uint32_t timer1_direction:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} mcpwm_timer1_status_reg_t; - - -/** Group: MCPWM Timer 2 Configuration and status */ -/** Type of timer2_cfg0 register - * PWM timer2 period and update method configuration register. - */ -typedef union { - struct { - /** timer2_prescale : R/W; bitpos: [7:0]; default: 0; - * period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1) - */ - uint32_t timer2_prescale:8; - /** timer2_period : R/W; bitpos: [23:8]; default: 255; - * period shadow register of PWM timer2 - */ - uint32_t timer2_period:16; - /** timer2_period_upmethod : R/W; bitpos: [25:24]; default: 0; - * Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: - * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event - */ - uint32_t timer2_period_upmethod:2; - uint32_t reserved_26:6; - }; - uint32_t val; -} mcpwm_timer2_cfg0_reg_t; - -/** Type of timer2_cfg1 register - * PWM timer2 working mode and start/stop control configuration register. - */ -typedef union { - struct { - /** timer2_start : R/W/SC; bitpos: [2:0]; default: 0; - * PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: - * if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 - * starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP - * here and below means the event that happens when the timer equals to period - */ - uint32_t timer2_start:3; - /** timer2_mod : R/W; bitpos: [4:3]; default: 0; - * PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down - * mode - */ - uint32_t timer2_mod:2; - uint32_t reserved_5:27; - }; - uint32_t val; -} mcpwm_timer2_cfg1_reg_t; - -/** Type of timer2_sync register - * PWM timer2 sync function configuration register. - */ -typedef union { - struct { - /** timer2_synci_en : R/W; bitpos: [0]; default: 0; - * When set, timer reloading with phase on sync input event is enabled. - */ - uint32_t timer2_synci_en:1; - /** timer2_sync_sw : R/W; bitpos: [1]; default: 0; - * Toggling this bit will trigger a software sync. - */ - uint32_t timer2_sync_sw:1; - /** timer2_synco_sel : R/W; bitpos: [3:2]; default: 0; - * PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always - * generate when toggling the reg_timer0_sync_sw bit - */ - uint32_t timer2_synco_sel:2; - /** timer2_phase : R/W; bitpos: [19:4]; default: 0; - * phase for timer reload on sync event - */ - uint32_t timer2_phase:16; - /** timer2_phase_direction : R/W; bitpos: [20]; default: 0; - * Configure the PWM timer2's direction when timer2 mode is up-down mode: - * 0-increase,1-decrease - */ - uint32_t timer2_phase_direction:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} mcpwm_timer2_sync_reg_t; - -/** Type of timer2_status register - * PWM timer2 status register. - */ -typedef union { - struct { - /** timer2_value : RO; bitpos: [15:0]; default: 0; - * current PWM timer2 counter value - */ - uint32_t timer2_value:16; - /** timer2_direction : RO; bitpos: [16]; default: 0; - * current PWM timer2 counter direction, 0: increment 1: decrement - */ - uint32_t timer2_direction:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} mcpwm_timer2_status_reg_t; +} mcpwm_timer_status_reg_t; /** Group: Common configuration for MCPWM timers */ @@ -384,1525 +190,438 @@ typedef union { } mcpwm_operator_timersel_reg_t; -/** Group: MCPWM Operator 0 Configuration and Status */ -/** Type of gen0_stmp_cfg register +/** Group: MCPWM Operator Configuration and Status */ +/** Type of gen_stmp_cfg register * Transfer status and update method for time stamp registers A and B */ typedef union { struct { - /** cmpr0_a_upmethod : R/W; bitpos: [3:0]; default: 0; - * Update method for PWM generator 0 time stamp A's active register. When all bits are + /** cmpr_a_upmethod : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator time stamp A's active register. When all bits are * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. */ - uint32_t cmpr0_a_upmethod:4; - /** cmpr0_b_upmethod : R/W; bitpos: [7:4]; default: 0; - * Update method for PWM generator 0 time stamp B's active register. When all bits are + uint32_t cmpr_a_upmethod:4; + /** cmpr_b_upmethod : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator time stamp B's active register. When all bits are * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. */ - uint32_t cmpr0_b_upmethod:4; - /** cmpr0_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; - * Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is + uint32_t cmpr_b_upmethod:4; + /** cmpr_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator time stamp A's shadow reg is * filled and waiting to be transferred to A's active reg. If cleared, A's active reg * has been updated with shadow register latest value */ - uint32_t cmpr0_a_shdw_full:1; - /** cmpr0_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; - * Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is + uint32_t cmpr_a_shdw_full:1; + /** cmpr_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator time stamp B's shadow reg is * filled and waiting to be transferred to B's active reg. If cleared, B's active reg * has been updated with shadow register latest value */ - uint32_t cmpr0_b_shdw_full:1; + uint32_t cmpr_b_shdw_full:1; uint32_t reserved_10:22; }; uint32_t val; -} mcpwm_gen0_stmp_cfg_reg_t; +} mcpwm_gen_stmp_cfg_reg_t; -/** Type of gen0_tstmp_a register - * Shadow register for register A. - */ -typedef union { - struct { - /** cmpr0_a : R/W; bitpos: [15:0]; default: 0; - * PWM generator 0 time stamp A's shadow register - */ - uint32_t cmpr0_a:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_gen0_tstmp_a_reg_t; - -/** Type of gen0_tstmp_b register +/** Type of gen_tstmp register * Shadow register for register B. */ typedef union { struct { - /** cmpr0_b : R/W; bitpos: [15:0]; default: 0; - * PWM generator 0 time stamp B's shadow register + /** cmpr : R/W; bitpos: [15:0]; default: 0; + * PWM generator time stamp's shadow register */ - uint32_t cmpr0_b:16; + uint32_t cmpr:16; uint32_t reserved_16:16; }; uint32_t val; -} mcpwm_gen0_tstmp_b_reg_t; +} mcpwm_gen_tstmp_reg_t; -/** Type of gen0_cfg0 register +/** Type of gen_cfg0 register * Fault event T0 and T1 handling */ typedef union { struct { - /** gen0_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; - * Update method for PWM generator 0's active register of configuration. When all bits + /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator's active register of configuration. When all bits * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to * 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update */ - uint32_t gen0_cfg_upmethod:4; - /** gen0_t0_sel : R/W; bitpos: [6:4]; default: 0; - * Source selection for PWM generator 0 event_t0, take effect immediately, 0: + uint32_t gen_cfg_upmethod:4; + /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator event_t0, take effect immediately, 0: * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none */ - uint32_t gen0_t0_sel:3; - /** gen0_t1_sel : R/W; bitpos: [9:7]; default: 0; - * Source selection for PWM generator 0 event_t1, take effect immediately, 0: + uint32_t gen_t0_sel:3; + /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator event_t1, take effect immediately, 0: * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none */ - uint32_t gen0_t1_sel:3; + uint32_t gen_t1_sel:3; uint32_t reserved_10:22; }; uint32_t val; -} mcpwm_gen0_cfg0_reg_t; +} mcpwm_gen_cfg0_reg_t; -/** Type of gen0_force register +/** Type of gen_force register * Permissives to force PWM0A and PWM0B outputs by software */ typedef union { struct { - /** gen0_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; - * Updating method for continuous software force of PWM generator0. When all bits are + /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator. When all bits are * set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, * when bit5 is set to 1: disable update. (TEA/B here and below means an event * generated when the timer's value equals to that of register A/B.) */ - uint32_t gen0_cntuforce_upmethod:6; - /** gen0_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; - * Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled + uint32_t gen_cntuforce_upmethod:6; + /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWMnA. 0: disabled, 1: low, 2: high, 3: disabled */ - uint32_t gen0_a_cntuforce_mode:2; - /** gen0_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; - * Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled + uint32_t gen_a_cntuforce_mode:2; + /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWMnB. 0: disabled, 1: low, 2: high, 3: disabled */ - uint32_t gen0_b_cntuforce_mode:2; - /** gen0_a_nciforce : R/W; bitpos: [10]; default: 0; - * Trigger of non-continuous immediate software-force event for PWM0A, a toggle will + uint32_t gen_b_cntuforce_mode:2; + /** gen_a_nciforce : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWMnA, a toggle will * trigger a force event. */ - uint32_t gen0_a_nciforce:1; - /** gen0_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; - * non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: + uint32_t gen_a_nciforce:1; + /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWMnA, 0: disabled, 1: low, 2: * high, 3: disabled */ - uint32_t gen0_a_nciforce_mode:2; - /** gen0_b_nciforce : R/W; bitpos: [13]; default: 0; - * Trigger of non-continuous immediate software-force event for PWM0B, a toggle will + uint32_t gen_a_nciforce_mode:2; + /** gen_b_nciforce : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWMnB, a toggle will * trigger a force event. */ - uint32_t gen0_b_nciforce:1; - /** gen0_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; - * non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: + uint32_t gen_b_nciforce:1; + /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWMnB, 0: disabled, 1: low, 2: * high, 3: disabled */ - uint32_t gen0_b_nciforce_mode:2; + uint32_t gen_b_nciforce_mode:2; uint32_t reserved_16:16; }; uint32_t val; -} mcpwm_gen0_force_reg_t; +} mcpwm_gen_force_reg_t; -/** Type of gen0_a register - * Actions triggered by events on PWM0A - */ -typedef union { - struct { - /** gen0_a_utez : R/W; bitpos: [1:0]; default: 0; - * Action on PWM0A triggered by event TEZ when timer increasing - */ - uint32_t gen0_a_utez:2; - /** gen0_a_utep : R/W; bitpos: [3:2]; default: 0; - * Action on PWM0A triggered by event TEP when timer increasing - */ - uint32_t gen0_a_utep:2; - /** gen0_a_utea : R/W; bitpos: [5:4]; default: 0; - * Action on PWM0A triggered by event TEA when timer increasing - */ - uint32_t gen0_a_utea:2; - /** gen0_a_uteb : R/W; bitpos: [7:6]; default: 0; - * Action on PWM0A triggered by event TEB when timer increasing - */ - uint32_t gen0_a_uteb:2; - /** gen0_a_ut0 : R/W; bitpos: [9:8]; default: 0; - * Action on PWM0A triggered by event_t0 when timer increasing - */ - uint32_t gen0_a_ut0:2; - /** gen0_a_ut1 : R/W; bitpos: [11:10]; default: 0; - * Action on PWM0A triggered by event_t1 when timer increasing - */ - uint32_t gen0_a_ut1:2; - /** gen0_a_dtez : R/W; bitpos: [13:12]; default: 0; - * Action on PWM0A triggered by event TEZ when timer decreasing - */ - uint32_t gen0_a_dtez:2; - /** gen0_a_dtep : R/W; bitpos: [15:14]; default: 0; - * Action on PWM0A triggered by event TEP when timer decreasing - */ - uint32_t gen0_a_dtep:2; - /** gen0_a_dtea : R/W; bitpos: [17:16]; default: 0; - * Action on PWM0A triggered by event TEA when timer decreasing - */ - uint32_t gen0_a_dtea:2; - /** gen0_a_dteb : R/W; bitpos: [19:18]; default: 0; - * Action on PWM0A triggered by event TEB when timer decreasing - */ - uint32_t gen0_a_dteb:2; - /** gen0_a_dt0 : R/W; bitpos: [21:20]; default: 0; - * Action on PWM0A triggered by event_t0 when timer decreasing - */ - uint32_t gen0_a_dt0:2; - /** gen0_a_dt1 : R/W; bitpos: [23:22]; default: 0; - * Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, - * 2: high, 3: toggle - */ - uint32_t gen0_a_dt1:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} mcpwm_gen0_a_reg_t; - -/** Type of gen0_b register +/** Type of gen register * Actions triggered by events on PWM0B */ typedef union { struct { - /** gen0_b_utez : R/W; bitpos: [1:0]; default: 0; - * Action on PWM0B triggered by event TEZ when timer increasing + /** gen_utez : R/W; bitpos: [1:0]; default: 0; + * Action on PWMnA/B triggered by event TEZ when timer increasing */ - uint32_t gen0_b_utez:2; - /** gen0_b_utep : R/W; bitpos: [3:2]; default: 0; - * Action on PWM0B triggered by event TEP when timer increasing + uint32_t gen_utez:2; + /** gen_utep : R/W; bitpos: [3:2]; default: 0; + * Action on PWMnA/B triggered by event TEP when timer increasing */ - uint32_t gen0_b_utep:2; - /** gen0_b_utea : R/W; bitpos: [5:4]; default: 0; - * Action on PWM0B triggered by event TEA when timer increasing + uint32_t gen_utep:2; + /** gen_utea : R/W; bitpos: [5:4]; default: 0; + * Action on PWMnA/B triggered by event TEA when timer increasing */ - uint32_t gen0_b_utea:2; - /** gen0_b_uteb : R/W; bitpos: [7:6]; default: 0; - * Action on PWM0B triggered by event TEB when timer increasing + uint32_t gen_utea:2; + /** gen_uteb : R/W; bitpos: [7:6]; default: 0; + * Action on PWMnA/B triggered by event TEB when timer increasing */ - uint32_t gen0_b_uteb:2; - /** gen0_b_ut0 : R/W; bitpos: [9:8]; default: 0; - * Action on PWM0B triggered by event_t0 when timer increasing + uint32_t gen_uteb:2; + /** gen_ut0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWMnA/B triggered by event_t0 when timer increasing */ - uint32_t gen0_b_ut0:2; - /** gen0_b_ut1 : R/W; bitpos: [11:10]; default: 0; - * Action on PWM0B triggered by event_t1 when timer increasing + uint32_t gen_ut0:2; + /** gen_ut1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWMnA/B triggered by event_t1 when timer increasing */ - uint32_t gen0_b_ut1:2; - /** gen0_b_dtez : R/W; bitpos: [13:12]; default: 0; - * Action on PWM0B triggered by event TEZ when timer decreasing + uint32_t gen_ut1:2; + /** gen_dtez : R/W; bitpos: [13:12]; default: 0; + * Action on PWMnA/B triggered by event TEZ when timer decreasing */ - uint32_t gen0_b_dtez:2; - /** gen0_b_dtep : R/W; bitpos: [15:14]; default: 0; - * Action on PWM0B triggered by event TEP when timer decreasing + uint32_t gen_dtez:2; + /** gen_dtep : R/W; bitpos: [15:14]; default: 0; + * Action on PWMnA/B triggered by event TEP when timer decreasing */ - uint32_t gen0_b_dtep:2; - /** gen0_b_dtea : R/W; bitpos: [17:16]; default: 0; - * Action on PWM0B triggered by event TEA when timer decreasing + uint32_t gen_dtep:2; + /** gen_dtea : R/W; bitpos: [17:16]; default: 0; + * Action on PWMnA/B triggered by event TEA when timer decreasing */ - uint32_t gen0_b_dtea:2; - /** gen0_b_dteb : R/W; bitpos: [19:18]; default: 0; - * Action on PWM0B triggered by event TEB when timer decreasing + uint32_t gen_dtea:2; + /** gen_dteb : R/W; bitpos: [19:18]; default: 0; + * Action on PWMnA/B triggered by event TEB when timer decreasing */ - uint32_t gen0_b_dteb:2; - /** gen0_b_dt0 : R/W; bitpos: [21:20]; default: 0; - * Action on PWM0B triggered by event_t0 when timer decreasing + uint32_t gen_dteb:2; + /** gen_dt0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWMnA/B triggered by event_t0 when timer decreasing */ - uint32_t gen0_b_dt0:2; - /** gen0_b_dt1 : R/W; bitpos: [23:22]; default: 0; - * Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + uint32_t gen_dt0:2; + /** gen_dt1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWMnA/B triggered by event_t1 when timer decreasing. 0: no change, 1: low, * 2: high, 3: toggle */ - uint32_t gen0_b_dt1:2; + uint32_t gen_dt1:2; uint32_t reserved_24:8; }; uint32_t val; -} mcpwm_gen0_b_reg_t; +} mcpwm_gen_reg_t; -/** Type of dt0_cfg register +/** Type of dt_cfg register * dead time type selection and configuration */ typedef union { struct { - /** db0_fed_upmethod : R/W; bitpos: [3:0]; default: 0; + /** db_fed_upmethod : R/W; bitpos: [3:0]; default: 0; * Update method for FED (rising edge delay) active register. 0: immediate, when bit0 * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when * bit3 is set to 1: disable the update */ - uint32_t db0_fed_upmethod:4; - /** db0_red_upmethod : R/W; bitpos: [7:4]; default: 0; + uint32_t db_fed_upmethod:4; + /** db_red_upmethod : R/W; bitpos: [7:4]; default: 0; * Update method for RED (rising edge delay) active register. 0: immediate, when bit0 * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when * bit3 is set to 1: disable the update */ - uint32_t db0_red_upmethod:4; - /** db0_deb_mode : R/W; bitpos: [8]; default: 0; + uint32_t db_red_upmethod:4; + /** db_deb_mode : R/W; bitpos: [8]; default: 0; * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, * 1: fed/red take effect on B path, A out is in bypass or dulpB mode */ - uint32_t db0_deb_mode:1; - /** db0_a_outswap : R/W; bitpos: [9]; default: 0; + uint32_t db_deb_mode:1; + /** db_a_outswap : R/W; bitpos: [9]; default: 0; * S6 in table */ - uint32_t db0_a_outswap:1; - /** db0_b_outswap : R/W; bitpos: [10]; default: 0; + uint32_t db_a_outswap:1; + /** db_b_outswap : R/W; bitpos: [10]; default: 0; * S7 in table */ - uint32_t db0_b_outswap:1; - /** db0_red_insel : R/W; bitpos: [11]; default: 0; + uint32_t db_b_outswap:1; + /** db_red_insel : R/W; bitpos: [11]; default: 0; * S4 in table */ - uint32_t db0_red_insel:1; - /** db0_fed_insel : R/W; bitpos: [12]; default: 0; + uint32_t db_red_insel:1; + /** db_fed_insel : R/W; bitpos: [12]; default: 0; * S5 in table */ - uint32_t db0_fed_insel:1; - /** db0_red_outinvert : R/W; bitpos: [13]; default: 0; + uint32_t db_fed_insel:1; + /** db_red_outinvert : R/W; bitpos: [13]; default: 0; * S2 in table */ - uint32_t db0_red_outinvert:1; - /** db0_fed_outinvert : R/W; bitpos: [14]; default: 0; + uint32_t db_red_outinvert:1; + /** db_fed_outinvert : R/W; bitpos: [14]; default: 0; * S3 in table */ - uint32_t db0_fed_outinvert:1; - /** db0_a_outbypass : R/W; bitpos: [15]; default: 1; + uint32_t db_fed_outinvert:1; + /** db_a_outbypass : R/W; bitpos: [15]; default: 1; * S1 in table */ - uint32_t db0_a_outbypass:1; - /** db0_b_outbypass : R/W; bitpos: [16]; default: 1; + uint32_t db_a_outbypass:1; + /** db_b_outbypass : R/W; bitpos: [16]; default: 1; * S0 in table */ - uint32_t db0_b_outbypass:1; - /** db0_clk_sel : R/W; bitpos: [17]; default: 0; - * Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk + uint32_t db_b_outbypass:1; + /** db_clk_sel : R/W; bitpos: [17]; default: 0; + * Dead time generator n clock selection. 0: PWM_clk, 1: PT_clk */ - uint32_t db0_clk_sel:1; + uint32_t db_clk_sel:1; uint32_t reserved_18:14; }; uint32_t val; -} mcpwm_dt0_cfg_reg_t; +} mcpwm_dt_cfg_reg_t; -/** Type of dt0_fed_cfg register +/** Type of dt_fed_cfg register * Shadow register for falling edge delay (FED). */ typedef union { struct { - /** db0_fed : R/W; bitpos: [15:0]; default: 0; + /** db_fed : R/W; bitpos: [15:0]; default: 0; * Shadow register for FED */ - uint32_t db0_fed:16; + uint32_t db_fed:16; uint32_t reserved_16:16; }; uint32_t val; -} mcpwm_dt0_fed_cfg_reg_t; +} mcpwm_dt_fed_cfg_reg_t; -/** Type of dt0_red_cfg register +/** Type of dt_red_cfg register * Shadow register for rising edge delay (RED). */ typedef union { struct { - /** db0_red : R/W; bitpos: [15:0]; default: 0; + /** db_red : R/W; bitpos: [15:0]; default: 0; * Shadow register for RED */ - uint32_t db0_red:16; + uint32_t db_red:16; uint32_t reserved_16:16; }; uint32_t val; -} mcpwm_dt0_red_cfg_reg_t; +} mcpwm_dt_red_cfg_reg_t; -/** Type of carrier0_cfg register +/** Type of carrier_cfg register * Carrier enable and configuration */ typedef union { struct { - /** chopper0_en : R/W; bitpos: [0]; default: 0; + /** chopper_en : R/W; bitpos: [0]; default: 0; * When set, carrier0 function is enabled. When cleared, carrier0 is bypassed */ - uint32_t chopper0_en:1; - /** chopper0_prescale : R/W; bitpos: [4:1]; default: 0; + uint32_t chopper_en:1; + /** chopper_prescale : R/W; bitpos: [4:1]; default: 0; * PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * * (PWM_CARRIER0_PRESCALE + 1) */ - uint32_t chopper0_prescale:4; - /** chopper0_duty : R/W; bitpos: [7:5]; default: 0; + uint32_t chopper_prescale:4; + /** chopper_duty : R/W; bitpos: [7:5]; default: 0; * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 */ - uint32_t chopper0_duty:3; - /** chopper0_oshtwth : R/W; bitpos: [11:8]; default: 0; + uint32_t chopper_duty:3; + /** chopper_oshtwth : R/W; bitpos: [11:8]; default: 0; * width of the first pulse in number of periods of the carrier */ - uint32_t chopper0_oshtwth:4; - /** chopper0_out_invert : R/W; bitpos: [12]; default: 0; + uint32_t chopper_oshtwth:4; + /** chopper_out_invert : R/W; bitpos: [12]; default: 0; * when set, invert the output of PWM0A and PWM0B for this submodule */ - uint32_t chopper0_out_invert:1; - /** chopper0_in_invert : R/W; bitpos: [13]; default: 0; + uint32_t chopper_out_invert:1; + /** chopper_in_invert : R/W; bitpos: [13]; default: 0; * when set, invert the input of PWM0A and PWM0B for this submodule */ - uint32_t chopper0_in_invert:1; + uint32_t chopper_in_invert:1; uint32_t reserved_14:18; }; uint32_t val; -} mcpwm_carrier0_cfg_reg_t; +} mcpwm_carrier_cfg_reg_t; -/** Type of fh0_cfg0 register +/** Type of fh_cfg0 register * Actions on PWM0A and PWM0B trip events */ typedef union { struct { - /** tz0_sw_cbc : R/W; bitpos: [0]; default: 0; + /** tz_sw_cbc : R/W; bitpos: [0]; default: 0; * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable */ - uint32_t tz0_sw_cbc:1; - /** tz0_f2_cbc : R/W; bitpos: [1]; default: 0; + uint32_t tz_sw_cbc:1; + /** tz_f2_cbc : R/W; bitpos: [1]; default: 0; * event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable */ - uint32_t tz0_f2_cbc:1; - /** tz0_f1_cbc : R/W; bitpos: [2]; default: 0; + uint32_t tz_f2_cbc:1; + /** tz_f1_cbc : R/W; bitpos: [2]; default: 0; * event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable */ - uint32_t tz0_f1_cbc:1; - /** tz0_f0_cbc : R/W; bitpos: [3]; default: 0; + uint32_t tz_f1_cbc:1; + /** tz_f0_cbc : R/W; bitpos: [3]; default: 0; * event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable */ - uint32_t tz0_f0_cbc:1; - /** tz0_sw_ost : R/W; bitpos: [4]; default: 0; + uint32_t tz_f0_cbc:1; + /** tz_sw_ost : R/W; bitpos: [4]; default: 0; * Enable register for software force one-shot mode action. 0: disable, 1: enable */ - uint32_t tz0_sw_ost:1; - /** tz0_f2_ost : R/W; bitpos: [5]; default: 0; + uint32_t tz_sw_ost:1; + /** tz_f2_ost : R/W; bitpos: [5]; default: 0; * event_f2 will trigger one-shot mode action. 0: disable, 1: enable */ - uint32_t tz0_f2_ost:1; - /** tz0_f1_ost : R/W; bitpos: [6]; default: 0; + uint32_t tz_f2_ost:1; + /** tz_f1_ost : R/W; bitpos: [6]; default: 0; * event_f1 will trigger one-shot mode action. 0: disable, 1: enable */ - uint32_t tz0_f1_ost:1; - /** tz0_f0_ost : R/W; bitpos: [7]; default: 0; + uint32_t tz_f1_ost:1; + /** tz_f0_ost : R/W; bitpos: [7]; default: 0; * event_f0 will trigger one-shot mode action. 0: disable, 1: enable */ - uint32_t tz0_f0_ost:1; - /** tz0_a_cbc_d : R/W; bitpos: [9:8]; default: 0; + uint32_t tz_f0_ost:1; + /** tz_a_cbc_d : R/W; bitpos: [9:8]; default: 0; * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle */ - uint32_t tz0_a_cbc_d:2; - /** tz0_a_cbc_u : R/W; bitpos: [11:10]; default: 0; + uint32_t tz_a_cbc_d:2; + /** tz_a_cbc_u : R/W; bitpos: [11:10]; default: 0; * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle */ - uint32_t tz0_a_cbc_u:2; - /** tz0_a_ost_d : R/W; bitpos: [13:12]; default: 0; + uint32_t tz_a_cbc_u:2; + /** tz_a_ost_d : R/W; bitpos: [13:12]; default: 0; * One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: * do nothing, 1: force low, 2: force high, 3: toggle */ - uint32_t tz0_a_ost_d:2; - /** tz0_a_ost_u : R/W; bitpos: [15:14]; default: 0; + uint32_t tz_a_ost_d:2; + /** tz_a_ost_u : R/W; bitpos: [15:14]; default: 0; * One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: * do nothing, 1: force low, 2: force high, 3: toggle */ - uint32_t tz0_a_ost_u:2; - /** tz0_b_cbc_d : R/W; bitpos: [17:16]; default: 0; + uint32_t tz_a_ost_u:2; + /** tz_b_cbc_d : R/W; bitpos: [17:16]; default: 0; * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle */ - uint32_t tz0_b_cbc_d:2; - /** tz0_b_cbc_u : R/W; bitpos: [19:18]; default: 0; + uint32_t tz_b_cbc_d:2; + /** tz_b_cbc_u : R/W; bitpos: [19:18]; default: 0; * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is * increasing. 0: do nothing,1: force low, 2: force high, 3: toggle */ - uint32_t tz0_b_cbc_u:2; - /** tz0_b_ost_d : R/W; bitpos: [21:20]; default: 0; + uint32_t tz_b_cbc_u:2; + /** tz_b_ost_d : R/W; bitpos: [21:20]; default: 0; * One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: * do nothing, 1: force low, 2: force high, 3: toggle */ - uint32_t tz0_b_ost_d:2; - /** tz0_b_ost_u : R/W; bitpos: [23:22]; default: 0; + uint32_t tz_b_ost_d:2; + /** tz_b_ost_u : R/W; bitpos: [23:22]; default: 0; * One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: * do nothing, 1: force low, 2: force high, 3: toggle */ - uint32_t tz0_b_ost_u:2; + uint32_t tz_b_ost_u:2; uint32_t reserved_24:8; }; uint32_t val; -} mcpwm_fh0_cfg0_reg_t; +} mcpwm_fh_cfg0_reg_t; -/** Type of fh0_cfg1 register +/** Type of fh_cfg1 register * Software triggers for fault handler actions */ typedef union { struct { - /** tz0_clr_ost : R/W; bitpos: [0]; default: 0; + /** tz_clr_ost : R/W; bitpos: [0]; default: 0; * a rising edge will clear on going one-shot mode action */ - uint32_t tz0_clr_ost:1; - /** tz0_cbcpulse : R/W; bitpos: [2:1]; default: 0; + uint32_t tz_clr_ost:1; + /** tz_cbcpulse : R/W; bitpos: [2:1]; default: 0; * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, * when bit1 is set to 1:TEP */ - uint32_t tz0_cbcpulse:2; - /** tz0_force_cbc : R/W; bitpos: [3]; default: 0; + uint32_t tz_cbcpulse:2; + /** tz_force_cbc : R/W; bitpos: [3]; default: 0; * a toggle trigger a cycle-by-cycle mode action */ - uint32_t tz0_force_cbc:1; - /** tz0_force_ost : R/W; bitpos: [4]; default: 0; + uint32_t tz_force_cbc:1; + /** tz_force_ost : R/W; bitpos: [4]; default: 0; * a toggle (software negate its value) triggers a one-shot mode action */ - uint32_t tz0_force_ost:1; + uint32_t tz_force_ost:1; uint32_t reserved_5:27; }; uint32_t val; -} mcpwm_fh0_cfg1_reg_t; +} mcpwm_fh_cfg1_reg_t; -/** Type of fh0_status register +/** Type of fh_status register * Status of fault events. */ typedef union { struct { - /** tz0_cbc_on : RO; bitpos: [0]; default: 0; + /** tz_cbc_on : RO; bitpos: [0]; default: 0; * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going */ - uint32_t tz0_cbc_on:1; - /** tz0_ost_on : RO; bitpos: [1]; default: 0; + uint32_t tz_cbc_on:1; + /** tz_ost_on : RO; bitpos: [1]; default: 0; * Set and reset by hardware. If set, an one-shot mode action is on going */ - uint32_t tz0_ost_on:1; + uint32_t tz_ost_on:1; uint32_t reserved_2:30; }; uint32_t val; -} mcpwm_fh0_status_reg_t; - - -/** Group: MCPWM Operator 1 Configuration and Status */ -/** Type of gen1_stmp_cfg register - * Transfer status and update method for time stamp registers A and B - */ -typedef union { - struct { - /** cmpr1_a_upmethod : R/W; bitpos: [3:0]; default: 0; - * Update method for PWM generator 1 time stamp A's active register. When all bits are - * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when - * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. - */ - uint32_t cmpr1_a_upmethod:4; - /** cmpr1_b_upmethod : R/W; bitpos: [7:4]; default: 0; - * Update method for PWM generator 1 time stamp B's active register. When all bits are - * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when - * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. - */ - uint32_t cmpr1_b_upmethod:4; - /** cmpr1_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; - * Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is - * filled and waiting to be transferred to A's active reg. If cleared, A's active reg - * has been updated with shadow register latest value - */ - uint32_t cmpr1_a_shdw_full:1; - /** cmpr1_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; - * Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is - * filled and waiting to be transferred to B's active reg. If cleared, B's active reg - * has been updated with shadow register latest value - */ - uint32_t cmpr1_b_shdw_full:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} mcpwm_gen1_stmp_cfg_reg_t; - -/** Type of gen1_tstmp_a register - * Shadow register for register A. - */ -typedef union { - struct { - /** cmpr1_a : R/W; bitpos: [15:0]; default: 0; - * PWM generator 1 time stamp A's shadow register - */ - uint32_t cmpr1_a:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_gen1_tstmp_a_reg_t; - -/** Type of gen1_tstmp_b register - * Shadow register for register B. - */ -typedef union { - struct { - /** cmpr1_b : R/W; bitpos: [15:0]; default: 0; - * PWM generator 1 time stamp B's shadow register - */ - uint32_t cmpr1_b:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_gen1_tstmp_b_reg_t; - -/** Type of gen1_cfg0 register - * Fault event T0 and T1 handling - */ -typedef union { - struct { - /** gen1_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; - * Update method for PWM generator 1's active register of configuration. When all bits - * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to - * 1:sync;when bit3 is set to 1:disable the update. - */ - uint32_t gen1_cfg_upmethod:4; - /** gen1_t0_sel : R/W; bitpos: [6:4]; default: 0; - * Source selection for PWM generator 1 event_t0, take effect immediately, 0: - * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none - */ - uint32_t gen1_t0_sel:3; - /** gen1_t1_sel : R/W; bitpos: [9:7]; default: 0; - * Source selection for PWM generator 1 event_t1, take effect immediately, 0: - * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none - */ - uint32_t gen1_t1_sel:3; - uint32_t reserved_10:22; - }; - uint32_t val; -} mcpwm_gen1_cfg0_reg_t; - -/** Type of gen1_force register - * Permissives to force PWM1A and PWM1B outputs by software - */ -typedef union { - struct { - /** gen1_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; - * Updating method for continuous software force of PWM generator 1. When all bits are - * set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when - * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, - * when bit5 is set to 1: disable update. (TEA/B here and below means an event - * generated when the timer's value equals to that of register A/B.) - */ - uint32_t gen1_cntuforce_upmethod:6; - /** gen1_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; - * Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled - */ - uint32_t gen1_a_cntuforce_mode:2; - /** gen1_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; - * Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled - */ - uint32_t gen1_b_cntuforce_mode:2; - /** gen1_a_nciforce : R/W; bitpos: [10]; default: 0; - * Trigger of non-continuous immediate software-force event for PWM1A, a toggle will - * trigger a force event. - */ - uint32_t gen1_a_nciforce:1; - /** gen1_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; - * non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: - * high, 3: disabled - */ - uint32_t gen1_a_nciforce_mode:2; - /** gen1_b_nciforce : R/W; bitpos: [13]; default: 0; - * Trigger of non-continuous immediate software-force event for PWM1B, a toggle will - * trigger a force event. - */ - uint32_t gen1_b_nciforce:1; - /** gen1_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; - * non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: - * high, 3: disabled - */ - uint32_t gen1_b_nciforce_mode:2; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_gen1_force_reg_t; - -/** Type of gen1_a register - * Actions triggered by events on PWM1A - */ -typedef union { - struct { - /** gen1_a_utez : R/W; bitpos: [1:0]; default: 0; - * Action on PWM1A triggered by event TEZ when timer increasing - */ - uint32_t gen1_a_utez:2; - /** gen1_a_utep : R/W; bitpos: [3:2]; default: 0; - * Action on PWM1A triggered by event TEP when timer increasing - */ - uint32_t gen1_a_utep:2; - /** gen1_a_utea : R/W; bitpos: [5:4]; default: 0; - * Action on PWM1A triggered by event TEA when timer increasing - */ - uint32_t gen1_a_utea:2; - /** gen1_a_uteb : R/W; bitpos: [7:6]; default: 0; - * Action on PWM1A triggered by event TEB when timer increasing - */ - uint32_t gen1_a_uteb:2; - /** gen1_a_ut0 : R/W; bitpos: [9:8]; default: 0; - * Action on PWM1A triggered by event_t0 when timer increasing - */ - uint32_t gen1_a_ut0:2; - /** gen1_a_ut1 : R/W; bitpos: [11:10]; default: 0; - * Action on PWM1A triggered by event_t1 when timer increasing - */ - uint32_t gen1_a_ut1:2; - /** gen1_a_dtez : R/W; bitpos: [13:12]; default: 0; - * Action on PWM1A triggered by event TEZ when timer decreasing - */ - uint32_t gen1_a_dtez:2; - /** gen1_a_dtep : R/W; bitpos: [15:14]; default: 0; - * Action on PWM1A triggered by event TEP when timer decreasing - */ - uint32_t gen1_a_dtep:2; - /** gen1_a_dtea : R/W; bitpos: [17:16]; default: 0; - * Action on PWM1A triggered by event TEA when timer decreasing - */ - uint32_t gen1_a_dtea:2; - /** gen1_a_dteb : R/W; bitpos: [19:18]; default: 0; - * Action on PWM1A triggered by event TEB when timer decreasing - */ - uint32_t gen1_a_dteb:2; - /** gen1_a_dt0 : R/W; bitpos: [21:20]; default: 0; - * Action on PWM1A triggered by event_t0 when timer decreasing - */ - uint32_t gen1_a_dt0:2; - /** gen1_a_dt1 : R/W; bitpos: [23:22]; default: 0; - * Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, - * 2: high, 3: toggle - */ - uint32_t gen1_a_dt1:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} mcpwm_gen1_a_reg_t; - -/** Type of gen1_b register - * Actions triggered by events on PWM1B - */ -typedef union { - struct { - /** gen1_b_utez : R/W; bitpos: [1:0]; default: 0; - * Action on PWM1B triggered by event TEZ when timer increasing - */ - uint32_t gen1_b_utez:2; - /** gen1_b_utep : R/W; bitpos: [3:2]; default: 0; - * Action on PWM1B triggered by event TEP when timer increasing - */ - uint32_t gen1_b_utep:2; - /** gen1_b_utea : R/W; bitpos: [5:4]; default: 0; - * Action on PWM1B triggered by event TEA when timer increasing - */ - uint32_t gen1_b_utea:2; - /** gen1_b_uteb : R/W; bitpos: [7:6]; default: 0; - * Action on PWM1B triggered by event TEB when timer increasing - */ - uint32_t gen1_b_uteb:2; - /** gen1_b_ut0 : R/W; bitpos: [9:8]; default: 0; - * Action on PWM1B triggered by event_t0 when timer increasing - */ - uint32_t gen1_b_ut0:2; - /** gen1_b_ut1 : R/W; bitpos: [11:10]; default: 0; - * Action on PWM1B triggered by event_t1 when timer increasing - */ - uint32_t gen1_b_ut1:2; - /** gen1_b_dtez : R/W; bitpos: [13:12]; default: 0; - * Action on PWM1B triggered by event TEZ when timer decreasing - */ - uint32_t gen1_b_dtez:2; - /** gen1_b_dtep : R/W; bitpos: [15:14]; default: 0; - * Action on PWM1B triggered by event TEP when timer decreasing - */ - uint32_t gen1_b_dtep:2; - /** gen1_b_dtea : R/W; bitpos: [17:16]; default: 0; - * Action on PWM1B triggered by event TEA when timer decreasing - */ - uint32_t gen1_b_dtea:2; - /** gen1_b_dteb : R/W; bitpos: [19:18]; default: 0; - * Action on PWM1B triggered by event TEB when timer decreasing - */ - uint32_t gen1_b_dteb:2; - /** gen1_b_dt0 : R/W; bitpos: [21:20]; default: 0; - * Action on PWM1B triggered by event_t0 when timer decreasing - */ - uint32_t gen1_b_dt0:2; - /** gen1_b_dt1 : R/W; bitpos: [23:22]; default: 0; - * Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, - * 2: high, 3: toggle - */ - uint32_t gen1_b_dt1:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} mcpwm_gen1_b_reg_t; - -/** Type of dt1_cfg register - * dead time type selection and configuration - */ -typedef union { - struct { - /** db1_fed_upmethod : R/W; bitpos: [3:0]; default: 0; - * Update method for FED (falling edge delay) active register. 0: immediate, when bit0 - * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when - * bit3 is set to 1: disable the update - */ - uint32_t db1_fed_upmethod:4; - /** db1_red_upmethod : R/W; bitpos: [7:4]; default: 0; - * Update method for RED (rising edge delay) active register. 0: immediate,when bit0 - * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when - * bit3 is set to 1: disable the update - */ - uint32_t db1_red_upmethod:4; - /** db1_deb_mode : R/W; bitpos: [8]; default: 0; - * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, - * 1: fed/red take effect on B path, A out is in bypass or dulpB mode - */ - uint32_t db1_deb_mode:1; - /** db1_a_outswap : R/W; bitpos: [9]; default: 0; - * S6 in table - */ - uint32_t db1_a_outswap:1; - /** db1_b_outswap : R/W; bitpos: [10]; default: 0; - * S7 in table - */ - uint32_t db1_b_outswap:1; - /** db1_red_insel : R/W; bitpos: [11]; default: 0; - * S4 in table - */ - uint32_t db1_red_insel:1; - /** db1_fed_insel : R/W; bitpos: [12]; default: 0; - * S5 in table - */ - uint32_t db1_fed_insel:1; - /** db1_red_outinvert : R/W; bitpos: [13]; default: 0; - * S2 in table - */ - uint32_t db1_red_outinvert:1; - /** db1_fed_outinvert : R/W; bitpos: [14]; default: 0; - * S3 in table - */ - uint32_t db1_fed_outinvert:1; - /** db1_a_outbypass : R/W; bitpos: [15]; default: 1; - * S1 in table - */ - uint32_t db1_a_outbypass:1; - /** db1_b_outbypass : R/W; bitpos: [16]; default: 1; - * S0 in table - */ - uint32_t db1_b_outbypass:1; - /** db1_clk_sel : R/W; bitpos: [17]; default: 0; - * Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk - */ - uint32_t db1_clk_sel:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} mcpwm_dt1_cfg_reg_t; - -/** Type of dt1_fed_cfg register - * Shadow register for falling edge delay (FED). - */ -typedef union { - struct { - /** db1_fed : R/W; bitpos: [15:0]; default: 0; - * Shadow register for FED - */ - uint32_t db1_fed:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_dt1_fed_cfg_reg_t; - -/** Type of dt1_red_cfg register - * Shadow register for rising edge delay (RED). - */ -typedef union { - struct { - /** db1_red : R/W; bitpos: [15:0]; default: 0; - * Shadow register for RED - */ - uint32_t db1_red:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_dt1_red_cfg_reg_t; - -/** Type of carrier1_cfg register - * Carrier enable and configuration - */ -typedef union { - struct { - /** chopper1_en : R/W; bitpos: [0]; default: 0; - * When set, carrier1 function is enabled. When cleared, carrier1 is bypassed - */ - uint32_t chopper1_en:1; - /** chopper1_prescale : R/W; bitpos: [4:1]; default: 0; - * PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * - * (PWM_CARRIER0_PRESCALE + 1) - */ - uint32_t chopper1_prescale:4; - /** chopper1_duty : R/W; bitpos: [7:5]; default: 0; - * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 - */ - uint32_t chopper1_duty:3; - /** chopper1_oshtwth : R/W; bitpos: [11:8]; default: 0; - * width of the first pulse in number of periods of the carrier - */ - uint32_t chopper1_oshtwth:4; - /** chopper1_out_invert : R/W; bitpos: [12]; default: 0; - * when set, invert the output of PWM1A and PWM1B for this submodule - */ - uint32_t chopper1_out_invert:1; - /** chopper1_in_invert : R/W; bitpos: [13]; default: 0; - * when set, invert the input of PWM1A and PWM1B for this submodule - */ - uint32_t chopper1_in_invert:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} mcpwm_carrier1_cfg_reg_t; - -/** Type of fh1_cfg0 register - * Actions on PWM1A and PWM1B trip events - */ -typedef union { - struct { - /** tz1_sw_cbc : R/W; bitpos: [0]; default: 0; - * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable - */ - uint32_t tz1_sw_cbc:1; - /** tz1_f2_cbc : R/W; bitpos: [1]; default: 0; - * event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable - */ - uint32_t tz1_f2_cbc:1; - /** tz1_f1_cbc : R/W; bitpos: [2]; default: 0; - * event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable - */ - uint32_t tz1_f1_cbc:1; - /** tz1_f0_cbc : R/W; bitpos: [3]; default: 0; - * event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable - */ - uint32_t tz1_f0_cbc:1; - /** tz1_sw_ost : R/W; bitpos: [4]; default: 0; - * Enable register for software force one-shot mode action. 0: disable, 1: enable - */ - uint32_t tz1_sw_ost:1; - /** tz1_f2_ost : R/W; bitpos: [5]; default: 0; - * event_f2 will trigger one-shot mode action. 0: disable, 1: enable - */ - uint32_t tz1_f2_ost:1; - /** tz1_f1_ost : R/W; bitpos: [6]; default: 0; - * event_f1 will trigger one-shot mode action. 0: disable, 1: enable - */ - uint32_t tz1_f1_ost:1; - /** tz1_f0_ost : R/W; bitpos: [7]; default: 0; - * event_f0 will trigger one-shot mode action. 0: disable, 1: enable - */ - uint32_t tz1_f0_ost:1; - /** tz1_a_cbc_d : R/W; bitpos: [9:8]; default: 0; - * Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is - * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz1_a_cbc_d:2; - /** tz1_a_cbc_u : R/W; bitpos: [11:10]; default: 0; - * Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is - * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz1_a_cbc_u:2; - /** tz1_a_ost_d : R/W; bitpos: [13:12]; default: 0; - * One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: - * do nothing,1: force low, 2: force high, 3: toggle - */ - uint32_t tz1_a_ost_d:2; - /** tz1_a_ost_u : R/W; bitpos: [15:14]; default: 0; - * One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: - * do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz1_a_ost_u:2; - /** tz1_b_cbc_d : R/W; bitpos: [17:16]; default: 0; - * Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is - * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz1_b_cbc_d:2; - /** tz1_b_cbc_u : R/W; bitpos: [19:18]; default: 0; - * Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is - * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz1_b_cbc_u:2; - /** tz1_b_ost_d : R/W; bitpos: [21:20]; default: 0; - * One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: - * do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz1_b_ost_d:2; - /** tz1_b_ost_u : R/W; bitpos: [23:22]; default: 0; - * One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: - * do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz1_b_ost_u:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} mcpwm_fh1_cfg0_reg_t; - -/** Type of fh1_cfg1 register - * Software triggers for fault handler actions - */ -typedef union { - struct { - /** tz1_clr_ost : R/W; bitpos: [0]; default: 0; - * a rising edge will clear on going one-shot mode action - */ - uint32_t tz1_clr_ost:1; - /** tz1_cbcpulse : R/W; bitpos: [2:1]; default: 0; - * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, - * when bit1 is set to 1:TEP - */ - uint32_t tz1_cbcpulse:2; - /** tz1_force_cbc : R/W; bitpos: [3]; default: 0; - * a toggle trigger a cycle-by-cycle mode action - */ - uint32_t tz1_force_cbc:1; - /** tz1_force_ost : R/W; bitpos: [4]; default: 0; - * a toggle (software negate its value) triggers a one-shot mode action - */ - uint32_t tz1_force_ost:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} mcpwm_fh1_cfg1_reg_t; - -/** Type of fh1_status register - * Status of fault events. - */ -typedef union { - struct { - /** tz1_cbc_on : RO; bitpos: [0]; default: 0; - * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going - */ - uint32_t tz1_cbc_on:1; - /** tz1_ost_on : RO; bitpos: [1]; default: 0; - * Set and reset by hardware. If set, an one-shot mode action is on going - */ - uint32_t tz1_ost_on:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} mcpwm_fh1_status_reg_t; - -/** Type of fh2_status register - * Status of fault events. - */ -typedef union { - struct { - /** tz2_cbc_on : RO; bitpos: [0]; default: 0; - * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going - */ - uint32_t tz2_cbc_on:1; - /** tz2_ost_on : RO; bitpos: [1]; default: 0; - * Set and reset by hardware. If set, an one-shot mode action is on going - */ - uint32_t tz2_ost_on:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} mcpwm_fh2_status_reg_t; - - -/** Group: MCPWM Operator 2 Configuration and Status */ -/** Type of gen2_stmp_cfg register - * Transfer status and update method for time stamp registers A and B - */ -typedef union { - struct { - /** cmpr2_a_upmethod : R/W; bitpos: [3:0]; default: 0; - * Update method for PWM generator 2 time stamp A's active register. When all bits are - * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when - * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. - */ - uint32_t cmpr2_a_upmethod:4; - /** cmpr2_b_upmethod : R/W; bitpos: [7:4]; default: 0; - * Update method for PWM generator 2 time stamp B's active register. When all bits are - * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when - * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. - */ - uint32_t cmpr2_b_upmethod:4; - /** cmpr2_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; - * Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is - * filled and waiting to be transferred to A's active reg. If cleared, A's active reg - * has been updated with shadow register latest value - */ - uint32_t cmpr2_a_shdw_full:1; - /** cmpr2_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; - * Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is - * filled and waiting to be transferred to B's active reg. If cleared, B's active reg - * has been updated with shadow register latest value - */ - uint32_t cmpr2_b_shdw_full:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} mcpwm_gen2_stmp_cfg_reg_t; - -/** Type of gen2_tstmp_a register - * Shadow register for register A. - */ -typedef union { - struct { - /** cmpr2_a : R/W; bitpos: [15:0]; default: 0; - * PWM generator 2 time stamp A's shadow register - */ - uint32_t cmpr2_a:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_gen2_tstmp_a_reg_t; - -/** Type of gen2_tstmp_b register - * Shadow register for register B. - */ -typedef union { - struct { - /** cmpr2_b : R/W; bitpos: [15:0]; default: 0; - * PWM generator 2 time stamp B's shadow register - */ - uint32_t cmpr2_b:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_gen2_tstmp_b_reg_t; - -/** Type of gen2_cfg0 register - * Fault event T0 and T1 handling - */ -typedef union { - struct { - /** gen2_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; - * Update method for PWM generator 2's active register of configuration. 0: - * immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is - * set to 1:disable the update. - */ - uint32_t gen2_cfg_upmethod:4; - /** gen2_t0_sel : R/W; bitpos: [6:4]; default: 0; - * Source selection for PWM generator 2 event_t0, take effect immediately, 0: - * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none - */ - uint32_t gen2_t0_sel:3; - /** gen2_t1_sel : R/W; bitpos: [9:7]; default: 0; - * Source selection for PWM generator 2 event_t1, take effect immediately, 0: - * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none - */ - uint32_t gen2_t1_sel:3; - uint32_t reserved_10:22; - }; - uint32_t val; -} mcpwm_gen2_cfg0_reg_t; - -/** Type of gen2_force register - * Permissives to force PWM2A and PWM2B outputs by software - */ -typedef union { - struct { - /** gen2_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; - * Updating method for continuous software force of PWM generator 2. When all bits are - * set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when - * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, - * when bit5 is set to 1: disable update. (TEA/B here and below means an event - * generated when the timer's value equals to that of register A/B.) - */ - uint32_t gen2_cntuforce_upmethod:6; - /** gen2_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; - * Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled - */ - uint32_t gen2_a_cntuforce_mode:2; - /** gen2_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; - * Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled - */ - uint32_t gen2_b_cntuforce_mode:2; - /** gen2_a_nciforce : R/W; bitpos: [10]; default: 0; - * Trigger of non-continuous immediate software-force event for PWM2A, a toggle will - * trigger a force event. - */ - uint32_t gen2_a_nciforce:1; - /** gen2_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; - * non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: - * high, 3: disabled - */ - uint32_t gen2_a_nciforce_mode:2; - /** gen2_b_nciforce : R/W; bitpos: [13]; default: 0; - * Trigger of non-continuous immediate software-force event for PWM2B, a toggle will - * trigger a force event. - */ - uint32_t gen2_b_nciforce:1; - /** gen2_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; - * non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: - * high, 3: disabled - */ - uint32_t gen2_b_nciforce_mode:2; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_gen2_force_reg_t; - -/** Type of gen2_a register - * Actions triggered by events on PWM2A - */ -typedef union { - struct { - /** gen2_a_utez : R/W; bitpos: [1:0]; default: 0; - * Action on PWM2A triggered by event TEZ when timer increasing - */ - uint32_t gen2_a_utez:2; - /** gen2_a_utep : R/W; bitpos: [3:2]; default: 0; - * Action on PWM2A triggered by event TEP when timer increasing - */ - uint32_t gen2_a_utep:2; - /** gen2_a_utea : R/W; bitpos: [5:4]; default: 0; - * Action on PWM2A triggered by event TEA when timer increasing - */ - uint32_t gen2_a_utea:2; - /** gen2_a_uteb : R/W; bitpos: [7:6]; default: 0; - * Action on PWM2A triggered by event TEB when timer increasing - */ - uint32_t gen2_a_uteb:2; - /** gen2_a_ut0 : R/W; bitpos: [9:8]; default: 0; - * Action on PWM2A triggered by event_t0 when timer increasing - */ - uint32_t gen2_a_ut0:2; - /** gen2_a_ut1 : R/W; bitpos: [11:10]; default: 0; - * Action on PWM2A triggered by event_t1 when timer increasing - */ - uint32_t gen2_a_ut1:2; - /** gen2_a_dtez : R/W; bitpos: [13:12]; default: 0; - * Action on PWM2A triggered by event TEZ when timer decreasing - */ - uint32_t gen2_a_dtez:2; - /** gen2_a_dtep : R/W; bitpos: [15:14]; default: 0; - * Action on PWM2A triggered by event TEP when timer decreasing - */ - uint32_t gen2_a_dtep:2; - /** gen2_a_dtea : R/W; bitpos: [17:16]; default: 0; - * Action on PWM2A triggered by event TEA when timer decreasing - */ - uint32_t gen2_a_dtea:2; - /** gen2_a_dteb : R/W; bitpos: [19:18]; default: 0; - * Action on PWM2A triggered by event TEB when timer decreasing - */ - uint32_t gen2_a_dteb:2; - /** gen2_a_dt0 : R/W; bitpos: [21:20]; default: 0; - * Action on PWM2A triggered by event_t0 when timer decreasing - */ - uint32_t gen2_a_dt0:2; - /** gen2_a_dt1 : R/W; bitpos: [23:22]; default: 0; - * Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, - * 2: high, 3: toggle - */ - uint32_t gen2_a_dt1:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} mcpwm_gen2_a_reg_t; - -/** Type of gen2_b register - * Actions triggered by events on PWM2B - */ -typedef union { - struct { - /** gen2_b_utez : R/W; bitpos: [1:0]; default: 0; - * Action on PWM2B triggered by event TEZ when timer increasing - */ - uint32_t gen2_b_utez:2; - /** gen2_b_utep : R/W; bitpos: [3:2]; default: 0; - * Action on PWM2B triggered by event TEP when timer increasing - */ - uint32_t gen2_b_utep:2; - /** gen2_b_utea : R/W; bitpos: [5:4]; default: 0; - * Action on PWM2B triggered by event TEA when timer increasing - */ - uint32_t gen2_b_utea:2; - /** gen2_b_uteb : R/W; bitpos: [7:6]; default: 0; - * Action on PWM2B triggered by event TEB when timer increasing - */ - uint32_t gen2_b_uteb:2; - /** gen2_b_ut0 : R/W; bitpos: [9:8]; default: 0; - * Action on PWM2B triggered by event_t0 when timer increasing - */ - uint32_t gen2_b_ut0:2; - /** gen2_b_ut1 : R/W; bitpos: [11:10]; default: 0; - * Action on PWM2B triggered by event_t1 when timer increasing - */ - uint32_t gen2_b_ut1:2; - /** gen2_b_dtez : R/W; bitpos: [13:12]; default: 0; - * Action on PWM2B triggered by event TEZ when timer decreasing - */ - uint32_t gen2_b_dtez:2; - /** gen2_b_dtep : R/W; bitpos: [15:14]; default: 0; - * Action on PWM2B triggered by event TEP when timer decreasing - */ - uint32_t gen2_b_dtep:2; - /** gen2_b_dtea : R/W; bitpos: [17:16]; default: 0; - * Action on PWM2B triggered by event TEA when timer decreasing - */ - uint32_t gen2_b_dtea:2; - /** gen2_b_dteb : R/W; bitpos: [19:18]; default: 0; - * Action on PWM2B triggered by event TEB when timer decreasing - */ - uint32_t gen2_b_dteb:2; - /** gen2_b_dt0 : R/W; bitpos: [21:20]; default: 0; - * Action on PWM2B triggered by event_t0 when timer decreasing - */ - uint32_t gen2_b_dt0:2; - /** gen2_b_dt1 : R/W; bitpos: [23:22]; default: 0; - * Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, - * 2: high, 3: toggle - */ - uint32_t gen2_b_dt1:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} mcpwm_gen2_b_reg_t; - -/** Type of dt2_cfg register - * dead time type selection and configuration - */ -typedef union { - struct { - /** db2_fed_upmethod : R/W; bitpos: [3:0]; default: 0; - * Update method for FED (falling edge delay) active register. 0: immediate,when bit0 - * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when - * bit3 is set to 1: disable the update - */ - uint32_t db2_fed_upmethod:4; - /** db2_red_upmethod : R/W; bitpos: [7:4]; default: 0; - * Update method for RED (rising edge delay) active register. 0: immediate,when bit0 - * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when - * bit3 is set to 1: disable the update - */ - uint32_t db2_red_upmethod:4; - /** db2_deb_mode : R/W; bitpos: [8]; default: 0; - * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, - * 1: fed/red take effect on B path, A out is in bypass or dulpB mode - */ - uint32_t db2_deb_mode:1; - /** db2_a_outswap : R/W; bitpos: [9]; default: 0; - * S6 in table - */ - uint32_t db2_a_outswap:1; - /** db2_b_outswap : R/W; bitpos: [10]; default: 0; - * S7 in table - */ - uint32_t db2_b_outswap:1; - /** db2_red_insel : R/W; bitpos: [11]; default: 0; - * S4 in table - */ - uint32_t db2_red_insel:1; - /** db2_fed_insel : R/W; bitpos: [12]; default: 0; - * S5 in table - */ - uint32_t db2_fed_insel:1; - /** db2_red_outinvert : R/W; bitpos: [13]; default: 0; - * S2 in table - */ - uint32_t db2_red_outinvert:1; - /** db2_fed_outinvert : R/W; bitpos: [14]; default: 0; - * S3 in table - */ - uint32_t db2_fed_outinvert:1; - /** db2_a_outbypass : R/W; bitpos: [15]; default: 1; - * S1 in table - */ - uint32_t db2_a_outbypass:1; - /** db2_b_outbypass : R/W; bitpos: [16]; default: 1; - * S0 in table - */ - uint32_t db2_b_outbypass:1; - /** db2_clk_sel : R/W; bitpos: [17]; default: 0; - * Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk - */ - uint32_t db2_clk_sel:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} mcpwm_dt2_cfg_reg_t; - -/** Type of dt2_fed_cfg register - * Shadow register for falling edge delay (FED). - */ -typedef union { - struct { - /** db2_fed : R/W; bitpos: [15:0]; default: 0; - * Shadow register for FED - */ - uint32_t db2_fed:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_dt2_fed_cfg_reg_t; - -/** Type of dt2_red_cfg register - * Shadow register for rising edge delay (RED). - */ -typedef union { - struct { - /** db2_red : R/W; bitpos: [15:0]; default: 0; - * Shadow register for RED - */ - uint32_t db2_red:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_dt2_red_cfg_reg_t; - -/** Type of carrier2_cfg register - * Carrier enable and configuration - */ -typedef union { - struct { - /** chopper2_en : R/W; bitpos: [0]; default: 0; - * When set, carrier2 function is enabled. When cleared, carrier2 is bypassed - */ - uint32_t chopper2_en:1; - /** chopper2_prescale : R/W; bitpos: [4:1]; default: 0; - * PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * - * (PWM_CARRIER0_PRESCALE + 1) - */ - uint32_t chopper2_prescale:4; - /** chopper2_duty : R/W; bitpos: [7:5]; default: 0; - * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 - */ - uint32_t chopper2_duty:3; - /** chopper2_oshtwth : R/W; bitpos: [11:8]; default: 0; - * width of the first pulse in number of periods of the carrier - */ - uint32_t chopper2_oshtwth:4; - /** chopper2_out_invert : R/W; bitpos: [12]; default: 0; - * when set, invert the output of PWM2A and PWM2B for this submodule - */ - uint32_t chopper2_out_invert:1; - /** chopper2_in_invert : R/W; bitpos: [13]; default: 0; - * when set, invert the input of PWM2A and PWM2B for this submodule - */ - uint32_t chopper2_in_invert:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} mcpwm_carrier2_cfg_reg_t; - -/** Type of fh2_cfg0 register - * Actions on PWM2A and PWM2B trip events - */ -typedef union { - struct { - /** tz2_sw_cbc : R/W; bitpos: [0]; default: 0; - * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable - */ - uint32_t tz2_sw_cbc:1; - /** tz2_f2_cbc : R/W; bitpos: [1]; default: 0; - * event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable - */ - uint32_t tz2_f2_cbc:1; - /** tz2_f1_cbc : R/W; bitpos: [2]; default: 0; - * event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable - */ - uint32_t tz2_f1_cbc:1; - /** tz2_f0_cbc : R/W; bitpos: [3]; default: 0; - * event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable - */ - uint32_t tz2_f0_cbc:1; - /** tz2_sw_ost : R/W; bitpos: [4]; default: 0; - * Enable register for software force one-shot mode action. 0: disable, 1: enable - */ - uint32_t tz2_sw_ost:1; - /** tz2_f2_ost : R/W; bitpos: [5]; default: 0; - * event_f2 will trigger one-shot mode action. 0: disable, 1: enable - */ - uint32_t tz2_f2_ost:1; - /** tz2_f1_ost : R/W; bitpos: [6]; default: 0; - * event_f1 will trigger one-shot mode action. 0: disable, 1: enable - */ - uint32_t tz2_f1_ost:1; - /** tz2_f0_ost : R/W; bitpos: [7]; default: 0; - * event_f0 will trigger one-shot mode action. 0: disable, 1: enable - */ - uint32_t tz2_f0_ost:1; - /** tz2_a_cbc_d : R/W; bitpos: [9:8]; default: 0; - * Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is - * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz2_a_cbc_d:2; - /** tz2_a_cbc_u : R/W; bitpos: [11:10]; default: 0; - * Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is - * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz2_a_cbc_u:2; - /** tz2_a_ost_d : R/W; bitpos: [13:12]; default: 0; - * One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: - * do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz2_a_ost_d:2; - /** tz2_a_ost_u : R/W; bitpos: [15:14]; default: 0; - * One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: - * do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz2_a_ost_u:2; - /** tz2_b_cbc_d : R/W; bitpos: [17:16]; default: 0; - * Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is - * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz2_b_cbc_d:2; - /** tz2_b_cbc_u : R/W; bitpos: [19:18]; default: 0; - * Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is - * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz2_b_cbc_u:2; - /** tz2_b_ost_d : R/W; bitpos: [21:20]; default: 0; - * One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: - * do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz2_b_ost_d:2; - /** tz2_b_ost_u : R/W; bitpos: [23:22]; default: 0; - * One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: - * do nothing, 1: force low, 2: force high, 3: toggle - */ - uint32_t tz2_b_ost_u:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} mcpwm_fh2_cfg0_reg_t; - -/** Type of fh2_cfg1 register - * Software triggers for fault handler actions - */ -typedef union { - struct { - /** tz2_clr_ost : R/W; bitpos: [0]; default: 0; - * a rising edge will clear on going one-shot mode action - */ - uint32_t tz2_clr_ost:1; - /** tz2_cbcpulse : R/W; bitpos: [2:1]; default: 0; - * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, - * when bit1 is set to 1:TEP - */ - uint32_t tz2_cbcpulse:2; - /** tz2_force_cbc : R/W; bitpos: [3]; default: 0; - * a toggle trigger a cycle-by-cycle mode action - */ - uint32_t tz2_force_cbc:1; - /** tz2_force_ost : R/W; bitpos: [4]; default: 0; - * a toggle (software negate its value) triggers a one-shot mode action - */ - uint32_t tz2_force_ost:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} mcpwm_fh2_cfg1_reg_t; +} mcpwm_fh_status_reg_t; /** Group: Fault Detection Configuration and Status */ @@ -1999,143 +718,51 @@ typedef union { uint32_t val; } mcpwm_cap_timer_phase_reg_t; -/** Type of cap_ch0_cfg register - * Capture channel 0 configuration and enable +/** Type of cap_chn_cfg register + * Capture channel n configuration and enable */ typedef union { struct { - /** cap0_en : R/W; bitpos: [0]; default: 0; + /** capn_en : R/W; bitpos: [0]; default: 0; * When set, capture on channel 0 is enabled */ - uint32_t cap0_en:1; - /** cap0_mode : R/W; bitpos: [2:1]; default: 0; - * Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable + uint32_t capn_en:1; + /** capn_mode : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel n after prescaling. When bit0 is set to 1: enable * capture on the negative edge, When bit1 is set to 1: enable capture on the positive * edge. */ - uint32_t cap0_mode:2; - /** cap0_prescale : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on positive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + + uint32_t capn_mode:2; + /** capn_prescale : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on positive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE + * 1 */ - uint32_t cap0_prescale:8; - /** cap0_in_invert : R/W; bitpos: [11]; default: 0; - * when set, CAP0 form GPIO matrix is inverted before prescale + uint32_t capn_prescale:8; + /** capn_in_invert : R/W; bitpos: [11]; default: 0; + * when set, CAPn form GPIO matrix is inverted before prescale */ - uint32_t cap0_in_invert:1; - /** cap0_sw : WT; bitpos: [12]; default: 0; - * Write 1 will trigger a software forced capture on channel 0 + uint32_t capn_in_invert:1; + /** capn_sw : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel n */ - uint32_t cap0_sw:1; + uint32_t capn_sw:1; uint32_t reserved_13:19; }; uint32_t val; -} mcpwm_cap_ch0_cfg_reg_t; +} mcpwm_cap_chn_cfg_reg_t; -/** Type of cap_ch1_cfg register - * Capture channel 1 configuration and enable +/** Type of cap_chn register + * chn capture value status register */ typedef union { struct { - /** cap1_en : R/W; bitpos: [0]; default: 0; - * When set, capture on channel 2 is enabled + /** capn_value : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel n */ - uint32_t cap1_en:1; - /** cap1_mode : R/W; bitpos: [2:1]; default: 0; - * Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable - * capture on the negative edge, When bit1 is set to 1: enable capture on the positive - * edge. - */ - uint32_t cap1_mode:2; - /** cap1_prescale : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on positive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + - * 1 - */ - uint32_t cap1_prescale:8; - /** cap1_in_invert : R/W; bitpos: [11]; default: 0; - * when set, CAP1 form GPIO matrix is inverted before prescale - */ - uint32_t cap1_in_invert:1; - /** cap1_sw : WT; bitpos: [12]; default: 0; - * Write 1 will trigger a software forced capture on channel 1 - */ - uint32_t cap1_sw:1; - uint32_t reserved_13:19; + uint32_t capn_value:32; }; uint32_t val; -} mcpwm_cap_ch1_cfg_reg_t; - -/** Type of cap_ch2_cfg register - * Capture channel 2 configuration and enable - */ -typedef union { - struct { - /** cap2_en : R/W; bitpos: [0]; default: 0; - * When set, capture on channel 2 is enabled - */ - uint32_t cap2_en:1; - /** cap2_mode : R/W; bitpos: [2:1]; default: 0; - * Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable - * capture on the negative edge, When bit1 is set to 1: enable capture on the positive - * edge. - */ - uint32_t cap2_mode:2; - /** cap2_prescale : R/W; bitpos: [10:3]; default: 0; - * Value of prescaling on positive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + - * 1 - */ - uint32_t cap2_prescale:8; - /** cap2_in_invert : R/W; bitpos: [11]; default: 0; - * when set, CAP2 form GPIO matrix is inverted before prescale - */ - uint32_t cap2_in_invert:1; - /** cap2_sw : WT; bitpos: [12]; default: 0; - * Write 1 will trigger a software forced capture on channel 2 - */ - uint32_t cap2_sw:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} mcpwm_cap_ch2_cfg_reg_t; - -/** Type of cap_ch0 register - * ch0 capture value status register - */ -typedef union { - struct { - /** cap0_value : RO; bitpos: [31:0]; default: 0; - * Value of last capture on channel 0 - */ - uint32_t cap0_value:32; - }; - uint32_t val; -} mcpwm_cap_ch0_reg_t; - -/** Type of cap_ch1 register - * ch1 capture value status register - */ -typedef union { - struct { - /** cap1_value : RO; bitpos: [31:0]; default: 0; - * Value of last capture on channel 1 - */ - uint32_t cap1_value:32; - }; - uint32_t val; -} mcpwm_cap_ch1_reg_t; - -/** Type of cap_ch2 register - * ch2 capture value status register - */ -typedef union { - struct { - /** cap2_value : RO; bitpos: [31:0]; default: 0; - * Value of last capture on channel 2 - */ - uint32_t cap2_value:32; - }; - uint32_t val; -} mcpwm_cap_ch2_reg_t; +} mcpwm_cap_chn_reg_t; /** Type of cap_status register * Edge of last capture trigger @@ -3011,74 +1638,39 @@ typedef union { uint32_t val; } mcpwm_version_reg_t; +typedef struct { + mcpwm_timer_cfg0_reg_t timer_cfg0; + mcpwm_timer_cfg1_reg_t timer_cfg1; + mcpwm_timer_sync_reg_t timer_sync; + mcpwm_timer_status_reg_t timer_status; +} mcpwm_timer_regs_t; typedef struct { + mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg; + mcpwm_gen_tstmp_reg_t timestamp[2]; + mcpwm_gen_cfg0_reg_t gen_cfg0; + mcpwm_gen_force_reg_t gen_force; + mcpwm_gen_reg_t generator[2]; + mcpwm_dt_cfg_reg_t dt_cfg; + mcpwm_dt_fed_cfg_reg_t dt_fed_cfg; + mcpwm_dt_red_cfg_reg_t dt_red_cfg; + mcpwm_carrier_cfg_reg_t carrier_cfg; + mcpwm_fh_cfg0_reg_t fh_cfg0; + mcpwm_fh_cfg1_reg_t fh_cfg1; + mcpwm_fh_status_reg_t fh_status; +} mcpwm_operator_reg_t; + +typedef struct mcpwm_dev_t { volatile mcpwm_clk_cfg_reg_t clk_cfg; - volatile mcpwm_timer0_cfg0_reg_t timer0_cfg0; - volatile mcpwm_timer0_cfg1_reg_t timer0_cfg1; - volatile mcpwm_timer0_sync_reg_t timer0_sync; - volatile mcpwm_timer0_status_reg_t timer0_status; - volatile mcpwm_timer1_cfg0_reg_t timer1_cfg0; - volatile mcpwm_timer1_cfg1_reg_t timer1_cfg1; - volatile mcpwm_timer1_sync_reg_t timer1_sync; - volatile mcpwm_timer1_status_reg_t timer1_status; - volatile mcpwm_timer2_cfg0_reg_t timer2_cfg0; - volatile mcpwm_timer2_cfg1_reg_t timer2_cfg1; - volatile mcpwm_timer2_sync_reg_t timer2_sync; - volatile mcpwm_timer2_status_reg_t timer2_status; + volatile mcpwm_timer_regs_t timer[3]; volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg; volatile mcpwm_operator_timersel_reg_t operator_timersel; - volatile mcpwm_gen0_stmp_cfg_reg_t gen0_stmp_cfg; - volatile mcpwm_gen0_tstmp_a_reg_t gen0_tstmp_a; - volatile mcpwm_gen0_tstmp_b_reg_t gen0_tstmp_b; - volatile mcpwm_gen0_cfg0_reg_t gen0_cfg0; - volatile mcpwm_gen0_force_reg_t gen0_force; - volatile mcpwm_gen0_a_reg_t gen0_a; - volatile mcpwm_gen0_b_reg_t gen0_b; - volatile mcpwm_dt0_cfg_reg_t dt0_cfg; - volatile mcpwm_dt0_fed_cfg_reg_t dt0_fed_cfg; - volatile mcpwm_dt0_red_cfg_reg_t dt0_red_cfg; - volatile mcpwm_carrier0_cfg_reg_t carrier0_cfg; - volatile mcpwm_fh0_cfg0_reg_t fh0_cfg0; - volatile mcpwm_fh0_cfg1_reg_t fh0_cfg1; - volatile mcpwm_fh0_status_reg_t fh0_status; - volatile mcpwm_gen1_stmp_cfg_reg_t gen1_stmp_cfg; - volatile mcpwm_gen1_tstmp_a_reg_t gen1_tstmp_a; - volatile mcpwm_gen1_tstmp_b_reg_t gen1_tstmp_b; - volatile mcpwm_gen1_cfg0_reg_t gen1_cfg0; - volatile mcpwm_gen1_force_reg_t gen1_force; - volatile mcpwm_gen1_a_reg_t gen1_a; - volatile mcpwm_gen1_b_reg_t gen1_b; - volatile mcpwm_dt1_cfg_reg_t dt1_cfg; - volatile mcpwm_dt1_fed_cfg_reg_t dt1_fed_cfg; - volatile mcpwm_dt1_red_cfg_reg_t dt1_red_cfg; - volatile mcpwm_carrier1_cfg_reg_t carrier1_cfg; - volatile mcpwm_fh1_cfg0_reg_t fh1_cfg0; - volatile mcpwm_fh1_cfg1_reg_t fh1_cfg1; - volatile mcpwm_fh1_status_reg_t fh1_status; - volatile mcpwm_gen2_stmp_cfg_reg_t gen2_stmp_cfg; - volatile mcpwm_gen2_tstmp_a_reg_t gen2_tstmp_a; - volatile mcpwm_gen2_tstmp_b_reg_t gen2_tstmp_b; - volatile mcpwm_gen2_cfg0_reg_t gen2_cfg0; - volatile mcpwm_gen2_force_reg_t gen2_force; - volatile mcpwm_gen2_a_reg_t gen2_a; - volatile mcpwm_gen2_b_reg_t gen2_b; - volatile mcpwm_dt2_cfg_reg_t dt2_cfg; - volatile mcpwm_dt2_fed_cfg_reg_t dt2_fed_cfg; - volatile mcpwm_dt2_red_cfg_reg_t dt2_red_cfg; - volatile mcpwm_carrier2_cfg_reg_t carrier2_cfg; - volatile mcpwm_fh2_cfg0_reg_t fh2_cfg0; - volatile mcpwm_fh2_cfg1_reg_t fh2_cfg1; - volatile mcpwm_fh2_status_reg_t fh2_status; + volatile mcpwm_operator_reg_t operators[3]; volatile mcpwm_fault_detect_reg_t fault_detect; volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg; volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase; - volatile mcpwm_cap_ch0_cfg_reg_t cap_ch0_cfg; - volatile mcpwm_cap_ch1_cfg_reg_t cap_ch1_cfg; - volatile mcpwm_cap_ch2_cfg_reg_t cap_ch2_cfg; - volatile mcpwm_cap_ch0_reg_t cap_ch0; - volatile mcpwm_cap_ch1_reg_t cap_ch1; - volatile mcpwm_cap_ch2_reg_t cap_ch2; + volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3]; + volatile mcpwm_cap_chn_reg_t cap_chn[3]; volatile mcpwm_cap_status_reg_t cap_status; volatile mcpwm_update_cfg_reg_t update_cfg; volatile mcpwm_int_ena_reg_t int_ena; diff --git a/components/soc/esp32h21/register/soc/reg_base.h b/components/soc/esp32h21/register/soc/reg_base.h index 2a162986b2..ad604684d3 100644 --- a/components/soc/esp32h21/register/soc/reg_base.h +++ b/components/soc/esp32h21/register/soc/reg_base.h @@ -25,7 +25,7 @@ #define DR_REG_INTMTX_BASE 0x60010000 #define DR_REG_PCNT_BASE 0x60012000 #define DR_REG_SOC_ETM_BASE 0x60013000 -#define DR_REG_MCPWM0_BASE 0x60014000 +#define DR_REG_MCPWM_BASE 0x60014000 #define DR_REG_PARL_IO_BASE 0x60015000 #define DR_REG_PVT_BASE 0x60019000 #define DR_REG_GDMA_BASE 0x60080000 diff --git a/components/soc/esp32h21/sdm_periph.c b/components/soc/esp32h21/sdm_periph.c index 1ffb2944be..19f5b6bfe8 100644 --- a/components/soc/esp32h21/sdm_periph.c +++ b/components/soc/esp32h21/sdm_periph.c @@ -30,12 +30,12 @@ const soc_sdm_signal_desc_t soc_sdm_signals[1] = { /** * @brief Registers in retention context: - * GPIO_EXT_SIGMADELTA[x]_REG * GPIO_EXT_SIGMADELTA_MISC_REG + * GPIO_EXT_SIGMADELTA[x]_REG */ #define GPIO_EXT_RETENTION_REGS_CNT 5 -#define GPIO_EXT_RETENTION_REGS_BASE (DR_REG_GPIO_EXT_BASE + 0x0) -static const uint32_t gpio_ext_regs_map[4] = {0x20f, 0x0, 0x0, 0x0}; +#define GPIO_EXT_RETENTION_REGS_BASE (DR_REG_GPIO_EXT_BASE + 0x4) +static const uint32_t gpio_ext_regs_map[4] = {0x1f, 0x0, 0x0, 0x0}; static const regdma_entries_config_t gpio_ext_regdma_entries[] = { // backup stage: save configuration and status registers // restore stage: restore the configuration and status registers diff --git a/docs/docs_not_updated/esp32h21.txt b/docs/docs_not_updated/esp32h21.txt index 45a3736915..d24794bdd0 100644 --- a/docs/docs_not_updated/esp32h21.txt +++ b/docs/docs_not_updated/esp32h21.txt @@ -119,7 +119,6 @@ api-reference/peripherals/index.rst api-reference/peripherals/sdio_slave.rst api-reference/peripherals/temp_sensor.rst api-reference/peripherals/usb_device.rst -api-reference/peripherals/mcpwm.rst api-reference/peripherals/usb_host.rst api-reference/peripherals/camera_driver.rst api-reference/peripherals/adc_oneshot.rst diff --git a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/README.md b/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/README.md index 22681cd506..ccb002d26f 100644 --- a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/README.md +++ b/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | # MCPWM Brushed DC Motor Example (See the README.md file in the upper level 'examples' directory for more information about examples.) diff --git a/examples/peripherals/mcpwm/mcpwm_bldc_hall_control/README.md b/examples/peripherals/mcpwm/mcpwm_bldc_hall_control/README.md index 561d3df89b..ad8367ebb7 100644 --- a/examples/peripherals/mcpwm/mcpwm_bldc_hall_control/README.md +++ b/examples/peripherals/mcpwm/mcpwm_bldc_hall_control/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | # MCPWM BLDC Motor Control with HALL Sensor Example diff --git a/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/README.md b/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/README.md index 391a9ebb43..40ff93752f 100644 --- a/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/README.md +++ b/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | # HC-SR04 Example based on MCPWM Capture diff --git a/examples/peripherals/mcpwm/mcpwm_foc_svpwm_open_loop/README.md b/examples/peripherals/mcpwm/mcpwm_foc_svpwm_open_loop/README.md index 3d93d9a0f2..38a22b5087 100644 --- a/examples/peripherals/mcpwm/mcpwm_foc_svpwm_open_loop/README.md +++ b/examples/peripherals/mcpwm/mcpwm_foc_svpwm_open_loop/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | # MCPWM FOC SVPWM Generation Open Loop Example diff --git a/examples/peripherals/mcpwm/mcpwm_servo_control/README.md b/examples/peripherals/mcpwm/mcpwm_servo_control/README.md index 28289fa1c3..ea7152b9a9 100644 --- a/examples/peripherals/mcpwm/mcpwm_servo_control/README.md +++ b/examples/peripherals/mcpwm/mcpwm_servo_control/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | # MCPWM RC Servo Control Example (See the README.md file in the upper level 'examples' directory for more information about examples.) diff --git a/examples/peripherals/mcpwm/mcpwm_sync/README.md b/examples/peripherals/mcpwm/mcpwm_sync/README.md index 75bbae4cf7..606099a2bc 100644 --- a/examples/peripherals/mcpwm/mcpwm_sync/README.md +++ b/examples/peripherals/mcpwm/mcpwm_sync/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | # MCPWM Sync Example