From ca135856c1b42e715aecd530baf8dcebe2338a35 Mon Sep 17 00:00:00 2001 From: armando Date: Wed, 8 Apr 2026 15:02:27 +0800 Subject: [PATCH] fix(mmu): fixed drom/irom reservation bus cap search logic --- components/esp_mm/esp_mmu_map.c | 4 ++-- .../hal/esp32s31/include/hal/cache_ll.h | 21 ++++--------------- 2 files changed, 6 insertions(+), 19 deletions(-) diff --git a/components/esp_mm/esp_mmu_map.c b/components/esp_mm/esp_mmu_map.c index 1508d3c8bf..3c32f3a999 100644 --- a/components/esp_mm/esp_mmu_map.c +++ b/components/esp_mm/esp_mmu_map.c @@ -150,7 +150,7 @@ static void s_reserve_irom_region(mem_region_t *hw_mem_regions, int region_nums) cache_bus_mask_t bus_mask = s_get_bus_mask((uint32_t)&_instruction_reserved_start, irom_len_to_reserve); for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) { - if (bus_mask & hw_mem_regions[i].bus_id) { + if ((bus_mask & hw_mem_regions[i].bus_id) == bus_mask) { if (hw_mem_regions[i].region_size <= irom_len_to_reserve) { hw_mem_regions[i].free_head = hw_mem_regions[i].end; hw_mem_regions[i].max_slot_size = 0; @@ -178,7 +178,7 @@ static void s_reserve_drom_region(mem_region_t *hw_mem_regions, int region_nums) cache_bus_mask_t bus_mask = s_get_bus_mask((uint32_t)&_rodata_reserved_start, drom_len_to_reserve); for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) { - if (bus_mask & hw_mem_regions[i].bus_id) { + if ((bus_mask & hw_mem_regions[i].bus_id) == bus_mask) { if (hw_mem_regions[i].region_size <= drom_len_to_reserve) { hw_mem_regions[i].free_head = hw_mem_regions[i].end; hw_mem_regions[i].max_slot_size = 0; diff --git a/components/hal/esp32s31/include/hal/cache_ll.h b/components/hal/esp32s31/include/hal/cache_ll.h index b9320403fc..c6fddad4b3 100644 --- a/components/hal/esp32s31/include/hal/cache_ll.h +++ b/components/hal/esp32s31/include/hal/cache_ll.h @@ -935,11 +935,7 @@ static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask REG_CLR_BIT(CACHE_L1_ICACHE_CTRL_REG, ibus_mask); uint32_t dbus_mask = 0; - if (bus_id == 1) { - dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS0 : 0); - } else { - dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS1 : 0); - } + dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS0 : 0); REG_CLR_BIT(CACHE_L1_DCACHE_CTRL_REG, dbus_mask); } @@ -963,11 +959,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id) } uint32_t dbus_mask = REG_READ(CACHE_L1_DCACHE_CTRL_REG); - if (cache_id == 0) { - mask = (cache_bus_mask_t)(mask | ((!(dbus_mask & CACHE_L1_DCACHE_SHUT_DBUS0)) ? CACHE_BUS_DBUS0 : 0)); - } else if (cache_id == 1) { - mask = (cache_bus_mask_t)(mask | ((!(dbus_mask & CACHE_L1_DCACHE_SHUT_DBUS1)) ? CACHE_BUS_DBUS0 : 0)); - } + mask = (cache_bus_mask_t)(mask | ((!(dbus_mask & CACHE_L1_DCACHE_SHUT_DBUS0)) ? CACHE_BUS_DBUS0 : 0)); return mask; } @@ -981,8 +973,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id) __attribute__((always_inline)) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask) { - //On esp32h4, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first - HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + HAL_ASSERT((mask & (CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; if (bus_id == 0) { @@ -993,11 +984,7 @@ static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mas REG_SET_BIT(CACHE_L1_ICACHE_CTRL_REG, ibus_mask); uint32_t dbus_mask = 0; - if (bus_id == 1) { - dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS0 : 0); - } else { - dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS1 : 0); - } + dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS0 : 0); REG_SET_BIT(CACHE_L1_DCACHE_CTRL_REG, dbus_mask); }