diff --git a/components/esp_driver_gpio/include/driver/lp_io.h b/components/esp_driver_gpio/include/driver/lp_io.h
index 01673d8bae..aafc409248 100644
--- a/components/esp_driver_gpio/include/driver/lp_io.h
+++ b/components/esp_driver_gpio/include/driver/lp_io.h
@@ -36,7 +36,7 @@ esp_err_t lp_gpio_connect_in_signal(gpio_num_t gpio_num, uint32_t signal_idx, bo
  * @note There's no limitation on the number of RTC(LP) GPIOs that a signal can connect with
  *
  * @param gpio_num GPIO number
- * @param signal_idx LP peripheral signal index (tagged as input attribute), especially, `SIG_LP_GPIO_OUT_IDX` means disconnect RTC(LP) GPIO and other peripherals. Only the RTC GPIO driver can control the output level
+ * @param signal_idx LP peripheral signal index (tagged as input attribute), especially, `LP_SIG_GPIO_OUT_IDX` means disconnect RTC(LP) GPIO and other peripherals. Only the RTC GPIO driver can control the output level
  * @param out_inv Whether to signal to be inverted or not
  * @param out_en_inv Whether the output enable control is inverted or not
  * @return
diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h
index 90bdc06b8e..9b0ba1a00e 100644
--- a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h
+++ b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h
@@ -99,7 +99,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
 };
 #define TEST_RTCIO_INTR_PIN_INDEX       5 // IO6
 #define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO6
-#elif CONFIG_IDF_TARGET_ESP32C6
+#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S31
 // Has no input-only rtcio pins, all pins support pull-up/down
 #define RTCIO_SUPPORT_PU_PD(num)    1
 #define TEST_GPIO_PIN_COUNT 8
diff --git a/components/esp_driver_uart/src/uart.c b/components/esp_driver_uart/src/uart.c
index 87e106a51c..6e24273be5 100644
--- a/components/esp_driver_uart/src/uart.c
+++ b/components/esp_driver_uart/src/uart.c
@@ -923,7 +923,7 @@ esp_err_t _uart_set_pin6(uart_port_t uart_num, int tx_io_num, int rx_io_num, int
             if (uart_num < SOC_UART_HP_NUM) {
                 gpio_matrix_output(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_TX), false, false);
             }
-#if SOC_LP_GPIO_MATRIX_SUPPORTED
+#if SOC_LP_GPIO_MATRIX_SUPPORTED && (SOC_UART_LP_NUM >= 1)
             else {
                 rtc_gpio_init(tx_io_num); // set as a LP_GPIO pin
                 lp_gpio_connect_out_signal(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_TX), 0, 0);
@@ -946,7 +946,7 @@ esp_err_t _uart_set_pin6(uart_port_t uart_num, int tx_io_num, int rx_io_num, int
             if (uart_num < SOC_UART_HP_NUM) {
                 gpio_matrix_input(rx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_RX), false);
             }
-#if SOC_LP_GPIO_MATRIX_SUPPORTED
+#if SOC_LP_GPIO_MATRIX_SUPPORTED && (SOC_UART_LP_NUM >= 1)
             else {
                 rtc_gpio_mode_t mode = (tx_rx_same_io ? RTC_GPIO_MODE_INPUT_OUTPUT : RTC_GPIO_MODE_INPUT_ONLY);
                 rtc_gpio_set_direction(rx_io_num, mode);
@@ -964,7 +964,7 @@ esp_err_t _uart_set_pin6(uart_port_t uart_num, int tx_io_num, int rx_io_num, int
         if (uart_num < SOC_UART_HP_NUM) {
             gpio_matrix_output(rts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_RTS), false, false);
         }
-#if SOC_LP_GPIO_MATRIX_SUPPORTED
+#if SOC_LP_GPIO_MATRIX_SUPPORTED && (SOC_UART_LP_NUM >= 1)
         else {
             rtc_gpio_init(rts_io_num); // set as a LP_GPIO pin
             lp_gpio_connect_out_signal(rts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_RTS), 0, 0);
@@ -978,7 +978,7 @@ esp_err_t _uart_set_pin6(uart_port_t uart_num, int tx_io_num, int rx_io_num, int
         if (uart_num < SOC_UART_HP_NUM) {
             gpio_matrix_input(cts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_CTS), false);
         }
-#if SOC_LP_GPIO_MATRIX_SUPPORTED
+#if SOC_LP_GPIO_MATRIX_SUPPORTED && (SOC_UART_LP_NUM >= 1)
         else {
             rtc_gpio_set_direction(cts_io_num, RTC_GPIO_MODE_INPUT_ONLY);
             rtc_gpio_init(cts_io_num); // set as a LP_GPIO pin
@@ -991,7 +991,7 @@ esp_err_t _uart_set_pin6(uart_port_t uart_num, int tx_io_num, int rx_io_num, int
         if (uart_num < SOC_UART_HP_NUM) {
             gpio_matrix_output(dtr_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_DTR), false, false);
         }
-#if SOC_LP_GPIO_MATRIX_SUPPORTED
+#if SOC_LP_GPIO_MATRIX_SUPPORTED && (SOC_UART_LP_NUM >= 1)
         else {
             rtc_gpio_init(dtr_io_num); // set as a LP_GPIO pin
             lp_gpio_connect_out_signal(dtr_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_DTR), 0, 0);
@@ -1005,7 +1005,7 @@ esp_err_t _uart_set_pin6(uart_port_t uart_num, int tx_io_num, int rx_io_num, int
         if (uart_num < SOC_UART_HP_NUM) {
             gpio_matrix_input(dsr_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_DSR), false);
         }
-#if SOC_LP_GPIO_MATRIX_SUPPORTED
+#if SOC_LP_GPIO_MATRIX_SUPPORTED && (SOC_UART_LP_NUM >= 1)
         else {
             rtc_gpio_set_direction(dsr_io_num, RTC_GPIO_MODE_INPUT_ONLY);
             rtc_gpio_init(dsr_io_num); // set as a LP_GPIO pin
diff --git a/components/esp_driver_uart/test_apps/uart/main/test_uart.c b/components/esp_driver_uart/test_apps/uart/main/test_uart.c
index be04b9ebfb..de9c2a0045 100644
--- a/components/esp_driver_uart/test_apps/uart/main/test_uart.c
+++ b/components/esp_driver_uart/test_apps/uart/main/test_uart.c
@@ -726,7 +726,7 @@ IRAM_ATTR static void uart_signal_inject_glitch_task(void *param)
             esp_rom_gpio_connect_out_signal(tx_pin, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_TX), false, false);
 #if SOC_UART_LP_NUM > 0 && SOC_LP_GPIO_MATRIX_SUPPORTED
         } else {
-            rtcio_ll_matrix_out(rtc_gpio_num, SIG_LP_GPIO_OUT_IDX, false, false);
+            rtcio_ll_matrix_out(rtc_gpio_num, LP_SIG_GPIO_OUT_IDX, false, false);
             LP_GPIO.func_out_sel_cfg[rtc_gpio_num].oe_sel = 1;
             rtcio_ll_matrix_out(rtc_gpio_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_TX), false, false);
 #endif
diff --git a/components/esp_hal_gpio/esp32p4/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32p4/include/hal/rtc_io_ll.h
index 8348f8a5e6..a76abbcd4f 100644
--- a/components/esp_hal_gpio/esp32p4/include/hal/rtc_io_ll.h
+++ b/components/esp_hal_gpio/esp32p4/include/hal/rtc_io_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -89,7 +89,7 @@ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
     LP_IOMUX.pad[rtcio_num].fun_sel = func;
     // When using as normal (output) LP_GPIO, it is reasonable to ensure that no peripheral signal is routed to the pin
     if (func == RTCIO_LL_PIN_FUNC) {
-        LP_GPIO.func_out_sel_cfg[rtcio_num].func_out_sel = SIG_LP_GPIO_OUT_IDX;
+        LP_GPIO.func_out_sel_cfg[rtcio_num].func_out_sel = LP_SIG_GPIO_OUT_IDX;
     }
 }
 
@@ -105,11 +105,7 @@ static inline void _rtcio_ll_enable_io_clock(bool enable)
         ;
     }
 }
-
-#define rtcio_ll_enable_io_clock(...) do { \
-        (void)__DECLARE_RCC_ATOMIC_ENV; \
-        _rtcio_ll_enable_io_clock(__VA_ARGS__); \
-    } while(0)
+#define rtcio_ll_enable_io_clock(...) _rtcio_ll_enable_io_clock(__VA_ARGS__)
 
 /**
  * @brief Select the lp_gpio/hp_gpio function to control the pad.
@@ -153,7 +149,7 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
 {
     LP_GPIO.enable_w1tc.val = BIT(rtcio_num);
     // Ensure no other output signal is routed via LP_GPIO matrix to this pin
-    LP_GPIO.func_out_sel_cfg[rtcio_num].func_out_sel = SIG_LP_GPIO_OUT_IDX;
+    LP_GPIO.func_out_sel_cfg[rtcio_num].func_out_sel = LP_SIG_GPIO_OUT_IDX;
 }
 
 /**
diff --git a/components/esp_hal_gpio/esp32s31/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32s31/include/hal/rtc_gpio_caps.h
index f797d22e79..8fcac029b1 100644
--- a/components/esp_hal_gpio/esp32s31/include/hal/rtc_gpio_caps.h
+++ b/components/esp_hal_gpio/esp32s31/include/hal/rtc_gpio_caps.h
@@ -1,16 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-// TODO: [ESP32S31] IDF-14785
-// RTC GPIO capabilities are temporarily bypassed for ESP32-S31
-// This file provides stub definitions to allow the build to succeed.
-// Full RTC GPIO capabilities for ESP32-S31 need to be implemented in the future.
-
 #pragma once
 
 #define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr
 
-// TODO: [ESP32S31] IDF-14785
+#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED      1
diff --git a/components/esp_hal_gpio/esp32s31/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32s31/include/hal/rtc_io_ll.h
index 251e9b8e9e..ba5e35eba8 100644
--- a/components/esp_hal_gpio/esp32s31/include/hal/rtc_io_ll.h
+++ b/components/esp_hal_gpio/esp32s31/include/hal/rtc_io_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,16 +10,17 @@
  * See readme.md in hal/include/hal/readme.md
  ******************************************************************************/
 
-// TODO: [ESP32S31] IDF-14785
-// RTC IO LL implementation is temporarily bypassed for ESP32-S31
-// This file provides stub function declarations to allow the build to succeed.
-// Full RTC IO support for ESP32-S31 needs to be implemented in the future.
-
 #pragma once
 
 #include <stdlib.h>
 #include <stdbool.h>
 #include "soc/soc_caps.h"
+#include "soc/lp_gpio_struct.h"
+#include "soc/lp_iomux_struct.h"
+#include "soc/lp_gpio_sig_map.h"
+#include "soc/lp_system_struct.h"
+#include "soc/lp_peri_clkrst_struct.h"
+#include "soc/pmu_struct.h"
 #include "hal/gpio_types.h"
 #include "hal/misc.h"
 #include "hal/assert.h"
@@ -50,9 +51,10 @@ typedef enum {
  */
 static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
-    (void)func;
+    LP_IO_MUX.gpion[rtcio_num].gpion_mcu_sel = func;
+    if (func == RTCIO_LL_PIN_FUNC) {
+        LP_GPIO.funcn_out_sel_cfg[rtcio_num].funcn_out_sel = LP_SIG_GPIO_OUT_IDX;
+    }
 }
 
 /**
@@ -62,14 +64,18 @@ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
  */
 static inline void _rtcio_ll_enable_io_clock(bool enable)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)enable;
+    LP_PERI_CLKRST.iomux_ctrl.lp_iomux_clk_en = enable;
+    LP_GPIO.clock_gate.clk_en = enable;
+    while ((LP_PERI_CLKRST.iomux_ctrl.lp_iomux_clk_en != enable) ||
+            (LP_GPIO.clock_gate.clk_en != enable)) {
+        ;
+    }
 }
 
-#define rtcio_ll_enable_io_clock(...) do { \
-        (void)__DECLARE_RCC_ATOMIC_ENV; \
-        _rtcio_ll_enable_io_clock(__VA_ARGS__); \
-    } while(0)
+static inline void rtcio_ll_enable_io_clock(bool enable)
+{
+    _rtcio_ll_enable_io_clock(enable);
+}
 
 /**
  * @brief Select the rtcio function.
@@ -81,9 +87,16 @@ static inline void _rtcio_ll_enable_io_clock(bool enable)
  */
 static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
-    (void)func;
+    if (func == RTCIO_LL_FUNC_RTC) {
+        uint32_t sel = HAL_FORCE_READ_U32_REG_FIELD(LP_SYS.padctrl, pad_mux_sel);
+        sel |= BIT(rtcio_num);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_SYS.padctrl, pad_mux_sel, sel);
+        rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
+    } else if (func == RTCIO_LL_FUNC_DIGITAL) {
+        uint32_t sel = HAL_FORCE_READ_U32_REG_FIELD(LP_SYS.padctrl, pad_mux_sel);
+        sel &= ~BIT(rtcio_num);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_SYS.padctrl, pad_mux_sel, sel);
+    }
 }
 
 /**
@@ -93,8 +106,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
  */
 static inline void rtcio_ll_output_enable(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_GPIO.enable_w1ts.val = BIT(rtcio_num);
 }
 
 /**
@@ -104,8 +116,9 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
  */
 static inline void rtcio_ll_output_disable(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_GPIO.enable_w1tc.val = BIT(rtcio_num);
+    // Ensure no other output signal is routed via LP_GPIO matrix to this pin
+    LP_GPIO.funcn_out_sel_cfg[rtcio_num].funcn_out_sel = LP_SIG_GPIO_OUT_IDX;
 }
 
 /**
@@ -116,9 +129,11 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
  */
 static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
-    (void)level;
+    if (level) {
+        LP_GPIO.out_w1ts.val = BIT(rtcio_num);
+    } else {
+        LP_GPIO.out_w1tc.val = BIT(rtcio_num);
+    }
 }
 
 /**
@@ -128,8 +143,7 @@ static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
  */
 static inline void rtcio_ll_input_enable(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_IO_MUX.gpion[rtcio_num].gpion_fun_ie = 1;
 }
 
 /**
@@ -139,8 +153,7 @@ static inline void rtcio_ll_input_enable(int rtcio_num)
  */
 static inline void rtcio_ll_input_disable(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_IO_MUX.gpion[rtcio_num].gpion_fun_ie = 0;
 }
 
 /**
@@ -151,9 +164,7 @@ static inline void rtcio_ll_input_disable(int rtcio_num)
  */
 static inline uint32_t rtcio_ll_get_level(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
-    return 0;
+    return (HAL_FORCE_READ_U32_REG_FIELD(LP_GPIO.in, in_data_next) >> rtcio_num) & 0x1;
 }
 
 /**
@@ -164,9 +175,7 @@ static inline uint32_t rtcio_ll_get_level(int rtcio_num)
  */
 static inline void rtcio_ll_set_drive_capability(int rtcio_num, uint32_t strength)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
-    (void)strength;
+    LP_IO_MUX.gpion[rtcio_num].gpion_fun_drv = strength;
 }
 
 /**
@@ -177,9 +186,7 @@ static inline void rtcio_ll_set_drive_capability(int rtcio_num, uint32_t strengt
  */
 static inline uint32_t rtcio_ll_get_drive_capability(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
-    return 0;
+    return LP_IO_MUX.gpion[rtcio_num].gpion_fun_drv;
 }
 
 /**
@@ -190,9 +197,7 @@ static inline uint32_t rtcio_ll_get_drive_capability(int rtcio_num)
  */
 static inline void rtcio_ll_output_mode_set(int rtcio_num, rtcio_ll_out_mode_t mode)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
-    (void)mode;
+    LP_GPIO.pinn[rtcio_num].pinn_pad_driver = mode;
 }
 
 /**
@@ -202,8 +207,7 @@ static inline void rtcio_ll_output_mode_set(int rtcio_num, rtcio_ll_out_mode_t m
  */
 static inline void rtcio_ll_pullup_enable(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpu = 1;
 }
 
 /**
@@ -213,8 +217,7 @@ static inline void rtcio_ll_pullup_enable(int rtcio_num)
  */
 static inline void rtcio_ll_pullup_disable(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpu = 0;
 }
 
 /**
@@ -225,9 +228,7 @@ static inline void rtcio_ll_pullup_disable(int rtcio_num)
  */
 static inline bool rtcio_ll_is_pullup_enabled(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
-    return false;
+    return LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpu;
 }
 
 /**
@@ -237,8 +238,7 @@ static inline bool rtcio_ll_is_pullup_enabled(int rtcio_num)
  */
 static inline void rtcio_ll_pulldown_enable(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpd = 1;
 }
 
 /**
@@ -248,8 +248,7 @@ static inline void rtcio_ll_pulldown_enable(int rtcio_num)
  */
 static inline void rtcio_ll_pulldown_disable(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpd = 0;
 }
 
 /**
@@ -260,9 +259,7 @@ static inline void rtcio_ll_pulldown_disable(int rtcio_num)
  */
 static inline bool rtcio_ll_is_pulldown_enabled(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
-    return false;
+    return LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpd;
 }
 
 /**
@@ -277,8 +274,9 @@ static inline bool rtcio_ll_is_pulldown_enabled(int rtcio_num)
  */
 static inline void rtcio_ll_force_hold_enable(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    uint32_t hold = HAL_FORCE_READ_U32_REG_FIELD(LP_SYS.padctrl, pad_hold);
+    hold |= BIT(rtcio_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_SYS.padctrl, pad_hold, hold);
 }
 
 /**
@@ -289,8 +287,9 @@ static inline void rtcio_ll_force_hold_enable(int rtcio_num)
  */
 static inline void rtcio_ll_force_hold_disable(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    uint32_t hold = HAL_FORCE_READ_U32_REG_FIELD(LP_SYS.padctrl, pad_hold);
+    hold &= ~BIT(rtcio_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_SYS.padctrl, pad_hold, hold);
 }
 
 /**
@@ -303,7 +302,7 @@ static inline void rtcio_ll_force_hold_disable(int rtcio_num)
  */
 static inline void rtcio_ll_force_hold_all(void)
 {
-    // TODO: [ESP32S31] IDF-14785
+    PMU.imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
 }
 
 /**
@@ -313,7 +312,7 @@ static inline void rtcio_ll_force_hold_all(void)
  */
 static inline void rtcio_ll_force_unhold_all(void)
 {
-    // TODO: [ESP32S31] IDF-14785
+    PMU.imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
 }
 
 /**
@@ -324,9 +323,8 @@ static inline void rtcio_ll_force_unhold_all(void)
  */
 static inline void rtcio_ll_wakeup_enable(int rtcio_num, gpio_int_type_t type)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
-    (void)type;
+    LP_GPIO.pinn[rtcio_num].pinn_wakeup_enable = 1;
+    LP_GPIO.pinn[rtcio_num].pinn_int_type = type;
 }
 
 /**
@@ -336,8 +334,8 @@ static inline void rtcio_ll_wakeup_enable(int rtcio_num, gpio_int_type_t type)
  */
 static inline void rtcio_ll_wakeup_disable(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_GPIO.pinn[rtcio_num].pinn_wakeup_enable = 0;
+    LP_GPIO.pinn[rtcio_num].pinn_int_type = 0;
 }
 
 /**
@@ -348,9 +346,7 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num)
  */
 static inline void rtcio_ll_intr_enable(int rtcio_num, gpio_int_type_t type)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
-    (void)type;
+    LP_GPIO.pinn[rtcio_num].pinn_int_type = type;
 }
 
 /**
@@ -360,8 +356,7 @@ static inline void rtcio_ll_intr_enable(int rtcio_num, gpio_int_type_t type)
  */
 static inline void rtcio_ll_enable_output_in_sleep(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_IO_MUX.gpion[rtcio_num].gpion_mcu_oe = 1;
 }
 
 /**
@@ -371,8 +366,7 @@ static inline void rtcio_ll_enable_output_in_sleep(int rtcio_num)
  */
 static inline void rtcio_ll_disable_output_in_sleep(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_IO_MUX.gpion[rtcio_num].gpion_mcu_oe = 0;
 }
 
 /**
@@ -382,8 +376,7 @@ static inline void rtcio_ll_disable_output_in_sleep(int rtcio_num)
  */
 static inline void rtcio_ll_enable_input_in_sleep(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_IO_MUX.gpion[rtcio_num].gpion_mcu_ie = 1;
 }
 
 /**
@@ -393,8 +386,7 @@ static inline void rtcio_ll_enable_input_in_sleep(int rtcio_num)
  */
 static inline void rtcio_ll_disable_input_in_sleep(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_IO_MUX.gpion[rtcio_num].gpion_mcu_ie = 0;
 }
 
 /**
@@ -404,8 +396,7 @@ static inline void rtcio_ll_disable_input_in_sleep(int rtcio_num)
  */
 static inline void rtcio_ll_enable_sleep_setting(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_IO_MUX.gpion[rtcio_num].gpion_slp_sel = 1;
 }
 
 /**
@@ -415,8 +406,7 @@ static inline void rtcio_ll_enable_sleep_setting(int rtcio_num)
  */
 static inline void rtcio_ll_disable_sleep_setting(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
+    LP_IO_MUX.gpion[rtcio_num].gpion_slp_sel = 0;
 }
 
 /**
@@ -427,12 +417,8 @@ static inline void rtcio_ll_disable_sleep_setting(int rtcio_num)
  */
 static inline bool rtcio_ll_wakeup_is_enabled(int rtcio_num)
 {
-    // TODO: [ESP32S31] IDF-14785
-#if SOC_RTCIO_PIN_COUNT > 0
     HAL_ASSERT(rtcio_num >= 0 && rtcio_num < SOC_RTCIO_PIN_COUNT && "io does not support deep sleep wake-up function");
-#endif
-    (void)rtcio_num;
-    return false;
+    return LP_GPIO.pinn[rtcio_num].pinn_wakeup_enable;
 }
 
 /**
@@ -442,8 +428,7 @@ static inline bool rtcio_ll_wakeup_is_enabled(int rtcio_num)
  */
 static inline uint32_t rtcio_ll_get_interrupt_status(void)
 {
-    // TODO: [ESP32S31] IDF-14785
-    return 0;
+    return HAL_FORCE_READ_U32_REG_FIELD(LP_GPIO.status, status_interrupt);
 }
 
 /**
@@ -451,57 +436,43 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void)
  */
 static inline void rtcio_ll_clear_interrupt_status(void)
 {
-    // TODO: [ESP32S31] IDF-14785
+    LP_GPIO.status_w1tc.val = 0xFF;
 }
 
-#if SOC_LP_GPIO_MATRIX_SUPPORTED
 /**
- * @brief Select signal input from a RTC GPIO
+ * @brief Select RTC GPIO input to a signal.
  *
  * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
- * @param signal_idx LP peripheral signal index.
+ * @param signal_idx LP peripheral input signal index (0 .. IN_SIGNAL_MAX - 1).
  * @param inv True to invert input signal; False then no invert.
  */
 static inline void rtcio_ll_matrix_in(int rtcio_num, int signal_idx, bool inv)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
-    (void)signal_idx;
-    (void)inv;
+    lp_gpio_funca_in_sel_cfg_reg_t reg;
+    reg.funca_in_sel = rtcio_num;
+    reg.funca_in_inv_sel = inv;
+    reg.siga_in_sel = 1; // Signal should not bypass LP_GPIO matrix
+    LP_GPIO.funca_in_sel_cfg[signal_idx].val = reg.val;
 }
 
 /**
  * @brief Select signal output to a RTC GPIO
  *
  * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
- * @param signal_idx LP peripheral signal index.
+ * @param signal_idx Peripheral output signal index (0 .. OUT_SIGNAL_MAX - 1).
  * @param out_inv True to invert output signal; False then no invert.
  * @param oen_inv True to invert output enable signal; False then no invert.
  */
 static inline void rtcio_ll_matrix_out(int rtcio_num, int signal_idx, bool out_inv, bool oen_inv)
 {
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
-    (void)signal_idx;
-    (void)out_inv;
-    (void)oen_inv;
-}
-#endif // SOC_LP_GPIO_MATRIX_SUPPORTED
+    lp_gpio_funcn_out_sel_cfg_reg_t reg;
+    reg.funcn_out_sel = signal_idx;
+    reg.funcn_out_inv_sel = out_inv;
+    reg.funcn_oe_inv_sel = oen_inv;
+    LP_GPIO.funcn_out_sel_cfg[rtcio_num].val = reg.val;
 
-#if SOC_RTCIO_WAKE_SUPPORTED
-/**
- * @brief Set specific logic level on an RTC IO pin as a ext0 wakeup trigger.
- *
- * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
- * @param level Logic level (0: low level trigger, 1: high level trigger)
- */
-static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level)
-{
-    // TODO: [ESP32S31] IDF-14785
-    (void)rtcio_num;
-    (void)level;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, enable_w1ts, BIT(rtcio_num));
 }
-#endif // SOC_RTCIO_WAKE_SUPPORTED
 
 #ifdef __cplusplus
 }
diff --git a/components/esp_hal_gpio/esp32s31/rtc_io_periph.c b/components/esp_hal_gpio/esp32s31/rtc_io_periph.c
index 3c47700dd4..7edb447721 100644
--- a/components/esp_hal_gpio/esp32s31/rtc_io_periph.c
+++ b/components/esp_hal_gpio/esp32s31/rtc_io_periph.c
@@ -1,27 +1,21 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-// TODO: [ESP32S31] IDF-14785
-// RTC IO peripheral implementation is temporarily bypassed
-// This file provides a stub implementation to allow the build to succeed.
-// Full RTC IO support for ESP32-S31 needs to be implemented in the future.
-// Related: Need to create soc/esp32s31/include/soc/rtc_io_channel.h and
-// implement proper RTC IO pin mapping and descriptor tables.
-
 #include "hal/rtc_io_periph.h"
+#include "soc/rtc_io_channel.h"
 
 const int8_t rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
-    -1,//GPIO0
-    -1,//GPIO1
-    -1,//GPIO2
-    -1,//GPIO3
-    -1,//GPIO4
-    -1,//GPIO5
-    -1,//GPIO6
-    -1,//GPIO7
+    RTCIO_GPIO0_CHANNEL,    //GPIO0
+    RTCIO_GPIO1_CHANNEL,    //GPIO1
+    RTCIO_GPIO2_CHANNEL,    //GPIO2
+    RTCIO_GPIO3_CHANNEL,    //GPIO3
+    RTCIO_GPIO4_CHANNEL,    //GPIO4
+    RTCIO_GPIO5_CHANNEL,    //GPIO5
+    RTCIO_GPIO6_CHANNEL,    //GPIO6
+    RTCIO_GPIO7_CHANNEL,    //GPIO7
     -1,//GPIO8
     -1,//GPIO9
     -1,//GPIO10
@@ -77,14 +71,3 @@ const int8_t rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
     -1,//GPIO60
     -1,//GPIO61
 };
-
-// TODO: [ESP32S31] IDF-14785
-#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
-// This requires soc/esp32s31/include/soc/rtc_io_channel.h and
-// soc/esp32s31/include/soc/rtc_io_reg.h to be created first
-// Currently providing empty array as placeholder - all fields will be 0
-const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT] = {
-    // TODO: Initialize 8 entries (SOC_RTCIO_PIN_COUNT = 8) with proper register addresses
-    // and bit masks once rtc_io_channel.h and rtc_io_reg.h are available
-};
-#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
diff --git a/components/soc/esp32p4/include/soc/lp_gpio_sig_map.h b/components/soc/esp32p4/include/soc/lp_gpio_sig_map.h
index d886ba246c..60a3b22c6d 100644
--- a/components/soc/esp32p4/include/soc/lp_gpio_sig_map.h
+++ b/components/soc/esp32p4/include/soc/lp_gpio_sig_map.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0 OR MIT
  */
@@ -51,6 +51,7 @@
 #define LP_PROBE_TOP_OUT15_IDX                            29
 #define PROBE_CHAIN_CLK_PAD_OUT_IDX                       30
 
-#define SIG_LP_GPIO_OUT_IDX                               32
+#define LP_SIG_GPIO_OUT_IDX                               32
+#define SIG_LP_GPIO_OUT_IDX _Pragma ("GCC warning \"'SIG_LP_GPIO_OUT_IDX' macro is deprecated, use 'LP_SIG_GPIO_OUT_IDX' instead\"") LP_SIG_GPIO_OUT_IDX
 
 #define LP_GPIO_MAP_DATE_IDX                              0x230323
diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
index d31a832dc7..5ed537c74c 100644
--- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
@@ -67,6 +67,14 @@ config SOC_RTC_TIMER_SUPPORTED
     bool
     default y
 
+config SOC_LP_GPIO_MATRIX_SUPPORTED
+    bool
+    default y
+
+config SOC_LP_PERIPHERALS_SUPPORTED
+    bool
+    default y
+
 config SOC_SPIRAM_SUPPORTED
     bool
     default y
@@ -271,6 +279,18 @@ config SOC_RTCIO_PIN_COUNT
     int
     default 8
 
+config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
+    bool
+    default y
+
+config SOC_RTCIO_HOLD_SUPPORTED
+    bool
+    default y
+
+config SOC_RTCIO_WAKE_SUPPORTED
+    bool
+    default y
+
 config SOC_SDM_SUPPORT_SLEEP_RETENTION
     bool
     default y
diff --git a/components/soc/esp32s31/include/soc/lp_gpio_pins.h b/components/soc/esp32s31/include/soc/lp_gpio_pins.h
new file mode 100644
index 0000000000..06f76d368d
--- /dev/null
+++ b/components/soc/esp32s31/include/soc/lp_gpio_pins.h
@@ -0,0 +1,20 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// `LP_GPIO_MATRIX_CONST_ONE_INPUT` means connect logic 1 to the LP peripheral signal
+#define LP_GPIO_MATRIX_CONST_ONE_INPUT   (0x8)
+// `LP_GPIO_MATRIX_CONST_ZERO_INPUT` means connect logic 0 to the LP peripheral signal
+#define LP_GPIO_MATRIX_CONST_ZERO_INPUT  (0xc)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/include/soc/lp_gpio_sig_map.h b/components/soc/esp32s31/include/soc/lp_gpio_sig_map.h
index 5b0533b2d1..181a83bac0 100644
--- a/components/soc/esp32s31/include/soc/lp_gpio_sig_map.h
+++ b/components/soc/esp32s31/include/soc/lp_gpio_sig_map.h
@@ -42,4 +42,4 @@
 #define LP_PROBE_TOP_OUT14_IDX                  28
 #define LP_PROBE_TOP_OUT15_IDX                  29
 // version date 2506050
-#define LP_SIG_GPIO_OUT_IDX                        128
+#define LP_SIG_GPIO_OUT_IDX                     32
diff --git a/components/soc/esp32s31/include/soc/rtc_io_channel.h b/components/soc/esp32s31/include/soc/rtc_io_channel.h
new file mode 100644
index 0000000000..7cfe757fcf
--- /dev/null
+++ b/components/soc/esp32s31/include/soc/rtc_io_channel.h
@@ -0,0 +1,31 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ */
+
+#pragma once
+
+#define RTCIO_GPIO0_CHANNEL         0   //RTCIO_CHANNEL_0
+#define RTCIO_CHANNEL_0_GPIO_NUM    0
+
+#define RTCIO_GPIO1_CHANNEL         1   //RTCIO_CHANNEL_1
+#define RTCIO_CHANNEL_1_GPIO_NUM    1
+
+#define RTCIO_GPIO2_CHANNEL         2   //RTCIO_CHANNEL_2
+#define RTCIO_CHANNEL_2_GPIO_NUM    2
+
+#define RTCIO_GPIO3_CHANNEL         3   //RTCIO_CHANNEL_3
+#define RTCIO_CHANNEL_3_GPIO_NUM    3
+
+#define RTCIO_GPIO4_CHANNEL         4   //RTCIO_CHANNEL_4
+#define RTCIO_CHANNEL_4_GPIO_NUM    4
+
+#define RTCIO_GPIO5_CHANNEL         5   //RTCIO_CHANNEL_5
+#define RTCIO_CHANNEL_5_GPIO_NUM    5
+
+#define RTCIO_GPIO6_CHANNEL         6   //RTCIO_CHANNEL_6
+#define RTCIO_CHANNEL_6_GPIO_NUM    6
+
+#define RTCIO_GPIO7_CHANNEL         7   //RTCIO_CHANNEL_7
+#define RTCIO_CHANNEL_7_GPIO_NUM    7
diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h
index 50bf58b087..ad3beeff2c 100644
--- a/components/soc/esp32s31/include/soc/soc_caps.h
+++ b/components/soc/esp32s31/include/soc/soc_caps.h
@@ -76,8 +76,8 @@
 #define SOC_PMU_SUPPORTED                  1
 #define SOC_RTC_TIMER_SUPPORTED            1
 // #define SOC_ULP_LP_UART_SUPPORTED       1      // TODO: [ESP32S31] IDF-14634
-// #define SOC_LP_GPIO_MATRIX_SUPPORTED    1      // TODO: [ESP32S31] IDF-14785
-// #define SOC_LP_PERIPHERALS_SUPPORTED    1      // TODO: [ESP32S31] IDF-14785
+#define SOC_LP_GPIO_MATRIX_SUPPORTED    1
+#define SOC_LP_PERIPHERALS_SUPPORTED    1
 // #define SOC_LP_I2C_SUPPORTED            1      // TODO: [ESP32S31] IDF-14635
 // #define SOC_LP_SPI_SUPPORTED            1      // TODO: [ESP32S31] IDF-14639
 #define SOC_SPIRAM_SUPPORTED            1      // TODO: [ESP32S31] IDF-14718
@@ -195,6 +195,11 @@
 
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 #define SOC_RTCIO_PIN_COUNT                 8
+#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED    1  /* This macro indicates that the target has separate RTC IOMUX hardware feature,
+                                                * so the RTC GPIOs can be used as general purpose RTC GPIOs.
+                                                */
+#define SOC_RTCIO_HOLD_SUPPORTED            1
+#define SOC_RTCIO_WAKE_SUPPORTED            1
 
 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/
 #define SOC_SDM_SUPPORT_SLEEP_RETENTION     1
diff --git a/components/soc/esp32s31/include/soc/uart_pins.h b/components/soc/esp32s31/include/soc/uart_pins.h
index 14db90dbb4..13634edba8 100644
--- a/components/soc/esp32s31/include/soc/uart_pins.h
+++ b/components/soc/esp32s31/include/soc/uart_pins.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0 OR MIT
  */
@@ -38,8 +38,10 @@
 
 #define LP_U0RXD_GPIO_NUM 7
 #define LP_U0TXD_GPIO_NUM 6
-#define LP_U0RTS_GPIO_NUM (-1)
-#define LP_U0CTS_GPIO_NUM (-1)
+#define LP_U0RTS_GPIO_NUM 4
+#define LP_U0CTS_GPIO_NUM 5
+#define LP_U0DTR_GPIO_NUM 2
+#define LP_U0DSR_GPIO_NUM 3
 
 /* The following defines are necessary for reconfiguring the UART
  * to use IOMUX, at runtime. */
@@ -70,5 +72,7 @@
 
 #define LP_U0TXD_MUX_FUNC  (0)
 #define LP_U0RXD_MUX_FUNC  (0)
-#define LP_U0RTS_MUX_FUNC  (-1)
-#define LP_U0CTS_MUX_FUNC  (-1)
+#define LP_U0RTS_MUX_FUNC  (0)
+#define LP_U0CTS_MUX_FUNC  (0)
+#define LP_U0DTR_MUX_FUNC  (0)
+#define LP_U0DSR_MUX_FUNC  (0)
diff --git a/components/soc/esp32s31/register/soc/lp_gpio_struct.h b/components/soc/esp32s31/register/soc/lp_gpio_struct.h
index 8ea05d6b3d..551fc37902 100644
--- a/components/soc/esp32s31/register/soc/lp_gpio_struct.h
+++ b/components/soc/esp32s31/register/soc/lp_gpio_struct.h
@@ -424,6 +424,8 @@ typedef struct {
     volatile lp_gpio_date_reg_t date;
 } lp_gpio_dev_t;
 
+extern lp_gpio_dev_t LP_GPIO;
+
 
 #ifndef __cplusplus
 _Static_assert(sizeof(lp_gpio_dev_t) == 0x400, "Invalid size of lp_gpio_dev_t structure");
diff --git a/components/soc/esp32s31/register/soc/lp_iomux_struct.h b/components/soc/esp32s31/register/soc/lp_iomux_struct.h
index 15dbc7bbe7..d8ab6f11dd 100644
--- a/components/soc/esp32s31/register/soc/lp_iomux_struct.h
+++ b/components/soc/esp32s31/register/soc/lp_iomux_struct.h
@@ -134,6 +134,8 @@ typedef struct {
     volatile lp_io_mux_date_reg_t date;
 } lp_io_mux_dev_t;
 
+extern lp_io_mux_dev_t LP_IO_MUX;
+
 
 #ifndef __cplusplus
 _Static_assert(sizeof(lp_io_mux_dev_t) == 0x200, "Invalid size of lp_io_mux_dev_t structure");