From d2be19ba18dda3693b65c3c0dfaab8ca731eeac4 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 25 Feb 2026 21:54:50 +0800 Subject: [PATCH] feat(esp_hw_support): support esp32s31 system sleep retention --- .../lowpower/port/esp32s31/sleep_clock.c | 127 ++++++++++++++ .../port/esp32s31/peripheral_domain_pd.c | 98 +++++++++++ components/esp_system/system_init_fn.txt | 1 + .../include/soc/system_periph_retention.h | 30 ++-- .../soc/esp32s31/ld/esp32s31.peripherals.ld | 2 +- .../soc/esp32s31/register/soc/reg_base.h | 2 +- .../soc/esp32s31/system_retention_periph.c | 164 ++++++++++++++++++ 7 files changed, 407 insertions(+), 17 deletions(-) create mode 100644 components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c create mode 100644 components/esp_hw_support/port/esp32s31/peripheral_domain_pd.c create mode 100644 components/soc/esp32s31/system_retention_periph.c diff --git a/components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c new file mode 100644 index 0000000000..e5f8db2972 --- /dev/null +++ b/components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c @@ -0,0 +1,127 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_private/sleep_clock.h" +#include "soc/hp_sys_clkrst_reg.h" +#include "soc/pmu_reg.h" +#include "soc/lp_peri_clkrst_reg.h" +#include "pmu_bit_defs.h" +#include "modem/modem_syscon_reg.h" +#include "modem/modem_lpcon_reg.h" + +ESP_LOG_ATTR_TAG(TAG, "sleep_clock"); + +esp_err_t sleep_clock_system_retention_init(void *arg) +{ + #define N_REGS_PCR() (((HP_SYS_CLKRST_CLK_EN0_REG - DR_REG_HP_SYS_CLKRST_BASE) / 4) + 1) + + const static sleep_retention_entries_config_t pcr_regs_retention[] = { + /* Enable i2c master clock */ + [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), LP_PERICLKRST_I2CMST_CTRL_REG, LP_PERICLKRST_LP_I2CMST_CLK_EN, LP_PERICLKRST_LP_I2CMST_CLK_EN_M, 1, 0), .owner = ENTRY(0) }, + /* Start SYSPLL self-calibration */ + [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, 0, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) }, + /* Wait calibration done */ + [2] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(2), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_END, HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_M, 1, 0), .owner = ENTRY(0) }, + /* Stop SYSPLL self-calibration */ + [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) }, + /* Clock configuration retention */ + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(4), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) }, /* pcr */ + [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) }, + [6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) }, + [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) }, + [8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) }, + }; + + esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM); + ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention"); + ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization"); + return ESP_OK; + + #undef N_REGS_PCR +} + +#if CONFIG_MAC_BB_PD || CONFIG_BTDM_CTRL_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE +#include "rom/ets_sys.h" +esp_err_t sleep_clock_modem_retention_init(void *arg) +{ + #define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_RF2_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1) + #define N_REGS_LPCON() (((MODEM_LPCON_MODEM_INTR_STATUS_REG - MODEM_LPCON_TEST_CONF_REG) / 4) + 1) + const static sleep_retention_entries_config_t modem_regs_retention[] = { + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MODEMSYSCON_LINK(0), 0x20109c30, 0xf, 0xffffffff, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(1), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, 12, 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */ + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMLPCON_LINK(0), MODEM_LPCON_TEST_CONF_REG, MODEM_LPCON_TEST_CONF_REG, N_REGS_LPCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */ + }; + + esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM); + ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 1 level priority"); + ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization"); + return ESP_OK; + + #undef N_REGS_SYSCON +} +#endif + +bool clock_domain_pd_allowed(void) +{ + const sleep_retention_module_bitmap_t inited_modules = sleep_retention_get_inited_modules(); + const sleep_retention_module_bitmap_t created_modules = sleep_retention_get_created_modules(); + const sleep_retention_module_bitmap_t sys_clk_dep_modules = (sleep_retention_module_bitmap_t){ .bitmap[SLEEP_RETENTION_MODULE_SYS_PERIPH >> 5] = BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH % 32) }; +/* The clock and reset of MODEM (WiFi, BLE and 15.4) modules are managed + * through MODEM_SYSCON, when one or more MODEMs are initialized, it is + * necessary to check the state of CLOCK_MODEM to determine MODEM domain on + * or off. The clock and reset of digital peripherals are managed through + * PCR, with TOP domain similar to MODEM domain. */ + __attribute__((unused)) sleep_retention_module_bitmap_t modem_clk_dep_modules = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } }; +#if SOC_WIFI_SUPPORTED + modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_WIFI_MAC >> 5] |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC % 32); + modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_WIFI_BB >> 5] |= BIT(SLEEP_RETENTION_MODULE_WIFI_BB % 32); +#endif +#if SOC_BT_SUPPORTED + modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_BLE_MAC >> 5] |= BIT(SLEEP_RETENTION_MODULE_BLE_MAC % 32); + modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_BT_BB >> 5] |= BIT(SLEEP_RETENTION_MODULE_BT_BB % 32); +#endif +#if SOC_IEEE802154_SUPPORTED + modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_802154_MAC >> 5] |= BIT(SLEEP_RETENTION_MODULE_802154_MAC % 32); + modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_BT_BB >> 5] |= BIT(SLEEP_RETENTION_MODULE_BT_BB % 32); +#endif + + const sleep_retention_module_bitmap_t null_module = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } }; + + sleep_retention_module_bitmap_t mask = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } }; + const sleep_retention_module_bitmap_t system_modules = sleep_retention_module_bitmap_and(inited_modules, sys_clk_dep_modules); + if (!sleep_retention_module_bitmap_eq(system_modules, null_module)) { + mask.bitmap[SLEEP_RETENTION_MODULE_CLOCK_SYSTEM >> 5] |= BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM % 32); + } + + #if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED + const sleep_retention_module_bitmap_t modem_modules = sleep_retention_module_bitmap_and(inited_modules, modem_clk_dep_modules); + if (!sleep_retention_module_bitmap_eq(modem_modules, null_module)) { + mask.bitmap[SLEEP_RETENTION_MODULE_CLOCK_MODEM >> 5] |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM % 32); + } +#endif + + const sleep_retention_module_bitmap_t clock_domain_inited_modules = sleep_retention_module_bitmap_and(inited_modules, mask); + const sleep_retention_module_bitmap_t clock_domain_created_modules = sleep_retention_module_bitmap_and(created_modules, mask); + return sleep_retention_module_bitmap_eq(clock_domain_inited_modules, clock_domain_created_modules); +} + +ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106) +{ + sleep_retention_module_init_param_t init_param = { + .cbs = { .create = { .handle = sleep_clock_system_retention_init, .arg = NULL } }, + .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE + }; + sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param); + +#if CONFIG_MAC_BB_PD || CONFIG_BTDM_CTRL_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE + init_param = (sleep_retention_module_init_param_t) { + .cbs = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } }, + .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE + }; + sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param); +#endif + return ESP_OK; +} diff --git a/components/esp_hw_support/port/esp32s31/peripheral_domain_pd.c b/components/esp_hw_support/port/esp32s31/peripheral_domain_pd.c new file mode 100644 index 0000000000..5b7ce3919a --- /dev/null +++ b/components/esp_hw_support/port/esp32s31/peripheral_domain_pd.c @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "sdkconfig.h" +#include "soc/system_periph_retention.h" +#include "esp_private/sleep_retention.h" + +bool peripheral_domain_pd_allowed(void) +{ +#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP + const sleep_retention_module_bitmap_t inited_modules = sleep_retention_get_inited_modules(); + const sleep_retention_module_bitmap_t created_modules = sleep_retention_get_created_modules(); + + sleep_retention_module_bitmap_t mask = RETENTION_MODULE_BITMAP_INIT(NULL); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_SYS_PERIPH); + // ESP32S31 supports WDT sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TG0_WDT); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TG1_WDT); + + // ESP32S31 supports Timer sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TG0_TIMER0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TG0_TIMER1); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TG1_TIMER0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TG1_TIMER1); + + // ESP32S31 supports AHB_DMA sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AHB_DMA_CH0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AHB_DMA_CH1); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AHB_DMA_CH2); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AHB_DMA_CH3); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AHB_DMA_CH4); + + // ESP32S31 supports AXI_DMA sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AXI_DMA_CH0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AXI_DMA_CH1); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AXI_DMA_CH2); + + // ESP32S31 supports UART sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_UART0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_UART1); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_UART2); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_UART3); + + // ESP32S31 supports RMT sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_RMT0); + + // ESP32S31 supports PAU and I2S sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_I2S0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_I2S1); + + // ESP32S31 supports I2C sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_I2C0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_I2C1); + + // ESP32S31 supports ETM sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_ETM0); + + // ESP32S31 supports TWAI sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TWAI0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TWAI1); + + // ESP32S31 supports PARLIO sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_PARLIO0); + + // ESP32S31 supports GPSPI2 sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_GPSPI2); + // ESP32S31 supports GPSPI3 sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_GPSPI3); + + // ESP32S31 supports LEDC sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_LEDC0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_LEDC1); + + // ESP32S31 supports MCPWM sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_MCPWM0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_MCPWM1); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_MCPWM2); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_MCPWM3); + + // ESP32S31 supports PCNT sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_PCNT0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_PCNT1); + + // ESP32S31 supports SDM sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_SDM0); + + const sleep_retention_module_bitmap_t peripheral_domain_inited_modules = sleep_retention_module_bitmap_and(inited_modules, mask); + const sleep_retention_module_bitmap_t peripheral_domain_created_modules = sleep_retention_module_bitmap_and(created_modules, mask); + return sleep_retention_module_bitmap_eq(peripheral_domain_inited_modules, peripheral_domain_created_modules); +#else + return false; +#endif +} diff --git a/components/esp_system/system_init_fn.txt b/components/esp_system/system_init_fn.txt index d1388091b3..26e07b8e55 100644 --- a/components/esp_system/system_init_fn.txt +++ b/components/esp_system/system_init_fn.txt @@ -93,6 +93,7 @@ SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/p SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c on BIT(0) SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c on BIT(0) SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32p4/sleep_clock.c on BIT(0) +SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c on BIT(0) SECONDARY: 107: sleep_sys_periph_startup_init in components/esp_hw_support/sleep_system_peripheral.c on BIT(0) # app_trace doesn't have init dependencies diff --git a/components/soc/esp32s31/include/soc/system_periph_retention.h b/components/soc/esp32s31/include/soc/system_periph_retention.h index 6680539a7c..7fa9390cd7 100644 --- a/components/soc/esp32s31/include/soc/system_periph_retention.h +++ b/components/soc/esp32s31/include/soc/system_periph_retention.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -23,17 +23,17 @@ extern "C" * useful for external use. */ #define INT_MTX_RETENTION_LINK_LEN 2 -// extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN]; +extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN]; /** - * @brief Provide access to cache configuration registers retention + * @brief Provide access to tee apm configuration registers retention * context definition. * * This is an internal function of the sleep retention driver, and is not * useful for external use. */ -#define CACHE_RETENTION_LINK_LEN 8 -// extern const regdma_entries_config_t cache_regs_retention[CACHE_RETENTION_LINK_LEN]; +#define TEE_APM_RETENTION_LINK_LEN 14 +extern const regdma_entries_config_t tee_apm_regs_retention[TEE_APM_RETENTION_LINK_LEN]; /** * @brief Provide access to hp_system configuration registers retention @@ -43,7 +43,7 @@ extern "C" * useful for external use. */ #define HP_SYSTEM_RETENTION_LINK_LEN 1 -// extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTION_LINK_LEN]; +extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTION_LINK_LEN]; /** * @brief Provide access to IOMUX configuration registers retention @@ -52,8 +52,8 @@ extern "C" * This is an internal function of the sleep retention driver, and is not * useful for external use. */ -#define IOMUX_RETENTION_LINK_LEN 6 -// extern const regdma_entries_config_t iomux_regs_retention[IOMUX_RETENTION_LINK_LEN]; +#define IOMUX_RETENTION_LINK_LEN 5 +extern const regdma_entries_config_t iomux_regs_retention[IOMUX_RETENTION_LINK_LEN]; /** * @brief Provide access to FLASH spimem configuration registers retention @@ -62,8 +62,8 @@ extern "C" * This is an internal function of the sleep retention driver, and is not * useful for external use. */ -#define SPIMEM_FLASH_RETENTION_LINK_LEN 8 -// extern const regdma_entries_config_t flash_spimem_regs_retention[SPIMEM_FLASH_RETENTION_LINK_LEN]; +#define SPIMEM_FLASH_RETENTION_LINK_LEN 7 +extern const regdma_entries_config_t flash_spimem_regs_retention[SPIMEM_FLASH_RETENTION_LINK_LEN]; /** * @brief Provide access to PSRAM spimem configuration registers retention @@ -72,8 +72,8 @@ extern "C" * This is an internal function of the sleep retention driver, and is not * useful for external use. */ -#define SPIMEM_PSRAM_RETENTION_LINK_LEN 14 -// extern const regdma_entries_config_t psram_spimem_regs_retention[SPIMEM_PSRAM_RETENTION_LINK_LEN]; +#define SPIMEM_PSRAM_RETENTION_LINK_LEN 5 +extern const regdma_entries_config_t psram_spimem_regs_retention[SPIMEM_PSRAM_RETENTION_LINK_LEN]; /** * @brief Provide access to systimer configuration registers retention @@ -82,8 +82,8 @@ extern "C" * This is an internal function of the sleep retention driver, and is not * useful for external use. */ -#define SYSTIMER_RETENTION_LINK_LEN 19 -// extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_LINK_LEN]; +#define SYSTIMER_RETENTION_LINK_LEN 10 +extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_LINK_LEN]; /** * @brief Provide access to pau configuration registers retention @@ -93,7 +93,7 @@ extern "C" * useful for external use. */ #define PAU_RETENTION_LINK_LEN 1 -// extern const regdma_entries_config_t pau_regs_retention[PAU_RETENTION_LINK_LEN]; +extern const regdma_entries_config_t pau_regs_retention[PAU_RETENTION_LINK_LEN]; #ifdef __cplusplus } diff --git a/components/soc/esp32s31/ld/esp32s31.peripherals.ld b/components/soc/esp32s31/ld/esp32s31.peripherals.ld index 61df5446b5..e47f458664 100644 --- a/components/soc/esp32s31/ld/esp32s31.peripherals.ld +++ b/components/soc/esp32s31/ld/esp32s31.peripherals.ld @@ -77,7 +77,7 @@ PROVIDE ( MSPI_IOMUX = 0x20584000 ); PROVIDE ( HP_SYSTEM = 0x20586000 ); PROVIDE ( HP_SYS_CLKRST = 0x20587000 ); PROVIDE ( CNNT_PAD_CTRL = 0x20588000 ); -PROVIDE ( HP_ALIVE_SYS_REG = 0x20589000 ); +PROVIDE ( HP_ALIVE_SYS = 0x20589000 ); PROVIDE ( HP_PERI1_PMS = 0x2058A000 ); PROVIDE ( LP_SYS = 0x20700000 ); PROVIDE ( LP_CLKRST = 0x20701000 ); diff --git a/components/soc/esp32s31/register/soc/reg_base.h b/components/soc/esp32s31/register/soc/reg_base.h index 97f8473038..609b347884 100644 --- a/components/soc/esp32s31/register/soc/reg_base.h +++ b/components/soc/esp32s31/register/soc/reg_base.h @@ -73,7 +73,7 @@ #define DR_REG_IO_MUX_BASE 0x20582000 #define DR_REG_GPIO_BASE 0x20583000 #define DR_REG_GPIO_EXT_BASE 0x20583E00 -#define DR_REG_MSPI_IOMUX_BASE 0x20584000 +#define DR_REG_IOMUX_MSPI_PIN_BASE 0x20584000 #define DR_REG_INTR0_BASE 0x20585000 #define DR_REG_HP_SYS_BASE 0x20586000 #define DR_REG_HP_SYS_CLKRST_BASE 0x20587000 diff --git a/components/soc/esp32s31/system_retention_periph.c b/components/soc/esp32s31/system_retention_periph.c new file mode 100644 index 0000000000..56b461576a --- /dev/null +++ b/components/soc/esp32s31/system_retention_periph.c @@ -0,0 +1,164 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#include "soc/cache_reg.h" +#include "soc/gpio_reg.h" +#include "soc/hp_system_reg.h" +#include "soc/hp_sys_clkrst_reg.h" +#include "soc/io_mux_reg.h" +#include "soc/iomux_mspi_pin_reg.h" +#include "soc/interrupt_core0_reg.h" +#include "soc/interrupt_core1_reg.h" +#include "soc/pau_reg.h" +#include "soc/regdma.h" +#include "soc/system_periph_retention.h" +#include "soc/spi_mem_reg.h" +#include "soc/spi_mem_s_reg.h" +#include "soc/spi1_mem_s_reg.h" +#include "soc/systimer_reg.h" +#include "soc/timer_group_reg.h" +// #include "soc/timer_periph.h" +#include "soc/uart_reg.h" +#include "esp32s31/rom/cache.h" +#include "soc/hp_apm_reg.h" +#include "soc/cpu_apm_reg.h" +#include "soc/hp_mem_apm_reg.h" +#include "soc/tee_reg.h" +#include "soc/hp_peri0_pms_reg.h" +#include "soc/hp_peri1_pms_reg.h" + +/* Interrupt Matrix Registers Context */ +#define N_REGS_INTR_CORE0() (((INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG - DR_REG_INTERRUPT_CORE0_BASE) / 4) + 1) +#define N_REGS_INTR_CORE1() (((INTERRUPT_CORE1_SIG_IDX_ASSERT_IN_SEC_REG - DR_REG_INTERRUPT_CORE1_BASE) / 4) + 1) +const regdma_entries_config_t intr_matrix_regs_retention[] = { + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0x00), DR_REG_INTERRUPT_CORE0_BASE, DR_REG_INTERRUPT_CORE0_BASE, N_REGS_INTR_CORE0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* intr matrix */ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0x01), DR_REG_INTERRUPT_CORE1_BASE, DR_REG_INTERRUPT_CORE1_BASE, N_REGS_INTR_CORE1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr matrix */ +}; +_Static_assert(ARRAY_SIZE(intr_matrix_regs_retention) == INT_MTX_RETENTION_LINK_LEN, "Inconsistent INT_MTX retention link length definitions"); + +#if SOC_APM_SUPPORTED +/* TEE APM Registers Context */ +#define N_REGS_TEE_0() (((TEE_M87_MODE_CTRL_REG - TEE_M0_MODE_CTRL_REG) / 4) + 1) +#define N_REGS_TEE_1() (((TEE_SUPERVISOR_PRIV_SEL_REG - TEE_SUPERVISOR_PRIV_SEL_REG) / 4) + 1) +#define N_REGS_APM_0() (((HP_APM_FUNC_CTRL_REG - HP_APM_REGION_FILTER_EN_REG) / 4) + 1) +#define N_REGS_APM_1() (((HP_APM_BUS_ERR_CONF_REG - HP_APM_INT_EN_REG) / 4) + 1) +#define N_REGS_APM_2() (((CPU_APM_FUNC_CTRL_REG - CPU_APM_REGION_FILTER_EN_REG) / 4) + 1) +#define N_REGS_APM_3() (((CPU_APM_BUS_ERR_CONF_REG - CPU_APM_INT_EN_REG) / 4) + 1) +#define N_REGS_APM_4() (((HP_MEM_APM_FUNC_CTRL_REG - HP_MEM_APM_REGION_FILTER_EN_REG) / 4) + 1) +#define N_REGS_APM_5() (((HP_MEM_APM_BUS_ERR_CONF_REG - HP_MEM_APM_INT_EN_REG) / 4) + 1) + +#define N_REGS_PMS0_0() (((HP_PERI0_PMS_AXI_PERF_MON_CTRL_REG - HP_PERI0_PMS_TRACE0_CTRL_REG) / 4) + 1) +#define N_REGS_PMS0_1() (((HP_PERI0_PMS_INT_EN_REG - HP_PERI0_PMS_INT_EN_REG) / 4) + 1) +#define N_REGS_PMS0_2() (((HP_PERI0_PMS_CLOCK_GATE_REG - HP_PERI0_PMS_BUS_ERR_CONF_REG) / 4) + 1) +#define N_REGS_PMS1_0() (((HP_PERI1_PMS_HP_PERI1_PMS_CTRL_REG - HP_PERI1_PMS_HP_USBOTG_PHY_CTRL_REG) / 4) + 1) +#define N_REGS_PMS1_1() (((HP_PERI1_PMS_INT_EN_REG - HP_PERI1_PMS_INT_EN_REG) / 4) + 1) +#define N_REGS_PMS1_2() (((HP_PERI1_PMS_CLOCK_GATE_REG - HP_PERI1_PMS_BUS_ERR_CONF_REG) / 4) + 1) + +const regdma_entries_config_t tee_apm_regs_retention[] = { + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x00), TEE_M0_MODE_CTRL_REG, TEE_M0_MODE_CTRL_REG, N_REGS_TEE_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* tee */ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x01), TEE_SUPERVISOR_PRIV_SEL_REG, TEE_SUPERVISOR_PRIV_SEL_REG, N_REGS_TEE_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x02), HP_APM_REGION_FILTER_EN_REG, HP_APM_REGION_FILTER_EN_REG, N_REGS_APM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x03), HP_APM_INT_EN_REG, HP_APM_INT_EN_REG, N_REGS_APM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x04), CPU_APM_REGION_FILTER_EN_REG, CPU_APM_REGION_FILTER_EN_REG, N_REGS_APM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x05), CPU_APM_INT_EN_REG, CPU_APM_INT_EN_REG, N_REGS_APM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x06), HP_MEM_APM_REGION_FILTER_EN_REG, HP_MEM_APM_REGION_FILTER_EN_REG, N_REGS_APM_4(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x07), HP_MEM_APM_INT_EN_REG, HP_MEM_APM_INT_EN_REG, N_REGS_APM_5(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x08), HP_PERI0_PMS_TRACE0_CTRL_REG, HP_PERI0_PMS_TRACE0_CTRL_REG, N_REGS_PMS0_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [9] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x09), HP_PERI0_PMS_INT_EN_REG, HP_PERI0_PMS_INT_EN_REG, N_REGS_PMS0_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [10] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x0a), HP_PERI0_PMS_BUS_ERR_CONF_REG, HP_PERI0_PMS_BUS_ERR_CONF_REG, N_REGS_PMS0_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [11] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x0b), HP_PERI1_PMS_HP_USBOTG_PHY_CTRL_REG, HP_PERI1_PMS_HP_USBOTG_PHY_CTRL_REG, N_REGS_PMS1_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [12] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x0c), HP_PERI1_PMS_INT_EN_REG, HP_PERI1_PMS_INT_EN_REG, N_REGS_PMS1_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [13] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x0d), HP_PERI1_PMS_BUS_ERR_CONF_REG, HP_PERI1_PMS_BUS_ERR_CONF_REG, N_REGS_PMS1_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, +}; +_Static_assert(ARRAY_SIZE(tee_apm_regs_retention) == TEE_APM_RETENTION_LINK_LEN, "Inconsistent HP_SYSTEM retention link length definitions"); +#endif + +/* HP System Registers Context */ +#define N_REGS_HP_SYSTEM() (((HP_SYSTEM_GMAC1_PAD_BIST_INT_ENA_REG - DR_REG_HP_SYS_BASE) / 4) + 1) +const regdma_entries_config_t hp_system_regs_retention[] = { + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_HPSYS_LINK(0), DR_REG_HP_SYS_BASE, DR_REG_HP_SYS_BASE, N_REGS_HP_SYSTEM(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* hp system */ +}; +_Static_assert(ARRAY_SIZE(hp_system_regs_retention) == HP_SYSTEM_RETENTION_LINK_LEN, "Inconsistent HP_SYSTEM retention link length definitions"); + +/* IO MUX Registers Context */ +#define N_REGS_IOMUX() (((IO_MUX_GPIO62_REG - REG_IO_MUX_BASE) / 4) + 1) +#define N_REGS_MSPI_IOMUX() (((IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG - IOMUX_MSPI_PIN_CLK_EN0_REG) / 4) + 1) +#define N_REGS_GPIO_PINx() (((GPIO_PIN62_REG - GPIO_PIN0_REG) / 4) + 1) +#define N_REGS_GPIO_FUNC_IN() (((GPIO_FUNC255_IN_SEL_CFG_REG - GPIO_FUNC0_IN_SEL_CFG_REG) / 4) + 1) +#define N_REGS_GPIO_FUNC_OUT() (((GPIO_FUNC62_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1) + +const regdma_entries_config_t iomux_regs_retention[] = { + /* IO_MUX */ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), REG_IO_MUX_BASE, REG_IO_MUX_BASE, N_REGS_IOMUX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + /* MSPI IOMUX */ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG, IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG, N_REGS_MSPI_IOMUX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + /* GPIO_PIN0_REG ~ GPIO_PIN62_REG*/ + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_PIN0_REG, GPIO_PIN0_REG, N_REGS_GPIO_PINx(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + /* GPIO_FUNC0_IN_SEL_CFG_REG ~ GPIO_FUNC255_IN_SEL_CFG_REG & GPIO_FUNC0_OUT_SEL_CFG_REG ~ GPIO_FUNC0_IN_SEL_CFG_REG */ + [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x03), GPIO_FUNC0_IN_SEL_CFG_REG, GPIO_FUNC0_IN_SEL_CFG_REG, N_REGS_GPIO_FUNC_IN(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x04), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_GPIO_FUNC_OUT(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, +}; +_Static_assert(ARRAY_SIZE(iomux_regs_retention) == IOMUX_RETENTION_LINK_LEN, "Inconsistent IOMUX retention link length definitions"); + +/* Memory SPI Registers Context */ +#define N_REGS_SPI1_C_MEM_0() (((SPI1_MEM_C_INT_ENA_REG - DR_REG_FLASH_SPI1_BASE) / 4) + 1) +#define N_REGS_SPI1_C_MEM_1() (((SPI1_MEM_C_TIMING_CALI_REG - SPI1_MEM_C_TIMING_CALI_REG) / 4) + 1) +#define N_REGS_SPI0_C_MEM_0() (((SPI_MEM_C_DDR_REG - DR_REG_FLASH_SPI0_BASE) / 4) + 1) +#define N_REGS_SPI0_C_MEM_1() (((SPI_MEM_C_DOUT_MODE_REG - SPI_FMEM_C_PMS0_ATTR_REG) / 4) + 1) +#define N_REGS_SPI0_C_MEM_2() (((SPI_MEM_C_NAND_FLASH_SPI_SEQ31_REG - SPI_MEM_C_CLOCK_GATE_REG) / 4) + 1) +#define N_REGS_SPI0_C_MEM_3() (((SPI_MEM_C_REGISTERRND_ECO_LOW_REG - SPI_MEM_C_MMU_POWER_CTRL_REG) / 4) + 1) + +const regdma_entries_config_t flash_spimem_regs_retention[] = { + /* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), DR_REG_FLASH_SPI1_BASE, DR_REG_FLASH_SPI1_BASE, N_REGS_SPI1_C_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi1_mem */ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI1_MEM_C_INT_ENA_REG, SPI1_MEM_C_INT_ENA_REG, N_REGS_SPI1_C_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + + /* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */ + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), DR_REG_FLASH_SPI0_BASE, DR_REG_FLASH_SPI0_BASE, N_REGS_SPI0_C_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi0_mem */ + [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x03), SPI_FMEM_C_PMS0_ATTR_REG, SPI_FMEM_C_PMS0_ATTR_REG, N_REGS_SPI0_C_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), SPI_MEM_C_CLOCK_GATE_REG, SPI_MEM_C_CLOCK_GATE_REG, N_REGS_SPI0_C_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_C_MMU_POWER_CTRL_REG, SPI_MEM_C_MMU_POWER_CTRL_REG, N_REGS_SPI0_C_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CALI_UPDATE, SPI_MEM_C_TIMING_CALI_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, +}; +_Static_assert(ARRAY_SIZE(flash_spimem_regs_retention) == SPIMEM_FLASH_RETENTION_LINK_LEN, "Inconsistent Flash SPI Mem retention link length definitions"); + +#if CONFIG_SPIRAM +#define N_REGS_SPI0_S_MEM_0() (((SPI_MEM_S_INT_ENA_REG - SPI_MEM_S_CTRL_REG) / 4) + 1) +#define N_REGS_SPI0_S_MEM_1() (((SPI_MEM_S_CLOCK_GATE_REG - SPI_MEM_S_DDR_REG) / 4) + 1) +#define N_REGS_SPI1_S_MEM_0() (((SPI1_MEM_S_INT_ENA_REG - SPI1_MEM_S_CMD_REG) / 4) + 1) +#define N_REGS_SPI1_S_MEM_1() (((SPI1_MEM_S_DDR_REG - SPI1_MEM_S_DDR_REG) / 4) + 1) +#define N_REGS_SPI1_S_MEM_2() (((SPI1_MEM_S_TIMING_CALI_REG - SPI1_MEM_S_TIMING_CALI_REG) / 4) + 1) + +const regdma_entries_config_t psram_spimem_regs_retention[SPIMEM_PSRAM_RETENTION_LINK_LEN] = { + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), SPI_MEM_S_CTRL_REG, SPI_MEM_S_CTRL_REG, N_REGS_SPI0_S_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi0_mem */ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI_MEM_S_DDR_REG, SPI_MEM_S_DDR_REG, N_REGS_SPI0_S_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), SPI1_MEM_S_CMD_REG, SPI1_MEM_S_CMD_REG, N_REGS_SPI1_S_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x03), SPI1_MEM_S_DDR_REG, SPI1_MEM_S_DDR_REG, N_REGS_SPI1_S_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), SPI1_MEM_S_TIMING_CALI_REG, SPI1_MEM_S_TIMING_CALI_REG, N_REGS_SPI1_S_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, +}; + +_Static_assert(ARRAY_SIZE(psram_spimem_regs_retention) == SPIMEM_PSRAM_RETENTION_LINK_LEN, "Inconsistent PSRAM SPI Mem retention link length definitions"); +#endif + +/* Systimer Registers Context */ +#define N_REGS_SYSTIMER_0() (((SYSTIMER_TARGET2_CONF_REG - SYSTIMER_TARGET0_HI_REG) / 4) + 1) +const regdma_entries_config_t systimer_regs_retention[] = { + // cnt value + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_UPDATE_M, SYSTIMER_TIMER_UNIT1_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, + [1] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_SYSTIMER_LINK(0x01), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_VALUE_VALID, SYSTIMER_TIMER_UNIT1_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x02), SYSTIMER_UNIT1_VALUE_HI_REG, SYSTIMER_UNIT1_LOAD_HI_REG, 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT1_LOAD_REG, SYSTIMER_TIMER_UNIT1_LOAD_M, SYSTIMER_TIMER_UNIT1_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + + // target value + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_TARGET0_HI_REG, SYSTIMER_TARGET0_HI_REG, N_REGS_SYSTIMER_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer target value & period */ + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x05), SYSTIMER_COMP0_LOAD_REG, SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_TIMER_COMP0_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x06), SYSTIMER_COMP1_LOAD_REG, SYSTIMER_TIMER_COMP1_LOAD, SYSTIMER_TIMER_COMP1_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x07), SYSTIMER_COMP2_LOAD_REG, SYSTIMER_TIMER_COMP2_LOAD, SYSTIMER_TIMER_COMP2_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + + // conf & int value + [8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x08), SYSTIMER_CONF_REG, SYSTIMER_CONF_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer work enable */ + [9] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x09), SYSTIMER_INT_ENA_REG, SYSTIMER_INT_ENA_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer intr enable */ +}; +_Static_assert(ARRAY_SIZE(systimer_regs_retention) == SYSTIMER_RETENTION_LINK_LEN, "Inconsistent Systimer retention link length definitions");