From 94f9f086f96335e2cd8cabbd7c5d96ddc755c675 Mon Sep 17 00:00:00 2001 From: Chen Chen Date: Thu, 6 Nov 2025 17:18:31 +0800 Subject: [PATCH 1/2] fix(intr_alloc): Fix ISR allocate methods in several drivers --- components/esp_driver_ledc/src/ledc.c | 10 +++++++++- components/esp_driver_sdio/src/sdio_slave.c | 19 ++++++++++++------- .../include/driver/sdmmc_host.h | 2 +- .../esp_driver_spi/src/gpspi/spi_common.c | 2 +- .../esp_driver_spi/src/gpspi/spi_slave.c | 2 +- components/esp_driver_uart/src/uart.c | 12 +++++++++--- components/hal/esp32/include/hal/ledc_ll.h | 15 ++++++++++++++- .../hal/esp32/include/hal/sdio_slave_ll.h | 13 +++++++++++++ components/hal/esp32/include/hal/uart_ll.h | 5 +++++ components/hal/esp32c2/include/hal/ledc_ll.h | 15 ++++++++++++++- components/hal/esp32c2/include/hal/uart_ll.h | 5 +++++ components/hal/esp32c3/include/hal/ledc_ll.h | 15 ++++++++++++++- components/hal/esp32c3/include/hal/uart_ll.h | 5 +++++ components/hal/esp32c5/include/hal/uart_ll.h | 5 +++++ components/hal/esp32c6/include/hal/ledc_ll.h | 15 ++++++++++++++- .../hal/esp32c6/include/hal/sdio_slave_ll.h | 13 +++++++++++++ components/hal/esp32c6/include/hal/spi_ll.h | 2 +- components/hal/esp32c6/include/hal/uart_ll.h | 5 +++++ components/hal/esp32c61/include/hal/uart_ll.h | 5 +++++ components/hal/esp32h2/include/hal/ledc_ll.h | 15 ++++++++++++++- components/hal/esp32h2/include/hal/spi_ll.h | 2 +- components/hal/esp32h2/include/hal/uart_ll.h | 5 +++++ components/hal/esp32p4/include/hal/ledc_ll.h | 15 ++++++++++++++- components/hal/esp32p4/include/hal/uart_ll.h | 5 +++++ components/hal/esp32s2/include/hal/cache_ll.h | 3 ++- components/hal/esp32s2/include/hal/ledc_ll.h | 15 ++++++++++++++- components/hal/esp32s2/include/hal/uart_ll.h | 5 +++++ components/hal/esp32s3/include/hal/ledc_ll.h | 15 ++++++++++++++- components/hal/esp32s3/include/hal/uart_ll.h | 5 +++++ components/hal/include/hal/ledc_hal.h | 8 ++++++++ components/hal/include/hal/sdio_slave_hal.h | 8 ++++++++ components/hal/include/hal/spi_hal.h | 2 +- components/hal/include/hal/spi_slave_hal.h | 2 +- components/hal/include/hal/uart_hal.h | 10 ++++++++++ components/hal/ledc_hal_iram.c | 7 ++++++- components/hal/sdio_slave_hal.c | 5 +++++ components/hal/spi_hal.c | 2 +- 37 files changed, 265 insertions(+), 29 deletions(-) diff --git a/components/esp_driver_ledc/src/ledc.c b/components/esp_driver_ledc/src/ledc.c index 276732afc0..811a7be74b 100644 --- a/components/esp_driver_ledc/src/ledc.c +++ b/components/esp_driver_ledc/src/ledc.c @@ -1280,7 +1280,15 @@ esp_err_t ledc_fade_func_install(int intr_alloc_flags) { LEDC_CHECK(s_ledc_fade_isr_handle == NULL, "fade function already installed", ESP_ERR_INVALID_STATE); //OR intr_alloc_flags with ESP_INTR_FLAG_IRAM because the fade isr is in IRAM - return ledc_isr_register(ledc_fade_isr, NULL, intr_alloc_flags | ESP_INTR_FLAG_IRAM, &s_ledc_fade_isr_handle); + return esp_intr_alloc_intrstatus( + ETS_LEDC_INTR_SOURCE, + intr_alloc_flags | ESP_INTR_FLAG_IRAM, + (uint32_t)ledc_hal_get_fade_end_intr_addr(&(p_ledc_obj[0]->ledc_hal)), + LEDC_LL_FADE_END_INTR_MASK, + ledc_fade_isr, + NULL, + &s_ledc_fade_isr_handle + ); } void ledc_fade_func_uninstall(void) diff --git a/components/esp_driver_sdio/src/sdio_slave.c b/components/esp_driver_sdio/src/sdio_slave.c index ccc56d9ae9..f3b1623a3e 100644 --- a/components/esp_driver_sdio/src/sdio_slave.c +++ b/components/esp_driver_sdio/src/sdio_slave.c @@ -354,15 +354,20 @@ esp_err_t sdio_slave_initialize(sdio_slave_config_t *config) esp_err_t r; intr_handle_t intr_handle = NULL; const int flags = 0; - r = esp_intr_alloc(ETS_SLC0_INTR_SOURCE, flags, sdio_intr, NULL, &intr_handle); - if (r != ESP_OK) { - return r; - } r = init_context(config); - if (r != ESP_OK) { - return r; - } + SDIO_SLAVE_CHECK(r == ESP_OK, "context initialization failed", r); + + r = esp_intr_alloc_intrstatus( + ETS_SLC0_INTR_SOURCE, + flags, + (uint32_t)sdio_slave_hal_get_intr_status_reg(context.hal), + sdio_slave_ll_intr_status_mask, + sdio_intr, + NULL, + &intr_handle + ); + SDIO_SLAVE_CHECK(r == ESP_OK, "interrupt allocation failed", r); context.intr_handle = intr_handle; r = sdio_slave_hw_init(config); diff --git a/components/esp_driver_sdmmc/include/driver/sdmmc_host.h b/components/esp_driver_sdmmc/include/driver/sdmmc_host.h index 26dfaae44a..97dd791e3f 100644 --- a/components/esp_driver_sdmmc/include/driver/sdmmc_host.h +++ b/components/esp_driver_sdmmc/include/driver/sdmmc_host.h @@ -14,7 +14,7 @@ #include "esp_err.h" #include "driver/sdmmc_types.h" #include "driver/sdmmc_default_configs.h" -#include "driver/gpio.h" +#include "soc/gpio_num.h" #ifdef __cplusplus extern "C" { diff --git a/components/esp_driver_spi/src/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c index 59ce304fdf..1e16da71a2 100644 --- a/components/esp_driver_spi/src/gpspi/spi_common.c +++ b/components/esp_driver_spi/src/gpspi/spi_common.c @@ -826,7 +826,7 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * #elif SOC_GDMA_SUPPORTED SPI_CHECK(dma_chan == SPI_DMA_DISABLED || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG); #endif - SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH | ESP_INTR_FLAG_EDGE | ESP_INTR_FLAG_INTRDISABLED)) == 0, "intr flag not allowed", ESP_ERR_INVALID_ARG); + SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH | ESP_INTR_FLAG_EDGE | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_INTRDISABLED)) == 0, "intr flag not allowed", ESP_ERR_INVALID_ARG); #ifndef CONFIG_SPI_MASTER_ISR_IN_IRAM SPI_CHECK((bus_config->intr_flags & ESP_INTR_FLAG_IRAM) == 0, "ESP_INTR_FLAG_IRAM should be disabled when CONFIG_SPI_MASTER_ISR_IN_IRAM is not set.", ESP_ERR_INVALID_ARG); #endif diff --git a/components/esp_driver_spi/src/gpspi/spi_slave.c b/components/esp_driver_spi/src/gpspi/spi_slave.c index debaf74223..f78bacbc2e 100644 --- a/components/esp_driver_spi/src/gpspi/spi_slave.c +++ b/components/esp_driver_spi/src/gpspi/spi_slave.c @@ -148,7 +148,7 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b #elif SOC_GDMA_SUPPORTED SPI_CHECK(dma_chan == SPI_DMA_DISABLED || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG); #endif - SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH | ESP_INTR_FLAG_EDGE | ESP_INTR_FLAG_INTRDISABLED)) == 0, "intr flag not allowed", ESP_ERR_INVALID_ARG); + SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH | ESP_INTR_FLAG_EDGE | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_INTRDISABLED)) == 0, "intr flag not allowed", ESP_ERR_INVALID_ARG); #ifndef CONFIG_SPI_SLAVE_ISR_IN_IRAM SPI_CHECK((bus_config->intr_flags & ESP_INTR_FLAG_IRAM) == 0, "ESP_INTR_FLAG_IRAM should be disabled when CONFIG_SPI_SLAVE_ISR_IN_IRAM is not set.", ESP_ERR_INVALID_ARG); #endif diff --git a/components/esp_driver_uart/src/uart.c b/components/esp_driver_uart/src/uart.c index 38aced1dcd..6f979b4083 100644 --- a/components/esp_driver_uart/src/uart.c +++ b/components/esp_driver_uart/src/uart.c @@ -1944,9 +1944,15 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK); uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK); - ret = esp_intr_alloc(uart_periph_signal[uart_num].irq, intr_alloc_flags, - uart_rx_intr_handler_default, p_uart_obj[uart_num], - &p_uart_obj[uart_num]->intr_handle); + ret = esp_intr_alloc_intrstatus( + uart_periph_signal[uart_num].irq, + intr_alloc_flags, + (uint32_t)uart_hal_get_intr_status_reg(&(uart_context[uart_num].hal)), + UART_LL_INTR_MASK, + uart_rx_intr_handler_default, + p_uart_obj[uart_num], + &p_uart_obj[uart_num]->intr_handle + ); ESP_GOTO_ON_ERROR(ret, err, UART_TAG, "Could not allocate an interrupt for UART"); uart_intr_config_t uart_intr = { diff --git a/components/hal/esp32/include/hal/ledc_ll.h b/components/hal/esp32/include/hal/ledc_ll.h index 0f59bb1ff6..a2e2a520d6 100644 --- a/components/hal/esp32/include/hal/ledc_ll.h +++ b/components/hal/esp32/include/hal/ledc_ll.h @@ -26,6 +26,8 @@ extern "C" { #define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_LSCH0_V) #define LEDC_LL_FRACTIONAL_BITS (8) #define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) +/// Get the mask of the fade end interrupt status register. +#define LEDC_LL_FADE_END_INTR_MASK (0xffffUL << LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S) #define LEDC_LL_GLOBAL_CLOCKS { \ LEDC_SLOW_CLK_APB, \ @@ -513,7 +515,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m * * @param hw Beginning address of the peripheral registers * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t * @param intr_status The fade end interrupt status * * @return None @@ -525,6 +526,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t *intr_status = (value >> int_en_base) & 0xff; } +/** + * @brief Get the address of the fade end interrupt status register. + * + * @param hw Beginning address of the peripheral registers + * @return Pointer to the fade end interrupt status register. + */ +static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw) +{ + return &hw->int_st.val; +} + + /** * @brief Clear fade end interrupt status * diff --git a/components/hal/esp32/include/hal/sdio_slave_ll.h b/components/hal/esp32/include/hal/sdio_slave_ll.h index aa0a001ca6..76cd8ac7f3 100644 --- a/components/hal/esp32/include/hal/sdio_slave_ll.h +++ b/components/hal/esp32/include/hal/sdio_slave_ll.h @@ -36,6 +36,8 @@ extern "C" { #define sdio_slave_ll_get_host(ID) (&HOST) /// Get address of the only HINF registers for ESP32 #define sdio_slave_ll_get_hinf(ID) (&HINF) +/// Get the mask of the interrupt status. +#define sdio_slave_ll_intr_status_mask (0xff | SLC_SLC0_RX_DONE_INT_ST | SLC_SLC0_RX_EOF_INT_ST | SLC_SLC0_TX_DONE_INT_ST) /* * SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t @@ -543,6 +545,17 @@ static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_l slc->slc0_int_clr.val = slv_int; } +/** + * Get the address of the interrupt status register. + * + * @param slc Address of the SLC registers + * @return Address of the interrupt status register + */ +static inline volatile void* sdio_slave_ll_get_intr_status_reg(slc_dev_t *slc) +{ + return &slc->slc0_int_st.val; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32/include/hal/uart_ll.h b/components/hal/esp32/include/hal/uart_ll.h index 2c6500bdb3..b0dfcf42db 100644 --- a/components/hal/esp32/include/hal/uart_ll.h +++ b/components/hal/esp32/include/hal/uart_ll.h @@ -267,6 +267,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) return hw->int_st.val; } +FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw) +{ + return &hw->int_st.val; +} + /** * @brief Clear the UART interrupt status based on the given mask. * diff --git a/components/hal/esp32c2/include/hal/ledc_ll.h b/components/hal/esp32c2/include/hal/ledc_ll.h index 55b393e61f..fab68ae3e5 100644 --- a/components/hal/esp32c2/include/hal/ledc_ll.h +++ b/components/hal/esp32c2/include/hal/ledc_ll.h @@ -26,6 +26,8 @@ extern "C" { #define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V) #define LEDC_LL_FRACTIONAL_BITS (8) #define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) +/// Get the mask of the fade end interrupt status register. +#define LEDC_LL_FADE_END_INTR_MASK (0x3fUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) #define LEDC_LL_GLOBAL_CLOCKS { \ LEDC_SLOW_CLK_PLL_DIV, \ @@ -487,7 +489,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m * * @param hw Beginning address of the peripheral registers * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t * @param intr_status The fade end interrupt status * * @return None @@ -499,6 +500,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t *intr_status = (value >> int_en_base) & 0xff; } +/** + * @brief Get the address of the fade end interrupt status register. + * + * @param hw Beginning address of the peripheral registers + * @return Pointer to the fade end interrupt status register. + */ +static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw) +{ + return &hw->int_st.val; +} + + /** * @brief Clear fade end interrupt status * diff --git a/components/hal/esp32c2/include/hal/uart_ll.h b/components/hal/esp32c2/include/hal/uart_ll.h index 52f9d8f011..013c127213 100644 --- a/components/hal/esp32c2/include/hal/uart_ll.h +++ b/components/hal/esp32c2/include/hal/uart_ll.h @@ -298,6 +298,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) return hw->int_st.val; } +FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw) +{ + return &hw->int_st.val; +} + /** * @brief Clear the UART interrupt status based on the given mask. * diff --git a/components/hal/esp32c3/include/hal/ledc_ll.h b/components/hal/esp32c3/include/hal/ledc_ll.h index 8671b4f1c0..8728d83e3f 100644 --- a/components/hal/esp32c3/include/hal/ledc_ll.h +++ b/components/hal/esp32c3/include/hal/ledc_ll.h @@ -27,6 +27,8 @@ extern "C" { #define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_LSCH0_V) #define LEDC_LL_FRACTIONAL_BITS (8) #define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) +/// Get the mask of the fade end interrupt status register. +#define LEDC_LL_FADE_END_INTR_MASK (0x3fUL << LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S) #define LEDC_LL_GLOBAL_CLOCKS { \ LEDC_SLOW_CLK_APB, \ @@ -488,7 +490,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m * * @param hw Beginning address of the peripheral registers * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t * @param intr_status The fade end interrupt status * * @return None @@ -500,6 +501,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t *intr_status = (value >> int_en_base) & 0xff; } +/** + * @brief Get the address of the fade end interrupt status register. + * + * @param hw Beginning address of the peripheral registers + * @return Pointer to the fade end interrupt status register. + */ +static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw) +{ + return &hw->int_st.val; +} + + /** * @brief Clear fade end interrupt status * diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h index df687ea7dd..c1094583ec 100644 --- a/components/hal/esp32c3/include/hal/uart_ll.h +++ b/components/hal/esp32c3/include/hal/uart_ll.h @@ -303,6 +303,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) return hw->int_st.val; } +FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw) +{ + return &hw->int_st.val; +} + /** * @brief Clear the UART interrupt status based on the given mask. * diff --git a/components/hal/esp32c5/include/hal/uart_ll.h b/components/hal/esp32c5/include/hal/uart_ll.h index 3f2afb7f85..2e51175f9f 100644 --- a/components/hal/esp32c5/include/hal/uart_ll.h +++ b/components/hal/esp32c5/include/hal/uart_ll.h @@ -496,6 +496,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) return hw->int_st.val; } +FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw) +{ + return &hw->int_st.val; +} + /** * @brief Clear the UART interrupt status based on the given mask. * diff --git a/components/hal/esp32c6/include/hal/ledc_ll.h b/components/hal/esp32c6/include/hal/ledc_ll.h index ad2008cc7b..b5a3a9471d 100644 --- a/components/hal/esp32c6/include/hal/ledc_ll.h +++ b/components/hal/esp32c6/include/hal/ledc_ll.h @@ -31,6 +31,8 @@ extern "C" { #define LEDC_LL_FRACTIONAL_BITS (8) #define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) #define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS +/// Get the mask of the fade end interrupt status register. +#define LEDC_LL_FADE_END_INTR_MASK (0x3fUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) #define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST @@ -615,7 +617,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m * * @param hw Beginning address of the peripheral registers * @param speed_mode LEDC speed_mode, low-speed mode only - * @param channel_num LEDC channel index (0-5), select from ledc_channel_t * @param intr_status The fade end interrupt status * * @return None @@ -627,6 +628,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t *intr_status = (value >> int_en_base) & 0xff; } +/** + * @brief Get the address of the fade end interrupt status register. + * + * @param hw Beginning address of the peripheral registers + * @return Pointer to the fade end interrupt status register. + */ +static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw) +{ + return &hw->int_st.val; +} + + /** * @brief Clear fade end interrupt status * diff --git a/components/hal/esp32c6/include/hal/sdio_slave_ll.h b/components/hal/esp32c6/include/hal/sdio_slave_ll.h index 2831edd57b..32fdd870d3 100644 --- a/components/hal/esp32c6/include/hal/sdio_slave_ll.h +++ b/components/hal/esp32c6/include/hal/sdio_slave_ll.h @@ -36,6 +36,8 @@ extern "C" { #define sdio_slave_ll_get_host(ID) (&HOST) /// Get address of the only HINF registers #define sdio_slave_ll_get_hinf(ID) (&HINF) +/// Get the mask of the interrupt status. +#define sdio_slave_ll_intr_status_mask (0xff | SDIO_SLC0_RX_DONE_INT_ST | SDIO_SLC0_RX_EOF_INT_ST | SDIO_SLC0_TX_DONE_INT_ST) /* * SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t @@ -532,6 +534,17 @@ static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_l slc->slc0int_clr.val = slv_int; } +/** + * Get the address of the interrupt status register. + * + * @param slc Address of the SLC registers + * @return Address of the interrupt status register + */ +static inline volatile void* sdio_slave_ll_get_intr_status_reg(slc_dev_t *slc) +{ + return &slc->slc0int_st.val; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c6/include/hal/spi_ll.h b/components/hal/esp32c6/include/hal/spi_ll.h index 9070e079a7..207569b42d 100644 --- a/components/hal/esp32c6/include/hal/spi_ll.h +++ b/components/hal/esp32c6/include/hal/spi_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/hal/esp32c6/include/hal/uart_ll.h b/components/hal/esp32c6/include/hal/uart_ll.h index 2b229d7c7d..f6aa5c030a 100644 --- a/components/hal/esp32c6/include/hal/uart_ll.h +++ b/components/hal/esp32c6/include/hal/uart_ll.h @@ -480,6 +480,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) return hw->int_st.val; } +FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw) +{ + return &hw->int_st.val; +} + /** * @brief Clear the UART interrupt status based on the given mask. * diff --git a/components/hal/esp32c61/include/hal/uart_ll.h b/components/hal/esp32c61/include/hal/uart_ll.h index ecb6ac4b2c..4d29cfd341 100644 --- a/components/hal/esp32c61/include/hal/uart_ll.h +++ b/components/hal/esp32c61/include/hal/uart_ll.h @@ -328,6 +328,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) return hw->int_st.val; } +FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw) +{ + return &hw->int_st.val; +} + /** * @brief Clear the UART interrupt status based on the given mask. * diff --git a/components/hal/esp32h2/include/hal/ledc_ll.h b/components/hal/esp32h2/include/hal/ledc_ll.h index fe3c46d1c3..99e886ebe5 100644 --- a/components/hal/esp32h2/include/hal/ledc_ll.h +++ b/components/hal/esp32h2/include/hal/ledc_ll.h @@ -31,6 +31,8 @@ extern "C" { #define LEDC_LL_FRACTIONAL_BITS (8) #define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) #define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS +/// Get the mask of the fade end interrupt status register. +#define LEDC_LL_FADE_END_INTR_MASK (0x3fUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) /** * @brief Enable peripheral register clock @@ -613,7 +615,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m * * @param hw Beginning address of the peripheral registers * @param speed_mode LEDC speed_mode, low-speed mode only - * @param channel_num LEDC channel index (0-5), select from ledc_channel_t * @param intr_status The fade end interrupt status * * @return None @@ -625,6 +626,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t *intr_status = (value >> int_en_base) & 0xff; } +/** + * @brief Get the address of the fade end interrupt status register. + * + * @param hw Beginning address of the peripheral registers + * @return Pointer to the fade end interrupt status register. + */ +static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw) +{ + return &hw->int_st.val; +} + + /** * @brief Clear fade end interrupt status * diff --git a/components/hal/esp32h2/include/hal/spi_ll.h b/components/hal/esp32h2/include/hal/spi_ll.h index 4496e0c806..65a3801bfe 100644 --- a/components/hal/esp32h2/include/hal/spi_ll.h +++ b/components/hal/esp32h2/include/hal/spi_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/hal/esp32h2/include/hal/uart_ll.h b/components/hal/esp32h2/include/hal/uart_ll.h index 4a77627d83..dd4773cf25 100644 --- a/components/hal/esp32h2/include/hal/uart_ll.h +++ b/components/hal/esp32h2/include/hal/uart_ll.h @@ -330,6 +330,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) return hw->int_st.val; } +FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw) +{ + return &hw->int_st.val; +} + /** * @brief Clear the UART interrupt status based on the given mask. * diff --git a/components/hal/esp32p4/include/hal/ledc_ll.h b/components/hal/esp32p4/include/hal/ledc_ll.h index 3ed1b7015b..06788e1950 100644 --- a/components/hal/esp32p4/include/hal/ledc_ll.h +++ b/components/hal/esp32p4/include/hal/ledc_ll.h @@ -30,6 +30,8 @@ extern "C" { #define LEDC_LL_FRACTIONAL_BITS (8) #define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) #define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS +/// Get the mask of the fade end interrupt status register. +#define LEDC_LL_FADE_END_INTR_MASK (0xffUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) /** * @brief Enable peripheral register clock @@ -507,7 +509,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m * * @param hw Beginning address of the peripheral registers * @param speed_mode LEDC speed_mode, low-speed mode only - * @param channel_num LEDC channel index (0-5), select from ledc_channel_t * @param intr_status The fade end interrupt status * * @return None @@ -519,6 +520,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t *intr_status = (value >> int_en_base) & 0xff; } +/** + * @brief Get the address of the fade end interrupt status register. + * + * @param hw Beginning address of the peripheral registers + * @return Pointer to the fade end interrupt status register. + */ +static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw) +{ + return &hw->int_st.val; +} + + /** * @brief Clear fade end interrupt status * diff --git a/components/hal/esp32p4/include/hal/uart_ll.h b/components/hal/esp32p4/include/hal/uart_ll.h index 6138f27c18..daa889e8e7 100644 --- a/components/hal/esp32p4/include/hal/uart_ll.h +++ b/components/hal/esp32p4/include/hal/uart_ll.h @@ -601,6 +601,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) return hw->int_st.val; } +FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw) +{ + return &hw->int_st.val; +} + /** * @brief Clear the UART interrupt status based on the given mask. * diff --git a/components/hal/esp32s2/include/hal/cache_ll.h b/components/hal/esp32s2/include/hal/cache_ll.h index 0a2ecbde7a..aa55aeeafc 100644 --- a/components/hal/esp32s2/include/hal/cache_ll.h +++ b/components/hal/esp32s2/include/hal/cache_ll.h @@ -282,7 +282,8 @@ static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type * @return true: enabled; false: disabled */ __attribute__((always_inline)) -static inline bool cache_ll_l1_is_icache_enabled(uint32_t cache_id){ +static inline bool cache_ll_l1_is_icache_enabled(uint32_t cache_id) +{ HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); bool enabled; diff --git a/components/hal/esp32s2/include/hal/ledc_ll.h b/components/hal/esp32s2/include/hal/ledc_ll.h index a3ce0b4feb..fb4c0e70a1 100644 --- a/components/hal/esp32s2/include/hal/ledc_ll.h +++ b/components/hal/esp32s2/include/hal/ledc_ll.h @@ -27,6 +27,8 @@ extern "C" { #define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_LSCH0_V) #define LEDC_LL_FRACTIONAL_BITS (8) #define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) +/// Get the mask of the fade end interrupt status register. +#define LEDC_LL_FADE_END_INTR_MASK (0xffUL << LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S) #define LEDC_LL_GLOBAL_CLOCKS { \ LEDC_SLOW_CLK_APB, \ @@ -527,7 +529,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m * * @param hw Beginning address of the peripheral registers * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t * @param intr_status The fade end interrupt status * * @return None @@ -539,6 +540,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t *intr_status = (value >> int_en_base) & 0xff; } +/** + * @brief Get the address of the fade end interrupt status register. + * + * @param hw Beginning address of the peripheral registers + * @return Pointer to the fade end interrupt status register. + */ +static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw) +{ + return &hw->int_st.val; +} + + /** * @brief Clear fade end interrupt status * diff --git a/components/hal/esp32s2/include/hal/uart_ll.h b/components/hal/esp32s2/include/hal/uart_ll.h index 719c1173ad..f215329c20 100644 --- a/components/hal/esp32s2/include/hal/uart_ll.h +++ b/components/hal/esp32s2/include/hal/uart_ll.h @@ -256,6 +256,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) return hw->int_st.val; } +FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw) +{ + return &hw->int_st.val; +} + /** * @brief Clear the UART interrupt status based on the given mask. * diff --git a/components/hal/esp32s3/include/hal/ledc_ll.h b/components/hal/esp32s3/include/hal/ledc_ll.h index 7fd9a6b06f..66c1760332 100644 --- a/components/hal/esp32s3/include/hal/ledc_ll.h +++ b/components/hal/esp32s3/include/hal/ledc_ll.h @@ -27,6 +27,8 @@ extern "C" { #define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_LSCH0_V) #define LEDC_LL_FRACTIONAL_BITS (8) #define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) +/// Get the mask of the fade end interrupt status register. +#define LEDC_LL_FADE_END_INTR_MASK (0xffUL << LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S) #define LEDC_LL_GLOBAL_CLOCKS { \ LEDC_SLOW_CLK_APB, \ @@ -488,7 +490,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m * * @param hw Beginning address of the peripheral registers * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t * @param intr_status The fade end interrupt status * * @return None @@ -500,6 +501,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t *intr_status = (value >> int_en_base) & 0xff; } +/** + * @brief Get the address of the fade end interrupt status register. + * + * @param hw Beginning address of the peripheral registers + * @return Pointer to the fade end interrupt status register. + */ +static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw) +{ + return &hw->int_st.val; +} + + /** * @brief Clear fade end interrupt status * diff --git a/components/hal/esp32s3/include/hal/uart_ll.h b/components/hal/esp32s3/include/hal/uart_ll.h index 76bffbfd6e..261297d1f0 100644 --- a/components/hal/esp32s3/include/hal/uart_ll.h +++ b/components/hal/esp32s3/include/hal/uart_ll.h @@ -313,6 +313,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) return hw->int_ena.val; } +FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw) +{ + return &hw->int_st.val; +} + /** * @brief Read the UART rxfifo. * diff --git a/components/hal/include/hal/ledc_hal.h b/components/hal/include/hal/ledc_hal.h index 18ac920a2d..04d9ba0f9f 100644 --- a/components/hal/include/hal/ledc_hal.h +++ b/components/hal/include/hal/ledc_hal.h @@ -396,6 +396,14 @@ void ledc_hal_get_fade_end_intr_status(ledc_hal_context_t *hal, uint32_t *intr_s */ void ledc_hal_clear_fade_end_intr_status(ledc_hal_context_t *hal, ledc_channel_t channel_num); +/** + * @brief Get the address of the fade end interrupt status register. + * + * @param hal Context of the HAL layer + * @return Pointer to the fade end interrupt status register. + */ +volatile void* ledc_hal_get_fade_end_intr_addr(ledc_hal_context_t *hal); + /** * @brief Get clock config of LEDC timer * diff --git a/components/hal/include/hal/sdio_slave_hal.h b/components/hal/include/hal/sdio_slave_hal.h index a517f6b6d8..c7fc402ece 100644 --- a/components/hal/include/hal/sdio_slave_hal.h +++ b/components/hal/include/hal/sdio_slave_hal.h @@ -532,6 +532,14 @@ uint8_t sdio_slave_hal_host_get_reg(sdio_slave_context_t *hal, int pos); */ void sdio_slave_hal_host_set_reg(sdio_slave_context_t *hal, int pos, uint8_t reg); +/** + * Get the address of the interrupt status register. + * + * @param hal Context of the HAL layer. + * @return Address of the interrupt status register + */ +volatile void* sdio_slave_hal_get_intr_status_reg(sdio_slave_context_t *hal); + #endif // SOC_SDIO_SLAVE_SUPPORTED #ifdef __cplusplus diff --git a/components/hal/include/hal/spi_hal.h b/components/hal/include/hal/spi_hal.h index dff1b6563c..ee44759e61 100644 --- a/components/hal/include/hal/spi_hal.h +++ b/components/hal/include/hal/spi_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/hal/include/hal/spi_slave_hal.h b/components/hal/include/hal/spi_slave_hal.h index 24f89b8c72..9424e99eda 100644 --- a/components/hal/include/hal/spi_slave_hal.h +++ b/components/hal/include/hal/spi_slave_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/hal/include/hal/uart_hal.h b/components/hal/include/hal/uart_hal.h index 6d628f3481..18ad408914 100644 --- a/components/hal/include/hal/uart_hal.h +++ b/components/hal/include/hal/uart_hal.h @@ -106,6 +106,16 @@ typedef struct { */ #define uart_hal_get_intr_ena_status(hal) uart_ll_get_intr_ena_status((hal)->dev) +/** + * @brief Get the pointer to the UART interrupt status register + * + * @param hal Context of the HAL layer + * + * @return UART interrupt status register + */ +#define uart_hal_get_intr_status_reg(hal) uart_ll_get_intr_status_reg((hal)->dev) + + /** * @brief Get the UART pattern char configuration * diff --git a/components/hal/ledc_hal_iram.c b/components/hal/ledc_hal_iram.c index 34884c78e7..3a6279982c 100644 --- a/components/hal/ledc_hal_iram.c +++ b/components/hal/ledc_hal_iram.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -75,3 +75,8 @@ void ledc_hal_clear_fade_end_intr_status(ledc_hal_context_t *hal, ledc_channel_t { ledc_ll_clear_fade_end_intr_status(hal->dev, hal->speed_mode, channel_num); } + +volatile void* ledc_hal_get_fade_end_intr_addr(ledc_hal_context_t *hal) +{ + return ledc_ll_get_fade_end_intr_addr(hal->dev); +} diff --git a/components/hal/sdio_slave_hal.c b/components/hal/sdio_slave_hal.c index 21f4c4c158..3391148d04 100644 --- a/components/hal/sdio_slave_hal.c +++ b/components/hal/sdio_slave_hal.c @@ -721,3 +721,8 @@ void sdio_slave_hal_slvint_fetch_clear(sdio_slave_context_t *hal, sdio_slave_ll_ { sdio_slave_ll_slvint_fetch_clear(hal->slc, out_int_mask); } + +volatile void* sdio_slave_hal_get_intr_status_reg(sdio_slave_context_t *hal) +{ + return sdio_slave_ll_get_intr_status_reg(hal->slc); +} diff --git a/components/hal/spi_hal.c b/components/hal/spi_hal.c index 8d1dca9006..c143d9162a 100644 --- a/components/hal/spi_hal.c +++ b/components/hal/spi_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ From 96d681fc14c03153d3f29cbe988c33dcc7642842 Mon Sep 17 00:00:00 2001 From: Chen Chen Date: Wed, 19 Nov 2025 11:59:51 +0800 Subject: [PATCH 2/2] fix(ledc): fix potential null dereference issue & add test case --- components/esp_driver_ledc/src/ledc.c | 11 +++++- .../test_apps/ledc/main/test_ledc.c | 39 +++++++++++++++++++ components/hal/include/hal/ledc_hal.h | 19 +++++---- components/hal/include/hal/sdio_slave_hal.h | 10 ++--- components/hal/ledc_hal_iram.c | 5 --- components/hal/spi_hal.c | 2 +- 6 files changed, 66 insertions(+), 20 deletions(-) diff --git a/components/esp_driver_ledc/src/ledc.c b/components/esp_driver_ledc/src/ledc.c index 811a7be74b..f383c6e11c 100644 --- a/components/esp_driver_ledc/src/ledc.c +++ b/components/esp_driver_ledc/src/ledc.c @@ -1279,11 +1279,20 @@ exit: esp_err_t ledc_fade_func_install(int intr_alloc_flags) { LEDC_CHECK(s_ledc_fade_isr_handle == NULL, "fade function already installed", ESP_ERR_INVALID_STATE); + + ledc_mode_t speed_mode = LEDC_SPEED_MODE_MAX; + for (int i = 0; i < LEDC_SPEED_MODE_MAX; i++) { + if (p_ledc_obj[i] != NULL) { + speed_mode = i; + break; + } + } + //OR intr_alloc_flags with ESP_INTR_FLAG_IRAM because the fade isr is in IRAM return esp_intr_alloc_intrstatus( ETS_LEDC_INTR_SOURCE, intr_alloc_flags | ESP_INTR_FLAG_IRAM, - (uint32_t)ledc_hal_get_fade_end_intr_addr(&(p_ledc_obj[0]->ledc_hal)), + (uint32_t)ledc_hal_get_fade_end_intr_addr(&(p_ledc_obj[speed_mode]->ledc_hal)), LEDC_LL_FADE_END_INTR_MASK, ledc_fade_isr, NULL, diff --git a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c index fe9e591810..21806c4982 100644 --- a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c +++ b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c @@ -298,6 +298,45 @@ TEST_CASE("LEDC fade with step", "[ledc]") ledc_fade_func_uninstall(); } +#if SOC_LEDC_SUPPORT_HS_MODE +TEST_CASE("LEDC fade install with low speed mode only", "[ledc]") +{ + // This test verifies that ledc_fade_func_install works correctly when only + // LEDC_LOW_SPEED_MODE is initialized, without initializing LEDC_HIGH_SPEED_MODE. + // This tests the fix for NULL pointer dereference issue. + + // Only initialize low speed mode, do NOT initialize high speed mode + ledc_channel_config_t ledc_ch_config = initialize_channel_config(); + ledc_ch_config.speed_mode = LEDC_LOW_SPEED_MODE; + ledc_ch_config.duty = 0; + ledc_ch_config.channel = LEDC_CHANNEL_0; + ledc_ch_config.timer_sel = LEDC_TIMER_0; + + ledc_timer_config_t ledc_time_config = create_default_timer_config(); + ledc_time_config.speed_mode = LEDC_LOW_SPEED_MODE; + ledc_time_config.timer_num = LEDC_TIMER_0; + + // Initialize only low speed mode + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); + TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); + vTaskDelay(5 / portTICK_PERIOD_MS); + TEST_ESP_OK(ledc_fade_func_install(0)); + + // Verify that fade functionality works correctly with low speed mode + TEST_ESP_OK(ledc_set_fade_with_time(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 4000, 200)); + TEST_ESP_OK(ledc_fade_start(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, LEDC_FADE_WAIT_DONE)); + TEST_ASSERT_EQUAL_INT32(4000, ledc_get_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0)); + + // Test fade down + TEST_ESP_OK(ledc_set_fade_with_time(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0, 200)); + TEST_ESP_OK(ledc_fade_start(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, LEDC_FADE_WAIT_DONE)); + TEST_ASSERT_EQUAL_INT32(0, ledc_get_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0)); + + // Cleanup + ledc_fade_func_uninstall(); +} +#endif // SOC_LEDC_SUPPORT_HS_MODE + TEST_CASE("LEDC fast switching duty with fade_wait_done", "[ledc]") { const ledc_mode_t test_speed_mode = TEST_SPEED_MODE; diff --git a/components/hal/include/hal/ledc_hal.h b/components/hal/include/hal/ledc_hal.h index 04d9ba0f9f..c8cafc8449 100644 --- a/components/hal/include/hal/ledc_hal.h +++ b/components/hal/include/hal/ledc_hal.h @@ -396,14 +396,6 @@ void ledc_hal_get_fade_end_intr_status(ledc_hal_context_t *hal, uint32_t *intr_s */ void ledc_hal_clear_fade_end_intr_status(ledc_hal_context_t *hal, ledc_channel_t channel_num); -/** - * @brief Get the address of the fade end interrupt status register. - * - * @param hal Context of the HAL layer - * @return Pointer to the fade end interrupt status register. - */ -volatile void* ledc_hal_get_fade_end_intr_addr(ledc_hal_context_t *hal); - /** * @brief Get clock config of LEDC timer * @@ -415,6 +407,17 @@ volatile void* ledc_hal_get_fade_end_intr_addr(ledc_hal_context_t *hal); */ void ledc_hal_get_clk_cfg(ledc_hal_context_t *hal, ledc_timer_t timer_sel, ledc_clk_cfg_t *clk_cfg); +/** + * @brief Get the address of the fade end interrupt status register. + * + * @param hal Context of the HAL layer + * @return Pointer to the fade end interrupt status register. + */ +static inline volatile void* ledc_hal_get_fade_end_intr_addr(ledc_hal_context_t *hal) +{ + return ledc_ll_get_fade_end_intr_addr(hal->dev); +} + #endif //#if SOC_LEDC_SUPPORTED #ifdef __cplusplus diff --git a/components/hal/include/hal/sdio_slave_hal.h b/components/hal/include/hal/sdio_slave_hal.h index c7fc402ece..94588c26af 100644 --- a/components/hal/include/hal/sdio_slave_hal.h +++ b/components/hal/include/hal/sdio_slave_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -153,7 +153,7 @@ extern "C" { #endif #if SOC_SDIO_SLAVE_SUPPORTED -/// Space used for each sending descriptor. Should initialize the sendbuf accoring to this size. +/// Space used for each sending descriptor. Should initialize the sendbuf according to this size. #define SDIO_SLAVE_SEND_DESC_SIZE sizeof(sdio_slave_hal_send_desc_t) @@ -239,7 +239,7 @@ typedef struct { /** * Initialize the HAL, should provide buffers to the context and configure the - * members before this funciton is called. + * members before this function is called. * * @param hal Context of the HAL layer. */ @@ -350,7 +350,7 @@ esp_err_t sdio_slave_hal_send_get_next_finished_arg(sdio_slave_context_t *hal, v * * @note Only call when the DMA is stopped! * @param hal Context of the HAL layer. - * @param out_arg Argument indiciating the buffer to send + * @param out_arg Argument indicating the buffer to send * @param out_return_cnt Space in the queue released after this descriptor is flushed. * @return * - ESP_ERR_INVALID_STATE: This function call be called only when the DMA is stopped. @@ -476,7 +476,7 @@ void sdio_slave_hal_recv_flush_one_buffer(sdio_slave_context_t *hal); /** * Enable some of the interrupts for the host. * - * @note May have concurrency issue wit the host or other tasks, suggest only use it during + * @note May have concurrency issue with the host or other tasks, suggest only use it during * initialization. * @param hal Context of the HAL layer. * @param mask Bitwise mask for the interrupts to enable. diff --git a/components/hal/ledc_hal_iram.c b/components/hal/ledc_hal_iram.c index 3a6279982c..804473132c 100644 --- a/components/hal/ledc_hal_iram.c +++ b/components/hal/ledc_hal_iram.c @@ -75,8 +75,3 @@ void ledc_hal_clear_fade_end_intr_status(ledc_hal_context_t *hal, ledc_channel_t { ledc_ll_clear_fade_end_intr_status(hal->dev, hal->speed_mode, channel_num); } - -volatile void* ledc_hal_get_fade_end_intr_addr(ledc_hal_context_t *hal) -{ - return ledc_ll_get_fade_end_intr_addr(hal->dev); -} diff --git a/components/hal/spi_hal.c b/components/hal/spi_hal.c index c143d9162a..5a3db57521 100644 --- a/components/hal/spi_hal.c +++ b/components/hal/spi_hal.c @@ -57,7 +57,7 @@ void spi_hal_sct_init(spi_hal_context_t *hal) { spi_ll_conf_state_enable(hal->hw, true); spi_ll_set_magic_number(hal->hw, SPI_LL_SCT_MAGIC_NUMBER); - spi_ll_disable_int(hal->hw); //trans_done intr enabled in `add device` phase, sct mode shoud use sct_trans_done only + spi_ll_disable_int(hal->hw); //trans_done intr enabled in `add device` phase, sct mode should use sct_trans_done only spi_ll_enable_intr(hal->hw, SPI_LL_INTR_SEG_DONE); spi_ll_set_intr(hal->hw, SPI_LL_INTR_SEG_DONE); }