From 5faff98cc55ba2ca036abdebb034967661627a41 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mattias=20Sch=C3=A4ffersmann?= Date: Wed, 19 Nov 2025 19:16:53 +0100 Subject: [PATCH 1/2] fix(hw_support): Fix crash when reconfiguring flash from 40 to 80 MHz Reading from the flash while it is being reconfigured leads to data corruption and a crash when the reconfiguration code is located in flash. This is only an issue if a device has a bootloader that runs with 40 MHz flash and an application flashed via OTA that runs with 80 MHz flash. If bootloader and application run with the same flash speed, the reconfiguration is basically a no-op and no data corruption occurs. Fix reconfiguration by placing the code back into IRAM. Issue introduced in: 7549d08 Closes: https://github.com/espressif/esp-idf/pull/17905 --- components/esp_system/port/cpu_start.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 1ad4fd6316..e2d2af515d 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -655,6 +655,20 @@ MSPI_INIT_ATTR void mspi_init(void) } #endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#if CONFIG_IDF_TARGET_ESP32 && !CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_SPIRAM_BOOT_HW_INIT +/* + * Adjust flash configuration. This must be placed in IRAM because running from flash, + * while it is being reconfigured, will result in corrupt data being read. + */ +NOINLINE_ATTR IRAM_ATTR static void configure_flash(esp_image_header_t *fhdr) +{ + bootloader_flash_gpio_config(fhdr); + bootloader_flash_dummy_config(fhdr); + bootloader_flash_clock_config(fhdr); + bootloader_flash_cs_timing_config(); +} +#endif // CONFIG_IDF_TARGET_ESP32 && !CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_SPIRAM_BOOT_HW_INIT + /* * Initialize other parts of the system, including other CPUs. * As CPU0 needs to disable the cache in system_early_init function, the other cores are not allowed to run with the @@ -897,10 +911,7 @@ NOINLINE_ATTR static void system_early_init(const soc_reset_reason_t *rst_reas) #if CONFIG_IDF_TARGET_ESP32 #if !CONFIG_SPIRAM_BOOT_HW_INIT // If psram is uninitialized, we need to improve some flash configuration. - bootloader_flash_clock_config(&fhdr); - bootloader_flash_gpio_config(&fhdr); - bootloader_flash_dummy_config(&fhdr); - bootloader_flash_cs_timing_config(); + configure_flash(&fhdr); #endif //!CONFIG_SPIRAM_BOOT_HW_INIT #endif //CONFIG_IDF_TARGET_ESP32 From 206274d29893ad9109a26970b88437c625ded6d4 Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Sun, 4 Jan 2026 11:23:42 +0800 Subject: [PATCH 2/2] refactor(startup): make flash_init_state static --- components/esp_system/port/cpu_start.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index e2d2af515d..2e9cc96272 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -590,7 +590,8 @@ MSPI_INIT_ATTR void sys_rtc_init(const soc_reset_reason_t *rst_reas) esp_rtc_init(); } -NOINLINE_ATTR IRAM_ATTR void flash_init_state(void) +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +static NOINLINE_ATTR IRAM_ATTR void flash_init_state(void) { /** * This function initialise the Flash chip to the user-defined settings. @@ -607,7 +608,6 @@ NOINLINE_ATTR IRAM_ATTR void flash_init_state(void) #endif } -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP MSPI_INIT_ATTR void mspi_init(void) { #if CONFIG_ESPTOOLPY_OCT_FLASH && !CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT