From defaa4340bc6ddf6dbb9b8e94020e1354cb91080 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Mon, 16 Mar 2026 12:24:52 +0800 Subject: [PATCH] fix(esp_hw_support): adjust PSRAM half-sleep resume handling for CONFIG_SPIRAM_XIP_FROM_PSRAM --- components/esp_hw_support/sleep_modes.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index c350649201..fe308d2f43 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -993,6 +993,12 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint /* Cache Resume 1: Resume cache for continue running*/ resume_cache(); resume_timers(sleep_flags); +#if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED && CONFIG_SPIRAM_XIP_FROM_PSRAM + // Code outside of esp_sleep_start_safe may be linked to FLASH, and if CONFIG_SPIRAM_XIP_FROM_PSRAM + // is enabled, code in Flash will be copied to PSRAM for execution. We need to wait here until + // PSRAM exits half-sleep before returning. + esp_psram_impl_resume_from_halfsleep_mode(s_config.rtc_clk_cal_period); +#endif } return result; } @@ -1391,10 +1397,6 @@ static SLEEP_FN_ATTR esp_err_t esp_light_sleep_inner(uint32_t sleep_flags, uint3 #endif } -#if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED - esp_psram_impl_resume_from_halfsleep_mode(s_config.rtc_clk_cal_period); -#endif - #if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION if (sleep_flags & RTC_SLEEP_PD_VDDSDIO) { /* Cache Resume 2: flash is ready now, we can resume the cache and access flash safely after */ @@ -1679,6 +1681,14 @@ esp_err_t esp_light_sleep_start(void) } #endif +#if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED && !CONFIG_SPIRAM_XIP_FROM_PSRAM + // If CONFIG_SPIRAM_XIP_FROM_PSRAM is not enabled, the sleep-wake process + // prior to this point does not access the PSRAM, so we can postpone waiting + // for the PSRAM to resume until here, in order to reuse the time overhead + // of the wake-up process as much as possible. + esp_psram_impl_resume_from_halfsleep_mode(s_config.rtc_clk_cal_period); +#endif + #if !CONFIG_FREERTOS_UNICORE esp_ipc_isr_stall_resume(); #if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && SOC_PM_CPU_RETENTION_BY_SW