diff --git a/components/efuse/esp32c5/esp_efuse_table.c b/components/efuse/esp32c5/esp_efuse_table.c
index 2986775f3b..d6c8a5cebc 100644
--- a/components/efuse/esp32c5/esp_efuse_table.c
+++ b/components/efuse/esp32c5/esp_efuse_table.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,7 +9,7 @@
 #include <assert.h>
 #include "esp_efuse_table.h"
 
-// md5_digest_table a89a21bde56c3936f31af16ba1de1fe3
+// md5_digest_table e18555ab3140262c47fb3f6a03944676
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -391,6 +391,10 @@ static const esp_efuse_desc_t WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF,
 };
 
+static const esp_efuse_desc_t WR_DIS_PVT_DBIAS[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of PVT_DBIAS,
+};
+
 static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
     {EFUSE_BLK0, 22, 1}, 	 // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
 };
@@ -869,6 +873,10 @@ static const esp_efuse_desc_t ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
     {EFUSE_BLK2, 245, 4}, 	 // [] Gap between ADC1 CH5 and average initcode,
 };
 
+static const esp_efuse_desc_t PVT_DBIAS[] = {
+    {EFUSE_BLK2, 249, 5}, 	 // [] Average initcode of ADC1 atten0,
+};
+
 static const esp_efuse_desc_t USER_DATA[] = {
     {EFUSE_BLK3, 0, 256}, 	 // [BLOCK_USR_DATA] User data,
 };
@@ -1379,6 +1387,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_DBIAS[] = {
+    &WR_DIS_PVT_DBIAS[0],    		// [] wr_dis of PVT_DBIAS
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
     &WR_DIS_BLOCK_USR_DATA[0],    		// [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
     NULL
@@ -1975,6 +1988,11 @@ const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_PVT_DBIAS[] = {
+    &PVT_DBIAS[0],    		// [] Average initcode of ADC1 atten0
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
     &USER_DATA[0],    		// [BLOCK_USR_DATA] User data
     NULL
diff --git a/components/efuse/esp32c5/esp_efuse_table.csv b/components/efuse/esp32c5/esp_efuse_table.csv
index bb8065a4e7..7be5debfcf 100644
--- a/components/efuse/esp32c5/esp_efuse_table.csv
+++ b/components/efuse/esp32c5/esp_efuse_table.csv
@@ -9,7 +9,7 @@
 # this will generate new source files, next rebuild all the sources.
 # !!!!!!!!!!! #
 
-# This file was generated by regtools.py based on the efuses.yaml file with the version: 31c7fe3f5f4e0a55b178a57126c0aca7
+# This file was generated by regtools.py based on the efuses.yaml file with the version: 5fa19c47032b7b37cf3859318065fb59
 
 WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
 WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
@@ -105,6 +105,7 @@ WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis
 WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
 WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
 WR_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
+WR_DIS.PVT_DBIAS,                                EFUSE_BLK0,  21,   1, [] wr_dis of PVT_DBIAS
 WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
 WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,  22,   1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
 WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
@@ -229,6 +230,7 @@ ADC1_CH2_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 233,   4, [] Gap be
 ADC1_CH3_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 237,   4, [] Gap between ADC1 CH3 and average initcode
 ADC1_CH4_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 241,   4, [] Gap between ADC1 CH4 and average initcode
 ADC1_CH5_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 245,   4, [] Gap between ADC1 CH5 and average initcode
+PVT_DBIAS,                                       EFUSE_BLK2, 249,   5, [] Average initcode of ADC1 atten0
 USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
 USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
 KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data
diff --git a/components/efuse/esp32c5/include/esp_efuse_table.h b/components/efuse/esp32c5/include/esp_efuse_table.h
index b736956047..856cae0b42 100644
--- a/components/efuse/esp32c5/include/esp_efuse_table.h
+++ b/components/efuse/esp32c5/include/esp_efuse_table.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,7 @@ extern "C" {
 
 #include "esp_efuse.h"
 
-// md5_digest_table a89a21bde56c3936f31af16ba1de1fe3
+// md5_digest_table e18555ab3140262c47fb3f6a03944676
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -118,6 +118,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_DBIAS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
 #define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
@@ -260,6 +261,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
 extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
 extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
 extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PVT_DBIAS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
 #define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
diff --git a/components/soc/esp32c5/register/soc/efuse_reg.h b/components/soc/esp32c5/register/soc/efuse_reg.h
index 57104f378c..e8fc24687c 100644
--- a/components/soc/esp32c5/register/soc/efuse_reg.h
+++ b/components/soc/esp32c5/register/soc/efuse_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0 OR MIT
  */
@@ -1238,13 +1238,20 @@ extern "C" {
 #define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S)
 #define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V  0x0000000FU
 #define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S  21
-/** EFUSE_RESERVED_2_249 : R; bitpos: [31:25]; default: 0;
+/** EFUSE_PVT_DBIAS : R; bitpos: [29:25]; default: 0;
+ *  Average initcode of ADC1 atten0
+ */
+#define EFUSE_PVT_DBIAS    0x0000001FU
+#define EFUSE_PVT_DBIAS_M  (EFUSE_PVT_DBIAS_V << EFUSE_PVT_DBIAS_S)
+#define EFUSE_PVT_DBIAS_V  0x0000001FU
+#define EFUSE_PVT_DBIAS_S  25
+/** EFUSE_RESERVED_2_254 : R; bitpos: [31:30]; default: 0;
  *  reserved
  */
-#define EFUSE_RESERVED_2_249    0x0000007FU
-#define EFUSE_RESERVED_2_249_M  (EFUSE_RESERVED_2_249_V << EFUSE_RESERVED_2_249_S)
-#define EFUSE_RESERVED_2_249_V  0x0000007FU
-#define EFUSE_RESERVED_2_249_S  25
+#define EFUSE_RESERVED_2_254    0x00000003U
+#define EFUSE_RESERVED_2_254_M  (EFUSE_RESERVED_2_254_V << EFUSE_RESERVED_2_254_S)
+#define EFUSE_RESERVED_2_254_V  0x00000003U
+#define EFUSE_RESERVED_2_254_S  30
 
 /** EFUSE_RD_USR_DATA0_REG register
  *  Represents rd_usr_data0
diff --git a/components/soc/esp32c5/register/soc/efuse_struct.h b/components/soc/esp32c5/register/soc/efuse_struct.h
index 99a51ece0b..5df3278172 100644
--- a/components/soc/esp32c5/register/soc/efuse_struct.h
+++ b/components/soc/esp32c5/register/soc/efuse_struct.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0 OR MIT
  */
@@ -863,10 +863,14 @@ typedef union {
          *  Gap between ADC1 CH5 and average initcode
          */
         uint32_t adc1_ch5_atten0_initcode_diff:4;
-        /** reserved_2_249 : R; bitpos: [31:25]; default: 0;
+        /** pvt_dbias : R; bitpos: [29:25]; default: 0;
+         *  Average initcode of ADC1 atten0
+         */
+        uint32_t pvt_dbias:5;
+        /** reserved_2_254 : R; bitpos: [31:30]; default: 0;
          *  reserved
          */
-        uint32_t reserved_2_249:7;
+        uint32_t reserved_2_254:2;
     };
     uint32_t val;
 } efuse_rd_sys_part1_data7_reg_t;