diff --git a/components/esp_hal_usb/README.md b/components/esp_hal_usb/README.md
index 490b955c9b..91698d04d5 100644
--- a/components/esp_hal_usb/README.md
+++ b/components/esp_hal_usb/README.md
@@ -51,3 +51,20 @@ The HAL functions primarily serve ESP-IDF USB drivers, primarily the [USB Host s
 
 - `soc`: Provides chip-specific register definitions
 - `hal`: Core hardware abstraction utilities and macros
+
+## Hardware configuration
+
+The USB-DWC2 peripheral has many internal configuration parameters. The configuration is saved `GHWCFGx` registers. Configuration parameters which are often checked in run-time, are cached in USB-HAL context variable `usb_dwc_hal_context_t::constant_config` to limit access to the registers and offload system bus.
+
+### Selected configuration parameters across ESP SoCs
+
+|                    | S2, S3, H4 & P4-OTG1.1 | P4-OTG2.0, version < 3  | P4-OTG2.0, version >= 3 |
+|--------------------|------------------------|-------------------------|-------------------------|
+| HS PHY interface   | None                   | UTMI+ 16bit             | UTMI+ 16bit             |
+| Single point       | Yes                    | No (SPLIT supported)    | No (SPLIT supported)    |
+| Number of channels | 8                      | 16                      | 16                      |
+| FIFO depth         | 256 lines (1024 bytes) | 1024 lines (4096 bytes) | 1024 lines (4096 bytes) |
+| Perio queue depth  | 8                      | 4                       | 16                      |
+| NPerio queue depth | 4                      | 4                       | 8                       |
+| Transfer cnt width | 16bits (max 65,535)    | 16bits (max 65,535)     | 19bits (max 524,287)    |
+| Packet cnt width   | 7bits (max 127)        | 7bits (max 127)         | 10bits (max 1,023)      |
diff --git a/components/esp_hal_usb/esp32h4/include/hal/usb_dwc_ll.h b/components/esp_hal_usb/esp32h4/include/hal/usb_dwc_ll.h
index 5b4dc74621..3a29756850 100644
--- a/components/esp_hal_usb/esp32h4/include/hal/usb_dwc_ll.h
+++ b/components/esp_hal_usb/esp32h4/include/hal/usb_dwc_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,6 @@
 #include <stdbool.h>
 #include "esp_attr.h"
 #include "soc/usb_dwc_struct.h"
-#include "soc/usb_dwc_cfg.h"
 #include "hal/usb_dwc_types.h"
 #include "hal/misc.h"
 
@@ -354,6 +353,41 @@ static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
     return hw->ghwcfg3_reg.dfifodepth;
 }
 
+/**
+ * @brief Get transfer size counter width
+ *
+ * For each transfer, the USB-DWC core keeps track of number of bytes for the particular transfer.
+ * Hence, maximum transfer size is limited by (2^xfer_size_width - 1) bytes
+ *
+ * Minimum transfer size counter width is 11. So value of 0 of xfersizewidth field in the register must be interpreted as 11.
+ *
+ * @see USB-DWC databook Table 5-26
+ * @param[in] hw Start address of the DWC_OTG registers
+ * @return Effective bitwidth of the transfer size counter
+ */
+static inline unsigned usb_dwc_ll_ghwcfg_get_xfer_size_width(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg3_reg.xfersizewidth + 11;
+}
+
+/**
+ * @brief Get packet counter width
+ *
+ * For each transfer, the USB-DWC core keeps track of the number of packets needed for the particular transfer
+ * and its endpoint's Maximum Packet Size.
+ * Hence, maximum transfer size is limited by MPS * (2^packet_counter_width - 1)
+ *
+ * Minimum packet counter width is 4. So value of 0 of pktsizewidth field in the register must be interpreted as 4.
+ *
+ * @see USB-DWC databook Table 5-26
+ * @param[in] hw Start address of the DWC_OTG registers
+ * @return Effective bitwidth of the packet counter
+ */
+static inline unsigned usb_dwc_ll_ghwcfg_get_packet_size_width(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg3_reg.pktsizewidth + 4;
+}
+
 static inline unsigned usb_dwc_ll_ghwcfg_get_hsphy_type(usb_dwc_dev_t *hw)
 {
     return hw->ghwcfg2_reg.hsphytype;
diff --git a/components/esp_hal_usb/esp32p4/include/hal/usb_dwc_ll.h b/components/esp_hal_usb/esp32p4/include/hal/usb_dwc_ll.h
index 0f0feb9022..d79133ca5d 100644
--- a/components/esp_hal_usb/esp32p4/include/hal/usb_dwc_ll.h
+++ b/components/esp_hal_usb/esp32p4/include/hal/usb_dwc_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -376,6 +376,41 @@ static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
     return hw->ghwcfg3_reg.dfifodepth;
 }
 
+/**
+ * @brief Get transfer size counter width
+ *
+ * For each transfer, the USB-DWC core keeps track of number of bytes for the particular transfer.
+ * Hence, maximum transfer size is limited by (2^xfer_size_width - 1) bytes
+ *
+ * Minimum transfer size counter width is 11. So value of 0 of xfersizewidth field in the register must be interpreted as 11.
+ *
+ * @see USB-DWC databook Table 5-26
+ * @param[in] hw Start address of the DWC_OTG registers
+ * @return Effective bitwidth of the transfer size counter
+ */
+static inline unsigned usb_dwc_ll_ghwcfg_get_xfer_size_width(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg3_reg.xfersizewidth + 11;
+}
+
+/**
+ * @brief Get packet counter width
+ *
+ * For each transfer, the USB-DWC core keeps track of the number of packets needed for the particular transfer
+ * and its endpoint's Maximum Packet Size.
+ * Hence, maximum transfer size is limited by MPS * (2^packet_counter_width - 1)
+ *
+ * Minimum packet counter width is 4. So value of 0 of pktsizewidth field in the register must be interpreted as 4.
+ *
+ * @see USB-DWC databook Table 5-26
+ * @param[in] hw Start address of the DWC_OTG registers
+ * @return Effective bitwidth of the packet counter
+ */
+static inline unsigned usb_dwc_ll_ghwcfg_get_packet_size_width(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg3_reg.pktsizewidth + 4;
+}
+
 static inline unsigned usb_dwc_ll_ghwcfg_get_hsphy_type(usb_dwc_dev_t *hw)
 {
     return hw->ghwcfg2_reg.hsphytype;
diff --git a/components/esp_hal_usb/esp32s2/include/hal/usb_dwc_ll.h b/components/esp_hal_usb/esp32s2/include/hal/usb_dwc_ll.h
index bcc0a9d278..5ba840c13e 100644
--- a/components/esp_hal_usb/esp32s2/include/hal/usb_dwc_ll.h
+++ b/components/esp_hal_usb/esp32s2/include/hal/usb_dwc_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,6 @@
 #include <stdbool.h>
 #include "esp_attr.h"
 #include "soc/usb_dwc_struct.h"
-#include "soc/usb_dwc_cfg.h"
 #include "hal/usb_dwc_types.h"
 #include "hal/misc.h"
 
@@ -352,6 +351,41 @@ static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
     return hw->ghwcfg3_reg.dfifodepth;
 }
 
+/**
+ * @brief Get transfer size counter width
+ *
+ * For each transfer, the USB-DWC core keeps track of number of bytes for the particular transfer.
+ * Hence, maximum transfer size is limited by (2^xfer_size_width - 1) bytes
+ *
+ * Minimum transfer size counter width is 11. So value of 0 of xfersizewidth field in the register must be interpreted as 11.
+ *
+ * @see USB-DWC databook Table 5-26
+ * @param[in] hw Start address of the DWC_OTG registers
+ * @return Effective bitwidth of the transfer size counter
+ */
+static inline unsigned usb_dwc_ll_ghwcfg_get_xfer_size_width(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg3_reg.xfersizewidth + 11;
+}
+
+/**
+ * @brief Get packet counter width
+ *
+ * For each transfer, the USB-DWC core keeps track of the number of packets needed for the particular transfer
+ * and its endpoint's Maximum Packet Size.
+ * Hence, maximum transfer size is limited by MPS * (2^packet_counter_width - 1)
+ *
+ * Minimum packet counter width is 4. So value of 0 of pktsizewidth field in the register must be interpreted as 4.
+ *
+ * @see USB-DWC databook Table 5-26
+ * @param[in] hw Start address of the DWC_OTG registers
+ * @return Effective bitwidth of the packet counter
+ */
+static inline unsigned usb_dwc_ll_ghwcfg_get_packet_size_width(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg3_reg.pktsizewidth + 4;
+}
+
 static inline unsigned usb_dwc_ll_ghwcfg_get_hsphy_type(usb_dwc_dev_t *hw)
 {
     return hw->ghwcfg2_reg.hsphytype;
diff --git a/components/esp_hal_usb/esp32s3/include/hal/usb_dwc_ll.h b/components/esp_hal_usb/esp32s3/include/hal/usb_dwc_ll.h
index 97c1290ad9..93ea797ec2 100644
--- a/components/esp_hal_usb/esp32s3/include/hal/usb_dwc_ll.h
+++ b/components/esp_hal_usb/esp32s3/include/hal/usb_dwc_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,6 @@
 #include <stdbool.h>
 #include "esp_attr.h"
 #include "soc/usb_dwc_struct.h"
-#include "soc/usb_dwc_cfg.h"
 #include "hal/usb_dwc_types.h"
 #include "hal/misc.h"
 
@@ -352,6 +351,41 @@ static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
     return hw->ghwcfg3_reg.dfifodepth;
 }
 
+/**
+ * @brief Get transfer size counter width
+ *
+ * For each transfer, the USB-DWC core keeps track of number of bytes for the particular transfer.
+ * Hence, maximum transfer size is limited by (2^xfer_size_width - 1) bytes
+ *
+ * Minimum transfer size counter width is 11. So value of 0 of xfersizewidth field in the register must be interpreted as 11.
+ *
+ * @see USB-DWC databook Table 5-26
+ * @param[in] hw Start address of the DWC_OTG registers
+ * @return Effective bitwidth of the transfer size counter
+ */
+static inline unsigned usb_dwc_ll_ghwcfg_get_xfer_size_width(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg3_reg.xfersizewidth + 11;
+}
+
+/**
+ * @brief Get packet counter width
+ *
+ * For each transfer, the USB-DWC core keeps track of the number of packets needed for the particular transfer
+ * and its endpoint's Maximum Packet Size.
+ * Hence, maximum transfer size is limited by MPS * (2^packet_counter_width - 1)
+ *
+ * Minimum packet counter width is 4. So value of 0 of pktsizewidth field in the register must be interpreted as 4.
+ *
+ * @see USB-DWC databook Table 5-26
+ * @param[in] hw Start address of the DWC_OTG registers
+ * @return Effective bitwidth of the packet counter
+ */
+static inline unsigned usb_dwc_ll_ghwcfg_get_packet_size_width(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg3_reg.pktsizewidth + 4;
+}
+
 static inline unsigned usb_dwc_ll_ghwcfg_get_hsphy_type(usb_dwc_dev_t *hw)
 {
     return hw->ghwcfg2_reg.hsphytype;
diff --git a/components/esp_hal_usb/include/hal/usb_dwc_hal.h b/components/esp_hal_usb/include/hal/usb_dwc_hal.h
index 3b567a5718..9e1d777b82 100644
--- a/components/esp_hal_usb/include/hal/usb_dwc_hal.h
+++ b/components/esp_hal_usb/include/hal/usb_dwc_hal.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -174,10 +174,13 @@ typedef struct {
     usb_dwc_hal_fifo_config_t fifo_config;      /**< FIFO sizes configuration */
 
     // Configuration of the USB-DWC core. Read from read-only HW registers
+    // These constants are cached from HW registers to avoid repeated reads
     struct {
         unsigned chan_num_total;                /**< Total number of channels for this configuration */
         unsigned hsphy_type;                    /**< HS PHY type of this configuration */
         unsigned fifo_size;                     /**< Total FIFO size [in lines] in this configuration */
+        unsigned max_size_byte_limit;           /**< Maximum size of a transfer in bytes */
+        unsigned max_size_packet_limit;         /**< Maximum size of a transfer in packets */
     } constant_config;
 
     union {
@@ -290,6 +293,25 @@ void usb_dwc_hal_set_fifo_config(usb_dwc_hal_context_t *hal, const usb_dwc_hal_f
  */
 void usb_dwc_hal_get_mps_limits(usb_dwc_hal_context_t *hal, usb_hal_fifo_mps_limits_t *mps_limits);
 
+/**
+ * @brief Get Transfer Size limit
+ *
+ * There are 2 constraints on the size of a transfer:
+ * 1. Maximum transfer size: The maximum total size of data that can be transferred in a single transfer.
+ *    This is determined by the width of the transfer size counter in the hardware
+ * 2. Maximum packet count: The maximum number of packets that can be transferred in a single transfer.
+ *    This is determined by the width of the packet counter in the hardware
+ *
+ * The actual maximum transfer size of a transfer is the minimum of (xfer_size, packet_count * MPS), where MPS is the maximum packet size of the endpoint.
+ *
+ * @see USB-DWC databook Table 5-26
+ *
+ * @param[in] hal Context of the HAL layer
+ * @param[in] mps Maximum packet size of the endpoint in bytes
+ * @return Maximum transfer size in bytes based on the hardware counters
+ */
+size_t usb_dwc_hal_get_xfer_size_limit(usb_dwc_hal_context_t *hal, uint16_t mps);
+
 // ---------------------------------------------------- Host Port ------------------------------------------------------
 
 // ------------------ Host Port Control --------------------
diff --git a/components/esp_hal_usb/usb_dwc_hal.c b/components/esp_hal_usb/usb_dwc_hal.c
index 64ac930483..c2e0b44656 100644
--- a/components/esp_hal_usb/usb_dwc_hal.c
+++ b/components/esp_hal_usb/usb_dwc_hal.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -165,6 +165,8 @@ void usb_dwc_hal_init(usb_dwc_hal_context_t *hal, int port_id)
     hal->constant_config.fifo_size = usb_dwc_ll_ghwcfg_get_fifo_depth(dev);
     hal->constant_config.hsphy_type = usb_dwc_ll_ghwcfg_get_hsphy_type(dev);
     hal->constant_config.chan_num_total = usb_dwc_ll_ghwcfg_get_channel_num(dev);
+    hal->constant_config.max_size_byte_limit = (1U << usb_dwc_ll_ghwcfg_get_xfer_size_width(dev)) - 1;
+    hal->constant_config.max_size_packet_limit = (1U << usb_dwc_ll_ghwcfg_get_packet_size_width(dev)) - 1;
 
     set_defaults(hal);
 }
@@ -260,6 +262,23 @@ void usb_dwc_hal_get_mps_limits(usb_dwc_hal_context_t *hal, usb_hal_fifo_mps_lim
     mps_limits->periodic_out_mps = fifo_config->ptx_fifo_lines * 4;
 }
 
+size_t usb_dwc_hal_get_xfer_size_limit(usb_dwc_hal_context_t *hal, uint16_t mps)
+{
+    HAL_ASSERT(hal);
+    HAL_ASSERT(mps > 0);
+    size_t max_xfer_size;
+
+    // Minimum of the two limits
+    if (mps * hal->constant_config.max_size_packet_limit > hal->constant_config.max_size_byte_limit) {
+        // We hit the overall byte limit
+        max_xfer_size = hal->constant_config.max_size_byte_limit;
+    } else {
+        // We hit the overall packet limit
+        max_xfer_size = mps * hal->constant_config.max_size_packet_limit;
+    }
+    return max_xfer_size;
+}
+
 // ---------------------------------------------------- Host Port ------------------------------------------------------
 
 static inline void debounce_lock_enable(usb_dwc_hal_context_t *hal)
diff --git a/components/soc/esp32h4/include/soc/usb_dwc_cfg.h b/components/soc/esp32h4/include/soc/usb_dwc_cfg.h
deleted file mode 100644
index 5dad643afc..0000000000
--- a/components/soc/esp32h4/include/soc/usb_dwc_cfg.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-Configuration Set ID: 1
-*/
-
-/* 3.1 Basic Config Parameters */
-#define OTG_MODE                0
-#define OTG_ARCHITECTURE        2
-#define OTG_SINGLE_POINT        1
-#define OTG_ENABLE_LPM          0
-#define OTG_EN_DED_TX_FIFO      1
-#define OTG_EN_DESC_DMA         1
-#define OTG_MULTI_PROC_INTRPT   0
-
-/* 3.2 USB Physical Layer Interface Parameters */
-#define OTG_HSPHY_INTERFACE     0
-#define OTG_FSPHY_INTERFACE     1
-#define OTG_ENABLE_IC_USB       0
-#define OTG_I2C_INTERFACE       0
-#define OTG_ADP_SUPPORT         0
-#define OTG_BC_SUPPORT          0
-
-/* 3.3 Device Endpoint Configuration Parameters */
-#define OTG_NUM_EPS         6
-#define OTG_NUM_IN_EPS      5
-#define OTG_NUM_CRL_EPS     0
-
-/* 3.4 Host Endpoint Configuration Parameters */
-#define OTG_NUM_HOST_CHAN   8
-#define OTG_EN_PERIO_HOST   1
-
-/* 3.5 Endpoint Channel FIFO Configuration Parameters */
-#define OTG_DFIFO_DEPTH             256
-#define OTG_DFIFO_DYNAMIC           1
-#define OTG_RX_DFIFO_DEPTH          256
-#define OTG_TX_HNPERIO_DFIFO_DEPTH  256
-#define OTG_TX_NPERIO_DFIFO_DEPTH   256
-#define OTG_TX_HPERIO_DFIFO_DEPTH   256
-#define OTG_NPERIO_TX_QUEUE_DEPTH   4
-#define OTG_PERIO_TX_QUEUE_DEPTH    8
-
-/* 3.6 Additional Configuration Options Parameters */
-#define OTG_TRANS_COUNT_WIDTH       16
-#define OTG_PACKET_COUNT_WIDTH      7
-#define OTG_RM_OPT_FEATURES         1
-#define OTG_EN_PWROPT               1
-#define OTG_SYNC_RESET_TYPE         0
-#define OTG_EN_IDDIG_FILTER         1
-#define OTG_EN_VBUSVALID_FILTER     1
-#define OTG_EN_A_VALID_FILTER       1
-#define OTG_EN_B_VALID_FILTER       1
-#define OTG_EN_SESSIONEND_FILTER    1
-#define OTG_EXCP_CNTL_XFER_FLOW     1
-#define OTG_PWR_CLAMP               0
-#define OTG_PWR_SWITCH_POLARITY     0
-
-/* 3.7 Endpoint Direction Parameters */
-#define OTG_EP_DIR_1    0
-#define OTG_EP_DIR_2    0
-#define OTG_EP_DIR_3    0
-#define OTG_EP_DIR_4    0
-#define OTG_EP_DIR_5    0
-#define OTG_EP_DIR_6    0
-
-/* 3.8 Device Periodic FIFO Depth Parameters */
-
-/* 3.9 Device IN Endpoint FIFO Depth Parameters */
-#define OTG_TX_DINEP_DFIFO_DEPTH_1  256
-#define OTG_TX_DINEP_DFIFO_DEPTH_2  256
-#define OTG_TX_DINEP_DFIFO_DEPTH_3  256
-#define OTG_TX_DINEP_DFIFO_DEPTH_4  256
-
-/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
-#define U2UB_EN     0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h4/include/soc/usb_dwc_struct.h b/components/soc/esp32h4/include/soc/usb_dwc_struct.h
index aa39e9ce29..e58ed023dd 100644
--- a/components/soc/esp32h4/include/soc/usb_dwc_struct.h
+++ b/components/soc/esp32h4/include/soc/usb_dwc_struct.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,7 +13,6 @@ extern "C" {
 #endif
 
 // Registers and fields were generated based on a set of configuration options.
-// See the ESP32-H4 "usb_dwc_cfg.h" for more details.
 
 // ---------------------------- Register Types ------------------------------
 
diff --git a/components/soc/esp32p4/include/soc/usb_dwc_struct.h b/components/soc/esp32p4/include/soc/usb_dwc_struct.h
index 1848978546..7b73e774fe 100644
--- a/components/soc/esp32p4/include/soc/usb_dwc_struct.h
+++ b/components/soc/esp32p4/include/soc/usb_dwc_struct.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,8 +17,6 @@ Registers and fields were generated based on a set of USB-DWC configuration opti
 ESP32-P4 contains 2 instances of USB-DWC with different configurations and versions, the structure below corresponds to the High Speed v4.30a instance.
 The Full Speed instance contains a subset of registers from High Speed instance, the user (HAL) is responsible for accessing only existing fields.
 
-See ESP32-P4 "usb_dwc_cfg.h" for more details.
-
 List of changes v4.00a -> v4.30a
 - GRSTCTL register now contains the CSftRstDone bit which indicates the completion of a soft reset.
 */
diff --git a/components/soc/esp32p4/register/hw_ver1/soc/usb_dwc_cfg.h b/components/soc/esp32p4/register/hw_ver1/soc/usb_dwc_cfg.h
deleted file mode 100644
index ddd2cdc38b..0000000000
--- a/components/soc/esp32p4/register/hw_ver1/soc/usb_dwc_cfg.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-HS Instance:
-Configuration Set ID: 11
-*/
-
-/* 3.1 Basic Config Parameters */
-#define OTG20_MODE                0
-#define OTG20_ARCHITECTURE        2
-#define OTG20_SINGLE_POINT        1
-#define OTG20_ENABLE_LPM          0
-#define OTG20_EN_DED_TX_FIFO      1
-#define OTG20_EN_DESC_DMA         1
-#define OTG20_MULTI_PROC_INTRPT   1
-
-/* 3.2 USB Physical Layer Interface Parameters */
-#define OTG20_HSPHY_INTERFACE         3 // Although we support both UTMI+ and ULPI, the ULPI is not wired out of the USB-DWC. Hence only UTMI+ can be used
-#define OTG20_HSPHY_DWIDTH            2
-#define OTG20_FSPHY_INTERFACE         2
-#define OTG20_ENABLE_IC_USB           0
-#define OTG20_ENABLE_HSIC             0
-#define OTG20_I2C_INTERFACE           0
-#define OTG20_ULPI_CARKIT             1
-#define OTG20_ADP_SUPPORT             1
-#define OTG20_BC_SUPPORT              0
-#define OTG20_VENDOR_CTL_INTERFACE    1
-
-/* 3.3 Device Endpoint Configuration Parameters */
-#define OTG20_NUM_EPS         15
-#define OTG20_NUM_IN_EPS      8
-#define OTG20_NUM_CRL_EPS     1
-
-/* 3.4 Host Endpoint Configuration Parameters */
-#define OTG20_NUM_HOST_CHAN   16
-#define OTG20_EN_PERIO_HOST   1
-
-/* 3.5 Endpoint Channel FIFO Configuration Parameters */
-#define OTG20_DFIFO_DEPTH             1024
-#define OTG20_DFIFO_DYNAMIC           1
-#define OTG20_RX_DFIFO_DEPTH          1024
-#define OTG20_TX_HNPERIO_DFIFO_DEPTH  1024
-#define OTG20_TX_HPERIO_DFIFO_DEPTH   1024
-#define OTG20_NPERIO_TX_QUEUE_DEPTH   4
-#define OTG20_PERIO_TX_QUEUE_DEPTH    4
-
-/* 3.6 Additional Configuration Options Parameters */
-#define OTG20_TRANS_COUNT_WIDTH       17
-#define OTG20_PACKET_COUNT_WIDTH      8
-#define OTG20_RM_OPT_FEATURES         1
-#define OTG20_EN_PWROPT               1
-#define OTG20_SYNC_RESET_TYPE         0
-#define OTG20_EN_IDDIG_FILTER         1
-#define OTG20_EN_VBUSVALID_FILTER     1
-#define OTG20_EN_A_VALID_FILTER       1
-#define OTG20_EN_B_VALID_FILTER       1
-#define OTG20_EN_SESSIONEND_FILTER    1
-#define OTG20_EXCP_CNTL_XFER_FLOW     1
-#define OTG20_PWR_CLAMP               0
-#define OTG20_PWR_SWITCH_POLARITY     0
-
-/* 3.7 Endpoint Direction Parameters */
-#define OTG20_EP_DIR_1    0
-#define OTG20_EP_DIR_2    0
-#define OTG20_EP_DIR_3    0
-#define OTG20_EP_DIR_4    0
-#define OTG20_EP_DIR_5    0
-#define OTG20_EP_DIR_6    0
-#define OTG20_EP_DIR_7    0
-#define OTG20_EP_DIR_8    0
-#define OTG20_EP_DIR_9    0
-#define OTG20_EP_DIR_10   0
-#define OTG20_EP_DIR_11   0
-#define OTG20_EP_DIR_12   0
-#define OTG20_EP_DIR_13   0
-#define OTG20_EP_DIR_14   0
-#define OTG20_EP_DIR_15   0
-
-/* 3.8 Device Periodic FIFO Depth Parameters */
-
-/* 3.9 Device IN Endpoint FIFO Depth Parameters */
-#define OTG20_TX_DINEP_DFIFO_DEPTH_0  512
-#define OTG20_TX_DINEP_DFIFO_DEPTH_1  512
-#define OTG20_TX_DINEP_DFIFO_DEPTH_2  512
-#define OTG20_TX_DINEP_DFIFO_DEPTH_3  512
-#define OTG20_TX_DINEP_DFIFO_DEPTH_4  512
-#define OTG20_TX_DINEP_DFIFO_DEPTH_5  512
-#define OTG20_TX_DINEP_DFIFO_DEPTH_6  512
-#define OTG20_TX_DINEP_DFIFO_DEPTH_7  512
-
-/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
-#define OTG20_U2UB_EN     0
-
-/*
-FS Instance:
-Configuration Set ID: 1
-*/
-
-/* 3.1 Basic Config Parameters */
-#define OTG11_MODE                0
-#define OTG11_ARCHITECTURE        2
-#define OTG11_SINGLE_POINT        1
-#define OTG11_ENABLE_LPM          0
-#define OTG11_EN_DED_TX_FIFO      1
-#define OTG11_EN_DESC_DMA         1
-#define OTG11_MULTI_PROC_INTRPT   0
-
-/* 3.2 USB Physical Layer Interface Parameters */
-#define OTG11_HSPHY_INTERFACE     0
-#define OTG11_FSPHY_INTERFACE     1
-#define OTG11_ENABLE_IC_USB       0
-#define OTG11_I2C_INTERFACE       0
-#define OTG11_ADP_SUPPORT         0
-#define OTG11_BC_SUPPORT          0
-
-/* 3.3 Device Endpoint Configuration Parameters */
-#define OTG11_NUM_EPS         6
-#define OTG11_NUM_IN_EPS      5
-#define OTG11_NUM_CRL_EPS     0
-
-/* 3.4 Host Endpoint Configuration Parameters */
-#define OTG11_NUM_HOST_CHAN   8
-#define OTG11_EN_PERIO_HOST   1
-
-/* 3.5 Endpoint Channel FIFO Configuration Parameters */
-#define OTG11_DFIFO_DEPTH             256
-#define OTG11_DFIFO_DYNAMIC           1
-#define OTG11_RX_DFIFO_DEPTH          256
-#define OTG11_TX_HNPERIO_DFIFO_DEPTH  256
-#define OTG11_TX_NPERIO_DFIFO_DEPTH   256
-#define OTG11_TX_HPERIO_DFIFO_DEPTH   256
-#define OTG11_NPERIO_TX_QUEUE_DEPTH   4
-#define OTG11_PERIO_TX_QUEUE_DEPTH    8
-
-/* 3.6 Additional Configuration Options Parameters */
-#define OTG11_TRANS_COUNT_WIDTH       16
-#define OTG11_PACKET_COUNT_WIDTH      7
-#define OTG11_RM_OPT_FEATURES         1
-#define OTG11_EN_PWROPT               1
-#define OTG11_SYNC_RESET_TYPE         0
-#define OTG11_EN_IDDIG_FILTER         1
-#define OTG11_EN_VBUSVALID_FILTER     1
-#define OTG11_EN_A_VALID_FILTER       1
-#define OTG11_EN_B_VALID_FILTER       1
-#define OTG11_EN_SESSIONEND_FILTER    1
-#define OTG11_EXCP_CNTL_XFER_FLOW     1
-#define OTG11_PWR_CLAMP               0
-#define OTG11_PWR_SWITCH_POLARITY     0
-
-/* 3.7 Endpoint Direction Parameters */
-#define OTG11_EP_DIR_1    0
-#define OTG11_EP_DIR_2    0
-#define OTG11_EP_DIR_3    0
-#define OTG11_EP_DIR_4    0
-#define OTG11_EP_DIR_5    0
-#define OTG11_EP_DIR_6    0
-
-/* 3.8 Device Periodic FIFO Depth Parameters */
-
-/* 3.9 Device IN Endpoint FIFO Depth Parameters */
-#define OTG11_TX_DINEP_DFIFO_DEPTH_1  256
-#define OTG11_TX_DINEP_DFIFO_DEPTH_2  256
-#define OTG11_TX_DINEP_DFIFO_DEPTH_3  256
-#define OTG11_TX_DINEP_DFIFO_DEPTH_4  256
-
-/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
-#define OTG11_U2UB_EN     0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/usb_dwc_cfg.h b/components/soc/esp32p4/register/hw_ver3/soc/usb_dwc_cfg.h
deleted file mode 100644
index 788e538823..0000000000
--- a/components/soc/esp32p4/register/hw_ver3/soc/usb_dwc_cfg.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-HS Instance:
-Configuration Set ID: 11
-*/
-
-/* 3.1 Basic Config Parameters */
-#define OTG20_MODE                0
-#define OTG20_ARCHITECTURE        2
-#define OTG20_SINGLE_POINT        1
-#define OTG20_ENABLE_LPM          0
-#define OTG20_EN_DED_TX_FIFO      1
-#define OTG20_EN_DESC_DMA         1
-#define OTG20_MULTI_PROC_INTRPT   1
-
-/* 3.2 USB Physical Layer Interface Parameters */
-#define OTG20_HSPHY_INTERFACE         3 // Although we support both UTMI+ and ULPI, the ULPI is not wired out of the USB-DWC. Hence only UTMI+ can be used
-#define OTG20_HSPHY_DWIDTH            2
-#define OTG20_FSPHY_INTERFACE         2
-#define OTG20_ENABLE_IC_USB           0
-#define OTG20_ENABLE_HSIC             0
-#define OTG20_I2C_INTERFACE           0
-#define OTG20_ULPI_CARKIT             1
-#define OTG20_ADP_SUPPORT             1
-#define OTG20_BC_SUPPORT              0
-#define OTG20_VENDOR_CTL_INTERFACE    1
-
-/* 3.3 Device Endpoint Configuration Parameters */
-#define OTG20_NUM_EPS         15
-#define OTG20_NUM_IN_EPS      8
-#define OTG20_NUM_CRL_EPS     1
-
-/* 3.4 Host Endpoint Configuration Parameters */
-#define OTG20_NUM_HOST_CHAN   16
-#define OTG20_EN_PERIO_HOST   1
-
-/* 3.5 Endpoint Channel FIFO Configuration Parameters */
-#define OTG20_DFIFO_DEPTH             1024
-#define OTG20_DFIFO_DYNAMIC           1
-#define OTG20_RX_DFIFO_DEPTH          1024
-#define OTG20_TX_HNPERIO_DFIFO_DEPTH  1024
-#define OTG20_TX_HPERIO_DFIFO_DEPTH   1024
-#define OTG20_NPERIO_TX_QUEUE_DEPTH   8
-#define OTG20_PERIO_TX_QUEUE_DEPTH    16
-
-/* 3.6 Additional Configuration Options Parameters */
-#define OTG20_TRANS_COUNT_WIDTH       17
-#define OTG20_PACKET_COUNT_WIDTH      8
-#define OTG20_RM_OPT_FEATURES         1
-#define OTG20_EN_PWROPT               1
-#define OTG20_SYNC_RESET_TYPE         0
-#define OTG20_EN_IDDIG_FILTER         1
-#define OTG20_EN_VBUSVALID_FILTER     1
-#define OTG20_EN_A_VALID_FILTER       1
-#define OTG20_EN_B_VALID_FILTER       1
-#define OTG20_EN_SESSIONEND_FILTER    1
-#define OTG20_EXCP_CNTL_XFER_FLOW     1
-#define OTG20_PWR_CLAMP               0
-#define OTG20_PWR_SWITCH_POLARITY     0
-
-/* 3.7 Endpoint Direction Parameters */
-#define OTG20_EP_DIR_1    0
-#define OTG20_EP_DIR_2    0
-#define OTG20_EP_DIR_3    0
-#define OTG20_EP_DIR_4    0
-#define OTG20_EP_DIR_5    0
-#define OTG20_EP_DIR_6    0
-#define OTG20_EP_DIR_7    0
-#define OTG20_EP_DIR_8    0
-#define OTG20_EP_DIR_9    0
-#define OTG20_EP_DIR_10   0
-#define OTG20_EP_DIR_11   0
-#define OTG20_EP_DIR_12   0
-#define OTG20_EP_DIR_13   0
-#define OTG20_EP_DIR_14   0
-#define OTG20_EP_DIR_15   0
-
-/* 3.8 Device Periodic FIFO Depth Parameters */
-
-/* 3.9 Device IN Endpoint FIFO Depth Parameters */
-#define OTG20_TX_DINEP_DFIFO_DEPTH_0  512
-#define OTG20_TX_DINEP_DFIFO_DEPTH_1  512
-#define OTG20_TX_DINEP_DFIFO_DEPTH_2  512
-#define OTG20_TX_DINEP_DFIFO_DEPTH_3  512
-#define OTG20_TX_DINEP_DFIFO_DEPTH_4  512
-#define OTG20_TX_DINEP_DFIFO_DEPTH_5  512
-#define OTG20_TX_DINEP_DFIFO_DEPTH_6  512
-#define OTG20_TX_DINEP_DFIFO_DEPTH_7  512
-
-/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
-#define OTG20_U2UB_EN     0
-
-/*
-FS Instance:
-Configuration Set ID: 1
-*/
-
-/* 3.1 Basic Config Parameters */
-#define OTG11_MODE                0
-#define OTG11_ARCHITECTURE        2
-#define OTG11_SINGLE_POINT        1
-#define OTG11_ENABLE_LPM          0
-#define OTG11_EN_DED_TX_FIFO      1
-#define OTG11_EN_DESC_DMA         1
-#define OTG11_MULTI_PROC_INTRPT   0
-
-/* 3.2 USB Physical Layer Interface Parameters */
-#define OTG11_HSPHY_INTERFACE     0
-#define OTG11_FSPHY_INTERFACE     1
-#define OTG11_ENABLE_IC_USB       0
-#define OTG11_I2C_INTERFACE       0
-#define OTG11_ADP_SUPPORT         0
-#define OTG11_BC_SUPPORT          0
-
-/* 3.3 Device Endpoint Configuration Parameters */
-#define OTG11_NUM_EPS         6
-#define OTG11_NUM_IN_EPS      5
-#define OTG11_NUM_CRL_EPS     0
-
-/* 3.4 Host Endpoint Configuration Parameters */
-#define OTG11_NUM_HOST_CHAN   8
-#define OTG11_EN_PERIO_HOST   1
-
-/* 3.5 Endpoint Channel FIFO Configuration Parameters */
-#define OTG11_DFIFO_DEPTH             256
-#define OTG11_DFIFO_DYNAMIC           1
-#define OTG11_RX_DFIFO_DEPTH          256
-#define OTG11_TX_HNPERIO_DFIFO_DEPTH  256
-#define OTG11_TX_NPERIO_DFIFO_DEPTH   256
-#define OTG11_TX_HPERIO_DFIFO_DEPTH   256
-#define OTG11_NPERIO_TX_QUEUE_DEPTH   4
-#define OTG11_PERIO_TX_QUEUE_DEPTH    8
-
-/* 3.6 Additional Configuration Options Parameters */
-#define OTG11_TRANS_COUNT_WIDTH       16
-#define OTG11_PACKET_COUNT_WIDTH      7
-#define OTG11_RM_OPT_FEATURES         1
-#define OTG11_EN_PWROPT               1
-#define OTG11_SYNC_RESET_TYPE         0
-#define OTG11_EN_IDDIG_FILTER         1
-#define OTG11_EN_VBUSVALID_FILTER     1
-#define OTG11_EN_A_VALID_FILTER       1
-#define OTG11_EN_B_VALID_FILTER       1
-#define OTG11_EN_SESSIONEND_FILTER    1
-#define OTG11_EXCP_CNTL_XFER_FLOW     1
-#define OTG11_PWR_CLAMP               0
-#define OTG11_PWR_SWITCH_POLARITY     0
-
-/* 3.7 Endpoint Direction Parameters */
-#define OTG11_EP_DIR_1    0
-#define OTG11_EP_DIR_2    0
-#define OTG11_EP_DIR_3    0
-#define OTG11_EP_DIR_4    0
-#define OTG11_EP_DIR_5    0
-#define OTG11_EP_DIR_6    0
-
-/* 3.8 Device Periodic FIFO Depth Parameters */
-
-/* 3.9 Device IN Endpoint FIFO Depth Parameters */
-#define OTG11_TX_DINEP_DFIFO_DEPTH_1  256
-#define OTG11_TX_DINEP_DFIFO_DEPTH_2  256
-#define OTG11_TX_DINEP_DFIFO_DEPTH_3  256
-#define OTG11_TX_DINEP_DFIFO_DEPTH_4  256
-
-/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
-#define OTG11_U2UB_EN     0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s2/include/soc/usb_dwc_cfg.h b/components/soc/esp32s2/include/soc/usb_dwc_cfg.h
deleted file mode 100644
index 37cdcdf4bf..0000000000
--- a/components/soc/esp32s2/include/soc/usb_dwc_cfg.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-Configuration Set ID: 1
-*/
-
-/* 3.1 Basic Config Parameters */
-#define OTG_MODE                0
-#define OTG_ARCHITECTURE        2
-#define OTG_SINGLE_POINT        1
-#define OTG_ENABLE_LPM          0
-#define OTG_EN_DED_TX_FIFO      1
-#define OTG_EN_DESC_DMA         1
-#define OTG_MULTI_PROC_INTRPT   0
-
-/* 3.2 USB Physical Layer Interface Parameters */
-#define OTG_HSPHY_INTERFACE     0
-#define OTG_FSPHY_INTERFACE     1
-#define OTG_ENABLE_IC_USB       0
-#define OTG_I2C_INTERFACE       0
-#define OTG_ADP_SUPPORT         0
-#define OTG_BC_SUPPORT          0
-
-/* 3.3 Device Endpoint Configuration Parameters */
-#define OTG_NUM_EPS         6
-#define OTG_NUM_IN_EPS      5
-#define OTG_NUM_CRL_EPS     0
-
-/* 3.4 Host Endpoint Configuration Parameters */
-#define OTG_NUM_HOST_CHAN   8
-#define OTG_EN_PERIO_HOST   1
-
-/* 3.5 Endpoint Channel FIFO Configuration Parameters */
-#define OTG_DFIFO_DEPTH             256
-#define OTG_DFIFO_DYNAMIC           1
-#define OTG_RX_DFIFO_DEPTH          256
-#define OTG_TX_HNPERIO_DFIFO_DEPTH  256
-#define OTG_TX_NPERIO_DFIFO_DEPTH   256
-#define OTG_TX_HPERIO_DFIFO_DEPTH   256
-#define OTG_NPERIO_TX_QUEUE_DEPTH   4
-#define OTG_PERIO_TX_QUEUE_DEPTH    8
-
-/* 3.6 Additional Configuration Options Parameters */
-#define OTG_TRANS_COUNT_WIDTH       16
-#define OTG_PACKET_COUNT_WIDTH      7
-#define OTG_RM_OPT_FEATURES         1
-#define OTG_EN_PWROPT               1
-#define OTG_SYNC_RESET_TYPE         0
-#define OTG_EN_IDDIG_FILTER         1
-#define OTG_EN_VBUSVALID_FILTER     1
-#define OTG_EN_A_VALID_FILTER       1
-#define OTG_EN_B_VALID_FILTER       1
-#define OTG_EN_SESSIONEND_FILTER    1
-#define OTG_EXCP_CNTL_XFER_FLOW     1
-#define OTG_PWR_CLAMP               0
-#define OTG_PWR_SWITCH_POLARITY     0
-
-/* 3.7 Endpoint Direction Parameters */
-#define OTG_EP_DIR_1    0
-#define OTG_EP_DIR_2    0
-#define OTG_EP_DIR_3    0
-#define OTG_EP_DIR_4    0
-#define OTG_EP_DIR_5    0
-#define OTG_EP_DIR_6    0
-
-/* 3.8 Device Periodic FIFO Depth Parameters */
-
-/* 3.9 Device IN Endpoint FIFO Depth Parameters */
-#define OTG_TX_DINEP_DFIFO_DEPTH_1  256
-#define OTG_TX_DINEP_DFIFO_DEPTH_2  256
-#define OTG_TX_DINEP_DFIFO_DEPTH_3  256
-#define OTG_TX_DINEP_DFIFO_DEPTH_4  256
-
-/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
-#define U2UB_EN     0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s2/include/soc/usb_dwc_struct.h b/components/soc/esp32s2/include/soc/usb_dwc_struct.h
index 340ce02bc4..18cbc68b07 100644
--- a/components/soc/esp32s2/include/soc/usb_dwc_struct.h
+++ b/components/soc/esp32s2/include/soc/usb_dwc_struct.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,7 +14,6 @@ extern "C" {
 
 /*
 Registers and fields were generated based on a set of configuration options.
-See the ESP32-S2 "usb_dwc_cfg.h" for more details.
 */
 
 /* ---------------------------- Register Types ------------------------------ */
diff --git a/components/soc/esp32s3/include/soc/usb_dwc_cfg.h b/components/soc/esp32s3/include/soc/usb_dwc_cfg.h
deleted file mode 100644
index 37cdcdf4bf..0000000000
--- a/components/soc/esp32s3/include/soc/usb_dwc_cfg.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-Configuration Set ID: 1
-*/
-
-/* 3.1 Basic Config Parameters */
-#define OTG_MODE                0
-#define OTG_ARCHITECTURE        2
-#define OTG_SINGLE_POINT        1
-#define OTG_ENABLE_LPM          0
-#define OTG_EN_DED_TX_FIFO      1
-#define OTG_EN_DESC_DMA         1
-#define OTG_MULTI_PROC_INTRPT   0
-
-/* 3.2 USB Physical Layer Interface Parameters */
-#define OTG_HSPHY_INTERFACE     0
-#define OTG_FSPHY_INTERFACE     1
-#define OTG_ENABLE_IC_USB       0
-#define OTG_I2C_INTERFACE       0
-#define OTG_ADP_SUPPORT         0
-#define OTG_BC_SUPPORT          0
-
-/* 3.3 Device Endpoint Configuration Parameters */
-#define OTG_NUM_EPS         6
-#define OTG_NUM_IN_EPS      5
-#define OTG_NUM_CRL_EPS     0
-
-/* 3.4 Host Endpoint Configuration Parameters */
-#define OTG_NUM_HOST_CHAN   8
-#define OTG_EN_PERIO_HOST   1
-
-/* 3.5 Endpoint Channel FIFO Configuration Parameters */
-#define OTG_DFIFO_DEPTH             256
-#define OTG_DFIFO_DYNAMIC           1
-#define OTG_RX_DFIFO_DEPTH          256
-#define OTG_TX_HNPERIO_DFIFO_DEPTH  256
-#define OTG_TX_NPERIO_DFIFO_DEPTH   256
-#define OTG_TX_HPERIO_DFIFO_DEPTH   256
-#define OTG_NPERIO_TX_QUEUE_DEPTH   4
-#define OTG_PERIO_TX_QUEUE_DEPTH    8
-
-/* 3.6 Additional Configuration Options Parameters */
-#define OTG_TRANS_COUNT_WIDTH       16
-#define OTG_PACKET_COUNT_WIDTH      7
-#define OTG_RM_OPT_FEATURES         1
-#define OTG_EN_PWROPT               1
-#define OTG_SYNC_RESET_TYPE         0
-#define OTG_EN_IDDIG_FILTER         1
-#define OTG_EN_VBUSVALID_FILTER     1
-#define OTG_EN_A_VALID_FILTER       1
-#define OTG_EN_B_VALID_FILTER       1
-#define OTG_EN_SESSIONEND_FILTER    1
-#define OTG_EXCP_CNTL_XFER_FLOW     1
-#define OTG_PWR_CLAMP               0
-#define OTG_PWR_SWITCH_POLARITY     0
-
-/* 3.7 Endpoint Direction Parameters */
-#define OTG_EP_DIR_1    0
-#define OTG_EP_DIR_2    0
-#define OTG_EP_DIR_3    0
-#define OTG_EP_DIR_4    0
-#define OTG_EP_DIR_5    0
-#define OTG_EP_DIR_6    0
-
-/* 3.8 Device Periodic FIFO Depth Parameters */
-
-/* 3.9 Device IN Endpoint FIFO Depth Parameters */
-#define OTG_TX_DINEP_DFIFO_DEPTH_1  256
-#define OTG_TX_DINEP_DFIFO_DEPTH_2  256
-#define OTG_TX_DINEP_DFIFO_DEPTH_3  256
-#define OTG_TX_DINEP_DFIFO_DEPTH_4  256
-
-/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
-#define U2UB_EN     0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/usb_dwc_struct.h b/components/soc/esp32s3/include/soc/usb_dwc_struct.h
index 1d84a6b85b..18cbc68b07 100644
--- a/components/soc/esp32s3/include/soc/usb_dwc_struct.h
+++ b/components/soc/esp32s3/include/soc/usb_dwc_struct.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,7 +14,6 @@ extern "C" {
 
 /*
 Registers and fields were generated based on a set of configuration options.
-See the ESP32-S3 "usb_dwc_cfg.h" for more details.
 */
 
 /* ---------------------------- Register Types ------------------------------ */