From fbcb51653aa7fc1ac0bace9fc5a24b9f461b43bf Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Mon, 27 Oct 2025 19:10:48 +0530 Subject: [PATCH] fix(hal): Fix MMU PSRAM anti-fi MMU target check In case of ESP32-C5 and ESP32-C61, mmu_ids for PSRAM and Flash MMU are the same due to their shared memory space. Thus, instead of mmu_id we should use mmu_target_t. --- components/hal/esp32c5/include/hal/mmu_ll.h | 2 +- components/hal/esp32c61/include/hal/mmu_ll.h | 2 +- components/hal/esp32p4/include/hal/mmu_ll.h | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/components/hal/esp32c5/include/hal/mmu_ll.h b/components/hal/esp32c5/include/hal/mmu_ll.h index 5dcc6e5fd1..79df1a7067 100644 --- a/components/hal/esp32c5/include/hal/mmu_ll.h +++ b/components/hal/esp32c5/include/hal/mmu_ll.h @@ -233,7 +233,7 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100) { ESP_FAULT_ASSERT(REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_SENSITIVE); } else { - ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID && efuse_hal_chip_revision() > 100)); + ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100)); } } diff --git a/components/hal/esp32c61/include/hal/mmu_ll.h b/components/hal/esp32c61/include/hal/mmu_ll.h index 1e9da4aba8..b0dc2d03b7 100644 --- a/components/hal/esp32c61/include/hal/mmu_ll.h +++ b/components/hal/esp32c61/include/hal/mmu_ll.h @@ -235,7 +235,7 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100) { ESP_FAULT_ASSERT(REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_SENSITIVE); } else { - ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID && efuse_hal_chip_revision() > 100)); + ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100)); } } diff --git a/components/hal/esp32p4/include/hal/mmu_ll.h b/components/hal/esp32p4/include/hal/mmu_ll.h index 7120c30964..e86d1a18fb 100644 --- a/components/hal/esp32p4/include/hal/mmu_ll.h +++ b/components/hal/esp32p4/include/hal/mmu_ll.h @@ -294,10 +294,10 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm // Anti-FI check to confirm the encryption status for PSRAM entry. // This avoids a potential FI attacks to keep PSRAM unencrypted and // hence read out plaintext in execute from PSRAM model. - if (mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID) { + if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0) { ESP_FAULT_ASSERT(REG_READ(content_reg) & SOC_MMU_PSRAM_SENSITIVE); } else { - ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID)); + ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0)); } }