diff --git a/components/esp_hal_wdt/CMakeLists.txt b/components/esp_hal_wdt/CMakeLists.txt
index 4df47401ca..afe16f32cc 100644
--- a/components/esp_hal_wdt/CMakeLists.txt
+++ b/components/esp_hal_wdt/CMakeLists.txt
@@ -29,9 +29,5 @@ idf_component_register(SRCS ${srcs}
 
 # Link the ROM WDT HAL implementation linker script if selected
 if(CONFIG_HAL_WDT_USE_ROM_IMPL)
-    if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
-        target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/rom.beta5.wdt.ld")
-    else()
-        target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/rom.wdt.ld")
-    endif()
+    target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/rom.wdt.ld")
 endif()
diff --git a/components/esp_hal_wdt/esp32h4/rom.beta5.wdt.ld b/components/esp_hal_wdt/esp32h4/rom.beta5.wdt.ld
deleted file mode 100644
index a8bd93077c..0000000000
--- a/components/esp_hal_wdt/esp32h4/rom.beta5.wdt.ld
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/***************************************
- Group hal_wdt
- ***************************************/
-
-/* Functions */
-wdt_hal_init = 0x40000370;
-wdt_hal_deinit = 0x40000374;
-wdt_hal_config_stage = 0x40000378;
-wdt_hal_write_protect_disable = 0x4000037c;
-wdt_hal_write_protect_enable = 0x40000380;
-wdt_hal_enable = 0x40000384;
-wdt_hal_disable = 0x40000388;
-wdt_hal_handle_intr = 0x4000038c;
-wdt_hal_feed = 0x40000390;
-wdt_hal_set_flashboot_en = 0x40000394;
-wdt_hal_is_enabled = 0x40000398;
diff --git a/components/esp_hw_support/port/esp32h4/Kconfig.hw_support b/components/esp_hw_support/port/esp32h4/Kconfig.hw_support
index 22a251a477..674b8004aa 100644
--- a/components/esp_hw_support/port/esp32h4/Kconfig.hw_support
+++ b/components/esp_hw_support/port/esp32h4/Kconfig.hw_support
@@ -1,14 +1,6 @@
 comment "NOTE! Support of ESP32-H4 MP is mutually exclusive"
 comment "Read the help text of the option below for explanation"
 
-config ESP32H4_SELECTS_REV_MP
-    bool "Select ESP32-H4 MP version"
-    default y
-    help
-        Enable this option to select ESP32-H4 MP revision.
-        MP revisions have some hardware differences with Beta revision.
-        MP revisions is not compatible with Beta revision.
-
 choice ESP32H4_REV_MIN
     prompt "Minimum Supported ESP32-H4 Revision"
     default ESP32H4_REV_MIN_0
diff --git a/components/esp_hw_support/port/esp32h4/pmu_init.c b/components/esp_hw_support/port/esp32h4/pmu_init.c
index 1a1db472e2..1c28630666 100644
--- a/components/esp_hw_support/port/esp32h4/pmu_init.c
+++ b/components/esp_hw_support/port/esp32h4/pmu_init.c
@@ -122,7 +122,6 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, const pmu_hp_sys
     /* set dcdc ccm mode software enable */
     pmu_ll_set_dcdc_ccm_sw_en(ctx->hal->dev, true);
 
-#if CONFIG_ESP32H4_SELECTS_REV_MP
     /* set ble bandgap ocode */
     uint32_t ulp_ocode = 0;
 #if !CONFIG_IDF_ENV_FPGA
@@ -135,7 +134,6 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, const pmu_hp_sys
 #endif
     REG_SET_FIELD(PMU_BLE_BANDGAP_CTRL_REG, PMU_EXT_OCODE, ulp_ocode);
     SET_PERI_REG_MASK(PMU_BLE_BANDGAP_CTRL_REG, PMU_EXT_FORCE_OCODE);
-#endif
 }
 
 void pmu_lp_system_init(pmu_context_t *ctx, pmu_lp_mode_t mode, const pmu_lp_system_param_t *param)
diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt
index c99e007707..b71433043c 100644
--- a/components/esp_rom/CMakeLists.txt
+++ b/components/esp_rom/CMakeLists.txt
@@ -99,8 +99,6 @@ if(target STREQUAL "linux")
 else()
     if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
         target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.eco5.ld")
-    elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
-        target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.beta5.ld")
     else()
         target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.ld")
     endif()
@@ -114,8 +112,6 @@ else()
     if(CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB)
         if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
             rom_linker_script("eco5.libgcc")
-        elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
-            rom_linker_script("beta5.libgcc")
         else()
             rom_linker_script("libgcc")
         endif()
@@ -131,11 +127,7 @@ endif()
 # Common API which is linked both for bootloader and app builds
 
 if(CONFIG_HAL_SYSTIMER_USE_ROM_IMPL)
-    if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
-        rom_linker_script("beta5.systimer")
-    else()
-        rom_linker_script("systimer")
-    endif()
+    rom_linker_script("systimer")
 endif()
 
 if(CONFIG_ESP_ROM_HAS_VERSION)
@@ -169,8 +161,6 @@ if(BOOTLOADER_BUILD)
         else()
             if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
                 rom_linker_script("eco5.libc")
-            elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
-                rom_linker_script("beta5.libc")
             else()
                 rom_linker_script("libc")
             endif()
@@ -181,8 +171,6 @@ if(BOOTLOADER_BUILD)
             if(CONFIG_LIBC_NEWLIB)
                 if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
                     rom_linker_script("eco5.newlib")
-                elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
-                    rom_linker_script("beta5.newlib")
                 else()
                     rom_linker_script("newlib")
                 endif()
@@ -340,8 +328,6 @@ else() # Regular app build
         # ESP32 and S2 are a bit different, keep them as special cases in the target specific include section
         if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
             rom_linker_script("eco5.libc")
-        elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
-            rom_linker_script("beta5.libc")
         else()
             rom_linker_script("libc")
         endif()
@@ -351,8 +337,6 @@ else() # Regular app build
         if(CONFIG_LIBC_NEWLIB)
             if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
                 rom_linker_script("eco5.newlib")
-            elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
-                rom_linker_script("beta5.newlib")
             else()
                 rom_linker_script("newlib")
             endif()
@@ -362,11 +346,7 @@ else() # Regular app build
             if(NOT CONFIG_ESP_ROM_HAS_NEWLIB_32BIT_TIME AND NOT CONFIG_ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG)
                 # Newlib-nano functions contains time_t related functions
                 # and cannot be used if they were compiled with 32 bit time_t
-                if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
-                    rom_linker_script("beta5.newlib-nano")
-                else()
-                    rom_linker_script("newlib-nano")
-                endif()
+                rom_linker_script("newlib-nano")
             endif()
         endif()
 
@@ -388,21 +368,13 @@ else() # Regular app build
             target_link_libraries(${COMPONENT_LIB} PRIVATE "-u esp_rom_include_multi_heap_patch")
         endif()
 
-        if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
-            rom_linker_script("beta5.heap")
-        else()
-            rom_linker_script("heap")
-        endif()
+        rom_linker_script("heap")
     endif()
 
     if(CONFIG_SPI_FLASH_ROM_IMPL)
         # Older targets do not have a separate ld file for spiflash
         if(NOT target STREQUAL "esp32c3" AND NOT target STREQUAL "esp32s3" AND NOT target STREQUAL "esp32c2")
-            if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
-                rom_linker_script("beta5.spiflash")
-            else()
-                rom_linker_script("spiflash")
-            endif()
+            rom_linker_script("spiflash")
         endif()
     endif()
 
diff --git a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.heap.ld b/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.heap.ld
deleted file mode 100644
index 48460a5ad3..0000000000
--- a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.heap.ld
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* ROM function interface esp32h4.rom.heap.ld for esp32h4
- *
- *
- * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
- *
- * Compatible with ROM where ECO version equal or greater to 0.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
- */
-
-/***************************************
- Group heap
- ***************************************/
-
-/* Functions */
-tlsf_create = 0x400003d8;
-tlsf_create_with_pool = 0x400003dc;
-tlsf_get_pool = 0x400003e0;
-tlsf_add_pool = 0x400003e4;
-tlsf_remove_pool = 0x400003e8;
-tlsf_malloc = 0x400003ec;
-tlsf_memalign = 0x400003f0;
-tlsf_memalign_offs = 0x400003f4;
-tlsf_malloc_addr = 0x400003f8;
-tlsf_realloc = 0x400003fc;
-tlsf_free = 0x40000400;
-tlsf_block_size = 0x40000404;
-tlsf_size = 0x40000408;
-tlsf_pool_overhead = 0x4000040c;
-tlsf_alloc_overhead = 0x40000410;
-tlsf_walk_pool = 0x40000414;
-tlsf_check = 0x40000418;
-tlsf_check_pool = 0x4000041c;
-tlsf_poison_fill_pfunc_set = 0x40000420;
-tlsf_poison_check_pfunc_set = 0x40000424;
-multi_heap_get_block_address_impl = 0x40000428;
-multi_heap_get_allocated_size_impl = 0x4000042c;
-multi_heap_register_impl = 0x40000430;
-multi_heap_set_lock = 0x40000434;
-multi_heap_os_funcs_init = 0x40000438;
-multi_heap_internal_lock = 0x4000043c;
-multi_heap_internal_unlock = 0x40000440;
-multi_heap_get_first_block = 0x40000444;
-multi_heap_get_next_block = 0x40000448;
-multi_heap_is_free = 0x4000044c;
-multi_heap_malloc_impl = 0x40000450;
-multi_heap_free_impl = 0x40000454;
-multi_heap_realloc_impl = 0x40000458;
-multi_heap_aligned_alloc_impl_offs = 0x4000045c;
-multi_heap_aligned_alloc_impl = 0x40000460;
-multi_heap_check = 0x40000464;
-multi_heap_dump = 0x40000468;
-multi_heap_free_size_impl = 0x4000046c;
-multi_heap_minimum_free_size_impl = 0x40000470;
-multi_heap_get_info_impl = 0x40000474;
-/* Data (.data, .bss, .rodata) */
-heap_tlsf_table_ptr = 0x4085ffd4;
-
-PROVIDE (multi_heap_malloc = multi_heap_malloc_impl);
-PROVIDE (multi_heap_free = multi_heap_free_impl);
-PROVIDE (multi_heap_realloc = multi_heap_realloc_impl);
-PROVIDE (multi_heap_get_allocated_size = multi_heap_get_allocated_size_impl);
-PROVIDE (multi_heap_register = multi_heap_register_impl);
-PROVIDE (multi_heap_get_info = multi_heap_get_info_impl);
-PROVIDE (multi_heap_free_size = multi_heap_free_size_impl);
-PROVIDE (multi_heap_minimum_free_size = multi_heap_minimum_free_size_impl);
-PROVIDE (multi_heap_get_block_address = multi_heap_get_block_address_impl);
-PROVIDE (multi_heap_aligned_alloc = multi_heap_aligned_alloc_impl);
-PROVIDE (multi_heap_aligned_free = multi_heap_aligned_free_impl);
-PROVIDE (multi_heap_check = multi_heap_check);
-PROVIDE (multi_heap_set_lock = multi_heap_set_lock);
-PROVIDE (multi_heap_os_funcs_init = multi_heap_mutex_init);
-PROVIDE (multi_heap_internal_lock = multi_heap_internal_lock);
-PROVIDE (multi_heap_internal_unlock = multi_heap_internal_unlock);
diff --git a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.ld b/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.ld
deleted file mode 100644
index 1938fae87b..0000000000
--- a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.ld
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* ROM function interface esp32h4.rom.ld for esp32h4
- *
- *
- * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
- *
- * Compatible with ROM where ECO version equal or greater to 0.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
- */
-
-/***************************************
- Group common
- ***************************************/
-
-/* Functions */
-rtc_get_reset_reason = 0x40000018;
-rtc_get_wakeup_cause = 0x4000001c;
-pmu_enable_unhold_pads = 0x40000020;
-ets_printf = 0x40000024;
-ets_install_putc1 = 0x40000028;
-ets_install_putc2 = 0x4000002c;
-ets_install_uart_printf = 0x40000030;
-ets_install_usb_printf = 0x40000034;
-ets_get_printf_channel = 0x40000038;
-ets_delay_us = 0x4000003c;
-ets_get_cpu_frequency = 0x40000040;
-ets_update_cpu_frequency = 0x40000044;
-ets_install_lock = 0x40000048;
-UartRxString = 0x4000004c;
-UartGetCmdLn = 0x40000050;
-uart_tx_one_char = 0x40000054;
-uart_tx_one_char2 = 0x40000058;
-uart_tx_one_char3 = 0x4000005c;
-uart_rx_one_char = 0x40000060;
-uart_rx_one_char_block = 0x40000064;
-uart_rx_intr_handler = 0x40000068;
-uart_rx_readbuff = 0x4000006c;
-uartAttach = 0x40000070;
-uart_tx_flush = 0x40000074;
-uart_tx_wait_idle = 0x40000078;
-uart_div_modify = 0x4000007c;
-ets_write_char_uart = 0x40000080;
-uart_tx_switch = 0x40000084;
-uart_buff_switch = 0x40000088;
-roundup2 = 0x4000008c;
-multofup = 0x40000090;
-software_reset = 0x40000094;
-software_reset_cpu = 0x40000098;
-ets_clk_assist_debug_clock_enable = 0x4000009c;
-clear_super_wdt_reset_flag = 0x400000a0;
-disable_default_watchdog = 0x400000a4;
-ets_set_appcpu_boot_addr = 0x400000a8;
-send_packet = 0x400000ac;
-recv_packet = 0x400000b0;
-GetUartDevice = 0x400000b4;
-UartDwnLdProc = 0x400000b8;
-GetSecurityInfoProc = 0x400000bc;
-Uart_Init = 0x400000c0;
-ets_set_user_start = 0x400000c4;
-/* Data (.data, .bss, .rodata) */
-ets_rom_layout_p = 0x4001fffc;
-ets_ops_table_ptr = 0x4085fff4;
-g_saved_pc = 0x4085fff8;
-
-
-/***************************************
- Group miniz
- ***************************************/
-
-/* Functions */
-mz_adler32 = 0x400000c8;
-mz_free = 0x400000cc;
-tdefl_compress = 0x400000d0;
-tdefl_compress_buffer = 0x400000d4;
-tdefl_compress_mem_to_heap = 0x400000d8;
-tdefl_compress_mem_to_mem = 0x400000dc;
-tdefl_compress_mem_to_output = 0x400000e0;
-tdefl_get_adler32 = 0x400000e4;
-tdefl_get_prev_return_status = 0x400000e8;
-tdefl_init = 0x400000ec;
-tdefl_write_image_to_png_file_in_memory = 0x400000f0;
-tdefl_write_image_to_png_file_in_memory_ex = 0x400000f4;
-tinfl_decompress = 0x400000f8;
-tinfl_decompress_mem_to_callback = 0x400000fc;
-tinfl_decompress_mem_to_heap = 0x40000100;
-tinfl_decompress_mem_to_mem = 0x40000104;
-
-
-/***************************************
- Group spi_extmem_common
- ***************************************/
-
-/* Functions */
-esp_rom_spi_cmd_config = 0x40000108;
-esp_rom_spi_cmd_start = 0x4000010c;
-esp_rom_spi_set_op_mode = 0x40000110;
-
-
-/***************************************
- Group spiflash_legacy
- ***************************************/
-
-/* Functions */
-esp_rom_spiflash_wait_idle = 0x40000114;
-esp_rom_spiflash_write_encrypted = 0x40000118;
-esp_rom_spiflash_write_encrypted_dest = 0x4000011c;
-esp_rom_spiflash_write_encrypted_enable = 0x40000120;
-esp_rom_spiflash_write_encrypted_disable = 0x40000124;
-esp_rom_spiflash_erase_chip = 0x40000128;
-_esp_rom_spiflash_erase_sector = 0x4000012c;
-_esp_rom_spiflash_erase_block = 0x40000130;
-_esp_rom_spiflash_write = 0x40000134;
-_esp_rom_spiflash_read = 0x40000138;
-_esp_rom_spiflash_unlock = 0x4000013c;
-_SPIEraseArea = 0x40000140;
-_SPI_write_enable = 0x40000144;
-esp_rom_spiflash_erase_sector = 0x40000148;
-esp_rom_spiflash_erase_block = 0x4000014c;
-esp_rom_spiflash_write = 0x40000150;
-esp_rom_spiflash_read = 0x40000154;
-esp_rom_spiflash_unlock = 0x40000158;
-SPIEraseArea = 0x4000015c;
-SPI_write_enable = 0x40000160;
-esp_rom_spiflash_config_param = 0x40000164;
-esp_rom_spiflash_read_user_cmd = 0x40000168;
-esp_rom_spiflash_select_qio_pins = 0x4000016c;
-esp_rom_spi_flash_auto_sus_res = 0x40000170;
-esp_rom_spi_flash_send_resume = 0x40000174;
-esp_rom_spi_flash_update_id = 0x40000178;
-esp_rom_spiflash_config_clk = 0x4000017c;
-esp_rom_spiflash_config_readmode = 0x40000180;
-esp_rom_spiflash_read_status = 0x40000184;
-esp_rom_spiflash_read_statushigh = 0x40000188;
-esp_rom_spiflash_write_status = 0x4000018c;
-esp_rom_spiflash_write_disable = 0x40000190;
-spi_cache_mode_switch = 0x40000194;
-spi_common_set_dummy_output = 0x40000198;
-spi_common_set_flash_cs_timing = 0x4000019c;
-esp_rom_spi_set_address_bit_len = 0x400001a0;
-SPILock = 0x400001a4;
-SPIMasterReadModeCnfig = 0x400001a8;
-SPI_Common_Command = 0x400001ac;
-SPI_WakeUp = 0x400001b0;
-SPI_block_erase = 0x400001b4;
-SPI_chip_erase = 0x400001b8;
-SPI_init = 0x400001bc;
-SPI_page_program = 0x400001c0;
-SPI_read_data = 0x400001c4;
-SPI_sector_erase = 0x400001c8;
-SelectSpiFunction = 0x400001cc;
-SetSpiDrvs = 0x400001d0;
-Wait_SPI_Idle = 0x400001d4;
-spi_dummy_len_fix = 0x400001d8;
-Disable_QMode = 0x400001dc;
-Enable_QMode = 0x400001e0;
-spi_flash_attach = 0x400001e4;
-spi_flash_get_chip_size = 0x400001e8;
-spi_flash_guard_set = 0x400001ec;
-spi_flash_guard_get = 0x400001f0;
-spi_flash_read_encrypted = 0x400001f4;
-/* Data (.data, .bss, .rodata) */
-rom_spiflash_legacy_funcs = 0x4085ffec;
-rom_spiflash_legacy_data = 0x4085ffe8;
-g_flash_guard_ops = 0x4085fff0;
-
-
-/***************************************
- Group cache
- ***************************************/
-
-/* Functions */
-Cache_Get_Line_Size = 0x400005d8;
-Cache_Get_Mode = 0x400005dc;
-Cache_Address_Through_Cache = 0x400005e0;
-ROM_Boot_Cache_Init = 0x400005e4;
-Cache_Sync_Items = 0x400005e8;
-Cache_Op_Addr = 0x400005ec;
-Cache_Invalidate_Addr = 0x400005f0;
-Cache_Clean_Addr = 0x400005f4;
-Cache_WriteBack_Addr = 0x400005f8;
-Cache_WriteBack_Invalidate_Addr = 0x400005fc;
-Cache_Invalidate_All = 0x40000600;
-Cache_Clean_All = 0x40000604;
-Cache_WriteBack_All = 0x40000608;
-Cache_WriteBack_Invalidate_All = 0x4000060c;
-Cache_Mask_All = 0x40000610;
-Cache_UnMask_Dram0 = 0x40000614;
-Cache_Suspend_Autoload = 0x40000618;
-Cache_Resume_Autoload = 0x4000061c;
-Cache_Start_Preload = 0x40000620;
-Cache_Preload_Done = 0x40000624;
-Cache_End_Preload = 0x40000628;
-Cache_Config_Autoload = 0x4000062c;
-Cache_Enable_Autoload = 0x40000630;
-Cache_Disable_Autoload = 0x40000634;
-Cache_Enable_PreLock = 0x40000638;
-Cache_Disable_PreLock = 0x4000063c;
-Cache_Lock_Items = 0x40000640;
-Cache_Lock_Addr = 0x40000644;
-Cache_Unlock_Addr = 0x40000648;
-Cache_Disable_Cache = 0x4000064c;
-Cache_Enable_Cache = 0x40000650;
-Cache_Suspend_Cache = 0x40000654;
-Cache_Resume_Cache = 0x40000658;
-Cache_Freeze_Enable = 0x4000065c;
-Cache_Freeze_Disable = 0x40000660;
-Cache_Set_IDROM_MMU_Size = 0x40000664;
-Cache_Get_IROM_MMU_End = 0x40000668;
-Cache_Get_DROM_MMU_End = 0x4000066c;
-Cache_MMU_Init = 0x40000670;
-Cache_MSPI_MMU_Set = 0x40000674;
-Cache_MSPI_MMU_Set_Secure = 0x40000678;
-Cache_Count_Flash_Pages = 0x4000067c;
-Cache_Travel_Tag_Memory = 0x40000680;
-Cache_Get_Virtual_Addr = 0x40000684;
-flash2spiram_instruction_offset = 0x40000688;
-flash2spiram_rodata_offset = 0x4000068c;
-flash_instr_rodata_start_page = 0x40000690;
-flash_instr_rodata_end_page = 0x40000694;
-Cache_Set_IDROM_MMU_Info = 0x40000698;
-Cache_Flash_To_SPIRAM_Copy = 0x4000069c;
-/* Data (.data, .bss, .rodata) */
-rom_cache_op_cb = 0x4085ffc8;
-rom_cache_internal_table_ptr = 0x4085ffc4;
-
-
-/***************************************
- Group clock
- ***************************************/
-
-/* Functions */
-ets_clk_get_xtal_freq = 0x400006a0;
-ets_clk_get_cpu_freq = 0x400006a4;
-
-
-/***************************************
- Group gpio
- ***************************************/
-
-/* Functions */
-rom_gpio_set_output_level = 0x400006a8;
-rom_gpio_get_input_level = 0x400006ac;
-rom_gpio_matrix_in = 0x400006b0;
-rom_gpio_matrix_out = 0x400006b4;
-rom_gpio_bypass_matrix_in = 0x400006b8;
-rom_gpio_output_disable = 0x400006bc;
-rom_gpio_output_enable = 0x400006c0;
-rom_gpio_pad_input_disable = 0x400006c4;
-rom_gpio_pad_input_enable = 0x400006c8;
-rom_gpio_pad_pulldown = 0x400006cc;
-rom_gpio_pad_pullup = 0x400006d0;
-rom_gpio_pad_select_gpio = 0x400006d4;
-rom_gpio_pad_set_drv = 0x400006d8;
-rom_gpio_pad_unhold = 0x400006dc;
-rom_gpio_pad_hold = 0x400006e0;
-
-
-/***************************************
- Group interrupts
- ***************************************/
-
-/* Functions */
-esprv_intc_int_set_priority = 0x400006e4;
-esprv_intc_int_set_threshold = 0x400006e8;
-esprv_intc_int_enable = 0x400006ec;
-esprv_intc_int_disable = 0x400006f0;
-esprv_intc_int_set_type = 0x400006f4;
-PROVIDE( intr_handler_set = 0x400006f8 );
-intr_matrix_set = 0x400006fc;
-ets_intr_register_ctx = 0x40000700;
-ets_intr_lock = 0x40000704;
-ets_intr_unlock = 0x40000708;
-ets_isr_attach = 0x4000070c;
-ets_isr_mask = 0x40000710;
-ets_isr_unmask = 0x40000714;
-
-
-/***************************************
- Group crc
- ***************************************/
-
-/* Functions */
-crc32_le = 0x40000718;
-crc16_le = 0x4000071c;
-crc8_le = 0x40000720;
-crc32_be = 0x40000724;
-crc16_be = 0x40000728;
-crc8_be = 0x4000072c;
-esp_crc8 = 0x40000730;
-/* Data (.data, .bss, .rodata) */
-crc32_le_table_ptr = 0x4001fff8;
-crc16_le_table_ptr = 0x4001fff4;
-crc8_le_table_ptr = 0x4001fff0;
-crc32_be_table_ptr = 0x4001ffec;
-crc16_be_table_ptr = 0x4001ffe8;
-crc8_be_table_ptr = 0x4001ffe4;
-
-
-/***************************************
- Group md5
- ***************************************/
-
-/* Functions */
-md5_vector = 0x40000734;
-MD5Init = 0x40000738;
-MD5Update = 0x4000073c;
-MD5Final = 0x40000740;
-
-
-/***************************************
- Group hwcrypto
- ***************************************/
-
-/* Functions */
-ets_sha_enable = 0x40000744;
-ets_sha_disable = 0x40000748;
-ets_sha_get_state = 0x4000074c;
-ets_sha_init = 0x40000750;
-ets_sha_process = 0x40000754;
-ets_sha_starts = 0x40000758;
-ets_sha_update = 0x4000075c;
-ets_sha_finish = 0x40000760;
-ets_sha_clone = 0x40000764;
-ets_hmac_enable = 0x40000768;
-ets_hmac_disable = 0x4000076c;
-ets_hmac_calculate_message = 0x40000770;
-ets_hmac_calculate_downstream = 0x40000774;
-ets_hmac_invalidate_downstream = 0x40000778;
-ets_aes_enable = 0x4000077c;
-ets_aes_disable = 0x40000780;
-ets_aes_setkey = 0x40000784;
-ets_aes_block = 0x40000788;
-ets_aes_setkey_dec = 0x4000078c;
-ets_aes_setkey_enc = 0x40000790;
-
-
-/***************************************
- Group efuse
- ***************************************/
-
-/* Functions */
-ets_efuse_read = 0x40000794;
-ets_efuse_program = 0x40000798;
-ets_efuse_clear_program_registers = 0x4000079c;
-ets_efuse_write_key = 0x400007a0;
-ets_efuse_get_read_register_address = 0x400007a4;
-ets_efuse_get_key_purpose = 0x400007a8;
-ets_efuse_key_block_unused = 0x400007ac;
-ets_efuse_find_unused_key_block = 0x400007b0;
-ets_efuse_rs_calculate = 0x400007b4;
-ets_efuse_count_unused_key_blocks = 0x400007b8;
-ets_efuse_secure_boot_enabled = 0x400007bc;
-ets_efuse_secure_boot_aggressive_revoke_enabled = 0x400007c0;
-ets_efuse_cache_encryption_enabled = 0x400007c4;
-ets_efuse_download_modes_disabled = 0x400007c8;
-ets_efuse_find_purpose = 0x400007cc;
-ets_efuse_force_send_resume = 0x400007d0;
-ets_efuse_get_flash_delay_us = 0x400007d4;
-ets_efuse_get_uart_print_control = 0x400007d8;
-ets_efuse_direct_boot_mode_disabled = 0x400007dc;
-ets_efuse_security_download_modes_enabled = 0x400007e0;
-ets_efuse_jtag_disabled = 0x400007e4;
-ets_efuse_usb_print_is_disabled = 0x400007e8;
-ets_efuse_usb_download_mode_disabled = 0x400007ec;
-ets_efuse_usb_device_disabled = 0x400007f0;
-ets_jtag_enable_temporarily = 0x400007f4;
-
-
-/***************************************
- Group key_mgr
- ***************************************/
-
-/* Functions */
-esp_rom_check_recover_key = 0x400007f8;
-esp_rom_km_huk_conf = 0x400007fc;
-esp_rom_km_huk_risk = 0x40000800;
-
-
-/***************************************
- Group secureboot
- ***************************************/
-
-/* Functions */
-ets_ecdsa_verify = 0x40000804;
-ets_secure_boot_verify_bootloader_with_keys = 0x40000808;
-ets_secure_boot_verify_signature = 0x4000080c;
-ets_secure_boot_read_key_digests = 0x40000810;
-ets_secure_boot_revoke_public_key_digest = 0x40000814;
-
-
-/***************************************
- Group usb_device_uart
- ***************************************/
-
-/* Functions */
-usb_serial_device_rx_one_char = 0x40000944;
-usb_serial_device_rx_one_char_block = 0x40000948;
-usb_serial_device_tx_flush = 0x4000094c;
-usb_serial_device_tx_one_char = 0x40000950;
diff --git a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.libc.ld b/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.libc.ld
deleted file mode 100644
index dc2b90c4b3..0000000000
--- a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.libc.ld
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-esp_rom_newlib_init_common_mutexes = 0x40000478;
-memset = 0x4000047c;
-memcpy = 0x40000480;
-memmove = 0x40000484;
-memcmp = 0x40000488;
-strcpy = 0x4000048c;
-strncpy = 0x40000490;
-strcmp = 0x40000494;
-strncmp = 0x40000498;
-strlen = 0x4000049c;
-strstr = 0x400004a0;
-bzero = 0x400004a4;
-sbrk = 0x400004ac;
-isalnum = 0x400004b0;
-isalpha = 0x400004b4;
-isascii = 0x400004b8;
-isblank = 0x400004bc;
-iscntrl = 0x400004c0;
-isdigit = 0x400004c4;
-islower = 0x400004c8;
-isgraph = 0x400004cc;
-isprint = 0x400004d0;
-ispunct = 0x400004d4;
-isspace = 0x400004d8;
-isupper = 0x400004dc;
-toupper = 0x400004e0;
-tolower = 0x400004e4;
-toascii = 0x400004e8;
-memccpy = 0x400004ec;
-memchr = 0x400004f0;
-memrchr = 0x400004f4;
-strcasecmp = 0x400004f8;
-strcasestr = 0x400004fc;
-strcat = 0x40000500;
-strchr = 0x40000508;
-strcspn = 0x4000050c;
-strcoll = 0x40000510;
-strlcat = 0x40000514;
-strlcpy = 0x40000518;
-strlwr = 0x4000051c;
-strncasecmp = 0x40000520;
-strncat = 0x40000524;
-strnlen = 0x4000052c;
-strrchr = 0x40000530;
-strsep = 0x40000534;
-strspn = 0x40000538;
-strtok_r = 0x4000053c;
-strupr = 0x40000540;
-longjmp = 0x40000544;
-setjmp = 0x40000548;
-abs = 0x4000054c;
-div = 0x40000550;
-labs = 0x40000554;
-ldiv = 0x40000558;
-qsort = 0x4000055c;
-utoa = 0x4000056c;
-itoa = 0x40000570;
-/* Data (.data, .bss, .rodata) */
-syscall_table_ptr = 0x4085ffd0;
-_global_impure_ptr = 0x4085ffcc;
diff --git a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.libgcc.ld b/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.libgcc.ld
deleted file mode 100644
index c59f6bf5b4..0000000000
--- a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.libgcc.ld
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* ROM function interface esp32h4.rom.libgcc.ld for esp32h4
- *
- *
- * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
- *
- * Compatible with ROM where ECO version equal or greater to 0.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
- */
-
-/***************************************
- Group libgccdf
- ***************************************/
-
-/* Functions */
-__absvdi2 = 0x40000818;
-__absvsi2 = 0x4000081c;
-__adddf3 = 0x40000820;
-__addvdi3 = 0x40000824;
-__addvsi3 = 0x40000828;
-__ashldi3 = 0x4000082c;
-__ashrdi3 = 0x40000830;
-__bswapdi2 = 0x40000834;
-__bswapsi2 = 0x40000838;
-__clear_cache = 0x4000083c;
-__clrsbdi2 = 0x40000840;
-__clrsbsi2 = 0x40000844;
-__clzdi2 = 0x40000848;
-__clzsi2 = 0x4000084c;
-__cmpdi2 = 0x40000850;
-__ctzdi2 = 0x40000854;
-__ctzsi2 = 0x40000858;
-__divdc3 = 0x4000085c;
-__divdf3 = 0x40000860;
-__divdi3 = 0x40000864;
-__divsc3 = 0x40000868;
-__divsi3 = 0x4000086c;
-__eqdf2 = 0x40000870;
-__extendsfdf2 = 0x40000874;
-__ffsdi2 = 0x40000878;
-__ffssi2 = 0x4000087c;
-__fixdfdi = 0x40000880;
-__fixdfsi = 0x40000884;
-__fixsfdi = 0x40000888;
-__fixunsdfsi = 0x4000088c;
-__fixunssfdi = 0x40000890;
-__fixunssfsi = 0x40000894;
-__floatdidf = 0x40000898;
-__floatdisf = 0x4000089c;
-__floatsidf = 0x400008a0;
-__floatundidf = 0x400008a4;
-__floatundisf = 0x400008a8;
-__floatunsidf = 0x400008ac;
-__gcc_bcmp = 0x400008b0;
-__gedf2 = 0x400008b4;
-__gtdf2 = 0x400008b8;
-__ledf2 = 0x400008bc;
-__lshrdi3 = 0x400008c0;
-__ltdf2 = 0x400008c4;
-__moddi3 = 0x400008c8;
-__modsi3 = 0x400008cc;
-__muldc3 = 0x400008d0;
-__muldf3 = 0x400008d4;
-__muldi3 = 0x400008d8;
-__mulsc3 = 0x400008dc;
-__mulsi3 = 0x400008e0;
-__mulvdi3 = 0x400008e4;
-__mulvsi3 = 0x400008e8;
-__nedf2 = 0x400008ec;
-__negdf2 = 0x400008f0;
-__negdi2 = 0x400008f4;
-__negvdi2 = 0x400008f8;
-__negvsi2 = 0x400008fc;
-__paritysi2 = 0x40000900;
-__popcountdi2 = 0x40000904;
-__popcountsi2 = 0x40000908;
-__powidf2 = 0x4000090c;
-__subdf3 = 0x40000910;
-__subvdi3 = 0x40000914;
-__subvsi3 = 0x40000918;
-__ucmpdi2 = 0x4000091c;
-__udivdi3 = 0x40000920;
-__udivmoddi4 = 0x40000924;
-__udivsi3 = 0x40000928;
-__udiv_w_sdiv = 0x4000092c;
-__umoddi3 = 0x40000930;
-__umodsi3 = 0x40000934;
-__unorddf2 = 0x40000938;
-__extenddftf2 = 0x4000093c;
-__trunctfdf2 = 0x40000940;
diff --git a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.newlib-nano.ld b/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.newlib-nano.ld
deleted file mode 100644
index 7013065490..0000000000
--- a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.newlib-nano.ld
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* ROM function interface esp32h4.rom.newlib-nano.ld for esp32h4
- *
- *
- * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
- *
- * Compatible with ROM where ECO version equal or greater to 0.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
- */
-
-/***************************************
- Group newlib_nano_format
- ***************************************/
-
-/* Functions */
-__sprint_r = 0x400005a8;
-_fiprintf_r = 0x400005ac;
-_fprintf_r = 0x400005b0;
-_printf_common = 0x400005b4;
-_printf_i = 0x400005b8;
-_vfiprintf_r = 0x400005bc;
-_vfprintf_r = 0x400005c0;
-fiprintf = 0x400005c4;
-fprintf = 0x400005c8;
-printf = 0x400005cc;
-vfiprintf = 0x400005d0;
-vfprintf = 0x400005d4;
diff --git a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.newlib.ld b/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.newlib.ld
deleted file mode 100644
index f5aa9ed91f..0000000000
--- a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.newlib.ld
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* ROM function interface esp32h4.rom.newlib.ld for esp32h4
- *
- *
- * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
- *
- * Compatible with ROM where ECO version equal or greater to 0.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. !!! BUT EDITED !!!
- * The file was originally generated for use with newlib, but it was split into
- * multiple files to make it compatible with picolibc.
- */
-
-/***************************************
- Group newlib
- ***************************************/
-
-/* Functions */
-_isatty_r = 0x400004a8;
-strdup = 0x40000504;
-strndup = 0x40000528;
-rand_r = 0x40000560;
-rand = 0x40000564;
-srand = 0x40000568;
-atoi = 0x40000574;
-atol = 0x40000578;
-strtol = 0x4000057c;
-strtoul = 0x40000580;
-fflush = 0x40000584;
-_fflush_r = 0x40000588;
-_fwalk = 0x4000058c;
-_fwalk_reent = 0x40000590;
-__smakebuf_r = 0x40000594;
-__swhatbuf_r = 0x40000598;
-__swbuf_r = 0x4000059c;
-__swbuf = 0x400005a0;
-__swsetup_r = 0x400005a4;
diff --git a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.spiflash.ld b/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.spiflash.ld
deleted file mode 100644
index 68d4edec42..0000000000
--- a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.spiflash.ld
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* ROM function interface esp32h4.rom.spiflash.ld for esp32h4
- *
- *
- * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
- *
- * Compatible with ROM where ECO version equal or greater to 0.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
- */
-
-/***************************************
- Group spi_flash_cache
- ***************************************/
-
-/* Functions */
-spi_flash_disable_cache = 0x400001f8;
-spi_flash_restore_cache = 0x400001fc;
-spi_flash_cache_enabled = 0x40000200;
-spi_flash_enable_cache = 0x40000204;
-esp_enable_cache_flash_wrap = 0x40000208;
-
-
-/***************************************
- Group esp_flash
- ***************************************/
-
-/* Functions */
-esp_flash_chip_driver_initialized = 0x4000020c;
-esp_flash_read_id = 0x40000210;
-esp_flash_get_size = 0x40000214;
-esp_flash_erase_chip = 0x40000218;
-rom_esp_flash_erase_region = 0x4000021c;
-esp_flash_get_chip_write_protect = 0x40000220;
-esp_flash_set_chip_write_protect = 0x40000224;
-esp_flash_get_protectable_regions = 0x40000228;
-esp_flash_get_protected_region = 0x4000022c;
-esp_flash_set_protected_region = 0x40000230;
-esp_flash_read = 0x40000234;
-rom_esp_flash_write = 0x40000238;
-rom_esp_flash_write_encrypted = 0x4000023c;
-esp_flash_read_encrypted = 0x40000240;
-esp_flash_get_io_mode = 0x40000244;
-esp_flash_set_io_mode = 0x40000248;
-spi_flash_boot_attach = 0x4000024c;
-esp_flash_read_chip_id = 0x40000250;
-detect_spi_flash_chip = 0x40000254;
-esp_flash_suspend_cmd_init = 0x40000258;
-/* Data (.data, .bss, .rodata) */
-esp_flash_default_chip = 0x4085ffe4;
-esp_flash_api_funcs = 0x4085ffe0;
-
-
-/***************************************
- Group spi_flash_chips
- ***************************************/
-
-/* Functions */
-spi_flash_chip_generic_probe = 0x4000025c;
-spi_flash_chip_generic_detect_size = 0x40000260;
-spi_flash_chip_generic_write = 0x40000264;
-spi_flash_chip_generic_write_encrypted = 0x40000268;
-spi_flash_chip_generic_set_write_protect = 0x4000026c;
-spi_flash_common_write_status_16b_wrsr = 0x40000270;
-spi_flash_chip_generic_reset = 0x40000274;
-spi_flash_chip_generic_erase_chip = 0x40000278;
-spi_flash_chip_generic_erase_sector = 0x4000027c;
-spi_flash_chip_generic_erase_block = 0x40000280;
-spi_flash_chip_generic_page_program = 0x40000284;
-spi_flash_chip_generic_get_write_protect = 0x40000288;
-spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x4000028c;
-spi_flash_chip_generic_read_reg = 0x40000290;
-spi_flash_chip_generic_yield = 0x40000294;
-spi_flash_generic_wait_host_idle = 0x40000298;
-spi_flash_chip_generic_wait_idle = 0x4000029c;
-spi_flash_chip_generic_config_host_io_mode = 0x400002a0;
-spi_flash_chip_generic_read = 0x400002a4;
-spi_flash_common_read_status_8b_rdsr2 = 0x400002a8;
-spi_flash_chip_generic_get_io_mode = 0x400002ac;
-spi_flash_common_read_status_8b_rdsr = 0x400002b0;
-spi_flash_common_write_status_8b_wrsr = 0x400002b4;
-spi_flash_common_write_status_8b_wrsr2 = 0x400002b8;
-spi_flash_common_set_io_mode = 0x400002bc;
-spi_flash_chip_generic_set_io_mode = 0x400002c0;
-spi_flash_chip_generic_read_unique_id = 0x400002c4;
-spi_flash_chip_generic_get_caps = 0x400002c8;
-spi_flash_chip_generic_suspend_cmd_conf = 0x400002cc;
-spi_flash_chip_gd_get_io_mode = 0x400002d0;
-spi_flash_chip_gd_probe = 0x400002d4;
-spi_flash_chip_gd_set_io_mode = 0x400002d8;
-/* Data (.data, .bss, .rodata) */
-spi_flash_chip_generic_config_data = 0x4085ffdc;
-spi_flash_encryption = 0x4085ffd8;
-
-
-/***************************************
- Group memspi_host
- ***************************************/
-
-/* Functions */
-memspi_host_read_id_hs = 0x400002dc;
-memspi_host_read_status_hs = 0x400002e0;
-memspi_host_flush_cache = 0x400002e4;
-memspi_host_erase_chip = 0x400002e8;
-memspi_host_erase_sector = 0x400002ec;
-memspi_host_erase_block = 0x400002f0;
-memspi_host_program_page = 0x400002f4;
-memspi_host_read = 0x400002f8;
-memspi_host_set_write_protect = 0x400002fc;
-memspi_host_set_max_read_len = 0x40000300;
-memspi_host_read_data_slicer = 0x40000304;
-memspi_host_write_data_slicer = 0x40000308;
-
-
-/***************************************
- Group hal_spiflash
- ***************************************/
-
-/* Functions */
-spi_flash_hal_poll_cmd_done = 0x4000030c;
-spi_flash_hal_device_config = 0x40000310;
-spi_flash_hal_configure_host_io_mode = 0x40000314;
-spi_flash_hal_common_command = 0x40000318;
-spi_flash_hal_read = 0x4000031c;
-spi_flash_hal_erase_chip = 0x40000320;
-spi_flash_hal_erase_sector = 0x40000324;
-spi_flash_hal_erase_block = 0x40000328;
-spi_flash_hal_program_page = 0x4000032c;
-spi_flash_hal_set_write_protect = 0x40000330;
-spi_flash_hal_host_idle = 0x40000334;
-spi_flash_hal_check_status = 0x40000338;
-spi_flash_hal_setup_read_suspend = 0x4000033c;
-spi_flash_hal_setup_auto_suspend_mode = 0x40000340;
-spi_flash_hal_setup_auto_resume_mode = 0x40000344;
-spi_flash_hal_disable_auto_suspend_mode = 0x40000348;
-spi_flash_hal_disable_auto_resume_mode = 0x4000034c;
-spi_flash_hal_resume = 0x40000350;
-spi_flash_hal_suspend = 0x40000354;
-spi_flash_encryption_hal_enable = 0x40000358;
-spi_flash_encryption_hal_disable = 0x4000035c;
-spi_flash_encryption_hal_prepare = 0x40000360;
-spi_flash_encryption_hal_done = 0x40000364;
-spi_flash_encryption_hal_destroy = 0x40000368;
-spi_flash_encryption_hal_check = 0x4000036c;
diff --git a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.systimer.ld b/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.systimer.ld
deleted file mode 100644
index 9b884abe8a..0000000000
--- a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.systimer.ld
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/***************************************
- Group hal_systimer
- ***************************************/
-
-/* Functions */
-/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
-/* systimer_hal_init = 0x4000039c; */
-/* systimer_hal_deinit = 0x400003a0; */
-
-systimer_hal_set_tick_rate_ops = 0x400003a4;
-systimer_hal_get_counter_value = 0x400003a8;
-systimer_hal_get_time = 0x400003ac;
-systimer_hal_set_alarm_target = 0x400003b0;
-systimer_hal_set_alarm_period = 0x400003b4;
-systimer_hal_get_alarm_value = 0x400003b8;
-systimer_hal_enable_alarm_int = 0x400003bc;
-systimer_hal_on_apb_freq_update = 0x400003c0;
-systimer_hal_counter_value_advance = 0x400003c4;
-systimer_hal_enable_counter = 0x400003c8;
-systimer_hal_select_alarm_mode = 0x400003cc;
-systimer_hal_connect_alarm_counter = 0x400003d0;
-systimer_hal_counter_can_stall_by_cpu = 0x400003d4;
diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt
index e316be13d3..27cc786832 100644
--- a/components/soc/CMakeLists.txt
+++ b/components/soc/CMakeLists.txt
@@ -4,17 +4,10 @@ set(target_folder "${target}")
 
 # On Linux the soc component is a simple wrapper, without much functionality
 if(NOT ${target} STREQUAL "linux")
-    if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
-        set(srcs "lldesc.c"
-                "dport_access_common.c"
-                "${target_folder}/interrupts_beta5.c"
-                "${target_folder}/gpio_periph.c")
-    else()
-        set(srcs "lldesc.c"
-                "dport_access_common.c"
-                "${target_folder}/interrupts.c"
-                "${target_folder}/gpio_periph.c")
-    endif()
+    set(srcs "lldesc.c"
+            "dport_access_common.c"
+            "${target_folder}/interrupts.c"
+            "${target_folder}/gpio_periph.c")
 endif()
 
 set(includes "include" "${target_folder}")
@@ -22,13 +15,6 @@ set(includes "include" "${target_folder}")
 if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/include")
     # miscellaneous headers, like definitions, man-made register headers, wrappers, etc.
     list(APPEND includes "${target_folder}/include")
-    if(CONFIG_IDF_TARGET_ESP32H4) # TODO: ESP32H4 IDF-13835
-        if(CONFIG_ESP32H4_SELECTS_REV_MP)
-            list(APPEND includes "${target_folder}/include/hw_ver_mp")
-        else()
-            list(APPEND includes "${target_folder}/include/hw_ver_beta5")
-        endif()
-    endif()
 endif()
 
 # register headers that generated by script from CSV
@@ -45,13 +31,6 @@ elseif(CONFIG_IDF_TARGET_ESP32H21) # TODO: ESP32H21 IDF-13923
     else()
         list(APPEND includes "${target_folder}/register/hw_ver_beta1")
     endif()
-elseif(CONFIG_IDF_TARGET_ESP32H4) # TODO: ESP32H4 IDF-13835
-    list(APPEND includes "${target_folder}/register")
-    if(CONFIG_ESP32H4_SELECTS_REV_MP)
-        list(APPEND includes "${target_folder}/register/hw_ver_mp")
-    else()
-        list(APPEND includes "${target_folder}/register/hw_ver_beta5")
-    endif()
 else()
     if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/register")
         list(APPEND includes "${target_folder}/register")
@@ -96,9 +75,5 @@ if(target STREQUAL "esp32")
 endif()
 
 if(NOT CONFIG_IDF_TARGET_LINUX)
-    if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
-        target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/ld/${target}.peripherals.beta5.ld")
-    else()
-        target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/ld/${target}.peripherals.ld")
-    endif()
+    target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/ld/${target}.peripherals.ld")
 endif()
diff --git a/components/soc/esp32h4/include/hw_ver_beta5/soc/interrupts.h b/components/soc/esp32h4/include/hw_ver_beta5/soc/interrupts.h
deleted file mode 100644
index fa561f85f0..0000000000
--- a/components/soc/esp32h4/include/hw_ver_beta5/soc/interrupts.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0 OR MIT
- */
-
-#pragma once
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//Interrupt hardware source table
-//This table is decided by hardware, don't touch this.
-typedef enum {
-    ETS_WIFI_MAC_INTR_SOURCE,
-    ETS_WIFI_MAC_NMI_SOURCE,
-    ETS_WIFI_PWR_INTR_SOURCE,
-    ETS_WIFI_BB_INTR_SOURCE,
-    ETS_BT_MAC_INTR_SOURCE,
-    ETS_BT_BB_INTR_SOURCE,
-    ETS_BT_BB_NMI_SOURCE,
-    ETS_LP_TIMER_INTR_SOURCE,
-    ETS_COEX_INTR_SOURCE,
-    ETS_BLE_TIMER_INTR_SOURCE,
-    ETS_BLE_SEC_INTR_SOURCE,
-    ETS_I2C_MST_INTR_SOURCE,
-    ETS_ZB_MAC_INTR_SOURCE,
-    ETS_MODEM_APB_TIMEOUT_INTR_SOURCE,
-    ETS_BT_MAC_INT1_SOURCE,
-    ETS_PMU_INTR_SOURCE,
-    ETS_EFUSE_INTR_SOURCE,
-    ETS_LP_RTC_TIMER_INTR_SOURCE,
-    ETS_LP_RTC_BLE_TIMER_INTR_SOURCE,
-    ETS_LP_WDT_INTR_SOURCE,
-    ETS_TOUCH_INTR_SOURCE,
-    ETS_HUK_INTR_SOURCE,
-    ETS_CPU_INTR_FROM_CPU_0_SOURCE,
-    ETS_CPU_INTR_FROM_CPU_1_SOURCE,
-    ETS_CPU_INTR_FROM_CPU_2_SOURCE,
-    ETS_CPU_INTR_FROM_CPU_3_SOURCE,
-    ETS_BUS_MONITOR_INTR_SOURCE,
-    ETS_CORE0_TRACE_INTR_SOURCE,
-    ETS_CORE1_TRACE_INTR_SOURCE,
-    ETS_CACHE_INTR_SOURCE,
-    ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
-    ETS_GPIO_INTERRUPT_PRO_SOURCE,
-    ETS_GPIO_INTERRUPT_2_SOURCE,
-    ETS_PAU_INTR_SOURCE,
-    ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
-    ETS_HP_APM_M0_INTR_SOURCE,
-    ETS_HP_APM_M1_INTR_SOURCE,
-    ETS_HP_APM_M2_INTR_SOURCE,
-    ETS_HP_APM_M3_INTR_SOURCE,
-    ETS_HP_APM_M4_INTR_SOURCE,
-    ETS_CPU_APM_M0_INTR_SOURCE,
-    ETS_CPU_APM_M1_INTR_SOURCE,
-    ETS_CPU_APM_M2_INTR_SOURCE,
-    ETS_CPU_APM_M3_INTR_SOURCE,
-    ETS_MSPI_INTR_SOURCE,
-    ETS_I2S_INTR_SOURCE,
-    ETS_UHCI0_INTR_SOURCE,
-    ETS_UART0_INTR_SOURCE,
-    ETS_UART1_INTR_SOURCE,
-    ETS_LEDC_INTR_SOURCE,
-    ETS_TWAI0_INTR_SOURCE,
-    ETS_TWAI0_TIMER_INTR_SOURCE,
-    ETS_USB_SERIAL_JTAG_INTR_SOURCE,
-    ETS_RMT_INTR_SOURCE,
-    ETS_I2C_EXT0_INTR_SOURCE,
-    ETS_I2C_EXT1_INTR_SOURCE,
-    ETS_TG0_T0_INTR_SOURCE,
-    ETS_TG0_WDT_INTR_SOURCE,
-    ETS_TG1_T0_INTR_SOURCE,
-    ETS_TG1_WDT_INTR_SOURCE,
-    ETS_SYSTIMER_TARGET0_INTR_SOURCE,
-    ETS_SYSTIMER_TARGET1_INTR_SOURCE,
-    ETS_SYSTIMER_TARGET2_INTR_SOURCE,
-    ETS_APB_ADC_INTR_SOURCE,
-    ETS_PWM0_INTR_SOURCE,
-    ETS_PWM1_INTR_SOURCE,
-    ETS_PCNT_INTR_SOURCE,
-    ETS_PARL_IO_TX_INTR_SOURCE,
-    ETS_PARL_IO_RX_INTR_SOURCE,
-    ETS_USB_OTG11_INTR_SOURCE,
-    ETS_ASRC_CHNL0_INTR_SOURCE,
-    ETS_ASRC_CHNL1_INTR_SOURCE,
-    ETS_ZERO_DET_INTR_SOURCE,
-    ETS_DMA_IN_CH0_INTR_SOURCE,
-    ETS_DMA_IN_CH1_INTR_SOURCE,
-    ETS_DMA_IN_CH2_INTR_SOURCE,
-    ETS_DMA_IN_CH3_INTR_SOURCE,
-    ETS_DMA_IN_CH4_INTR_SOURCE,
-    ETS_DMA_OUT_CH0_INTR_SOURCE,
-    ETS_DMA_OUT_CH1_INTR_SOURCE,
-    ETS_DMA_OUT_CH2_INTR_SOURCE,
-    ETS_DMA_OUT_CH3_INTR_SOURCE,
-    ETS_DMA_OUT_CH4_INTR_SOURCE,
-    ETS_GPSPI2_INTR_SOURCE,
-    ETS_GPSPI3_INTR_SOURCE,
-    ETS_AES_INTR_SOURCE,
-    ETS_SHA_INTR_SOURCE,
-    ETS_ECC_INTR_SOURCE,
-    ETS_ECDSA_INTR_SOURCE,
-    ETS_KM_INTR_SOURCE,
-    ETS_MAX_INTR_SOURCE,
-} periph_interrupt_t;
-
-extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h4/include/hw_ver_mp/soc/interrupts.h b/components/soc/esp32h4/include/soc/interrupts.h
similarity index 100%
rename from components/soc/esp32h4/include/hw_ver_mp/soc/interrupts.h
rename to components/soc/esp32h4/include/soc/interrupts.h
diff --git a/components/soc/esp32h4/interrupts_beta5.c b/components/soc/esp32h4/interrupts_beta5.c
deleted file mode 100644
index 16bc4d9b63..0000000000
--- a/components/soc/esp32h4/interrupts_beta5.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0 OR MIT
- */
-
-#include "soc/interrupts.h"
-
-const char *const esp_isr_names[] = {
-    [0] = "WIFI_MAC",
-    [1] = "WIFI_MAC_NMI",
-    [2] = "WIFI_PWR",
-    [3] = "WIFI_BB",
-    [4] = "BT_MAC",
-    [5] = "BT_BB",
-    [6] = "BT_BB_NMI",
-    [7] = "LP_TIMER",
-    [8] = "COEX",
-    [9] = "BLE_TIMER",
-    [10] = "BLE_SEC",
-    [11] = "I2C_MST",
-    [12] = "ZB_MAC",
-    [13] = "MODEM_APB_TIMEOUT",
-    [14] = "BT_MAC_INT1",
-    [15] = "PMU",
-    [16] = "EFUSE",
-    [17] = "LP_RTC_TIMER",
-    [18] = "LP_RTC_BLE_TIMER",
-    [19] = "LP_WDT",
-    [20] = "TOUCH",
-    [21] = "HUK",
-    [22] = "CPU_FROM_CPU_0",
-    [23] = "CPU_FROM_CPU_1",
-    [24] = "CPU_FROM_CPU_2",
-    [25] = "CPU_FROM_CPU_3",
-    [26] = "BUS_MONITOR",
-    [27] = "CORE0_TRACE",
-    [28] = "CORE1_TRACE",
-    [29] = "CACHE",
-    [30] = "CPU_PERI_TIMEOUT",
-    [31] = "GPIO_INTERRUPT_PRO",
-    [32] = "GPIO_INTERRUPT_2",
-    [33] = "PAU",
-    [34] = "HP_PERI_TIMEOUT",
-    [35] = "HP_APM_M0",
-    [36] = "HP_APM_M1",
-    [37] = "HP_APM_M2",
-    [38] = "HP_APM_M3",
-    [39] = "HP_APM_M4",
-    [40] = "CPU_APM_M0",
-    [41] = "CPU_APM_M1",
-    [42] = "CPU_APM_M2",
-    [43] = "CPU_APM_M3",
-    [44] = "MSPI",
-    [45] = "I2S",
-    [46] = "UHCI0",
-    [47] = "UART0",
-    [48] = "UART1",
-    [49] = "LEDC",
-    [50] = "TWAI0",
-    [51] = "TWAI0_TIMER",
-    [52] = "USB_SERIAL_JTAG",
-    [53] = "RMT",
-    [54] = "I2C_EXT0",
-    [55] = "I2C_EXT1",
-    [56] = "TG0_T0",
-    [57] = "TG0_WDT",
-    [58] = "TG1_T0",
-    [59] = "TG1_WDT",
-    [60] = "SYSTIMER_TARGET0",
-    [61] = "SYSTIMER_TARGET1",
-    [62] = "SYSTIMER_TARGET2",
-    [63] = "APB_ADC",
-    [64] = "PWM0",
-    [65] = "PWM1",
-    [66] = "PCNT",
-    [67] = "PARL_IO_TX",
-    [68] = "PARL_IO_RX",
-    [69] = "USB_OTG11",
-    [70] = "ASRC_CHNL0",
-    [71] = "ASRC_CHNL1",
-    [72] = "ZERO_DET",
-    [73] = "DMA_IN_CH0",
-    [74] = "DMA_IN_CH1",
-    [75] = "DMA_IN_CH2",
-    [76] = "DMA_IN_CH3",
-    [77] = "DMA_IN_CH4",
-    [78] = "DMA_OUT_CH0",
-    [79] = "DMA_OUT_CH1",
-    [80] = "DMA_OUT_CH2",
-    [81] = "DMA_OUT_CH3",
-    [82] = "DMA_OUT_CH4",
-    [83] = "GPSPI2",
-    [84] = "GPSPI3",
-    [85] = "AES",
-    [86] = "SHA",
-    [87] = "ECC",
-    [88] = "ECDSA",
-    [89] = "KM",
-};
diff --git a/components/soc/esp32h4/ld/esp32h4.peripherals.beta5.ld b/components/soc/esp32h4/ld/esp32h4.peripherals.beta5.ld
deleted file mode 100644
index 3c3f88eb1e..0000000000
--- a/components/soc/esp32h4/ld/esp32h4.peripherals.beta5.ld
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0 OR MIT
- */
-
-PROVIDE ( TRACE0              = 0x60000000 );
-PROVIDE ( TRACE1              = 0x60001000 );
-PROVIDE ( BUS_MONITOR         = 0x60002000 );
-PROVIDE ( INTPRI              = 0x60005000 );
-PROVIDE ( CACHE               = 0x60008000 );
-PROVIDE ( GPSPI2              = 0x60010000 );
-PROVIDE ( GPSPI3              = 0x60011000 );
-PROVIDE ( UART0               = 0x60012000 );
-PROVIDE ( UART1               = 0x60013000 );
-PROVIDE ( UHCI0               = 0x60014000 );
-PROVIDE ( I2C0                = 0x60015000 );
-PROVIDE ( I2C1                = 0x60016000 );
-PROVIDE ( I2S0                = 0x60017000 );
-PROVIDE ( PARL_IO             = 0x60018000 );
-PROVIDE ( MCPWM0              = 0x60019000 );
-PROVIDE ( MCPWM1              = 0x6001A000 );
-PROVIDE ( LEDC                = 0x6001B000 );
-PROVIDE ( TWAI0               = 0x6001C000 );
-PROVIDE ( USB_SERIAL_JTAG     = 0x6001D000 );
-PROVIDE ( RMT                 = 0x6001E000 );
-PROVIDE ( RMTMEM              = 0x6001E400 );
-PROVIDE ( AHB_DMA             = 0x6001F000 );
-PROVIDE ( PAU                 = 0x60020000 );
-PROVIDE ( SOC_ETM             = 0x60021000 );
-PROVIDE ( ADC                 = 0x60022000 );
-PROVIDE ( SYSTIMER            = 0x60023000 );
-PROVIDE ( PSRAM_ACS_MONITOR   = 0x60024000 ); /*  TODO: IDF-12491 [ESP32H4] inherit from verify code, need check */
-PROVIDE ( MEM_MONITOR         = 0x60025000 );
-PROVIDE ( PVT                 = 0x60026000 );
-PROVIDE ( PCNT                = 0x60027000 );
-PROVIDE ( SAMPLE_RATE_CONVERTER = 0x60028000 );
-PROVIDE ( ZERO_DET            = 0x60029000 );
-PROVIDE ( USB_OTG_FS_CORE0    = 0x60040000 );
-PROVIDE ( USB_OTG_FS_CORE1    = 0x6007F000 );
-PROVIDE ( USB_DWC             = 0x60040000 );
-PROVIDE ( USB_WRAP            = 0x60080000 );
-PROVIDE ( TIMERG0             = 0x60090000 );
-PROVIDE ( TIMERG1             = 0x60091000 );
-PROVIDE ( IO_MUX              = 0x60092000 );
-PROVIDE ( GPIO                = 0x60093000 );
-PROVIDE ( GPIO_EXT            = 0x60093E00 );
-PROVIDE ( SDM                 = 0x60093E00 );
-PROVIDE ( GLITCH_FILTER       = 0x60093ED8 );
-PROVIDE ( GPIO_ETM            = 0x60093F18 );
-PROVIDE ( PCR                 = 0x60094000 );
-PROVIDE ( SPIMEM0             = 0x60098000 );
-PROVIDE ( SPIMEM1             = 0x60099000 );
-PROVIDE ( INTMTX0             = 0x6009A000 );
-PROVIDE ( INTMTX1             = 0x6009B000 );
-PROVIDE ( HP_SYSTEM           = 0x6009C000 );
-PROVIDE ( HP_APM              = 0x6009D000 );
-PROVIDE ( CPU_APM             = 0x6009E000 );
-PROVIDE ( TEE                 = 0x6009F000 );
-PROVIDE ( KEYMNG              = 0x600A5000 );
-PROVIDE ( AES                 = 0x600A6000 );
-PROVIDE ( SHA                 = 0x600A7000 );
-PROVIDE ( ECC                 = 0x600A8000 );
-PROVIDE ( HMAC                = 0x600A9000 );
-PROVIDE ( ECDSA               = 0x600AA000 );
-PROVIDE ( HUK                 = 0x600B1000 );
-PROVIDE ( LP_TEE              = 0x600B1400 );
-PROVIDE ( EFUSE               = 0x600B1800 );
-PROVIDE ( OTP_DEBUG           = 0x600B1C00 );
-PROVIDE ( TRNG                = 0x600B2000 );
-PROVIDE ( PMU                 = 0x600B2400 );
-PROVIDE ( LP_AON              = 0x600B2800 );
-PROVIDE ( LP_ANA_PERI         = 0x600B2C00 );
-PROVIDE ( LP_CLKRST           = 0x600B3000 );
-PROVIDE ( LPPERI              = 0x600B3400 );
-PROVIDE ( LP_IO_MUX           = 0x600B3800 );
-PROVIDE ( LP_GPIO             = 0x600B3C00 );
-PROVIDE ( LP_TIMER            = 0x600B5000 );
-PROVIDE ( LP_WDT              = 0x600B5400 );
-PROVIDE ( TOUCH_SENS          = 0x600B5800 );
-PROVIDE ( TOUCH_AON           = 0x600B5C00 );
-PROVIDE ( IEEE802154          = 0x600C3000 );
-PROVIDE ( MODEM_SYSCON        = 0x600C9C00 );
-PROVIDE ( MODEM_LPCON         = 0x600CF000 );
diff --git a/components/soc/esp32h4/register/hw_ver_beta5/soc/cpu_apm_reg.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/cpu_apm_reg.h
deleted file mode 100644
index cbadb03916..0000000000
--- a/components/soc/esp32h4/register/hw_ver_beta5/soc/cpu_apm_reg.h
+++ /dev/null
@@ -1,1402 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0 OR MIT
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** CPU_APM_REGION_FILTER_EN_REG register
- *  Region filter enable register
- */
-#define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_APM_BASE + 0x0)
-/** CPU_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1;
- *  Configure bit $n (0-7) to enable region $n.
- *  0: disable
- *  1: enable
- */
-#define CPU_APM_REGION_FILTER_EN    0x000000FFU
-#define CPU_APM_REGION_FILTER_EN_M  (CPU_APM_REGION_FILTER_EN_V << CPU_APM_REGION_FILTER_EN_S)
-#define CPU_APM_REGION_FILTER_EN_V  0x000000FFU
-#define CPU_APM_REGION_FILTER_EN_S  0
-
-/** CPU_APM_REGION0_ADDR_START_REG register
- *  Region address register
- */
-#define CPU_APM_REGION0_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x4)
-/** CPU_APM_REGION0_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
- *  Low 12 bit, start address of region 0.
- */
-#define CPU_APM_REGION0_ADDR_START_L    0x00000FFFU
-#define CPU_APM_REGION0_ADDR_START_L_M  (CPU_APM_REGION0_ADDR_START_L_V << CPU_APM_REGION0_ADDR_START_L_S)
-#define CPU_APM_REGION0_ADDR_START_L_V  0x00000FFFU
-#define CPU_APM_REGION0_ADDR_START_L_S  0
-/** CPU_APM_REGION0_ADDR_START : R/W; bitpos: [18:12]; default: 0;
- *  Configures start address of region 0.
- */
-#define CPU_APM_REGION0_ADDR_START    0x0000007FU
-#define CPU_APM_REGION0_ADDR_START_M  (CPU_APM_REGION0_ADDR_START_V << CPU_APM_REGION0_ADDR_START_S)
-#define CPU_APM_REGION0_ADDR_START_V  0x0000007FU
-#define CPU_APM_REGION0_ADDR_START_S  12
-/** CPU_APM_REGION0_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  start address of region 0.
- */
-#define CPU_APM_REGION0_ADDR_START_H    0x00001FFFU
-#define CPU_APM_REGION0_ADDR_START_H_M  (CPU_APM_REGION0_ADDR_START_H_V << CPU_APM_REGION0_ADDR_START_H_S)
-#define CPU_APM_REGION0_ADDR_START_H_V  0x00001FFFU
-#define CPU_APM_REGION0_ADDR_START_H_S  19
-
-/** CPU_APM_REGION0_ADDR_END_REG register
- *  Region address register
- */
-#define CPU_APM_REGION0_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x8)
-/** CPU_APM_REGION0_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
- *  Low 12 bit, end address of region 0.
- */
-#define CPU_APM_REGION0_ADDR_END_L    0x00000FFFU
-#define CPU_APM_REGION0_ADDR_END_L_M  (CPU_APM_REGION0_ADDR_END_L_V << CPU_APM_REGION0_ADDR_END_L_S)
-#define CPU_APM_REGION0_ADDR_END_L_V  0x00000FFFU
-#define CPU_APM_REGION0_ADDR_END_L_S  0
-/** CPU_APM_REGION0_ADDR_END : R/W; bitpos: [18:12]; default: 127;
- *  Configures end address of region 0.
- */
-#define CPU_APM_REGION0_ADDR_END    0x0000007FU
-#define CPU_APM_REGION0_ADDR_END_M  (CPU_APM_REGION0_ADDR_END_V << CPU_APM_REGION0_ADDR_END_S)
-#define CPU_APM_REGION0_ADDR_END_V  0x0000007FU
-#define CPU_APM_REGION0_ADDR_END_S  12
-/** CPU_APM_REGION0_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  end address of region 0.
- */
-#define CPU_APM_REGION0_ADDR_END_H    0x00001FFFU
-#define CPU_APM_REGION0_ADDR_END_H_M  (CPU_APM_REGION0_ADDR_END_H_V << CPU_APM_REGION0_ADDR_END_H_S)
-#define CPU_APM_REGION0_ADDR_END_H_V  0x00001FFFU
-#define CPU_APM_REGION0_ADDR_END_H_S  19
-
-/** CPU_APM_REGION0_ATTR_REG register
- *  Region access authority attribute register
- */
-#define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_APM_BASE + 0xc)
-/** CPU_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0;
- *  Configures the execution authority of REE_MODE 0 in region 0.
- */
-#define CPU_APM_REGION0_R0_X    (BIT(0))
-#define CPU_APM_REGION0_R0_X_M  (CPU_APM_REGION0_R0_X_V << CPU_APM_REGION0_R0_X_S)
-#define CPU_APM_REGION0_R0_X_V  0x00000001U
-#define CPU_APM_REGION0_R0_X_S  0
-/** CPU_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0;
- *  Configures the write authority of REE_MODE 0 in region 0.
- */
-#define CPU_APM_REGION0_R0_W    (BIT(1))
-#define CPU_APM_REGION0_R0_W_M  (CPU_APM_REGION0_R0_W_V << CPU_APM_REGION0_R0_W_S)
-#define CPU_APM_REGION0_R0_W_V  0x00000001U
-#define CPU_APM_REGION0_R0_W_S  1
-/** CPU_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0;
- *  Configures the read authority of REE_MODE 0 in region 0.
- */
-#define CPU_APM_REGION0_R0_R    (BIT(2))
-#define CPU_APM_REGION0_R0_R_M  (CPU_APM_REGION0_R0_R_V << CPU_APM_REGION0_R0_R_S)
-#define CPU_APM_REGION0_R0_R_V  0x00000001U
-#define CPU_APM_REGION0_R0_R_S  2
-/** CPU_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0;
- *  Configures the execution authority of REE_MODE 1 in region 0.
- */
-#define CPU_APM_REGION0_R1_X    (BIT(4))
-#define CPU_APM_REGION0_R1_X_M  (CPU_APM_REGION0_R1_X_V << CPU_APM_REGION0_R1_X_S)
-#define CPU_APM_REGION0_R1_X_V  0x00000001U
-#define CPU_APM_REGION0_R1_X_S  4
-/** CPU_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0;
- *  Configures the write authority of REE_MODE 1 in region 0.
- */
-#define CPU_APM_REGION0_R1_W    (BIT(5))
-#define CPU_APM_REGION0_R1_W_M  (CPU_APM_REGION0_R1_W_V << CPU_APM_REGION0_R1_W_S)
-#define CPU_APM_REGION0_R1_W_V  0x00000001U
-#define CPU_APM_REGION0_R1_W_S  5
-/** CPU_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0;
- *  Configures the read authority of REE_MODE 1 in region 0.
- */
-#define CPU_APM_REGION0_R1_R    (BIT(6))
-#define CPU_APM_REGION0_R1_R_M  (CPU_APM_REGION0_R1_R_V << CPU_APM_REGION0_R1_R_S)
-#define CPU_APM_REGION0_R1_R_V  0x00000001U
-#define CPU_APM_REGION0_R1_R_S  6
-/** CPU_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0;
- *  Configures the execution authority of REE_MODE 2 in region 0.
- */
-#define CPU_APM_REGION0_R2_X    (BIT(8))
-#define CPU_APM_REGION0_R2_X_M  (CPU_APM_REGION0_R2_X_V << CPU_APM_REGION0_R2_X_S)
-#define CPU_APM_REGION0_R2_X_V  0x00000001U
-#define CPU_APM_REGION0_R2_X_S  8
-/** CPU_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0;
- *  Configures the write authority of REE_MODE 2 in region 0.
- */
-#define CPU_APM_REGION0_R2_W    (BIT(9))
-#define CPU_APM_REGION0_R2_W_M  (CPU_APM_REGION0_R2_W_V << CPU_APM_REGION0_R2_W_S)
-#define CPU_APM_REGION0_R2_W_V  0x00000001U
-#define CPU_APM_REGION0_R2_W_S  9
-/** CPU_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0;
- *  Configures the read authority of REE_MODE 2 in region 0.
- */
-#define CPU_APM_REGION0_R2_R    (BIT(10))
-#define CPU_APM_REGION0_R2_R_M  (CPU_APM_REGION0_R2_R_V << CPU_APM_REGION0_R2_R_S)
-#define CPU_APM_REGION0_R2_R_V  0x00000001U
-#define CPU_APM_REGION0_R2_R_S  10
-/** CPU_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region0 configuration
- */
-#define CPU_APM_REGION0_LOCK    (BIT(11))
-#define CPU_APM_REGION0_LOCK_M  (CPU_APM_REGION0_LOCK_V << CPU_APM_REGION0_LOCK_S)
-#define CPU_APM_REGION0_LOCK_V  0x00000001U
-#define CPU_APM_REGION0_LOCK_S  11
-
-/** CPU_APM_REGION1_ADDR_START_REG register
- *  Region address register
- */
-#define CPU_APM_REGION1_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x10)
-/** CPU_APM_REGION1_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
- *  Low 12 bit, start address of region 1.
- */
-#define CPU_APM_REGION1_ADDR_START_L    0x00000FFFU
-#define CPU_APM_REGION1_ADDR_START_L_M  (CPU_APM_REGION1_ADDR_START_L_V << CPU_APM_REGION1_ADDR_START_L_S)
-#define CPU_APM_REGION1_ADDR_START_L_V  0x00000FFFU
-#define CPU_APM_REGION1_ADDR_START_L_S  0
-/** CPU_APM_REGION1_ADDR_START : R/W; bitpos: [18:12]; default: 0;
- *  Configures start address of region 1.
- */
-#define CPU_APM_REGION1_ADDR_START    0x0000007FU
-#define CPU_APM_REGION1_ADDR_START_M  (CPU_APM_REGION1_ADDR_START_V << CPU_APM_REGION1_ADDR_START_S)
-#define CPU_APM_REGION1_ADDR_START_V  0x0000007FU
-#define CPU_APM_REGION1_ADDR_START_S  12
-/** CPU_APM_REGION1_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  start address of region 1.
- */
-#define CPU_APM_REGION1_ADDR_START_H    0x00001FFFU
-#define CPU_APM_REGION1_ADDR_START_H_M  (CPU_APM_REGION1_ADDR_START_H_V << CPU_APM_REGION1_ADDR_START_H_S)
-#define CPU_APM_REGION1_ADDR_START_H_V  0x00001FFFU
-#define CPU_APM_REGION1_ADDR_START_H_S  19
-
-/** CPU_APM_REGION1_ADDR_END_REG register
- *  Region address register
- */
-#define CPU_APM_REGION1_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x14)
-/** CPU_APM_REGION1_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
- *  Low 12 bit, end address of region 1.
- */
-#define CPU_APM_REGION1_ADDR_END_L    0x00000FFFU
-#define CPU_APM_REGION1_ADDR_END_L_M  (CPU_APM_REGION1_ADDR_END_L_V << CPU_APM_REGION1_ADDR_END_L_S)
-#define CPU_APM_REGION1_ADDR_END_L_V  0x00000FFFU
-#define CPU_APM_REGION1_ADDR_END_L_S  0
-/** CPU_APM_REGION1_ADDR_END : R/W; bitpos: [18:12]; default: 127;
- *  Configures end address of region 1.
- */
-#define CPU_APM_REGION1_ADDR_END    0x0000007FU
-#define CPU_APM_REGION1_ADDR_END_M  (CPU_APM_REGION1_ADDR_END_V << CPU_APM_REGION1_ADDR_END_S)
-#define CPU_APM_REGION1_ADDR_END_V  0x0000007FU
-#define CPU_APM_REGION1_ADDR_END_S  12
-/** CPU_APM_REGION1_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  end address of region 1.
- */
-#define CPU_APM_REGION1_ADDR_END_H    0x00001FFFU
-#define CPU_APM_REGION1_ADDR_END_H_M  (CPU_APM_REGION1_ADDR_END_H_V << CPU_APM_REGION1_ADDR_END_H_S)
-#define CPU_APM_REGION1_ADDR_END_H_V  0x00001FFFU
-#define CPU_APM_REGION1_ADDR_END_H_S  19
-
-/** CPU_APM_REGION1_ATTR_REG register
- *  Region access authority attribute register
- */
-#define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_APM_BASE + 0x18)
-/** CPU_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0;
- *  Configures the execution authority of REE_MODE 0 in region 1.
- */
-#define CPU_APM_REGION1_R0_X    (BIT(0))
-#define CPU_APM_REGION1_R0_X_M  (CPU_APM_REGION1_R0_X_V << CPU_APM_REGION1_R0_X_S)
-#define CPU_APM_REGION1_R0_X_V  0x00000001U
-#define CPU_APM_REGION1_R0_X_S  0
-/** CPU_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0;
- *  Configures the write authority of REE_MODE 0 in region 1.
- */
-#define CPU_APM_REGION1_R0_W    (BIT(1))
-#define CPU_APM_REGION1_R0_W_M  (CPU_APM_REGION1_R0_W_V << CPU_APM_REGION1_R0_W_S)
-#define CPU_APM_REGION1_R0_W_V  0x00000001U
-#define CPU_APM_REGION1_R0_W_S  1
-/** CPU_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0;
- *  Configures the read authority of REE_MODE 0 in region 1.
- */
-#define CPU_APM_REGION1_R0_R    (BIT(2))
-#define CPU_APM_REGION1_R0_R_M  (CPU_APM_REGION1_R0_R_V << CPU_APM_REGION1_R0_R_S)
-#define CPU_APM_REGION1_R0_R_V  0x00000001U
-#define CPU_APM_REGION1_R0_R_S  2
-/** CPU_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0;
- *  Configures the execution authority of REE_MODE 1 in region 1.
- */
-#define CPU_APM_REGION1_R1_X    (BIT(4))
-#define CPU_APM_REGION1_R1_X_M  (CPU_APM_REGION1_R1_X_V << CPU_APM_REGION1_R1_X_S)
-#define CPU_APM_REGION1_R1_X_V  0x00000001U
-#define CPU_APM_REGION1_R1_X_S  4
-/** CPU_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0;
- *  Configures the write authority of REE_MODE 1 in region 1.
- */
-#define CPU_APM_REGION1_R1_W    (BIT(5))
-#define CPU_APM_REGION1_R1_W_M  (CPU_APM_REGION1_R1_W_V << CPU_APM_REGION1_R1_W_S)
-#define CPU_APM_REGION1_R1_W_V  0x00000001U
-#define CPU_APM_REGION1_R1_W_S  5
-/** CPU_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0;
- *  Configures the read authority of REE_MODE 1 in region 1.
- */
-#define CPU_APM_REGION1_R1_R    (BIT(6))
-#define CPU_APM_REGION1_R1_R_M  (CPU_APM_REGION1_R1_R_V << CPU_APM_REGION1_R1_R_S)
-#define CPU_APM_REGION1_R1_R_V  0x00000001U
-#define CPU_APM_REGION1_R1_R_S  6
-/** CPU_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0;
- *  Configures the execution authority of REE_MODE 2 in region 1.
- */
-#define CPU_APM_REGION1_R2_X    (BIT(8))
-#define CPU_APM_REGION1_R2_X_M  (CPU_APM_REGION1_R2_X_V << CPU_APM_REGION1_R2_X_S)
-#define CPU_APM_REGION1_R2_X_V  0x00000001U
-#define CPU_APM_REGION1_R2_X_S  8
-/** CPU_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0;
- *  Configures the write authority of REE_MODE 2 in region 1.
- */
-#define CPU_APM_REGION1_R2_W    (BIT(9))
-#define CPU_APM_REGION1_R2_W_M  (CPU_APM_REGION1_R2_W_V << CPU_APM_REGION1_R2_W_S)
-#define CPU_APM_REGION1_R2_W_V  0x00000001U
-#define CPU_APM_REGION1_R2_W_S  9
-/** CPU_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0;
- *  Configures the read authority of REE_MODE 2 in region 1.
- */
-#define CPU_APM_REGION1_R2_R    (BIT(10))
-#define CPU_APM_REGION1_R2_R_M  (CPU_APM_REGION1_R2_R_V << CPU_APM_REGION1_R2_R_S)
-#define CPU_APM_REGION1_R2_R_V  0x00000001U
-#define CPU_APM_REGION1_R2_R_S  10
-/** CPU_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region0 configuration
- */
-#define CPU_APM_REGION1_LOCK    (BIT(11))
-#define CPU_APM_REGION1_LOCK_M  (CPU_APM_REGION1_LOCK_V << CPU_APM_REGION1_LOCK_S)
-#define CPU_APM_REGION1_LOCK_V  0x00000001U
-#define CPU_APM_REGION1_LOCK_S  11
-
-/** CPU_APM_REGION2_ADDR_START_REG register
- *  Region address register
- */
-#define CPU_APM_REGION2_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x1c)
-/** CPU_APM_REGION2_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
- *  Low 12 bit, start address of region 2.
- */
-#define CPU_APM_REGION2_ADDR_START_L    0x00000FFFU
-#define CPU_APM_REGION2_ADDR_START_L_M  (CPU_APM_REGION2_ADDR_START_L_V << CPU_APM_REGION2_ADDR_START_L_S)
-#define CPU_APM_REGION2_ADDR_START_L_V  0x00000FFFU
-#define CPU_APM_REGION2_ADDR_START_L_S  0
-/** CPU_APM_REGION2_ADDR_START : R/W; bitpos: [18:12]; default: 0;
- *  Configures start address of region 2.
- */
-#define CPU_APM_REGION2_ADDR_START    0x0000007FU
-#define CPU_APM_REGION2_ADDR_START_M  (CPU_APM_REGION2_ADDR_START_V << CPU_APM_REGION2_ADDR_START_S)
-#define CPU_APM_REGION2_ADDR_START_V  0x0000007FU
-#define CPU_APM_REGION2_ADDR_START_S  12
-/** CPU_APM_REGION2_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  start address of region 2.
- */
-#define CPU_APM_REGION2_ADDR_START_H    0x00001FFFU
-#define CPU_APM_REGION2_ADDR_START_H_M  (CPU_APM_REGION2_ADDR_START_H_V << CPU_APM_REGION2_ADDR_START_H_S)
-#define CPU_APM_REGION2_ADDR_START_H_V  0x00001FFFU
-#define CPU_APM_REGION2_ADDR_START_H_S  19
-
-/** CPU_APM_REGION2_ADDR_END_REG register
- *  Region address register
- */
-#define CPU_APM_REGION2_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x20)
-/** CPU_APM_REGION2_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
- *  Low 12 bit, end address of region 2.
- */
-#define CPU_APM_REGION2_ADDR_END_L    0x00000FFFU
-#define CPU_APM_REGION2_ADDR_END_L_M  (CPU_APM_REGION2_ADDR_END_L_V << CPU_APM_REGION2_ADDR_END_L_S)
-#define CPU_APM_REGION2_ADDR_END_L_V  0x00000FFFU
-#define CPU_APM_REGION2_ADDR_END_L_S  0
-/** CPU_APM_REGION2_ADDR_END : R/W; bitpos: [18:12]; default: 127;
- *  Configures end address of region 2.
- */
-#define CPU_APM_REGION2_ADDR_END    0x0000007FU
-#define CPU_APM_REGION2_ADDR_END_M  (CPU_APM_REGION2_ADDR_END_V << CPU_APM_REGION2_ADDR_END_S)
-#define CPU_APM_REGION2_ADDR_END_V  0x0000007FU
-#define CPU_APM_REGION2_ADDR_END_S  12
-/** CPU_APM_REGION2_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  end address of region 2.
- */
-#define CPU_APM_REGION2_ADDR_END_H    0x00001FFFU
-#define CPU_APM_REGION2_ADDR_END_H_M  (CPU_APM_REGION2_ADDR_END_H_V << CPU_APM_REGION2_ADDR_END_H_S)
-#define CPU_APM_REGION2_ADDR_END_H_V  0x00001FFFU
-#define CPU_APM_REGION2_ADDR_END_H_S  19
-
-/** CPU_APM_REGION2_ATTR_REG register
- *  Region access authority attribute register
- */
-#define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_APM_BASE + 0x24)
-/** CPU_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0;
- *  Configures the execution authority of REE_MODE 0 in region 2.
- */
-#define CPU_APM_REGION2_R0_X    (BIT(0))
-#define CPU_APM_REGION2_R0_X_M  (CPU_APM_REGION2_R0_X_V << CPU_APM_REGION2_R0_X_S)
-#define CPU_APM_REGION2_R0_X_V  0x00000001U
-#define CPU_APM_REGION2_R0_X_S  0
-/** CPU_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0;
- *  Configures the write authority of REE_MODE 0 in region 2.
- */
-#define CPU_APM_REGION2_R0_W    (BIT(1))
-#define CPU_APM_REGION2_R0_W_M  (CPU_APM_REGION2_R0_W_V << CPU_APM_REGION2_R0_W_S)
-#define CPU_APM_REGION2_R0_W_V  0x00000001U
-#define CPU_APM_REGION2_R0_W_S  1
-/** CPU_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0;
- *  Configures the read authority of REE_MODE 0 in region 2.
- */
-#define CPU_APM_REGION2_R0_R    (BIT(2))
-#define CPU_APM_REGION2_R0_R_M  (CPU_APM_REGION2_R0_R_V << CPU_APM_REGION2_R0_R_S)
-#define CPU_APM_REGION2_R0_R_V  0x00000001U
-#define CPU_APM_REGION2_R0_R_S  2
-/** CPU_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0;
- *  Configures the execution authority of REE_MODE 1 in region 2.
- */
-#define CPU_APM_REGION2_R1_X    (BIT(4))
-#define CPU_APM_REGION2_R1_X_M  (CPU_APM_REGION2_R1_X_V << CPU_APM_REGION2_R1_X_S)
-#define CPU_APM_REGION2_R1_X_V  0x00000001U
-#define CPU_APM_REGION2_R1_X_S  4
-/** CPU_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0;
- *  Configures the write authority of REE_MODE 1 in region 2.
- */
-#define CPU_APM_REGION2_R1_W    (BIT(5))
-#define CPU_APM_REGION2_R1_W_M  (CPU_APM_REGION2_R1_W_V << CPU_APM_REGION2_R1_W_S)
-#define CPU_APM_REGION2_R1_W_V  0x00000001U
-#define CPU_APM_REGION2_R1_W_S  5
-/** CPU_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0;
- *  Configures the read authority of REE_MODE 1 in region 2.
- */
-#define CPU_APM_REGION2_R1_R    (BIT(6))
-#define CPU_APM_REGION2_R1_R_M  (CPU_APM_REGION2_R1_R_V << CPU_APM_REGION2_R1_R_S)
-#define CPU_APM_REGION2_R1_R_V  0x00000001U
-#define CPU_APM_REGION2_R1_R_S  6
-/** CPU_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0;
- *  Configures the execution authority of REE_MODE 2 in region 2.
- */
-#define CPU_APM_REGION2_R2_X    (BIT(8))
-#define CPU_APM_REGION2_R2_X_M  (CPU_APM_REGION2_R2_X_V << CPU_APM_REGION2_R2_X_S)
-#define CPU_APM_REGION2_R2_X_V  0x00000001U
-#define CPU_APM_REGION2_R2_X_S  8
-/** CPU_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0;
- *  Configures the write authority of REE_MODE 2 in region 2.
- */
-#define CPU_APM_REGION2_R2_W    (BIT(9))
-#define CPU_APM_REGION2_R2_W_M  (CPU_APM_REGION2_R2_W_V << CPU_APM_REGION2_R2_W_S)
-#define CPU_APM_REGION2_R2_W_V  0x00000001U
-#define CPU_APM_REGION2_R2_W_S  9
-/** CPU_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0;
- *  Configures the read authority of REE_MODE 2 in region 2.
- */
-#define CPU_APM_REGION2_R2_R    (BIT(10))
-#define CPU_APM_REGION2_R2_R_M  (CPU_APM_REGION2_R2_R_V << CPU_APM_REGION2_R2_R_S)
-#define CPU_APM_REGION2_R2_R_V  0x00000001U
-#define CPU_APM_REGION2_R2_R_S  10
-/** CPU_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region0 configuration
- */
-#define CPU_APM_REGION2_LOCK    (BIT(11))
-#define CPU_APM_REGION2_LOCK_M  (CPU_APM_REGION2_LOCK_V << CPU_APM_REGION2_LOCK_S)
-#define CPU_APM_REGION2_LOCK_V  0x00000001U
-#define CPU_APM_REGION2_LOCK_S  11
-
-/** CPU_APM_REGION3_ADDR_START_REG register
- *  Region address register
- */
-#define CPU_APM_REGION3_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x28)
-/** CPU_APM_REGION3_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
- *  Low 12 bit, start address of region 3.
- */
-#define CPU_APM_REGION3_ADDR_START_L    0x00000FFFU
-#define CPU_APM_REGION3_ADDR_START_L_M  (CPU_APM_REGION3_ADDR_START_L_V << CPU_APM_REGION3_ADDR_START_L_S)
-#define CPU_APM_REGION3_ADDR_START_L_V  0x00000FFFU
-#define CPU_APM_REGION3_ADDR_START_L_S  0
-/** CPU_APM_REGION3_ADDR_START : R/W; bitpos: [18:12]; default: 0;
- *  Configures start address of region 3.
- */
-#define CPU_APM_REGION3_ADDR_START    0x0000007FU
-#define CPU_APM_REGION3_ADDR_START_M  (CPU_APM_REGION3_ADDR_START_V << CPU_APM_REGION3_ADDR_START_S)
-#define CPU_APM_REGION3_ADDR_START_V  0x0000007FU
-#define CPU_APM_REGION3_ADDR_START_S  12
-/** CPU_APM_REGION3_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  start address of region 3.
- */
-#define CPU_APM_REGION3_ADDR_START_H    0x00001FFFU
-#define CPU_APM_REGION3_ADDR_START_H_M  (CPU_APM_REGION3_ADDR_START_H_V << CPU_APM_REGION3_ADDR_START_H_S)
-#define CPU_APM_REGION3_ADDR_START_H_V  0x00001FFFU
-#define CPU_APM_REGION3_ADDR_START_H_S  19
-
-/** CPU_APM_REGION3_ADDR_END_REG register
- *  Region address register
- */
-#define CPU_APM_REGION3_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x2c)
-/** CPU_APM_REGION3_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
- *  Low 12 bit, end address of region 3.
- */
-#define CPU_APM_REGION3_ADDR_END_L    0x00000FFFU
-#define CPU_APM_REGION3_ADDR_END_L_M  (CPU_APM_REGION3_ADDR_END_L_V << CPU_APM_REGION3_ADDR_END_L_S)
-#define CPU_APM_REGION3_ADDR_END_L_V  0x00000FFFU
-#define CPU_APM_REGION3_ADDR_END_L_S  0
-/** CPU_APM_REGION3_ADDR_END : R/W; bitpos: [18:12]; default: 127;
- *  Configures end address of region 3.
- */
-#define CPU_APM_REGION3_ADDR_END    0x0000007FU
-#define CPU_APM_REGION3_ADDR_END_M  (CPU_APM_REGION3_ADDR_END_V << CPU_APM_REGION3_ADDR_END_S)
-#define CPU_APM_REGION3_ADDR_END_V  0x0000007FU
-#define CPU_APM_REGION3_ADDR_END_S  12
-/** CPU_APM_REGION3_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  end address of region 3.
- */
-#define CPU_APM_REGION3_ADDR_END_H    0x00001FFFU
-#define CPU_APM_REGION3_ADDR_END_H_M  (CPU_APM_REGION3_ADDR_END_H_V << CPU_APM_REGION3_ADDR_END_H_S)
-#define CPU_APM_REGION3_ADDR_END_H_V  0x00001FFFU
-#define CPU_APM_REGION3_ADDR_END_H_S  19
-
-/** CPU_APM_REGION3_ATTR_REG register
- *  Region access authority attribute register
- */
-#define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_APM_BASE + 0x30)
-/** CPU_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0;
- *  Configures the execution authority of REE_MODE 0 in region 3.
- */
-#define CPU_APM_REGION3_R0_X    (BIT(0))
-#define CPU_APM_REGION3_R0_X_M  (CPU_APM_REGION3_R0_X_V << CPU_APM_REGION3_R0_X_S)
-#define CPU_APM_REGION3_R0_X_V  0x00000001U
-#define CPU_APM_REGION3_R0_X_S  0
-/** CPU_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0;
- *  Configures the write authority of REE_MODE 0 in region 3.
- */
-#define CPU_APM_REGION3_R0_W    (BIT(1))
-#define CPU_APM_REGION3_R0_W_M  (CPU_APM_REGION3_R0_W_V << CPU_APM_REGION3_R0_W_S)
-#define CPU_APM_REGION3_R0_W_V  0x00000001U
-#define CPU_APM_REGION3_R0_W_S  1
-/** CPU_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0;
- *  Configures the read authority of REE_MODE 0 in region 3.
- */
-#define CPU_APM_REGION3_R0_R    (BIT(2))
-#define CPU_APM_REGION3_R0_R_M  (CPU_APM_REGION3_R0_R_V << CPU_APM_REGION3_R0_R_S)
-#define CPU_APM_REGION3_R0_R_V  0x00000001U
-#define CPU_APM_REGION3_R0_R_S  2
-/** CPU_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0;
- *  Configures the execution authority of REE_MODE 1 in region 3.
- */
-#define CPU_APM_REGION3_R1_X    (BIT(4))
-#define CPU_APM_REGION3_R1_X_M  (CPU_APM_REGION3_R1_X_V << CPU_APM_REGION3_R1_X_S)
-#define CPU_APM_REGION3_R1_X_V  0x00000001U
-#define CPU_APM_REGION3_R1_X_S  4
-/** CPU_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0;
- *  Configures the write authority of REE_MODE 1 in region 3.
- */
-#define CPU_APM_REGION3_R1_W    (BIT(5))
-#define CPU_APM_REGION3_R1_W_M  (CPU_APM_REGION3_R1_W_V << CPU_APM_REGION3_R1_W_S)
-#define CPU_APM_REGION3_R1_W_V  0x00000001U
-#define CPU_APM_REGION3_R1_W_S  5
-/** CPU_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0;
- *  Configures the read authority of REE_MODE 1 in region 3.
- */
-#define CPU_APM_REGION3_R1_R    (BIT(6))
-#define CPU_APM_REGION3_R1_R_M  (CPU_APM_REGION3_R1_R_V << CPU_APM_REGION3_R1_R_S)
-#define CPU_APM_REGION3_R1_R_V  0x00000001U
-#define CPU_APM_REGION3_R1_R_S  6
-/** CPU_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0;
- *  Configures the execution authority of REE_MODE 2 in region 3.
- */
-#define CPU_APM_REGION3_R2_X    (BIT(8))
-#define CPU_APM_REGION3_R2_X_M  (CPU_APM_REGION3_R2_X_V << CPU_APM_REGION3_R2_X_S)
-#define CPU_APM_REGION3_R2_X_V  0x00000001U
-#define CPU_APM_REGION3_R2_X_S  8
-/** CPU_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0;
- *  Configures the write authority of REE_MODE 2 in region 3.
- */
-#define CPU_APM_REGION3_R2_W    (BIT(9))
-#define CPU_APM_REGION3_R2_W_M  (CPU_APM_REGION3_R2_W_V << CPU_APM_REGION3_R2_W_S)
-#define CPU_APM_REGION3_R2_W_V  0x00000001U
-#define CPU_APM_REGION3_R2_W_S  9
-/** CPU_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0;
- *  Configures the read authority of REE_MODE 2 in region 3.
- */
-#define CPU_APM_REGION3_R2_R    (BIT(10))
-#define CPU_APM_REGION3_R2_R_M  (CPU_APM_REGION3_R2_R_V << CPU_APM_REGION3_R2_R_S)
-#define CPU_APM_REGION3_R2_R_V  0x00000001U
-#define CPU_APM_REGION3_R2_R_S  10
-/** CPU_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region0 configuration
- */
-#define CPU_APM_REGION3_LOCK    (BIT(11))
-#define CPU_APM_REGION3_LOCK_M  (CPU_APM_REGION3_LOCK_V << CPU_APM_REGION3_LOCK_S)
-#define CPU_APM_REGION3_LOCK_V  0x00000001U
-#define CPU_APM_REGION3_LOCK_S  11
-
-/** CPU_APM_REGION4_ADDR_START_REG register
- *  Region address register
- */
-#define CPU_APM_REGION4_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x34)
-/** CPU_APM_REGION4_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
- *  Low 12 bit, start address of region 4.
- */
-#define CPU_APM_REGION4_ADDR_START_L    0x00000FFFU
-#define CPU_APM_REGION4_ADDR_START_L_M  (CPU_APM_REGION4_ADDR_START_L_V << CPU_APM_REGION4_ADDR_START_L_S)
-#define CPU_APM_REGION4_ADDR_START_L_V  0x00000FFFU
-#define CPU_APM_REGION4_ADDR_START_L_S  0
-/** CPU_APM_REGION4_ADDR_START : R/W; bitpos: [18:12]; default: 0;
- *  Configures start address of region 4.
- */
-#define CPU_APM_REGION4_ADDR_START    0x0000007FU
-#define CPU_APM_REGION4_ADDR_START_M  (CPU_APM_REGION4_ADDR_START_V << CPU_APM_REGION4_ADDR_START_S)
-#define CPU_APM_REGION4_ADDR_START_V  0x0000007FU
-#define CPU_APM_REGION4_ADDR_START_S  12
-/** CPU_APM_REGION4_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  start address of region 4.
- */
-#define CPU_APM_REGION4_ADDR_START_H    0x00001FFFU
-#define CPU_APM_REGION4_ADDR_START_H_M  (CPU_APM_REGION4_ADDR_START_H_V << CPU_APM_REGION4_ADDR_START_H_S)
-#define CPU_APM_REGION4_ADDR_START_H_V  0x00001FFFU
-#define CPU_APM_REGION4_ADDR_START_H_S  19
-
-/** CPU_APM_REGION4_ADDR_END_REG register
- *  Region address register
- */
-#define CPU_APM_REGION4_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x38)
-/** CPU_APM_REGION4_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
- *  Low 12 bit, end address of region 4.
- */
-#define CPU_APM_REGION4_ADDR_END_L    0x00000FFFU
-#define CPU_APM_REGION4_ADDR_END_L_M  (CPU_APM_REGION4_ADDR_END_L_V << CPU_APM_REGION4_ADDR_END_L_S)
-#define CPU_APM_REGION4_ADDR_END_L_V  0x00000FFFU
-#define CPU_APM_REGION4_ADDR_END_L_S  0
-/** CPU_APM_REGION4_ADDR_END : R/W; bitpos: [18:12]; default: 127;
- *  Configures end address of region 4.
- */
-#define CPU_APM_REGION4_ADDR_END    0x0000007FU
-#define CPU_APM_REGION4_ADDR_END_M  (CPU_APM_REGION4_ADDR_END_V << CPU_APM_REGION4_ADDR_END_S)
-#define CPU_APM_REGION4_ADDR_END_V  0x0000007FU
-#define CPU_APM_REGION4_ADDR_END_S  12
-/** CPU_APM_REGION4_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  end address of region 4.
- */
-#define CPU_APM_REGION4_ADDR_END_H    0x00001FFFU
-#define CPU_APM_REGION4_ADDR_END_H_M  (CPU_APM_REGION4_ADDR_END_H_V << CPU_APM_REGION4_ADDR_END_H_S)
-#define CPU_APM_REGION4_ADDR_END_H_V  0x00001FFFU
-#define CPU_APM_REGION4_ADDR_END_H_S  19
-
-/** CPU_APM_REGION4_ATTR_REG register
- *  Region access authority attribute register
- */
-#define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_APM_BASE + 0x3c)
-/** CPU_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0;
- *  Configures the execution authority of REE_MODE 0 in region 4.
- */
-#define CPU_APM_REGION4_R0_X    (BIT(0))
-#define CPU_APM_REGION4_R0_X_M  (CPU_APM_REGION4_R0_X_V << CPU_APM_REGION4_R0_X_S)
-#define CPU_APM_REGION4_R0_X_V  0x00000001U
-#define CPU_APM_REGION4_R0_X_S  0
-/** CPU_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0;
- *  Configures the write authority of REE_MODE 0 in region 4.
- */
-#define CPU_APM_REGION4_R0_W    (BIT(1))
-#define CPU_APM_REGION4_R0_W_M  (CPU_APM_REGION4_R0_W_V << CPU_APM_REGION4_R0_W_S)
-#define CPU_APM_REGION4_R0_W_V  0x00000001U
-#define CPU_APM_REGION4_R0_W_S  1
-/** CPU_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0;
- *  Configures the read authority of REE_MODE 0 in region 4.
- */
-#define CPU_APM_REGION4_R0_R    (BIT(2))
-#define CPU_APM_REGION4_R0_R_M  (CPU_APM_REGION4_R0_R_V << CPU_APM_REGION4_R0_R_S)
-#define CPU_APM_REGION4_R0_R_V  0x00000001U
-#define CPU_APM_REGION4_R0_R_S  2
-/** CPU_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0;
- *  Configures the execution authority of REE_MODE 1 in region 4.
- */
-#define CPU_APM_REGION4_R1_X    (BIT(4))
-#define CPU_APM_REGION4_R1_X_M  (CPU_APM_REGION4_R1_X_V << CPU_APM_REGION4_R1_X_S)
-#define CPU_APM_REGION4_R1_X_V  0x00000001U
-#define CPU_APM_REGION4_R1_X_S  4
-/** CPU_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0;
- *  Configures the write authority of REE_MODE 1 in region 4.
- */
-#define CPU_APM_REGION4_R1_W    (BIT(5))
-#define CPU_APM_REGION4_R1_W_M  (CPU_APM_REGION4_R1_W_V << CPU_APM_REGION4_R1_W_S)
-#define CPU_APM_REGION4_R1_W_V  0x00000001U
-#define CPU_APM_REGION4_R1_W_S  5
-/** CPU_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0;
- *  Configures the read authority of REE_MODE 1 in region 4.
- */
-#define CPU_APM_REGION4_R1_R    (BIT(6))
-#define CPU_APM_REGION4_R1_R_M  (CPU_APM_REGION4_R1_R_V << CPU_APM_REGION4_R1_R_S)
-#define CPU_APM_REGION4_R1_R_V  0x00000001U
-#define CPU_APM_REGION4_R1_R_S  6
-/** CPU_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0;
- *  Configures the execution authority of REE_MODE 2 in region 4.
- */
-#define CPU_APM_REGION4_R2_X    (BIT(8))
-#define CPU_APM_REGION4_R2_X_M  (CPU_APM_REGION4_R2_X_V << CPU_APM_REGION4_R2_X_S)
-#define CPU_APM_REGION4_R2_X_V  0x00000001U
-#define CPU_APM_REGION4_R2_X_S  8
-/** CPU_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0;
- *  Configures the write authority of REE_MODE 2 in region 4.
- */
-#define CPU_APM_REGION4_R2_W    (BIT(9))
-#define CPU_APM_REGION4_R2_W_M  (CPU_APM_REGION4_R2_W_V << CPU_APM_REGION4_R2_W_S)
-#define CPU_APM_REGION4_R2_W_V  0x00000001U
-#define CPU_APM_REGION4_R2_W_S  9
-/** CPU_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0;
- *  Configures the read authority of REE_MODE 2 in region 4.
- */
-#define CPU_APM_REGION4_R2_R    (BIT(10))
-#define CPU_APM_REGION4_R2_R_M  (CPU_APM_REGION4_R2_R_V << CPU_APM_REGION4_R2_R_S)
-#define CPU_APM_REGION4_R2_R_V  0x00000001U
-#define CPU_APM_REGION4_R2_R_S  10
-/** CPU_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region0 configuration
- */
-#define CPU_APM_REGION4_LOCK    (BIT(11))
-#define CPU_APM_REGION4_LOCK_M  (CPU_APM_REGION4_LOCK_V << CPU_APM_REGION4_LOCK_S)
-#define CPU_APM_REGION4_LOCK_V  0x00000001U
-#define CPU_APM_REGION4_LOCK_S  11
-
-/** CPU_APM_REGION5_ADDR_START_REG register
- *  Region address register
- */
-#define CPU_APM_REGION5_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x40)
-/** CPU_APM_REGION5_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
- *  Low 12 bit, start address of region 5.
- */
-#define CPU_APM_REGION5_ADDR_START_L    0x00000FFFU
-#define CPU_APM_REGION5_ADDR_START_L_M  (CPU_APM_REGION5_ADDR_START_L_V << CPU_APM_REGION5_ADDR_START_L_S)
-#define CPU_APM_REGION5_ADDR_START_L_V  0x00000FFFU
-#define CPU_APM_REGION5_ADDR_START_L_S  0
-/** CPU_APM_REGION5_ADDR_START : R/W; bitpos: [18:12]; default: 0;
- *  Configures start address of region 5.
- */
-#define CPU_APM_REGION5_ADDR_START    0x0000007FU
-#define CPU_APM_REGION5_ADDR_START_M  (CPU_APM_REGION5_ADDR_START_V << CPU_APM_REGION5_ADDR_START_S)
-#define CPU_APM_REGION5_ADDR_START_V  0x0000007FU
-#define CPU_APM_REGION5_ADDR_START_S  12
-/** CPU_APM_REGION5_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  start address of region 5.
- */
-#define CPU_APM_REGION5_ADDR_START_H    0x00001FFFU
-#define CPU_APM_REGION5_ADDR_START_H_M  (CPU_APM_REGION5_ADDR_START_H_V << CPU_APM_REGION5_ADDR_START_H_S)
-#define CPU_APM_REGION5_ADDR_START_H_V  0x00001FFFU
-#define CPU_APM_REGION5_ADDR_START_H_S  19
-
-/** CPU_APM_REGION5_ADDR_END_REG register
- *  Region address register
- */
-#define CPU_APM_REGION5_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x44)
-/** CPU_APM_REGION5_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
- *  Low 12 bit, end address of region 5.
- */
-#define CPU_APM_REGION5_ADDR_END_L    0x00000FFFU
-#define CPU_APM_REGION5_ADDR_END_L_M  (CPU_APM_REGION5_ADDR_END_L_V << CPU_APM_REGION5_ADDR_END_L_S)
-#define CPU_APM_REGION5_ADDR_END_L_V  0x00000FFFU
-#define CPU_APM_REGION5_ADDR_END_L_S  0
-/** CPU_APM_REGION5_ADDR_END : R/W; bitpos: [18:12]; default: 127;
- *  Configures end address of region 5.
- */
-#define CPU_APM_REGION5_ADDR_END    0x0000007FU
-#define CPU_APM_REGION5_ADDR_END_M  (CPU_APM_REGION5_ADDR_END_V << CPU_APM_REGION5_ADDR_END_S)
-#define CPU_APM_REGION5_ADDR_END_V  0x0000007FU
-#define CPU_APM_REGION5_ADDR_END_S  12
-/** CPU_APM_REGION5_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  end address of region 5.
- */
-#define CPU_APM_REGION5_ADDR_END_H    0x00001FFFU
-#define CPU_APM_REGION5_ADDR_END_H_M  (CPU_APM_REGION5_ADDR_END_H_V << CPU_APM_REGION5_ADDR_END_H_S)
-#define CPU_APM_REGION5_ADDR_END_H_V  0x00001FFFU
-#define CPU_APM_REGION5_ADDR_END_H_S  19
-
-/** CPU_APM_REGION5_ATTR_REG register
- *  Region access authority attribute register
- */
-#define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_APM_BASE + 0x48)
-/** CPU_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0;
- *  Configures the execution authority of REE_MODE 0 in region 5.
- */
-#define CPU_APM_REGION5_R0_X    (BIT(0))
-#define CPU_APM_REGION5_R0_X_M  (CPU_APM_REGION5_R0_X_V << CPU_APM_REGION5_R0_X_S)
-#define CPU_APM_REGION5_R0_X_V  0x00000001U
-#define CPU_APM_REGION5_R0_X_S  0
-/** CPU_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0;
- *  Configures the write authority of REE_MODE 0 in region 5.
- */
-#define CPU_APM_REGION5_R0_W    (BIT(1))
-#define CPU_APM_REGION5_R0_W_M  (CPU_APM_REGION5_R0_W_V << CPU_APM_REGION5_R0_W_S)
-#define CPU_APM_REGION5_R0_W_V  0x00000001U
-#define CPU_APM_REGION5_R0_W_S  1
-/** CPU_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0;
- *  Configures the read authority of REE_MODE 0 in region 5.
- */
-#define CPU_APM_REGION5_R0_R    (BIT(2))
-#define CPU_APM_REGION5_R0_R_M  (CPU_APM_REGION5_R0_R_V << CPU_APM_REGION5_R0_R_S)
-#define CPU_APM_REGION5_R0_R_V  0x00000001U
-#define CPU_APM_REGION5_R0_R_S  2
-/** CPU_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0;
- *  Configures the execution authority of REE_MODE 1 in region 5.
- */
-#define CPU_APM_REGION5_R1_X    (BIT(4))
-#define CPU_APM_REGION5_R1_X_M  (CPU_APM_REGION5_R1_X_V << CPU_APM_REGION5_R1_X_S)
-#define CPU_APM_REGION5_R1_X_V  0x00000001U
-#define CPU_APM_REGION5_R1_X_S  4
-/** CPU_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0;
- *  Configures the write authority of REE_MODE 1 in region 5.
- */
-#define CPU_APM_REGION5_R1_W    (BIT(5))
-#define CPU_APM_REGION5_R1_W_M  (CPU_APM_REGION5_R1_W_V << CPU_APM_REGION5_R1_W_S)
-#define CPU_APM_REGION5_R1_W_V  0x00000001U
-#define CPU_APM_REGION5_R1_W_S  5
-/** CPU_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0;
- *  Configures the read authority of REE_MODE 1 in region 5.
- */
-#define CPU_APM_REGION5_R1_R    (BIT(6))
-#define CPU_APM_REGION5_R1_R_M  (CPU_APM_REGION5_R1_R_V << CPU_APM_REGION5_R1_R_S)
-#define CPU_APM_REGION5_R1_R_V  0x00000001U
-#define CPU_APM_REGION5_R1_R_S  6
-/** CPU_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0;
- *  Configures the execution authority of REE_MODE 2 in region 5.
- */
-#define CPU_APM_REGION5_R2_X    (BIT(8))
-#define CPU_APM_REGION5_R2_X_M  (CPU_APM_REGION5_R2_X_V << CPU_APM_REGION5_R2_X_S)
-#define CPU_APM_REGION5_R2_X_V  0x00000001U
-#define CPU_APM_REGION5_R2_X_S  8
-/** CPU_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0;
- *  Configures the write authority of REE_MODE 2 in region 5.
- */
-#define CPU_APM_REGION5_R2_W    (BIT(9))
-#define CPU_APM_REGION5_R2_W_M  (CPU_APM_REGION5_R2_W_V << CPU_APM_REGION5_R2_W_S)
-#define CPU_APM_REGION5_R2_W_V  0x00000001U
-#define CPU_APM_REGION5_R2_W_S  9
-/** CPU_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0;
- *  Configures the read authority of REE_MODE 2 in region 5.
- */
-#define CPU_APM_REGION5_R2_R    (BIT(10))
-#define CPU_APM_REGION5_R2_R_M  (CPU_APM_REGION5_R2_R_V << CPU_APM_REGION5_R2_R_S)
-#define CPU_APM_REGION5_R2_R_V  0x00000001U
-#define CPU_APM_REGION5_R2_R_S  10
-/** CPU_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region0 configuration
- */
-#define CPU_APM_REGION5_LOCK    (BIT(11))
-#define CPU_APM_REGION5_LOCK_M  (CPU_APM_REGION5_LOCK_V << CPU_APM_REGION5_LOCK_S)
-#define CPU_APM_REGION5_LOCK_V  0x00000001U
-#define CPU_APM_REGION5_LOCK_S  11
-
-/** CPU_APM_REGION6_ADDR_START_REG register
- *  Region address register
- */
-#define CPU_APM_REGION6_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x4c)
-/** CPU_APM_REGION6_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
- *  Low 12 bit, start address of region 6.
- */
-#define CPU_APM_REGION6_ADDR_START_L    0x00000FFFU
-#define CPU_APM_REGION6_ADDR_START_L_M  (CPU_APM_REGION6_ADDR_START_L_V << CPU_APM_REGION6_ADDR_START_L_S)
-#define CPU_APM_REGION6_ADDR_START_L_V  0x00000FFFU
-#define CPU_APM_REGION6_ADDR_START_L_S  0
-/** CPU_APM_REGION6_ADDR_START : R/W; bitpos: [18:12]; default: 0;
- *  Configures start address of region 6.
- */
-#define CPU_APM_REGION6_ADDR_START    0x0000007FU
-#define CPU_APM_REGION6_ADDR_START_M  (CPU_APM_REGION6_ADDR_START_V << CPU_APM_REGION6_ADDR_START_S)
-#define CPU_APM_REGION6_ADDR_START_V  0x0000007FU
-#define CPU_APM_REGION6_ADDR_START_S  12
-/** CPU_APM_REGION6_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  start address of region 6.
- */
-#define CPU_APM_REGION6_ADDR_START_H    0x00001FFFU
-#define CPU_APM_REGION6_ADDR_START_H_M  (CPU_APM_REGION6_ADDR_START_H_V << CPU_APM_REGION6_ADDR_START_H_S)
-#define CPU_APM_REGION6_ADDR_START_H_V  0x00001FFFU
-#define CPU_APM_REGION6_ADDR_START_H_S  19
-
-/** CPU_APM_REGION6_ADDR_END_REG register
- *  Region address register
- */
-#define CPU_APM_REGION6_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x50)
-/** CPU_APM_REGION6_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
- *  Low 12 bit, end address of region 6.
- */
-#define CPU_APM_REGION6_ADDR_END_L    0x00000FFFU
-#define CPU_APM_REGION6_ADDR_END_L_M  (CPU_APM_REGION6_ADDR_END_L_V << CPU_APM_REGION6_ADDR_END_L_S)
-#define CPU_APM_REGION6_ADDR_END_L_V  0x00000FFFU
-#define CPU_APM_REGION6_ADDR_END_L_S  0
-/** CPU_APM_REGION6_ADDR_END : R/W; bitpos: [18:12]; default: 127;
- *  Configures end address of region 6.
- */
-#define CPU_APM_REGION6_ADDR_END    0x0000007FU
-#define CPU_APM_REGION6_ADDR_END_M  (CPU_APM_REGION6_ADDR_END_V << CPU_APM_REGION6_ADDR_END_S)
-#define CPU_APM_REGION6_ADDR_END_V  0x0000007FU
-#define CPU_APM_REGION6_ADDR_END_S  12
-/** CPU_APM_REGION6_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  end address of region 6.
- */
-#define CPU_APM_REGION6_ADDR_END_H    0x00001FFFU
-#define CPU_APM_REGION6_ADDR_END_H_M  (CPU_APM_REGION6_ADDR_END_H_V << CPU_APM_REGION6_ADDR_END_H_S)
-#define CPU_APM_REGION6_ADDR_END_H_V  0x00001FFFU
-#define CPU_APM_REGION6_ADDR_END_H_S  19
-
-/** CPU_APM_REGION6_ATTR_REG register
- *  Region access authority attribute register
- */
-#define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_APM_BASE + 0x54)
-/** CPU_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0;
- *  Configures the execution authority of REE_MODE 0 in region 6.
- */
-#define CPU_APM_REGION6_R0_X    (BIT(0))
-#define CPU_APM_REGION6_R0_X_M  (CPU_APM_REGION6_R0_X_V << CPU_APM_REGION6_R0_X_S)
-#define CPU_APM_REGION6_R0_X_V  0x00000001U
-#define CPU_APM_REGION6_R0_X_S  0
-/** CPU_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0;
- *  Configures the write authority of REE_MODE 0 in region 6.
- */
-#define CPU_APM_REGION6_R0_W    (BIT(1))
-#define CPU_APM_REGION6_R0_W_M  (CPU_APM_REGION6_R0_W_V << CPU_APM_REGION6_R0_W_S)
-#define CPU_APM_REGION6_R0_W_V  0x00000001U
-#define CPU_APM_REGION6_R0_W_S  1
-/** CPU_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0;
- *  Configures the read authority of REE_MODE 0 in region 6.
- */
-#define CPU_APM_REGION6_R0_R    (BIT(2))
-#define CPU_APM_REGION6_R0_R_M  (CPU_APM_REGION6_R0_R_V << CPU_APM_REGION6_R0_R_S)
-#define CPU_APM_REGION6_R0_R_V  0x00000001U
-#define CPU_APM_REGION6_R0_R_S  2
-/** CPU_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0;
- *  Configures the execution authority of REE_MODE 1 in region 6.
- */
-#define CPU_APM_REGION6_R1_X    (BIT(4))
-#define CPU_APM_REGION6_R1_X_M  (CPU_APM_REGION6_R1_X_V << CPU_APM_REGION6_R1_X_S)
-#define CPU_APM_REGION6_R1_X_V  0x00000001U
-#define CPU_APM_REGION6_R1_X_S  4
-/** CPU_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0;
- *  Configures the write authority of REE_MODE 1 in region 6.
- */
-#define CPU_APM_REGION6_R1_W    (BIT(5))
-#define CPU_APM_REGION6_R1_W_M  (CPU_APM_REGION6_R1_W_V << CPU_APM_REGION6_R1_W_S)
-#define CPU_APM_REGION6_R1_W_V  0x00000001U
-#define CPU_APM_REGION6_R1_W_S  5
-/** CPU_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0;
- *  Configures the read authority of REE_MODE 1 in region 6.
- */
-#define CPU_APM_REGION6_R1_R    (BIT(6))
-#define CPU_APM_REGION6_R1_R_M  (CPU_APM_REGION6_R1_R_V << CPU_APM_REGION6_R1_R_S)
-#define CPU_APM_REGION6_R1_R_V  0x00000001U
-#define CPU_APM_REGION6_R1_R_S  6
-/** CPU_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0;
- *  Configures the execution authority of REE_MODE 2 in region 6.
- */
-#define CPU_APM_REGION6_R2_X    (BIT(8))
-#define CPU_APM_REGION6_R2_X_M  (CPU_APM_REGION6_R2_X_V << CPU_APM_REGION6_R2_X_S)
-#define CPU_APM_REGION6_R2_X_V  0x00000001U
-#define CPU_APM_REGION6_R2_X_S  8
-/** CPU_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0;
- *  Configures the write authority of REE_MODE 2 in region 6.
- */
-#define CPU_APM_REGION6_R2_W    (BIT(9))
-#define CPU_APM_REGION6_R2_W_M  (CPU_APM_REGION6_R2_W_V << CPU_APM_REGION6_R2_W_S)
-#define CPU_APM_REGION6_R2_W_V  0x00000001U
-#define CPU_APM_REGION6_R2_W_S  9
-/** CPU_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0;
- *  Configures the read authority of REE_MODE 2 in region 6.
- */
-#define CPU_APM_REGION6_R2_R    (BIT(10))
-#define CPU_APM_REGION6_R2_R_M  (CPU_APM_REGION6_R2_R_V << CPU_APM_REGION6_R2_R_S)
-#define CPU_APM_REGION6_R2_R_V  0x00000001U
-#define CPU_APM_REGION6_R2_R_S  10
-/** CPU_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region0 configuration
- */
-#define CPU_APM_REGION6_LOCK    (BIT(11))
-#define CPU_APM_REGION6_LOCK_M  (CPU_APM_REGION6_LOCK_V << CPU_APM_REGION6_LOCK_S)
-#define CPU_APM_REGION6_LOCK_V  0x00000001U
-#define CPU_APM_REGION6_LOCK_S  11
-
-/** CPU_APM_REGION7_ADDR_START_REG register
- *  Region address register
- */
-#define CPU_APM_REGION7_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x58)
-/** CPU_APM_REGION7_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
- *  Low 12 bit, start address of region 7.
- */
-#define CPU_APM_REGION7_ADDR_START_L    0x00000FFFU
-#define CPU_APM_REGION7_ADDR_START_L_M  (CPU_APM_REGION7_ADDR_START_L_V << CPU_APM_REGION7_ADDR_START_L_S)
-#define CPU_APM_REGION7_ADDR_START_L_V  0x00000FFFU
-#define CPU_APM_REGION7_ADDR_START_L_S  0
-/** CPU_APM_REGION7_ADDR_START : R/W; bitpos: [18:12]; default: 0;
- *  Configures start address of region 7.
- */
-#define CPU_APM_REGION7_ADDR_START    0x0000007FU
-#define CPU_APM_REGION7_ADDR_START_M  (CPU_APM_REGION7_ADDR_START_V << CPU_APM_REGION7_ADDR_START_S)
-#define CPU_APM_REGION7_ADDR_START_V  0x0000007FU
-#define CPU_APM_REGION7_ADDR_START_S  12
-/** CPU_APM_REGION7_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  start address of region 7.
- */
-#define CPU_APM_REGION7_ADDR_START_H    0x00001FFFU
-#define CPU_APM_REGION7_ADDR_START_H_M  (CPU_APM_REGION7_ADDR_START_H_V << CPU_APM_REGION7_ADDR_START_H_S)
-#define CPU_APM_REGION7_ADDR_START_H_V  0x00001FFFU
-#define CPU_APM_REGION7_ADDR_START_H_S  19
-
-/** CPU_APM_REGION7_ADDR_END_REG register
- *  Region address register
- */
-#define CPU_APM_REGION7_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x5c)
-/** CPU_APM_REGION7_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
- *  Low 12 bit, end address of region 7.
- */
-#define CPU_APM_REGION7_ADDR_END_L    0x00000FFFU
-#define CPU_APM_REGION7_ADDR_END_L_M  (CPU_APM_REGION7_ADDR_END_L_V << CPU_APM_REGION7_ADDR_END_L_S)
-#define CPU_APM_REGION7_ADDR_END_L_V  0x00000FFFU
-#define CPU_APM_REGION7_ADDR_END_L_S  0
-/** CPU_APM_REGION7_ADDR_END : R/W; bitpos: [18:12]; default: 127;
- *  Configures end address of region 7.
- */
-#define CPU_APM_REGION7_ADDR_END    0x0000007FU
-#define CPU_APM_REGION7_ADDR_END_M  (CPU_APM_REGION7_ADDR_END_V << CPU_APM_REGION7_ADDR_END_S)
-#define CPU_APM_REGION7_ADDR_END_V  0x0000007FU
-#define CPU_APM_REGION7_ADDR_END_S  12
-/** CPU_APM_REGION7_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064;
- *  High 13 bit,  end address of region 7.
- */
-#define CPU_APM_REGION7_ADDR_END_H    0x00001FFFU
-#define CPU_APM_REGION7_ADDR_END_H_M  (CPU_APM_REGION7_ADDR_END_H_V << CPU_APM_REGION7_ADDR_END_H_S)
-#define CPU_APM_REGION7_ADDR_END_H_V  0x00001FFFU
-#define CPU_APM_REGION7_ADDR_END_H_S  19
-
-/** CPU_APM_REGION7_ATTR_REG register
- *  Region access authority attribute register
- */
-#define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_APM_BASE + 0x60)
-/** CPU_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0;
- *  Configures the execution authority of REE_MODE 0 in region 7.
- */
-#define CPU_APM_REGION7_R0_X    (BIT(0))
-#define CPU_APM_REGION7_R0_X_M  (CPU_APM_REGION7_R0_X_V << CPU_APM_REGION7_R0_X_S)
-#define CPU_APM_REGION7_R0_X_V  0x00000001U
-#define CPU_APM_REGION7_R0_X_S  0
-/** CPU_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0;
- *  Configures the write authority of REE_MODE 0 in region 7.
- */
-#define CPU_APM_REGION7_R0_W    (BIT(1))
-#define CPU_APM_REGION7_R0_W_M  (CPU_APM_REGION7_R0_W_V << CPU_APM_REGION7_R0_W_S)
-#define CPU_APM_REGION7_R0_W_V  0x00000001U
-#define CPU_APM_REGION7_R0_W_S  1
-/** CPU_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0;
- *  Configures the read authority of REE_MODE 0 in region 7.
- */
-#define CPU_APM_REGION7_R0_R    (BIT(2))
-#define CPU_APM_REGION7_R0_R_M  (CPU_APM_REGION7_R0_R_V << CPU_APM_REGION7_R0_R_S)
-#define CPU_APM_REGION7_R0_R_V  0x00000001U
-#define CPU_APM_REGION7_R0_R_S  2
-/** CPU_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0;
- *  Configures the execution authority of REE_MODE 1 in region 7.
- */
-#define CPU_APM_REGION7_R1_X    (BIT(4))
-#define CPU_APM_REGION7_R1_X_M  (CPU_APM_REGION7_R1_X_V << CPU_APM_REGION7_R1_X_S)
-#define CPU_APM_REGION7_R1_X_V  0x00000001U
-#define CPU_APM_REGION7_R1_X_S  4
-/** CPU_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0;
- *  Configures the write authority of REE_MODE 1 in region 7.
- */
-#define CPU_APM_REGION7_R1_W    (BIT(5))
-#define CPU_APM_REGION7_R1_W_M  (CPU_APM_REGION7_R1_W_V << CPU_APM_REGION7_R1_W_S)
-#define CPU_APM_REGION7_R1_W_V  0x00000001U
-#define CPU_APM_REGION7_R1_W_S  5
-/** CPU_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0;
- *  Configures the read authority of REE_MODE 1 in region 7.
- */
-#define CPU_APM_REGION7_R1_R    (BIT(6))
-#define CPU_APM_REGION7_R1_R_M  (CPU_APM_REGION7_R1_R_V << CPU_APM_REGION7_R1_R_S)
-#define CPU_APM_REGION7_R1_R_V  0x00000001U
-#define CPU_APM_REGION7_R1_R_S  6
-/** CPU_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0;
- *  Configures the execution authority of REE_MODE 2 in region 7.
- */
-#define CPU_APM_REGION7_R2_X    (BIT(8))
-#define CPU_APM_REGION7_R2_X_M  (CPU_APM_REGION7_R2_X_V << CPU_APM_REGION7_R2_X_S)
-#define CPU_APM_REGION7_R2_X_V  0x00000001U
-#define CPU_APM_REGION7_R2_X_S  8
-/** CPU_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0;
- *  Configures the write authority of REE_MODE 2 in region 7.
- */
-#define CPU_APM_REGION7_R2_W    (BIT(9))
-#define CPU_APM_REGION7_R2_W_M  (CPU_APM_REGION7_R2_W_V << CPU_APM_REGION7_R2_W_S)
-#define CPU_APM_REGION7_R2_W_V  0x00000001U
-#define CPU_APM_REGION7_R2_W_S  9
-/** CPU_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0;
- *  Configures the read authority of REE_MODE 2 in region 7.
- */
-#define CPU_APM_REGION7_R2_R    (BIT(10))
-#define CPU_APM_REGION7_R2_R_M  (CPU_APM_REGION7_R2_R_V << CPU_APM_REGION7_R2_R_S)
-#define CPU_APM_REGION7_R2_R_V  0x00000001U
-#define CPU_APM_REGION7_R2_R_S  10
-/** CPU_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region0 configuration
- */
-#define CPU_APM_REGION7_LOCK    (BIT(11))
-#define CPU_APM_REGION7_LOCK_M  (CPU_APM_REGION7_LOCK_V << CPU_APM_REGION7_LOCK_S)
-#define CPU_APM_REGION7_LOCK_V  0x00000001U
-#define CPU_APM_REGION7_LOCK_S  11
-
-/** CPU_APM_FUNC_CTRL_REG register
- *  APM function control register
- */
-#define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_APM_BASE + 0xc4)
-/** CPU_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1;
- *  PMS M0 function enable
- */
-#define CPU_APM_M0_FUNC_EN    (BIT(0))
-#define CPU_APM_M0_FUNC_EN_M  (CPU_APM_M0_FUNC_EN_V << CPU_APM_M0_FUNC_EN_S)
-#define CPU_APM_M0_FUNC_EN_V  0x00000001U
-#define CPU_APM_M0_FUNC_EN_S  0
-/** CPU_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1;
- *  PMS M1 function enable
- */
-#define CPU_APM_M1_FUNC_EN    (BIT(1))
-#define CPU_APM_M1_FUNC_EN_M  (CPU_APM_M1_FUNC_EN_V << CPU_APM_M1_FUNC_EN_S)
-#define CPU_APM_M1_FUNC_EN_V  0x00000001U
-#define CPU_APM_M1_FUNC_EN_S  1
-/** CPU_APM_M2_FUNC_EN : R/W; bitpos: [2]; default: 1;
- *  PMS M2 function enable
- */
-#define CPU_APM_M2_FUNC_EN    (BIT(2))
-#define CPU_APM_M2_FUNC_EN_M  (CPU_APM_M2_FUNC_EN_V << CPU_APM_M2_FUNC_EN_S)
-#define CPU_APM_M2_FUNC_EN_V  0x00000001U
-#define CPU_APM_M2_FUNC_EN_S  2
-/** CPU_APM_M3_FUNC_EN : R/W; bitpos: [3]; default: 1;
- *  PMS M3 function enable
- */
-#define CPU_APM_M3_FUNC_EN    (BIT(3))
-#define CPU_APM_M3_FUNC_EN_M  (CPU_APM_M3_FUNC_EN_V << CPU_APM_M3_FUNC_EN_S)
-#define CPU_APM_M3_FUNC_EN_V  0x00000001U
-#define CPU_APM_M3_FUNC_EN_S  3
-
-/** CPU_APM_M0_STATUS_REG register
- *  M0 status register
- */
-#define CPU_APM_M0_STATUS_REG (DR_REG_CPU_APM_BASE + 0xc8)
-/** CPU_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Represents exception status.
- *  bit0: 1 represents authority_exception
- *  bit1: 1 represents space_exception
- */
-#define CPU_APM_M0_EXCEPTION_STATUS    0x00000003U
-#define CPU_APM_M0_EXCEPTION_STATUS_M  (CPU_APM_M0_EXCEPTION_STATUS_V << CPU_APM_M0_EXCEPTION_STATUS_S)
-#define CPU_APM_M0_EXCEPTION_STATUS_V  0x00000003U
-#define CPU_APM_M0_EXCEPTION_STATUS_S  0
-
-/** CPU_APM_M0_STATUS_CLR_REG register
- *  M0 status clear register
- */
-#define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xcc)
-/** CPU_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Configures to clear exception status.
- */
-#define CPU_APM_M0_EXCEPTION_STATUS_CLR    (BIT(0))
-#define CPU_APM_M0_EXCEPTION_STATUS_CLR_M  (CPU_APM_M0_EXCEPTION_STATUS_CLR_V << CPU_APM_M0_EXCEPTION_STATUS_CLR_S)
-#define CPU_APM_M0_EXCEPTION_STATUS_CLR_V  0x00000001U
-#define CPU_APM_M0_EXCEPTION_STATUS_CLR_S  0
-
-/** CPU_APM_M0_EXCEPTION_INFO0_REG register
- *  M0 exception_info0 register
- */
-#define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xd0)
-/** CPU_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
- *  Represents exception region.
- */
-#define CPU_APM_M0_EXCEPTION_REGION    0x0000FFFFU
-#define CPU_APM_M0_EXCEPTION_REGION_M  (CPU_APM_M0_EXCEPTION_REGION_V << CPU_APM_M0_EXCEPTION_REGION_S)
-#define CPU_APM_M0_EXCEPTION_REGION_V  0x0000FFFFU
-#define CPU_APM_M0_EXCEPTION_REGION_S  0
-/** CPU_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Represents exception mode.
- */
-#define CPU_APM_M0_EXCEPTION_MODE    0x00000003U
-#define CPU_APM_M0_EXCEPTION_MODE_M  (CPU_APM_M0_EXCEPTION_MODE_V << CPU_APM_M0_EXCEPTION_MODE_S)
-#define CPU_APM_M0_EXCEPTION_MODE_V  0x00000003U
-#define CPU_APM_M0_EXCEPTION_MODE_S  16
-/** CPU_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Represents exception id information.
- */
-#define CPU_APM_M0_EXCEPTION_ID    0x0000001FU
-#define CPU_APM_M0_EXCEPTION_ID_M  (CPU_APM_M0_EXCEPTION_ID_V << CPU_APM_M0_EXCEPTION_ID_S)
-#define CPU_APM_M0_EXCEPTION_ID_V  0x0000001FU
-#define CPU_APM_M0_EXCEPTION_ID_S  18
-
-/** CPU_APM_M0_EXCEPTION_INFO1_REG register
- *  M0 exception_info1 register
- */
-#define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xd4)
-/** CPU_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Represents exception addr.
- */
-#define CPU_APM_M0_EXCEPTION_ADDR    0xFFFFFFFFU
-#define CPU_APM_M0_EXCEPTION_ADDR_M  (CPU_APM_M0_EXCEPTION_ADDR_V << CPU_APM_M0_EXCEPTION_ADDR_S)
-#define CPU_APM_M0_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define CPU_APM_M0_EXCEPTION_ADDR_S  0
-
-/** CPU_APM_M1_STATUS_REG register
- *  M1 status register
- */
-#define CPU_APM_M1_STATUS_REG (DR_REG_CPU_APM_BASE + 0xd8)
-/** CPU_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Represents exception status.
- *  bit0: 1 represents authority_exception
- *  bit1: 1 represents space_exception
- */
-#define CPU_APM_M1_EXCEPTION_STATUS    0x00000003U
-#define CPU_APM_M1_EXCEPTION_STATUS_M  (CPU_APM_M1_EXCEPTION_STATUS_V << CPU_APM_M1_EXCEPTION_STATUS_S)
-#define CPU_APM_M1_EXCEPTION_STATUS_V  0x00000003U
-#define CPU_APM_M1_EXCEPTION_STATUS_S  0
-
-/** CPU_APM_M1_STATUS_CLR_REG register
- *  M1 status clear register
- */
-#define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xdc)
-/** CPU_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Configures to clear exception status.
- */
-#define CPU_APM_M1_EXCEPTION_STATUS_CLR    (BIT(0))
-#define CPU_APM_M1_EXCEPTION_STATUS_CLR_M  (CPU_APM_M1_EXCEPTION_STATUS_CLR_V << CPU_APM_M1_EXCEPTION_STATUS_CLR_S)
-#define CPU_APM_M1_EXCEPTION_STATUS_CLR_V  0x00000001U
-#define CPU_APM_M1_EXCEPTION_STATUS_CLR_S  0
-
-/** CPU_APM_M1_EXCEPTION_INFO0_REG register
- *  M1 exception_info0 register
- */
-#define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xe0)
-/** CPU_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
- *  Represents exception region.
- */
-#define CPU_APM_M1_EXCEPTION_REGION    0x0000FFFFU
-#define CPU_APM_M1_EXCEPTION_REGION_M  (CPU_APM_M1_EXCEPTION_REGION_V << CPU_APM_M1_EXCEPTION_REGION_S)
-#define CPU_APM_M1_EXCEPTION_REGION_V  0x0000FFFFU
-#define CPU_APM_M1_EXCEPTION_REGION_S  0
-/** CPU_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Represents exception mode.
- */
-#define CPU_APM_M1_EXCEPTION_MODE    0x00000003U
-#define CPU_APM_M1_EXCEPTION_MODE_M  (CPU_APM_M1_EXCEPTION_MODE_V << CPU_APM_M1_EXCEPTION_MODE_S)
-#define CPU_APM_M1_EXCEPTION_MODE_V  0x00000003U
-#define CPU_APM_M1_EXCEPTION_MODE_S  16
-/** CPU_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Represents exception id information.
- */
-#define CPU_APM_M1_EXCEPTION_ID    0x0000001FU
-#define CPU_APM_M1_EXCEPTION_ID_M  (CPU_APM_M1_EXCEPTION_ID_V << CPU_APM_M1_EXCEPTION_ID_S)
-#define CPU_APM_M1_EXCEPTION_ID_V  0x0000001FU
-#define CPU_APM_M1_EXCEPTION_ID_S  18
-
-/** CPU_APM_M1_EXCEPTION_INFO1_REG register
- *  M1 exception_info1 register
- */
-#define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xe4)
-/** CPU_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Represents exception addr.
- */
-#define CPU_APM_M1_EXCEPTION_ADDR    0xFFFFFFFFU
-#define CPU_APM_M1_EXCEPTION_ADDR_M  (CPU_APM_M1_EXCEPTION_ADDR_V << CPU_APM_M1_EXCEPTION_ADDR_S)
-#define CPU_APM_M1_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define CPU_APM_M1_EXCEPTION_ADDR_S  0
-
-/** CPU_APM_M2_STATUS_REG register
- *  M2 status register
- */
-#define CPU_APM_M2_STATUS_REG (DR_REG_CPU_APM_BASE + 0xe8)
-/** CPU_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Represents exception status.
- *  bit0: 1 represents authority_exception
- *  bit1: 1 represents space_exception
- */
-#define CPU_APM_M2_EXCEPTION_STATUS    0x00000003U
-#define CPU_APM_M2_EXCEPTION_STATUS_M  (CPU_APM_M2_EXCEPTION_STATUS_V << CPU_APM_M2_EXCEPTION_STATUS_S)
-#define CPU_APM_M2_EXCEPTION_STATUS_V  0x00000003U
-#define CPU_APM_M2_EXCEPTION_STATUS_S  0
-
-/** CPU_APM_M2_STATUS_CLR_REG register
- *  M2 status clear register
- */
-#define CPU_APM_M2_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xec)
-/** CPU_APM_M2_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Configures to clear exception status.
- */
-#define CPU_APM_M2_EXCEPTION_STATUS_CLR    (BIT(0))
-#define CPU_APM_M2_EXCEPTION_STATUS_CLR_M  (CPU_APM_M2_EXCEPTION_STATUS_CLR_V << CPU_APM_M2_EXCEPTION_STATUS_CLR_S)
-#define CPU_APM_M2_EXCEPTION_STATUS_CLR_V  0x00000001U
-#define CPU_APM_M2_EXCEPTION_STATUS_CLR_S  0
-
-/** CPU_APM_M2_EXCEPTION_INFO0_REG register
- *  M2 exception_info0 register
- */
-#define CPU_APM_M2_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xf0)
-/** CPU_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
- *  Represents exception region.
- */
-#define CPU_APM_M2_EXCEPTION_REGION    0x0000FFFFU
-#define CPU_APM_M2_EXCEPTION_REGION_M  (CPU_APM_M2_EXCEPTION_REGION_V << CPU_APM_M2_EXCEPTION_REGION_S)
-#define CPU_APM_M2_EXCEPTION_REGION_V  0x0000FFFFU
-#define CPU_APM_M2_EXCEPTION_REGION_S  0
-/** CPU_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Represents exception mode.
- */
-#define CPU_APM_M2_EXCEPTION_MODE    0x00000003U
-#define CPU_APM_M2_EXCEPTION_MODE_M  (CPU_APM_M2_EXCEPTION_MODE_V << CPU_APM_M2_EXCEPTION_MODE_S)
-#define CPU_APM_M2_EXCEPTION_MODE_V  0x00000003U
-#define CPU_APM_M2_EXCEPTION_MODE_S  16
-/** CPU_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Represents exception id information.
- */
-#define CPU_APM_M2_EXCEPTION_ID    0x0000001FU
-#define CPU_APM_M2_EXCEPTION_ID_M  (CPU_APM_M2_EXCEPTION_ID_V << CPU_APM_M2_EXCEPTION_ID_S)
-#define CPU_APM_M2_EXCEPTION_ID_V  0x0000001FU
-#define CPU_APM_M2_EXCEPTION_ID_S  18
-
-/** CPU_APM_M2_EXCEPTION_INFO1_REG register
- *  M2 exception_info1 register
- */
-#define CPU_APM_M2_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xf4)
-/** CPU_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Represents exception addr.
- */
-#define CPU_APM_M2_EXCEPTION_ADDR    0xFFFFFFFFU
-#define CPU_APM_M2_EXCEPTION_ADDR_M  (CPU_APM_M2_EXCEPTION_ADDR_V << CPU_APM_M2_EXCEPTION_ADDR_S)
-#define CPU_APM_M2_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define CPU_APM_M2_EXCEPTION_ADDR_S  0
-
-/** CPU_APM_M3_STATUS_REG register
- *  M3 status register
- */
-#define CPU_APM_M3_STATUS_REG (DR_REG_CPU_APM_BASE + 0xf8)
-/** CPU_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Represents exception status.
- *  bit0: 1 represents authority_exception
- *  bit1: 1 represents space_exception
- */
-#define CPU_APM_M3_EXCEPTION_STATUS    0x00000003U
-#define CPU_APM_M3_EXCEPTION_STATUS_M  (CPU_APM_M3_EXCEPTION_STATUS_V << CPU_APM_M3_EXCEPTION_STATUS_S)
-#define CPU_APM_M3_EXCEPTION_STATUS_V  0x00000003U
-#define CPU_APM_M3_EXCEPTION_STATUS_S  0
-
-/** CPU_APM_M3_STATUS_CLR_REG register
- *  M3 status clear register
- */
-#define CPU_APM_M3_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xfc)
-/** CPU_APM_M3_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Configures to clear exception status.
- */
-#define CPU_APM_M3_EXCEPTION_STATUS_CLR    (BIT(0))
-#define CPU_APM_M3_EXCEPTION_STATUS_CLR_M  (CPU_APM_M3_EXCEPTION_STATUS_CLR_V << CPU_APM_M3_EXCEPTION_STATUS_CLR_S)
-#define CPU_APM_M3_EXCEPTION_STATUS_CLR_V  0x00000001U
-#define CPU_APM_M3_EXCEPTION_STATUS_CLR_S  0
-
-/** CPU_APM_M3_EXCEPTION_INFO0_REG register
- *  M3 exception_info0 register
- */
-#define CPU_APM_M3_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0x100)
-/** CPU_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
- *  Represents exception region.
- */
-#define CPU_APM_M3_EXCEPTION_REGION    0x0000FFFFU
-#define CPU_APM_M3_EXCEPTION_REGION_M  (CPU_APM_M3_EXCEPTION_REGION_V << CPU_APM_M3_EXCEPTION_REGION_S)
-#define CPU_APM_M3_EXCEPTION_REGION_V  0x0000FFFFU
-#define CPU_APM_M3_EXCEPTION_REGION_S  0
-/** CPU_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Represents exception mode.
- */
-#define CPU_APM_M3_EXCEPTION_MODE    0x00000003U
-#define CPU_APM_M3_EXCEPTION_MODE_M  (CPU_APM_M3_EXCEPTION_MODE_V << CPU_APM_M3_EXCEPTION_MODE_S)
-#define CPU_APM_M3_EXCEPTION_MODE_V  0x00000003U
-#define CPU_APM_M3_EXCEPTION_MODE_S  16
-/** CPU_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Represents exception id information.
- */
-#define CPU_APM_M3_EXCEPTION_ID    0x0000001FU
-#define CPU_APM_M3_EXCEPTION_ID_M  (CPU_APM_M3_EXCEPTION_ID_V << CPU_APM_M3_EXCEPTION_ID_S)
-#define CPU_APM_M3_EXCEPTION_ID_V  0x0000001FU
-#define CPU_APM_M3_EXCEPTION_ID_S  18
-
-/** CPU_APM_M3_EXCEPTION_INFO1_REG register
- *  M3 exception_info1 register
- */
-#define CPU_APM_M3_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0x104)
-/** CPU_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Represents exception addr.
- */
-#define CPU_APM_M3_EXCEPTION_ADDR    0xFFFFFFFFU
-#define CPU_APM_M3_EXCEPTION_ADDR_M  (CPU_APM_M3_EXCEPTION_ADDR_V << CPU_APM_M3_EXCEPTION_ADDR_S)
-#define CPU_APM_M3_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define CPU_APM_M3_EXCEPTION_ADDR_S  0
-
-/** CPU_APM_INT_EN_REG register
- *  APM interrupt enable register
- */
-#define CPU_APM_INT_EN_REG (DR_REG_CPU_APM_BASE + 0x118)
-/** CPU_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
- *  Configures to enable APM M0 interrupt.
- *  0: disable
- *  1: enable
- */
-#define CPU_APM_M0_APM_INT_EN    (BIT(0))
-#define CPU_APM_M0_APM_INT_EN_M  (CPU_APM_M0_APM_INT_EN_V << CPU_APM_M0_APM_INT_EN_S)
-#define CPU_APM_M0_APM_INT_EN_V  0x00000001U
-#define CPU_APM_M0_APM_INT_EN_S  0
-/** CPU_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
- *  Configures to enable APM M1 interrupt.
- *  0: disable
- *  1: enable
- */
-#define CPU_APM_M1_APM_INT_EN    (BIT(1))
-#define CPU_APM_M1_APM_INT_EN_M  (CPU_APM_M1_APM_INT_EN_V << CPU_APM_M1_APM_INT_EN_S)
-#define CPU_APM_M1_APM_INT_EN_V  0x00000001U
-#define CPU_APM_M1_APM_INT_EN_S  1
-/** CPU_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0;
- *  Configures to enable APM M2 interrupt.
- *  0: disable
- *  1: enable
- */
-#define CPU_APM_M2_APM_INT_EN    (BIT(2))
-#define CPU_APM_M2_APM_INT_EN_M  (CPU_APM_M2_APM_INT_EN_V << CPU_APM_M2_APM_INT_EN_S)
-#define CPU_APM_M2_APM_INT_EN_V  0x00000001U
-#define CPU_APM_M2_APM_INT_EN_S  2
-/** CPU_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0;
- *  Configures to enable APM M3 interrupt.
- *  0: disable
- *  1: enable
- */
-#define CPU_APM_M3_APM_INT_EN    (BIT(3))
-#define CPU_APM_M3_APM_INT_EN_M  (CPU_APM_M3_APM_INT_EN_V << CPU_APM_M3_APM_INT_EN_S)
-#define CPU_APM_M3_APM_INT_EN_V  0x00000001U
-#define CPU_APM_M3_APM_INT_EN_S  3
-
-/** CPU_APM_CLOCK_GATE_REG register
- *  Clock gating register
- */
-#define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_APM_BASE + 0x7f8)
-/** CPU_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Configures whether to keep the clock always on.
- *  0: enable automatic clock gating
- *  1: keep the clock always on
- */
-#define CPU_APM_CLK_EN    (BIT(0))
-#define CPU_APM_CLK_EN_M  (CPU_APM_CLK_EN_V << CPU_APM_CLK_EN_S)
-#define CPU_APM_CLK_EN_V  0x00000001U
-#define CPU_APM_CLK_EN_S  0
-
-/** CPU_APM_DATE_REG register
- *  Version control register
- */
-#define CPU_APM_DATE_REG (DR_REG_CPU_APM_BASE + 0x7fc)
-/** CPU_APM_DATE : R/W; bitpos: [27:0]; default: 37769360;
- *  Version control register.
- */
-#define CPU_APM_DATE    0x0FFFFFFFU
-#define CPU_APM_DATE_M  (CPU_APM_DATE_V << CPU_APM_DATE_S)
-#define CPU_APM_DATE_V  0x0FFFFFFFU
-#define CPU_APM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h4/register/hw_ver_beta5/soc/cpu_apm_struct.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/cpu_apm_struct.h
deleted file mode 100644
index 1775e739b0..0000000000
--- a/components/soc/esp32h4/register/hw_ver_beta5/soc/cpu_apm_struct.h
+++ /dev/null
@@ -1,578 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0 OR MIT
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Region filter enable register */
-/** Type of apm_region_filter_en register
- *  Region filter enable register
- */
-typedef union {
-    struct {
-        /** apm_region_filter_en : R/W; bitpos: [7:0]; default: 1;
-         *  Configure bit $n (0-7) to enable region $n.
-         *  0: disable
-         *  1: enable
-         */
-        uint32_t apm_region_filter_en:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} cpu_apm_region_filter_en_reg_t;
-
-
-/** Group: Region address register */
-/** Type of apm_regionn_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** apm_regionn_addr_start_l : HRO; bitpos: [11:0]; default: 0;
-         *  Low 12 bit, start address of region n.
-         */
-        uint32_t apm_regionn_addr_start_l:12;
-        /** apm_regionn_addr_start : R/W; bitpos: [18:12]; default: 0;
-         *  Configures start address of region n.
-         */
-        uint32_t apm_regionn_addr_start:7;
-        /** apm_regionn_addr_start_h : HRO; bitpos: [31:19]; default: 2064;
-         *  High 13 bit,  start address of region n.
-         */
-        uint32_t apm_regionn_addr_start_h:13;
-    };
-    uint32_t val;
-} cpu_apm_regionn_addr_start_reg_t;
-
-/** Type of apm_regionn_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** apm_regionn_addr_end_l : HRO; bitpos: [11:0]; default: 4095;
-         *  Low 12 bit, end address of region n.
-         */
-        uint32_t apm_regionn_addr_end_l:12;
-        /** apm_regionn_addr_end : R/W; bitpos: [18:12]; default: 127;
-         *  Configures end address of region n.
-         */
-        uint32_t apm_regionn_addr_end:7;
-        /** apm_regionn_addr_end_h : HRO; bitpos: [31:19]; default: 2064;
-         *  High 13 bit,  end address of region n.
-         */
-        uint32_t apm_regionn_addr_end_h:13;
-    };
-    uint32_t val;
-} cpu_apm_regionn_addr_end_reg_t;
-
-
-/** Group: Region access authority attribute register */
-/** Type of apm_regionn_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** apm_regionn_r0_x : R/W; bitpos: [0]; default: 0;
-         *  Configures the execution authority of REE_MODE 0 in region n.
-         */
-        uint32_t apm_regionn_r0_x:1;
-        /** apm_regionn_r0_w : R/W; bitpos: [1]; default: 0;
-         *  Configures the write authority of REE_MODE 0 in region n.
-         */
-        uint32_t apm_regionn_r0_w:1;
-        /** apm_regionn_r0_r : R/W; bitpos: [2]; default: 0;
-         *  Configures the read authority of REE_MODE 0 in region n.
-         */
-        uint32_t apm_regionn_r0_r:1;
-        uint32_t reserved_3:1;
-        /** apm_regionn_r1_x : R/W; bitpos: [4]; default: 0;
-         *  Configures the execution authority of REE_MODE 1 in region n.
-         */
-        uint32_t apm_regionn_r1_x:1;
-        /** apm_regionn_r1_w : R/W; bitpos: [5]; default: 0;
-         *  Configures the write authority of REE_MODE 1 in region n.
-         */
-        uint32_t apm_regionn_r1_w:1;
-        /** apm_regionn_r1_r : R/W; bitpos: [6]; default: 0;
-         *  Configures the read authority of REE_MODE 1 in region n.
-         */
-        uint32_t apm_regionn_r1_r:1;
-        uint32_t reserved_7:1;
-        /** apm_regionn_r2_x : R/W; bitpos: [8]; default: 0;
-         *  Configures the execution authority of REE_MODE 2 in region n.
-         */
-        uint32_t apm_regionn_r2_x:1;
-        /** apm_regionn_r2_w : R/W; bitpos: [9]; default: 0;
-         *  Configures the write authority of REE_MODE 2 in region n.
-         */
-        uint32_t apm_regionn_r2_w:1;
-        /** apm_regionn_r2_r : R/W; bitpos: [10]; default: 0;
-         *  Configures the read authority of REE_MODE 2 in region n.
-         */
-        uint32_t apm_regionn_r2_r:1;
-        /** apm_regionn_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region0 configuration
-         */
-        uint32_t apm_regionn_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} cpu_apm_regionn_attr_reg_t;
-
-
-/** Group: function control register */
-/** Type of apm_func_ctrl register
- *  APM function control register
- */
-typedef union {
-    struct {
-        /** apm_m0_func_en : R/W; bitpos: [0]; default: 1;
-         *  PMS M0 function enable
-         */
-        uint32_t apm_m0_func_en:1;
-        /** apm_m1_func_en : R/W; bitpos: [1]; default: 1;
-         *  PMS M1 function enable
-         */
-        uint32_t apm_m1_func_en:1;
-        /** apm_m2_func_en : R/W; bitpos: [2]; default: 1;
-         *  PMS M2 function enable
-         */
-        uint32_t apm_m2_func_en:1;
-        /** apm_m3_func_en : R/W; bitpos: [3]; default: 1;
-         *  PMS M3 function enable
-         */
-        uint32_t apm_m3_func_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} cpu_apm_func_ctrl_reg_t;
-
-
-/** Group: M0 status register */
-/** Type of apm_m0_status register
- *  M0 status register
- */
-typedef union {
-    struct {
-        /** apm_m0_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Represents exception status.
-         *  bit0: 1 represents authority_exception
-         *  bit1: 1 represents space_exception
-         */
-        uint32_t apm_m0_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} cpu_apm_m0_status_reg_t;
-
-
-/** Group: M0 status clear register */
-/** Type of apm_m0_status_clr register
- *  M0 status clear register
- */
-typedef union {
-    struct {
-        /** apm_m0_exception_status_clr : WT; bitpos: [0]; default: 0;
-         *  Configures to clear exception status.
-         */
-        uint32_t apm_m0_exception_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} cpu_apm_m0_status_clr_reg_t;
-
-
-/** Group: M0 exception_info0 register */
-/** Type of apm_m0_exception_info0 register
- *  M0 exception_info0 register
- */
-typedef union {
-    struct {
-        /** apm_m0_exception_region : RO; bitpos: [15:0]; default: 0;
-         *  Represents exception region.
-         */
-        uint32_t apm_m0_exception_region:16;
-        /** apm_m0_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Represents exception mode.
-         */
-        uint32_t apm_m0_exception_mode:2;
-        /** apm_m0_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Represents exception id information.
-         */
-        uint32_t apm_m0_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} cpu_apm_m0_exception_info0_reg_t;
-
-
-/** Group: M0 exception_info1 register */
-/** Type of apm_m0_exception_info1 register
- *  M0 exception_info1 register
- */
-typedef union {
-    struct {
-        /** apm_m0_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Represents exception addr.
-         */
-        uint32_t apm_m0_exception_addr:32;
-    };
-    uint32_t val;
-} cpu_apm_m0_exception_info1_reg_t;
-
-
-/** Group: M1 status register */
-/** Type of apm_m1_status register
- *  M1 status register
- */
-typedef union {
-    struct {
-        /** apm_m1_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Represents exception status.
-         *  bit0: 1 represents authority_exception
-         *  bit1: 1 represents space_exception
-         */
-        uint32_t apm_m1_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} cpu_apm_m1_status_reg_t;
-
-
-/** Group: M1 status clear register */
-/** Type of apm_m1_status_clr register
- *  M1 status clear register
- */
-typedef union {
-    struct {
-        /** apm_m1_exception_status_clr : WT; bitpos: [0]; default: 0;
-         *  Configures to clear exception status.
-         */
-        uint32_t apm_m1_exception_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} cpu_apm_m1_status_clr_reg_t;
-
-
-/** Group: M1 exception_info0 register */
-/** Type of apm_m1_exception_info0 register
- *  M1 exception_info0 register
- */
-typedef union {
-    struct {
-        /** apm_m1_exception_region : RO; bitpos: [15:0]; default: 0;
-         *  Represents exception region.
-         */
-        uint32_t apm_m1_exception_region:16;
-        /** apm_m1_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Represents exception mode.
-         */
-        uint32_t apm_m1_exception_mode:2;
-        /** apm_m1_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Represents exception id information.
-         */
-        uint32_t apm_m1_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} cpu_apm_m1_exception_info0_reg_t;
-
-
-/** Group: M1 exception_info1 register */
-/** Type of apm_m1_exception_info1 register
- *  M1 exception_info1 register
- */
-typedef union {
-    struct {
-        /** apm_m1_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Represents exception addr.
-         */
-        uint32_t apm_m1_exception_addr:32;
-    };
-    uint32_t val;
-} cpu_apm_m1_exception_info1_reg_t;
-
-
-/** Group: M2 status register */
-/** Type of apm_m2_status register
- *  M2 status register
- */
-typedef union {
-    struct {
-        /** apm_m2_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Represents exception status.
-         *  bit0: 1 represents authority_exception
-         *  bit1: 1 represents space_exception
-         */
-        uint32_t apm_m2_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} cpu_apm_m2_status_reg_t;
-
-
-/** Group: M2 status clear register */
-/** Type of apm_m2_status_clr register
- *  M2 status clear register
- */
-typedef union {
-    struct {
-        /** apm_m2_exception_status_clr : WT; bitpos: [0]; default: 0;
-         *  Configures to clear exception status.
-         */
-        uint32_t apm_m2_exception_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} cpu_apm_m2_status_clr_reg_t;
-
-
-/** Group: M2 exception_info0 register */
-/** Type of apm_m2_exception_info0 register
- *  M2 exception_info0 register
- */
-typedef union {
-    struct {
-        /** apm_m2_exception_region : RO; bitpos: [15:0]; default: 0;
-         *  Represents exception region.
-         */
-        uint32_t apm_m2_exception_region:16;
-        /** apm_m2_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Represents exception mode.
-         */
-        uint32_t apm_m2_exception_mode:2;
-        /** apm_m2_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Represents exception id information.
-         */
-        uint32_t apm_m2_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} cpu_apm_m2_exception_info0_reg_t;
-
-
-/** Group: M2 exception_info1 register */
-/** Type of apm_m2_exception_info1 register
- *  M2 exception_info1 register
- */
-typedef union {
-    struct {
-        /** apm_m2_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Represents exception addr.
-         */
-        uint32_t apm_m2_exception_addr:32;
-    };
-    uint32_t val;
-} cpu_apm_m2_exception_info1_reg_t;
-
-
-/** Group: M3 status register */
-/** Type of apm_m3_status register
- *  M3 status register
- */
-typedef union {
-    struct {
-        /** apm_m3_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Represents exception status.
-         *  bit0: 1 represents authority_exception
-         *  bit1: 1 represents space_exception
-         */
-        uint32_t apm_m3_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} cpu_apm_m3_status_reg_t;
-
-
-/** Group: M3 status clear register */
-/** Type of apm_m3_status_clr register
- *  M3 status clear register
- */
-typedef union {
-    struct {
-        /** apm_m3_exception_status_clr : WT; bitpos: [0]; default: 0;
-         *  Configures to clear exception status.
-         */
-        uint32_t apm_m3_exception_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} cpu_apm_m3_status_clr_reg_t;
-
-
-/** Group: M3 exception_info0 register */
-/** Type of apm_m3_exception_info0 register
- *  M3 exception_info0 register
- */
-typedef union {
-    struct {
-        /** apm_m3_exception_region : RO; bitpos: [15:0]; default: 0;
-         *  Represents exception region.
-         */
-        uint32_t apm_m3_exception_region:16;
-        /** apm_m3_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Represents exception mode.
-         */
-        uint32_t apm_m3_exception_mode:2;
-        /** apm_m3_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Represents exception id information.
-         */
-        uint32_t apm_m3_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} cpu_apm_m3_exception_info0_reg_t;
-
-
-/** Group: M3 exception_info1 register */
-/** Type of apm_m3_exception_info1 register
- *  M3 exception_info1 register
- */
-typedef union {
-    struct {
-        /** apm_m3_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Represents exception addr.
-         */
-        uint32_t apm_m3_exception_addr:32;
-    };
-    uint32_t val;
-} cpu_apm_m3_exception_info1_reg_t;
-
-
-/** Group: APM interrupt enable register */
-/** Type of apm_int_en register
- *  APM interrupt enable register
- */
-typedef union {
-    struct {
-        /** apm_m0_apm_int_en : R/W; bitpos: [0]; default: 0;
-         *  Configures to enable APM M0 interrupt.
-         *  0: disable
-         *  1: enable
-         */
-        uint32_t apm_m0_apm_int_en:1;
-        /** apm_m1_apm_int_en : R/W; bitpos: [1]; default: 0;
-         *  Configures to enable APM M1 interrupt.
-         *  0: disable
-         *  1: enable
-         */
-        uint32_t apm_m1_apm_int_en:1;
-        /** apm_m2_apm_int_en : R/W; bitpos: [2]; default: 0;
-         *  Configures to enable APM M2 interrupt.
-         *  0: disable
-         *  1: enable
-         */
-        uint32_t apm_m2_apm_int_en:1;
-        /** apm_m3_apm_int_en : R/W; bitpos: [3]; default: 0;
-         *  Configures to enable APM M3 interrupt.
-         *  0: disable
-         *  1: enable
-         */
-        uint32_t apm_m3_apm_int_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} cpu_apm_int_en_reg_t;
-
-
-/** Group: Clock gating register */
-/** Type of apm_clock_gate register
- *  Clock gating register
- */
-typedef union {
-    struct {
-        /** apm_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Configures whether to keep the clock always on.
-         *  0: enable automatic clock gating
-         *  1: keep the clock always on
-         */
-        uint32_t apm_clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} cpu_apm_clock_gate_reg_t;
-
-
-/** Group: Version control register */
-/** Type of apm_date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** apm_date : R/W; bitpos: [27:0]; default: 37769360;
-         *  Version control register.
-         */
-        uint32_t apm_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cpu_apm_date_reg_t;
-
-
-typedef struct {
-    volatile cpu_apm_region_filter_en_reg_t apm_region_filter_en;
-    volatile cpu_apm_regionn_addr_start_reg_t apm_region0_addr_start;
-    volatile cpu_apm_regionn_addr_end_reg_t apm_region0_addr_end;
-    volatile cpu_apm_regionn_attr_reg_t apm_region0_attr;
-    volatile cpu_apm_regionn_addr_start_reg_t apm_region1_addr_start;
-    volatile cpu_apm_regionn_addr_end_reg_t apm_region1_addr_end;
-    volatile cpu_apm_regionn_attr_reg_t apm_region1_attr;
-    volatile cpu_apm_regionn_addr_start_reg_t apm_region2_addr_start;
-    volatile cpu_apm_regionn_addr_end_reg_t apm_region2_addr_end;
-    volatile cpu_apm_regionn_attr_reg_t apm_region2_attr;
-    volatile cpu_apm_regionn_addr_start_reg_t apm_region3_addr_start;
-    volatile cpu_apm_regionn_addr_end_reg_t apm_region3_addr_end;
-    volatile cpu_apm_regionn_attr_reg_t apm_region3_attr;
-    volatile cpu_apm_regionn_addr_start_reg_t apm_region4_addr_start;
-    volatile cpu_apm_regionn_addr_end_reg_t apm_region4_addr_end;
-    volatile cpu_apm_regionn_attr_reg_t apm_region4_attr;
-    volatile cpu_apm_regionn_addr_start_reg_t apm_region5_addr_start;
-    volatile cpu_apm_regionn_addr_end_reg_t apm_region5_addr_end;
-    volatile cpu_apm_regionn_attr_reg_t apm_region5_attr;
-    volatile cpu_apm_regionn_addr_start_reg_t apm_region6_addr_start;
-    volatile cpu_apm_regionn_addr_end_reg_t apm_region6_addr_end;
-    volatile cpu_apm_regionn_attr_reg_t apm_region6_attr;
-    volatile cpu_apm_regionn_addr_start_reg_t apm_region7_addr_start;
-    volatile cpu_apm_regionn_addr_end_reg_t apm_region7_addr_end;
-    volatile cpu_apm_regionn_attr_reg_t apm_region7_attr;
-    uint32_t reserved_064[24];
-    volatile cpu_apm_func_ctrl_reg_t apm_func_ctrl;
-    volatile cpu_apm_m0_status_reg_t apm_m0_status;
-    volatile cpu_apm_m0_status_clr_reg_t apm_m0_status_clr;
-    volatile cpu_apm_m0_exception_info0_reg_t apm_m0_exception_info0;
-    volatile cpu_apm_m0_exception_info1_reg_t apm_m0_exception_info1;
-    volatile cpu_apm_m1_status_reg_t apm_m1_status;
-    volatile cpu_apm_m1_status_clr_reg_t apm_m1_status_clr;
-    volatile cpu_apm_m1_exception_info0_reg_t apm_m1_exception_info0;
-    volatile cpu_apm_m1_exception_info1_reg_t apm_m1_exception_info1;
-    volatile cpu_apm_m2_status_reg_t apm_m2_status;
-    volatile cpu_apm_m2_status_clr_reg_t apm_m2_status_clr;
-    volatile cpu_apm_m2_exception_info0_reg_t apm_m2_exception_info0;
-    volatile cpu_apm_m2_exception_info1_reg_t apm_m2_exception_info1;
-    volatile cpu_apm_m3_status_reg_t apm_m3_status;
-    volatile cpu_apm_m3_status_clr_reg_t apm_m3_status_clr;
-    volatile cpu_apm_m3_exception_info0_reg_t apm_m3_exception_info0;
-    volatile cpu_apm_m3_exception_info1_reg_t apm_m3_exception_info1;
-    uint32_t reserved_108[4];
-    volatile cpu_apm_int_en_reg_t apm_int_en;
-    uint32_t reserved_11c[439];
-    volatile cpu_apm_clock_gate_reg_t apm_clock_gate;
-    volatile cpu_apm_date_reg_t apm_date;
-} cpu_dev_t;
-
-extern cpu_dev_t CPU_APM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(cpu_dev_t) == 0x800, "Invalid size of cpu_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h4/register/hw_ver_beta5/soc/interrupt_matrix_reg.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/interrupt_matrix_reg.h
deleted file mode 100644
index 0200b13afd..0000000000
--- a/components/soc/esp32h4/register/hw_ver_beta5/soc/interrupt_matrix_reg.h
+++ /dev/null
@@ -1,1865 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0 OR MIT
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define DR_REG_INTERRUPT_BASE(i)             (DR_REG_INTMTX0_BASE + (i) * 0x1000)
-
-/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG register
- *  WIFI_MAC_INTR mapping register
- */
-#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x0)
-/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_M  (INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V << INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S)
-#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S  0
-/** INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register
- *  WIFI_MAC_NMI mapping register
- */
-#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x4)
-/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP    0x0000003FU
-#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M  (INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V << INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S)
-#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S  0
-/** INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_M  (INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG register
- *  WIFI_PWR_INTR mapping register
- */
-#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x8)
-/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_M  (INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V << INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S)
-#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S  0
-/** INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG register
- *  WIFI_BB_INTR mapping register
- */
-#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xc)
-/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_M  (INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V << INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S)
-#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S  0
-/** INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG register
- *  BT_MAC_INTR mapping register
- */
-#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x10)
-/** INTERRUPT_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_BT_MAC_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_M  (INTERRUPT_CORE0_BT_MAC_INTR_MAP_V << INTERRUPT_CORE0_BT_MAC_INTR_MAP_S)
-#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_S  0
-/** INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_BT_BB_INTR_MAP_REG register
- *  BT_BB_INTR mapping register
- */
-#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x14)
-/** INTERRUPT_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_BT_BB_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_BT_BB_INTR_MAP_M  (INTERRUPT_CORE0_BT_BB_INTR_MAP_V << INTERRUPT_CORE0_BT_BB_INTR_MAP_S)
-#define INTERRUPT_CORE0_BT_BB_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_BT_BB_INTR_MAP_S  0
-/** INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register
- *  BT_BB_NMI mapping register
- */
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x18)
-/** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP    0x0000003FU
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M  (INTERRUPT_CORE0_BT_BB_NMI_MAP_V << INTERRUPT_CORE0_BT_BB_NMI_MAP_S)
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S  0
-/** INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_M  (INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG register
- *  LP_TIMER_INTR mapping register
- */
-#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x1c)
-/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S)
-#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S  0
-/** INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_COEX_INTR_MAP_REG register
- *  COEX_INTR mapping register
- */
-#define INTERRUPT_CORE0_COEX_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x20)
-/** INTERRUPT_CORE0_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_COEX_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_COEX_INTR_MAP_M  (INTERRUPT_CORE0_COEX_INTR_MAP_V << INTERRUPT_CORE0_COEX_INTR_MAP_S)
-#define INTERRUPT_CORE0_COEX_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_COEX_INTR_MAP_S  0
-/** INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG register
- *  BLE_TIMER_INTR mapping register
- */
-#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x24)
-/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S)
-#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S  0
-/** INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG register
- *  BLE_SEC_INTR mapping register
- */
-#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x28)
-/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_M  (INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V << INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S)
-#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S  0
-/** INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG register
- *  I2C_MST_INTR mapping register
- */
-#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x2c)
-/** INTERRUPT_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_I2C_MST_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_M  (INTERRUPT_CORE0_I2C_MST_INTR_MAP_V << INTERRUPT_CORE0_I2C_MST_INTR_MAP_S)
-#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_S  0
-/** INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG register
- *  ZB_MAC_INTR mapping register
- */
-#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x30)
-/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_M  (INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V << INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S)
-#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S  0
-/** INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_REG register
- *  MODEM_APB_TIMEOUT_INTR mapping register
- */
-#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x34)
-/** INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_S)
-#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_S  0
-/** INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_BT_MAC_INT1_MAP_REG register
- *  BT_MAC_INT1 mapping register
- */
-#define INTERRUPT_CORE0_BT_MAC_INT1_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x38)
-/** INTERRUPT_CORE0_BT_MAC_INT1_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_BT_MAC_INT1_MAP    0x0000003FU
-#define INTERRUPT_CORE0_BT_MAC_INT1_MAP_M  (INTERRUPT_CORE0_BT_MAC_INT1_MAP_V << INTERRUPT_CORE0_BT_MAC_INT1_MAP_S)
-#define INTERRUPT_CORE0_BT_MAC_INT1_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_BT_MAC_INT1_MAP_S  0
-/** INTERRUPT_CORE0_BT_MAC_INT1_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_BT_MAC_INT1_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_BT_MAC_INT1_PASS_IN_SEC_M  (INTERRUPT_CORE0_BT_MAC_INT1_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_MAC_INT1_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_BT_MAC_INT1_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_BT_MAC_INT1_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_PMU_INTR_MAP_REG register
- *  PMU_INTR mapping register
- */
-#define INTERRUPT_CORE0_PMU_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x3c)
-/** INTERRUPT_CORE0_PMU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_PMU_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_PMU_INTR_MAP_M  (INTERRUPT_CORE0_PMU_INTR_MAP_V << INTERRUPT_CORE0_PMU_INTR_MAP_S)
-#define INTERRUPT_CORE0_PMU_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_PMU_INTR_MAP_S  0
-/** INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_EFUSE_INTR_MAP_REG register
- *  EFUSE_INTR mapping register
- */
-#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x40)
-/** INTERRUPT_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_EFUSE_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_EFUSE_INTR_MAP_M  (INTERRUPT_CORE0_EFUSE_INTR_MAP_V << INTERRUPT_CORE0_EFUSE_INTR_MAP_S)
-#define INTERRUPT_CORE0_EFUSE_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_EFUSE_INTR_MAP_S  0
-/** INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
- *  LP_RTC_TIMER_INTR mapping register
- */
-#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x44)
-/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S)
-#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S  0
-/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_REG register
- *  LP_RTC_BLE_TIMER_INTR mapping register
- */
-#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x48)
-/** INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_S)
-#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_S  0
-/** INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register
- *  LP_WDT_INTR mapping register
- */
-#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x4c)
-/** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LP_WDT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_M  (INTERRUPT_CORE0_LP_WDT_INTR_MAP_V << INTERRUPT_CORE0_LP_WDT_INTR_MAP_S)
-#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_S  0
-/** INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_TOUCH_INTR_MAP_REG register
- *  TOUCH_INTR mapping register
- */
-#define INTERRUPT_CORE0_TOUCH_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x50)
-/** INTERRUPT_CORE0_TOUCH_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_TOUCH_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_TOUCH_INTR_MAP_M  (INTERRUPT_CORE0_TOUCH_INTR_MAP_V << INTERRUPT_CORE0_TOUCH_INTR_MAP_S)
-#define INTERRUPT_CORE0_TOUCH_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_TOUCH_INTR_MAP_S  0
-/** INTERRUPT_CORE0_TOUCH_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_TOUCH_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_TOUCH_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_TOUCH_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TOUCH_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_TOUCH_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_TOUCH_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_HUK_INTR_MAP_REG register
- *  HUK_INTR mapping register
- */
-#define INTERRUPT_CORE0_HUK_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x54)
-/** INTERRUPT_CORE0_HUK_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_HUK_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_HUK_INTR_MAP_M  (INTERRUPT_CORE0_HUK_INTR_MAP_V << INTERRUPT_CORE0_HUK_INTR_MAP_S)
-#define INTERRUPT_CORE0_HUK_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_HUK_INTR_MAP_S  0
-/** INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
- *  CPU_INTR_FROM_CPU_0 mapping register
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x58)
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
- *  CPU_INTR_FROM_CPU_1 mapping register
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x5c)
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
- *  CPU_INTR_FROM_CPU_2 mapping register
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x60)
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
- *  CPU_INTR_FROM_CPU_3 mapping register
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x64)
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG register
- *  BUS_MONITOR_INTR mapping register
- */
-#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x68)
-/** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_M  (INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_V << INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_S)
-#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_S  0
-/** INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG register
- *  CORE0_TRACE_INTR mapping register
- */
-#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x6c)
-/** INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_M  (INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_V << INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_S)
-#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_S  0
-/** INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG register
- *  CORE1_TRACE_INTR mapping register
- */
-#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x70)
-/** INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_M  (INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_V << INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_S)
-#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_S  0
-/** INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register
- *  CACHE_INTR mapping register
- */
-#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x74)
-/** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CACHE_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CACHE_INTR_MAP_M  (INTERRUPT_CORE0_CACHE_INTR_MAP_V << INTERRUPT_CORE0_CACHE_INTR_MAP_S)
-#define INTERRUPT_CORE0_CACHE_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CACHE_INTR_MAP_S  0
-/** INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
- *  CPU_PERI_TIMEOUT_INTR mapping register
- */
-#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x78)
-/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S)
-#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S  0
-/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
- *  GPIO_INTERRUPT_PRO mapping register
- */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x7c)
-/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP    0x0000003FU
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M  (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S)
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
-/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_M  (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_REG register
- *  GPIO_INTERRUPT_2 mapping register
- */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x80)
-/** INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP    0x0000003FU
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_M  (INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_S)
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_S  0
-/** INTERRUPT_CORE0_GPIO_INTERRUPT_2_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_PASS_IN_SEC_M  (INTERRUPT_CORE0_GPIO_INTERRUPT_2_PASS_IN_SEC_V << INTERRUPT_CORE0_GPIO_INTERRUPT_2_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_PAU_INTR_MAP_REG register
- *  PAU_INTR mapping register
- */
-#define INTERRUPT_CORE0_PAU_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x84)
-/** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_PAU_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_PAU_INTR_MAP_M  (INTERRUPT_CORE0_PAU_INTR_MAP_V << INTERRUPT_CORE0_PAU_INTR_MAP_S)
-#define INTERRUPT_CORE0_PAU_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_PAU_INTR_MAP_S  0
-/** INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
- *  HP_PERI_TIMEOUT_INTR mapping register
- */
-#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x88)
-/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S)
-#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S  0
-/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register
- *  HP_APM_M0_INTR mapping register
- */
-#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x8c)
-/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S)
-#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S  0
-/** INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register
- *  HP_APM_M1_INTR mapping register
- */
-#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x90)
-/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S)
-#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S  0
-/** INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register
- *  HP_APM_M2_INTR mapping register
- */
-#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x94)
-/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S)
-#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S  0
-/** INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register
- *  HP_APM_M3_INTR mapping register
- */
-#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x98)
-/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S)
-#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S  0
-/** INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG register
- *  HP_APM_M4_INTR mapping register
- */
-#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x9c)
-/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S)
-#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S  0
-/** INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG register
- *  CPU_APM_M0_INTR mapping register
- */
-#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xa0)
-/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_M  (INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_S)
-#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_S  0
-/** INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG register
- *  CPU_APM_M1_INTR mapping register
- */
-#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xa4)
-/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_M  (INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_S)
-#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_S  0
-/** INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG register
- *  CPU_APM_M2_INTR mapping register
- */
-#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xa8)
-/** INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_M  (INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_S)
-#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_S  0
-/** INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG register
- *  CPU_APM_M3_INTR mapping register
- */
-#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xac)
-/** INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_M  (INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_S)
-#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_S  0
-/** INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_MSPI_INTR_MAP_REG register
- *  MSPI_INTR mapping register
- */
-#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xb0)
-/** INTERRUPT_CORE0_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_MSPI_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_MSPI_INTR_MAP_M  (INTERRUPT_CORE0_MSPI_INTR_MAP_V << INTERRUPT_CORE0_MSPI_INTR_MAP_S)
-#define INTERRUPT_CORE0_MSPI_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_MSPI_INTR_MAP_S  0
-/** INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_I2S_INTR_MAP_REG register
- *  I2S_INTR mapping register
- */
-#define INTERRUPT_CORE0_I2S_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xb4)
-/** INTERRUPT_CORE0_I2S_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_I2S_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_I2S_INTR_MAP_M  (INTERRUPT_CORE0_I2S_INTR_MAP_V << INTERRUPT_CORE0_I2S_INTR_MAP_S)
-#define INTERRUPT_CORE0_I2S_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_I2S_INTR_MAP_S  0
-/** INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register
- *  UHCI0_INTR mapping register
- */
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xb8)
-/** INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M  (INTERRUPT_CORE0_UHCI0_INTR_MAP_V << INTERRUPT_CORE0_UHCI0_INTR_MAP_S)
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S  0
-/** INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_UART0_INTR_MAP_REG register
- *  UART0_INTR mapping register
- */
-#define INTERRUPT_CORE0_UART0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xbc)
-/** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_UART0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_UART0_INTR_MAP_M  (INTERRUPT_CORE0_UART0_INTR_MAP_V << INTERRUPT_CORE0_UART0_INTR_MAP_S)
-#define INTERRUPT_CORE0_UART0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_UART0_INTR_MAP_S  0
-/** INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_UART1_INTR_MAP_REG register
- *  UART1_INTR mapping register
- */
-#define INTERRUPT_CORE0_UART1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xc0)
-/** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_UART1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_UART1_INTR_MAP_M  (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S)
-#define INTERRUPT_CORE0_UART1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_UART1_INTR_MAP_S  0
-/** INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_LEDC_INTR_MAP_REG register
- *  LEDC_INTR mapping register
- */
-#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xc4)
-/** INTERRUPT_CORE0_LEDC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LEDC_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LEDC_INTR_MAP_M  (INTERRUPT_CORE0_LEDC_INTR_MAP_V << INTERRUPT_CORE0_LEDC_INTR_MAP_S)
-#define INTERRUPT_CORE0_LEDC_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LEDC_INTR_MAP_S  0
-/** INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_CAN0_INTR_MAP_REG register
- *  CAN0_INTR mapping register
- */
-#define INTERRUPT_CORE0_CAN0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xc8)
-/** INTERRUPT_CORE0_CAN0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CAN0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CAN0_INTR_MAP_M  (INTERRUPT_CORE0_CAN0_INTR_MAP_V << INTERRUPT_CORE0_CAN0_INTR_MAP_S)
-#define INTERRUPT_CORE0_CAN0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CAN0_INTR_MAP_S  0
-/** INTERRUPT_CORE0_CAN0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_CAN0_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_CAN0_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_CAN0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CAN0_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_CAN0_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_CAN0_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG register
- *  CAN0_TIMER_INTR mapping register
- */
-#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xcc)
-/** INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_V << INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_S)
-#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_S  0
-/** INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG register
- *  USB_SERIAL_JTAG_INTR mapping register
- */
-#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xd0)
-/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_M  (INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_V << INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_S)
-#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_S  0
-/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_RMT_INTR_MAP_REG register
- *  RMT_INTR mapping register
- */
-#define INTERRUPT_CORE0_RMT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xd4)
-/** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_RMT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_RMT_INTR_MAP_M  (INTERRUPT_CORE0_RMT_INTR_MAP_V << INTERRUPT_CORE0_RMT_INTR_MAP_S)
-#define INTERRUPT_CORE0_RMT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_RMT_INTR_MAP_S  0
-/** INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register
- *  I2C_EXT0_INTR mapping register
- */
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xd8)
-/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M  (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S)
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S  0
-/** INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG register
- *  I2C_EXT1_INTR mapping register
- */
-#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xdc)
-/** INTERRUPT_CORE0_I2C_EXT1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_M  (INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S)
-#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S  0
-/** INTERRUPT_CORE0_I2C_EXT1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_I2C_EXT1_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_I2C_EXT1_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_I2C_EXT1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2C_EXT1_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_I2C_EXT1_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_I2C_EXT1_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register
- *  TG0_T0_INTR mapping register
- */
-#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xe0)
-/** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_TG0_T0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_M  (INTERRUPT_CORE0_TG0_T0_INTR_MAP_V << INTERRUPT_CORE0_TG0_T0_INTR_MAP_S)
-#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_S  0
-/** INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register
- *  TG0_WDT_INTR mapping register
- */
-#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xe4)
-/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_M  (INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S)
-#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S  0
-/** INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register
- *  TG1_T0_INTR mapping register
- */
-#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xe8)
-/** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_TG1_T0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_M  (INTERRUPT_CORE0_TG1_T0_INTR_MAP_V << INTERRUPT_CORE0_TG1_T0_INTR_MAP_S)
-#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_S  0
-/** INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register
- *  TG1_WDT_INTR mapping register
- */
-#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xec)
-/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_M  (INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S)
-#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S  0
-/** INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
- *  SYSTIMER_TARGET0_INTR mapping register
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xf0)
-/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S  0
-/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
- *  SYSTIMER_TARGET1_INTR mapping register
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xf4)
-/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S  0
-/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
- *  SYSTIMER_TARGET2_INTR mapping register
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xf8)
-/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S  0
-/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG register
- *  APB_ADC_INTR mapping register
- */
-#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xfc)
-/** INTERRUPT_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_APB_ADC_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_M  (INTERRUPT_CORE0_APB_ADC_INTR_MAP_V << INTERRUPT_CORE0_APB_ADC_INTR_MAP_S)
-#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_S  0
-/** INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_PWM0_INTR_MAP_REG register
- *  PWM0_INTR mapping register
- */
-#define INTERRUPT_CORE0_PWM0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x100)
-/** INTERRUPT_CORE0_PWM0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_PWM0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_PWM0_INTR_MAP_M  (INTERRUPT_CORE0_PWM0_INTR_MAP_V << INTERRUPT_CORE0_PWM0_INTR_MAP_S)
-#define INTERRUPT_CORE0_PWM0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_PWM0_INTR_MAP_S  0
-/** INTERRUPT_CORE0_PWM0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_PWM0_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_PWM0_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_PWM0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PWM0_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_PWM0_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_PWM0_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_PWM1_INTR_MAP_REG register
- *  PWM1_INTR mapping register
- */
-#define INTERRUPT_CORE0_PWM1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x104)
-/** INTERRUPT_CORE0_PWM1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_PWM1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_PWM1_INTR_MAP_M  (INTERRUPT_CORE0_PWM1_INTR_MAP_V << INTERRUPT_CORE0_PWM1_INTR_MAP_S)
-#define INTERRUPT_CORE0_PWM1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_PWM1_INTR_MAP_S  0
-/** INTERRUPT_CORE0_PWM1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_PWM1_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_PWM1_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_PWM1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PWM1_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_PWM1_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_PWM1_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_PCNT_INTR_MAP_REG register
- *  PCNT_INTR mapping register
- */
-#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x108)
-/** INTERRUPT_CORE0_PCNT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_PCNT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_PCNT_INTR_MAP_M  (INTERRUPT_CORE0_PCNT_INTR_MAP_V << INTERRUPT_CORE0_PCNT_INTR_MAP_S)
-#define INTERRUPT_CORE0_PCNT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_PCNT_INTR_MAP_S  0
-/** INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG register
- *  PARL_IO_TX_INTR mapping register
- */
-#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x10c)
-/** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_M  (INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_V << INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_S)
-#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_S  0
-/** INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG register
- *  PARL_IO_RX_INTR mapping register
- */
-#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x110)
-/** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_M  (INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V << INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S)
-#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S  0
-/** INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_USB_OTG11_INTR_MAP_REG register
- *  USB_OTG11_INTR mapping register
- */
-#define INTERRUPT_CORE0_USB_OTG11_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x114)
-/** INTERRUPT_CORE0_USB_OTG11_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_USB_OTG11_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_USB_OTG11_INTR_MAP_M  (INTERRUPT_CORE0_USB_OTG11_INTR_MAP_V << INTERRUPT_CORE0_USB_OTG11_INTR_MAP_S)
-#define INTERRUPT_CORE0_USB_OTG11_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_USB_OTG11_INTR_MAP_S  0
-/** INTERRUPT_CORE0_USB_OTG11_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_USB_OTG11_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_USB_OTG11_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_USB_OTG11_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_USB_OTG11_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_USB_OTG11_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_USB_OTG11_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG register
- *  ASRC_CHNL0_INTR mapping register
- */
-#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x118)
-/** INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_M  (INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_V << INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_S)
-#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_S  0
-/** INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG register
- *  ASRC_CHNL1_INTR mapping register
- */
-#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x11c)
-/** INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_M  (INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_V << INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_S)
-#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_S  0
-/** INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG register
- *  ZERO_DET_INTR mapping register
- */
-#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x120)
-/** INTERRUPT_CORE0_ZERO_DET_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_M  (INTERRUPT_CORE0_ZERO_DET_INTR_MAP_V << INTERRUPT_CORE0_ZERO_DET_INTR_MAP_S)
-#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_S  0
-/** INTERRUPT_CORE0_ZERO_DET_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_ZERO_DET_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ZERO_DET_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register
- *  DMA_IN_CH0_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x124)
-/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_M  (INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S  0
-/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register
- *  DMA_IN_CH1_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x128)
-/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_M  (INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S  0
-/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG register
- *  DMA_IN_CH2_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x12c)
-/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_M  (INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_S  0
-/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_REG register
- *  DMA_IN_CH3_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x130)
-/** INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_M  (INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_S  0
-/** INTERRUPT_CORE0_DMA_IN_CH3_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_DMA_IN_CH3_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH3_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_REG register
- *  DMA_IN_CH4_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x134)
-/** INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_M  (INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_S  0
-/** INTERRUPT_CORE0_DMA_IN_CH4_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_DMA_IN_CH4_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH4_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
- *  DMA_OUT_CH0_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x138)
-/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_M  (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S  0
-/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
- *  DMA_OUT_CH1_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x13c)
-/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_M  (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S  0
-/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
- *  DMA_OUT_CH2_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x140)
-/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_M  (INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_S  0
-/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_REG register
- *  DMA_OUT_CH3_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x144)
-/** INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_M  (INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_S  0
-/** INTERRUPT_CORE0_DMA_OUT_CH3_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_DMA_OUT_CH3_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH3_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_REG register
- *  DMA_OUT_CH4_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x148)
-/** INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_M  (INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_S  0
-/** INTERRUPT_CORE0_DMA_OUT_CH4_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_DMA_OUT_CH4_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH4_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register
- *  GPSPI2_INTR mapping register
- */
-#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x14c)
-/** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_GPSPI2_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_M  (INTERRUPT_CORE0_GPSPI2_INTR_MAP_V << INTERRUPT_CORE0_GPSPI2_INTR_MAP_S)
-#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_S  0
-/** INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_GPSPI3_INTR_MAP_REG register
- *  GPSPI3_INTR mapping register
- */
-#define INTERRUPT_CORE0_GPSPI3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x150)
-/** INTERRUPT_CORE0_GPSPI3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_GPSPI3_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_GPSPI3_INTR_MAP_M  (INTERRUPT_CORE0_GPSPI3_INTR_MAP_V << INTERRUPT_CORE0_GPSPI3_INTR_MAP_S)
-#define INTERRUPT_CORE0_GPSPI3_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_GPSPI3_INTR_MAP_S  0
-/** INTERRUPT_CORE0_GPSPI3_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_GPSPI3_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_GPSPI3_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_GPSPI3_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_GPSPI3_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_GPSPI3_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_GPSPI3_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_AES_INTR_MAP_REG register
- *  AES_INTR mapping register
- */
-#define INTERRUPT_CORE0_AES_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x154)
-/** INTERRUPT_CORE0_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_AES_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_AES_INTR_MAP_M  (INTERRUPT_CORE0_AES_INTR_MAP_V << INTERRUPT_CORE0_AES_INTR_MAP_S)
-#define INTERRUPT_CORE0_AES_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_AES_INTR_MAP_S  0
-/** INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_SHA_INTR_MAP_REG register
- *  SHA_INTR mapping register
- */
-#define INTERRUPT_CORE0_SHA_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x158)
-/** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_SHA_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_SHA_INTR_MAP_M  (INTERRUPT_CORE0_SHA_INTR_MAP_V << INTERRUPT_CORE0_SHA_INTR_MAP_S)
-#define INTERRUPT_CORE0_SHA_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_SHA_INTR_MAP_S  0
-/** INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_ECC_INTR_MAP_REG register
- *  ECC_INTR mapping register
- */
-#define INTERRUPT_CORE0_ECC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x15c)
-/** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_ECC_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_ECC_INTR_MAP_M  (INTERRUPT_CORE0_ECC_INTR_MAP_V << INTERRUPT_CORE0_ECC_INTR_MAP_S)
-#define INTERRUPT_CORE0_ECC_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_ECC_INTR_MAP_S  0
-/** INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register
- *  ECDSA_INTR mapping register
- */
-#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x160)
-/** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_ECDSA_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_ECDSA_INTR_MAP_M  (INTERRUPT_CORE0_ECDSA_INTR_MAP_V << INTERRUPT_CORE0_ECDSA_INTR_MAP_S)
-#define INTERRUPT_CORE0_ECDSA_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_ECDSA_INTR_MAP_S  0
-/** INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_KM_INTR_MAP_REG register
- *  KM_INTR mapping register
- */
-#define INTERRUPT_CORE0_KM_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x164)
-/** INTERRUPT_CORE0_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_KM_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_KM_INTR_MAP_M  (INTERRUPT_CORE0_KM_INTR_MAP_V << INTERRUPT_CORE0_KM_INTR_MAP_S)
-#define INTERRUPT_CORE0_KM_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_KM_INTR_MAP_S  0
-/** INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0;
- *  Configures the PASS_IN_SEC flag of the interrupt source.
- */
-#define INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC    (BIT(8))
-#define INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_M  (INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_S)
-#define INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_V  0x00000001U
-#define INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_S  8
-
-/** INTERRUPT_CORE0_INT_STATUS_REG_0_REG register
- *  Status register for interrupt sources 0 ~ 31
- */
-#define INTERRUPT_CORE0_INT_STATUS_REG_0_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x168)
-/** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31.
- *  Each bit corresponds to one interrupt source
- *  0:The corresponding interrupt source triggered an interrupt
- *  1:No interrupt triggered
- */
-#define INTERRUPT_CORE0_INT_STATUS_0    0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_STATUS_0_M  (INTERRUPT_CORE0_INT_STATUS_0_V << INTERRUPT_CORE0_INT_STATUS_0_S)
-#define INTERRUPT_CORE0_INT_STATUS_0_V  0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_STATUS_0_S  0
-
-/** INTERRUPT_CORE0_INT_STATUS_REG_1_REG register
- *  Status register for interrupt sources 32 ~ 63
- */
-#define INTERRUPT_CORE0_INT_STATUS_REG_1_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x16c)
-/** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the status of the interrupt sources within interrupt-index-range 32 ~
- *  63. Each bit corresponds to one interrupt source
- *  0:The corresponding interrupt source triggered an interrupt
- *  1:No interrupt triggered
- */
-#define INTERRUPT_CORE0_INT_STATUS_1    0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_STATUS_1_M  (INTERRUPT_CORE0_INT_STATUS_1_V << INTERRUPT_CORE0_INT_STATUS_1_S)
-#define INTERRUPT_CORE0_INT_STATUS_1_V  0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_STATUS_1_S  0
-
-/** INTERRUPT_CORE0_INT_STATUS_REG_2_REG register
- *  Status register for interrupt sources 64 ~ 89
- */
-#define INTERRUPT_CORE0_INT_STATUS_REG_2_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x170)
-/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [25:0]; default: 0;
- *  Represents the status of the interrupt sources within interrupt-index-range 64 ~
- *  89. Each bit corresponds to one interrupt source
- *  0:The corresponding interrupt source triggered an interrupt
- *  1:No interrupt triggered
- */
-#define INTERRUPT_CORE0_INT_STATUS_2    0x03FFFFFFU
-#define INTERRUPT_CORE0_INT_STATUS_2_M  (INTERRUPT_CORE0_INT_STATUS_2_V << INTERRUPT_CORE0_INT_STATUS_2_S)
-#define INTERRUPT_CORE0_INT_STATUS_2_V  0x03FFFFFFU
-#define INTERRUPT_CORE0_INT_STATUS_2_S  0
-
-/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG register
- *  PASS_IN_SEC status register for interrupt sources 0 ~ 31
- */
-#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x174)
-/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the PASS_IN_SEC status of the interrupt sources within
- *  interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source
- *  0:The corresponding interrupt source is not PASS_IN_SEC.
- *  1:The corresponding interrupt source is PASS_IN_SEC.
- */
-#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0    0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_S)
-#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_V  0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_S  0
-
-/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG register
- *  PASS_IN_SEC status register for interrupt sources 32 ~ 63
- */
-#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x178)
-/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the PASS_IN_SEC status of the interrupt sources within
- *  interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source
- *  0:The corresponding interrupt source is not PASS_IN_SEC.
- *  1:The corresponding interrupt source is PASS_IN_SEC.
- */
-#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1    0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_S)
-#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_V  0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_S  0
-
-/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG register
- *  PASS_IN_SEC status register for interrupt sources 64 ~ 89
- */
-#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x17c)
-/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2 : RO; bitpos: [25:0]; default: 0;
- *  Represents the PASS_IN_SEC status of the interrupt sources with
- *  interrupt-index-range 64 ~ 89. Each bit corresponds to one interrupt source
- *  0:The corresponding interrupt source is not PASS_IN_SEC.
- *  1:The corresponding interrupt source is PASS_IN_SEC.
- */
-#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2    0x03FFFFFFU
-#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_S)
-#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_V  0x03FFFFFFU
-#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_S  0
-
-/** INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG register
- *  reserved
- */
-#define INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x180)
-/** INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC : R/W; bitpos: [5:0]; default: 0;
- *  reserved
- */
-#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC    0x0000003FU
-#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_M  (INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_V << INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_S)
-#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_V  0x0000003FU
-#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_S  0
-
-/** INTERRUPT_CORE0_SECURE_STATUS_REG register
- *  reserved
- */
-#define INTERRUPT_CORE0_SECURE_STATUS_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x184)
-/** INTERRUPT_CORE0_INT_SECURE_STATUS : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define INTERRUPT_CORE0_INT_SECURE_STATUS    0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_SECURE_STATUS_M  (INTERRUPT_CORE0_INT_SECURE_STATUS_V << INTERRUPT_CORE0_INT_SECURE_STATUS_S)
-#define INTERRUPT_CORE0_INT_SECURE_STATUS_V  0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_SECURE_STATUS_S  0
-
-/** INTERRUPT_CORE0_CLOCK_GATE_REG register
- *  Interrupt clock gating configure register
- */
-#define INTERRUPT_CORE0_CLOCK_GATE_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x188)
-/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Interrupt clock gating configure register
- */
-#define INTERRUPT_CORE0_REG_CLK_EN    (BIT(0))
-#define INTERRUPT_CORE0_REG_CLK_EN_M  (INTERRUPT_CORE0_REG_CLK_EN_V << INTERRUPT_CORE0_REG_CLK_EN_S)
-#define INTERRUPT_CORE0_REG_CLK_EN_V  0x00000001U
-#define INTERRUPT_CORE0_REG_CLK_EN_S  0
-
-/** INTERRUPT_CORE0_INTERRUPT_DATE_REG register
- *  Version control register
- */
-#define INTERRUPT_CORE0_INTERRUPT_DATE_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x7fc)
-/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 37822544;
- *  Version control register
- */
-#define INTERRUPT_CORE0_INTERRUPT_DATE    0x0FFFFFFFU
-#define INTERRUPT_CORE0_INTERRUPT_DATE_M  (INTERRUPT_CORE0_INTERRUPT_DATE_V << INTERRUPT_CORE0_INTERRUPT_DATE_S)
-#define INTERRUPT_CORE0_INTERRUPT_DATE_V  0x0FFFFFFFU
-#define INTERRUPT_CORE0_INTERRUPT_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h4/register/hw_ver_beta5/soc/interrupt_matrix_struct.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/interrupt_matrix_struct.h
deleted file mode 100644
index 23fda3cc97..0000000000
--- a/components/soc/esp32h4/register/hw_ver_beta5/soc/interrupt_matrix_struct.h
+++ /dev/null
@@ -1,1995 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0 OR MIT
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Registers */
-/** Type of core0_wifi_mac_intr_map register
- *  WIFI_MAC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_wifi_mac_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_wifi_mac_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_wifi_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_wifi_mac_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_wifi_mac_intr_map_reg_t;
-
-/** Type of core0_wifi_mac_nmi_map register
- *  WIFI_MAC_NMI mapping register
- */
-typedef union {
-    struct {
-        /** core0_wifi_mac_nmi_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_wifi_mac_nmi_map:6;
-        uint32_t reserved_6:2;
-        /** core0_wifi_mac_nmi_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_wifi_mac_nmi_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_wifi_mac_nmi_map_reg_t;
-
-/** Type of core0_wifi_pwr_intr_map register
- *  WIFI_PWR_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_wifi_pwr_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_wifi_pwr_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_wifi_pwr_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_wifi_pwr_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_wifi_pwr_intr_map_reg_t;
-
-/** Type of core0_wifi_bb_intr_map register
- *  WIFI_BB_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_wifi_bb_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_wifi_bb_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_wifi_bb_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_wifi_bb_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_wifi_bb_intr_map_reg_t;
-
-/** Type of core0_bt_mac_intr_map register
- *  BT_MAC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_bt_mac_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_bt_mac_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_bt_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_bt_mac_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_bt_mac_intr_map_reg_t;
-
-/** Type of core0_bt_bb_intr_map register
- *  BT_BB_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_bt_bb_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_bt_bb_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_bt_bb_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_bt_bb_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_bt_bb_intr_map_reg_t;
-
-/** Type of core0_bt_bb_nmi_map register
- *  BT_BB_NMI mapping register
- */
-typedef union {
-    struct {
-        /** core0_bt_bb_nmi_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_bt_bb_nmi_map:6;
-        uint32_t reserved_6:2;
-        /** core0_bt_bb_nmi_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_bt_bb_nmi_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_bt_bb_nmi_map_reg_t;
-
-/** Type of core0_lp_timer_intr_map register
- *  LP_TIMER_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_lp_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_lp_timer_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_lp_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_lp_timer_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_lp_timer_intr_map_reg_t;
-
-/** Type of core0_coex_intr_map register
- *  COEX_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_coex_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_coex_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_coex_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_coex_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_coex_intr_map_reg_t;
-
-/** Type of core0_ble_timer_intr_map register
- *  BLE_TIMER_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_ble_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_ble_timer_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_ble_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_ble_timer_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_ble_timer_intr_map_reg_t;
-
-/** Type of core0_ble_sec_intr_map register
- *  BLE_SEC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_ble_sec_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_ble_sec_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_ble_sec_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_ble_sec_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_ble_sec_intr_map_reg_t;
-
-/** Type of core0_i2c_mst_intr_map register
- *  I2C_MST_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_i2c_mst_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_i2c_mst_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_i2c_mst_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_i2c_mst_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_i2c_mst_intr_map_reg_t;
-
-/** Type of core0_zb_mac_intr_map register
- *  ZB_MAC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_zb_mac_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_zb_mac_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_zb_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_zb_mac_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_zb_mac_intr_map_reg_t;
-
-/** Type of core0_modem_apb_timeout_intr_map register
- *  MODEM_APB_TIMEOUT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_modem_apb_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_modem_apb_timeout_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_modem_apb_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_modem_apb_timeout_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_modem_apb_timeout_intr_map_reg_t;
-
-/** Type of core0_bt_mac_int1_map register
- *  BT_MAC_INT1 mapping register
- */
-typedef union {
-    struct {
-        /** core0_bt_mac_int1_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_bt_mac_int1_map:6;
-        uint32_t reserved_6:2;
-        /** core0_bt_mac_int1_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_bt_mac_int1_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_bt_mac_int1_map_reg_t;
-
-/** Type of core0_pmu_intr_map register
- *  PMU_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_pmu_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_pmu_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_pmu_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_pmu_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_pmu_intr_map_reg_t;
-
-/** Type of core0_efuse_intr_map register
- *  EFUSE_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_efuse_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_efuse_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_efuse_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_efuse_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_efuse_intr_map_reg_t;
-
-/** Type of core0_lp_rtc_timer_intr_map register
- *  LP_RTC_TIMER_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_lp_rtc_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_lp_rtc_timer_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_lp_rtc_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_lp_rtc_timer_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_lp_rtc_timer_intr_map_reg_t;
-
-/** Type of core0_lp_rtc_ble_timer_intr_map register
- *  LP_RTC_BLE_TIMER_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_lp_rtc_ble_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_lp_rtc_ble_timer_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_lp_rtc_ble_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_lp_rtc_ble_timer_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_lp_rtc_ble_timer_intr_map_reg_t;
-
-/** Type of core0_lp_wdt_intr_map register
- *  LP_WDT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_lp_wdt_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_lp_wdt_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_lp_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_lp_wdt_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_lp_wdt_intr_map_reg_t;
-
-/** Type of core0_touch_intr_map register
- *  TOUCH_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_touch_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_touch_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_touch_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_touch_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_touch_intr_map_reg_t;
-
-/** Type of core0_huk_intr_map register
- *  HUK_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_huk_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_huk_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_huk_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_huk_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_huk_intr_map_reg_t;
-
-/** Type of core0_cpu_intr_from_cpu_0_map register
- *  CPU_INTR_FROM_CPU_0 mapping register
- */
-typedef union {
-    struct {
-        /** core0_cpu_intr_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_cpu_intr_from_cpu_0_map:6;
-        uint32_t reserved_6:2;
-        /** core0_cpu_intr_from_cpu_0_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_cpu_intr_from_cpu_0_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_cpu_intr_from_cpu_0_map_reg_t;
-
-/** Type of core0_cpu_intr_from_cpu_1_map register
- *  CPU_INTR_FROM_CPU_1 mapping register
- */
-typedef union {
-    struct {
-        /** core0_cpu_intr_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_cpu_intr_from_cpu_1_map:6;
-        uint32_t reserved_6:2;
-        /** core0_cpu_intr_from_cpu_1_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_cpu_intr_from_cpu_1_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_cpu_intr_from_cpu_1_map_reg_t;
-
-/** Type of core0_cpu_intr_from_cpu_2_map register
- *  CPU_INTR_FROM_CPU_2 mapping register
- */
-typedef union {
-    struct {
-        /** core0_cpu_intr_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_cpu_intr_from_cpu_2_map:6;
-        uint32_t reserved_6:2;
-        /** core0_cpu_intr_from_cpu_2_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_cpu_intr_from_cpu_2_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_cpu_intr_from_cpu_2_map_reg_t;
-
-/** Type of core0_cpu_intr_from_cpu_3_map register
- *  CPU_INTR_FROM_CPU_3 mapping register
- */
-typedef union {
-    struct {
-        /** core0_cpu_intr_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_cpu_intr_from_cpu_3_map:6;
-        uint32_t reserved_6:2;
-        /** core0_cpu_intr_from_cpu_3_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_cpu_intr_from_cpu_3_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_cpu_intr_from_cpu_3_map_reg_t;
-
-/** Type of core0_bus_monitor_intr_map register
- *  BUS_MONITOR_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_bus_monitor_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_bus_monitor_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_bus_monitor_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_bus_monitor_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_bus_monitor_intr_map_reg_t;
-
-/** Type of core0_core0_trace_intr_map register
- *  CORE0_TRACE_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_core0_trace_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_core0_trace_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_core0_trace_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_core0_trace_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_core0_trace_intr_map_reg_t;
-
-/** Type of core0_core1_trace_intr_map register
- *  CORE1_TRACE_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_core1_trace_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_core1_trace_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_core1_trace_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_core1_trace_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_core1_trace_intr_map_reg_t;
-
-/** Type of core0_cache_intr_map register
- *  CACHE_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_cache_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_cache_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_cache_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_cache_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_cache_intr_map_reg_t;
-
-/** Type of core0_cpu_peri_timeout_intr_map register
- *  CPU_PERI_TIMEOUT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_cpu_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_cpu_peri_timeout_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_cpu_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_cpu_peri_timeout_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_cpu_peri_timeout_intr_map_reg_t;
-
-/** Type of core0_gpio_interrupt_pro_map register
- *  GPIO_INTERRUPT_PRO mapping register
- */
-typedef union {
-    struct {
-        /** core0_gpio_interrupt_pro_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_gpio_interrupt_pro_map:6;
-        uint32_t reserved_6:2;
-        /** core0_gpio_interrupt_pro_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_gpio_interrupt_pro_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_gpio_interrupt_pro_map_reg_t;
-
-/** Type of core0_gpio_interrupt_2_map register
- *  GPIO_INTERRUPT_2 mapping register
- */
-typedef union {
-    struct {
-        /** core0_gpio_interrupt_2_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_gpio_interrupt_2_map:6;
-        uint32_t reserved_6:2;
-        /** core0_gpio_interrupt_2_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_gpio_interrupt_2_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_gpio_interrupt_2_map_reg_t;
-
-/** Type of core0_pau_intr_map register
- *  PAU_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_pau_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_pau_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_pau_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_pau_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_pau_intr_map_reg_t;
-
-/** Type of core0_hp_peri_timeout_intr_map register
- *  HP_PERI_TIMEOUT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_hp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_hp_peri_timeout_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_hp_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_hp_peri_timeout_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_hp_peri_timeout_intr_map_reg_t;
-
-/** Type of core0_hp_apm_m0_intr_map register
- *  HP_APM_M0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_hp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_hp_apm_m0_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_hp_apm_m0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_hp_apm_m0_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_hp_apm_m0_intr_map_reg_t;
-
-/** Type of core0_hp_apm_m1_intr_map register
- *  HP_APM_M1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_hp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_hp_apm_m1_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_hp_apm_m1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_hp_apm_m1_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_hp_apm_m1_intr_map_reg_t;
-
-/** Type of core0_hp_apm_m2_intr_map register
- *  HP_APM_M2_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_hp_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_hp_apm_m2_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_hp_apm_m2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_hp_apm_m2_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_hp_apm_m2_intr_map_reg_t;
-
-/** Type of core0_hp_apm_m3_intr_map register
- *  HP_APM_M3_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_hp_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_hp_apm_m3_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_hp_apm_m3_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_hp_apm_m3_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_hp_apm_m3_intr_map_reg_t;
-
-/** Type of core0_hp_apm_m4_intr_map register
- *  HP_APM_M4_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_hp_apm_m4_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_hp_apm_m4_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_hp_apm_m4_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_hp_apm_m4_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_hp_apm_m4_intr_map_reg_t;
-
-/** Type of core0_cpu_apm_m0_intr_map register
- *  CPU_APM_M0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_cpu_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_cpu_apm_m0_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_cpu_apm_m0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_cpu_apm_m0_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_cpu_apm_m0_intr_map_reg_t;
-
-/** Type of core0_cpu_apm_m1_intr_map register
- *  CPU_APM_M1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_cpu_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_cpu_apm_m1_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_cpu_apm_m1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_cpu_apm_m1_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_cpu_apm_m1_intr_map_reg_t;
-
-/** Type of core0_cpu_apm_m2_intr_map register
- *  CPU_APM_M2_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_cpu_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_cpu_apm_m2_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_cpu_apm_m2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_cpu_apm_m2_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_cpu_apm_m2_intr_map_reg_t;
-
-/** Type of core0_cpu_apm_m3_intr_map register
- *  CPU_APM_M3_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_cpu_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_cpu_apm_m3_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_cpu_apm_m3_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_cpu_apm_m3_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_cpu_apm_m3_intr_map_reg_t;
-
-/** Type of core0_mspi_intr_map register
- *  MSPI_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_mspi_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_mspi_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_mspi_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_mspi_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_mspi_intr_map_reg_t;
-
-/** Type of core0_i2s_intr_map register
- *  I2S_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_i2s_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_i2s_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_i2s_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_i2s_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_i2s_intr_map_reg_t;
-
-/** Type of core0_uhci0_intr_map register
- *  UHCI0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_uhci0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_uhci0_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_uhci0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_uhci0_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_uhci0_intr_map_reg_t;
-
-/** Type of core0_uart0_intr_map register
- *  UART0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_uart0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_uart0_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_uart0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_uart0_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_uart0_intr_map_reg_t;
-
-/** Type of core0_uart1_intr_map register
- *  UART1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_uart1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_uart1_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_uart1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_uart1_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_uart1_intr_map_reg_t;
-
-/** Type of core0_ledc_intr_map register
- *  LEDC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_ledc_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_ledc_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_ledc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_ledc_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_ledc_intr_map_reg_t;
-
-/** Type of core0_can0_intr_map register
- *  CAN0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_can0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_can0_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_can0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_can0_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_can0_intr_map_reg_t;
-
-/** Type of core0_can0_timer_intr_map register
- *  CAN0_TIMER_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_can0_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_can0_timer_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_can0_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_can0_timer_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_can0_timer_intr_map_reg_t;
-
-/** Type of core0_usb_serial_jtag_intr_map register
- *  USB_SERIAL_JTAG_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_usb_serial_jtag_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_usb_serial_jtag_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_usb_serial_jtag_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_usb_serial_jtag_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_usb_serial_jtag_intr_map_reg_t;
-
-/** Type of core0_rmt_intr_map register
- *  RMT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_rmt_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_rmt_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_rmt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_rmt_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_rmt_intr_map_reg_t;
-
-/** Type of core0_i2c_ext0_intr_map register
- *  I2C_EXT0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_i2c_ext0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_i2c_ext0_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_i2c_ext0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_i2c_ext0_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_i2c_ext0_intr_map_reg_t;
-
-/** Type of core0_i2c_ext1_intr_map register
- *  I2C_EXT1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_i2c_ext1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_i2c_ext1_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_i2c_ext1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_i2c_ext1_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_i2c_ext1_intr_map_reg_t;
-
-/** Type of core0_tg0_t0_intr_map register
- *  TG0_T0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_tg0_t0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_tg0_t0_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_tg0_t0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_tg0_t0_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_tg0_t0_intr_map_reg_t;
-
-/** Type of core0_tg0_wdt_intr_map register
- *  TG0_WDT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_tg0_wdt_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_tg0_wdt_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_tg0_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_tg0_wdt_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_tg0_wdt_intr_map_reg_t;
-
-/** Type of core0_tg1_t0_intr_map register
- *  TG1_T0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_tg1_t0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_tg1_t0_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_tg1_t0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_tg1_t0_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_tg1_t0_intr_map_reg_t;
-
-/** Type of core0_tg1_wdt_intr_map register
- *  TG1_WDT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_tg1_wdt_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_tg1_wdt_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_tg1_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_tg1_wdt_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_tg1_wdt_intr_map_reg_t;
-
-/** Type of core0_systimer_target0_intr_map register
- *  SYSTIMER_TARGET0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_systimer_target0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_systimer_target0_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_systimer_target0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_systimer_target0_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_systimer_target0_intr_map_reg_t;
-
-/** Type of core0_systimer_target1_intr_map register
- *  SYSTIMER_TARGET1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_systimer_target1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_systimer_target1_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_systimer_target1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_systimer_target1_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_systimer_target1_intr_map_reg_t;
-
-/** Type of core0_systimer_target2_intr_map register
- *  SYSTIMER_TARGET2_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_systimer_target2_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_systimer_target2_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_systimer_target2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_systimer_target2_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_systimer_target2_intr_map_reg_t;
-
-/** Type of core0_apb_adc_intr_map register
- *  APB_ADC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_apb_adc_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_apb_adc_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_apb_adc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_apb_adc_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_apb_adc_intr_map_reg_t;
-
-/** Type of core0_pwm0_intr_map register
- *  PWM0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_pwm0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_pwm0_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_pwm0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_pwm0_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_pwm0_intr_map_reg_t;
-
-/** Type of core0_pwm1_intr_map register
- *  PWM1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_pwm1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_pwm1_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_pwm1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_pwm1_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_pwm1_intr_map_reg_t;
-
-/** Type of core0_pcnt_intr_map register
- *  PCNT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_pcnt_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_pcnt_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_pcnt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_pcnt_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_pcnt_intr_map_reg_t;
-
-/** Type of core0_parl_io_tx_intr_map register
- *  PARL_IO_TX_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_parl_io_tx_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_parl_io_tx_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_parl_io_tx_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_parl_io_tx_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_parl_io_tx_intr_map_reg_t;
-
-/** Type of core0_parl_io_rx_intr_map register
- *  PARL_IO_RX_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_parl_io_rx_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_parl_io_rx_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_parl_io_rx_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_parl_io_rx_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_parl_io_rx_intr_map_reg_t;
-
-/** Type of core0_usb_otg11_intr_map register
- *  USB_OTG11_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_usb_otg11_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_usb_otg11_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_usb_otg11_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_usb_otg11_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_usb_otg11_intr_map_reg_t;
-
-/** Type of core0_asrc_chnl0_intr_map register
- *  ASRC_CHNL0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_asrc_chnl0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_asrc_chnl0_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_asrc_chnl0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_asrc_chnl0_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_asrc_chnl0_intr_map_reg_t;
-
-/** Type of core0_asrc_chnl1_intr_map register
- *  ASRC_CHNL1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_asrc_chnl1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_asrc_chnl1_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_asrc_chnl1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_asrc_chnl1_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_asrc_chnl1_intr_map_reg_t;
-
-/** Type of core0_zero_det_intr_map register
- *  ZERO_DET_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_zero_det_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_zero_det_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_zero_det_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_zero_det_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_zero_det_intr_map_reg_t;
-
-/** Type of core0_dma_in_ch0_intr_map register
- *  DMA_IN_CH0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_dma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_dma_in_ch0_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_dma_in_ch0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_dma_in_ch0_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_dma_in_ch0_intr_map_reg_t;
-
-/** Type of core0_dma_in_ch1_intr_map register
- *  DMA_IN_CH1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_dma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_dma_in_ch1_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_dma_in_ch1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_dma_in_ch1_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_dma_in_ch1_intr_map_reg_t;
-
-/** Type of core0_dma_in_ch2_intr_map register
- *  DMA_IN_CH2_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_dma_in_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_dma_in_ch2_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_dma_in_ch2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_dma_in_ch2_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_dma_in_ch2_intr_map_reg_t;
-
-/** Type of core0_dma_in_ch3_intr_map register
- *  DMA_IN_CH3_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_dma_in_ch3_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_dma_in_ch3_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_dma_in_ch3_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_dma_in_ch3_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_dma_in_ch3_intr_map_reg_t;
-
-/** Type of core0_dma_in_ch4_intr_map register
- *  DMA_IN_CH4_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_dma_in_ch4_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_dma_in_ch4_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_dma_in_ch4_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_dma_in_ch4_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_dma_in_ch4_intr_map_reg_t;
-
-/** Type of core0_dma_out_ch0_intr_map register
- *  DMA_OUT_CH0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_dma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_dma_out_ch0_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_dma_out_ch0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_dma_out_ch0_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_dma_out_ch0_intr_map_reg_t;
-
-/** Type of core0_dma_out_ch1_intr_map register
- *  DMA_OUT_CH1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_dma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_dma_out_ch1_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_dma_out_ch1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_dma_out_ch1_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_dma_out_ch1_intr_map_reg_t;
-
-/** Type of core0_dma_out_ch2_intr_map register
- *  DMA_OUT_CH2_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_dma_out_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_dma_out_ch2_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_dma_out_ch2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_dma_out_ch2_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_dma_out_ch2_intr_map_reg_t;
-
-/** Type of core0_dma_out_ch3_intr_map register
- *  DMA_OUT_CH3_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_dma_out_ch3_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_dma_out_ch3_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_dma_out_ch3_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_dma_out_ch3_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_dma_out_ch3_intr_map_reg_t;
-
-/** Type of core0_dma_out_ch4_intr_map register
- *  DMA_OUT_CH4_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_dma_out_ch4_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_dma_out_ch4_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_dma_out_ch4_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_dma_out_ch4_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_dma_out_ch4_intr_map_reg_t;
-
-/** Type of core0_gpspi2_intr_map register
- *  GPSPI2_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_gpspi2_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_gpspi2_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_gpspi2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_gpspi2_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_gpspi2_intr_map_reg_t;
-
-/** Type of core0_gpspi3_intr_map register
- *  GPSPI3_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_gpspi3_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_gpspi3_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_gpspi3_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_gpspi3_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_gpspi3_intr_map_reg_t;
-
-/** Type of core0_aes_intr_map register
- *  AES_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_aes_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_aes_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_aes_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_aes_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_aes_intr_map_reg_t;
-
-/** Type of core0_sha_intr_map register
- *  SHA_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_sha_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_sha_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_sha_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_sha_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_sha_intr_map_reg_t;
-
-/** Type of core0_ecc_intr_map register
- *  ECC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_ecc_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_ecc_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_ecc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_ecc_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_ecc_intr_map_reg_t;
-
-/** Type of core0_ecdsa_intr_map register
- *  ECDSA_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_ecdsa_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_ecdsa_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_ecdsa_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_ecdsa_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_ecdsa_intr_map_reg_t;
-
-/** Type of core0_km_intr_map register
- *  KM_INTR mapping register
- */
-typedef union {
-    struct {
-        /** core0_km_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t core0_km_intr_map:6;
-        uint32_t reserved_6:2;
-        /** core0_km_intr_pass_in_sec : R/W; bitpos: [8]; default: 0;
-         *  Configures the PASS_IN_SEC flag of the interrupt source.
-         */
-        uint32_t core0_km_intr_pass_in_sec:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} interrupt_core0_km_intr_map_reg_t;
-
-/** Type of core0_sig_idx_assert_in_sec register
- *  reserved
- */
-typedef union {
-    struct {
-        /** core0_int_sig_idx_assert_in_sec : R/W; bitpos: [5:0]; default: 0;
-         *  reserved
-         */
-        uint32_t core0_int_sig_idx_assert_in_sec:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_sig_idx_assert_in_sec_reg_t;
-
-/** Type of core0_clock_gate register
- *  Interrupt clock gating configure register
- */
-typedef union {
-    struct {
-        /** core0_reg_clk_en : R/W; bitpos: [0]; default: 0;
-         *  Interrupt clock gating configure register
-         */
-        uint32_t core0_reg_clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} interrupt_core0_clock_gate_reg_t;
-
-
-/** Group: Status Registers */
-/** Type of core0_int_status_reg_0 register
- *  Status register for interrupt sources 0 ~ 31
- */
-typedef union {
-    struct {
-        /** core0_int_status_0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31.
-         *  Each bit corresponds to one interrupt source
-         *  0:The corresponding interrupt source triggered an interrupt
-         *  1:No interrupt triggered
-         */
-        uint32_t core0_int_status_0:32;
-    };
-    uint32_t val;
-} interrupt_core0_int_status_reg_0_reg_t;
-
-/** Type of core0_int_status_reg_1 register
- *  Status register for interrupt sources 32 ~ 63
- */
-typedef union {
-    struct {
-        /** core0_int_status_1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the status of the interrupt sources within interrupt-index-range 32 ~
-         *  63. Each bit corresponds to one interrupt source
-         *  0:The corresponding interrupt source triggered an interrupt
-         *  1:No interrupt triggered
-         */
-        uint32_t core0_int_status_1:32;
-    };
-    uint32_t val;
-} interrupt_core0_int_status_reg_1_reg_t;
-
-/** Type of core0_int_status_reg_2 register
- *  Status register for interrupt sources 64 ~ 89
- */
-typedef union {
-    struct {
-        /** core0_int_status_2 : RO; bitpos: [25:0]; default: 0;
-         *  Represents the status of the interrupt sources within interrupt-index-range 64 ~
-         *  89. Each bit corresponds to one interrupt source
-         *  0:The corresponding interrupt source triggered an interrupt
-         *  1:No interrupt triggered
-         */
-        uint32_t core0_int_status_2:26;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} interrupt_core0_int_status_reg_2_reg_t;
-
-/** Type of core0_src_pass_in_sec_status_0 register
- *  PASS_IN_SEC status register for interrupt sources 0 ~ 31
- */
-typedef union {
-    struct {
-        /** core0_int_src_pass_in_sec_status_0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the PASS_IN_SEC status of the interrupt sources within
-         *  interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source
-         *  0:The corresponding interrupt source is not PASS_IN_SEC.
-         *  1:The corresponding interrupt source is PASS_IN_SEC.
-         */
-        uint32_t core0_int_src_pass_in_sec_status_0:32;
-    };
-    uint32_t val;
-} interrupt_core0_src_pass_in_sec_status_0_reg_t;
-
-/** Type of core0_src_pass_in_sec_status_1 register
- *  PASS_IN_SEC status register for interrupt sources 32 ~ 63
- */
-typedef union {
-    struct {
-        /** core0_int_src_pass_in_sec_status_1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the PASS_IN_SEC status of the interrupt sources within
-         *  interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source
-         *  0:The corresponding interrupt source is not PASS_IN_SEC.
-         *  1:The corresponding interrupt source is PASS_IN_SEC.
-         */
-        uint32_t core0_int_src_pass_in_sec_status_1:32;
-    };
-    uint32_t val;
-} interrupt_core0_src_pass_in_sec_status_1_reg_t;
-
-/** Type of core0_src_pass_in_sec_status_2 register
- *  PASS_IN_SEC status register for interrupt sources 64 ~ 89
- */
-typedef union {
-    struct {
-        /** core0_int_src_pass_in_sec_status_2 : RO; bitpos: [25:0]; default: 0;
-         *  Represents the PASS_IN_SEC status of the interrupt sources with
-         *  interrupt-index-range 64 ~ 89. Each bit corresponds to one interrupt source
-         *  0:The corresponding interrupt source is not PASS_IN_SEC.
-         *  1:The corresponding interrupt source is PASS_IN_SEC.
-         */
-        uint32_t core0_int_src_pass_in_sec_status_2:26;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} interrupt_core0_src_pass_in_sec_status_2_reg_t;
-
-/** Type of core0_secure_status register
- *  reserved
- */
-typedef union {
-    struct {
-        /** core0_int_secure_status : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t core0_int_secure_status:32;
-    };
-    uint32_t val;
-} interrupt_core0_secure_status_reg_t;
-
-
-/** Group: Version Register */
-/** Type of core0_interrupt_date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** core0_interrupt_date : R/W; bitpos: [27:0]; default: 37822544;
-         *  Version control register
-         */
-        uint32_t core0_interrupt_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} interrupt_core0_interrupt_date_reg_t;
-
-
-typedef struct {
-    volatile interrupt_core0_wifi_mac_intr_map_reg_t core0_wifi_mac_intr_map;
-    volatile interrupt_core0_wifi_mac_nmi_map_reg_t core0_wifi_mac_nmi_map;
-    volatile interrupt_core0_wifi_pwr_intr_map_reg_t core0_wifi_pwr_intr_map;
-    volatile interrupt_core0_wifi_bb_intr_map_reg_t core0_wifi_bb_intr_map;
-    volatile interrupt_core0_bt_mac_intr_map_reg_t core0_bt_mac_intr_map;
-    volatile interrupt_core0_bt_bb_intr_map_reg_t core0_bt_bb_intr_map;
-    volatile interrupt_core0_bt_bb_nmi_map_reg_t core0_bt_bb_nmi_map;
-    volatile interrupt_core0_lp_timer_intr_map_reg_t core0_lp_timer_intr_map;
-    volatile interrupt_core0_coex_intr_map_reg_t core0_coex_intr_map;
-    volatile interrupt_core0_ble_timer_intr_map_reg_t core0_ble_timer_intr_map;
-    volatile interrupt_core0_ble_sec_intr_map_reg_t core0_ble_sec_intr_map;
-    volatile interrupt_core0_i2c_mst_intr_map_reg_t core0_i2c_mst_intr_map;
-    volatile interrupt_core0_zb_mac_intr_map_reg_t core0_zb_mac_intr_map;
-    volatile interrupt_core0_modem_apb_timeout_intr_map_reg_t core0_modem_apb_timeout_intr_map;
-    volatile interrupt_core0_bt_mac_int1_map_reg_t core0_bt_mac_int1_map;
-    volatile interrupt_core0_pmu_intr_map_reg_t core0_pmu_intr_map;
-    volatile interrupt_core0_efuse_intr_map_reg_t core0_efuse_intr_map;
-    volatile interrupt_core0_lp_rtc_timer_intr_map_reg_t core0_lp_rtc_timer_intr_map;
-    volatile interrupt_core0_lp_rtc_ble_timer_intr_map_reg_t core0_lp_rtc_ble_timer_intr_map;
-    volatile interrupt_core0_lp_wdt_intr_map_reg_t core0_lp_wdt_intr_map;
-    volatile interrupt_core0_touch_intr_map_reg_t core0_touch_intr_map;
-    volatile interrupt_core0_huk_intr_map_reg_t core0_huk_intr_map;
-    volatile interrupt_core0_cpu_intr_from_cpu_0_map_reg_t core0_cpu_intr_from_cpu_0_map;
-    volatile interrupt_core0_cpu_intr_from_cpu_1_map_reg_t core0_cpu_intr_from_cpu_1_map;
-    volatile interrupt_core0_cpu_intr_from_cpu_2_map_reg_t core0_cpu_intr_from_cpu_2_map;
-    volatile interrupt_core0_cpu_intr_from_cpu_3_map_reg_t core0_cpu_intr_from_cpu_3_map;
-    volatile interrupt_core0_bus_monitor_intr_map_reg_t core0_bus_monitor_intr_map;
-    volatile interrupt_core0_core0_trace_intr_map_reg_t core0_core0_trace_intr_map;
-    volatile interrupt_core0_core1_trace_intr_map_reg_t core0_core1_trace_intr_map;
-    volatile interrupt_core0_cache_intr_map_reg_t core0_cache_intr_map;
-    volatile interrupt_core0_cpu_peri_timeout_intr_map_reg_t core0_cpu_peri_timeout_intr_map;
-    volatile interrupt_core0_gpio_interrupt_pro_map_reg_t core0_gpio_interrupt_pro_map;
-    volatile interrupt_core0_gpio_interrupt_2_map_reg_t core0_gpio_interrupt_2_map;
-    volatile interrupt_core0_pau_intr_map_reg_t core0_pau_intr_map;
-    volatile interrupt_core0_hp_peri_timeout_intr_map_reg_t core0_hp_peri_timeout_intr_map;
-    volatile interrupt_core0_hp_apm_m0_intr_map_reg_t core0_hp_apm_m0_intr_map;
-    volatile interrupt_core0_hp_apm_m1_intr_map_reg_t core0_hp_apm_m1_intr_map;
-    volatile interrupt_core0_hp_apm_m2_intr_map_reg_t core0_hp_apm_m2_intr_map;
-    volatile interrupt_core0_hp_apm_m3_intr_map_reg_t core0_hp_apm_m3_intr_map;
-    volatile interrupt_core0_hp_apm_m4_intr_map_reg_t core0_hp_apm_m4_intr_map;
-    volatile interrupt_core0_cpu_apm_m0_intr_map_reg_t core0_cpu_apm_m0_intr_map;
-    volatile interrupt_core0_cpu_apm_m1_intr_map_reg_t core0_cpu_apm_m1_intr_map;
-    volatile interrupt_core0_cpu_apm_m2_intr_map_reg_t core0_cpu_apm_m2_intr_map;
-    volatile interrupt_core0_cpu_apm_m3_intr_map_reg_t core0_cpu_apm_m3_intr_map;
-    volatile interrupt_core0_mspi_intr_map_reg_t core0_mspi_intr_map;
-    volatile interrupt_core0_i2s_intr_map_reg_t core0_i2s_intr_map;
-    volatile interrupt_core0_uhci0_intr_map_reg_t core0_uhci0_intr_map;
-    volatile interrupt_core0_uart0_intr_map_reg_t core0_uart0_intr_map;
-    volatile interrupt_core0_uart1_intr_map_reg_t core0_uart1_intr_map;
-    volatile interrupt_core0_ledc_intr_map_reg_t core0_ledc_intr_map;
-    volatile interrupt_core0_can0_intr_map_reg_t core0_can0_intr_map;
-    volatile interrupt_core0_can0_timer_intr_map_reg_t core0_can0_timer_intr_map;
-    volatile interrupt_core0_usb_serial_jtag_intr_map_reg_t core0_usb_serial_jtag_intr_map;
-    volatile interrupt_core0_rmt_intr_map_reg_t core0_rmt_intr_map;
-    volatile interrupt_core0_i2c_ext0_intr_map_reg_t core0_i2c_ext0_intr_map;
-    volatile interrupt_core0_i2c_ext1_intr_map_reg_t core0_i2c_ext1_intr_map;
-    volatile interrupt_core0_tg0_t0_intr_map_reg_t core0_tg0_t0_intr_map;
-    volatile interrupt_core0_tg0_wdt_intr_map_reg_t core0_tg0_wdt_intr_map;
-    volatile interrupt_core0_tg1_t0_intr_map_reg_t core0_tg1_t0_intr_map;
-    volatile interrupt_core0_tg1_wdt_intr_map_reg_t core0_tg1_wdt_intr_map;
-    volatile interrupt_core0_systimer_target0_intr_map_reg_t core0_systimer_target0_intr_map;
-    volatile interrupt_core0_systimer_target1_intr_map_reg_t core0_systimer_target1_intr_map;
-    volatile interrupt_core0_systimer_target2_intr_map_reg_t core0_systimer_target2_intr_map;
-    volatile interrupt_core0_apb_adc_intr_map_reg_t core0_apb_adc_intr_map;
-    volatile interrupt_core0_pwm0_intr_map_reg_t core0_pwm0_intr_map;
-    volatile interrupt_core0_pwm1_intr_map_reg_t core0_pwm1_intr_map;
-    volatile interrupt_core0_pcnt_intr_map_reg_t core0_pcnt_intr_map;
-    volatile interrupt_core0_parl_io_tx_intr_map_reg_t core0_parl_io_tx_intr_map;
-    volatile interrupt_core0_parl_io_rx_intr_map_reg_t core0_parl_io_rx_intr_map;
-    volatile interrupt_core0_usb_otg11_intr_map_reg_t core0_usb_otg11_intr_map;
-    volatile interrupt_core0_asrc_chnl0_intr_map_reg_t core0_asrc_chnl0_intr_map;
-    volatile interrupt_core0_asrc_chnl1_intr_map_reg_t core0_asrc_chnl1_intr_map;
-    volatile interrupt_core0_zero_det_intr_map_reg_t core0_zero_det_intr_map;
-    volatile interrupt_core0_dma_in_ch0_intr_map_reg_t core0_dma_in_ch0_intr_map;
-    volatile interrupt_core0_dma_in_ch1_intr_map_reg_t core0_dma_in_ch1_intr_map;
-    volatile interrupt_core0_dma_in_ch2_intr_map_reg_t core0_dma_in_ch2_intr_map;
-    volatile interrupt_core0_dma_in_ch3_intr_map_reg_t core0_dma_in_ch3_intr_map;
-    volatile interrupt_core0_dma_in_ch4_intr_map_reg_t core0_dma_in_ch4_intr_map;
-    volatile interrupt_core0_dma_out_ch0_intr_map_reg_t core0_dma_out_ch0_intr_map;
-    volatile interrupt_core0_dma_out_ch1_intr_map_reg_t core0_dma_out_ch1_intr_map;
-    volatile interrupt_core0_dma_out_ch2_intr_map_reg_t core0_dma_out_ch2_intr_map;
-    volatile interrupt_core0_dma_out_ch3_intr_map_reg_t core0_dma_out_ch3_intr_map;
-    volatile interrupt_core0_dma_out_ch4_intr_map_reg_t core0_dma_out_ch4_intr_map;
-    volatile interrupt_core0_gpspi2_intr_map_reg_t core0_gpspi2_intr_map;
-    volatile interrupt_core0_gpspi3_intr_map_reg_t core0_gpspi3_intr_map;
-    volatile interrupt_core0_aes_intr_map_reg_t core0_aes_intr_map;
-    volatile interrupt_core0_sha_intr_map_reg_t core0_sha_intr_map;
-    volatile interrupt_core0_ecc_intr_map_reg_t core0_ecc_intr_map;
-    volatile interrupt_core0_ecdsa_intr_map_reg_t core0_ecdsa_intr_map;
-    volatile interrupt_core0_km_intr_map_reg_t core0_km_intr_map;
-    volatile interrupt_core0_int_status_reg_0_reg_t core0_int_status_reg_0;
-    volatile interrupt_core0_int_status_reg_1_reg_t core0_int_status_reg_1;
-    volatile interrupt_core0_int_status_reg_2_reg_t core0_int_status_reg_2;
-    volatile interrupt_core0_src_pass_in_sec_status_0_reg_t core0_src_pass_in_sec_status_0;
-    volatile interrupt_core0_src_pass_in_sec_status_1_reg_t core0_src_pass_in_sec_status_1;
-    volatile interrupt_core0_src_pass_in_sec_status_2_reg_t core0_src_pass_in_sec_status_2;
-    volatile interrupt_core0_sig_idx_assert_in_sec_reg_t core0_sig_idx_assert_in_sec;
-    volatile interrupt_core0_secure_status_reg_t core0_secure_status;
-    volatile interrupt_core0_clock_gate_reg_t core0_clock_gate;
-    uint32_t reserved_18c[412];
-    volatile interrupt_core0_interrupt_date_reg_t core0_interrupt_date;
-} interrupt_dev_t;
-
-extern interrupt_dev_t INTMTX0;
-extern interrupt_dev_t INTMTX1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(interrupt_dev_t) == 0x800, "Invalid size of interrupt_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h4/register/hw_ver_beta5/soc/pmu_reg.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/pmu_reg.h
deleted file mode 100644
index 769c39adb0..0000000000
--- a/components/soc/esp32h4/register/hw_ver_beta5/soc/pmu_reg.h
+++ /dev/null
@@ -1,3766 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0 OR MIT
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** PMU_HP_ACTIVE_DIG_POWER_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0)
-/** PMU_HP_ACTIVE_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_VDD_FLASH_MODE    0x0000000FU
-#define PMU_HP_ACTIVE_VDD_FLASH_MODE_M  (PMU_HP_ACTIVE_VDD_FLASH_MODE_V << PMU_HP_ACTIVE_VDD_FLASH_MODE_S)
-#define PMU_HP_ACTIVE_VDD_FLASH_MODE_V  0x0000000FU
-#define PMU_HP_ACTIVE_VDD_FLASH_MODE_S  18
-/** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_MEM_DSLP    (BIT(22))
-#define PMU_HP_ACTIVE_HP_MEM_DSLP_M  (PMU_HP_ACTIVE_HP_MEM_DSLP_V << PMU_HP_ACTIVE_HP_MEM_DSLP_S)
-#define PMU_HP_ACTIVE_HP_MEM_DSLP_V  0x00000001U
-#define PMU_HP_ACTIVE_HP_MEM_DSLP_S  22
-/** PMU_HP_ACTIVE_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN    0x0000000FU
-#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M  (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S)
-#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V  0x0000000FU
-#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S  23
-/** PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN    (BIT(27))
-#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_M  (PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S)
-#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S  27
-/** PMU_HP_ACTIVE_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN    (BIT(28))
-#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_M  (PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S)
-#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S  28
-/** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN    (BIT(29))
-#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_M  (PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V << PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S)
-#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S  29
-/** PMU_HP_ACTIVE_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN    (BIT(30))
-#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_M  (PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V << PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S)
-#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S  30
-/** PMU_HP_ACTIVE_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_PD_TOP_PD_EN    (BIT(31))
-#define PMU_HP_ACTIVE_PD_TOP_PD_EN_M  (PMU_HP_ACTIVE_PD_TOP_PD_EN_V << PMU_HP_ACTIVE_PD_TOP_PD_EN_S)
-#define PMU_HP_ACTIVE_PD_TOP_PD_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_PD_TOP_PD_EN_S  31
-
-/** PMU_HP_ACTIVE_ICG_HP_FUNC_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x4)
-/** PMU_HP_ACTIVE_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN    0xFFFFFFFFU
-#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_M  (PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V << PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S)
-#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V  0xFFFFFFFFU
-#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S  0
-
-/** PMU_HP_ACTIVE_ICG_HP_APB_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x8)
-/** PMU_HP_ACTIVE_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_ICG_APB_EN    0xFFFFFFFFU
-#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_M  (PMU_HP_ACTIVE_DIG_ICG_APB_EN_V << PMU_HP_ACTIVE_DIG_ICG_APB_EN_S)
-#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_V  0xFFFFFFFFU
-#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_S  0
-
-/** PMU_HP_ACTIVE_ICG_MODEM_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_ICG_MODEM_REG (DR_REG_PMU_BASE + 0xc)
-/** PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE    0x00000003U
-#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_M  (PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V << PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S)
-#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V  0x00000003U
-#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S  30
-
-/** PMU_HP_ACTIVE_HP_SYS_CNTL_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x10)
-/** PMU_HP_ACTIVE_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_UART_WAKEUP_EN    (BIT(24))
-#define PMU_HP_ACTIVE_UART_WAKEUP_EN_M  (PMU_HP_ACTIVE_UART_WAKEUP_EN_V << PMU_HP_ACTIVE_UART_WAKEUP_EN_S)
-#define PMU_HP_ACTIVE_UART_WAKEUP_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_UART_WAKEUP_EN_S  24
-/** PMU_HP_ACTIVE_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL    (BIT(25))
-#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_M  (PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S)
-#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S  25
-/** PMU_HP_ACTIVE_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL    (BIT(26))
-#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_M  (PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S)
-#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S  26
-/** PMU_HP_ACTIVE_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL    (BIT(27))
-#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_M  (PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V << PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S)
-#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V  0x00000001U
-#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S  27
-/** PMU_HP_ACTIVE_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_PAUSE_WDT    (BIT(28))
-#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_M  (PMU_HP_ACTIVE_DIG_PAUSE_WDT_V << PMU_HP_ACTIVE_DIG_PAUSE_WDT_S)
-#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_V  0x00000001U
-#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_S  28
-/** PMU_HP_ACTIVE_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_CPU_STALL    (BIT(29))
-#define PMU_HP_ACTIVE_DIG_CPU_STALL_M  (PMU_HP_ACTIVE_DIG_CPU_STALL_V << PMU_HP_ACTIVE_DIG_CPU_STALL_S)
-#define PMU_HP_ACTIVE_DIG_CPU_STALL_V  0x00000001U
-#define PMU_HP_ACTIVE_DIG_CPU_STALL_S  29
-
-/** PMU_HP_ACTIVE_HP_CK_POWER_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x14)
-/** PMU_HP_ACTIVE_I2C_ISO_EN : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_I2C_ISO_EN    (BIT(26))
-#define PMU_HP_ACTIVE_I2C_ISO_EN_M  (PMU_HP_ACTIVE_I2C_ISO_EN_V << PMU_HP_ACTIVE_I2C_ISO_EN_S)
-#define PMU_HP_ACTIVE_I2C_ISO_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_I2C_ISO_EN_S  26
-/** PMU_HP_ACTIVE_I2C_RETENTION : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_I2C_RETENTION    (BIT(27))
-#define PMU_HP_ACTIVE_I2C_RETENTION_M  (PMU_HP_ACTIVE_I2C_RETENTION_V << PMU_HP_ACTIVE_I2C_RETENTION_S)
-#define PMU_HP_ACTIVE_I2C_RETENTION_V  0x00000001U
-#define PMU_HP_ACTIVE_I2C_RETENTION_S  27
-/** PMU_HP_ACTIVE_XPD_BB_I2C : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_XPD_BB_I2C    (BIT(28))
-#define PMU_HP_ACTIVE_XPD_BB_I2C_M  (PMU_HP_ACTIVE_XPD_BB_I2C_V << PMU_HP_ACTIVE_XPD_BB_I2C_S)
-#define PMU_HP_ACTIVE_XPD_BB_I2C_V  0x00000001U
-#define PMU_HP_ACTIVE_XPD_BB_I2C_S  28
-/** PMU_HP_ACTIVE_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_XPD_BBPLL_I2C    (BIT(29))
-#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_M  (PMU_HP_ACTIVE_XPD_BBPLL_I2C_V << PMU_HP_ACTIVE_XPD_BBPLL_I2C_S)
-#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_V  0x00000001U
-#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_S  29
-/** PMU_HP_ACTIVE_XPD_BBPLL : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_XPD_BBPLL    (BIT(30))
-#define PMU_HP_ACTIVE_XPD_BBPLL_M  (PMU_HP_ACTIVE_XPD_BBPLL_V << PMU_HP_ACTIVE_XPD_BBPLL_S)
-#define PMU_HP_ACTIVE_XPD_BBPLL_V  0x00000001U
-#define PMU_HP_ACTIVE_XPD_BBPLL_S  30
-
-/** PMU_HP_ACTIVE_BIAS_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18)
-/** PMU_HP_ACTIVE_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DCDC_CCM_ENB    (BIT(9))
-#define PMU_HP_ACTIVE_DCDC_CCM_ENB_M  (PMU_HP_ACTIVE_DCDC_CCM_ENB_V << PMU_HP_ACTIVE_DCDC_CCM_ENB_S)
-#define PMU_HP_ACTIVE_DCDC_CCM_ENB_V  0x00000001U
-#define PMU_HP_ACTIVE_DCDC_CCM_ENB_S  9
-/** PMU_HP_ACTIVE_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY    (BIT(10))
-#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_M  (PMU_HP_ACTIVE_DCDC_CLEAR_RDY_V << PMU_HP_ACTIVE_DCDC_CLEAR_RDY_S)
-#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_V  0x00000001U
-#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_S  10
-/** PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 3;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS    0x00000003U
-#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_M  (PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_V << PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_S)
-#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_V  0x00000003U
-#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_S  11
-/** PMU_HP_ACTIVE_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 6;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS    0x0000000FU
-#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_M  (PMU_HP_ACTIVE_DIG_PMU_DSFMOS_V << PMU_HP_ACTIVE_DIG_PMU_DSFMOS_S)
-#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_V  0x0000000FU
-#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_S  13
-/** PMU_HP_ACTIVE_DCM_VSET : R/W; bitpos: [21:17]; default: 23;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DCM_VSET    0x0000001FU
-#define PMU_HP_ACTIVE_DCM_VSET_M  (PMU_HP_ACTIVE_DCM_VSET_V << PMU_HP_ACTIVE_DCM_VSET_S)
-#define PMU_HP_ACTIVE_DCM_VSET_V  0x0000001FU
-#define PMU_HP_ACTIVE_DCM_VSET_S  17
-/** PMU_HP_ACTIVE_DCM_MODE : R/W; bitpos: [23:22]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DCM_MODE    0x00000003U
-#define PMU_HP_ACTIVE_DCM_MODE_M  (PMU_HP_ACTIVE_DCM_MODE_V << PMU_HP_ACTIVE_DCM_MODE_S)
-#define PMU_HP_ACTIVE_DCM_MODE_V  0x00000003U
-#define PMU_HP_ACTIVE_DCM_MODE_S  22
-/** PMU_HP_ACTIVE_XPD_TRX : R/W; bitpos: [24]; default: 1;
- *  need_des
- */
-#define PMU_HP_ACTIVE_XPD_TRX    (BIT(24))
-#define PMU_HP_ACTIVE_XPD_TRX_M  (PMU_HP_ACTIVE_XPD_TRX_V << PMU_HP_ACTIVE_XPD_TRX_S)
-#define PMU_HP_ACTIVE_XPD_TRX_V  0x00000001U
-#define PMU_HP_ACTIVE_XPD_TRX_S  24
-/** PMU_HP_ACTIVE_XPD_BIAS : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_XPD_BIAS    (BIT(25))
-#define PMU_HP_ACTIVE_XPD_BIAS_M  (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S)
-#define PMU_HP_ACTIVE_XPD_BIAS_V  0x00000001U
-#define PMU_HP_ACTIVE_XPD_BIAS_S  25
-/** PMU_HP_ACTIVE_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC    (BIT(29))
-#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_M  (PMU_HP_ACTIVE_DISCNNT_DIG_RTC_V << PMU_HP_ACTIVE_DISCNNT_DIG_RTC_S)
-#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_V  0x00000001U
-#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_S  29
-/** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_PD_CUR    (BIT(30))
-#define PMU_HP_ACTIVE_PD_CUR_M  (PMU_HP_ACTIVE_PD_CUR_V << PMU_HP_ACTIVE_PD_CUR_S)
-#define PMU_HP_ACTIVE_PD_CUR_V  0x00000001U
-#define PMU_HP_ACTIVE_PD_CUR_S  30
-/** PMU_HP_ACTIVE_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_BIAS_SLEEP    (BIT(31))
-#define PMU_HP_ACTIVE_BIAS_SLEEP_M  (PMU_HP_ACTIVE_BIAS_SLEEP_V << PMU_HP_ACTIVE_BIAS_SLEEP_S)
-#define PMU_HP_ACTIVE_BIAS_SLEEP_V  0x00000001U
-#define PMU_HP_ACTIVE_BIAS_SLEEP_S  31
-
-/** PMU_HP_ACTIVE_BACKUP_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_BACKUP_REG (DR_REG_PMU_BASE + 0x1c)
-/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE    0x00000003U
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S)
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V  0x00000003U
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S  4
-/** PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE    0x00000003U
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S)
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V  0x00000003U
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S  6
-/** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL    0x00000003U
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S)
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V  0x00000003U
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S  14
-/** PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL    0x00000003U
-#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M  (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S)
-#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V  0x00000003U
-#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S  16
-/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:18]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE    0x0000001FU
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S)
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V  0x0000001FU
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S  18
-/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [27:23]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE    0x0000001FU
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M  (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S)
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V  0x0000001FU
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S  23
-/** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN    (BIT(29))
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V << PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S)
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V  0x00000001U
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S  29
-/** PMU_HP_MODEM2ACTIVE_BACKUP_EN : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2ACTIVE_BACKUP_EN    (BIT(30))
-#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_M  (PMU_HP_MODEM2ACTIVE_BACKUP_EN_V << PMU_HP_MODEM2ACTIVE_BACKUP_EN_S)
-#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_V  0x00000001U
-#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_S  30
-
-/** PMU_HP_ACTIVE_BACKUP_CLK_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x20)
-/** PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN    0xFFFFFFFFU
-#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_M  (PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V << PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S)
-#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V  0xFFFFFFFFU
-#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S  0
-
-/** PMU_HP_ACTIVE_SYSCLK_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_SYSCLK_REG (DR_REG_PMU_BASE + 0x24)
-/** PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV    (BIT(26))
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_M  (PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V << PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S)
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V  0x00000001U
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S  26
-/** PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN    (BIT(27))
-#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_M  (PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V << PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S)
-#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S  27
-/** PMU_HP_ACTIVE_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL    (BIT(28))
-#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_M  (PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V << PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S)
-#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V  0x00000001U
-#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S  28
-/** PMU_HP_ACTIVE_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_ICG_SLP_SEL    (BIT(29))
-#define PMU_HP_ACTIVE_ICG_SLP_SEL_M  (PMU_HP_ACTIVE_ICG_SLP_SEL_V << PMU_HP_ACTIVE_ICG_SLP_SEL_S)
-#define PMU_HP_ACTIVE_ICG_SLP_SEL_V  0x00000001U
-#define PMU_HP_ACTIVE_ICG_SLP_SEL_S  29
-/** PMU_HP_ACTIVE_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL    0x00000003U
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_M  (PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V << PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S)
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V  0x00000003U
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S  30
-
-/** PMU_HP_ACTIVE_HP_REGULATOR0_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28)
-/** PMU_HP_ACTIVE_HP_POWER_DET_BYPASS : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS    (BIT(0))
-#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_M  (PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V << PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S)
-#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V  0x00000001U
-#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S  0
-/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24;
- *  need_des
- */
-#define PMU_LP_DBIAS_VOL    0x0000001FU
-#define PMU_LP_DBIAS_VOL_M  (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S)
-#define PMU_LP_DBIAS_VOL_V  0x0000001FU
-#define PMU_LP_DBIAS_VOL_S  4
-/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24;
- *  need_des
- */
-#define PMU_HP_DBIAS_VOL    0x0000001FU
-#define PMU_HP_DBIAS_VOL_M  (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S)
-#define PMU_HP_DBIAS_VOL_V  0x0000001FU
-#define PMU_HP_DBIAS_VOL_S  9
-/** PMU_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [14]; default: 1;
- *  need_des
- */
-#define PMU_DIG_REGULATOR0_DBIAS_SEL    (BIT(14))
-#define PMU_DIG_REGULATOR0_DBIAS_SEL_M  (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S)
-#define PMU_DIG_REGULATOR0_DBIAS_SEL_V  0x00000001U
-#define PMU_DIG_REGULATOR0_DBIAS_SEL_S  14
-/** PMU_DIG_DBIAS_INIT : WT; bitpos: [15]; default: 0;
- *  need_des
- */
-#define PMU_DIG_DBIAS_INIT    (BIT(15))
-#define PMU_DIG_DBIAS_INIT_M  (PMU_DIG_DBIAS_INIT_V << PMU_DIG_DBIAS_INIT_S)
-#define PMU_DIG_DBIAS_INIT_V  0x00000001U
-#define PMU_DIG_DBIAS_INIT_S  15
-/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD    (BIT(16))
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S)
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V  0x00000001U
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S  16
-/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD    (BIT(17))
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S)
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V  0x00000001U
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S  17
-/** PMU_HP_ACTIVE_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR_XPD    (BIT(18))
-#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M  (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S)
-#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V  0x00000001U
-#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_S  18
-/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 8;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS    0x0000000FU
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S)
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V  0x0000000FU
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S  19
-/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 8;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS    0x0000000FU
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S)
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V  0x0000000FU
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S  23
-/** PMU_HP_ACTIVE_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 16;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS    0x0000001FU
-#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_M  (PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S)
-#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V  0x0000001FU
-#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S  27
-
-/** PMU_HP_ACTIVE_HP_REGULATOR1_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c)
-/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B    0x00FFFFFFU
-#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_M  (PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V << PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S)
-#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V  0x00FFFFFFU
-#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S  8
-
-/** PMU_HP_ACTIVE_XTAL_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30)
-/** PMU_HP_ACTIVE_XPD_XTALX2 : R/W; bitpos: [30]; default: 1;
- *  need_des
- */
-#define PMU_HP_ACTIVE_XPD_XTALX2    (BIT(30))
-#define PMU_HP_ACTIVE_XPD_XTALX2_M  (PMU_HP_ACTIVE_XPD_XTALX2_V << PMU_HP_ACTIVE_XPD_XTALX2_S)
-#define PMU_HP_ACTIVE_XPD_XTALX2_V  0x00000001U
-#define PMU_HP_ACTIVE_XPD_XTALX2_S  30
-/** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define PMU_HP_ACTIVE_XPD_XTAL    (BIT(31))
-#define PMU_HP_ACTIVE_XPD_XTAL_M  (PMU_HP_ACTIVE_XPD_XTAL_V << PMU_HP_ACTIVE_XPD_XTAL_S)
-#define PMU_HP_ACTIVE_XPD_XTAL_V  0x00000001U
-#define PMU_HP_ACTIVE_XPD_XTAL_S  31
-
-/** PMU_HP_SLEEP_DIG_POWER_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68)
-/** PMU_HP_SLEEP_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_VDD_FLASH_MODE    0x0000000FU
-#define PMU_HP_SLEEP_VDD_FLASH_MODE_M  (PMU_HP_SLEEP_VDD_FLASH_MODE_V << PMU_HP_SLEEP_VDD_FLASH_MODE_S)
-#define PMU_HP_SLEEP_VDD_FLASH_MODE_V  0x0000000FU
-#define PMU_HP_SLEEP_VDD_FLASH_MODE_S  18
-/** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_MEM_DSLP    (BIT(22))
-#define PMU_HP_SLEEP_HP_MEM_DSLP_M  (PMU_HP_SLEEP_HP_MEM_DSLP_V << PMU_HP_SLEEP_HP_MEM_DSLP_S)
-#define PMU_HP_SLEEP_HP_MEM_DSLP_V  0x00000001U
-#define PMU_HP_SLEEP_HP_MEM_DSLP_S  22
-/** PMU_HP_SLEEP_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN    0x0000000FU
-#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M  (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S)
-#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V  0x0000000FU
-#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S  23
-/** PMU_HP_SLEEP_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN    (BIT(27))
-#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_M  (PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V << PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S)
-#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V  0x00000001U
-#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S  27
-/** PMU_HP_SLEEP_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN    (BIT(28))
-#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_M  (PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S)
-#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V  0x00000001U
-#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S  28
-/** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN    (BIT(29))
-#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_M  (PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V << PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S)
-#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V  0x00000001U
-#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S  29
-/** PMU_HP_SLEEP_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_HP_AON_PD_EN    (BIT(30))
-#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_M  (PMU_HP_SLEEP_PD_HP_AON_PD_EN_V << PMU_HP_SLEEP_PD_HP_AON_PD_EN_S)
-#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_V  0x00000001U
-#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_S  30
-/** PMU_HP_SLEEP_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_TOP_PD_EN    (BIT(31))
-#define PMU_HP_SLEEP_PD_TOP_PD_EN_M  (PMU_HP_SLEEP_PD_TOP_PD_EN_V << PMU_HP_SLEEP_PD_TOP_PD_EN_S)
-#define PMU_HP_SLEEP_PD_TOP_PD_EN_V  0x00000001U
-#define PMU_HP_SLEEP_PD_TOP_PD_EN_S  31
-
-/** PMU_HP_SLEEP_ICG_HP_FUNC_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x6c)
-/** PMU_HP_SLEEP_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN    0xFFFFFFFFU
-#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_M  (PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V << PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S)
-#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V  0xFFFFFFFFU
-#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S  0
-
-/** PMU_HP_SLEEP_ICG_HP_APB_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x70)
-/** PMU_HP_SLEEP_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_ICG_APB_EN    0xFFFFFFFFU
-#define PMU_HP_SLEEP_DIG_ICG_APB_EN_M  (PMU_HP_SLEEP_DIG_ICG_APB_EN_V << PMU_HP_SLEEP_DIG_ICG_APB_EN_S)
-#define PMU_HP_SLEEP_DIG_ICG_APB_EN_V  0xFFFFFFFFU
-#define PMU_HP_SLEEP_DIG_ICG_APB_EN_S  0
-
-/** PMU_HP_SLEEP_ICG_MODEM_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x74)
-/** PMU_HP_SLEEP_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE    0x00000003U
-#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_M  (PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V << PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S)
-#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V  0x00000003U
-#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S  30
-
-/** PMU_HP_SLEEP_HP_SYS_CNTL_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x78)
-/** PMU_HP_SLEEP_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_UART_WAKEUP_EN    (BIT(24))
-#define PMU_HP_SLEEP_UART_WAKEUP_EN_M  (PMU_HP_SLEEP_UART_WAKEUP_EN_V << PMU_HP_SLEEP_UART_WAKEUP_EN_S)
-#define PMU_HP_SLEEP_UART_WAKEUP_EN_V  0x00000001U
-#define PMU_HP_SLEEP_UART_WAKEUP_EN_S  24
-/** PMU_HP_SLEEP_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL    (BIT(25))
-#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_M  (PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S)
-#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S  25
-/** PMU_HP_SLEEP_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL    (BIT(26))
-#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_M  (PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S)
-#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S  26
-/** PMU_HP_SLEEP_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL    (BIT(27))
-#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_M  (PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V << PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S)
-#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V  0x00000001U
-#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S  27
-/** PMU_HP_SLEEP_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_PAUSE_WDT    (BIT(28))
-#define PMU_HP_SLEEP_DIG_PAUSE_WDT_M  (PMU_HP_SLEEP_DIG_PAUSE_WDT_V << PMU_HP_SLEEP_DIG_PAUSE_WDT_S)
-#define PMU_HP_SLEEP_DIG_PAUSE_WDT_V  0x00000001U
-#define PMU_HP_SLEEP_DIG_PAUSE_WDT_S  28
-/** PMU_HP_SLEEP_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_CPU_STALL    (BIT(29))
-#define PMU_HP_SLEEP_DIG_CPU_STALL_M  (PMU_HP_SLEEP_DIG_CPU_STALL_V << PMU_HP_SLEEP_DIG_CPU_STALL_S)
-#define PMU_HP_SLEEP_DIG_CPU_STALL_V  0x00000001U
-#define PMU_HP_SLEEP_DIG_CPU_STALL_S  29
-
-/** PMU_HP_SLEEP_HP_CK_POWER_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x7c)
-/** PMU_HP_SLEEP_I2C_ISO_EN : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_I2C_ISO_EN    (BIT(26))
-#define PMU_HP_SLEEP_I2C_ISO_EN_M  (PMU_HP_SLEEP_I2C_ISO_EN_V << PMU_HP_SLEEP_I2C_ISO_EN_S)
-#define PMU_HP_SLEEP_I2C_ISO_EN_V  0x00000001U
-#define PMU_HP_SLEEP_I2C_ISO_EN_S  26
-/** PMU_HP_SLEEP_I2C_RETENTION : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_I2C_RETENTION    (BIT(27))
-#define PMU_HP_SLEEP_I2C_RETENTION_M  (PMU_HP_SLEEP_I2C_RETENTION_V << PMU_HP_SLEEP_I2C_RETENTION_S)
-#define PMU_HP_SLEEP_I2C_RETENTION_V  0x00000001U
-#define PMU_HP_SLEEP_I2C_RETENTION_S  27
-/** PMU_HP_SLEEP_XPD_BB_I2C : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_BB_I2C    (BIT(28))
-#define PMU_HP_SLEEP_XPD_BB_I2C_M  (PMU_HP_SLEEP_XPD_BB_I2C_V << PMU_HP_SLEEP_XPD_BB_I2C_S)
-#define PMU_HP_SLEEP_XPD_BB_I2C_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_BB_I2C_S  28
-/** PMU_HP_SLEEP_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_BBPLL_I2C    (BIT(29))
-#define PMU_HP_SLEEP_XPD_BBPLL_I2C_M  (PMU_HP_SLEEP_XPD_BBPLL_I2C_V << PMU_HP_SLEEP_XPD_BBPLL_I2C_S)
-#define PMU_HP_SLEEP_XPD_BBPLL_I2C_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_BBPLL_I2C_S  29
-/** PMU_HP_SLEEP_XPD_BBPLL : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_BBPLL    (BIT(30))
-#define PMU_HP_SLEEP_XPD_BBPLL_M  (PMU_HP_SLEEP_XPD_BBPLL_V << PMU_HP_SLEEP_XPD_BBPLL_S)
-#define PMU_HP_SLEEP_XPD_BBPLL_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_BBPLL_S  30
-
-/** PMU_HP_SLEEP_BIAS_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80)
-/** PMU_HP_SLEEP_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_DCDC_CCM_ENB    (BIT(9))
-#define PMU_HP_SLEEP_DCDC_CCM_ENB_M  (PMU_HP_SLEEP_DCDC_CCM_ENB_V << PMU_HP_SLEEP_DCDC_CCM_ENB_S)
-#define PMU_HP_SLEEP_DCDC_CCM_ENB_V  0x00000001U
-#define PMU_HP_SLEEP_DCDC_CCM_ENB_S  9
-/** PMU_HP_SLEEP_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DCDC_CLEAR_RDY    (BIT(10))
-#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_M  (PMU_HP_SLEEP_DCDC_CLEAR_RDY_V << PMU_HP_SLEEP_DCDC_CLEAR_RDY_S)
-#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_V  0x00000001U
-#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_S  10
-/** PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS    0x00000003U
-#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_M  (PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_V << PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_S)
-#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_V  0x00000003U
-#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_S  11
-/** PMU_HP_SLEEP_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_PMU_DSFMOS    0x0000000FU
-#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_M  (PMU_HP_SLEEP_DIG_PMU_DSFMOS_V << PMU_HP_SLEEP_DIG_PMU_DSFMOS_S)
-#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_V  0x0000000FU
-#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_S  13
-/** PMU_HP_SLEEP_DCM_VSET : R/W; bitpos: [21:17]; default: 23;
- *  need_des
- */
-#define PMU_HP_SLEEP_DCM_VSET    0x0000001FU
-#define PMU_HP_SLEEP_DCM_VSET_M  (PMU_HP_SLEEP_DCM_VSET_V << PMU_HP_SLEEP_DCM_VSET_S)
-#define PMU_HP_SLEEP_DCM_VSET_V  0x0000001FU
-#define PMU_HP_SLEEP_DCM_VSET_S  17
-/** PMU_HP_SLEEP_DCM_MODE : R/W; bitpos: [23:22]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DCM_MODE    0x00000003U
-#define PMU_HP_SLEEP_DCM_MODE_M  (PMU_HP_SLEEP_DCM_MODE_V << PMU_HP_SLEEP_DCM_MODE_S)
-#define PMU_HP_SLEEP_DCM_MODE_V  0x00000003U
-#define PMU_HP_SLEEP_DCM_MODE_S  22
-/** PMU_HP_SLEEP_XPD_TRX : R/W; bitpos: [24]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_TRX    (BIT(24))
-#define PMU_HP_SLEEP_XPD_TRX_M  (PMU_HP_SLEEP_XPD_TRX_V << PMU_HP_SLEEP_XPD_TRX_S)
-#define PMU_HP_SLEEP_XPD_TRX_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_TRX_S  24
-/** PMU_HP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_BIAS    (BIT(25))
-#define PMU_HP_SLEEP_XPD_BIAS_M  (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S)
-#define PMU_HP_SLEEP_XPD_BIAS_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_BIAS_S  25
-/** PMU_HP_SLEEP_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DISCNNT_DIG_RTC    (BIT(29))
-#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_M  (PMU_HP_SLEEP_DISCNNT_DIG_RTC_V << PMU_HP_SLEEP_DISCNNT_DIG_RTC_S)
-#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_V  0x00000001U
-#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_S  29
-/** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_CUR    (BIT(30))
-#define PMU_HP_SLEEP_PD_CUR_M  (PMU_HP_SLEEP_PD_CUR_V << PMU_HP_SLEEP_PD_CUR_S)
-#define PMU_HP_SLEEP_PD_CUR_V  0x00000001U
-#define PMU_HP_SLEEP_PD_CUR_S  30
-/** PMU_HP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_BIAS_SLEEP    (BIT(31))
-#define PMU_HP_SLEEP_BIAS_SLEEP_M  (PMU_HP_SLEEP_BIAS_SLEEP_V << PMU_HP_SLEEP_BIAS_SLEEP_S)
-#define PMU_HP_SLEEP_BIAS_SLEEP_V  0x00000001U
-#define PMU_HP_SLEEP_BIAS_SLEEP_S  31
-
-/** PMU_HP_SLEEP_BACKUP_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_BACKUP_REG (DR_REG_PMU_BASE + 0x84)
-/** PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE    0x00000003U
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S)
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V  0x00000003U
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S  6
-/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [9:8]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE    0x00000003U
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S)
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V  0x00000003U
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S  8
-/** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL    0x00000003U
-#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_M  (PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S)
-#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V  0x00000003U
-#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S  16
-/** PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [19:18]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL    0x00000003U
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S)
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V  0x00000003U
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S  18
-/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [24:20]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODE    0x0000001FU
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M  (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S)
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V  0x0000001FU
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S  20
-/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [29:25]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE    0x0000001FU
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S)
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V  0x0000001FU
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S  25
-/** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2SLEEP_BACKUP_EN    (BIT(30))
-#define PMU_HP_MODEM2SLEEP_BACKUP_EN_M  (PMU_HP_MODEM2SLEEP_BACKUP_EN_V << PMU_HP_MODEM2SLEEP_BACKUP_EN_S)
-#define PMU_HP_MODEM2SLEEP_BACKUP_EN_V  0x00000001U
-#define PMU_HP_MODEM2SLEEP_BACKUP_EN_S  30
-/** PMU_HP_ACTIVE2SLEEP_BACKUP_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN    (BIT(31))
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V << PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S)
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V  0x00000001U
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S  31
-
-/** PMU_HP_SLEEP_BACKUP_CLK_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x88)
-/** PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN    0xFFFFFFFFU
-#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_M  (PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V << PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S)
-#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V  0xFFFFFFFFU
-#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S  0
-
-/** PMU_HP_SLEEP_SYSCLK_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0x8c)
-/** PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV    (BIT(26))
-#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_M  (PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V << PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S)
-#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V  0x00000001U
-#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S  26
-/** PMU_HP_SLEEP_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN    (BIT(27))
-#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_M  (PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V << PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S)
-#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V  0x00000001U
-#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S  27
-/** PMU_HP_SLEEP_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL    (BIT(28))
-#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_M  (PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V << PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S)
-#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V  0x00000001U
-#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S  28
-/** PMU_HP_SLEEP_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_ICG_SLP_SEL    (BIT(29))
-#define PMU_HP_SLEEP_ICG_SLP_SEL_M  (PMU_HP_SLEEP_ICG_SLP_SEL_V << PMU_HP_SLEEP_ICG_SLP_SEL_S)
-#define PMU_HP_SLEEP_ICG_SLP_SEL_V  0x00000001U
-#define PMU_HP_SLEEP_ICG_SLP_SEL_S  29
-/** PMU_HP_SLEEP_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL    0x00000003U
-#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_M  (PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V << PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S)
-#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V  0x00000003U
-#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S  30
-
-/** PMU_HP_SLEEP_HP_REGULATOR0_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x90)
-/** PMU_HP_SLEEP_HP_POWER_DET_BYPASS : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS    (BIT(0))
-#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_M  (PMU_HP_SLEEP_HP_POWER_DET_BYPASS_V << PMU_HP_SLEEP_HP_POWER_DET_BYPASS_S)
-#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_V  0x00000001U
-#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_S  0
-/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD    (BIT(16))
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S)
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V  0x00000001U
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S  16
-/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD    (BIT(17))
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S)
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V  0x00000001U
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S  17
-/** PMU_HP_SLEEP_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR_XPD    (BIT(18))
-#define PMU_HP_SLEEP_HP_REGULATOR_XPD_M  (PMU_HP_SLEEP_HP_REGULATOR_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_XPD_S)
-#define PMU_HP_SLEEP_HP_REGULATOR_XPD_V  0x00000001U
-#define PMU_HP_SLEEP_HP_REGULATOR_XPD_S  18
-/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 8;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS    0x0000000FU
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S)
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V  0x0000000FU
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S  19
-/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 8;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS    0x0000000FU
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S)
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V  0x0000000FU
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S  23
-/** PMU_HP_SLEEP_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 16;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS    0x0000001FU
-#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_M  (PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S)
-#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V  0x0000001FU
-#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S  27
-
-/** PMU_HP_SLEEP_HP_REGULATOR1_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94)
-/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: .;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B    0x00FFFFFFU
-#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_M  (PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S)
-#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V  0x00FFFFFFU
-#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S  8
-
-/** PMU_HP_SLEEP_XTAL_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98)
-/** PMU_HP_SLEEP_XPD_XTALX2 : R/W; bitpos: [30]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_XTALX2    (BIT(30))
-#define PMU_HP_SLEEP_XPD_XTALX2_M  (PMU_HP_SLEEP_XPD_XTALX2_V << PMU_HP_SLEEP_XPD_XTALX2_S)
-#define PMU_HP_SLEEP_XPD_XTALX2_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_XTALX2_S  30
-/** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_XTAL    (BIT(31))
-#define PMU_HP_SLEEP_XPD_XTAL_M  (PMU_HP_SLEEP_XPD_XTAL_V << PMU_HP_SLEEP_XPD_XTAL_S)
-#define PMU_HP_SLEEP_XPD_XTAL_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_XTAL_S  31
-
-/** PMU_HP_SLEEP_LP_REGULATOR0_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c)
-/** PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD    (BIT(21))
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_M  (PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S)
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V  0x00000001U
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S  21
-/** PMU_HP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_REGULATOR_XPD    (BIT(22))
-#define PMU_HP_SLEEP_LP_REGULATOR_XPD_M  (PMU_HP_SLEEP_LP_REGULATOR_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_XPD_S)
-#define PMU_HP_SLEEP_LP_REGULATOR_XPD_V  0x00000001U
-#define PMU_HP_SLEEP_LP_REGULATOR_XPD_S  22
-/** PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 8;
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS    0x0000000FU
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M  (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S)
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V  0x0000000FU
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S  23
-/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS    0x0000001FU
-#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M  (PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S)
-#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V  0x0000001FU
-#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S  27
-
-/** PMU_HP_SLEEP_LP_REGULATOR1_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xa0)
-/** PMU_HP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B    0x0000000FU
-#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_M  (PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S)
-#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V  0x0000000FU
-#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S  28
-
-/** PMU_HP_SLEEP_LP_DIG_POWER_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8)
-/** PMU_HP_SLEEP_VDD_IO_MODE : R/W; bitpos: [26:23]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_VDD_IO_MODE    0x0000000FU
-#define PMU_HP_SLEEP_VDD_IO_MODE_M  (PMU_HP_SLEEP_VDD_IO_MODE_V << PMU_HP_SLEEP_VDD_IO_MODE_S)
-#define PMU_HP_SLEEP_VDD_IO_MODE_V  0x0000000FU
-#define PMU_HP_SLEEP_VDD_IO_MODE_S  23
-/** PMU_HP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_BOD_SOURCE_SEL    (BIT(27))
-#define PMU_HP_SLEEP_BOD_SOURCE_SEL_M  (PMU_HP_SLEEP_BOD_SOURCE_SEL_V << PMU_HP_SLEEP_BOD_SOURCE_SEL_S)
-#define PMU_HP_SLEEP_BOD_SOURCE_SEL_V  0x00000001U
-#define PMU_HP_SLEEP_BOD_SOURCE_SEL_S  27
-/** PMU_HP_SLEEP_VDDBAT_MODE : R/W; bitpos: [29:28]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_VDDBAT_MODE    0x00000003U
-#define PMU_HP_SLEEP_VDDBAT_MODE_M  (PMU_HP_SLEEP_VDDBAT_MODE_V << PMU_HP_SLEEP_VDDBAT_MODE_S)
-#define PMU_HP_SLEEP_VDDBAT_MODE_V  0x00000003U
-#define PMU_HP_SLEEP_VDDBAT_MODE_S  28
-/** PMU_HP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_MEM_DSLP    (BIT(30))
-#define PMU_HP_SLEEP_LP_MEM_DSLP_M  (PMU_HP_SLEEP_LP_MEM_DSLP_V << PMU_HP_SLEEP_LP_MEM_DSLP_S)
-#define PMU_HP_SLEEP_LP_MEM_DSLP_V  0x00000001U
-#define PMU_HP_SLEEP_LP_MEM_DSLP_S  30
-/** PMU_HP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN    (BIT(31))
-#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_M  (PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S)
-#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V  0x00000001U
-#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S  31
-
-/** PMU_HP_SLEEP_LP_CK_POWER_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xac)
-/** PMU_HP_SLEEP_XPD_LPPLL : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_LPPLL    (BIT(27))
-#define PMU_HP_SLEEP_XPD_LPPLL_M  (PMU_HP_SLEEP_XPD_LPPLL_V << PMU_HP_SLEEP_XPD_LPPLL_S)
-#define PMU_HP_SLEEP_XPD_LPPLL_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_LPPLL_S  27
-/** PMU_HP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_XTAL32K    (BIT(28))
-#define PMU_HP_SLEEP_XPD_XTAL32K_M  (PMU_HP_SLEEP_XPD_XTAL32K_V << PMU_HP_SLEEP_XPD_XTAL32K_S)
-#define PMU_HP_SLEEP_XPD_XTAL32K_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_XTAL32K_S  28
-/** PMU_HP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_RC32K    (BIT(29))
-#define PMU_HP_SLEEP_XPD_RC32K_M  (PMU_HP_SLEEP_XPD_RC32K_V << PMU_HP_SLEEP_XPD_RC32K_S)
-#define PMU_HP_SLEEP_XPD_RC32K_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_RC32K_S  29
-/** PMU_HP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_FOSC_CLK    (BIT(30))
-#define PMU_HP_SLEEP_XPD_FOSC_CLK_M  (PMU_HP_SLEEP_XPD_FOSC_CLK_V << PMU_HP_SLEEP_XPD_FOSC_CLK_S)
-#define PMU_HP_SLEEP_XPD_FOSC_CLK_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_FOSC_CLK_S  30
-/** PMU_HP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_OSC_CLK    (BIT(31))
-#define PMU_HP_SLEEP_PD_OSC_CLK_M  (PMU_HP_SLEEP_PD_OSC_CLK_V << PMU_HP_SLEEP_PD_OSC_CLK_S)
-#define PMU_HP_SLEEP_PD_OSC_CLK_V  0x00000001U
-#define PMU_HP_SLEEP_PD_OSC_CLK_S  31
-
-/** PMU_LP_SLEEP_LP_REGULATOR0_REG register
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0xb4)
-/** PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1;
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD    (BIT(21))
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_M  (PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S)
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V  0x00000001U
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S  21
-/** PMU_LP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1;
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_REGULATOR_XPD    (BIT(22))
-#define PMU_LP_SLEEP_LP_REGULATOR_XPD_M  (PMU_LP_SLEEP_LP_REGULATOR_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_XPD_S)
-#define PMU_LP_SLEEP_LP_REGULATOR_XPD_V  0x00000001U
-#define PMU_LP_SLEEP_LP_REGULATOR_XPD_S  22
-/** PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 8;
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS    0x0000000FU
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M  (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S)
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V  0x0000000FU
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S  23
-/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS    0x0000001FU
-#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_M  (PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S)
-#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V  0x0000001FU
-#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S  27
-
-/** PMU_LP_SLEEP_LP_REGULATOR1_REG register
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xb8)
-/** PMU_LP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B    0x0000000FU
-#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_M  (PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S)
-#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V  0x0000000FU
-#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S  28
-
-/** PMU_LP_SLEEP_XTAL_REG register
- *  need_des
- */
-#define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc)
-/** PMU_LP_SLEEP_XPD_XTALX2 : R/W; bitpos: [30]; default: 1;
- *  need_des
- */
-#define PMU_LP_SLEEP_XPD_XTALX2    (BIT(30))
-#define PMU_LP_SLEEP_XPD_XTALX2_M  (PMU_LP_SLEEP_XPD_XTALX2_V << PMU_LP_SLEEP_XPD_XTALX2_S)
-#define PMU_LP_SLEEP_XPD_XTALX2_V  0x00000001U
-#define PMU_LP_SLEEP_XPD_XTALX2_S  30
-/** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define PMU_LP_SLEEP_XPD_XTAL    (BIT(31))
-#define PMU_LP_SLEEP_XPD_XTAL_M  (PMU_LP_SLEEP_XPD_XTAL_V << PMU_LP_SLEEP_XPD_XTAL_S)
-#define PMU_LP_SLEEP_XPD_XTAL_V  0x00000001U
-#define PMU_LP_SLEEP_XPD_XTAL_S  31
-
-/** PMU_LP_SLEEP_LP_DIG_POWER_REG register
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0)
-/** PMU_LP_SLEEP_VDD_IO_MODE : R/W; bitpos: [26:23]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_VDD_IO_MODE    0x0000000FU
-#define PMU_LP_SLEEP_VDD_IO_MODE_M  (PMU_LP_SLEEP_VDD_IO_MODE_V << PMU_LP_SLEEP_VDD_IO_MODE_S)
-#define PMU_LP_SLEEP_VDD_IO_MODE_V  0x0000000FU
-#define PMU_LP_SLEEP_VDD_IO_MODE_S  23
-/** PMU_LP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_BOD_SOURCE_SEL    (BIT(27))
-#define PMU_LP_SLEEP_BOD_SOURCE_SEL_M  (PMU_LP_SLEEP_BOD_SOURCE_SEL_V << PMU_LP_SLEEP_BOD_SOURCE_SEL_S)
-#define PMU_LP_SLEEP_BOD_SOURCE_SEL_V  0x00000001U
-#define PMU_LP_SLEEP_BOD_SOURCE_SEL_S  27
-/** PMU_LP_SLEEP_VDDBAT_MODE : R/W; bitpos: [29:28]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_VDDBAT_MODE    0x00000003U
-#define PMU_LP_SLEEP_VDDBAT_MODE_M  (PMU_LP_SLEEP_VDDBAT_MODE_V << PMU_LP_SLEEP_VDDBAT_MODE_S)
-#define PMU_LP_SLEEP_VDDBAT_MODE_V  0x00000003U
-#define PMU_LP_SLEEP_VDDBAT_MODE_S  28
-/** PMU_LP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_MEM_DSLP    (BIT(30))
-#define PMU_LP_SLEEP_LP_MEM_DSLP_M  (PMU_LP_SLEEP_LP_MEM_DSLP_V << PMU_LP_SLEEP_LP_MEM_DSLP_S)
-#define PMU_LP_SLEEP_LP_MEM_DSLP_V  0x00000001U
-#define PMU_LP_SLEEP_LP_MEM_DSLP_S  30
-/** PMU_LP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN    (BIT(31))
-#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_M  (PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S)
-#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V  0x00000001U
-#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S  31
-
-/** PMU_LP_SLEEP_LP_CK_POWER_REG register
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xc4)
-/** PMU_LP_SLEEP_XPD_LPPLL : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_XPD_LPPLL    (BIT(27))
-#define PMU_LP_SLEEP_XPD_LPPLL_M  (PMU_LP_SLEEP_XPD_LPPLL_V << PMU_LP_SLEEP_XPD_LPPLL_S)
-#define PMU_LP_SLEEP_XPD_LPPLL_V  0x00000001U
-#define PMU_LP_SLEEP_XPD_LPPLL_S  27
-/** PMU_LP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_XPD_XTAL32K    (BIT(28))
-#define PMU_LP_SLEEP_XPD_XTAL32K_M  (PMU_LP_SLEEP_XPD_XTAL32K_V << PMU_LP_SLEEP_XPD_XTAL32K_S)
-#define PMU_LP_SLEEP_XPD_XTAL32K_V  0x00000001U
-#define PMU_LP_SLEEP_XPD_XTAL32K_S  28
-/** PMU_LP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_XPD_RC32K    (BIT(29))
-#define PMU_LP_SLEEP_XPD_RC32K_M  (PMU_LP_SLEEP_XPD_RC32K_V << PMU_LP_SLEEP_XPD_RC32K_S)
-#define PMU_LP_SLEEP_XPD_RC32K_V  0x00000001U
-#define PMU_LP_SLEEP_XPD_RC32K_S  29
-/** PMU_LP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1;
- *  need_des
- */
-#define PMU_LP_SLEEP_XPD_FOSC_CLK    (BIT(30))
-#define PMU_LP_SLEEP_XPD_FOSC_CLK_M  (PMU_LP_SLEEP_XPD_FOSC_CLK_V << PMU_LP_SLEEP_XPD_FOSC_CLK_S)
-#define PMU_LP_SLEEP_XPD_FOSC_CLK_V  0x00000001U
-#define PMU_LP_SLEEP_XPD_FOSC_CLK_S  30
-/** PMU_LP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_PD_OSC_CLK    (BIT(31))
-#define PMU_LP_SLEEP_PD_OSC_CLK_M  (PMU_LP_SLEEP_PD_OSC_CLK_V << PMU_LP_SLEEP_PD_OSC_CLK_S)
-#define PMU_LP_SLEEP_PD_OSC_CLK_V  0x00000001U
-#define PMU_LP_SLEEP_PD_OSC_CLK_S  31
-
-/** PMU_LP_SLEEP_BIAS_REG register
- *  need_des
- */
-#define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8)
-/** PMU_LP_SLEEP_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1;
- *  need_des
- */
-#define PMU_LP_SLEEP_DCDC_CCM_ENB    (BIT(9))
-#define PMU_LP_SLEEP_DCDC_CCM_ENB_M  (PMU_LP_SLEEP_DCDC_CCM_ENB_V << PMU_LP_SLEEP_DCDC_CCM_ENB_S)
-#define PMU_LP_SLEEP_DCDC_CCM_ENB_V  0x00000001U
-#define PMU_LP_SLEEP_DCDC_CCM_ENB_S  9
-/** PMU_LP_SLEEP_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_DCDC_CLEAR_RDY    (BIT(10))
-#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_M  (PMU_LP_SLEEP_DCDC_CLEAR_RDY_V << PMU_LP_SLEEP_DCDC_CLEAR_RDY_S)
-#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_V  0x00000001U
-#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_S  10
-/** PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1;
- *  need_des
- */
-#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS    0x00000003U
-#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_M  (PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_V << PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_S)
-#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_V  0x00000003U
-#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_S  11
-/** PMU_LP_SLEEP_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4;
- *  need_des
- */
-#define PMU_LP_SLEEP_DIG_PMU_DSFMOS    0x0000000FU
-#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_M  (PMU_LP_SLEEP_DIG_PMU_DSFMOS_V << PMU_LP_SLEEP_DIG_PMU_DSFMOS_S)
-#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_V  0x0000000FU
-#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_S  13
-/** PMU_LP_SLEEP_DCM_VSET : R/W; bitpos: [21:17]; default: 23;
- *  need_des
- */
-#define PMU_LP_SLEEP_DCM_VSET    0x0000001FU
-#define PMU_LP_SLEEP_DCM_VSET_M  (PMU_LP_SLEEP_DCM_VSET_V << PMU_LP_SLEEP_DCM_VSET_S)
-#define PMU_LP_SLEEP_DCM_VSET_V  0x0000001FU
-#define PMU_LP_SLEEP_DCM_VSET_S  17
-/** PMU_LP_SLEEP_DCM_MODE : R/W; bitpos: [23:22]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_DCM_MODE    0x00000003U
-#define PMU_LP_SLEEP_DCM_MODE_M  (PMU_LP_SLEEP_DCM_MODE_V << PMU_LP_SLEEP_DCM_MODE_S)
-#define PMU_LP_SLEEP_DCM_MODE_V  0x00000003U
-#define PMU_LP_SLEEP_DCM_MODE_S  22
-/** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_XPD_BIAS    (BIT(25))
-#define PMU_LP_SLEEP_XPD_BIAS_M  (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S)
-#define PMU_LP_SLEEP_XPD_BIAS_V  0x00000001U
-#define PMU_LP_SLEEP_XPD_BIAS_S  25
-/** PMU_LP_SLEEP_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_DISCNNT_DIG_RTC    (BIT(29))
-#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_M  (PMU_LP_SLEEP_DISCNNT_DIG_RTC_V << PMU_LP_SLEEP_DISCNNT_DIG_RTC_S)
-#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_V  0x00000001U
-#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_S  29
-/** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_PD_CUR    (BIT(30))
-#define PMU_LP_SLEEP_PD_CUR_M  (PMU_LP_SLEEP_PD_CUR_V << PMU_LP_SLEEP_PD_CUR_S)
-#define PMU_LP_SLEEP_PD_CUR_V  0x00000001U
-#define PMU_LP_SLEEP_PD_CUR_S  30
-/** PMU_LP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_BIAS_SLEEP    (BIT(31))
-#define PMU_LP_SLEEP_BIAS_SLEEP_M  (PMU_LP_SLEEP_BIAS_SLEEP_V << PMU_LP_SLEEP_BIAS_SLEEP_S)
-#define PMU_LP_SLEEP_BIAS_SLEEP_V  0x00000001U
-#define PMU_LP_SLEEP_BIAS_SLEEP_S  31
-
-/** PMU_IMM_HP_CK_POWER_REG register
- *  need_des
- */
-#define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc)
-/** PMU_TIE_LOW_GLOBAL_BBPLL_ICG : WT; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG    (BIT(0))
-#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_M  (PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V << PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S)
-#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V  0x00000001U
-#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S  0
-/** PMU_TIE_LOW_GLOBAL_XTAL_ICG : WT; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_GLOBAL_XTAL_ICG    (BIT(1))
-#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_M  (PMU_TIE_LOW_GLOBAL_XTAL_ICG_V << PMU_TIE_LOW_GLOBAL_XTAL_ICG_S)
-#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_V  0x00000001U
-#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_S  1
-/** PMU_TIE_LOW_I2C_RETENTION : WT; bitpos: [2]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_I2C_RETENTION    (BIT(2))
-#define PMU_TIE_LOW_I2C_RETENTION_M  (PMU_TIE_LOW_I2C_RETENTION_V << PMU_TIE_LOW_I2C_RETENTION_S)
-#define PMU_TIE_LOW_I2C_RETENTION_V  0x00000001U
-#define PMU_TIE_LOW_I2C_RETENTION_S  2
-/** PMU_TIE_LOW_XPD_BB_I2C : WT; bitpos: [3]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_XPD_BB_I2C    (BIT(3))
-#define PMU_TIE_LOW_XPD_BB_I2C_M  (PMU_TIE_LOW_XPD_BB_I2C_V << PMU_TIE_LOW_XPD_BB_I2C_S)
-#define PMU_TIE_LOW_XPD_BB_I2C_V  0x00000001U
-#define PMU_TIE_LOW_XPD_BB_I2C_S  3
-/** PMU_TIE_LOW_XPD_BBPLL_I2C : WT; bitpos: [4]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_XPD_BBPLL_I2C    (BIT(4))
-#define PMU_TIE_LOW_XPD_BBPLL_I2C_M  (PMU_TIE_LOW_XPD_BBPLL_I2C_V << PMU_TIE_LOW_XPD_BBPLL_I2C_S)
-#define PMU_TIE_LOW_XPD_BBPLL_I2C_V  0x00000001U
-#define PMU_TIE_LOW_XPD_BBPLL_I2C_S  4
-/** PMU_TIE_LOW_XPD_BBPLL : WT; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_XPD_BBPLL    (BIT(5))
-#define PMU_TIE_LOW_XPD_BBPLL_M  (PMU_TIE_LOW_XPD_BBPLL_V << PMU_TIE_LOW_XPD_BBPLL_S)
-#define PMU_TIE_LOW_XPD_BBPLL_V  0x00000001U
-#define PMU_TIE_LOW_XPD_BBPLL_S  5
-/** PMU_TIE_LOW_XPD_XTAL : WT; bitpos: [6]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_XPD_XTAL    (BIT(6))
-#define PMU_TIE_LOW_XPD_XTAL_M  (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S)
-#define PMU_TIE_LOW_XPD_XTAL_V  0x00000001U
-#define PMU_TIE_LOW_XPD_XTAL_S  6
-/** PMU_TIE_LOW_GLOBAL_XTALX2_ICG : WT; bitpos: [7]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG    (BIT(7))
-#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_M  (PMU_TIE_LOW_GLOBAL_XTALX2_ICG_V << PMU_TIE_LOW_GLOBAL_XTALX2_ICG_S)
-#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_V  0x00000001U
-#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_S  7
-/** PMU_TIE_LOW_XPD_XTALX2 : WT; bitpos: [8]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_XPD_XTALX2    (BIT(8))
-#define PMU_TIE_LOW_XPD_XTALX2_M  (PMU_TIE_LOW_XPD_XTALX2_V << PMU_TIE_LOW_XPD_XTALX2_S)
-#define PMU_TIE_LOW_XPD_XTALX2_V  0x00000001U
-#define PMU_TIE_LOW_XPD_XTALX2_S  8
-/** PMU_TIE_HIGH_XTALX2 : WT; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_XTALX2    (BIT(23))
-#define PMU_TIE_HIGH_XTALX2_M  (PMU_TIE_HIGH_XTALX2_V << PMU_TIE_HIGH_XTALX2_S)
-#define PMU_TIE_HIGH_XTALX2_V  0x00000001U
-#define PMU_TIE_HIGH_XTALX2_S  23
-/** PMU_TIE_HIGH_GLOBAL_XTALX2_ICG : WT; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG    (BIT(24))
-#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_M  (PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_V << PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_S)
-#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_V  0x00000001U
-#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_S  24
-/** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : WT; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG    (BIT(25))
-#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_M  (PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S)
-#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V  0x00000001U
-#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S  25
-/** PMU_TIE_HIGH_GLOBAL_XTAL_ICG : WT; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG    (BIT(26))
-#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_M  (PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V << PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S)
-#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V  0x00000001U
-#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S  26
-/** PMU_TIE_HIGH_I2C_RETENTION : WT; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_I2C_RETENTION    (BIT(27))
-#define PMU_TIE_HIGH_I2C_RETENTION_M  (PMU_TIE_HIGH_I2C_RETENTION_V << PMU_TIE_HIGH_I2C_RETENTION_S)
-#define PMU_TIE_HIGH_I2C_RETENTION_V  0x00000001U
-#define PMU_TIE_HIGH_I2C_RETENTION_S  27
-/** PMU_TIE_HIGH_XPD_BB_I2C : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_XPD_BB_I2C    (BIT(28))
-#define PMU_TIE_HIGH_XPD_BB_I2C_M  (PMU_TIE_HIGH_XPD_BB_I2C_V << PMU_TIE_HIGH_XPD_BB_I2C_S)
-#define PMU_TIE_HIGH_XPD_BB_I2C_V  0x00000001U
-#define PMU_TIE_HIGH_XPD_BB_I2C_S  28
-/** PMU_TIE_HIGH_XPD_BBPLL_I2C : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_XPD_BBPLL_I2C    (BIT(29))
-#define PMU_TIE_HIGH_XPD_BBPLL_I2C_M  (PMU_TIE_HIGH_XPD_BBPLL_I2C_V << PMU_TIE_HIGH_XPD_BBPLL_I2C_S)
-#define PMU_TIE_HIGH_XPD_BBPLL_I2C_V  0x00000001U
-#define PMU_TIE_HIGH_XPD_BBPLL_I2C_S  29
-/** PMU_TIE_HIGH_XPD_BBPLL : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_XPD_BBPLL    (BIT(30))
-#define PMU_TIE_HIGH_XPD_BBPLL_M  (PMU_TIE_HIGH_XPD_BBPLL_V << PMU_TIE_HIGH_XPD_BBPLL_S)
-#define PMU_TIE_HIGH_XPD_BBPLL_V  0x00000001U
-#define PMU_TIE_HIGH_XPD_BBPLL_S  30
-/** PMU_TIE_HIGH_XPD_XTAL : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_XPD_XTAL    (BIT(31))
-#define PMU_TIE_HIGH_XPD_XTAL_M  (PMU_TIE_HIGH_XPD_XTAL_V << PMU_TIE_HIGH_XPD_XTAL_S)
-#define PMU_TIE_HIGH_XPD_XTAL_V  0x00000001U
-#define PMU_TIE_HIGH_XPD_XTAL_S  31
-
-/** PMU_IMM_SLEEP_SYSCLK_REG register
- *  need_des
- */
-#define PMU_IMM_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0xd0)
-/** PMU_UPDATE_DIG_ICG_SWITCH : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_UPDATE_DIG_ICG_SWITCH    (BIT(28))
-#define PMU_UPDATE_DIG_ICG_SWITCH_M  (PMU_UPDATE_DIG_ICG_SWITCH_V << PMU_UPDATE_DIG_ICG_SWITCH_S)
-#define PMU_UPDATE_DIG_ICG_SWITCH_V  0x00000001U
-#define PMU_UPDATE_DIG_ICG_SWITCH_S  28
-/** PMU_TIE_LOW_ICG_SLP_SEL : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_ICG_SLP_SEL    (BIT(29))
-#define PMU_TIE_LOW_ICG_SLP_SEL_M  (PMU_TIE_LOW_ICG_SLP_SEL_V << PMU_TIE_LOW_ICG_SLP_SEL_S)
-#define PMU_TIE_LOW_ICG_SLP_SEL_V  0x00000001U
-#define PMU_TIE_LOW_ICG_SLP_SEL_S  29
-/** PMU_TIE_HIGH_ICG_SLP_SEL : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_ICG_SLP_SEL    (BIT(30))
-#define PMU_TIE_HIGH_ICG_SLP_SEL_M  (PMU_TIE_HIGH_ICG_SLP_SEL_V << PMU_TIE_HIGH_ICG_SLP_SEL_S)
-#define PMU_TIE_HIGH_ICG_SLP_SEL_V  0x00000001U
-#define PMU_TIE_HIGH_ICG_SLP_SEL_S  30
-/** PMU_UPDATE_DIG_SYS_CLK_SEL : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_UPDATE_DIG_SYS_CLK_SEL    (BIT(31))
-#define PMU_UPDATE_DIG_SYS_CLK_SEL_M  (PMU_UPDATE_DIG_SYS_CLK_SEL_V << PMU_UPDATE_DIG_SYS_CLK_SEL_S)
-#define PMU_UPDATE_DIG_SYS_CLK_SEL_V  0x00000001U
-#define PMU_UPDATE_DIG_SYS_CLK_SEL_S  31
-
-/** PMU_IMM_HP_FUNC_ICG_REG register
- *  need_des
- */
-#define PMU_IMM_HP_FUNC_ICG_REG (DR_REG_PMU_BASE + 0xd4)
-/** PMU_UPDATE_DIG_ICG_FUNC_EN : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_UPDATE_DIG_ICG_FUNC_EN    (BIT(31))
-#define PMU_UPDATE_DIG_ICG_FUNC_EN_M  (PMU_UPDATE_DIG_ICG_FUNC_EN_V << PMU_UPDATE_DIG_ICG_FUNC_EN_S)
-#define PMU_UPDATE_DIG_ICG_FUNC_EN_V  0x00000001U
-#define PMU_UPDATE_DIG_ICG_FUNC_EN_S  31
-
-/** PMU_IMM_HP_APB_ICG_REG register
- *  need_des
- */
-#define PMU_IMM_HP_APB_ICG_REG (DR_REG_PMU_BASE + 0xd8)
-/** PMU_UPDATE_DIG_ICG_APB_EN : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_UPDATE_DIG_ICG_APB_EN    (BIT(31))
-#define PMU_UPDATE_DIG_ICG_APB_EN_M  (PMU_UPDATE_DIG_ICG_APB_EN_V << PMU_UPDATE_DIG_ICG_APB_EN_S)
-#define PMU_UPDATE_DIG_ICG_APB_EN_V  0x00000001U
-#define PMU_UPDATE_DIG_ICG_APB_EN_S  31
-
-/** PMU_IMM_MODEM_ICG_REG register
- *  need_des
- */
-#define PMU_IMM_MODEM_ICG_REG (DR_REG_PMU_BASE + 0xdc)
-/** PMU_UPDATE_DIG_ICG_MODEM_EN : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_UPDATE_DIG_ICG_MODEM_EN    (BIT(31))
-#define PMU_UPDATE_DIG_ICG_MODEM_EN_M  (PMU_UPDATE_DIG_ICG_MODEM_EN_V << PMU_UPDATE_DIG_ICG_MODEM_EN_S)
-#define PMU_UPDATE_DIG_ICG_MODEM_EN_V  0x00000001U
-#define PMU_UPDATE_DIG_ICG_MODEM_EN_S  31
-
-/** PMU_IMM_LP_ICG_REG register
- *  need_des
- */
-#define PMU_IMM_LP_ICG_REG (DR_REG_PMU_BASE + 0xe0)
-/** PMU_TIE_LOW_LP_ROOTCLK_SEL : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_LP_ROOTCLK_SEL    (BIT(30))
-#define PMU_TIE_LOW_LP_ROOTCLK_SEL_M  (PMU_TIE_LOW_LP_ROOTCLK_SEL_V << PMU_TIE_LOW_LP_ROOTCLK_SEL_S)
-#define PMU_TIE_LOW_LP_ROOTCLK_SEL_V  0x00000001U
-#define PMU_TIE_LOW_LP_ROOTCLK_SEL_S  30
-/** PMU_TIE_HIGH_LP_ROOTCLK_SEL : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_LP_ROOTCLK_SEL    (BIT(31))
-#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_M  (PMU_TIE_HIGH_LP_ROOTCLK_SEL_V << PMU_TIE_HIGH_LP_ROOTCLK_SEL_S)
-#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_V  0x00000001U
-#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_S  31
-
-/** PMU_IMM_PAD_HOLD_ALL_REG register
- *  need_des
- */
-#define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4)
-/** PMU_TIE_HIGH_DIG_PAD_SLP_SEL : WT; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL    (BIT(26))
-#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_M  (PMU_TIE_HIGH_DIG_PAD_SLP_SEL_V << PMU_TIE_HIGH_DIG_PAD_SLP_SEL_S)
-#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_V  0x00000001U
-#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_S  26
-/** PMU_TIE_LOW_DIG_PAD_SLP_SEL : WT; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_DIG_PAD_SLP_SEL    (BIT(27))
-#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_M  (PMU_TIE_LOW_DIG_PAD_SLP_SEL_V << PMU_TIE_LOW_DIG_PAD_SLP_SEL_S)
-#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_V  0x00000001U
-#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_S  27
-/** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL    (BIT(28))
-#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_M  (PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S)
-#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S  28
-/** PMU_TIE_LOW_LP_PAD_HOLD_ALL : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_LP_PAD_HOLD_ALL    (BIT(29))
-#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_M  (PMU_TIE_LOW_LP_PAD_HOLD_ALL_V << PMU_TIE_LOW_LP_PAD_HOLD_ALL_S)
-#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_S  29
-/** PMU_TIE_HIGH_HP_PAD_HOLD_ALL : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL    (BIT(30))
-#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_M  (PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S)
-#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S  30
-/** PMU_TIE_LOW_HP_PAD_HOLD_ALL : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_HP_PAD_HOLD_ALL    (BIT(31))
-#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_M  (PMU_TIE_LOW_HP_PAD_HOLD_ALL_V << PMU_TIE_LOW_HP_PAD_HOLD_ALL_S)
-#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_S  31
-
-/** PMU_IMM_I2C_ISO_REG register
- *  need_des
- */
-#define PMU_IMM_I2C_ISO_REG (DR_REG_PMU_BASE + 0xe8)
-/** PMU_TIE_HIGH_I2C_ISO_EN : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_I2C_ISO_EN    (BIT(30))
-#define PMU_TIE_HIGH_I2C_ISO_EN_M  (PMU_TIE_HIGH_I2C_ISO_EN_V << PMU_TIE_HIGH_I2C_ISO_EN_S)
-#define PMU_TIE_HIGH_I2C_ISO_EN_V  0x00000001U
-#define PMU_TIE_HIGH_I2C_ISO_EN_S  30
-/** PMU_TIE_LOW_I2C_ISO_EN : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_I2C_ISO_EN    (BIT(31))
-#define PMU_TIE_LOW_I2C_ISO_EN_M  (PMU_TIE_LOW_I2C_ISO_EN_V << PMU_TIE_LOW_I2C_ISO_EN_S)
-#define PMU_TIE_LOW_I2C_ISO_EN_V  0x00000001U
-#define PMU_TIE_LOW_I2C_ISO_EN_S  31
-
-/** PMU_POWER_WAIT_TIMER0_REG register
- *  need_des
- */
-#define PMU_POWER_WAIT_TIMER0_REG (DR_REG_PMU_BASE + 0xec)
-/** PMU_DG_HP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255;
- *  need_des
- */
-#define PMU_DG_HP_POWERDOWN_TIMER    0x000001FFU
-#define PMU_DG_HP_POWERDOWN_TIMER_M  (PMU_DG_HP_POWERDOWN_TIMER_V << PMU_DG_HP_POWERDOWN_TIMER_S)
-#define PMU_DG_HP_POWERDOWN_TIMER_V  0x000001FFU
-#define PMU_DG_HP_POWERDOWN_TIMER_S  5
-/** PMU_DG_HP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255;
- *  need_des
- */
-#define PMU_DG_HP_POWERUP_TIMER    0x000001FFU
-#define PMU_DG_HP_POWERUP_TIMER_M  (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S)
-#define PMU_DG_HP_POWERUP_TIMER_V  0x000001FFU
-#define PMU_DG_HP_POWERUP_TIMER_S  14
-/** PMU_DG_HP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255;
- *  need_des
- */
-#define PMU_DG_HP_PD_WAIT_TIMER    0x000001FFU
-#define PMU_DG_HP_PD_WAIT_TIMER_M  (PMU_DG_HP_PD_WAIT_TIMER_V << PMU_DG_HP_PD_WAIT_TIMER_S)
-#define PMU_DG_HP_PD_WAIT_TIMER_V  0x000001FFU
-#define PMU_DG_HP_PD_WAIT_TIMER_S  23
-
-/** PMU_POWER_WAIT_TIMER1_REG register
- *  need_des
- */
-#define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0)
-/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 63;
- *  need_des
- */
-#define PMU_DG_LP_POWERDOWN_TIMER    0x0000007FU
-#define PMU_DG_LP_POWERDOWN_TIMER_M  (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S)
-#define PMU_DG_LP_POWERDOWN_TIMER_V  0x0000007FU
-#define PMU_DG_LP_POWERDOWN_TIMER_S  9
-/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 63;
- *  need_des
- */
-#define PMU_DG_LP_POWERUP_TIMER    0x0000007FU
-#define PMU_DG_LP_POWERUP_TIMER_M  (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S)
-#define PMU_DG_LP_POWERUP_TIMER_V  0x0000007FU
-#define PMU_DG_LP_POWERUP_TIMER_S  16
-/** PMU_DG_LP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255;
- *  need_des
- */
-#define PMU_DG_LP_PD_WAIT_TIMER    0x000001FFU
-#define PMU_DG_LP_PD_WAIT_TIMER_M  (PMU_DG_LP_PD_WAIT_TIMER_V << PMU_DG_LP_PD_WAIT_TIMER_S)
-#define PMU_DG_LP_PD_WAIT_TIMER_V  0x000001FFU
-#define PMU_DG_LP_PD_WAIT_TIMER_S  23
-
-/** PMU_POWER_WAIT_TIMER2_REG register
- *  need_des
- */
-#define PMU_POWER_WAIT_TIMER2_REG (DR_REG_PMU_BASE + 0xf4)
-/** PMU_DG_LP_ISO_WAIT_TIMER : R/W; bitpos: [7:0]; default: 255;
- *  need_des
- */
-#define PMU_DG_LP_ISO_WAIT_TIMER    0x000000FFU
-#define PMU_DG_LP_ISO_WAIT_TIMER_M  (PMU_DG_LP_ISO_WAIT_TIMER_V << PMU_DG_LP_ISO_WAIT_TIMER_S)
-#define PMU_DG_LP_ISO_WAIT_TIMER_V  0x000000FFU
-#define PMU_DG_LP_ISO_WAIT_TIMER_S  0
-/** PMU_DG_LP_RST_WAIT_TIMER : R/W; bitpos: [15:8]; default: 255;
- *  need_des
- */
-#define PMU_DG_LP_RST_WAIT_TIMER    0x000000FFU
-#define PMU_DG_LP_RST_WAIT_TIMER_M  (PMU_DG_LP_RST_WAIT_TIMER_V << PMU_DG_LP_RST_WAIT_TIMER_S)
-#define PMU_DG_LP_RST_WAIT_TIMER_V  0x000000FFU
-#define PMU_DG_LP_RST_WAIT_TIMER_S  8
-/** PMU_DG_HP_ISO_WAIT_TIMER : R/W; bitpos: [23:16]; default: 255;
- *  need_des
- */
-#define PMU_DG_HP_ISO_WAIT_TIMER    0x000000FFU
-#define PMU_DG_HP_ISO_WAIT_TIMER_M  (PMU_DG_HP_ISO_WAIT_TIMER_V << PMU_DG_HP_ISO_WAIT_TIMER_S)
-#define PMU_DG_HP_ISO_WAIT_TIMER_V  0x000000FFU
-#define PMU_DG_HP_ISO_WAIT_TIMER_S  16
-/** PMU_DG_HP_RST_WAIT_TIMER : R/W; bitpos: [31:24]; default: 255;
- *  need_des
- */
-#define PMU_DG_HP_RST_WAIT_TIMER    0x000000FFU
-#define PMU_DG_HP_RST_WAIT_TIMER_M  (PMU_DG_HP_RST_WAIT_TIMER_V << PMU_DG_HP_RST_WAIT_TIMER_S)
-#define PMU_DG_HP_RST_WAIT_TIMER_V  0x000000FFU
-#define PMU_DG_HP_RST_WAIT_TIMER_S  24
-
-/** PMU_POWER_PD_TOP_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf8)
-/** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_TOP_RESET    (BIT(0))
-#define PMU_FORCE_TOP_RESET_M  (PMU_FORCE_TOP_RESET_V << PMU_FORCE_TOP_RESET_S)
-#define PMU_FORCE_TOP_RESET_V  0x00000001U
-#define PMU_FORCE_TOP_RESET_S  0
-/** PMU_FORCE_TOP_ISO : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_TOP_ISO    (BIT(1))
-#define PMU_FORCE_TOP_ISO_M  (PMU_FORCE_TOP_ISO_V << PMU_FORCE_TOP_ISO_S)
-#define PMU_FORCE_TOP_ISO_V  0x00000001U
-#define PMU_FORCE_TOP_ISO_S  1
-/** PMU_FORCE_TOP_PU : R/W; bitpos: [2]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_TOP_PU    (BIT(2))
-#define PMU_FORCE_TOP_PU_M  (PMU_FORCE_TOP_PU_V << PMU_FORCE_TOP_PU_S)
-#define PMU_FORCE_TOP_PU_V  0x00000001U
-#define PMU_FORCE_TOP_PU_S  2
-/** PMU_FORCE_TOP_NO_RESET : R/W; bitpos: [3]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_TOP_NO_RESET    (BIT(3))
-#define PMU_FORCE_TOP_NO_RESET_M  (PMU_FORCE_TOP_NO_RESET_V << PMU_FORCE_TOP_NO_RESET_S)
-#define PMU_FORCE_TOP_NO_RESET_V  0x00000001U
-#define PMU_FORCE_TOP_NO_RESET_S  3
-/** PMU_FORCE_TOP_NO_ISO : R/W; bitpos: [4]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_TOP_NO_ISO    (BIT(4))
-#define PMU_FORCE_TOP_NO_ISO_M  (PMU_FORCE_TOP_NO_ISO_V << PMU_FORCE_TOP_NO_ISO_S)
-#define PMU_FORCE_TOP_NO_ISO_V  0x00000001U
-#define PMU_FORCE_TOP_NO_ISO_S  4
-/** PMU_FORCE_TOP_PD : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_TOP_PD    (BIT(5))
-#define PMU_FORCE_TOP_PD_M  (PMU_FORCE_TOP_PD_V << PMU_FORCE_TOP_PD_S)
-#define PMU_FORCE_TOP_PD_V  0x00000001U
-#define PMU_FORCE_TOP_PD_S  5
-/** PMU_PD_TOP_MASK : R/W; bitpos: [10:6]; default: 0;
- *  need_des
- */
-#define PMU_PD_TOP_MASK    0x0000001FU
-#define PMU_PD_TOP_MASK_M  (PMU_PD_TOP_MASK_V << PMU_PD_TOP_MASK_S)
-#define PMU_PD_TOP_MASK_V  0x0000001FU
-#define PMU_PD_TOP_MASK_S  6
-/** PMU_PD_TOP_PD_MASK : R/W; bitpos: [31:27]; default: 0;
- *  need_des
- */
-#define PMU_PD_TOP_PD_MASK    0x0000001FU
-#define PMU_PD_TOP_PD_MASK_M  (PMU_PD_TOP_PD_MASK_V << PMU_PD_TOP_PD_MASK_S)
-#define PMU_PD_TOP_PD_MASK_V  0x0000001FU
-#define PMU_PD_TOP_PD_MASK_S  27
-
-/** PMU_POWER_PD_HPAON_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xfc)
-/** PMU_FORCE_HP_AON_RESET : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_AON_RESET    (BIT(0))
-#define PMU_FORCE_HP_AON_RESET_M  (PMU_FORCE_HP_AON_RESET_V << PMU_FORCE_HP_AON_RESET_S)
-#define PMU_FORCE_HP_AON_RESET_V  0x00000001U
-#define PMU_FORCE_HP_AON_RESET_S  0
-/** PMU_FORCE_HP_AON_ISO : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_AON_ISO    (BIT(1))
-#define PMU_FORCE_HP_AON_ISO_M  (PMU_FORCE_HP_AON_ISO_V << PMU_FORCE_HP_AON_ISO_S)
-#define PMU_FORCE_HP_AON_ISO_V  0x00000001U
-#define PMU_FORCE_HP_AON_ISO_S  1
-/** PMU_FORCE_HP_AON_PU : R/W; bitpos: [2]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_AON_PU    (BIT(2))
-#define PMU_FORCE_HP_AON_PU_M  (PMU_FORCE_HP_AON_PU_V << PMU_FORCE_HP_AON_PU_S)
-#define PMU_FORCE_HP_AON_PU_V  0x00000001U
-#define PMU_FORCE_HP_AON_PU_S  2
-/** PMU_FORCE_HP_AON_NO_RESET : R/W; bitpos: [3]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_AON_NO_RESET    (BIT(3))
-#define PMU_FORCE_HP_AON_NO_RESET_M  (PMU_FORCE_HP_AON_NO_RESET_V << PMU_FORCE_HP_AON_NO_RESET_S)
-#define PMU_FORCE_HP_AON_NO_RESET_V  0x00000001U
-#define PMU_FORCE_HP_AON_NO_RESET_S  3
-/** PMU_FORCE_HP_AON_NO_ISO : R/W; bitpos: [4]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_AON_NO_ISO    (BIT(4))
-#define PMU_FORCE_HP_AON_NO_ISO_M  (PMU_FORCE_HP_AON_NO_ISO_V << PMU_FORCE_HP_AON_NO_ISO_S)
-#define PMU_FORCE_HP_AON_NO_ISO_V  0x00000001U
-#define PMU_FORCE_HP_AON_NO_ISO_S  4
-/** PMU_FORCE_HP_AON_PD : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_AON_PD    (BIT(5))
-#define PMU_FORCE_HP_AON_PD_M  (PMU_FORCE_HP_AON_PD_V << PMU_FORCE_HP_AON_PD_S)
-#define PMU_FORCE_HP_AON_PD_V  0x00000001U
-#define PMU_FORCE_HP_AON_PD_S  5
-/** PMU_PD_HP_AON_MASK : R/W; bitpos: [10:6]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_AON_MASK    0x0000001FU
-#define PMU_PD_HP_AON_MASK_M  (PMU_PD_HP_AON_MASK_V << PMU_PD_HP_AON_MASK_S)
-#define PMU_PD_HP_AON_MASK_V  0x0000001FU
-#define PMU_PD_HP_AON_MASK_S  6
-/** PMU_PD_HP_AON_PD_MASK : R/W; bitpos: [31:27]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_AON_PD_MASK    0x0000001FU
-#define PMU_PD_HP_AON_PD_MASK_M  (PMU_PD_HP_AON_PD_MASK_V << PMU_PD_HP_AON_PD_MASK_S)
-#define PMU_PD_HP_AON_PD_MASK_V  0x0000001FU
-#define PMU_PD_HP_AON_PD_MASK_S  27
-
-/** PMU_POWER_PD_HPCPU_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0x100)
-/** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_CPU_RESET    (BIT(0))
-#define PMU_FORCE_HP_CPU_RESET_M  (PMU_FORCE_HP_CPU_RESET_V << PMU_FORCE_HP_CPU_RESET_S)
-#define PMU_FORCE_HP_CPU_RESET_V  0x00000001U
-#define PMU_FORCE_HP_CPU_RESET_S  0
-/** PMU_FORCE_HP_CPU_ISO : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_CPU_ISO    (BIT(1))
-#define PMU_FORCE_HP_CPU_ISO_M  (PMU_FORCE_HP_CPU_ISO_V << PMU_FORCE_HP_CPU_ISO_S)
-#define PMU_FORCE_HP_CPU_ISO_V  0x00000001U
-#define PMU_FORCE_HP_CPU_ISO_S  1
-/** PMU_FORCE_HP_CPU_PU : R/W; bitpos: [2]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_CPU_PU    (BIT(2))
-#define PMU_FORCE_HP_CPU_PU_M  (PMU_FORCE_HP_CPU_PU_V << PMU_FORCE_HP_CPU_PU_S)
-#define PMU_FORCE_HP_CPU_PU_V  0x00000001U
-#define PMU_FORCE_HP_CPU_PU_S  2
-/** PMU_FORCE_HP_CPU_NO_RESET : R/W; bitpos: [3]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_CPU_NO_RESET    (BIT(3))
-#define PMU_FORCE_HP_CPU_NO_RESET_M  (PMU_FORCE_HP_CPU_NO_RESET_V << PMU_FORCE_HP_CPU_NO_RESET_S)
-#define PMU_FORCE_HP_CPU_NO_RESET_V  0x00000001U
-#define PMU_FORCE_HP_CPU_NO_RESET_S  3
-/** PMU_FORCE_HP_CPU_NO_ISO : R/W; bitpos: [4]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_CPU_NO_ISO    (BIT(4))
-#define PMU_FORCE_HP_CPU_NO_ISO_M  (PMU_FORCE_HP_CPU_NO_ISO_V << PMU_FORCE_HP_CPU_NO_ISO_S)
-#define PMU_FORCE_HP_CPU_NO_ISO_V  0x00000001U
-#define PMU_FORCE_HP_CPU_NO_ISO_S  4
-/** PMU_FORCE_HP_CPU_PD : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_CPU_PD    (BIT(5))
-#define PMU_FORCE_HP_CPU_PD_M  (PMU_FORCE_HP_CPU_PD_V << PMU_FORCE_HP_CPU_PD_S)
-#define PMU_FORCE_HP_CPU_PD_V  0x00000001U
-#define PMU_FORCE_HP_CPU_PD_S  5
-/** PMU_PD_HP_CPU_MASK : R/W; bitpos: [10:6]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_CPU_MASK    0x0000001FU
-#define PMU_PD_HP_CPU_MASK_M  (PMU_PD_HP_CPU_MASK_V << PMU_PD_HP_CPU_MASK_S)
-#define PMU_PD_HP_CPU_MASK_V  0x0000001FU
-#define PMU_PD_HP_CPU_MASK_S  6
-/** PMU_PD_HP_CPU_PD_MASK : R/W; bitpos: [31:27]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_CPU_PD_MASK    0x0000001FU
-#define PMU_PD_HP_CPU_PD_MASK_M  (PMU_PD_HP_CPU_PD_MASK_V << PMU_PD_HP_CPU_PD_MASK_S)
-#define PMU_PD_HP_CPU_PD_MASK_V  0x0000001FU
-#define PMU_PD_HP_CPU_PD_MASK_S  27
-
-/** PMU_POWER_PD_HPPERI_RESERVE_REG register
- *  need_des
- */
-#define PMU_POWER_PD_HPPERI_RESERVE_REG (DR_REG_PMU_BASE + 0x104)
-/** PMU_FORCE_HP_PERI_RESET : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_PERI_RESET    (BIT(0))
-#define PMU_FORCE_HP_PERI_RESET_M  (PMU_FORCE_HP_PERI_RESET_V << PMU_FORCE_HP_PERI_RESET_S)
-#define PMU_FORCE_HP_PERI_RESET_V  0x00000001U
-#define PMU_FORCE_HP_PERI_RESET_S  0
-/** PMU_FORCE_HP_PERI_ISO : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_PERI_ISO    (BIT(1))
-#define PMU_FORCE_HP_PERI_ISO_M  (PMU_FORCE_HP_PERI_ISO_V << PMU_FORCE_HP_PERI_ISO_S)
-#define PMU_FORCE_HP_PERI_ISO_V  0x00000001U
-#define PMU_FORCE_HP_PERI_ISO_S  1
-/** PMU_FORCE_HP_PERI_PU : R/W; bitpos: [2]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_PERI_PU    (BIT(2))
-#define PMU_FORCE_HP_PERI_PU_M  (PMU_FORCE_HP_PERI_PU_V << PMU_FORCE_HP_PERI_PU_S)
-#define PMU_FORCE_HP_PERI_PU_V  0x00000001U
-#define PMU_FORCE_HP_PERI_PU_S  2
-/** PMU_FORCE_HP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_PERI_NO_RESET    (BIT(3))
-#define PMU_FORCE_HP_PERI_NO_RESET_M  (PMU_FORCE_HP_PERI_NO_RESET_V << PMU_FORCE_HP_PERI_NO_RESET_S)
-#define PMU_FORCE_HP_PERI_NO_RESET_V  0x00000001U
-#define PMU_FORCE_HP_PERI_NO_RESET_S  3
-/** PMU_FORCE_HP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_PERI_NO_ISO    (BIT(4))
-#define PMU_FORCE_HP_PERI_NO_ISO_M  (PMU_FORCE_HP_PERI_NO_ISO_V << PMU_FORCE_HP_PERI_NO_ISO_S)
-#define PMU_FORCE_HP_PERI_NO_ISO_V  0x00000001U
-#define PMU_FORCE_HP_PERI_NO_ISO_S  4
-/** PMU_FORCE_HP_PERI_PD : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_PERI_PD    (BIT(5))
-#define PMU_FORCE_HP_PERI_PD_M  (PMU_FORCE_HP_PERI_PD_V << PMU_FORCE_HP_PERI_PD_S)
-#define PMU_FORCE_HP_PERI_PD_V  0x00000001U
-#define PMU_FORCE_HP_PERI_PD_S  5
-/** PMU_PD_HP_PERI_MASK : R/W; bitpos: [10:6]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_PERI_MASK    0x0000001FU
-#define PMU_PD_HP_PERI_MASK_M  (PMU_PD_HP_PERI_MASK_V << PMU_PD_HP_PERI_MASK_S)
-#define PMU_PD_HP_PERI_MASK_V  0x0000001FU
-#define PMU_PD_HP_PERI_MASK_S  6
-/** PMU_PD_HP_PERI_PD_MASK : R/W; bitpos: [31:27]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_PERI_PD_MASK    0x0000001FU
-#define PMU_PD_HP_PERI_PD_MASK_M  (PMU_PD_HP_PERI_PD_MASK_V << PMU_PD_HP_PERI_PD_MASK_S)
-#define PMU_PD_HP_PERI_PD_MASK_V  0x0000001FU
-#define PMU_PD_HP_PERI_PD_MASK_S  27
-
-/** PMU_POWER_PD_HPWIFI_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x108)
-/** PMU_FORCE_HP_WIFI_RESET : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_WIFI_RESET    (BIT(0))
-#define PMU_FORCE_HP_WIFI_RESET_M  (PMU_FORCE_HP_WIFI_RESET_V << PMU_FORCE_HP_WIFI_RESET_S)
-#define PMU_FORCE_HP_WIFI_RESET_V  0x00000001U
-#define PMU_FORCE_HP_WIFI_RESET_S  0
-/** PMU_FORCE_HP_WIFI_ISO : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_WIFI_ISO    (BIT(1))
-#define PMU_FORCE_HP_WIFI_ISO_M  (PMU_FORCE_HP_WIFI_ISO_V << PMU_FORCE_HP_WIFI_ISO_S)
-#define PMU_FORCE_HP_WIFI_ISO_V  0x00000001U
-#define PMU_FORCE_HP_WIFI_ISO_S  1
-/** PMU_FORCE_HP_WIFI_PU : R/W; bitpos: [2]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_WIFI_PU    (BIT(2))
-#define PMU_FORCE_HP_WIFI_PU_M  (PMU_FORCE_HP_WIFI_PU_V << PMU_FORCE_HP_WIFI_PU_S)
-#define PMU_FORCE_HP_WIFI_PU_V  0x00000001U
-#define PMU_FORCE_HP_WIFI_PU_S  2
-/** PMU_FORCE_HP_WIFI_NO_RESET : R/W; bitpos: [3]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_WIFI_NO_RESET    (BIT(3))
-#define PMU_FORCE_HP_WIFI_NO_RESET_M  (PMU_FORCE_HP_WIFI_NO_RESET_V << PMU_FORCE_HP_WIFI_NO_RESET_S)
-#define PMU_FORCE_HP_WIFI_NO_RESET_V  0x00000001U
-#define PMU_FORCE_HP_WIFI_NO_RESET_S  3
-/** PMU_FORCE_HP_WIFI_NO_ISO : R/W; bitpos: [4]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_WIFI_NO_ISO    (BIT(4))
-#define PMU_FORCE_HP_WIFI_NO_ISO_M  (PMU_FORCE_HP_WIFI_NO_ISO_V << PMU_FORCE_HP_WIFI_NO_ISO_S)
-#define PMU_FORCE_HP_WIFI_NO_ISO_V  0x00000001U
-#define PMU_FORCE_HP_WIFI_NO_ISO_S  4
-/** PMU_FORCE_HP_WIFI_PD : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_WIFI_PD    (BIT(5))
-#define PMU_FORCE_HP_WIFI_PD_M  (PMU_FORCE_HP_WIFI_PD_V << PMU_FORCE_HP_WIFI_PD_S)
-#define PMU_FORCE_HP_WIFI_PD_V  0x00000001U
-#define PMU_FORCE_HP_WIFI_PD_S  5
-/** PMU_PD_HP_WIFI_MASK : R/W; bitpos: [10:6]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_WIFI_MASK    0x0000001FU
-#define PMU_PD_HP_WIFI_MASK_M  (PMU_PD_HP_WIFI_MASK_V << PMU_PD_HP_WIFI_MASK_S)
-#define PMU_PD_HP_WIFI_MASK_V  0x0000001FU
-#define PMU_PD_HP_WIFI_MASK_S  6
-/** PMU_PD_HP_WIFI_PD_MASK : R/W; bitpos: [31:27]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_WIFI_PD_MASK    0x0000001FU
-#define PMU_PD_HP_WIFI_PD_MASK_M  (PMU_PD_HP_WIFI_PD_MASK_V << PMU_PD_HP_WIFI_PD_MASK_S)
-#define PMU_PD_HP_WIFI_PD_MASK_V  0x0000001FU
-#define PMU_PD_HP_WIFI_PD_MASK_S  27
-
-/** PMU_POWER_PD_LPPERI_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x10c)
-/** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_LP_PERI_RESET    (BIT(0))
-#define PMU_FORCE_LP_PERI_RESET_M  (PMU_FORCE_LP_PERI_RESET_V << PMU_FORCE_LP_PERI_RESET_S)
-#define PMU_FORCE_LP_PERI_RESET_V  0x00000001U
-#define PMU_FORCE_LP_PERI_RESET_S  0
-/** PMU_FORCE_LP_PERI_ISO : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_LP_PERI_ISO    (BIT(1))
-#define PMU_FORCE_LP_PERI_ISO_M  (PMU_FORCE_LP_PERI_ISO_V << PMU_FORCE_LP_PERI_ISO_S)
-#define PMU_FORCE_LP_PERI_ISO_V  0x00000001U
-#define PMU_FORCE_LP_PERI_ISO_S  1
-/** PMU_FORCE_LP_PERI_PU : R/W; bitpos: [2]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_LP_PERI_PU    (BIT(2))
-#define PMU_FORCE_LP_PERI_PU_M  (PMU_FORCE_LP_PERI_PU_V << PMU_FORCE_LP_PERI_PU_S)
-#define PMU_FORCE_LP_PERI_PU_V  0x00000001U
-#define PMU_FORCE_LP_PERI_PU_S  2
-/** PMU_FORCE_LP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_LP_PERI_NO_RESET    (BIT(3))
-#define PMU_FORCE_LP_PERI_NO_RESET_M  (PMU_FORCE_LP_PERI_NO_RESET_V << PMU_FORCE_LP_PERI_NO_RESET_S)
-#define PMU_FORCE_LP_PERI_NO_RESET_V  0x00000001U
-#define PMU_FORCE_LP_PERI_NO_RESET_S  3
-/** PMU_FORCE_LP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_LP_PERI_NO_ISO    (BIT(4))
-#define PMU_FORCE_LP_PERI_NO_ISO_M  (PMU_FORCE_LP_PERI_NO_ISO_V << PMU_FORCE_LP_PERI_NO_ISO_S)
-#define PMU_FORCE_LP_PERI_NO_ISO_V  0x00000001U
-#define PMU_FORCE_LP_PERI_NO_ISO_S  4
-/** PMU_FORCE_LP_PERI_PD : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_LP_PERI_PD    (BIT(5))
-#define PMU_FORCE_LP_PERI_PD_M  (PMU_FORCE_LP_PERI_PD_V << PMU_FORCE_LP_PERI_PD_S)
-#define PMU_FORCE_LP_PERI_PD_V  0x00000001U
-#define PMU_FORCE_LP_PERI_PD_S  5
-
-/** PMU_POWER_PD_MEM_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x110)
-/** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [3:0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_MEM_ISO    0x0000000FU
-#define PMU_FORCE_HP_MEM_ISO_M  (PMU_FORCE_HP_MEM_ISO_V << PMU_FORCE_HP_MEM_ISO_S)
-#define PMU_FORCE_HP_MEM_ISO_V  0x0000000FU
-#define PMU_FORCE_HP_MEM_ISO_S  0
-/** PMU_FORCE_HP_MEM_PD : R/W; bitpos: [7:4]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_MEM_PD    0x0000000FU
-#define PMU_FORCE_HP_MEM_PD_M  (PMU_FORCE_HP_MEM_PD_V << PMU_FORCE_HP_MEM_PD_S)
-#define PMU_FORCE_HP_MEM_PD_V  0x0000000FU
-#define PMU_FORCE_HP_MEM_PD_S  4
-/** PMU_FORCE_HP_MEM_NO_ISO : R/W; bitpos: [27:24]; default: 15;
- *  need_des
- */
-#define PMU_FORCE_HP_MEM_NO_ISO    0x0000000FU
-#define PMU_FORCE_HP_MEM_NO_ISO_M  (PMU_FORCE_HP_MEM_NO_ISO_V << PMU_FORCE_HP_MEM_NO_ISO_S)
-#define PMU_FORCE_HP_MEM_NO_ISO_V  0x0000000FU
-#define PMU_FORCE_HP_MEM_NO_ISO_S  24
-/** PMU_FORCE_HP_MEM_PU : R/W; bitpos: [31:28]; default: 15;
- *  need_des
- */
-#define PMU_FORCE_HP_MEM_PU    0x0000000FU
-#define PMU_FORCE_HP_MEM_PU_M  (PMU_FORCE_HP_MEM_PU_V << PMU_FORCE_HP_MEM_PU_S)
-#define PMU_FORCE_HP_MEM_PU_V  0x0000000FU
-#define PMU_FORCE_HP_MEM_PU_S  28
-
-/** PMU_POWER_PD_MEM_MASK_REG register
- *  need_des
- */
-#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x114)
-/** PMU_PD_HP_MEM2_PD_MASK : R/W; bitpos: [4:0]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_MEM2_PD_MASK    0x0000001FU
-#define PMU_PD_HP_MEM2_PD_MASK_M  (PMU_PD_HP_MEM2_PD_MASK_V << PMU_PD_HP_MEM2_PD_MASK_S)
-#define PMU_PD_HP_MEM2_PD_MASK_V  0x0000001FU
-#define PMU_PD_HP_MEM2_PD_MASK_S  0
-/** PMU_PD_HP_MEM1_PD_MASK : R/W; bitpos: [9:5]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_MEM1_PD_MASK    0x0000001FU
-#define PMU_PD_HP_MEM1_PD_MASK_M  (PMU_PD_HP_MEM1_PD_MASK_V << PMU_PD_HP_MEM1_PD_MASK_S)
-#define PMU_PD_HP_MEM1_PD_MASK_V  0x0000001FU
-#define PMU_PD_HP_MEM1_PD_MASK_S  5
-/** PMU_PD_HP_MEM0_PD_MASK : R/W; bitpos: [14:10]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_MEM0_PD_MASK    0x0000001FU
-#define PMU_PD_HP_MEM0_PD_MASK_M  (PMU_PD_HP_MEM0_PD_MASK_V << PMU_PD_HP_MEM0_PD_MASK_S)
-#define PMU_PD_HP_MEM0_PD_MASK_V  0x0000001FU
-#define PMU_PD_HP_MEM0_PD_MASK_S  10
-/** PMU_PD_HP_MEM2_MASK : R/W; bitpos: [21:17]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_MEM2_MASK    0x0000001FU
-#define PMU_PD_HP_MEM2_MASK_M  (PMU_PD_HP_MEM2_MASK_V << PMU_PD_HP_MEM2_MASK_S)
-#define PMU_PD_HP_MEM2_MASK_V  0x0000001FU
-#define PMU_PD_HP_MEM2_MASK_S  17
-/** PMU_PD_HP_MEM1_MASK : R/W; bitpos: [26:22]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_MEM1_MASK    0x0000001FU
-#define PMU_PD_HP_MEM1_MASK_M  (PMU_PD_HP_MEM1_MASK_V << PMU_PD_HP_MEM1_MASK_S)
-#define PMU_PD_HP_MEM1_MASK_V  0x0000001FU
-#define PMU_PD_HP_MEM1_MASK_S  22
-/** PMU_PD_HP_MEM0_MASK : R/W; bitpos: [31:27]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_MEM0_MASK    0x0000001FU
-#define PMU_PD_HP_MEM0_MASK_M  (PMU_PD_HP_MEM0_MASK_V << PMU_PD_HP_MEM0_MASK_S)
-#define PMU_PD_HP_MEM0_MASK_V  0x0000001FU
-#define PMU_PD_HP_MEM0_MASK_S  27
-
-/** PMU_POWER_HP_PAD_REG register
- *  need_des
- */
-#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x118)
-/** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_PAD_NO_ISO_ALL    (BIT(0))
-#define PMU_FORCE_HP_PAD_NO_ISO_ALL_M  (PMU_FORCE_HP_PAD_NO_ISO_ALL_V << PMU_FORCE_HP_PAD_NO_ISO_ALL_S)
-#define PMU_FORCE_HP_PAD_NO_ISO_ALL_V  0x00000001U
-#define PMU_FORCE_HP_PAD_NO_ISO_ALL_S  0
-/** PMU_FORCE_HP_PAD_ISO_ALL : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_PAD_ISO_ALL    (BIT(1))
-#define PMU_FORCE_HP_PAD_ISO_ALL_M  (PMU_FORCE_HP_PAD_ISO_ALL_V << PMU_FORCE_HP_PAD_ISO_ALL_S)
-#define PMU_FORCE_HP_PAD_ISO_ALL_V  0x00000001U
-#define PMU_FORCE_HP_PAD_ISO_ALL_S  1
-
-/** PMU_POWER_FLASH1P8_LDO_REG register
- *  need_des
- */
-#define PMU_POWER_FLASH1P8_LDO_REG (DR_REG_PMU_BASE + 0x11c)
-/** PMU_FLASH1P8_LDO_RDY : RO; bitpos: [0]; default: 1;
- *  need_des
- */
-#define PMU_FLASH1P8_LDO_RDY    (BIT(0))
-#define PMU_FLASH1P8_LDO_RDY_M  (PMU_FLASH1P8_LDO_RDY_V << PMU_FLASH1P8_LDO_RDY_S)
-#define PMU_FLASH1P8_LDO_RDY_V  0x00000001U
-#define PMU_FLASH1P8_LDO_RDY_S  0
-/** PMU_FLASH1P8_SW_EN_XPD : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P8_SW_EN_XPD    (BIT(1))
-#define PMU_FLASH1P8_SW_EN_XPD_M  (PMU_FLASH1P8_SW_EN_XPD_V << PMU_FLASH1P8_SW_EN_XPD_S)
-#define PMU_FLASH1P8_SW_EN_XPD_V  0x00000001U
-#define PMU_FLASH1P8_SW_EN_XPD_S  1
-/** PMU_FLASH1P8_SW_EN_THRU : R/W; bitpos: [2]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P8_SW_EN_THRU    (BIT(2))
-#define PMU_FLASH1P8_SW_EN_THRU_M  (PMU_FLASH1P8_SW_EN_THRU_V << PMU_FLASH1P8_SW_EN_THRU_S)
-#define PMU_FLASH1P8_SW_EN_THRU_V  0x00000001U
-#define PMU_FLASH1P8_SW_EN_THRU_S  2
-/** PMU_FLASH1P8_SW_EN_STANDBY : R/W; bitpos: [3]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P8_SW_EN_STANDBY    (BIT(3))
-#define PMU_FLASH1P8_SW_EN_STANDBY_M  (PMU_FLASH1P8_SW_EN_STANDBY_V << PMU_FLASH1P8_SW_EN_STANDBY_S)
-#define PMU_FLASH1P8_SW_EN_STANDBY_V  0x00000001U
-#define PMU_FLASH1P8_SW_EN_STANDBY_S  3
-/** PMU_FLASH1P8_SW_EN_POWER_ADJUST : R/W; bitpos: [4]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P8_SW_EN_POWER_ADJUST    (BIT(4))
-#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_M  (PMU_FLASH1P8_SW_EN_POWER_ADJUST_V << PMU_FLASH1P8_SW_EN_POWER_ADJUST_S)
-#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_V  0x00000001U
-#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_S  4
-/** PMU_FLASH1P8_SW_EN_ENDET : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P8_SW_EN_ENDET    (BIT(5))
-#define PMU_FLASH1P8_SW_EN_ENDET_M  (PMU_FLASH1P8_SW_EN_ENDET_V << PMU_FLASH1P8_SW_EN_ENDET_S)
-#define PMU_FLASH1P8_SW_EN_ENDET_V  0x00000001U
-#define PMU_FLASH1P8_SW_EN_ENDET_S  5
-/** PMU_FLASH1P8_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P8_BYPASS_LDO_RDY    (BIT(22))
-#define PMU_FLASH1P8_BYPASS_LDO_RDY_M  (PMU_FLASH1P8_BYPASS_LDO_RDY_V << PMU_FLASH1P8_BYPASS_LDO_RDY_S)
-#define PMU_FLASH1P8_BYPASS_LDO_RDY_V  0x00000001U
-#define PMU_FLASH1P8_BYPASS_LDO_RDY_S  22
-/** PMU_FLASH1P8_XPD : R/W; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P8_XPD    (BIT(23))
-#define PMU_FLASH1P8_XPD_M  (PMU_FLASH1P8_XPD_V << PMU_FLASH1P8_XPD_S)
-#define PMU_FLASH1P8_XPD_V  0x00000001U
-#define PMU_FLASH1P8_XPD_S  23
-/** PMU_FLASH1P8_THRU : R/W; bitpos: [24]; default: 1;
- *  need_des
- */
-#define PMU_FLASH1P8_THRU    (BIT(24))
-#define PMU_FLASH1P8_THRU_M  (PMU_FLASH1P8_THRU_V << PMU_FLASH1P8_THRU_S)
-#define PMU_FLASH1P8_THRU_V  0x00000001U
-#define PMU_FLASH1P8_THRU_S  24
-/** PMU_FLASH1P8_STANDBY : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P8_STANDBY    (BIT(25))
-#define PMU_FLASH1P8_STANDBY_M  (PMU_FLASH1P8_STANDBY_V << PMU_FLASH1P8_STANDBY_S)
-#define PMU_FLASH1P8_STANDBY_V  0x00000001U
-#define PMU_FLASH1P8_STANDBY_S  25
-/** PMU_FLASH1P8_POWER_ADJUST : R/W; bitpos: [29:26]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P8_POWER_ADJUST    0x0000000FU
-#define PMU_FLASH1P8_POWER_ADJUST_M  (PMU_FLASH1P8_POWER_ADJUST_V << PMU_FLASH1P8_POWER_ADJUST_S)
-#define PMU_FLASH1P8_POWER_ADJUST_V  0x0000000FU
-#define PMU_FLASH1P8_POWER_ADJUST_S  26
-/** PMU_FLASH1P8_ENDET : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P8_ENDET    (BIT(31))
-#define PMU_FLASH1P8_ENDET_M  (PMU_FLASH1P8_ENDET_V << PMU_FLASH1P8_ENDET_S)
-#define PMU_FLASH1P8_ENDET_V  0x00000001U
-#define PMU_FLASH1P8_ENDET_S  31
-
-/** PMU_POWER_FLASH1P2_LDO_REG register
- *  need_des
- */
-#define PMU_POWER_FLASH1P2_LDO_REG (DR_REG_PMU_BASE + 0x120)
-/** PMU_FLASH1P2_LDO_RDY : RO; bitpos: [0]; default: 1;
- *  need_des
- */
-#define PMU_FLASH1P2_LDO_RDY    (BIT(0))
-#define PMU_FLASH1P2_LDO_RDY_M  (PMU_FLASH1P2_LDO_RDY_V << PMU_FLASH1P2_LDO_RDY_S)
-#define PMU_FLASH1P2_LDO_RDY_V  0x00000001U
-#define PMU_FLASH1P2_LDO_RDY_S  0
-/** PMU_FLASH1P2_SW_EN_XPD : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P2_SW_EN_XPD    (BIT(1))
-#define PMU_FLASH1P2_SW_EN_XPD_M  (PMU_FLASH1P2_SW_EN_XPD_V << PMU_FLASH1P2_SW_EN_XPD_S)
-#define PMU_FLASH1P2_SW_EN_XPD_V  0x00000001U
-#define PMU_FLASH1P2_SW_EN_XPD_S  1
-/** PMU_FLASH1P2_SW_EN_THRU : R/W; bitpos: [2]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P2_SW_EN_THRU    (BIT(2))
-#define PMU_FLASH1P2_SW_EN_THRU_M  (PMU_FLASH1P2_SW_EN_THRU_V << PMU_FLASH1P2_SW_EN_THRU_S)
-#define PMU_FLASH1P2_SW_EN_THRU_V  0x00000001U
-#define PMU_FLASH1P2_SW_EN_THRU_S  2
-/** PMU_FLASH1P2_SW_EN_STANDBY : R/W; bitpos: [3]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P2_SW_EN_STANDBY    (BIT(3))
-#define PMU_FLASH1P2_SW_EN_STANDBY_M  (PMU_FLASH1P2_SW_EN_STANDBY_V << PMU_FLASH1P2_SW_EN_STANDBY_S)
-#define PMU_FLASH1P2_SW_EN_STANDBY_V  0x00000001U
-#define PMU_FLASH1P2_SW_EN_STANDBY_S  3
-/** PMU_FLASH1P2_SW_EN_POWER_ADJUST : R/W; bitpos: [4]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P2_SW_EN_POWER_ADJUST    (BIT(4))
-#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_M  (PMU_FLASH1P2_SW_EN_POWER_ADJUST_V << PMU_FLASH1P2_SW_EN_POWER_ADJUST_S)
-#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_V  0x00000001U
-#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_S  4
-/** PMU_FLASH1P2_SW_EN_ENDET : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P2_SW_EN_ENDET    (BIT(5))
-#define PMU_FLASH1P2_SW_EN_ENDET_M  (PMU_FLASH1P2_SW_EN_ENDET_V << PMU_FLASH1P2_SW_EN_ENDET_S)
-#define PMU_FLASH1P2_SW_EN_ENDET_V  0x00000001U
-#define PMU_FLASH1P2_SW_EN_ENDET_S  5
-/** PMU_FLASH1P2_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P2_BYPASS_LDO_RDY    (BIT(22))
-#define PMU_FLASH1P2_BYPASS_LDO_RDY_M  (PMU_FLASH1P2_BYPASS_LDO_RDY_V << PMU_FLASH1P2_BYPASS_LDO_RDY_S)
-#define PMU_FLASH1P2_BYPASS_LDO_RDY_V  0x00000001U
-#define PMU_FLASH1P2_BYPASS_LDO_RDY_S  22
-/** PMU_FLASH1P2_XPD : R/W; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P2_XPD    (BIT(23))
-#define PMU_FLASH1P2_XPD_M  (PMU_FLASH1P2_XPD_V << PMU_FLASH1P2_XPD_S)
-#define PMU_FLASH1P2_XPD_V  0x00000001U
-#define PMU_FLASH1P2_XPD_S  23
-/** PMU_FLASH1P2_THRU : R/W; bitpos: [24]; default: 1;
- *  need_des
- */
-#define PMU_FLASH1P2_THRU    (BIT(24))
-#define PMU_FLASH1P2_THRU_M  (PMU_FLASH1P2_THRU_V << PMU_FLASH1P2_THRU_S)
-#define PMU_FLASH1P2_THRU_V  0x00000001U
-#define PMU_FLASH1P2_THRU_S  24
-/** PMU_FLASH1P2_STANDBY : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P2_STANDBY    (BIT(25))
-#define PMU_FLASH1P2_STANDBY_M  (PMU_FLASH1P2_STANDBY_V << PMU_FLASH1P2_STANDBY_S)
-#define PMU_FLASH1P2_STANDBY_V  0x00000001U
-#define PMU_FLASH1P2_STANDBY_S  25
-/** PMU_FLASH1P2_POWER_ADJUST : R/W; bitpos: [29:26]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P2_POWER_ADJUST    0x0000000FU
-#define PMU_FLASH1P2_POWER_ADJUST_M  (PMU_FLASH1P2_POWER_ADJUST_V << PMU_FLASH1P2_POWER_ADJUST_S)
-#define PMU_FLASH1P2_POWER_ADJUST_V  0x0000000FU
-#define PMU_FLASH1P2_POWER_ADJUST_S  26
-/** PMU_FLASH1P2_ENDET : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_FLASH1P2_ENDET    (BIT(31))
-#define PMU_FLASH1P2_ENDET_M  (PMU_FLASH1P2_ENDET_V << PMU_FLASH1P2_ENDET_S)
-#define PMU_FLASH1P2_ENDET_V  0x00000001U
-#define PMU_FLASH1P2_ENDET_S  31
-
-/** PMU_POWER_VDD_FLASH_REG register
- *  need_des
- */
-#define PMU_POWER_VDD_FLASH_REG (DR_REG_PMU_BASE + 0x124)
-/** PMU_FLASH_LDO_SW_EN_TIEL : R/W; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_FLASH_LDO_SW_EN_TIEL    (BIT(22))
-#define PMU_FLASH_LDO_SW_EN_TIEL_M  (PMU_FLASH_LDO_SW_EN_TIEL_V << PMU_FLASH_LDO_SW_EN_TIEL_S)
-#define PMU_FLASH_LDO_SW_EN_TIEL_V  0x00000001U
-#define PMU_FLASH_LDO_SW_EN_TIEL_S  22
-/** PMU_FLASH_LDO_POWER_SEL : R/W; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_FLASH_LDO_POWER_SEL    (BIT(23))
-#define PMU_FLASH_LDO_POWER_SEL_M  (PMU_FLASH_LDO_POWER_SEL_V << PMU_FLASH_LDO_POWER_SEL_S)
-#define PMU_FLASH_LDO_POWER_SEL_V  0x00000001U
-#define PMU_FLASH_LDO_POWER_SEL_S  23
-/** PMU_FLASH_LDO_SW_EN_POWER_SEL : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_FLASH_LDO_SW_EN_POWER_SEL    (BIT(24))
-#define PMU_FLASH_LDO_SW_EN_POWER_SEL_M  (PMU_FLASH_LDO_SW_EN_POWER_SEL_V << PMU_FLASH_LDO_SW_EN_POWER_SEL_S)
-#define PMU_FLASH_LDO_SW_EN_POWER_SEL_V  0x00000001U
-#define PMU_FLASH_LDO_SW_EN_POWER_SEL_S  24
-/** PMU_FLASH_LDO_WAIT_TARGET : R/W; bitpos: [28:25]; default: 15;
- *  need_des
- */
-#define PMU_FLASH_LDO_WAIT_TARGET    0x0000000FU
-#define PMU_FLASH_LDO_WAIT_TARGET_M  (PMU_FLASH_LDO_WAIT_TARGET_V << PMU_FLASH_LDO_WAIT_TARGET_S)
-#define PMU_FLASH_LDO_WAIT_TARGET_V  0x0000000FU
-#define PMU_FLASH_LDO_WAIT_TARGET_S  25
-/** PMU_FLASH_LDO_TIEL_EN : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_FLASH_LDO_TIEL_EN    (BIT(29))
-#define PMU_FLASH_LDO_TIEL_EN_M  (PMU_FLASH_LDO_TIEL_EN_V << PMU_FLASH_LDO_TIEL_EN_S)
-#define PMU_FLASH_LDO_TIEL_EN_V  0x00000001U
-#define PMU_FLASH_LDO_TIEL_EN_S  29
-/** PMU_FLASH_LDO_TIEL : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_FLASH_LDO_TIEL    (BIT(30))
-#define PMU_FLASH_LDO_TIEL_M  (PMU_FLASH_LDO_TIEL_V << PMU_FLASH_LDO_TIEL_S)
-#define PMU_FLASH_LDO_TIEL_V  0x00000001U
-#define PMU_FLASH_LDO_TIEL_S  30
-/** PMU_FLASH_LDO_SW_UPDATE : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_FLASH_LDO_SW_UPDATE    (BIT(31))
-#define PMU_FLASH_LDO_SW_UPDATE_M  (PMU_FLASH_LDO_SW_UPDATE_V << PMU_FLASH_LDO_SW_UPDATE_S)
-#define PMU_FLASH_LDO_SW_UPDATE_V  0x00000001U
-#define PMU_FLASH_LDO_SW_UPDATE_S  31
-
-/** PMU_POWER_IO_LDO_REG register
- *  need_des
- */
-#define PMU_POWER_IO_LDO_REG (DR_REG_PMU_BASE + 0x128)
-/** PMU_IO_LDO_RDY : RO; bitpos: [0]; default: 1;
- *  need_des
- */
-#define PMU_IO_LDO_RDY    (BIT(0))
-#define PMU_IO_LDO_RDY_M  (PMU_IO_LDO_RDY_V << PMU_IO_LDO_RDY_S)
-#define PMU_IO_LDO_RDY_V  0x00000001U
-#define PMU_IO_LDO_RDY_S  0
-/** PMU_IO_SW_EN_XPD : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_IO_SW_EN_XPD    (BIT(1))
-#define PMU_IO_SW_EN_XPD_M  (PMU_IO_SW_EN_XPD_V << PMU_IO_SW_EN_XPD_S)
-#define PMU_IO_SW_EN_XPD_V  0x00000001U
-#define PMU_IO_SW_EN_XPD_S  1
-/** PMU_IO_SW_EN_THRU : R/W; bitpos: [3]; default: 0;
- *  need_des
- */
-#define PMU_IO_SW_EN_THRU    (BIT(3))
-#define PMU_IO_SW_EN_THRU_M  (PMU_IO_SW_EN_THRU_V << PMU_IO_SW_EN_THRU_S)
-#define PMU_IO_SW_EN_THRU_V  0x00000001U
-#define PMU_IO_SW_EN_THRU_S  3
-/** PMU_IO_SW_EN_STANDBY : R/W; bitpos: [4]; default: 0;
- *  need_des
- */
-#define PMU_IO_SW_EN_STANDBY    (BIT(4))
-#define PMU_IO_SW_EN_STANDBY_M  (PMU_IO_SW_EN_STANDBY_V << PMU_IO_SW_EN_STANDBY_S)
-#define PMU_IO_SW_EN_STANDBY_V  0x00000001U
-#define PMU_IO_SW_EN_STANDBY_S  4
-/** PMU_IO_SW_EN_POWER_ADJUST : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_IO_SW_EN_POWER_ADJUST    (BIT(5))
-#define PMU_IO_SW_EN_POWER_ADJUST_M  (PMU_IO_SW_EN_POWER_ADJUST_V << PMU_IO_SW_EN_POWER_ADJUST_S)
-#define PMU_IO_SW_EN_POWER_ADJUST_V  0x00000001U
-#define PMU_IO_SW_EN_POWER_ADJUST_S  5
-/** PMU_IO_SW_EN_ENDET : R/W; bitpos: [6]; default: 0;
- *  need_des
- */
-#define PMU_IO_SW_EN_ENDET    (BIT(6))
-#define PMU_IO_SW_EN_ENDET_M  (PMU_IO_SW_EN_ENDET_V << PMU_IO_SW_EN_ENDET_S)
-#define PMU_IO_SW_EN_ENDET_V  0x00000001U
-#define PMU_IO_SW_EN_ENDET_S  6
-/** PMU_IO_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_IO_BYPASS_LDO_RDY    (BIT(22))
-#define PMU_IO_BYPASS_LDO_RDY_M  (PMU_IO_BYPASS_LDO_RDY_V << PMU_IO_BYPASS_LDO_RDY_S)
-#define PMU_IO_BYPASS_LDO_RDY_V  0x00000001U
-#define PMU_IO_BYPASS_LDO_RDY_S  22
-/** PMU_IO_XPD : R/W; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_IO_XPD    (BIT(23))
-#define PMU_IO_XPD_M  (PMU_IO_XPD_V << PMU_IO_XPD_S)
-#define PMU_IO_XPD_V  0x00000001U
-#define PMU_IO_XPD_S  23
-/** PMU_IO_THRU : R/W; bitpos: [24]; default: 1;
- *  need_des
- */
-#define PMU_IO_THRU    (BIT(24))
-#define PMU_IO_THRU_M  (PMU_IO_THRU_V << PMU_IO_THRU_S)
-#define PMU_IO_THRU_V  0x00000001U
-#define PMU_IO_THRU_S  24
-/** PMU_IO_STANDBY : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_IO_STANDBY    (BIT(25))
-#define PMU_IO_STANDBY_M  (PMU_IO_STANDBY_V << PMU_IO_STANDBY_S)
-#define PMU_IO_STANDBY_V  0x00000001U
-#define PMU_IO_STANDBY_S  25
-/** PMU_IO_POWER_ADJUST : R/W; bitpos: [29:26]; default: 0;
- *  need_des
- */
-#define PMU_IO_POWER_ADJUST    0x0000000FU
-#define PMU_IO_POWER_ADJUST_M  (PMU_IO_POWER_ADJUST_V << PMU_IO_POWER_ADJUST_S)
-#define PMU_IO_POWER_ADJUST_V  0x0000000FU
-#define PMU_IO_POWER_ADJUST_S  26
-/** PMU_IO_ENDET : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_IO_ENDET    (BIT(31))
-#define PMU_IO_ENDET_M  (PMU_IO_ENDET_V << PMU_IO_ENDET_S)
-#define PMU_IO_ENDET_V  0x00000001U
-#define PMU_IO_ENDET_S  31
-
-/** PMU_POWER_VDD_IO_REG register
- *  need_des
- */
-#define PMU_POWER_VDD_IO_REG (DR_REG_PMU_BASE + 0x12c)
-/** PMU_IO_LDO_POWER_SEL : R/W; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_IO_LDO_POWER_SEL    (BIT(23))
-#define PMU_IO_LDO_POWER_SEL_M  (PMU_IO_LDO_POWER_SEL_V << PMU_IO_LDO_POWER_SEL_S)
-#define PMU_IO_LDO_POWER_SEL_V  0x00000001U
-#define PMU_IO_LDO_POWER_SEL_S  23
-/** PMU_IO_LDO_SW_EN_POWER_SEL : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_IO_LDO_SW_EN_POWER_SEL    (BIT(24))
-#define PMU_IO_LDO_SW_EN_POWER_SEL_M  (PMU_IO_LDO_SW_EN_POWER_SEL_V << PMU_IO_LDO_SW_EN_POWER_SEL_S)
-#define PMU_IO_LDO_SW_EN_POWER_SEL_V  0x00000001U
-#define PMU_IO_LDO_SW_EN_POWER_SEL_S  24
-
-/** PMU_POWER_CK_WAIT_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x130)
-/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256;
- *  need_des
- */
-#define PMU_WAIT_XTL_STABLE    0x0000FFFFU
-#define PMU_WAIT_XTL_STABLE_M  (PMU_WAIT_XTL_STABLE_V << PMU_WAIT_XTL_STABLE_S)
-#define PMU_WAIT_XTL_STABLE_V  0x0000FFFFU
-#define PMU_WAIT_XTL_STABLE_S  0
-/** PMU_WAIT_PLL_STABLE : R/W; bitpos: [31:16]; default: 256;
- *  need_des
- */
-#define PMU_WAIT_PLL_STABLE    0x0000FFFFU
-#define PMU_WAIT_PLL_STABLE_M  (PMU_WAIT_PLL_STABLE_V << PMU_WAIT_PLL_STABLE_S)
-#define PMU_WAIT_PLL_STABLE_V  0x0000FFFFU
-#define PMU_WAIT_PLL_STABLE_S  16
-
-/** PMU_SLP_WAKEUP_CNTL0_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x134)
-/** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_REQ    (BIT(31))
-#define PMU_SLEEP_REQ_M  (PMU_SLEEP_REQ_V << PMU_SLEEP_REQ_S)
-#define PMU_SLEEP_REQ_V  0x00000001U
-#define PMU_SLEEP_REQ_S  31
-
-/** PMU_SLP_WAKEUP_CNTL1_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x138)
-/** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_REJECT_ENA    0x7FFFFFFFU
-#define PMU_SLEEP_REJECT_ENA_M  (PMU_SLEEP_REJECT_ENA_V << PMU_SLEEP_REJECT_ENA_S)
-#define PMU_SLEEP_REJECT_ENA_V  0x7FFFFFFFU
-#define PMU_SLEEP_REJECT_ENA_S  0
-/** PMU_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_SLP_REJECT_EN    (BIT(31))
-#define PMU_SLP_REJECT_EN_M  (PMU_SLP_REJECT_EN_V << PMU_SLP_REJECT_EN_S)
-#define PMU_SLP_REJECT_EN_V  0x00000001U
-#define PMU_SLP_REJECT_EN_S  31
-
-/** PMU_SLP_WAKEUP_CNTL2_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x13c)
-/** PMU_WAKEUP_ENA : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define PMU_WAKEUP_ENA    0xFFFFFFFFU
-#define PMU_WAKEUP_ENA_M  (PMU_WAKEUP_ENA_V << PMU_WAKEUP_ENA_S)
-#define PMU_WAKEUP_ENA_V  0xFFFFFFFFU
-#define PMU_WAKEUP_ENA_S  0
-
-/** PMU_SLP_WAKEUP_CNTL3_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x140)
-/** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0;
- *  need_des
- */
-#define PMU_LP_MIN_SLP_VAL    0x000000FFU
-#define PMU_LP_MIN_SLP_VAL_M  (PMU_LP_MIN_SLP_VAL_V << PMU_LP_MIN_SLP_VAL_S)
-#define PMU_LP_MIN_SLP_VAL_V  0x000000FFU
-#define PMU_LP_MIN_SLP_VAL_S  0
-/** PMU_HP_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 0;
- *  need_des
- */
-#define PMU_HP_MIN_SLP_VAL    0x000000FFU
-#define PMU_HP_MIN_SLP_VAL_M  (PMU_HP_MIN_SLP_VAL_V << PMU_HP_MIN_SLP_VAL_S)
-#define PMU_HP_MIN_SLP_VAL_V  0x000000FFU
-#define PMU_HP_MIN_SLP_VAL_S  8
-/** PMU_SLEEP_PRT_SEL : R/W; bitpos: [17:16]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_PRT_SEL    0x00000003U
-#define PMU_SLEEP_PRT_SEL_M  (PMU_SLEEP_PRT_SEL_V << PMU_SLEEP_PRT_SEL_S)
-#define PMU_SLEEP_PRT_SEL_V  0x00000003U
-#define PMU_SLEEP_PRT_SEL_S  16
-
-/** PMU_SLP_WAKEUP_CNTL4_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x144)
-/** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_SLP_REJECT_CAUSE_CLR    (BIT(31))
-#define PMU_SLP_REJECT_CAUSE_CLR_M  (PMU_SLP_REJECT_CAUSE_CLR_V << PMU_SLP_REJECT_CAUSE_CLR_S)
-#define PMU_SLP_REJECT_CAUSE_CLR_V  0x00000001U
-#define PMU_SLP_REJECT_CAUSE_CLR_S  31
-
-/** PMU_SLP_WAKEUP_CNTL5_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x148)
-/** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128;
- *  need_des
- */
-#define PMU_MODEM_WAIT_TARGET    0x000FFFFFU
-#define PMU_MODEM_WAIT_TARGET_M  (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S)
-#define PMU_MODEM_WAIT_TARGET_V  0x000FFFFFU
-#define PMU_MODEM_WAIT_TARGET_S  0
-/** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1;
- *  need_des
- */
-#define PMU_LP_ANA_WAIT_TARGET    0x000000FFU
-#define PMU_LP_ANA_WAIT_TARGET_M  (PMU_LP_ANA_WAIT_TARGET_V << PMU_LP_ANA_WAIT_TARGET_S)
-#define PMU_LP_ANA_WAIT_TARGET_V  0x000000FFU
-#define PMU_LP_ANA_WAIT_TARGET_S  24
-
-/** PMU_SLP_WAKEUP_CNTL6_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x14c)
-/** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128;
- *  need_des
- */
-#define PMU_SOC_WAKEUP_WAIT    0x000FFFFFU
-#define PMU_SOC_WAKEUP_WAIT_M  (PMU_SOC_WAKEUP_WAIT_V << PMU_SOC_WAKEUP_WAIT_S)
-#define PMU_SOC_WAKEUP_WAIT_V  0x000FFFFFU
-#define PMU_SOC_WAKEUP_WAIT_S  0
-/** PMU_SOC_WAKEUP_WAIT_CFG : R/W; bitpos: [31:30]; default: 0;
- *  need_des
- */
-#define PMU_SOC_WAKEUP_WAIT_CFG    0x00000003U
-#define PMU_SOC_WAKEUP_WAIT_CFG_M  (PMU_SOC_WAKEUP_WAIT_CFG_V << PMU_SOC_WAKEUP_WAIT_CFG_S)
-#define PMU_SOC_WAKEUP_WAIT_CFG_V  0x00000003U
-#define PMU_SOC_WAKEUP_WAIT_CFG_S  30
-
-/** PMU_SLP_WAKEUP_CNTL7_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x150)
-/** PMU_ANA_WAIT_CLK_SEL : R/W; bitpos: [15]; default: 0;
- *  need_des
- */
-#define PMU_ANA_WAIT_CLK_SEL    (BIT(15))
-#define PMU_ANA_WAIT_CLK_SEL_M  (PMU_ANA_WAIT_CLK_SEL_V << PMU_ANA_WAIT_CLK_SEL_S)
-#define PMU_ANA_WAIT_CLK_SEL_V  0x00000001U
-#define PMU_ANA_WAIT_CLK_SEL_S  15
-/** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1;
- *  need_des
- */
-#define PMU_ANA_WAIT_TARGET    0x0000FFFFU
-#define PMU_ANA_WAIT_TARGET_M  (PMU_ANA_WAIT_TARGET_V << PMU_ANA_WAIT_TARGET_S)
-#define PMU_ANA_WAIT_TARGET_V  0x0000FFFFU
-#define PMU_ANA_WAIT_TARGET_S  16
-
-/** PMU_SLP_WAKEUP_STATUS0_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x154)
-/** PMU_WAKEUP_CAUSE : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define PMU_WAKEUP_CAUSE    0xFFFFFFFFU
-#define PMU_WAKEUP_CAUSE_M  (PMU_WAKEUP_CAUSE_V << PMU_WAKEUP_CAUSE_S)
-#define PMU_WAKEUP_CAUSE_V  0xFFFFFFFFU
-#define PMU_WAKEUP_CAUSE_S  0
-
-/** PMU_SLP_WAKEUP_STATUS1_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x158)
-/** PMU_REJECT_CAUSE : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define PMU_REJECT_CAUSE    0xFFFFFFFFU
-#define PMU_REJECT_CAUSE_M  (PMU_REJECT_CAUSE_V << PMU_REJECT_CAUSE_S)
-#define PMU_REJECT_CAUSE_V  0xFFFFFFFFU
-#define PMU_REJECT_CAUSE_S  0
-
-/** PMU_HP_CK_POWERON_REG register
- *  need_des
- */
-#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x15c)
-/** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50;
- *  need_des
- */
-#define PMU_I2C_POR_WAIT_TARGET    0x000000FFU
-#define PMU_I2C_POR_WAIT_TARGET_M  (PMU_I2C_POR_WAIT_TARGET_V << PMU_I2C_POR_WAIT_TARGET_S)
-#define PMU_I2C_POR_WAIT_TARGET_V  0x000000FFU
-#define PMU_I2C_POR_WAIT_TARGET_S  0
-
-/** PMU_HP_CK_CNTL_REG register
- *  need_des
- */
-#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x160)
-/** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10;
- *  need_des
- */
-#define PMU_MODIFY_ICG_CNTL_WAIT    0x000000FFU
-#define PMU_MODIFY_ICG_CNTL_WAIT_M  (PMU_MODIFY_ICG_CNTL_WAIT_V << PMU_MODIFY_ICG_CNTL_WAIT_S)
-#define PMU_MODIFY_ICG_CNTL_WAIT_V  0x000000FFU
-#define PMU_MODIFY_ICG_CNTL_WAIT_S  0
-/** PMU_SWITCH_ICG_CNTL_WAIT : R/W; bitpos: [15:8]; default: 10;
- *  need_des
- */
-#define PMU_SWITCH_ICG_CNTL_WAIT    0x000000FFU
-#define PMU_SWITCH_ICG_CNTL_WAIT_M  (PMU_SWITCH_ICG_CNTL_WAIT_V << PMU_SWITCH_ICG_CNTL_WAIT_S)
-#define PMU_SWITCH_ICG_CNTL_WAIT_V  0x000000FFU
-#define PMU_SWITCH_ICG_CNTL_WAIT_S  8
-
-/** PMU_POR_STATUS_REG register
- *  need_des
- */
-#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x164)
-/** PMU_POR_DONE : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_POR_DONE    (BIT(31))
-#define PMU_POR_DONE_M  (PMU_POR_DONE_V << PMU_POR_DONE_S)
-#define PMU_POR_DONE_V  0x00000001U
-#define PMU_POR_DONE_S  31
-
-/** PMU_RF_PWC_REG register
- *  need_des
- */
-#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x168)
-/** PMU_XPD_FORCE_RFTX : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_XPD_FORCE_RFTX    (BIT(26))
-#define PMU_XPD_FORCE_RFTX_M  (PMU_XPD_FORCE_RFTX_V << PMU_XPD_FORCE_RFTX_S)
-#define PMU_XPD_FORCE_RFTX_V  0x00000001U
-#define PMU_XPD_FORCE_RFTX_S  26
-/** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1;
- *  need_des
- */
-#define PMU_XPD_PERIF_I2C    (BIT(27))
-#define PMU_XPD_PERIF_I2C_M  (PMU_XPD_PERIF_I2C_V << PMU_XPD_PERIF_I2C_S)
-#define PMU_XPD_PERIF_I2C_V  0x00000001U
-#define PMU_XPD_PERIF_I2C_S  27
-/** PMU_XPD_RFTX_I2C : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_XPD_RFTX_I2C    (BIT(28))
-#define PMU_XPD_RFTX_I2C_M  (PMU_XPD_RFTX_I2C_V << PMU_XPD_RFTX_I2C_S)
-#define PMU_XPD_RFTX_I2C_V  0x00000001U
-#define PMU_XPD_RFTX_I2C_S  28
-/** PMU_XPD_RFRX_I2C : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_XPD_RFRX_I2C    (BIT(29))
-#define PMU_XPD_RFRX_I2C_M  (PMU_XPD_RFRX_I2C_V << PMU_XPD_RFRX_I2C_S)
-#define PMU_XPD_RFRX_I2C_V  0x00000001U
-#define PMU_XPD_RFRX_I2C_S  29
-/** PMU_XPD_RFPLL : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_XPD_RFPLL    (BIT(30))
-#define PMU_XPD_RFPLL_M  (PMU_XPD_RFPLL_V << PMU_XPD_RFPLL_S)
-#define PMU_XPD_RFPLL_V  0x00000001U
-#define PMU_XPD_RFPLL_S  30
-/** PMU_XPD_FORCE_RFPLL : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_XPD_FORCE_RFPLL    (BIT(31))
-#define PMU_XPD_FORCE_RFPLL_M  (PMU_XPD_FORCE_RFPLL_V << PMU_XPD_FORCE_RFPLL_S)
-#define PMU_XPD_FORCE_RFPLL_V  0x00000001U
-#define PMU_XPD_FORCE_RFPLL_S  31
-
-/** PMU_VDDBAT_CFG_REG register
- *  need_des
- */
-#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x16c)
-/** PMU_VDDBAT_MODE : RO; bitpos: [1:0]; default: 0;
- *  need_des
- */
-#define PMU_VDDBAT_MODE    0x00000003U
-#define PMU_VDDBAT_MODE_M  (PMU_VDDBAT_MODE_V << PMU_VDDBAT_MODE_S)
-#define PMU_VDDBAT_MODE_V  0x00000003U
-#define PMU_VDDBAT_MODE_S  0
-/** PMU_VDDBAT_SW_UPDATE : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_VDDBAT_SW_UPDATE    (BIT(31))
-#define PMU_VDDBAT_SW_UPDATE_M  (PMU_VDDBAT_SW_UPDATE_V << PMU_VDDBAT_SW_UPDATE_S)
-#define PMU_VDDBAT_SW_UPDATE_V  0x00000001U
-#define PMU_VDDBAT_SW_UPDATE_S  31
-
-/** PMU_BACKUP_CFG_REG register
- *  need_des
- */
-#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x170)
-/** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define PMU_BACKUP_SYS_CLK_NO_DIV    (BIT(31))
-#define PMU_BACKUP_SYS_CLK_NO_DIV_M  (PMU_BACKUP_SYS_CLK_NO_DIV_V << PMU_BACKUP_SYS_CLK_NO_DIV_S)
-#define PMU_BACKUP_SYS_CLK_NO_DIV_V  0x00000001U
-#define PMU_BACKUP_SYS_CLK_NO_DIV_S  31
-
-/** PMU_INT_RAW_REG register
- *  need_des
- */
-#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x174)
-/** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_EXC_INT_RAW    (BIT(27))
-#define PMU_LP_CPU_EXC_INT_RAW_M  (PMU_LP_CPU_EXC_INT_RAW_V << PMU_LP_CPU_EXC_INT_RAW_S)
-#define PMU_LP_CPU_EXC_INT_RAW_V  0x00000001U
-#define PMU_LP_CPU_EXC_INT_RAW_S  27
-/** PMU_SDIO_IDLE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SDIO_IDLE_INT_RAW    (BIT(28))
-#define PMU_SDIO_IDLE_INT_RAW_M  (PMU_SDIO_IDLE_INT_RAW_V << PMU_SDIO_IDLE_INT_RAW_S)
-#define PMU_SDIO_IDLE_INT_RAW_V  0x00000001U
-#define PMU_SDIO_IDLE_INT_RAW_S  28
-/** PMU_SW_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_SW_INT_RAW    (BIT(29))
-#define PMU_SW_INT_RAW_M  (PMU_SW_INT_RAW_V << PMU_SW_INT_RAW_S)
-#define PMU_SW_INT_RAW_V  0x00000001U
-#define PMU_SW_INT_RAW_S  29
-/** PMU_SOC_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_SOC_SLEEP_REJECT_INT_RAW    (BIT(30))
-#define PMU_SOC_SLEEP_REJECT_INT_RAW_M  (PMU_SOC_SLEEP_REJECT_INT_RAW_V << PMU_SOC_SLEEP_REJECT_INT_RAW_S)
-#define PMU_SOC_SLEEP_REJECT_INT_RAW_V  0x00000001U
-#define PMU_SOC_SLEEP_REJECT_INT_RAW_S  30
-/** PMU_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_SOC_WAKEUP_INT_RAW    (BIT(31))
-#define PMU_SOC_WAKEUP_INT_RAW_M  (PMU_SOC_WAKEUP_INT_RAW_V << PMU_SOC_WAKEUP_INT_RAW_S)
-#define PMU_SOC_WAKEUP_INT_RAW_V  0x00000001U
-#define PMU_SOC_WAKEUP_INT_RAW_S  31
-
-/** PMU_HP_INT_ST_REG register
- *  need_des
- */
-#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x178)
-/** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_EXC_INT_ST    (BIT(27))
-#define PMU_LP_CPU_EXC_INT_ST_M  (PMU_LP_CPU_EXC_INT_ST_V << PMU_LP_CPU_EXC_INT_ST_S)
-#define PMU_LP_CPU_EXC_INT_ST_V  0x00000001U
-#define PMU_LP_CPU_EXC_INT_ST_S  27
-/** PMU_SDIO_IDLE_INT_ST : RO; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SDIO_IDLE_INT_ST    (BIT(28))
-#define PMU_SDIO_IDLE_INT_ST_M  (PMU_SDIO_IDLE_INT_ST_V << PMU_SDIO_IDLE_INT_ST_S)
-#define PMU_SDIO_IDLE_INT_ST_V  0x00000001U
-#define PMU_SDIO_IDLE_INT_ST_S  28
-/** PMU_SW_INT_ST : RO; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_SW_INT_ST    (BIT(29))
-#define PMU_SW_INT_ST_M  (PMU_SW_INT_ST_V << PMU_SW_INT_ST_S)
-#define PMU_SW_INT_ST_V  0x00000001U
-#define PMU_SW_INT_ST_S  29
-/** PMU_SOC_SLEEP_REJECT_INT_ST : RO; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_SOC_SLEEP_REJECT_INT_ST    (BIT(30))
-#define PMU_SOC_SLEEP_REJECT_INT_ST_M  (PMU_SOC_SLEEP_REJECT_INT_ST_V << PMU_SOC_SLEEP_REJECT_INT_ST_S)
-#define PMU_SOC_SLEEP_REJECT_INT_ST_V  0x00000001U
-#define PMU_SOC_SLEEP_REJECT_INT_ST_S  30
-/** PMU_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_SOC_WAKEUP_INT_ST    (BIT(31))
-#define PMU_SOC_WAKEUP_INT_ST_M  (PMU_SOC_WAKEUP_INT_ST_V << PMU_SOC_WAKEUP_INT_ST_S)
-#define PMU_SOC_WAKEUP_INT_ST_V  0x00000001U
-#define PMU_SOC_WAKEUP_INT_ST_S  31
-
-/** PMU_HP_INT_ENA_REG register
- *  need_des
- */
-#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x17c)
-/** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_EXC_INT_ENA    (BIT(27))
-#define PMU_LP_CPU_EXC_INT_ENA_M  (PMU_LP_CPU_EXC_INT_ENA_V << PMU_LP_CPU_EXC_INT_ENA_S)
-#define PMU_LP_CPU_EXC_INT_ENA_V  0x00000001U
-#define PMU_LP_CPU_EXC_INT_ENA_S  27
-/** PMU_SDIO_IDLE_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SDIO_IDLE_INT_ENA    (BIT(28))
-#define PMU_SDIO_IDLE_INT_ENA_M  (PMU_SDIO_IDLE_INT_ENA_V << PMU_SDIO_IDLE_INT_ENA_S)
-#define PMU_SDIO_IDLE_INT_ENA_V  0x00000001U
-#define PMU_SDIO_IDLE_INT_ENA_S  28
-/** PMU_SW_INT_ENA : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_SW_INT_ENA    (BIT(29))
-#define PMU_SW_INT_ENA_M  (PMU_SW_INT_ENA_V << PMU_SW_INT_ENA_S)
-#define PMU_SW_INT_ENA_V  0x00000001U
-#define PMU_SW_INT_ENA_S  29
-/** PMU_SOC_SLEEP_REJECT_INT_ENA : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_SOC_SLEEP_REJECT_INT_ENA    (BIT(30))
-#define PMU_SOC_SLEEP_REJECT_INT_ENA_M  (PMU_SOC_SLEEP_REJECT_INT_ENA_V << PMU_SOC_SLEEP_REJECT_INT_ENA_S)
-#define PMU_SOC_SLEEP_REJECT_INT_ENA_V  0x00000001U
-#define PMU_SOC_SLEEP_REJECT_INT_ENA_S  30
-/** PMU_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_SOC_WAKEUP_INT_ENA    (BIT(31))
-#define PMU_SOC_WAKEUP_INT_ENA_M  (PMU_SOC_WAKEUP_INT_ENA_V << PMU_SOC_WAKEUP_INT_ENA_S)
-#define PMU_SOC_WAKEUP_INT_ENA_V  0x00000001U
-#define PMU_SOC_WAKEUP_INT_ENA_S  31
-
-/** PMU_HP_INT_CLR_REG register
- *  need_des
- */
-#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x180)
-/** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_EXC_INT_CLR    (BIT(27))
-#define PMU_LP_CPU_EXC_INT_CLR_M  (PMU_LP_CPU_EXC_INT_CLR_V << PMU_LP_CPU_EXC_INT_CLR_S)
-#define PMU_LP_CPU_EXC_INT_CLR_V  0x00000001U
-#define PMU_LP_CPU_EXC_INT_CLR_S  27
-/** PMU_SDIO_IDLE_INT_CLR : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SDIO_IDLE_INT_CLR    (BIT(28))
-#define PMU_SDIO_IDLE_INT_CLR_M  (PMU_SDIO_IDLE_INT_CLR_V << PMU_SDIO_IDLE_INT_CLR_S)
-#define PMU_SDIO_IDLE_INT_CLR_V  0x00000001U
-#define PMU_SDIO_IDLE_INT_CLR_S  28
-/** PMU_SW_INT_CLR : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_SW_INT_CLR    (BIT(29))
-#define PMU_SW_INT_CLR_M  (PMU_SW_INT_CLR_V << PMU_SW_INT_CLR_S)
-#define PMU_SW_INT_CLR_V  0x00000001U
-#define PMU_SW_INT_CLR_S  29
-/** PMU_SOC_SLEEP_REJECT_INT_CLR : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_SOC_SLEEP_REJECT_INT_CLR    (BIT(30))
-#define PMU_SOC_SLEEP_REJECT_INT_CLR_M  (PMU_SOC_SLEEP_REJECT_INT_CLR_V << PMU_SOC_SLEEP_REJECT_INT_CLR_S)
-#define PMU_SOC_SLEEP_REJECT_INT_CLR_V  0x00000001U
-#define PMU_SOC_SLEEP_REJECT_INT_CLR_S  30
-/** PMU_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_SOC_WAKEUP_INT_CLR    (BIT(31))
-#define PMU_SOC_WAKEUP_INT_CLR_M  (PMU_SOC_WAKEUP_INT_CLR_V << PMU_SOC_WAKEUP_INT_CLR_S)
-#define PMU_SOC_WAKEUP_INT_CLR_V  0x00000001U
-#define PMU_SOC_WAKEUP_INT_CLR_S  31
-
-/** PMU_LP_INT_RAW_REG register
- *  need_des
- */
-#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x184)
-/** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_WAKEUP_INT_RAW    (BIT(20))
-#define PMU_LP_CPU_WAKEUP_INT_RAW_M  (PMU_LP_CPU_WAKEUP_INT_RAW_V << PMU_LP_CPU_WAKEUP_INT_RAW_S)
-#define PMU_LP_CPU_WAKEUP_INT_RAW_V  0x00000001U
-#define PMU_LP_CPU_WAKEUP_INT_RAW_S  20
-/** PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW    (BIT(21))
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_M  (PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S)
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S  21
-/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW    (BIT(22))
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S  22
-/** PMU_SLEEP_SWITCH_MODEM_END_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW    (BIT(23))
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_M  (PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S)
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S  23
-/** PMU_MODEM_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW    (BIT(24))
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_M  (PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S)
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S  24
-/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW    (BIT(25))
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S  25
-/** PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW    (BIT(26))
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_M  (PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S)
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S  26
-/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW    (BIT(27))
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S  27
-/** PMU_SLEEP_SWITCH_MODEM_START_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW    (BIT(28))
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_M  (PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S)
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S  28
-/** PMU_MODEM_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW    (BIT(29))
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_M  (PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S)
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S  29
-/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW    (BIT(30))
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S  30
-/** PMU_HP_SW_TRIGGER_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SW_TRIGGER_INT_RAW    (BIT(31))
-#define PMU_HP_SW_TRIGGER_INT_RAW_M  (PMU_HP_SW_TRIGGER_INT_RAW_V << PMU_HP_SW_TRIGGER_INT_RAW_S)
-#define PMU_HP_SW_TRIGGER_INT_RAW_V  0x00000001U
-#define PMU_HP_SW_TRIGGER_INT_RAW_S  31
-
-/** PMU_LP_INT_ST_REG register
- *  need_des
- */
-#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x188)
-/** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [20]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_WAKEUP_INT_ST    (BIT(20))
-#define PMU_LP_CPU_WAKEUP_INT_ST_M  (PMU_LP_CPU_WAKEUP_INT_ST_V << PMU_LP_CPU_WAKEUP_INT_ST_S)
-#define PMU_LP_CPU_WAKEUP_INT_ST_V  0x00000001U
-#define PMU_LP_CPU_WAKEUP_INT_ST_S  20
-/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [21]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST    (BIT(21))
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_M  (PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S)
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S  21
-/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST    (BIT(22))
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S  22
-/** PMU_SLEEP_SWITCH_MODEM_END_INT_ST : RO; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST    (BIT(23))
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_M  (PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S)
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S  23
-/** PMU_MODEM_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST    (BIT(24))
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_M  (PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S)
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S  24
-/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST    (BIT(25))
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S  25
-/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST    (BIT(26))
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_M  (PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S)
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S  26
-/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST    (BIT(27))
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S  27
-/** PMU_SLEEP_SWITCH_MODEM_START_INT_ST : RO; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST    (BIT(28))
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_M  (PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S)
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S  28
-/** PMU_MODEM_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST    (BIT(29))
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_M  (PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S)
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S  29
-/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST    (BIT(30))
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S  30
-/** PMU_HP_SW_TRIGGER_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SW_TRIGGER_INT_ST    (BIT(31))
-#define PMU_HP_SW_TRIGGER_INT_ST_M  (PMU_HP_SW_TRIGGER_INT_ST_V << PMU_HP_SW_TRIGGER_INT_ST_S)
-#define PMU_HP_SW_TRIGGER_INT_ST_V  0x00000001U
-#define PMU_HP_SW_TRIGGER_INT_ST_S  31
-
-/** PMU_LP_INT_ENA_REG register
- *  need_des
- */
-#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x18c)
-/** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_WAKEUP_INT_ENA    (BIT(20))
-#define PMU_LP_CPU_WAKEUP_INT_ENA_M  (PMU_LP_CPU_WAKEUP_INT_ENA_V << PMU_LP_CPU_WAKEUP_INT_ENA_S)
-#define PMU_LP_CPU_WAKEUP_INT_ENA_V  0x00000001U
-#define PMU_LP_CPU_WAKEUP_INT_ENA_S  20
-/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA    (BIT(21))
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_M  (PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S)
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S  21
-/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA    (BIT(22))
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S  22
-/** PMU_SLEEP_SWITCH_MODEM_END_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA    (BIT(23))
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_M  (PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S)
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S  23
-/** PMU_MODEM_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA    (BIT(24))
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_M  (PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S)
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S  24
-/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA    (BIT(25))
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S  25
-/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA    (BIT(26))
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_M  (PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S)
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S  26
-/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA    (BIT(27))
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S  27
-/** PMU_SLEEP_SWITCH_MODEM_START_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA    (BIT(28))
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_M  (PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S)
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S  28
-/** PMU_MODEM_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA    (BIT(29))
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_M  (PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S)
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S  29
-/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA    (BIT(30))
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S  30
-/** PMU_HP_SW_TRIGGER_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SW_TRIGGER_INT_ENA    (BIT(31))
-#define PMU_HP_SW_TRIGGER_INT_ENA_M  (PMU_HP_SW_TRIGGER_INT_ENA_V << PMU_HP_SW_TRIGGER_INT_ENA_S)
-#define PMU_HP_SW_TRIGGER_INT_ENA_V  0x00000001U
-#define PMU_HP_SW_TRIGGER_INT_ENA_S  31
-
-/** PMU_LP_INT_CLR_REG register
- *  need_des
- */
-#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x190)
-/** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [20]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_WAKEUP_INT_CLR    (BIT(20))
-#define PMU_LP_CPU_WAKEUP_INT_CLR_M  (PMU_LP_CPU_WAKEUP_INT_CLR_V << PMU_LP_CPU_WAKEUP_INT_CLR_S)
-#define PMU_LP_CPU_WAKEUP_INT_CLR_V  0x00000001U
-#define PMU_LP_CPU_WAKEUP_INT_CLR_S  20
-/** PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [21]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR    (BIT(21))
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_M  (PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S)
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S  21
-/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR    (BIT(22))
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S  22
-/** PMU_SLEEP_SWITCH_MODEM_END_INT_CLR : WT; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR    (BIT(23))
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_M  (PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S)
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S  23
-/** PMU_MODEM_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR    (BIT(24))
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_M  (PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S)
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S  24
-/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR    (BIT(25))
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S  25
-/** PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR    (BIT(26))
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_M  (PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S)
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S  26
-/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR    (BIT(27))
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S  27
-/** PMU_SLEEP_SWITCH_MODEM_START_INT_CLR : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR    (BIT(28))
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_M  (PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S)
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S  28
-/** PMU_MODEM_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR    (BIT(29))
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_M  (PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S)
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S  29
-/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR    (BIT(30))
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S  30
-/** PMU_HP_SW_TRIGGER_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SW_TRIGGER_INT_CLR    (BIT(31))
-#define PMU_HP_SW_TRIGGER_INT_CLR_M  (PMU_HP_SW_TRIGGER_INT_CLR_V << PMU_HP_SW_TRIGGER_INT_CLR_S)
-#define PMU_HP_SW_TRIGGER_INT_CLR_V  0x00000001U
-#define PMU_HP_SW_TRIGGER_INT_CLR_S  31
-
-/** PMU_LP_CPU_PWR0_REG register
- *  need_des
- */
-#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x194)
-/** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_WAITI_RDY    (BIT(0))
-#define PMU_LP_CPU_WAITI_RDY_M  (PMU_LP_CPU_WAITI_RDY_V << PMU_LP_CPU_WAITI_RDY_S)
-#define PMU_LP_CPU_WAITI_RDY_V  0x00000001U
-#define PMU_LP_CPU_WAITI_RDY_S  0
-/** PMU_LP_CPU_STALL_RDY : RO; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_STALL_RDY    (BIT(1))
-#define PMU_LP_CPU_STALL_RDY_M  (PMU_LP_CPU_STALL_RDY_V << PMU_LP_CPU_STALL_RDY_S)
-#define PMU_LP_CPU_STALL_RDY_V  0x00000001U
-#define PMU_LP_CPU_STALL_RDY_S  1
-/** PMU_LP_CPU_FORCE_STALL : R/W; bitpos: [18]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_FORCE_STALL    (BIT(18))
-#define PMU_LP_CPU_FORCE_STALL_M  (PMU_LP_CPU_FORCE_STALL_V << PMU_LP_CPU_FORCE_STALL_S)
-#define PMU_LP_CPU_FORCE_STALL_V  0x00000001U
-#define PMU_LP_CPU_FORCE_STALL_S  18
-/** PMU_LP_CPU_SLP_WAITI_FLAG_EN : R/W; bitpos: [19]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_SLP_WAITI_FLAG_EN    (BIT(19))
-#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_M  (PMU_LP_CPU_SLP_WAITI_FLAG_EN_V << PMU_LP_CPU_SLP_WAITI_FLAG_EN_S)
-#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_V  0x00000001U
-#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_S  19
-/** PMU_LP_CPU_SLP_STALL_FLAG_EN : R/W; bitpos: [20]; default: 1;
- *  need_des
- */
-#define PMU_LP_CPU_SLP_STALL_FLAG_EN    (BIT(20))
-#define PMU_LP_CPU_SLP_STALL_FLAG_EN_M  (PMU_LP_CPU_SLP_STALL_FLAG_EN_V << PMU_LP_CPU_SLP_STALL_FLAG_EN_S)
-#define PMU_LP_CPU_SLP_STALL_FLAG_EN_V  0x00000001U
-#define PMU_LP_CPU_SLP_STALL_FLAG_EN_S  20
-/** PMU_LP_CPU_SLP_STALL_WAIT : R/W; bitpos: [28:21]; default: 255;
- *  need_des
- */
-#define PMU_LP_CPU_SLP_STALL_WAIT    0x000000FFU
-#define PMU_LP_CPU_SLP_STALL_WAIT_M  (PMU_LP_CPU_SLP_STALL_WAIT_V << PMU_LP_CPU_SLP_STALL_WAIT_S)
-#define PMU_LP_CPU_SLP_STALL_WAIT_V  0x000000FFU
-#define PMU_LP_CPU_SLP_STALL_WAIT_S  21
-/** PMU_LP_CPU_SLP_STALL_EN : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_SLP_STALL_EN    (BIT(29))
-#define PMU_LP_CPU_SLP_STALL_EN_M  (PMU_LP_CPU_SLP_STALL_EN_V << PMU_LP_CPU_SLP_STALL_EN_S)
-#define PMU_LP_CPU_SLP_STALL_EN_V  0x00000001U
-#define PMU_LP_CPU_SLP_STALL_EN_S  29
-/** PMU_LP_CPU_SLP_RESET_EN : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_SLP_RESET_EN    (BIT(30))
-#define PMU_LP_CPU_SLP_RESET_EN_M  (PMU_LP_CPU_SLP_RESET_EN_V << PMU_LP_CPU_SLP_RESET_EN_S)
-#define PMU_LP_CPU_SLP_RESET_EN_V  0x00000001U
-#define PMU_LP_CPU_SLP_RESET_EN_S  30
-/** PMU_LP_CPU_SLP_BYPASS_INTR_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_SLP_BYPASS_INTR_EN    (BIT(31))
-#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_M  (PMU_LP_CPU_SLP_BYPASS_INTR_EN_V << PMU_LP_CPU_SLP_BYPASS_INTR_EN_S)
-#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_V  0x00000001U
-#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_S  31
-
-/** PMU_LP_CPU_PWR1_REG register
- *  need_des
- */
-#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x198)
-/** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_WAKEUP_EN    0x0000FFFFU
-#define PMU_LP_CPU_WAKEUP_EN_M  (PMU_LP_CPU_WAKEUP_EN_V << PMU_LP_CPU_WAKEUP_EN_S)
-#define PMU_LP_CPU_WAKEUP_EN_V  0x0000FFFFU
-#define PMU_LP_CPU_WAKEUP_EN_S  0
-/** PMU_LP_CPU_SLEEP_REQ : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_SLEEP_REQ    (BIT(31))
-#define PMU_LP_CPU_SLEEP_REQ_M  (PMU_LP_CPU_SLEEP_REQ_V << PMU_LP_CPU_SLEEP_REQ_S)
-#define PMU_LP_CPU_SLEEP_REQ_V  0x00000001U
-#define PMU_LP_CPU_SLEEP_REQ_S  31
-
-/** PMU_HP_LP_CPU_COMM_REG register
- *  need_des
- */
-#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x19c)
-/** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_LP_TRIGGER_HP    (BIT(30))
-#define PMU_LP_TRIGGER_HP_M  (PMU_LP_TRIGGER_HP_V << PMU_LP_TRIGGER_HP_S)
-#define PMU_LP_TRIGGER_HP_V  0x00000001U
-#define PMU_LP_TRIGGER_HP_S  30
-/** PMU_HP_TRIGGER_LP : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_TRIGGER_LP    (BIT(31))
-#define PMU_HP_TRIGGER_LP_M  (PMU_HP_TRIGGER_LP_V << PMU_HP_TRIGGER_LP_S)
-#define PMU_HP_TRIGGER_LP_V  0x00000001U
-#define PMU_HP_TRIGGER_LP_S  31
-
-/** PMU_HP_REGULATOR_CFG_REG register
- *  need_des
- */
-#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x1a0)
-/** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_DIG_REGULATOR_EN_CAL    (BIT(31))
-#define PMU_DIG_REGULATOR_EN_CAL_M  (PMU_DIG_REGULATOR_EN_CAL_V << PMU_DIG_REGULATOR_EN_CAL_S)
-#define PMU_DIG_REGULATOR_EN_CAL_V  0x00000001U
-#define PMU_DIG_REGULATOR_EN_CAL_S  31
-
-/** PMU_MAIN_STATE_REG register
- *  need_des
- */
-#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x1a4)
-/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 256;
- *  need_des
- */
-#define PMU_MAIN_LAST_ST_STATE    0x0000007FU
-#define PMU_MAIN_LAST_ST_STATE_M  (PMU_MAIN_LAST_ST_STATE_V << PMU_MAIN_LAST_ST_STATE_S)
-#define PMU_MAIN_LAST_ST_STATE_V  0x0000007FU
-#define PMU_MAIN_LAST_ST_STATE_S  11
-/** PMU_MAIN_TAR_ST_STATE : RO; bitpos: [24:18]; default: 4;
- *  need_des
- */
-#define PMU_MAIN_TAR_ST_STATE    0x0000007FU
-#define PMU_MAIN_TAR_ST_STATE_M  (PMU_MAIN_TAR_ST_STATE_V << PMU_MAIN_TAR_ST_STATE_S)
-#define PMU_MAIN_TAR_ST_STATE_V  0x0000007FU
-#define PMU_MAIN_TAR_ST_STATE_S  18
-/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 1;
- *  need_des
- */
-#define PMU_MAIN_CUR_ST_STATE    0x0000007FU
-#define PMU_MAIN_CUR_ST_STATE_M  (PMU_MAIN_CUR_ST_STATE_V << PMU_MAIN_CUR_ST_STATE_S)
-#define PMU_MAIN_CUR_ST_STATE_V  0x0000007FU
-#define PMU_MAIN_CUR_ST_STATE_S  25
-
-/** PMU_PWR_STATE_REG register
- *  need_des
- */
-#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x1a8)
-/** PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1;
- *  need_des
- */
-#define PMU_BACKUP_ST_STATE    0x0000001FU
-#define PMU_BACKUP_ST_STATE_M  (PMU_BACKUP_ST_STATE_V << PMU_BACKUP_ST_STATE_S)
-#define PMU_BACKUP_ST_STATE_V  0x0000001FU
-#define PMU_BACKUP_ST_STATE_S  13
-/** PMU_LP_PWR_ST_STATE : RO; bitpos: [22:18]; default: 0;
- *  need_des
- */
-#define PMU_LP_PWR_ST_STATE    0x0000001FU
-#define PMU_LP_PWR_ST_STATE_M  (PMU_LP_PWR_ST_STATE_V << PMU_LP_PWR_ST_STATE_S)
-#define PMU_LP_PWR_ST_STATE_V  0x0000001FU
-#define PMU_LP_PWR_ST_STATE_S  18
-/** PMU_HP_PWR_ST_STATE : RO; bitpos: [31:23]; default: 1;
- *  need_des
- */
-#define PMU_HP_PWR_ST_STATE    0x000001FFU
-#define PMU_HP_PWR_ST_STATE_M  (PMU_HP_PWR_ST_STATE_V << PMU_HP_PWR_ST_STATE_S)
-#define PMU_HP_PWR_ST_STATE_V  0x000001FFU
-#define PMU_HP_PWR_ST_STATE_S  23
-
-/** PMU_CLK_STATE0_REG register
- *  need_des
- */
-#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x1ac)
-/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_STABLE_XPD_BBPLL_STATE    (BIT(0))
-#define PMU_STABLE_XPD_BBPLL_STATE_M  (PMU_STABLE_XPD_BBPLL_STATE_V << PMU_STABLE_XPD_BBPLL_STATE_S)
-#define PMU_STABLE_XPD_BBPLL_STATE_V  0x00000001U
-#define PMU_STABLE_XPD_BBPLL_STATE_S  0
-/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_STABLE_XPD_XTAL_STATE    (BIT(1))
-#define PMU_STABLE_XPD_XTAL_STATE_M  (PMU_STABLE_XPD_XTAL_STATE_V << PMU_STABLE_XPD_XTAL_STATE_S)
-#define PMU_STABLE_XPD_XTAL_STATE_V  0x00000001U
-#define PMU_STABLE_XPD_XTAL_STATE_S  1
-/** PMU_SYS_CLK_SLP_SEL_STATE : RO; bitpos: [15]; default: 0;
- *  need_des
- */
-#define PMU_SYS_CLK_SLP_SEL_STATE    (BIT(15))
-#define PMU_SYS_CLK_SLP_SEL_STATE_M  (PMU_SYS_CLK_SLP_SEL_STATE_V << PMU_SYS_CLK_SLP_SEL_STATE_S)
-#define PMU_SYS_CLK_SLP_SEL_STATE_V  0x00000001U
-#define PMU_SYS_CLK_SLP_SEL_STATE_S  15
-/** PMU_SYS_CLK_SEL_STATE : RO; bitpos: [17:16]; default: 0;
- *  need_des
- */
-#define PMU_SYS_CLK_SEL_STATE    0x00000003U
-#define PMU_SYS_CLK_SEL_STATE_M  (PMU_SYS_CLK_SEL_STATE_V << PMU_SYS_CLK_SEL_STATE_S)
-#define PMU_SYS_CLK_SEL_STATE_V  0x00000003U
-#define PMU_SYS_CLK_SEL_STATE_S  16
-/** PMU_SYS_CLK_NO_DIV_STATE : RO; bitpos: [18]; default: 0;
- *  need_des
- */
-#define PMU_SYS_CLK_NO_DIV_STATE    (BIT(18))
-#define PMU_SYS_CLK_NO_DIV_STATE_M  (PMU_SYS_CLK_NO_DIV_STATE_V << PMU_SYS_CLK_NO_DIV_STATE_S)
-#define PMU_SYS_CLK_NO_DIV_STATE_V  0x00000001U
-#define PMU_SYS_CLK_NO_DIV_STATE_S  18
-/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 1;
- *  need_des
- */
-#define PMU_ICG_SYS_CLK_EN_STATE    (BIT(19))
-#define PMU_ICG_SYS_CLK_EN_STATE_M  (PMU_ICG_SYS_CLK_EN_STATE_V << PMU_ICG_SYS_CLK_EN_STATE_S)
-#define PMU_ICG_SYS_CLK_EN_STATE_V  0x00000001U
-#define PMU_ICG_SYS_CLK_EN_STATE_S  19
-/** PMU_ICG_MODEM_SWITCH_STATE : RO; bitpos: [20]; default: 0;
- *  need_des
- */
-#define PMU_ICG_MODEM_SWITCH_STATE    (BIT(20))
-#define PMU_ICG_MODEM_SWITCH_STATE_M  (PMU_ICG_MODEM_SWITCH_STATE_V << PMU_ICG_MODEM_SWITCH_STATE_S)
-#define PMU_ICG_MODEM_SWITCH_STATE_V  0x00000001U
-#define PMU_ICG_MODEM_SWITCH_STATE_S  20
-/** PMU_ICG_MODEM_CODE_STATE : RO; bitpos: [22:21]; default: 0;
- *  need_des
- */
-#define PMU_ICG_MODEM_CODE_STATE    0x00000003U
-#define PMU_ICG_MODEM_CODE_STATE_M  (PMU_ICG_MODEM_CODE_STATE_V << PMU_ICG_MODEM_CODE_STATE_S)
-#define PMU_ICG_MODEM_CODE_STATE_V  0x00000003U
-#define PMU_ICG_MODEM_CODE_STATE_S  21
-/** PMU_ICG_SLP_SEL_STATE : RO; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_ICG_SLP_SEL_STATE    (BIT(23))
-#define PMU_ICG_SLP_SEL_STATE_M  (PMU_ICG_SLP_SEL_STATE_V << PMU_ICG_SLP_SEL_STATE_S)
-#define PMU_ICG_SLP_SEL_STATE_V  0x00000001U
-#define PMU_ICG_SLP_SEL_STATE_S  23
-/** PMU_ICG_GLOBAL_XTAL_STATE : RO; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_ICG_GLOBAL_XTAL_STATE    (BIT(24))
-#define PMU_ICG_GLOBAL_XTAL_STATE_M  (PMU_ICG_GLOBAL_XTAL_STATE_V << PMU_ICG_GLOBAL_XTAL_STATE_S)
-#define PMU_ICG_GLOBAL_XTAL_STATE_V  0x00000001U
-#define PMU_ICG_GLOBAL_XTAL_STATE_S  24
-/** PMU_ICG_GLOBAL_PLL_STATE : RO; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_ICG_GLOBAL_PLL_STATE    (BIT(25))
-#define PMU_ICG_GLOBAL_PLL_STATE_M  (PMU_ICG_GLOBAL_PLL_STATE_V << PMU_ICG_GLOBAL_PLL_STATE_S)
-#define PMU_ICG_GLOBAL_PLL_STATE_V  0x00000001U
-#define PMU_ICG_GLOBAL_PLL_STATE_S  25
-/** PMU_ANA_I2C_ISO_EN_STATE : RO; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_ANA_I2C_ISO_EN_STATE    (BIT(26))
-#define PMU_ANA_I2C_ISO_EN_STATE_M  (PMU_ANA_I2C_ISO_EN_STATE_V << PMU_ANA_I2C_ISO_EN_STATE_S)
-#define PMU_ANA_I2C_ISO_EN_STATE_V  0x00000001U
-#define PMU_ANA_I2C_ISO_EN_STATE_S  26
-/** PMU_ANA_I2C_RETENTION_STATE : RO; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_ANA_I2C_RETENTION_STATE    (BIT(27))
-#define PMU_ANA_I2C_RETENTION_STATE_M  (PMU_ANA_I2C_RETENTION_STATE_V << PMU_ANA_I2C_RETENTION_STATE_S)
-#define PMU_ANA_I2C_RETENTION_STATE_V  0x00000001U
-#define PMU_ANA_I2C_RETENTION_STATE_S  27
-/** PMU_ANA_XPD_BB_I2C_STATE : RO; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_ANA_XPD_BB_I2C_STATE    (BIT(28))
-#define PMU_ANA_XPD_BB_I2C_STATE_M  (PMU_ANA_XPD_BB_I2C_STATE_V << PMU_ANA_XPD_BB_I2C_STATE_S)
-#define PMU_ANA_XPD_BB_I2C_STATE_V  0x00000001U
-#define PMU_ANA_XPD_BB_I2C_STATE_S  28
-/** PMU_ANA_XPD_BBPLL_I2C_STATE : RO; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_ANA_XPD_BBPLL_I2C_STATE    (BIT(29))
-#define PMU_ANA_XPD_BBPLL_I2C_STATE_M  (PMU_ANA_XPD_BBPLL_I2C_STATE_V << PMU_ANA_XPD_BBPLL_I2C_STATE_S)
-#define PMU_ANA_XPD_BBPLL_I2C_STATE_V  0x00000001U
-#define PMU_ANA_XPD_BBPLL_I2C_STATE_S  29
-/** PMU_ANA_XPD_BBPLL_STATE : RO; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_ANA_XPD_BBPLL_STATE    (BIT(30))
-#define PMU_ANA_XPD_BBPLL_STATE_M  (PMU_ANA_XPD_BBPLL_STATE_V << PMU_ANA_XPD_BBPLL_STATE_S)
-#define PMU_ANA_XPD_BBPLL_STATE_V  0x00000001U
-#define PMU_ANA_XPD_BBPLL_STATE_S  30
-/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 1;
- *  need_des
- */
-#define PMU_ANA_XPD_XTAL_STATE    (BIT(31))
-#define PMU_ANA_XPD_XTAL_STATE_M  (PMU_ANA_XPD_XTAL_STATE_V << PMU_ANA_XPD_XTAL_STATE_S)
-#define PMU_ANA_XPD_XTAL_STATE_V  0x00000001U
-#define PMU_ANA_XPD_XTAL_STATE_S  31
-
-/** PMU_CLK_STATE1_REG register
- *  need_des
- */
-#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x1b0)
-/** PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define PMU_ICG_FUNC_EN_STATE    0xFFFFFFFFU
-#define PMU_ICG_FUNC_EN_STATE_M  (PMU_ICG_FUNC_EN_STATE_V << PMU_ICG_FUNC_EN_STATE_S)
-#define PMU_ICG_FUNC_EN_STATE_V  0xFFFFFFFFU
-#define PMU_ICG_FUNC_EN_STATE_S  0
-
-/** PMU_CLK_STATE2_REG register
- *  need_des
- */
-#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1b4)
-/** PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define PMU_ICG_APB_EN_STATE    0xFFFFFFFFU
-#define PMU_ICG_APB_EN_STATE_M  (PMU_ICG_APB_EN_STATE_V << PMU_ICG_APB_EN_STATE_S)
-#define PMU_ICG_APB_EN_STATE_V  0xFFFFFFFFU
-#define PMU_ICG_APB_EN_STATE_S  0
-
-/** PMU_DCM_CTRL_REG register
- *  need_des
- */
-#define PMU_DCM_CTRL_REG (DR_REG_PMU_BASE + 0x1b8)
-/** PMU_DSFMOS_USE_POR : R/W; bitpos: [0]; default: 1;
- *  need_des
- */
-#define PMU_DSFMOS_USE_POR    (BIT(0))
-#define PMU_DSFMOS_USE_POR_M  (PMU_DSFMOS_USE_POR_V << PMU_DSFMOS_USE_POR_S)
-#define PMU_DSFMOS_USE_POR_V  0x00000001U
-#define PMU_DSFMOS_USE_POR_S  0
-/** PMU_DCDC_DCM_UPDATE : WT; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_DCDC_DCM_UPDATE    (BIT(22))
-#define PMU_DCDC_DCM_UPDATE_M  (PMU_DCDC_DCM_UPDATE_V << PMU_DCDC_DCM_UPDATE_S)
-#define PMU_DCDC_DCM_UPDATE_V  0x00000001U
-#define PMU_DCDC_DCM_UPDATE_S  22
-/** PMU_DCDC_PCUR_LIMIT : R/W; bitpos: [25:23]; default: 1;
- *  need_des
- */
-#define PMU_DCDC_PCUR_LIMIT    0x00000007U
-#define PMU_DCDC_PCUR_LIMIT_M  (PMU_DCDC_PCUR_LIMIT_V << PMU_DCDC_PCUR_LIMIT_S)
-#define PMU_DCDC_PCUR_LIMIT_V  0x00000007U
-#define PMU_DCDC_PCUR_LIMIT_S  23
-/** PMU_DCDC_BIAS_CAL_DONE : RO; bitpos: [26]; default: 1;
- *  need_des
- */
-#define PMU_DCDC_BIAS_CAL_DONE    (BIT(26))
-#define PMU_DCDC_BIAS_CAL_DONE_M  (PMU_DCDC_BIAS_CAL_DONE_V << PMU_DCDC_BIAS_CAL_DONE_S)
-#define PMU_DCDC_BIAS_CAL_DONE_V  0x00000001U
-#define PMU_DCDC_BIAS_CAL_DONE_S  26
-/** PMU_DCDC_CCM_SW_EN : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_DCDC_CCM_SW_EN    (BIT(27))
-#define PMU_DCDC_CCM_SW_EN_M  (PMU_DCDC_CCM_SW_EN_V << PMU_DCDC_CCM_SW_EN_S)
-#define PMU_DCDC_CCM_SW_EN_V  0x00000001U
-#define PMU_DCDC_CCM_SW_EN_S  27
-/** PMU_DCDC_VCM_ENB : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_DCDC_VCM_ENB    (BIT(28))
-#define PMU_DCDC_VCM_ENB_M  (PMU_DCDC_VCM_ENB_V << PMU_DCDC_VCM_ENB_S)
-#define PMU_DCDC_VCM_ENB_V  0x00000001U
-#define PMU_DCDC_VCM_ENB_S  28
-/** PMU_DCDC_CCM_RDY : RO; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_DCDC_CCM_RDY    (BIT(29))
-#define PMU_DCDC_CCM_RDY_M  (PMU_DCDC_CCM_RDY_V << PMU_DCDC_CCM_RDY_S)
-#define PMU_DCDC_CCM_RDY_V  0x00000001U
-#define PMU_DCDC_CCM_RDY_S  29
-/** PMU_DCDC_VCM_RDY : RO; bitpos: [30]; default: 1;
- *  need_des
- */
-#define PMU_DCDC_VCM_RDY    (BIT(30))
-#define PMU_DCDC_VCM_RDY_M  (PMU_DCDC_VCM_RDY_V << PMU_DCDC_VCM_RDY_S)
-#define PMU_DCDC_VCM_RDY_V  0x00000001U
-#define PMU_DCDC_VCM_RDY_S  30
-/** PMU_DCDC_RDY_CLR : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_DCDC_RDY_CLR    (BIT(31))
-#define PMU_DCDC_RDY_CLR_M  (PMU_DCDC_RDY_CLR_V << PMU_DCDC_RDY_CLR_S)
-#define PMU_DCDC_RDY_CLR_V  0x00000001U
-#define PMU_DCDC_RDY_CLR_S  31
-
-/** PMU_DCM_BOOST_CTRL_REG register
- *  need_des
- */
-#define PMU_DCM_BOOST_CTRL_REG (DR_REG_PMU_BASE + 0x1bc)
-/** PMU_DCDC_BOOST_CCM_CTRLEN : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_DCDC_BOOST_CCM_CTRLEN    (BIT(24))
-#define PMU_DCDC_BOOST_CCM_CTRLEN_M  (PMU_DCDC_BOOST_CCM_CTRLEN_V << PMU_DCDC_BOOST_CCM_CTRLEN_S)
-#define PMU_DCDC_BOOST_CCM_CTRLEN_V  0x00000001U
-#define PMU_DCDC_BOOST_CCM_CTRLEN_S  24
-/** PMU_DCDC_BOOST_CCM_ENB : R/W; bitpos: [25]; default: 1;
- *  need_des
- */
-#define PMU_DCDC_BOOST_CCM_ENB    (BIT(25))
-#define PMU_DCDC_BOOST_CCM_ENB_M  (PMU_DCDC_BOOST_CCM_ENB_V << PMU_DCDC_BOOST_CCM_ENB_S)
-#define PMU_DCDC_BOOST_CCM_ENB_V  0x00000001U
-#define PMU_DCDC_BOOST_CCM_ENB_S  25
-/** PMU_DCDC_BOOST_EN : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_DCDC_BOOST_EN    (BIT(26))
-#define PMU_DCDC_BOOST_EN_M  (PMU_DCDC_BOOST_EN_V << PMU_DCDC_BOOST_EN_S)
-#define PMU_DCDC_BOOST_EN_V  0x00000001U
-#define PMU_DCDC_BOOST_EN_S  26
-/** PMU_DCDC_BOOST_DREG : R/W; bitpos: [31:27]; default: 23;
- *  need_des
- */
-#define PMU_DCDC_BOOST_DREG    0x0000001FU
-#define PMU_DCDC_BOOST_DREG_M  (PMU_DCDC_BOOST_DREG_V << PMU_DCDC_BOOST_DREG_S)
-#define PMU_DCDC_BOOST_DREG_V  0x0000001FU
-#define PMU_DCDC_BOOST_DREG_S  27
-
-/** PMU_TOUCH_PWR_CTRL_REG register
- *  need_des
- */
-#define PMU_TOUCH_PWR_CTRL_REG (DR_REG_PMU_BASE + 0x1c0)
-/** PMU_TOUCH_SLEEP_CYCLES : R/W; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define PMU_TOUCH_SLEEP_CYCLES    0x0000FFFFU
-#define PMU_TOUCH_SLEEP_CYCLES_M  (PMU_TOUCH_SLEEP_CYCLES_V << PMU_TOUCH_SLEEP_CYCLES_S)
-#define PMU_TOUCH_SLEEP_CYCLES_V  0x0000FFFFU
-#define PMU_TOUCH_SLEEP_CYCLES_S  0
-/** PMU_TOUCH_WAIT_CYCLES : R/W; bitpos: [29:21]; default: 0;
- *  need_des
- */
-#define PMU_TOUCH_WAIT_CYCLES    0x000001FFU
-#define PMU_TOUCH_WAIT_CYCLES_M  (PMU_TOUCH_WAIT_CYCLES_V << PMU_TOUCH_WAIT_CYCLES_S)
-#define PMU_TOUCH_WAIT_CYCLES_V  0x000001FFU
-#define PMU_TOUCH_WAIT_CYCLES_S  21
-/** PMU_TOUCH_SLEEP_TIMER_EN : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_TOUCH_SLEEP_TIMER_EN    (BIT(30))
-#define PMU_TOUCH_SLEEP_TIMER_EN_M  (PMU_TOUCH_SLEEP_TIMER_EN_V << PMU_TOUCH_SLEEP_TIMER_EN_S)
-#define PMU_TOUCH_SLEEP_TIMER_EN_V  0x00000001U
-#define PMU_TOUCH_SLEEP_TIMER_EN_S  30
-/** PMU_TOUCH_FORCE_DONE : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_TOUCH_FORCE_DONE    (BIT(31))
-#define PMU_TOUCH_FORCE_DONE_M  (PMU_TOUCH_FORCE_DONE_V << PMU_TOUCH_FORCE_DONE_S)
-#define PMU_TOUCH_FORCE_DONE_V  0x00000001U
-#define PMU_TOUCH_FORCE_DONE_S  31
-
-/** PMU_DATE_REG register
- *  need_des
- */
-#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc)
-/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 37818464;
- *  need_des
- */
-#define PMU_PMU_DATE    0x7FFFFFFFU
-#define PMU_PMU_DATE_M  (PMU_PMU_DATE_V << PMU_PMU_DATE_S)
-#define PMU_PMU_DATE_V  0x7FFFFFFFU
-#define PMU_PMU_DATE_S  0
-/** PMU_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_CLK_EN    (BIT(31))
-#define PMU_CLK_EN_M  (PMU_CLK_EN_V << PMU_CLK_EN_S)
-#define PMU_CLK_EN_V  0x00000001U
-#define PMU_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h4/register/hw_ver_beta5/soc/pmu_struct.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/pmu_struct.h
deleted file mode 100644
index 0b8bf3f40c..0000000000
--- a/components/soc/esp32h4/register/hw_ver_beta5/soc/pmu_struct.h
+++ /dev/null
@@ -1,917 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0 OR MIT
- */
-#pragma once
-
-#include <stdint.h>
-#include <stddef.h>
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#include "soc/pmu_reg.h"
-
-typedef union {
-    struct {
-        uint32_t reserved0     : 18;
-        uint32_t vdd_flash_mode: 4;
-        uint32_t mem_dslp      : 1;
-        uint32_t mem_pd_en     : 4;
-        uint32_t wifi_pd_en    : 1;
-        uint32_t peri_pd_en    : 1;
-        uint32_t cpu_pd_en     : 1;
-        uint32_t aon_pd_en     : 1;
-        uint32_t top_pd_en     : 1;
-    };
-    uint32_t val;
-} pmu_hp_dig_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 30;
-        uint32_t code     : 2;
-    };
-    uint32_t val;
-} pmu_hp_icg_modem_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 24;
-        uint32_t uart_wakeup_en : 1;
-        uint32_t lp_pad_hold_all: 1;
-        uint32_t hp_pad_hold_all: 1;
-        uint32_t dig_pad_slp_sel: 1;
-        uint32_t dig_pause_wdt  : 1;
-        uint32_t dig_cpu_stall  : 1;
-        uint32_t reserved1      : 2;
-    };
-    uint32_t val;
-} pmu_hp_sys_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0    : 26;
-        uint32_t i2c_iso_en   : 1;
-        uint32_t i2c_retention: 1;
-        uint32_t xpd_bb_i2c   : 1;
-        uint32_t xpd_bbpll_i2c: 1;
-        uint32_t xpd_bbpll    : 1;
-        uint32_t reserved1    : 1;
-    };
-    uint32_t val;
-} pmu_hp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0         : 9;
-        uint32_t dcdc_ccm_enb      : 1;
-        uint32_t dcdc_clear_rdy    : 1;
-        uint32_t dig_reg_dpcur_bias: 2;
-        uint32_t dig_reg_dsfmos    : 4;
-        uint32_t dcm_vset          : 5;
-        uint32_t dcm_mode          : 2;
-        uint32_t xpd_trx           : 1;
-        uint32_t xpd_bias          : 1;
-        uint32_t reserved1         : 3;
-        uint32_t discnnt_dig_rtc   : 1;
-        uint32_t pd_cur            : 1;
-        uint32_t bias_sleep        : 1;
-    };
-    uint32_t val;
-} pmu_hp_bias_reg_t;
-
-typedef union {
-    struct { /* HP: Active State */
-        uint32_t reserved0                            : 4;
-        uint32_t hp_sleep2active_backup_modem_clk_code: 2;
-        uint32_t hp_modem2active_backup_modem_clk_code: 2;
-        uint32_t reserved1                            : 6;
-        uint32_t hp_sleep2active_backup_clk_sel       : 2;
-        uint32_t hp_modem2active_backup_clk_sel       : 2;
-        uint32_t hp_sleep2active_backup_mode          : 5;
-        uint32_t hp_modem2active_backup_mode          : 5;
-        uint32_t reserved3                            : 1;
-        uint32_t hp_sleep2active_backup_en            : 1;
-        uint32_t hp_modem2active_backup_en            : 1;
-        uint32_t reserved4 : 1;
-    };
-    struct { /* HP: Modem State */
-        uint32_t reserved5                            : 4;
-        uint32_t hp_sleep2modem_backup_modem_clk_code : 2;
-        uint32_t reserved6                            : 8;
-        uint32_t hp_sleep2modem_backup_clk_sel        : 2;
-        uint32_t reserved8                            : 4;
-        uint32_t hp_sleep2modem_backup_mode           : 5;
-        uint32_t reserved9                            : 4;
-        uint32_t hp_sleep2modem_backup_en             : 1;
-        uint32_t reserved10                           : 2;
-    };
-    struct { /* HP: Sleep State */
-        uint32_t reserved11                           : 6;
-        uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
-        uint32_t hp_active2sleep_backup_modem_clk_code: 2;
-        uint32_t reserved12                           : 6;
-        uint32_t hp_modem2sleep_backup_clk_sel        : 2;
-        uint32_t hp_active2sleep_backup_clk_sel       : 2;
-        uint32_t hp_modem2sleep_backup_mode           : 5;
-        uint32_t hp_active2sleep_backup_mode          : 5;
-        uint32_t hp_modem2sleep_backup_en             : 1;
-        uint32_t hp_active2sleep_backup_en            : 1;
-    };
-    uint32_t val;
-} pmu_hp_backup_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0       : 26;
-        uint32_t dig_sysclk_nodiv: 1;
-        uint32_t icg_sysclk_en   : 1;
-        uint32_t sysclk_slp_sel  : 1;
-        uint32_t icg_slp_sel     : 1;
-        uint32_t dig_sysclk_sel  : 2;
-    };
-    uint32_t val;
-} pmu_hp_sysclk_reg_t;
-
-typedef union {
-    struct {
-        uint32_t power_det_bypass: 1;
-        uint32_t reserved0       : 3;
-        uint32_t lp_dbias_vol    : 5; /* Only HP_ACTIVE mode under hp system is valid */
-        uint32_t hp_dbias_vol    : 5; /* Only HP_ACTIVE mode under hp system is valid */
-        uint32_t dbias_sel       : 1; /* Only HP_ACTIVE mode under hp system is valid */
-        uint32_t dbias_init      : 1; /* Only HP_ACTIVE mode under hp system is valid */
-        uint32_t slp_mem_xpd     : 1;
-        uint32_t slp_logic_xpd   : 1;
-        uint32_t xpd             : 1;
-        uint32_t slp_mem_dbias   : 4;
-        uint32_t slp_logic_dbias : 4;
-        uint32_t dbias           : 5;
-    };
-    uint32_t val;
-} pmu_hp_regulator0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 8;
-        uint32_t drv_b    : 24;
-    };
-    uint32_t val;
-} pmu_hp_regulator1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 30;
-        uint32_t xpd_xtalx2: 1;
-        uint32_t xpd_xtal  : 1;
-    };
-    uint32_t val;
-} pmu_hp_xtal_reg_t;
-
-typedef struct pmu_hp_hw_regmap {
-    pmu_hp_dig_power_reg_t  dig_power;
-    uint32_t                icg_func;
-    uint32_t                icg_apb;
-    pmu_hp_icg_modem_reg_t  icg_modem;
-    pmu_hp_sys_cntl_reg_t   syscntl;
-    pmu_hp_clk_power_reg_t  clk_power;
-    pmu_hp_bias_reg_t       bias;
-    pmu_hp_backup_reg_t     backup;
-    uint32_t                backup_clk;
-    pmu_hp_sysclk_reg_t     sysclk;
-    pmu_hp_regulator0_reg_t regulator0;
-    pmu_hp_regulator1_reg_t regulator1;
-    pmu_hp_xtal_reg_t       xtal;
-} pmu_hp_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 21;
-        uint32_t slp_xpd  : 1;
-        uint32_t xpd      : 1;
-        uint32_t slp_dbias: 4;
-        uint32_t dbias    : 5;
-    };
-    uint32_t val;
-} pmu_lp_regulator0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 28;
-        uint32_t drv_b    : 4;
-    };
-    uint32_t val;
-} pmu_lp_regulator1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 30;
-        uint32_t xpd_xtalx2: 1;
-        uint32_t xpd_xtal  : 1;
-    };
-    uint32_t val;
-} pmu_lp_xtal_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0     : 23;
-        uint32_t vdd_io_mode   : 4;
-        uint32_t bod_source_sel: 1;
-        uint32_t vddbat_mode   : 2;
-        uint32_t mem_dslp      : 1;
-        uint32_t peri_pd_en    : 1;
-    };
-    uint32_t val;
-} pmu_lp_dig_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0  : 27;
-        uint32_t xpd_lppll  : 1;
-        uint32_t xpd_xtal32k: 1;
-        uint32_t xpd_rc32k  : 1;
-        uint32_t xpd_fosc   : 1;
-        uint32_t pd_osc     : 1;
-    };
-    uint32_t val;
-} pmu_lp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0         : 9;
-        uint32_t dcdc_ccm_enb      : 1;
-        uint32_t dcdc_clear_rdy    : 1;
-        uint32_t dig_reg_dpcur_bias: 2;
-        uint32_t dig_reg_dsfmos    : 4;
-        uint32_t dcm_vset          : 5;
-        uint32_t dcm_mode          : 2;
-        uint32_t reserved1         : 1;
-        uint32_t xpd_bias          : 1;
-        uint32_t reserved2         : 3;
-        uint32_t discnnt_dig_rtc   : 1;
-        uint32_t pd_cur            : 1;
-        uint32_t bias_sleep        : 1;
-    };
-    uint32_t val;
-} pmu_lp_bias_reg_t;
-
-typedef struct pmu_lp_hw_regmap {
-    pmu_lp_regulator0_reg_t regulator0;
-    pmu_lp_regulator1_reg_t regulator1;
-    pmu_lp_xtal_reg_t       xtal;       /* Only LP_SLEEP mode under lp system, xtal is valid */
-    pmu_lp_dig_power_reg_t  dig_power;
-    pmu_lp_clk_power_reg_t  clk_power;
-    pmu_lp_bias_reg_t       bias;       /* Only LP_SLEEP mode under lp system, bias is valid */
-} pmu_lp_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t tie_low_global_bbpll_icg  : 1;
-        uint32_t tie_low_global_xtal_icg   : 1;
-        uint32_t tie_low_i2c_retention     : 1;
-        uint32_t tie_low_xpd_bb_i2c        : 1;
-        uint32_t tie_low_xpd_bbpll_i2c     : 1;
-        uint32_t tie_low_xpd_bbpll         : 1;
-        uint32_t tie_low_xpd_xtal          : 1;
-        uint32_t tie_low_global_xtalx2_icg : 1;
-        uint32_t tie_low_xpd_xtalx2        : 1;
-        uint32_t reserved0                 : 14;
-        uint32_t tie_high_xtalx2           : 1;
-        uint32_t tie_high_global_xtalx2_icg: 1;
-        uint32_t tie_high_global_bbpll_icg : 1;
-        uint32_t tie_high_global_xtal_icg  : 1;
-        uint32_t tie_high_i2c_retention    : 1;
-        uint32_t tie_high_xpd_bb_i2c       : 1;
-        uint32_t tie_high_xpd_bbpll_i2c    : 1;
-        uint32_t tie_high_xpd_bbpll        : 1;
-        uint32_t tie_high_xpd_xtal         : 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0            : 28;
-        uint32_t update_dig_icg_switch: 1;
-        uint32_t tie_low_icg_slp_sel  : 1;
-        uint32_t tie_high_icg_slp_sel : 1;
-        uint32_t update_dig_sysclk_sel: 1;
-    };
-    uint32_t val;
-} pmu_imm_sleep_sysclk_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0             : 31;
-        uint32_t update_dig_icg_func_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_func_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0            : 31;
-        uint32_t update_dig_icg_apb_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_apb_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0              : 31;
-        uint32_t update_dig_icg_modem_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_modem_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0              : 30;
-        uint32_t tie_low_lp_rootclk_sel : 1;
-        uint32_t tie_high_lp_rootclk_sel: 1;
-    };
-    uint32_t val;
-} pmu_imm_lp_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0               : 26;
-        uint32_t tie_high_dig_pad_slp_sel: 1;
-        uint32_t tie_low_dig_pad_slp_sel : 1;
-        uint32_t tie_high_lp_pad_hold_all: 1;
-        uint32_t tie_low_lp_pad_hold_all : 1;
-        uint32_t tie_high_hp_pad_hold_all: 1;
-        uint32_t tie_low_hp_pad_hold_all : 1;
-    };
-    uint32_t val;
-} pmu_imm_pad_hold_all_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 30;
-        uint32_t tie_high_i2c_iso_en: 1;
-        uint32_t tie_low_i2c_iso_en : 1;
-    };
-    uint32_t val;
-} pmu_imm_i2c_isolate_reg_t;
-
-typedef struct pmu_imm_hw_regmap {
-    pmu_imm_hp_clk_power_reg_t  clk_power;
-    pmu_imm_sleep_sysclk_reg_t  sleep_sysclk;
-    pmu_imm_hp_func_icg_reg_t   hp_func_icg;
-    pmu_imm_hp_apb_icg_reg_t    hp_apb_icg;
-    pmu_imm_modem_icg_reg_t     modem_icg;
-    pmu_imm_lp_icg_reg_t        lp_icg;
-    pmu_imm_pad_hold_all_reg_t  pad_hold_all;
-    pmu_imm_i2c_isolate_reg_t   i2c_iso;
-} pmu_imm_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0         : 5;
-        uint32_t hp_powerdown_timer: 9;
-        uint32_t hp_powerup_timer  : 9;
-        uint32_t hp_wait_timer     : 9;
-    };
-    uint32_t val;
-} pmu_power_wait_timer0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0         : 9;
-        uint32_t lp_powerdown_timer: 7;
-        uint32_t lp_powerup_timer  : 7;
-        uint32_t lp_wait_timer     : 9;
-    };
-    uint32_t val;
-} pmu_power_wait_timer1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t lp_iso_wait_timer: 8;
-        uint32_t lp_rst_wait_timer: 8;
-        uint32_t hp_iso_wait_timer: 8;
-        uint32_t hp_rst_wait_timer: 8;
-    };
-    uint32_t val;
-} pmu_power_wait_timer2_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_reset   : 1;
-        uint32_t force_iso     : 1;
-        uint32_t force_pu      : 1;
-        uint32_t force_no_reset: 1;
-        uint32_t force_no_iso  : 1;
-        uint32_t force_pd      : 1;
-        uint32_t mask          : 5;  /* Invalid of lp peripherals */
-        uint32_t reserved0     : 16; /* Invalid of lp peripherals */
-        uint32_t pd_mask       : 5;  /* Invalid of lp peripherals */
-    };
-    uint32_t val;
-} pmu_power_domain_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_hp_mem_iso   : 4;
-        uint32_t force_hp_mem_pd    : 4;
-        uint32_t reserved0          : 16;
-        uint32_t force_hp_mem_no_iso: 4;
-        uint32_t force_hp_mem_pu    : 4;
-    };
-    uint32_t val;
-} pmu_power_memory_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t mem2_pd_mask : 5;
-        uint32_t mem1_pd_mask : 5;
-        uint32_t mem0_pd_mask : 5;
-        uint32_t reserved0 : 2;
-        uint32_t mem2_mask : 5;
-        uint32_t mem1_mask : 5;
-        uint32_t mem0_mask : 5;
-    };
-    uint32_t val;
-} pmu_power_memory_mask_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_hp_pad_no_iso_all: 1;
-        uint32_t force_hp_pad_iso_all   : 1;
-        uint32_t reserved0              : 30;
-    };
-    uint32_t val;
-} pmu_power_hp_pad_reg_t;
-
-typedef union {
-    struct {
-        uint32_t ldo_rdy           : 1;
-        uint32_t sw_en_xpd         : 1;
-        uint32_t sw_en_thru        : 1;
-        uint32_t sw_en_standby     : 1;
-        uint32_t sw_en_power_adjust: 1;
-        uint32_t sw_en_endet       : 1;
-        uint32_t reserved0         : 16;
-        uint32_t bypass_ldo_rdy    : 1;
-        uint32_t xpd               : 1;
-        uint32_t thru              : 1;
-        uint32_t standby           : 1;
-        uint32_t power_adjust      : 4;
-        uint32_t reserved1         : 1;
-        uint32_t endet             : 1;
-    };
-    uint32_t val;
-} pmu_power_flash_ldo_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 22;
-        uint32_t ldo_sw_en_tiel     : 1;
-        uint32_t ldo_power_sel      : 1;
-        uint32_t ldo_sw_en_power_sel: 1;
-        uint32_t ldo_wait_target    : 4;
-        uint32_t ldo_tiel_en        : 1;
-        uint32_t ldo_tiel           : 1;
-        uint32_t ldo_sw_update      : 1;
-    };
-    uint32_t val;
-} pmu_power_vdd_flash_reg_t;
-
-typedef union {
-    struct {
-        uint32_t ldo_rdy           : 1;
-        uint32_t sw_en_xpd         : 1;
-        uint32_t reserved0         : 1;
-        uint32_t sw_en_thru        : 1;
-        uint32_t sw_en_standby     : 1;
-        uint32_t sw_en_power_adjust: 1;
-        uint32_t sw_en_endet       : 1;
-        uint32_t reserved1         : 15;
-        uint32_t bypass_ldo_rdy    : 1;
-        uint32_t xpd               : 1;
-        uint32_t thru              : 1;
-        uint32_t standby           : 1;
-        uint32_t power_adjust      : 4;
-        uint32_t reserved2         : 1;
-        uint32_t endet             : 1;
-    };
-    uint32_t val;
-} pmu_power_io_ldo_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 23;
-        uint32_t ldo_power_sel      : 1;
-        uint32_t ldo_sw_en_power_sel: 1;
-        uint32_t reserved1          : 7;
-    };
-    uint32_t val;
-} pmu_power_vdd_io_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wait_xtal_stable: 16;
-        uint32_t wait_pll_stable : 16;
-    };
-    uint32_t val;
-} pmu_power_clk_wait_cntl_reg_t;
-
-typedef struct pmu_power_hw_regmap {
-    pmu_power_wait_timer0_reg_t     wait_timer0;
-    pmu_power_wait_timer1_reg_t     wait_timer1;
-    pmu_power_wait_timer2_reg_t     wait_timer2;
-    pmu_power_domain_cntl_reg_t     hp_pd[5];     /* Include TOP, HPAON, HPCPU, HPPERI and MODEM power domain */
-    pmu_power_domain_cntl_reg_t     lp_peri;
-    pmu_power_memory_cntl_reg_t     mem_cntl;
-    pmu_power_memory_mask_reg_t     mem_mask;
-    pmu_power_hp_pad_reg_t          hp_pad;
-    pmu_power_flash_ldo_reg_t       flash_ldo[2]; /* Include Flash 1p8 and 1p2 LDO */
-    pmu_power_vdd_flash_reg_t       vdd_flash;
-    pmu_power_io_ldo_reg_t          io_ldo;
-    pmu_power_vdd_io_reg_t          vdd_io;
-    pmu_power_clk_wait_cntl_reg_t   clk_wait;
-} pmu_power_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t sleep_req: 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t sleep_reject_ena: 31;
-        uint32_t slp_reject_en   : 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t lp_min_slp_val: 8;
-        uint32_t hp_min_slp_val: 8;
-        uint32_t sleep_prt_sel : 2;
-        uint32_t reserved0     : 14;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl3_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0           : 31;
-        uint32_t slp_reject_cause_clr: 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl4_reg_t;
-
-typedef union {
-    struct {
-        uint32_t modem_wait_target : 20;
-        uint32_t reserved0         : 4;
-        uint32_t lp_ana_wait_target: 8;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl5_reg_t;
-
-typedef union {
-    struct {
-        uint32_t soc_wakeup_wait    : 20;
-        uint32_t reserved0          : 10;
-        uint32_t soc_wakeup_wait_cfg: 2;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl6_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0       : 15;
-        uint32_t ana_wait_clk_sel: 1;
-        uint32_t ana_wait_target : 16;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl7_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wakeup_cause: 32;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_status0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reject_cause: 32;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_status1_reg_t;
-
-typedef struct pmu_wakeup_hw_regmap {
-    pmu_slp_wakeup_cntl0_reg_t      cntl0;
-    pmu_slp_wakeup_cntl1_reg_t      cntl1;
-    uint32_t                        cntl2;
-    pmu_slp_wakeup_cntl3_reg_t      cntl3;
-    pmu_slp_wakeup_cntl4_reg_t      cntl4;
-    pmu_slp_wakeup_cntl5_reg_t      cntl5;
-    pmu_slp_wakeup_cntl6_reg_t      cntl6;
-    pmu_slp_wakeup_cntl7_reg_t      cntl7;
-    pmu_slp_wakeup_status0_reg_t    status0;
-    pmu_slp_wakeup_status1_reg_t    status1;
-} pmu_wakeup_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t i2c_por_wait_target: 8;
-        uint32_t reserved0          : 24;
-    };
-    uint32_t val;
-} pmu_hp_clk_poweron_reg_t;
-
-typedef union {
-    struct {
-        uint32_t modify_icg_cntl_wait: 8;
-        uint32_t switch_icg_cntl_wait: 8;
-        uint32_t reserved0           : 16;
-    };
-    uint32_t val;
-} pmu_hp_clk_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t por_done : 1;
-    };
-    uint32_t val;
-} pmu_por_status_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 26;
-        uint32_t xpd_force_rftx : 1;
-        uint32_t xpd_perif_i2c  : 1;
-        uint32_t xpd_rftx_i2c   : 1;
-        uint32_t xpd_rfrx_i2c   : 1;
-        uint32_t xpd_rfpll      : 1;
-        uint32_t xpd_force_rfpll: 1;
-    };
-    uint32_t val;
-} pmu_rf_pwc_reg_t;
-
-typedef union {
-    struct {
-        uint32_t vddbat_mode     : 2;
-        uint32_t reserved0       : 29;
-        uint32_t vddbat_sw_update: 1;
-    };
-    uint32_t val;
-} pmu_vddbat_cfg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 31;
-        uint32_t backup_sysclk_nodiv: 1;
-    };
-    uint32_t val;
-} pmu_backup_cfg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0       : 27;
-        uint32_t lp_cpu_exc      : 1;
-        uint32_t sdio_idle       : 1;
-        uint32_t sw              : 1;
-        uint32_t soc_sleep_reject: 1;
-        uint32_t soc_wakeup      : 1;
-    };
-    uint32_t val;
-} pmu_hp_intr_reg_t;
-
-typedef struct pmu_hp_ext_hw_regmap {
-    pmu_hp_clk_poweron_reg_t    clk_poweron;
-    pmu_hp_clk_cntl_reg_t       clk_cntl;
-    pmu_por_status_reg_t        por_status;
-    pmu_rf_pwc_reg_t            rf_pwc;
-    pmu_vddbat_cfg_reg_t        vddbat_cfg;
-    pmu_backup_cfg_reg_t        backup_cfg;
-    pmu_hp_intr_reg_t           int_raw;
-    pmu_hp_intr_reg_t           int_st;
-    pmu_hp_intr_reg_t           int_ena;
-    pmu_hp_intr_reg_t           int_clr;
-} pmu_hp_ext_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0                : 20;
-        uint32_t lp_cpu_wakeup            : 1;
-        uint32_t modem_switch_active_end  : 1;
-        uint32_t sleep_switch_active_end  : 1;
-        uint32_t sleep_switch_modem_end   : 1;
-        uint32_t modem_switch_sleep_end   : 1;
-        uint32_t active_switch_sleep_end  : 1;
-        uint32_t modem_switch_active_start: 1;
-        uint32_t sleep_switch_active_start: 1;
-        uint32_t sleep_switch_modem_start : 1;
-        uint32_t modem_switch_sleep_start : 1;
-        uint32_t active_switch_sleep_start: 1;
-        uint32_t hp_sw_trigger            : 1;
-    };
-    uint32_t val;
-} pmu_lp_intr_reg_t;
-
-typedef union {
-    struct {
-        uint32_t waiti_rdy         : 1;
-        uint32_t stall_rdy         : 1;
-        uint32_t reserved0         : 16;
-        uint32_t force_stall       : 1;
-        uint32_t slp_waiti_flag_en : 1;
-        uint32_t slp_stall_flag_en : 1;
-        uint32_t slp_stall_wait    : 8;
-        uint32_t slp_stall_en      : 1;
-        uint32_t slp_reset_en      : 1;
-        uint32_t slp_bypass_intr_en: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wakeup_en: 16;
-        uint32_t reserved0: 15;
-        uint32_t sleep_req: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr1_reg_t;
-
-typedef struct pmu_lp_ext_hw_regmap {
-    pmu_lp_intr_reg_t       int_raw;
-    pmu_lp_intr_reg_t       int_st;
-    pmu_lp_intr_reg_t       int_ena;
-    pmu_lp_intr_reg_t       int_clr;
-    pmu_lp_cpu_pwr0_reg_t   pwr0;
-    pmu_lp_cpu_pwr1_reg_t   pwr1;
-} pmu_lp_ext_hw_regmap_t;
-
-
-typedef union {
-    struct {
-        uint32_t reserved0    : 30;
-        uint32_t lp_trigger_hp: 1;
-        uint32_t hp_trigger_lp: 1;
-    };
-    uint32_t val;
-} pmu_hp_lp_cpu_comm_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0           : 31;
-        uint32_t dig_regulator_en_cal: 1;
-    };
-    uint32_t val;
-} pmu_hp_regulator_cfg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0         : 11;
-        uint32_t main_last_st_state: 7;
-        uint32_t main_tar_st_state : 7;
-        uint32_t main_cur_st_state : 7;
-    };
-    uint32_t val;
-} pmu_main_state_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 13;
-        uint32_t backup_st_state: 5;
-        uint32_t lp_pwr_st_state: 5;
-        uint32_t hp_pwr_st_state: 9;
-    };
-    uint32_t val;
-} pmu_pwr_state_reg_t;
-
-typedef union {
-    struct {
-        uint32_t stable_xpd_bbpll_state : 1;
-        uint32_t stable_xpd_xtal_state  : 1;
-        uint32_t reserved0              : 13;
-        uint32_t sysclk_slp_sel_state   : 1;
-        uint32_t sysclk_sel_state       : 2;
-        uint32_t sysclk_nodiv_state     : 1;
-        uint32_t icg_sysclk_en_state    : 1;
-        uint32_t icg_modem_switch_state : 1;
-        uint32_t icg_modem_code_state   : 2;
-        uint32_t icg_slp_sel_state      : 1;
-        uint32_t icg_global_xtal_state  : 1;
-        uint32_t icg_global_pll_state   : 1;
-        uint32_t ana_i2c_iso_en_state   : 1;
-        uint32_t ana_i2c_retention_state: 1;
-        uint32_t ana_xpd_bb_i2c_state   : 1;
-        uint32_t ana_xpd_bbpll_i2c_state: 1;
-        uint32_t ana_xpd_bbpll_state    : 1;
-        uint32_t ana_xpd_xtal_state     : 1;
-    };
-    uint32_t val;
-} pmu_clk_state0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t icg_func_en_state: 32;
-    };
-    uint32_t val;
-} pmu_clk_state1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t icg_apb_en_state: 32;
-    };
-    uint32_t val;
-} pmu_clk_state2_reg_t;
-
-typedef union {
-    struct {
-        uint32_t dsfmos_use_por    : 1;
-        uint32_t reserved0         : 21;
-        uint32_t dcdc_dcm_update   : 1;
-        uint32_t dcdc_pcur_limit   : 3;
-        uint32_t dcdc_bias_cal_done: 1;
-        uint32_t dcdc_ccm_sw_en    : 1;
-        uint32_t dcdc_vcm_enb      : 1;
-        uint32_t dcdc_ccm_rdy      : 1;
-        uint32_t dcdc_vcm_rdy      : 1;
-        uint32_t dcdc_rdy_clr      : 1;
-    };
-    uint32_t val;
-} pmu_dcm_ctrl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0            : 24;
-        uint32_t dcdc_boost_ccm_ctrlen: 1;
-        uint32_t dcdc_boost_ccm_enb   : 1;
-        uint32_t dcdc_boost_en        : 1;
-        uint32_t dcdc_boost_dreg      : 5;
-    };
-    uint32_t val;
-} pmu_dcm_boost_ctrl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t touch_sleep_cycles  : 16;
-        uint32_t reserved0           : 5;
-        uint32_t touch_wait_cycles   : 9;
-        uint32_t touch_sleep_timer_en: 1;
-        uint32_t touch_force_done    : 1;
-    };
-    uint32_t val;
-} pmu_touch_pwr_ctrl_reg_t;
-
-typedef struct pmu_dev {
-    volatile pmu_hp_hw_regmap_t         hp_sys[3];
-    volatile pmu_lp_hw_regmap_t         lp_sys[2];
-    volatile pmu_imm_hw_regmap_t        imm;
-    volatile pmu_power_hw_regmap_t      power;
-    volatile pmu_wakeup_hw_regmap_t     wakeup;
-    volatile pmu_hp_ext_hw_regmap_t     hp_ext;
-    volatile pmu_lp_ext_hw_regmap_t     lp_ext;
-
-    volatile pmu_hp_lp_cpu_comm_reg_t   hp_lp_cpu_common;
-    volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg;
-
-    volatile pmu_main_state_reg_t       main_state;
-    volatile pmu_pwr_state_reg_t        pwr_state;
-    volatile pmu_clk_state0_reg_t       clk_state0;
-    volatile pmu_clk_state1_reg_t       clk_state1;
-    volatile pmu_clk_state2_reg_t       clk_state2;
-
-    volatile pmu_dcm_ctrl_reg_t         dcm_ctrl;
-    volatile pmu_dcm_boost_ctrl_reg_t   dcm_boost_ctrl;
-    volatile pmu_touch_pwr_ctrl_reg_t   touch_pwr_ctrl;
-
-    uint32_t reserved[142];
-
-    union {
-        struct {
-            uint32_t pmu_date: 31;
-            uint32_t clk_en  : 1;
-        };
-        uint32_t val;
-    } date;
-} pmu_dev_t;
-
-extern pmu_dev_t PMU;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
-
-_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_TOUCH_PWR_CTRL_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h4/register/hw_ver_beta5/soc/tee_reg.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/tee_reg.h
deleted file mode 100644
index 874299912b..0000000000
--- a/components/soc/esp32h4/register/hw_ver_beta5/soc/tee_reg.h
+++ /dev/null
@@ -1,4488 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0 OR MIT
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** TEE_M0_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0)
-/** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M0 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M0_MODE    0x00000003U
-#define TEE_M0_MODE_M  (TEE_M0_MODE_V << TEE_M0_MODE_S)
-#define TEE_M0_MODE_V  0x00000003U
-#define TEE_M0_MODE_S  0
-/** TEE_M0_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M0_LOCK    (BIT(2))
-#define TEE_M0_LOCK_M  (TEE_M0_LOCK_V << TEE_M0_LOCK_S)
-#define TEE_M0_LOCK_V  0x00000001U
-#define TEE_M0_LOCK_S  2
-
-/** TEE_M1_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4)
-/** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M1 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M1_MODE    0x00000003U
-#define TEE_M1_MODE_M  (TEE_M1_MODE_V << TEE_M1_MODE_S)
-#define TEE_M1_MODE_V  0x00000003U
-#define TEE_M1_MODE_S  0
-/** TEE_M1_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M1_LOCK    (BIT(2))
-#define TEE_M1_LOCK_M  (TEE_M1_LOCK_V << TEE_M1_LOCK_S)
-#define TEE_M1_LOCK_V  0x00000001U
-#define TEE_M1_LOCK_S  2
-
-/** TEE_M2_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8)
-/** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M2 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M2_MODE    0x00000003U
-#define TEE_M2_MODE_M  (TEE_M2_MODE_V << TEE_M2_MODE_S)
-#define TEE_M2_MODE_V  0x00000003U
-#define TEE_M2_MODE_S  0
-/** TEE_M2_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M2_LOCK    (BIT(2))
-#define TEE_M2_LOCK_M  (TEE_M2_LOCK_V << TEE_M2_LOCK_S)
-#define TEE_M2_LOCK_V  0x00000001U
-#define TEE_M2_LOCK_S  2
-
-/** TEE_M3_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc)
-/** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M3 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M3_MODE    0x00000003U
-#define TEE_M3_MODE_M  (TEE_M3_MODE_V << TEE_M3_MODE_S)
-#define TEE_M3_MODE_V  0x00000003U
-#define TEE_M3_MODE_S  0
-/** TEE_M3_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M3_LOCK    (BIT(2))
-#define TEE_M3_LOCK_M  (TEE_M3_LOCK_V << TEE_M3_LOCK_S)
-#define TEE_M3_LOCK_V  0x00000001U
-#define TEE_M3_LOCK_S  2
-
-/** TEE_M4_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10)
-/** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M4 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M4_MODE    0x00000003U
-#define TEE_M4_MODE_M  (TEE_M4_MODE_V << TEE_M4_MODE_S)
-#define TEE_M4_MODE_V  0x00000003U
-#define TEE_M4_MODE_S  0
-/** TEE_M4_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M4_LOCK    (BIT(2))
-#define TEE_M4_LOCK_M  (TEE_M4_LOCK_V << TEE_M4_LOCK_S)
-#define TEE_M4_LOCK_V  0x00000001U
-#define TEE_M4_LOCK_S  2
-
-/** TEE_M5_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14)
-/** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M5 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M5_MODE    0x00000003U
-#define TEE_M5_MODE_M  (TEE_M5_MODE_V << TEE_M5_MODE_S)
-#define TEE_M5_MODE_V  0x00000003U
-#define TEE_M5_MODE_S  0
-/** TEE_M5_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M5_LOCK    (BIT(2))
-#define TEE_M5_LOCK_M  (TEE_M5_LOCK_V << TEE_M5_LOCK_S)
-#define TEE_M5_LOCK_V  0x00000001U
-#define TEE_M5_LOCK_S  2
-
-/** TEE_M6_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18)
-/** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M6 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M6_MODE    0x00000003U
-#define TEE_M6_MODE_M  (TEE_M6_MODE_V << TEE_M6_MODE_S)
-#define TEE_M6_MODE_V  0x00000003U
-#define TEE_M6_MODE_S  0
-/** TEE_M6_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M6_LOCK    (BIT(2))
-#define TEE_M6_LOCK_M  (TEE_M6_LOCK_V << TEE_M6_LOCK_S)
-#define TEE_M6_LOCK_V  0x00000001U
-#define TEE_M6_LOCK_S  2
-
-/** TEE_M7_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c)
-/** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M7 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M7_MODE    0x00000003U
-#define TEE_M7_MODE_M  (TEE_M7_MODE_V << TEE_M7_MODE_S)
-#define TEE_M7_MODE_V  0x00000003U
-#define TEE_M7_MODE_S  0
-/** TEE_M7_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M7_LOCK    (BIT(2))
-#define TEE_M7_LOCK_M  (TEE_M7_LOCK_V << TEE_M7_LOCK_S)
-#define TEE_M7_LOCK_V  0x00000001U
-#define TEE_M7_LOCK_S  2
-
-/** TEE_M8_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20)
-/** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M8 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M8_MODE    0x00000003U
-#define TEE_M8_MODE_M  (TEE_M8_MODE_V << TEE_M8_MODE_S)
-#define TEE_M8_MODE_V  0x00000003U
-#define TEE_M8_MODE_S  0
-/** TEE_M8_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M8_LOCK    (BIT(2))
-#define TEE_M8_LOCK_M  (TEE_M8_LOCK_V << TEE_M8_LOCK_S)
-#define TEE_M8_LOCK_V  0x00000001U
-#define TEE_M8_LOCK_S  2
-
-/** TEE_M9_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24)
-/** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M9 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M9_MODE    0x00000003U
-#define TEE_M9_MODE_M  (TEE_M9_MODE_V << TEE_M9_MODE_S)
-#define TEE_M9_MODE_V  0x00000003U
-#define TEE_M9_MODE_S  0
-/** TEE_M9_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M9_LOCK    (BIT(2))
-#define TEE_M9_LOCK_M  (TEE_M9_LOCK_V << TEE_M9_LOCK_S)
-#define TEE_M9_LOCK_V  0x00000001U
-#define TEE_M9_LOCK_S  2
-
-/** TEE_M10_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28)
-/** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M10 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M10_MODE    0x00000003U
-#define TEE_M10_MODE_M  (TEE_M10_MODE_V << TEE_M10_MODE_S)
-#define TEE_M10_MODE_V  0x00000003U
-#define TEE_M10_MODE_S  0
-/** TEE_M10_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M10_LOCK    (BIT(2))
-#define TEE_M10_LOCK_M  (TEE_M10_LOCK_V << TEE_M10_LOCK_S)
-#define TEE_M10_LOCK_V  0x00000001U
-#define TEE_M10_LOCK_S  2
-
-/** TEE_M11_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c)
-/** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M11 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M11_MODE    0x00000003U
-#define TEE_M11_MODE_M  (TEE_M11_MODE_V << TEE_M11_MODE_S)
-#define TEE_M11_MODE_V  0x00000003U
-#define TEE_M11_MODE_S  0
-/** TEE_M11_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M11_LOCK    (BIT(2))
-#define TEE_M11_LOCK_M  (TEE_M11_LOCK_V << TEE_M11_LOCK_S)
-#define TEE_M11_LOCK_V  0x00000001U
-#define TEE_M11_LOCK_S  2
-
-/** TEE_M12_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30)
-/** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M12 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M12_MODE    0x00000003U
-#define TEE_M12_MODE_M  (TEE_M12_MODE_V << TEE_M12_MODE_S)
-#define TEE_M12_MODE_V  0x00000003U
-#define TEE_M12_MODE_S  0
-/** TEE_M12_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M12_LOCK    (BIT(2))
-#define TEE_M12_LOCK_M  (TEE_M12_LOCK_V << TEE_M12_LOCK_S)
-#define TEE_M12_LOCK_V  0x00000001U
-#define TEE_M12_LOCK_S  2
-
-/** TEE_M13_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34)
-/** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M13 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M13_MODE    0x00000003U
-#define TEE_M13_MODE_M  (TEE_M13_MODE_V << TEE_M13_MODE_S)
-#define TEE_M13_MODE_V  0x00000003U
-#define TEE_M13_MODE_S  0
-/** TEE_M13_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M13_LOCK    (BIT(2))
-#define TEE_M13_LOCK_M  (TEE_M13_LOCK_V << TEE_M13_LOCK_S)
-#define TEE_M13_LOCK_V  0x00000001U
-#define TEE_M13_LOCK_S  2
-
-/** TEE_M14_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38)
-/** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M14 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M14_MODE    0x00000003U
-#define TEE_M14_MODE_M  (TEE_M14_MODE_V << TEE_M14_MODE_S)
-#define TEE_M14_MODE_V  0x00000003U
-#define TEE_M14_MODE_S  0
-/** TEE_M14_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M14_LOCK    (BIT(2))
-#define TEE_M14_LOCK_M  (TEE_M14_LOCK_V << TEE_M14_LOCK_S)
-#define TEE_M14_LOCK_V  0x00000001U
-#define TEE_M14_LOCK_S  2
-
-/** TEE_M15_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c)
-/** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M15 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M15_MODE    0x00000003U
-#define TEE_M15_MODE_M  (TEE_M15_MODE_V << TEE_M15_MODE_S)
-#define TEE_M15_MODE_V  0x00000003U
-#define TEE_M15_MODE_S  0
-/** TEE_M15_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M15_LOCK    (BIT(2))
-#define TEE_M15_LOCK_M  (TEE_M15_LOCK_V << TEE_M15_LOCK_S)
-#define TEE_M15_LOCK_V  0x00000001U
-#define TEE_M15_LOCK_S  2
-
-/** TEE_M16_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40)
-/** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M16 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M16_MODE    0x00000003U
-#define TEE_M16_MODE_M  (TEE_M16_MODE_V << TEE_M16_MODE_S)
-#define TEE_M16_MODE_V  0x00000003U
-#define TEE_M16_MODE_S  0
-/** TEE_M16_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M16_LOCK    (BIT(2))
-#define TEE_M16_LOCK_M  (TEE_M16_LOCK_V << TEE_M16_LOCK_S)
-#define TEE_M16_LOCK_V  0x00000001U
-#define TEE_M16_LOCK_S  2
-
-/** TEE_M17_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44)
-/** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M17 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M17_MODE    0x00000003U
-#define TEE_M17_MODE_M  (TEE_M17_MODE_V << TEE_M17_MODE_S)
-#define TEE_M17_MODE_V  0x00000003U
-#define TEE_M17_MODE_S  0
-/** TEE_M17_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M17_LOCK    (BIT(2))
-#define TEE_M17_LOCK_M  (TEE_M17_LOCK_V << TEE_M17_LOCK_S)
-#define TEE_M17_LOCK_V  0x00000001U
-#define TEE_M17_LOCK_S  2
-
-/** TEE_M18_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48)
-/** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M18 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M18_MODE    0x00000003U
-#define TEE_M18_MODE_M  (TEE_M18_MODE_V << TEE_M18_MODE_S)
-#define TEE_M18_MODE_V  0x00000003U
-#define TEE_M18_MODE_S  0
-/** TEE_M18_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M18_LOCK    (BIT(2))
-#define TEE_M18_LOCK_M  (TEE_M18_LOCK_V << TEE_M18_LOCK_S)
-#define TEE_M18_LOCK_V  0x00000001U
-#define TEE_M18_LOCK_S  2
-
-/** TEE_M19_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c)
-/** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M19 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M19_MODE    0x00000003U
-#define TEE_M19_MODE_M  (TEE_M19_MODE_V << TEE_M19_MODE_S)
-#define TEE_M19_MODE_V  0x00000003U
-#define TEE_M19_MODE_S  0
-/** TEE_M19_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M19_LOCK    (BIT(2))
-#define TEE_M19_LOCK_M  (TEE_M19_LOCK_V << TEE_M19_LOCK_S)
-#define TEE_M19_LOCK_V  0x00000001U
-#define TEE_M19_LOCK_S  2
-
-/** TEE_M20_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50)
-/** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M20 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M20_MODE    0x00000003U
-#define TEE_M20_MODE_M  (TEE_M20_MODE_V << TEE_M20_MODE_S)
-#define TEE_M20_MODE_V  0x00000003U
-#define TEE_M20_MODE_S  0
-/** TEE_M20_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M20_LOCK    (BIT(2))
-#define TEE_M20_LOCK_M  (TEE_M20_LOCK_V << TEE_M20_LOCK_S)
-#define TEE_M20_LOCK_V  0x00000001U
-#define TEE_M20_LOCK_S  2
-
-/** TEE_M21_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54)
-/** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M21 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M21_MODE    0x00000003U
-#define TEE_M21_MODE_M  (TEE_M21_MODE_V << TEE_M21_MODE_S)
-#define TEE_M21_MODE_V  0x00000003U
-#define TEE_M21_MODE_S  0
-/** TEE_M21_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M21_LOCK    (BIT(2))
-#define TEE_M21_LOCK_M  (TEE_M21_LOCK_V << TEE_M21_LOCK_S)
-#define TEE_M21_LOCK_V  0x00000001U
-#define TEE_M21_LOCK_S  2
-
-/** TEE_M22_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58)
-/** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M22 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M22_MODE    0x00000003U
-#define TEE_M22_MODE_M  (TEE_M22_MODE_V << TEE_M22_MODE_S)
-#define TEE_M22_MODE_V  0x00000003U
-#define TEE_M22_MODE_S  0
-/** TEE_M22_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M22_LOCK    (BIT(2))
-#define TEE_M22_LOCK_M  (TEE_M22_LOCK_V << TEE_M22_LOCK_S)
-#define TEE_M22_LOCK_V  0x00000001U
-#define TEE_M22_LOCK_S  2
-
-/** TEE_M23_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c)
-/** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M23 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M23_MODE    0x00000003U
-#define TEE_M23_MODE_M  (TEE_M23_MODE_V << TEE_M23_MODE_S)
-#define TEE_M23_MODE_V  0x00000003U
-#define TEE_M23_MODE_S  0
-/** TEE_M23_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M23_LOCK    (BIT(2))
-#define TEE_M23_LOCK_M  (TEE_M23_LOCK_V << TEE_M23_LOCK_S)
-#define TEE_M23_LOCK_V  0x00000001U
-#define TEE_M23_LOCK_S  2
-
-/** TEE_M24_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60)
-/** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M24 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M24_MODE    0x00000003U
-#define TEE_M24_MODE_M  (TEE_M24_MODE_V << TEE_M24_MODE_S)
-#define TEE_M24_MODE_V  0x00000003U
-#define TEE_M24_MODE_S  0
-/** TEE_M24_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M24_LOCK    (BIT(2))
-#define TEE_M24_LOCK_M  (TEE_M24_LOCK_V << TEE_M24_LOCK_S)
-#define TEE_M24_LOCK_V  0x00000001U
-#define TEE_M24_LOCK_S  2
-
-/** TEE_M25_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64)
-/** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M25 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M25_MODE    0x00000003U
-#define TEE_M25_MODE_M  (TEE_M25_MODE_V << TEE_M25_MODE_S)
-#define TEE_M25_MODE_V  0x00000003U
-#define TEE_M25_MODE_S  0
-/** TEE_M25_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M25_LOCK    (BIT(2))
-#define TEE_M25_LOCK_M  (TEE_M25_LOCK_V << TEE_M25_LOCK_S)
-#define TEE_M25_LOCK_V  0x00000001U
-#define TEE_M25_LOCK_S  2
-
-/** TEE_M26_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68)
-/** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M26 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M26_MODE    0x00000003U
-#define TEE_M26_MODE_M  (TEE_M26_MODE_V << TEE_M26_MODE_S)
-#define TEE_M26_MODE_V  0x00000003U
-#define TEE_M26_MODE_S  0
-/** TEE_M26_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M26_LOCK    (BIT(2))
-#define TEE_M26_LOCK_M  (TEE_M26_LOCK_V << TEE_M26_LOCK_S)
-#define TEE_M26_LOCK_V  0x00000001U
-#define TEE_M26_LOCK_S  2
-
-/** TEE_M27_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c)
-/** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M27 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M27_MODE    0x00000003U
-#define TEE_M27_MODE_M  (TEE_M27_MODE_V << TEE_M27_MODE_S)
-#define TEE_M27_MODE_V  0x00000003U
-#define TEE_M27_MODE_S  0
-/** TEE_M27_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M27_LOCK    (BIT(2))
-#define TEE_M27_LOCK_M  (TEE_M27_LOCK_V << TEE_M27_LOCK_S)
-#define TEE_M27_LOCK_V  0x00000001U
-#define TEE_M27_LOCK_S  2
-
-/** TEE_M28_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70)
-/** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M28 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M28_MODE    0x00000003U
-#define TEE_M28_MODE_M  (TEE_M28_MODE_V << TEE_M28_MODE_S)
-#define TEE_M28_MODE_V  0x00000003U
-#define TEE_M28_MODE_S  0
-/** TEE_M28_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M28_LOCK    (BIT(2))
-#define TEE_M28_LOCK_M  (TEE_M28_LOCK_V << TEE_M28_LOCK_S)
-#define TEE_M28_LOCK_V  0x00000001U
-#define TEE_M28_LOCK_S  2
-
-/** TEE_M29_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74)
-/** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M29 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M29_MODE    0x00000003U
-#define TEE_M29_MODE_M  (TEE_M29_MODE_V << TEE_M29_MODE_S)
-#define TEE_M29_MODE_V  0x00000003U
-#define TEE_M29_MODE_S  0
-/** TEE_M29_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M29_LOCK    (BIT(2))
-#define TEE_M29_LOCK_M  (TEE_M29_LOCK_V << TEE_M29_LOCK_S)
-#define TEE_M29_LOCK_V  0x00000001U
-#define TEE_M29_LOCK_S  2
-
-/** TEE_M30_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78)
-/** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M30 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M30_MODE    0x00000003U
-#define TEE_M30_MODE_M  (TEE_M30_MODE_V << TEE_M30_MODE_S)
-#define TEE_M30_MODE_V  0x00000003U
-#define TEE_M30_MODE_S  0
-/** TEE_M30_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M30_LOCK    (BIT(2))
-#define TEE_M30_LOCK_M  (TEE_M30_LOCK_V << TEE_M30_LOCK_S)
-#define TEE_M30_LOCK_V  0x00000001U
-#define TEE_M30_LOCK_S  2
-
-/** TEE_M31_MODE_CTRL_REG register
- *  TEE mode control register
- */
-#define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c)
-/** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures M31 security level mode.
- *  0: tee_mode
- *  1: ree_mode0
- *  2: ree_mode1
- *  3: ree_mode2
- */
-#define TEE_M31_MODE    0x00000003U
-#define TEE_M31_MODE_M  (TEE_M31_MODE_V << TEE_M31_MODE_S)
-#define TEE_M31_MODE_V  0x00000003U
-#define TEE_M31_MODE_S  0
-/** TEE_M31_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M31_LOCK    (BIT(2))
-#define TEE_M31_LOCK_M  (TEE_M31_LOCK_V << TEE_M31_LOCK_S)
-#define TEE_M31_LOCK_V  0x00000001U
-#define TEE_M31_LOCK_S  2
-
-/** TEE_GPSPI0_CTRL_REG register
- *  gpspi0 read/write control register
- */
-#define TEE_GPSPI0_CTRL_REG (DR_REG_TEE_BASE + 0x80)
-/** TEE_READ_TEE_GPSPI0 : R/W; bitpos: [0]; default: 1;
- *  Configures gpspi0 registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_GPSPI0    (BIT(0))
-#define TEE_READ_TEE_GPSPI0_M  (TEE_READ_TEE_GPSPI0_V << TEE_READ_TEE_GPSPI0_S)
-#define TEE_READ_TEE_GPSPI0_V  0x00000001U
-#define TEE_READ_TEE_GPSPI0_S  0
-/** TEE_READ_REE0_GPSPI0 : R/W; bitpos: [1]; default: 0;
- *  Configures gpspi0 registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_GPSPI0    (BIT(1))
-#define TEE_READ_REE0_GPSPI0_M  (TEE_READ_REE0_GPSPI0_V << TEE_READ_REE0_GPSPI0_S)
-#define TEE_READ_REE0_GPSPI0_V  0x00000001U
-#define TEE_READ_REE0_GPSPI0_S  1
-/** TEE_READ_REE1_GPSPI0 : R/W; bitpos: [2]; default: 0;
- *  Configures gpspi0 registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_GPSPI0    (BIT(2))
-#define TEE_READ_REE1_GPSPI0_M  (TEE_READ_REE1_GPSPI0_V << TEE_READ_REE1_GPSPI0_S)
-#define TEE_READ_REE1_GPSPI0_V  0x00000001U
-#define TEE_READ_REE1_GPSPI0_S  2
-/** TEE_READ_REE2_GPSPI0 : R/W; bitpos: [3]; default: 0;
- *  Configures gpspi0 registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_GPSPI0    (BIT(3))
-#define TEE_READ_REE2_GPSPI0_M  (TEE_READ_REE2_GPSPI0_V << TEE_READ_REE2_GPSPI0_S)
-#define TEE_READ_REE2_GPSPI0_V  0x00000001U
-#define TEE_READ_REE2_GPSPI0_S  3
-/** TEE_WRITE_TEE_GPSPI0 : R/W; bitpos: [4]; default: 1;
- *  Configures gpspi0 registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_GPSPI0    (BIT(4))
-#define TEE_WRITE_TEE_GPSPI0_M  (TEE_WRITE_TEE_GPSPI0_V << TEE_WRITE_TEE_GPSPI0_S)
-#define TEE_WRITE_TEE_GPSPI0_V  0x00000001U
-#define TEE_WRITE_TEE_GPSPI0_S  4
-/** TEE_WRITE_REE0_GPSPI0 : R/W; bitpos: [5]; default: 0;
- *  Configures gpspi0 registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_GPSPI0    (BIT(5))
-#define TEE_WRITE_REE0_GPSPI0_M  (TEE_WRITE_REE0_GPSPI0_V << TEE_WRITE_REE0_GPSPI0_S)
-#define TEE_WRITE_REE0_GPSPI0_V  0x00000001U
-#define TEE_WRITE_REE0_GPSPI0_S  5
-/** TEE_WRITE_REE1_GPSPI0 : R/W; bitpos: [6]; default: 0;
- *  Configures gpspi0 registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_GPSPI0    (BIT(6))
-#define TEE_WRITE_REE1_GPSPI0_M  (TEE_WRITE_REE1_GPSPI0_V << TEE_WRITE_REE1_GPSPI0_S)
-#define TEE_WRITE_REE1_GPSPI0_V  0x00000001U
-#define TEE_WRITE_REE1_GPSPI0_S  6
-/** TEE_WRITE_REE2_GPSPI0 : R/W; bitpos: [7]; default: 0;
- *  Configures gpspi0 registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_GPSPI0    (BIT(7))
-#define TEE_WRITE_REE2_GPSPI0_M  (TEE_WRITE_REE2_GPSPI0_V << TEE_WRITE_REE2_GPSPI0_S)
-#define TEE_WRITE_REE2_GPSPI0_V  0x00000001U
-#define TEE_WRITE_REE2_GPSPI0_S  7
-
-/** TEE_GPSPI1_CTRL_REG register
- *  gpspi1 read/write control register
- */
-#define TEE_GPSPI1_CTRL_REG (DR_REG_TEE_BASE + 0x84)
-/** TEE_READ_TEE_GPSPI1 : R/W; bitpos: [0]; default: 1;
- *  Configures gpspi1 registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_GPSPI1    (BIT(0))
-#define TEE_READ_TEE_GPSPI1_M  (TEE_READ_TEE_GPSPI1_V << TEE_READ_TEE_GPSPI1_S)
-#define TEE_READ_TEE_GPSPI1_V  0x00000001U
-#define TEE_READ_TEE_GPSPI1_S  0
-/** TEE_READ_REE0_GPSPI1 : R/W; bitpos: [1]; default: 0;
- *  Configures gpspi1 registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_GPSPI1    (BIT(1))
-#define TEE_READ_REE0_GPSPI1_M  (TEE_READ_REE0_GPSPI1_V << TEE_READ_REE0_GPSPI1_S)
-#define TEE_READ_REE0_GPSPI1_V  0x00000001U
-#define TEE_READ_REE0_GPSPI1_S  1
-/** TEE_READ_REE1_GPSPI1 : R/W; bitpos: [2]; default: 0;
- *  Configures gpspi1 registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_GPSPI1    (BIT(2))
-#define TEE_READ_REE1_GPSPI1_M  (TEE_READ_REE1_GPSPI1_V << TEE_READ_REE1_GPSPI1_S)
-#define TEE_READ_REE1_GPSPI1_V  0x00000001U
-#define TEE_READ_REE1_GPSPI1_S  2
-/** TEE_READ_REE2_GPSPI1 : R/W; bitpos: [3]; default: 0;
- *  Configures gpspi1 registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_GPSPI1    (BIT(3))
-#define TEE_READ_REE2_GPSPI1_M  (TEE_READ_REE2_GPSPI1_V << TEE_READ_REE2_GPSPI1_S)
-#define TEE_READ_REE2_GPSPI1_V  0x00000001U
-#define TEE_READ_REE2_GPSPI1_S  3
-/** TEE_WRITE_TEE_GPSPI1 : R/W; bitpos: [4]; default: 1;
- *  Configures gpspi1 registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_GPSPI1    (BIT(4))
-#define TEE_WRITE_TEE_GPSPI1_M  (TEE_WRITE_TEE_GPSPI1_V << TEE_WRITE_TEE_GPSPI1_S)
-#define TEE_WRITE_TEE_GPSPI1_V  0x00000001U
-#define TEE_WRITE_TEE_GPSPI1_S  4
-/** TEE_WRITE_REE0_GPSPI1 : R/W; bitpos: [5]; default: 0;
- *  Configures gpspi1 registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_GPSPI1    (BIT(5))
-#define TEE_WRITE_REE0_GPSPI1_M  (TEE_WRITE_REE0_GPSPI1_V << TEE_WRITE_REE0_GPSPI1_S)
-#define TEE_WRITE_REE0_GPSPI1_V  0x00000001U
-#define TEE_WRITE_REE0_GPSPI1_S  5
-/** TEE_WRITE_REE1_GPSPI1 : R/W; bitpos: [6]; default: 0;
- *  Configures gpspi1 registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_GPSPI1    (BIT(6))
-#define TEE_WRITE_REE1_GPSPI1_M  (TEE_WRITE_REE1_GPSPI1_V << TEE_WRITE_REE1_GPSPI1_S)
-#define TEE_WRITE_REE1_GPSPI1_V  0x00000001U
-#define TEE_WRITE_REE1_GPSPI1_S  6
-/** TEE_WRITE_REE2_GPSPI1 : R/W; bitpos: [7]; default: 0;
- *  Configures gpspi1 registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_GPSPI1    (BIT(7))
-#define TEE_WRITE_REE2_GPSPI1_M  (TEE_WRITE_REE2_GPSPI1_V << TEE_WRITE_REE2_GPSPI1_S)
-#define TEE_WRITE_REE2_GPSPI1_V  0x00000001U
-#define TEE_WRITE_REE2_GPSPI1_S  7
-
-/** TEE_UART0_CTRL_REG register
- *  uart0 read/write control register
- */
-#define TEE_UART0_CTRL_REG (DR_REG_TEE_BASE + 0x88)
-/** TEE_READ_TEE_UART0 : R/W; bitpos: [0]; default: 1;
- *  Configures uart0 registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_UART0    (BIT(0))
-#define TEE_READ_TEE_UART0_M  (TEE_READ_TEE_UART0_V << TEE_READ_TEE_UART0_S)
-#define TEE_READ_TEE_UART0_V  0x00000001U
-#define TEE_READ_TEE_UART0_S  0
-/** TEE_READ_REE0_UART0 : R/W; bitpos: [1]; default: 0;
- *  Configures uart0 registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_UART0    (BIT(1))
-#define TEE_READ_REE0_UART0_M  (TEE_READ_REE0_UART0_V << TEE_READ_REE0_UART0_S)
-#define TEE_READ_REE0_UART0_V  0x00000001U
-#define TEE_READ_REE0_UART0_S  1
-/** TEE_READ_REE1_UART0 : R/W; bitpos: [2]; default: 0;
- *  Configures uart0 registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_UART0    (BIT(2))
-#define TEE_READ_REE1_UART0_M  (TEE_READ_REE1_UART0_V << TEE_READ_REE1_UART0_S)
-#define TEE_READ_REE1_UART0_V  0x00000001U
-#define TEE_READ_REE1_UART0_S  2
-/** TEE_READ_REE2_UART0 : R/W; bitpos: [3]; default: 0;
- *  Configures uart0 registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_UART0    (BIT(3))
-#define TEE_READ_REE2_UART0_M  (TEE_READ_REE2_UART0_V << TEE_READ_REE2_UART0_S)
-#define TEE_READ_REE2_UART0_V  0x00000001U
-#define TEE_READ_REE2_UART0_S  3
-/** TEE_WRITE_TEE_UART0 : R/W; bitpos: [4]; default: 1;
- *  Configures uart0 registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_UART0    (BIT(4))
-#define TEE_WRITE_TEE_UART0_M  (TEE_WRITE_TEE_UART0_V << TEE_WRITE_TEE_UART0_S)
-#define TEE_WRITE_TEE_UART0_V  0x00000001U
-#define TEE_WRITE_TEE_UART0_S  4
-/** TEE_WRITE_REE0_UART0 : R/W; bitpos: [5]; default: 0;
- *  Configures uart0 registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_UART0    (BIT(5))
-#define TEE_WRITE_REE0_UART0_M  (TEE_WRITE_REE0_UART0_V << TEE_WRITE_REE0_UART0_S)
-#define TEE_WRITE_REE0_UART0_V  0x00000001U
-#define TEE_WRITE_REE0_UART0_S  5
-/** TEE_WRITE_REE1_UART0 : R/W; bitpos: [6]; default: 0;
- *  Configures uart0 registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_UART0    (BIT(6))
-#define TEE_WRITE_REE1_UART0_M  (TEE_WRITE_REE1_UART0_V << TEE_WRITE_REE1_UART0_S)
-#define TEE_WRITE_REE1_UART0_V  0x00000001U
-#define TEE_WRITE_REE1_UART0_S  6
-/** TEE_WRITE_REE2_UART0 : R/W; bitpos: [7]; default: 0;
- *  Configures uart0 registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_UART0    (BIT(7))
-#define TEE_WRITE_REE2_UART0_M  (TEE_WRITE_REE2_UART0_V << TEE_WRITE_REE2_UART0_S)
-#define TEE_WRITE_REE2_UART0_V  0x00000001U
-#define TEE_WRITE_REE2_UART0_S  7
-
-/** TEE_UART1_CTRL_REG register
- *  uart1 read/write control register
- */
-#define TEE_UART1_CTRL_REG (DR_REG_TEE_BASE + 0x8c)
-/** TEE_READ_TEE_UART1 : R/W; bitpos: [0]; default: 1;
- *  Configures uart1 registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_UART1    (BIT(0))
-#define TEE_READ_TEE_UART1_M  (TEE_READ_TEE_UART1_V << TEE_READ_TEE_UART1_S)
-#define TEE_READ_TEE_UART1_V  0x00000001U
-#define TEE_READ_TEE_UART1_S  0
-/** TEE_READ_REE0_UART1 : R/W; bitpos: [1]; default: 0;
- *  Configures uart1 registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_UART1    (BIT(1))
-#define TEE_READ_REE0_UART1_M  (TEE_READ_REE0_UART1_V << TEE_READ_REE0_UART1_S)
-#define TEE_READ_REE0_UART1_V  0x00000001U
-#define TEE_READ_REE0_UART1_S  1
-/** TEE_READ_REE1_UART1 : R/W; bitpos: [2]; default: 0;
- *  Configures uart1 registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_UART1    (BIT(2))
-#define TEE_READ_REE1_UART1_M  (TEE_READ_REE1_UART1_V << TEE_READ_REE1_UART1_S)
-#define TEE_READ_REE1_UART1_V  0x00000001U
-#define TEE_READ_REE1_UART1_S  2
-/** TEE_READ_REE2_UART1 : R/W; bitpos: [3]; default: 0;
- *  Configures uart1 registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_UART1    (BIT(3))
-#define TEE_READ_REE2_UART1_M  (TEE_READ_REE2_UART1_V << TEE_READ_REE2_UART1_S)
-#define TEE_READ_REE2_UART1_V  0x00000001U
-#define TEE_READ_REE2_UART1_S  3
-/** TEE_WRITE_TEE_UART1 : R/W; bitpos: [4]; default: 1;
- *  Configures uart1 registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_UART1    (BIT(4))
-#define TEE_WRITE_TEE_UART1_M  (TEE_WRITE_TEE_UART1_V << TEE_WRITE_TEE_UART1_S)
-#define TEE_WRITE_TEE_UART1_V  0x00000001U
-#define TEE_WRITE_TEE_UART1_S  4
-/** TEE_WRITE_REE0_UART1 : R/W; bitpos: [5]; default: 0;
- *  Configures uart1 registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_UART1    (BIT(5))
-#define TEE_WRITE_REE0_UART1_M  (TEE_WRITE_REE0_UART1_V << TEE_WRITE_REE0_UART1_S)
-#define TEE_WRITE_REE0_UART1_V  0x00000001U
-#define TEE_WRITE_REE0_UART1_S  5
-/** TEE_WRITE_REE1_UART1 : R/W; bitpos: [6]; default: 0;
- *  Configures uart1 registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_UART1    (BIT(6))
-#define TEE_WRITE_REE1_UART1_M  (TEE_WRITE_REE1_UART1_V << TEE_WRITE_REE1_UART1_S)
-#define TEE_WRITE_REE1_UART1_V  0x00000001U
-#define TEE_WRITE_REE1_UART1_S  6
-/** TEE_WRITE_REE2_UART1 : R/W; bitpos: [7]; default: 0;
- *  Configures uart1 registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_UART1    (BIT(7))
-#define TEE_WRITE_REE2_UART1_M  (TEE_WRITE_REE2_UART1_V << TEE_WRITE_REE2_UART1_S)
-#define TEE_WRITE_REE2_UART1_V  0x00000001U
-#define TEE_WRITE_REE2_UART1_S  7
-
-/** TEE_UHCI_CTRL_REG register
- *  uhci read/write control register
- */
-#define TEE_UHCI_CTRL_REG (DR_REG_TEE_BASE + 0x90)
-/** TEE_READ_TEE_UHCI : R/W; bitpos: [0]; default: 1;
- *  Configures uhci registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_UHCI    (BIT(0))
-#define TEE_READ_TEE_UHCI_M  (TEE_READ_TEE_UHCI_V << TEE_READ_TEE_UHCI_S)
-#define TEE_READ_TEE_UHCI_V  0x00000001U
-#define TEE_READ_TEE_UHCI_S  0
-/** TEE_READ_REE0_UHCI : R/W; bitpos: [1]; default: 0;
- *  Configures uhci registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_UHCI    (BIT(1))
-#define TEE_READ_REE0_UHCI_M  (TEE_READ_REE0_UHCI_V << TEE_READ_REE0_UHCI_S)
-#define TEE_READ_REE0_UHCI_V  0x00000001U
-#define TEE_READ_REE0_UHCI_S  1
-/** TEE_READ_REE1_UHCI : R/W; bitpos: [2]; default: 0;
- *  Configures uhci registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_UHCI    (BIT(2))
-#define TEE_READ_REE1_UHCI_M  (TEE_READ_REE1_UHCI_V << TEE_READ_REE1_UHCI_S)
-#define TEE_READ_REE1_UHCI_V  0x00000001U
-#define TEE_READ_REE1_UHCI_S  2
-/** TEE_READ_REE2_UHCI : R/W; bitpos: [3]; default: 0;
- *  Configures uhci registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_UHCI    (BIT(3))
-#define TEE_READ_REE2_UHCI_M  (TEE_READ_REE2_UHCI_V << TEE_READ_REE2_UHCI_S)
-#define TEE_READ_REE2_UHCI_V  0x00000001U
-#define TEE_READ_REE2_UHCI_S  3
-/** TEE_WRITE_TEE_UHCI : R/W; bitpos: [4]; default: 1;
- *  Configures uhci registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_UHCI    (BIT(4))
-#define TEE_WRITE_TEE_UHCI_M  (TEE_WRITE_TEE_UHCI_V << TEE_WRITE_TEE_UHCI_S)
-#define TEE_WRITE_TEE_UHCI_V  0x00000001U
-#define TEE_WRITE_TEE_UHCI_S  4
-/** TEE_WRITE_REE0_UHCI : R/W; bitpos: [5]; default: 0;
- *  Configures uhci registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_UHCI    (BIT(5))
-#define TEE_WRITE_REE0_UHCI_M  (TEE_WRITE_REE0_UHCI_V << TEE_WRITE_REE0_UHCI_S)
-#define TEE_WRITE_REE0_UHCI_V  0x00000001U
-#define TEE_WRITE_REE0_UHCI_S  5
-/** TEE_WRITE_REE1_UHCI : R/W; bitpos: [6]; default: 0;
- *  Configures uhci registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_UHCI    (BIT(6))
-#define TEE_WRITE_REE1_UHCI_M  (TEE_WRITE_REE1_UHCI_V << TEE_WRITE_REE1_UHCI_S)
-#define TEE_WRITE_REE1_UHCI_V  0x00000001U
-#define TEE_WRITE_REE1_UHCI_S  6
-/** TEE_WRITE_REE2_UHCI : R/W; bitpos: [7]; default: 0;
- *  Configures uhci registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_UHCI    (BIT(7))
-#define TEE_WRITE_REE2_UHCI_M  (TEE_WRITE_REE2_UHCI_V << TEE_WRITE_REE2_UHCI_S)
-#define TEE_WRITE_REE2_UHCI_V  0x00000001U
-#define TEE_WRITE_REE2_UHCI_S  7
-
-/** TEE_I2C0_CTRL_REG register
- *  i2c0 read/write control register
- */
-#define TEE_I2C0_CTRL_REG (DR_REG_TEE_BASE + 0x94)
-/** TEE_READ_TEE_I2C0 : R/W; bitpos: [0]; default: 1;
- *  Configures i2c0 registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_I2C0    (BIT(0))
-#define TEE_READ_TEE_I2C0_M  (TEE_READ_TEE_I2C0_V << TEE_READ_TEE_I2C0_S)
-#define TEE_READ_TEE_I2C0_V  0x00000001U
-#define TEE_READ_TEE_I2C0_S  0
-/** TEE_READ_REE0_I2C0 : R/W; bitpos: [1]; default: 0;
- *  Configures i2c0 registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_I2C0    (BIT(1))
-#define TEE_READ_REE0_I2C0_M  (TEE_READ_REE0_I2C0_V << TEE_READ_REE0_I2C0_S)
-#define TEE_READ_REE0_I2C0_V  0x00000001U
-#define TEE_READ_REE0_I2C0_S  1
-/** TEE_READ_REE1_I2C0 : R/W; bitpos: [2]; default: 0;
- *  Configures i2c0 registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_I2C0    (BIT(2))
-#define TEE_READ_REE1_I2C0_M  (TEE_READ_REE1_I2C0_V << TEE_READ_REE1_I2C0_S)
-#define TEE_READ_REE1_I2C0_V  0x00000001U
-#define TEE_READ_REE1_I2C0_S  2
-/** TEE_READ_REE2_I2C0 : R/W; bitpos: [3]; default: 0;
- *  Configures i2c0 registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_I2C0    (BIT(3))
-#define TEE_READ_REE2_I2C0_M  (TEE_READ_REE2_I2C0_V << TEE_READ_REE2_I2C0_S)
-#define TEE_READ_REE2_I2C0_V  0x00000001U
-#define TEE_READ_REE2_I2C0_S  3
-/** TEE_WRITE_TEE_I2C0 : R/W; bitpos: [4]; default: 1;
- *  Configures i2c0 registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_I2C0    (BIT(4))
-#define TEE_WRITE_TEE_I2C0_M  (TEE_WRITE_TEE_I2C0_V << TEE_WRITE_TEE_I2C0_S)
-#define TEE_WRITE_TEE_I2C0_V  0x00000001U
-#define TEE_WRITE_TEE_I2C0_S  4
-/** TEE_WRITE_REE0_I2C0 : R/W; bitpos: [5]; default: 0;
- *  Configures i2c0 registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_I2C0    (BIT(5))
-#define TEE_WRITE_REE0_I2C0_M  (TEE_WRITE_REE0_I2C0_V << TEE_WRITE_REE0_I2C0_S)
-#define TEE_WRITE_REE0_I2C0_V  0x00000001U
-#define TEE_WRITE_REE0_I2C0_S  5
-/** TEE_WRITE_REE1_I2C0 : R/W; bitpos: [6]; default: 0;
- *  Configures i2c0 registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_I2C0    (BIT(6))
-#define TEE_WRITE_REE1_I2C0_M  (TEE_WRITE_REE1_I2C0_V << TEE_WRITE_REE1_I2C0_S)
-#define TEE_WRITE_REE1_I2C0_V  0x00000001U
-#define TEE_WRITE_REE1_I2C0_S  6
-/** TEE_WRITE_REE2_I2C0 : R/W; bitpos: [7]; default: 0;
- *  Configures i2c0 registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_I2C0    (BIT(7))
-#define TEE_WRITE_REE2_I2C0_M  (TEE_WRITE_REE2_I2C0_V << TEE_WRITE_REE2_I2C0_S)
-#define TEE_WRITE_REE2_I2C0_V  0x00000001U
-#define TEE_WRITE_REE2_I2C0_S  7
-
-/** TEE_I2C1_CTRL_REG register
- *  i2c1 read/write control register
- */
-#define TEE_I2C1_CTRL_REG (DR_REG_TEE_BASE + 0x98)
-/** TEE_READ_TEE_I2C1 : R/W; bitpos: [0]; default: 1;
- *  Configures i2c1 registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_I2C1    (BIT(0))
-#define TEE_READ_TEE_I2C1_M  (TEE_READ_TEE_I2C1_V << TEE_READ_TEE_I2C1_S)
-#define TEE_READ_TEE_I2C1_V  0x00000001U
-#define TEE_READ_TEE_I2C1_S  0
-/** TEE_READ_REE0_I2C1 : R/W; bitpos: [1]; default: 0;
- *  Configures i2c1 registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_I2C1    (BIT(1))
-#define TEE_READ_REE0_I2C1_M  (TEE_READ_REE0_I2C1_V << TEE_READ_REE0_I2C1_S)
-#define TEE_READ_REE0_I2C1_V  0x00000001U
-#define TEE_READ_REE0_I2C1_S  1
-/** TEE_READ_REE1_I2C1 : R/W; bitpos: [2]; default: 0;
- *  Configures i2c1 registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_I2C1    (BIT(2))
-#define TEE_READ_REE1_I2C1_M  (TEE_READ_REE1_I2C1_V << TEE_READ_REE1_I2C1_S)
-#define TEE_READ_REE1_I2C1_V  0x00000001U
-#define TEE_READ_REE1_I2C1_S  2
-/** TEE_READ_REE2_I2C1 : R/W; bitpos: [3]; default: 0;
- *  Configures i2c1 registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_I2C1    (BIT(3))
-#define TEE_READ_REE2_I2C1_M  (TEE_READ_REE2_I2C1_V << TEE_READ_REE2_I2C1_S)
-#define TEE_READ_REE2_I2C1_V  0x00000001U
-#define TEE_READ_REE2_I2C1_S  3
-/** TEE_WRITE_TEE_I2C1 : R/W; bitpos: [4]; default: 1;
- *  Configures i2c1 registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_I2C1    (BIT(4))
-#define TEE_WRITE_TEE_I2C1_M  (TEE_WRITE_TEE_I2C1_V << TEE_WRITE_TEE_I2C1_S)
-#define TEE_WRITE_TEE_I2C1_V  0x00000001U
-#define TEE_WRITE_TEE_I2C1_S  4
-/** TEE_WRITE_REE0_I2C1 : R/W; bitpos: [5]; default: 0;
- *  Configures i2c1 registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_I2C1    (BIT(5))
-#define TEE_WRITE_REE0_I2C1_M  (TEE_WRITE_REE0_I2C1_V << TEE_WRITE_REE0_I2C1_S)
-#define TEE_WRITE_REE0_I2C1_V  0x00000001U
-#define TEE_WRITE_REE0_I2C1_S  5
-/** TEE_WRITE_REE1_I2C1 : R/W; bitpos: [6]; default: 0;
- *  Configures i2c1 registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_I2C1    (BIT(6))
-#define TEE_WRITE_REE1_I2C1_M  (TEE_WRITE_REE1_I2C1_V << TEE_WRITE_REE1_I2C1_S)
-#define TEE_WRITE_REE1_I2C1_V  0x00000001U
-#define TEE_WRITE_REE1_I2C1_S  6
-/** TEE_WRITE_REE2_I2C1 : R/W; bitpos: [7]; default: 0;
- *  Configures i2c1 registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_I2C1    (BIT(7))
-#define TEE_WRITE_REE2_I2C1_M  (TEE_WRITE_REE2_I2C1_V << TEE_WRITE_REE2_I2C1_S)
-#define TEE_WRITE_REE2_I2C1_V  0x00000001U
-#define TEE_WRITE_REE2_I2C1_S  7
-
-/** TEE_I2S_CTRL_REG register
- *  i2s read/write control register
- */
-#define TEE_I2S_CTRL_REG (DR_REG_TEE_BASE + 0x9c)
-/** TEE_READ_TEE_I2S : R/W; bitpos: [0]; default: 1;
- *  Configures i2s registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_I2S    (BIT(0))
-#define TEE_READ_TEE_I2S_M  (TEE_READ_TEE_I2S_V << TEE_READ_TEE_I2S_S)
-#define TEE_READ_TEE_I2S_V  0x00000001U
-#define TEE_READ_TEE_I2S_S  0
-/** TEE_READ_REE0_I2S : R/W; bitpos: [1]; default: 0;
- *  Configures i2s registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_I2S    (BIT(1))
-#define TEE_READ_REE0_I2S_M  (TEE_READ_REE0_I2S_V << TEE_READ_REE0_I2S_S)
-#define TEE_READ_REE0_I2S_V  0x00000001U
-#define TEE_READ_REE0_I2S_S  1
-/** TEE_READ_REE1_I2S : R/W; bitpos: [2]; default: 0;
- *  Configures i2s registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_I2S    (BIT(2))
-#define TEE_READ_REE1_I2S_M  (TEE_READ_REE1_I2S_V << TEE_READ_REE1_I2S_S)
-#define TEE_READ_REE1_I2S_V  0x00000001U
-#define TEE_READ_REE1_I2S_S  2
-/** TEE_READ_REE2_I2S : R/W; bitpos: [3]; default: 0;
- *  Configures i2s registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_I2S    (BIT(3))
-#define TEE_READ_REE2_I2S_M  (TEE_READ_REE2_I2S_V << TEE_READ_REE2_I2S_S)
-#define TEE_READ_REE2_I2S_V  0x00000001U
-#define TEE_READ_REE2_I2S_S  3
-/** TEE_WRITE_TEE_I2S : R/W; bitpos: [4]; default: 1;
- *  Configures i2s registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_I2S    (BIT(4))
-#define TEE_WRITE_TEE_I2S_M  (TEE_WRITE_TEE_I2S_V << TEE_WRITE_TEE_I2S_S)
-#define TEE_WRITE_TEE_I2S_V  0x00000001U
-#define TEE_WRITE_TEE_I2S_S  4
-/** TEE_WRITE_REE0_I2S : R/W; bitpos: [5]; default: 0;
- *  Configures i2s registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_I2S    (BIT(5))
-#define TEE_WRITE_REE0_I2S_M  (TEE_WRITE_REE0_I2S_V << TEE_WRITE_REE0_I2S_S)
-#define TEE_WRITE_REE0_I2S_V  0x00000001U
-#define TEE_WRITE_REE0_I2S_S  5
-/** TEE_WRITE_REE1_I2S : R/W; bitpos: [6]; default: 0;
- *  Configures i2s registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_I2S    (BIT(6))
-#define TEE_WRITE_REE1_I2S_M  (TEE_WRITE_REE1_I2S_V << TEE_WRITE_REE1_I2S_S)
-#define TEE_WRITE_REE1_I2S_V  0x00000001U
-#define TEE_WRITE_REE1_I2S_S  6
-/** TEE_WRITE_REE2_I2S : R/W; bitpos: [7]; default: 0;
- *  Configures i2s registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_I2S    (BIT(7))
-#define TEE_WRITE_REE2_I2S_M  (TEE_WRITE_REE2_I2S_V << TEE_WRITE_REE2_I2S_S)
-#define TEE_WRITE_REE2_I2S_V  0x00000001U
-#define TEE_WRITE_REE2_I2S_S  7
-
-/** TEE_PARL_IO_CTRL_REG register
- *  parl_io read/write control register
- */
-#define TEE_PARL_IO_CTRL_REG (DR_REG_TEE_BASE + 0xa0)
-/** TEE_READ_TEE_PARL_IO : R/W; bitpos: [0]; default: 1;
- *  Configures parl_io registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_PARL_IO    (BIT(0))
-#define TEE_READ_TEE_PARL_IO_M  (TEE_READ_TEE_PARL_IO_V << TEE_READ_TEE_PARL_IO_S)
-#define TEE_READ_TEE_PARL_IO_V  0x00000001U
-#define TEE_READ_TEE_PARL_IO_S  0
-/** TEE_READ_REE0_PARL_IO : R/W; bitpos: [1]; default: 0;
- *  Configures parl_io registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_PARL_IO    (BIT(1))
-#define TEE_READ_REE0_PARL_IO_M  (TEE_READ_REE0_PARL_IO_V << TEE_READ_REE0_PARL_IO_S)
-#define TEE_READ_REE0_PARL_IO_V  0x00000001U
-#define TEE_READ_REE0_PARL_IO_S  1
-/** TEE_READ_REE1_PARL_IO : R/W; bitpos: [2]; default: 0;
- *  Configures parl_io registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_PARL_IO    (BIT(2))
-#define TEE_READ_REE1_PARL_IO_M  (TEE_READ_REE1_PARL_IO_V << TEE_READ_REE1_PARL_IO_S)
-#define TEE_READ_REE1_PARL_IO_V  0x00000001U
-#define TEE_READ_REE1_PARL_IO_S  2
-/** TEE_READ_REE2_PARL_IO : R/W; bitpos: [3]; default: 0;
- *  Configures parl_io registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_PARL_IO    (BIT(3))
-#define TEE_READ_REE2_PARL_IO_M  (TEE_READ_REE2_PARL_IO_V << TEE_READ_REE2_PARL_IO_S)
-#define TEE_READ_REE2_PARL_IO_V  0x00000001U
-#define TEE_READ_REE2_PARL_IO_S  3
-/** TEE_WRITE_TEE_PARL_IO : R/W; bitpos: [4]; default: 1;
- *  Configures parl_io registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_PARL_IO    (BIT(4))
-#define TEE_WRITE_TEE_PARL_IO_M  (TEE_WRITE_TEE_PARL_IO_V << TEE_WRITE_TEE_PARL_IO_S)
-#define TEE_WRITE_TEE_PARL_IO_V  0x00000001U
-#define TEE_WRITE_TEE_PARL_IO_S  4
-/** TEE_WRITE_REE0_PARL_IO : R/W; bitpos: [5]; default: 0;
- *  Configures parl_io registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_PARL_IO    (BIT(5))
-#define TEE_WRITE_REE0_PARL_IO_M  (TEE_WRITE_REE0_PARL_IO_V << TEE_WRITE_REE0_PARL_IO_S)
-#define TEE_WRITE_REE0_PARL_IO_V  0x00000001U
-#define TEE_WRITE_REE0_PARL_IO_S  5
-/** TEE_WRITE_REE1_PARL_IO : R/W; bitpos: [6]; default: 0;
- *  Configures parl_io registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_PARL_IO    (BIT(6))
-#define TEE_WRITE_REE1_PARL_IO_M  (TEE_WRITE_REE1_PARL_IO_V << TEE_WRITE_REE1_PARL_IO_S)
-#define TEE_WRITE_REE1_PARL_IO_V  0x00000001U
-#define TEE_WRITE_REE1_PARL_IO_S  6
-/** TEE_WRITE_REE2_PARL_IO : R/W; bitpos: [7]; default: 0;
- *  Configures parl_io registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_PARL_IO    (BIT(7))
-#define TEE_WRITE_REE2_PARL_IO_M  (TEE_WRITE_REE2_PARL_IO_V << TEE_WRITE_REE2_PARL_IO_S)
-#define TEE_WRITE_REE2_PARL_IO_V  0x00000001U
-#define TEE_WRITE_REE2_PARL_IO_S  7
-
-/** TEE_PWM0_CTRL_REG register
- *  pwm0 read/write control register
- */
-#define TEE_PWM0_CTRL_REG (DR_REG_TEE_BASE + 0xa4)
-/** TEE_READ_TEE_PWM0 : R/W; bitpos: [0]; default: 1;
- *  Configures pwm0 registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_PWM0    (BIT(0))
-#define TEE_READ_TEE_PWM0_M  (TEE_READ_TEE_PWM0_V << TEE_READ_TEE_PWM0_S)
-#define TEE_READ_TEE_PWM0_V  0x00000001U
-#define TEE_READ_TEE_PWM0_S  0
-/** TEE_READ_REE0_PWM0 : R/W; bitpos: [1]; default: 0;
- *  Configures pwm0 registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_PWM0    (BIT(1))
-#define TEE_READ_REE0_PWM0_M  (TEE_READ_REE0_PWM0_V << TEE_READ_REE0_PWM0_S)
-#define TEE_READ_REE0_PWM0_V  0x00000001U
-#define TEE_READ_REE0_PWM0_S  1
-/** TEE_READ_REE1_PWM0 : R/W; bitpos: [2]; default: 0;
- *  Configures pwm0 registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_PWM0    (BIT(2))
-#define TEE_READ_REE1_PWM0_M  (TEE_READ_REE1_PWM0_V << TEE_READ_REE1_PWM0_S)
-#define TEE_READ_REE1_PWM0_V  0x00000001U
-#define TEE_READ_REE1_PWM0_S  2
-/** TEE_READ_REE2_PWM0 : R/W; bitpos: [3]; default: 0;
- *  Configures pwm0 registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_PWM0    (BIT(3))
-#define TEE_READ_REE2_PWM0_M  (TEE_READ_REE2_PWM0_V << TEE_READ_REE2_PWM0_S)
-#define TEE_READ_REE2_PWM0_V  0x00000001U
-#define TEE_READ_REE2_PWM0_S  3
-/** TEE_WRITE_TEE_PWM0 : R/W; bitpos: [4]; default: 1;
- *  Configures pwm0 registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_PWM0    (BIT(4))
-#define TEE_WRITE_TEE_PWM0_M  (TEE_WRITE_TEE_PWM0_V << TEE_WRITE_TEE_PWM0_S)
-#define TEE_WRITE_TEE_PWM0_V  0x00000001U
-#define TEE_WRITE_TEE_PWM0_S  4
-/** TEE_WRITE_REE0_PWM0 : R/W; bitpos: [5]; default: 0;
- *  Configures pwm0 registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_PWM0    (BIT(5))
-#define TEE_WRITE_REE0_PWM0_M  (TEE_WRITE_REE0_PWM0_V << TEE_WRITE_REE0_PWM0_S)
-#define TEE_WRITE_REE0_PWM0_V  0x00000001U
-#define TEE_WRITE_REE0_PWM0_S  5
-/** TEE_WRITE_REE1_PWM0 : R/W; bitpos: [6]; default: 0;
- *  Configures pwm0 registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_PWM0    (BIT(6))
-#define TEE_WRITE_REE1_PWM0_M  (TEE_WRITE_REE1_PWM0_V << TEE_WRITE_REE1_PWM0_S)
-#define TEE_WRITE_REE1_PWM0_V  0x00000001U
-#define TEE_WRITE_REE1_PWM0_S  6
-/** TEE_WRITE_REE2_PWM0 : R/W; bitpos: [7]; default: 0;
- *  Configures pwm0 registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_PWM0    (BIT(7))
-#define TEE_WRITE_REE2_PWM0_M  (TEE_WRITE_REE2_PWM0_V << TEE_WRITE_REE2_PWM0_S)
-#define TEE_WRITE_REE2_PWM0_V  0x00000001U
-#define TEE_WRITE_REE2_PWM0_S  7
-
-/** TEE_PWM1_CTRL_REG register
- *  pwm1 read/write control register
- */
-#define TEE_PWM1_CTRL_REG (DR_REG_TEE_BASE + 0xa8)
-/** TEE_READ_TEE_PWM1 : R/W; bitpos: [0]; default: 1;
- *  Configures pwm1 registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_PWM1    (BIT(0))
-#define TEE_READ_TEE_PWM1_M  (TEE_READ_TEE_PWM1_V << TEE_READ_TEE_PWM1_S)
-#define TEE_READ_TEE_PWM1_V  0x00000001U
-#define TEE_READ_TEE_PWM1_S  0
-/** TEE_READ_REE0_PWM1 : R/W; bitpos: [1]; default: 0;
- *  Configures pwm1 registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_PWM1    (BIT(1))
-#define TEE_READ_REE0_PWM1_M  (TEE_READ_REE0_PWM1_V << TEE_READ_REE0_PWM1_S)
-#define TEE_READ_REE0_PWM1_V  0x00000001U
-#define TEE_READ_REE0_PWM1_S  1
-/** TEE_READ_REE1_PWM1 : R/W; bitpos: [2]; default: 0;
- *  Configures pwm1 registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_PWM1    (BIT(2))
-#define TEE_READ_REE1_PWM1_M  (TEE_READ_REE1_PWM1_V << TEE_READ_REE1_PWM1_S)
-#define TEE_READ_REE1_PWM1_V  0x00000001U
-#define TEE_READ_REE1_PWM1_S  2
-/** TEE_READ_REE2_PWM1 : R/W; bitpos: [3]; default: 0;
- *  Configures pwm1 registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_PWM1    (BIT(3))
-#define TEE_READ_REE2_PWM1_M  (TEE_READ_REE2_PWM1_V << TEE_READ_REE2_PWM1_S)
-#define TEE_READ_REE2_PWM1_V  0x00000001U
-#define TEE_READ_REE2_PWM1_S  3
-/** TEE_WRITE_TEE_PWM1 : R/W; bitpos: [4]; default: 1;
- *  Configures pwm1 registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_PWM1    (BIT(4))
-#define TEE_WRITE_TEE_PWM1_M  (TEE_WRITE_TEE_PWM1_V << TEE_WRITE_TEE_PWM1_S)
-#define TEE_WRITE_TEE_PWM1_V  0x00000001U
-#define TEE_WRITE_TEE_PWM1_S  4
-/** TEE_WRITE_REE0_PWM1 : R/W; bitpos: [5]; default: 0;
- *  Configures pwm1 registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_PWM1    (BIT(5))
-#define TEE_WRITE_REE0_PWM1_M  (TEE_WRITE_REE0_PWM1_V << TEE_WRITE_REE0_PWM1_S)
-#define TEE_WRITE_REE0_PWM1_V  0x00000001U
-#define TEE_WRITE_REE0_PWM1_S  5
-/** TEE_WRITE_REE1_PWM1 : R/W; bitpos: [6]; default: 0;
- *  Configures pwm1 registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_PWM1    (BIT(6))
-#define TEE_WRITE_REE1_PWM1_M  (TEE_WRITE_REE1_PWM1_V << TEE_WRITE_REE1_PWM1_S)
-#define TEE_WRITE_REE1_PWM1_V  0x00000001U
-#define TEE_WRITE_REE1_PWM1_S  6
-/** TEE_WRITE_REE2_PWM1 : R/W; bitpos: [7]; default: 0;
- *  Configures pwm1 registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_PWM1    (BIT(7))
-#define TEE_WRITE_REE2_PWM1_M  (TEE_WRITE_REE2_PWM1_V << TEE_WRITE_REE2_PWM1_S)
-#define TEE_WRITE_REE2_PWM1_V  0x00000001U
-#define TEE_WRITE_REE2_PWM1_S  7
-
-/** TEE_LEDC_CTRL_REG register
- *  ledc read/write control register
- */
-#define TEE_LEDC_CTRL_REG (DR_REG_TEE_BASE + 0xac)
-/** TEE_READ_TEE_LEDC : R/W; bitpos: [0]; default: 1;
- *  Configures ledc registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_LEDC    (BIT(0))
-#define TEE_READ_TEE_LEDC_M  (TEE_READ_TEE_LEDC_V << TEE_READ_TEE_LEDC_S)
-#define TEE_READ_TEE_LEDC_V  0x00000001U
-#define TEE_READ_TEE_LEDC_S  0
-/** TEE_READ_REE0_LEDC : R/W; bitpos: [1]; default: 0;
- *  Configures ledc registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_LEDC    (BIT(1))
-#define TEE_READ_REE0_LEDC_M  (TEE_READ_REE0_LEDC_V << TEE_READ_REE0_LEDC_S)
-#define TEE_READ_REE0_LEDC_V  0x00000001U
-#define TEE_READ_REE0_LEDC_S  1
-/** TEE_READ_REE1_LEDC : R/W; bitpos: [2]; default: 0;
- *  Configures ledc registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_LEDC    (BIT(2))
-#define TEE_READ_REE1_LEDC_M  (TEE_READ_REE1_LEDC_V << TEE_READ_REE1_LEDC_S)
-#define TEE_READ_REE1_LEDC_V  0x00000001U
-#define TEE_READ_REE1_LEDC_S  2
-/** TEE_READ_REE2_LEDC : R/W; bitpos: [3]; default: 0;
- *  Configures ledc registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_LEDC    (BIT(3))
-#define TEE_READ_REE2_LEDC_M  (TEE_READ_REE2_LEDC_V << TEE_READ_REE2_LEDC_S)
-#define TEE_READ_REE2_LEDC_V  0x00000001U
-#define TEE_READ_REE2_LEDC_S  3
-/** TEE_WRITE_TEE_LEDC : R/W; bitpos: [4]; default: 1;
- *  Configures ledc registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_LEDC    (BIT(4))
-#define TEE_WRITE_TEE_LEDC_M  (TEE_WRITE_TEE_LEDC_V << TEE_WRITE_TEE_LEDC_S)
-#define TEE_WRITE_TEE_LEDC_V  0x00000001U
-#define TEE_WRITE_TEE_LEDC_S  4
-/** TEE_WRITE_REE0_LEDC : R/W; bitpos: [5]; default: 0;
- *  Configures ledc registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_LEDC    (BIT(5))
-#define TEE_WRITE_REE0_LEDC_M  (TEE_WRITE_REE0_LEDC_V << TEE_WRITE_REE0_LEDC_S)
-#define TEE_WRITE_REE0_LEDC_V  0x00000001U
-#define TEE_WRITE_REE0_LEDC_S  5
-/** TEE_WRITE_REE1_LEDC : R/W; bitpos: [6]; default: 0;
- *  Configures ledc registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_LEDC    (BIT(6))
-#define TEE_WRITE_REE1_LEDC_M  (TEE_WRITE_REE1_LEDC_V << TEE_WRITE_REE1_LEDC_S)
-#define TEE_WRITE_REE1_LEDC_V  0x00000001U
-#define TEE_WRITE_REE1_LEDC_S  6
-/** TEE_WRITE_REE2_LEDC : R/W; bitpos: [7]; default: 0;
- *  Configures ledc registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_LEDC    (BIT(7))
-#define TEE_WRITE_REE2_LEDC_M  (TEE_WRITE_REE2_LEDC_V << TEE_WRITE_REE2_LEDC_S)
-#define TEE_WRITE_REE2_LEDC_V  0x00000001U
-#define TEE_WRITE_REE2_LEDC_S  7
-
-/** TEE_CAN_CTRL_REG register
- *  can read/write control register
- */
-#define TEE_CAN_CTRL_REG (DR_REG_TEE_BASE + 0xb0)
-/** TEE_READ_TEE_CAN : R/W; bitpos: [0]; default: 1;
- *  Configures can registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_CAN    (BIT(0))
-#define TEE_READ_TEE_CAN_M  (TEE_READ_TEE_CAN_V << TEE_READ_TEE_CAN_S)
-#define TEE_READ_TEE_CAN_V  0x00000001U
-#define TEE_READ_TEE_CAN_S  0
-/** TEE_READ_REE0_CAN : R/W; bitpos: [1]; default: 0;
- *  Configures can registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_CAN    (BIT(1))
-#define TEE_READ_REE0_CAN_M  (TEE_READ_REE0_CAN_V << TEE_READ_REE0_CAN_S)
-#define TEE_READ_REE0_CAN_V  0x00000001U
-#define TEE_READ_REE0_CAN_S  1
-/** TEE_READ_REE1_CAN : R/W; bitpos: [2]; default: 0;
- *  Configures can registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_CAN    (BIT(2))
-#define TEE_READ_REE1_CAN_M  (TEE_READ_REE1_CAN_V << TEE_READ_REE1_CAN_S)
-#define TEE_READ_REE1_CAN_V  0x00000001U
-#define TEE_READ_REE1_CAN_S  2
-/** TEE_READ_REE2_CAN : R/W; bitpos: [3]; default: 0;
- *  Configures can registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_CAN    (BIT(3))
-#define TEE_READ_REE2_CAN_M  (TEE_READ_REE2_CAN_V << TEE_READ_REE2_CAN_S)
-#define TEE_READ_REE2_CAN_V  0x00000001U
-#define TEE_READ_REE2_CAN_S  3
-/** TEE_WRITE_TEE_CAN : R/W; bitpos: [4]; default: 1;
- *  Configures can registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_CAN    (BIT(4))
-#define TEE_WRITE_TEE_CAN_M  (TEE_WRITE_TEE_CAN_V << TEE_WRITE_TEE_CAN_S)
-#define TEE_WRITE_TEE_CAN_V  0x00000001U
-#define TEE_WRITE_TEE_CAN_S  4
-/** TEE_WRITE_REE0_CAN : R/W; bitpos: [5]; default: 0;
- *  Configures can registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_CAN    (BIT(5))
-#define TEE_WRITE_REE0_CAN_M  (TEE_WRITE_REE0_CAN_V << TEE_WRITE_REE0_CAN_S)
-#define TEE_WRITE_REE0_CAN_V  0x00000001U
-#define TEE_WRITE_REE0_CAN_S  5
-/** TEE_WRITE_REE1_CAN : R/W; bitpos: [6]; default: 0;
- *  Configures can registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_CAN    (BIT(6))
-#define TEE_WRITE_REE1_CAN_M  (TEE_WRITE_REE1_CAN_V << TEE_WRITE_REE1_CAN_S)
-#define TEE_WRITE_REE1_CAN_V  0x00000001U
-#define TEE_WRITE_REE1_CAN_S  6
-/** TEE_WRITE_REE2_CAN : R/W; bitpos: [7]; default: 0;
- *  Configures can registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_CAN    (BIT(7))
-#define TEE_WRITE_REE2_CAN_M  (TEE_WRITE_REE2_CAN_V << TEE_WRITE_REE2_CAN_S)
-#define TEE_WRITE_REE2_CAN_V  0x00000001U
-#define TEE_WRITE_REE2_CAN_S  7
-
-/** TEE_USB_SERIAL_JTAG_CTRL_REG register
- *  usb_serial_jtag read/write control register
- */
-#define TEE_USB_SERIAL_JTAG_CTRL_REG (DR_REG_TEE_BASE + 0xb4)
-/** TEE_READ_TEE_USB_SERIAL_JTAG : R/W; bitpos: [0]; default: 1;
- *  Configures usb_serial_jtag registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_USB_SERIAL_JTAG    (BIT(0))
-#define TEE_READ_TEE_USB_SERIAL_JTAG_M  (TEE_READ_TEE_USB_SERIAL_JTAG_V << TEE_READ_TEE_USB_SERIAL_JTAG_S)
-#define TEE_READ_TEE_USB_SERIAL_JTAG_V  0x00000001U
-#define TEE_READ_TEE_USB_SERIAL_JTAG_S  0
-/** TEE_READ_REE0_USB_SERIAL_JTAG : R/W; bitpos: [1]; default: 0;
- *  Configures usb_serial_jtag registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_USB_SERIAL_JTAG    (BIT(1))
-#define TEE_READ_REE0_USB_SERIAL_JTAG_M  (TEE_READ_REE0_USB_SERIAL_JTAG_V << TEE_READ_REE0_USB_SERIAL_JTAG_S)
-#define TEE_READ_REE0_USB_SERIAL_JTAG_V  0x00000001U
-#define TEE_READ_REE0_USB_SERIAL_JTAG_S  1
-/** TEE_READ_REE1_USB_SERIAL_JTAG : R/W; bitpos: [2]; default: 0;
- *  Configures usb_serial_jtag registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_USB_SERIAL_JTAG    (BIT(2))
-#define TEE_READ_REE1_USB_SERIAL_JTAG_M  (TEE_READ_REE1_USB_SERIAL_JTAG_V << TEE_READ_REE1_USB_SERIAL_JTAG_S)
-#define TEE_READ_REE1_USB_SERIAL_JTAG_V  0x00000001U
-#define TEE_READ_REE1_USB_SERIAL_JTAG_S  2
-/** TEE_READ_REE2_USB_SERIAL_JTAG : R/W; bitpos: [3]; default: 0;
- *  Configures usb_serial_jtag registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_USB_SERIAL_JTAG    (BIT(3))
-#define TEE_READ_REE2_USB_SERIAL_JTAG_M  (TEE_READ_REE2_USB_SERIAL_JTAG_V << TEE_READ_REE2_USB_SERIAL_JTAG_S)
-#define TEE_READ_REE2_USB_SERIAL_JTAG_V  0x00000001U
-#define TEE_READ_REE2_USB_SERIAL_JTAG_S  3
-/** TEE_WRITE_TEE_USB_SERIAL_JTAG : R/W; bitpos: [4]; default: 1;
- *  Configures usb_serial_jtag registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_USB_SERIAL_JTAG    (BIT(4))
-#define TEE_WRITE_TEE_USB_SERIAL_JTAG_M  (TEE_WRITE_TEE_USB_SERIAL_JTAG_V << TEE_WRITE_TEE_USB_SERIAL_JTAG_S)
-#define TEE_WRITE_TEE_USB_SERIAL_JTAG_V  0x00000001U
-#define TEE_WRITE_TEE_USB_SERIAL_JTAG_S  4
-/** TEE_WRITE_REE0_USB_SERIAL_JTAG : R/W; bitpos: [5]; default: 0;
- *  Configures usb_serial_jtag registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_USB_SERIAL_JTAG    (BIT(5))
-#define TEE_WRITE_REE0_USB_SERIAL_JTAG_M  (TEE_WRITE_REE0_USB_SERIAL_JTAG_V << TEE_WRITE_REE0_USB_SERIAL_JTAG_S)
-#define TEE_WRITE_REE0_USB_SERIAL_JTAG_V  0x00000001U
-#define TEE_WRITE_REE0_USB_SERIAL_JTAG_S  5
-/** TEE_WRITE_REE1_USB_SERIAL_JTAG : R/W; bitpos: [6]; default: 0;
- *  Configures usb_serial_jtag registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_USB_SERIAL_JTAG    (BIT(6))
-#define TEE_WRITE_REE1_USB_SERIAL_JTAG_M  (TEE_WRITE_REE1_USB_SERIAL_JTAG_V << TEE_WRITE_REE1_USB_SERIAL_JTAG_S)
-#define TEE_WRITE_REE1_USB_SERIAL_JTAG_V  0x00000001U
-#define TEE_WRITE_REE1_USB_SERIAL_JTAG_S  6
-/** TEE_WRITE_REE2_USB_SERIAL_JTAG : R/W; bitpos: [7]; default: 0;
- *  Configures usb_serial_jtag registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_USB_SERIAL_JTAG    (BIT(7))
-#define TEE_WRITE_REE2_USB_SERIAL_JTAG_M  (TEE_WRITE_REE2_USB_SERIAL_JTAG_V << TEE_WRITE_REE2_USB_SERIAL_JTAG_S)
-#define TEE_WRITE_REE2_USB_SERIAL_JTAG_V  0x00000001U
-#define TEE_WRITE_REE2_USB_SERIAL_JTAG_S  7
-
-/** TEE_RMT_CTRL_REG register
- *  rmt read/write control register
- */
-#define TEE_RMT_CTRL_REG (DR_REG_TEE_BASE + 0xb8)
-/** TEE_READ_TEE_RMT : R/W; bitpos: [0]; default: 1;
- *  Configures rmt registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_RMT    (BIT(0))
-#define TEE_READ_TEE_RMT_M  (TEE_READ_TEE_RMT_V << TEE_READ_TEE_RMT_S)
-#define TEE_READ_TEE_RMT_V  0x00000001U
-#define TEE_READ_TEE_RMT_S  0
-/** TEE_READ_REE0_RMT : R/W; bitpos: [1]; default: 0;
- *  Configures rmt registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_RMT    (BIT(1))
-#define TEE_READ_REE0_RMT_M  (TEE_READ_REE0_RMT_V << TEE_READ_REE0_RMT_S)
-#define TEE_READ_REE0_RMT_V  0x00000001U
-#define TEE_READ_REE0_RMT_S  1
-/** TEE_READ_REE1_RMT : R/W; bitpos: [2]; default: 0;
- *  Configures rmt registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_RMT    (BIT(2))
-#define TEE_READ_REE1_RMT_M  (TEE_READ_REE1_RMT_V << TEE_READ_REE1_RMT_S)
-#define TEE_READ_REE1_RMT_V  0x00000001U
-#define TEE_READ_REE1_RMT_S  2
-/** TEE_READ_REE2_RMT : R/W; bitpos: [3]; default: 0;
- *  Configures rmt registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_RMT    (BIT(3))
-#define TEE_READ_REE2_RMT_M  (TEE_READ_REE2_RMT_V << TEE_READ_REE2_RMT_S)
-#define TEE_READ_REE2_RMT_V  0x00000001U
-#define TEE_READ_REE2_RMT_S  3
-/** TEE_WRITE_TEE_RMT : R/W; bitpos: [4]; default: 1;
- *  Configures rmt registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_RMT    (BIT(4))
-#define TEE_WRITE_TEE_RMT_M  (TEE_WRITE_TEE_RMT_V << TEE_WRITE_TEE_RMT_S)
-#define TEE_WRITE_TEE_RMT_V  0x00000001U
-#define TEE_WRITE_TEE_RMT_S  4
-/** TEE_WRITE_REE0_RMT : R/W; bitpos: [5]; default: 0;
- *  Configures rmt registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_RMT    (BIT(5))
-#define TEE_WRITE_REE0_RMT_M  (TEE_WRITE_REE0_RMT_V << TEE_WRITE_REE0_RMT_S)
-#define TEE_WRITE_REE0_RMT_V  0x00000001U
-#define TEE_WRITE_REE0_RMT_S  5
-/** TEE_WRITE_REE1_RMT : R/W; bitpos: [6]; default: 0;
- *  Configures rmt registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_RMT    (BIT(6))
-#define TEE_WRITE_REE1_RMT_M  (TEE_WRITE_REE1_RMT_V << TEE_WRITE_REE1_RMT_S)
-#define TEE_WRITE_REE1_RMT_V  0x00000001U
-#define TEE_WRITE_REE1_RMT_S  6
-/** TEE_WRITE_REE2_RMT : R/W; bitpos: [7]; default: 0;
- *  Configures rmt registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_RMT    (BIT(7))
-#define TEE_WRITE_REE2_RMT_M  (TEE_WRITE_REE2_RMT_V << TEE_WRITE_REE2_RMT_S)
-#define TEE_WRITE_REE2_RMT_V  0x00000001U
-#define TEE_WRITE_REE2_RMT_S  7
-
-/** TEE_GDMA_CTRL_REG register
- *  gdma read/write control register
- */
-#define TEE_GDMA_CTRL_REG (DR_REG_TEE_BASE + 0xbc)
-/** TEE_READ_TEE_GDMA : R/W; bitpos: [0]; default: 1;
- *  Configures gdma registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_GDMA    (BIT(0))
-#define TEE_READ_TEE_GDMA_M  (TEE_READ_TEE_GDMA_V << TEE_READ_TEE_GDMA_S)
-#define TEE_READ_TEE_GDMA_V  0x00000001U
-#define TEE_READ_TEE_GDMA_S  0
-/** TEE_READ_REE0_GDMA : R/W; bitpos: [1]; default: 0;
- *  Configures gdma registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_GDMA    (BIT(1))
-#define TEE_READ_REE0_GDMA_M  (TEE_READ_REE0_GDMA_V << TEE_READ_REE0_GDMA_S)
-#define TEE_READ_REE0_GDMA_V  0x00000001U
-#define TEE_READ_REE0_GDMA_S  1
-/** TEE_READ_REE1_GDMA : R/W; bitpos: [2]; default: 0;
- *  Configures gdma registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_GDMA    (BIT(2))
-#define TEE_READ_REE1_GDMA_M  (TEE_READ_REE1_GDMA_V << TEE_READ_REE1_GDMA_S)
-#define TEE_READ_REE1_GDMA_V  0x00000001U
-#define TEE_READ_REE1_GDMA_S  2
-/** TEE_READ_REE2_GDMA : R/W; bitpos: [3]; default: 0;
- *  Configures gdma registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_GDMA    (BIT(3))
-#define TEE_READ_REE2_GDMA_M  (TEE_READ_REE2_GDMA_V << TEE_READ_REE2_GDMA_S)
-#define TEE_READ_REE2_GDMA_V  0x00000001U
-#define TEE_READ_REE2_GDMA_S  3
-/** TEE_WRITE_TEE_GDMA : R/W; bitpos: [4]; default: 1;
- *  Configures gdma registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_GDMA    (BIT(4))
-#define TEE_WRITE_TEE_GDMA_M  (TEE_WRITE_TEE_GDMA_V << TEE_WRITE_TEE_GDMA_S)
-#define TEE_WRITE_TEE_GDMA_V  0x00000001U
-#define TEE_WRITE_TEE_GDMA_S  4
-/** TEE_WRITE_REE0_GDMA : R/W; bitpos: [5]; default: 0;
- *  Configures gdma registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_GDMA    (BIT(5))
-#define TEE_WRITE_REE0_GDMA_M  (TEE_WRITE_REE0_GDMA_V << TEE_WRITE_REE0_GDMA_S)
-#define TEE_WRITE_REE0_GDMA_V  0x00000001U
-#define TEE_WRITE_REE0_GDMA_S  5
-/** TEE_WRITE_REE1_GDMA : R/W; bitpos: [6]; default: 0;
- *  Configures gdma registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_GDMA    (BIT(6))
-#define TEE_WRITE_REE1_GDMA_M  (TEE_WRITE_REE1_GDMA_V << TEE_WRITE_REE1_GDMA_S)
-#define TEE_WRITE_REE1_GDMA_V  0x00000001U
-#define TEE_WRITE_REE1_GDMA_S  6
-/** TEE_WRITE_REE2_GDMA : R/W; bitpos: [7]; default: 0;
- *  Configures gdma registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_GDMA    (BIT(7))
-#define TEE_WRITE_REE2_GDMA_M  (TEE_WRITE_REE2_GDMA_V << TEE_WRITE_REE2_GDMA_S)
-#define TEE_WRITE_REE2_GDMA_V  0x00000001U
-#define TEE_WRITE_REE2_GDMA_S  7
-
-/** TEE_REGDMA_CTRL_REG register
- *  regdma read/write control register
- */
-#define TEE_REGDMA_CTRL_REG (DR_REG_TEE_BASE + 0xc0)
-/** TEE_READ_TEE_REGDMA : R/W; bitpos: [0]; default: 1;
- *  Configures regdma registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_REGDMA    (BIT(0))
-#define TEE_READ_TEE_REGDMA_M  (TEE_READ_TEE_REGDMA_V << TEE_READ_TEE_REGDMA_S)
-#define TEE_READ_TEE_REGDMA_V  0x00000001U
-#define TEE_READ_TEE_REGDMA_S  0
-/** TEE_READ_REE0_REGDMA : R/W; bitpos: [1]; default: 0;
- *  Configures regdma registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_REGDMA    (BIT(1))
-#define TEE_READ_REE0_REGDMA_M  (TEE_READ_REE0_REGDMA_V << TEE_READ_REE0_REGDMA_S)
-#define TEE_READ_REE0_REGDMA_V  0x00000001U
-#define TEE_READ_REE0_REGDMA_S  1
-/** TEE_READ_REE1_REGDMA : R/W; bitpos: [2]; default: 0;
- *  Configures regdma registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_REGDMA    (BIT(2))
-#define TEE_READ_REE1_REGDMA_M  (TEE_READ_REE1_REGDMA_V << TEE_READ_REE1_REGDMA_S)
-#define TEE_READ_REE1_REGDMA_V  0x00000001U
-#define TEE_READ_REE1_REGDMA_S  2
-/** TEE_READ_REE2_REGDMA : R/W; bitpos: [3]; default: 0;
- *  Configures regdma registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_REGDMA    (BIT(3))
-#define TEE_READ_REE2_REGDMA_M  (TEE_READ_REE2_REGDMA_V << TEE_READ_REE2_REGDMA_S)
-#define TEE_READ_REE2_REGDMA_V  0x00000001U
-#define TEE_READ_REE2_REGDMA_S  3
-/** TEE_WRITE_TEE_REGDMA : R/W; bitpos: [4]; default: 1;
- *  Configures regdma registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_REGDMA    (BIT(4))
-#define TEE_WRITE_TEE_REGDMA_M  (TEE_WRITE_TEE_REGDMA_V << TEE_WRITE_TEE_REGDMA_S)
-#define TEE_WRITE_TEE_REGDMA_V  0x00000001U
-#define TEE_WRITE_TEE_REGDMA_S  4
-/** TEE_WRITE_REE0_REGDMA : R/W; bitpos: [5]; default: 0;
- *  Configures regdma registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_REGDMA    (BIT(5))
-#define TEE_WRITE_REE0_REGDMA_M  (TEE_WRITE_REE0_REGDMA_V << TEE_WRITE_REE0_REGDMA_S)
-#define TEE_WRITE_REE0_REGDMA_V  0x00000001U
-#define TEE_WRITE_REE0_REGDMA_S  5
-/** TEE_WRITE_REE1_REGDMA : R/W; bitpos: [6]; default: 0;
- *  Configures regdma registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_REGDMA    (BIT(6))
-#define TEE_WRITE_REE1_REGDMA_M  (TEE_WRITE_REE1_REGDMA_V << TEE_WRITE_REE1_REGDMA_S)
-#define TEE_WRITE_REE1_REGDMA_V  0x00000001U
-#define TEE_WRITE_REE1_REGDMA_S  6
-/** TEE_WRITE_REE2_REGDMA : R/W; bitpos: [7]; default: 0;
- *  Configures regdma registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_REGDMA    (BIT(7))
-#define TEE_WRITE_REE2_REGDMA_M  (TEE_WRITE_REE2_REGDMA_V << TEE_WRITE_REE2_REGDMA_S)
-#define TEE_WRITE_REE2_REGDMA_V  0x00000001U
-#define TEE_WRITE_REE2_REGDMA_S  7
-
-/** TEE_ETM_CTRL_REG register
- *  etm read/write control register
- */
-#define TEE_ETM_CTRL_REG (DR_REG_TEE_BASE + 0xc4)
-/** TEE_READ_TEE_ETM : R/W; bitpos: [0]; default: 1;
- *  Configures etm registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_ETM    (BIT(0))
-#define TEE_READ_TEE_ETM_M  (TEE_READ_TEE_ETM_V << TEE_READ_TEE_ETM_S)
-#define TEE_READ_TEE_ETM_V  0x00000001U
-#define TEE_READ_TEE_ETM_S  0
-/** TEE_READ_REE0_ETM : R/W; bitpos: [1]; default: 0;
- *  Configures etm registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_ETM    (BIT(1))
-#define TEE_READ_REE0_ETM_M  (TEE_READ_REE0_ETM_V << TEE_READ_REE0_ETM_S)
-#define TEE_READ_REE0_ETM_V  0x00000001U
-#define TEE_READ_REE0_ETM_S  1
-/** TEE_READ_REE1_ETM : R/W; bitpos: [2]; default: 0;
- *  Configures etm registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_ETM    (BIT(2))
-#define TEE_READ_REE1_ETM_M  (TEE_READ_REE1_ETM_V << TEE_READ_REE1_ETM_S)
-#define TEE_READ_REE1_ETM_V  0x00000001U
-#define TEE_READ_REE1_ETM_S  2
-/** TEE_READ_REE2_ETM : R/W; bitpos: [3]; default: 0;
- *  Configures etm registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_ETM    (BIT(3))
-#define TEE_READ_REE2_ETM_M  (TEE_READ_REE2_ETM_V << TEE_READ_REE2_ETM_S)
-#define TEE_READ_REE2_ETM_V  0x00000001U
-#define TEE_READ_REE2_ETM_S  3
-/** TEE_WRITE_TEE_ETM : R/W; bitpos: [4]; default: 1;
- *  Configures etm registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_ETM    (BIT(4))
-#define TEE_WRITE_TEE_ETM_M  (TEE_WRITE_TEE_ETM_V << TEE_WRITE_TEE_ETM_S)
-#define TEE_WRITE_TEE_ETM_V  0x00000001U
-#define TEE_WRITE_TEE_ETM_S  4
-/** TEE_WRITE_REE0_ETM : R/W; bitpos: [5]; default: 0;
- *  Configures etm registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_ETM    (BIT(5))
-#define TEE_WRITE_REE0_ETM_M  (TEE_WRITE_REE0_ETM_V << TEE_WRITE_REE0_ETM_S)
-#define TEE_WRITE_REE0_ETM_V  0x00000001U
-#define TEE_WRITE_REE0_ETM_S  5
-/** TEE_WRITE_REE1_ETM : R/W; bitpos: [6]; default: 0;
- *  Configures etm registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_ETM    (BIT(6))
-#define TEE_WRITE_REE1_ETM_M  (TEE_WRITE_REE1_ETM_V << TEE_WRITE_REE1_ETM_S)
-#define TEE_WRITE_REE1_ETM_V  0x00000001U
-#define TEE_WRITE_REE1_ETM_S  6
-/** TEE_WRITE_REE2_ETM : R/W; bitpos: [7]; default: 0;
- *  Configures etm registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_ETM    (BIT(7))
-#define TEE_WRITE_REE2_ETM_M  (TEE_WRITE_REE2_ETM_V << TEE_WRITE_REE2_ETM_S)
-#define TEE_WRITE_REE2_ETM_V  0x00000001U
-#define TEE_WRITE_REE2_ETM_S  7
-
-/** TEE_INTMTX_CORE0_CTRL_REG register
- *  intmtx_core0 read/write control register
- */
-#define TEE_INTMTX_CORE0_CTRL_REG (DR_REG_TEE_BASE + 0xc8)
-/** TEE_READ_TEE_INTMTX_CORE0 : R/W; bitpos: [0]; default: 1;
- *  Configures intmtx_core0 registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_INTMTX_CORE0    (BIT(0))
-#define TEE_READ_TEE_INTMTX_CORE0_M  (TEE_READ_TEE_INTMTX_CORE0_V << TEE_READ_TEE_INTMTX_CORE0_S)
-#define TEE_READ_TEE_INTMTX_CORE0_V  0x00000001U
-#define TEE_READ_TEE_INTMTX_CORE0_S  0
-/** TEE_READ_REE0_INTMTX_CORE0 : R/W; bitpos: [1]; default: 0;
- *  Configures intmtx_core0 registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_INTMTX_CORE0    (BIT(1))
-#define TEE_READ_REE0_INTMTX_CORE0_M  (TEE_READ_REE0_INTMTX_CORE0_V << TEE_READ_REE0_INTMTX_CORE0_S)
-#define TEE_READ_REE0_INTMTX_CORE0_V  0x00000001U
-#define TEE_READ_REE0_INTMTX_CORE0_S  1
-/** TEE_READ_REE1_INTMTX_CORE0 : R/W; bitpos: [2]; default: 0;
- *  Configures intmtx_core0 registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_INTMTX_CORE0    (BIT(2))
-#define TEE_READ_REE1_INTMTX_CORE0_M  (TEE_READ_REE1_INTMTX_CORE0_V << TEE_READ_REE1_INTMTX_CORE0_S)
-#define TEE_READ_REE1_INTMTX_CORE0_V  0x00000001U
-#define TEE_READ_REE1_INTMTX_CORE0_S  2
-/** TEE_READ_REE2_INTMTX_CORE0 : R/W; bitpos: [3]; default: 0;
- *  Configures intmtx_core0 registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_INTMTX_CORE0    (BIT(3))
-#define TEE_READ_REE2_INTMTX_CORE0_M  (TEE_READ_REE2_INTMTX_CORE0_V << TEE_READ_REE2_INTMTX_CORE0_S)
-#define TEE_READ_REE2_INTMTX_CORE0_V  0x00000001U
-#define TEE_READ_REE2_INTMTX_CORE0_S  3
-/** TEE_WRITE_TEE_INTMTX_CORE0 : R/W; bitpos: [4]; default: 1;
- *  Configures intmtx_core0 registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_INTMTX_CORE0    (BIT(4))
-#define TEE_WRITE_TEE_INTMTX_CORE0_M  (TEE_WRITE_TEE_INTMTX_CORE0_V << TEE_WRITE_TEE_INTMTX_CORE0_S)
-#define TEE_WRITE_TEE_INTMTX_CORE0_V  0x00000001U
-#define TEE_WRITE_TEE_INTMTX_CORE0_S  4
-/** TEE_WRITE_REE0_INTMTX_CORE0 : R/W; bitpos: [5]; default: 0;
- *  Configures intmtx_core0 registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_INTMTX_CORE0    (BIT(5))
-#define TEE_WRITE_REE0_INTMTX_CORE0_M  (TEE_WRITE_REE0_INTMTX_CORE0_V << TEE_WRITE_REE0_INTMTX_CORE0_S)
-#define TEE_WRITE_REE0_INTMTX_CORE0_V  0x00000001U
-#define TEE_WRITE_REE0_INTMTX_CORE0_S  5
-/** TEE_WRITE_REE1_INTMTX_CORE0 : R/W; bitpos: [6]; default: 0;
- *  Configures intmtx_core0 registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_INTMTX_CORE0    (BIT(6))
-#define TEE_WRITE_REE1_INTMTX_CORE0_M  (TEE_WRITE_REE1_INTMTX_CORE0_V << TEE_WRITE_REE1_INTMTX_CORE0_S)
-#define TEE_WRITE_REE1_INTMTX_CORE0_V  0x00000001U
-#define TEE_WRITE_REE1_INTMTX_CORE0_S  6
-/** TEE_WRITE_REE2_INTMTX_CORE0 : R/W; bitpos: [7]; default: 0;
- *  Configures intmtx_core0 registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_INTMTX_CORE0    (BIT(7))
-#define TEE_WRITE_REE2_INTMTX_CORE0_M  (TEE_WRITE_REE2_INTMTX_CORE0_V << TEE_WRITE_REE2_INTMTX_CORE0_S)
-#define TEE_WRITE_REE2_INTMTX_CORE0_V  0x00000001U
-#define TEE_WRITE_REE2_INTMTX_CORE0_S  7
-
-/** TEE_INTMTX_CORE1_CTRL_REG register
- *  intmtx_core1 read/write control register
- */
-#define TEE_INTMTX_CORE1_CTRL_REG (DR_REG_TEE_BASE + 0xcc)
-/** TEE_READ_TEE_INTMTX_CORE1 : R/W; bitpos: [0]; default: 1;
- *  Configures intmtx_core1 registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_INTMTX_CORE1    (BIT(0))
-#define TEE_READ_TEE_INTMTX_CORE1_M  (TEE_READ_TEE_INTMTX_CORE1_V << TEE_READ_TEE_INTMTX_CORE1_S)
-#define TEE_READ_TEE_INTMTX_CORE1_V  0x00000001U
-#define TEE_READ_TEE_INTMTX_CORE1_S  0
-/** TEE_READ_REE0_INTMTX_CORE1 : R/W; bitpos: [1]; default: 0;
- *  Configures intmtx_core1 registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_INTMTX_CORE1    (BIT(1))
-#define TEE_READ_REE0_INTMTX_CORE1_M  (TEE_READ_REE0_INTMTX_CORE1_V << TEE_READ_REE0_INTMTX_CORE1_S)
-#define TEE_READ_REE0_INTMTX_CORE1_V  0x00000001U
-#define TEE_READ_REE0_INTMTX_CORE1_S  1
-/** TEE_READ_REE1_INTMTX_CORE1 : R/W; bitpos: [2]; default: 0;
- *  Configures intmtx_core1 registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_INTMTX_CORE1    (BIT(2))
-#define TEE_READ_REE1_INTMTX_CORE1_M  (TEE_READ_REE1_INTMTX_CORE1_V << TEE_READ_REE1_INTMTX_CORE1_S)
-#define TEE_READ_REE1_INTMTX_CORE1_V  0x00000001U
-#define TEE_READ_REE1_INTMTX_CORE1_S  2
-/** TEE_READ_REE2_INTMTX_CORE1 : R/W; bitpos: [3]; default: 0;
- *  Configures intmtx_core1 registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_INTMTX_CORE1    (BIT(3))
-#define TEE_READ_REE2_INTMTX_CORE1_M  (TEE_READ_REE2_INTMTX_CORE1_V << TEE_READ_REE2_INTMTX_CORE1_S)
-#define TEE_READ_REE2_INTMTX_CORE1_V  0x00000001U
-#define TEE_READ_REE2_INTMTX_CORE1_S  3
-/** TEE_WRITE_TEE_INTMTX_CORE1 : R/W; bitpos: [4]; default: 1;
- *  Configures intmtx_core1 registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_INTMTX_CORE1    (BIT(4))
-#define TEE_WRITE_TEE_INTMTX_CORE1_M  (TEE_WRITE_TEE_INTMTX_CORE1_V << TEE_WRITE_TEE_INTMTX_CORE1_S)
-#define TEE_WRITE_TEE_INTMTX_CORE1_V  0x00000001U
-#define TEE_WRITE_TEE_INTMTX_CORE1_S  4
-/** TEE_WRITE_REE0_INTMTX_CORE1 : R/W; bitpos: [5]; default: 0;
- *  Configures intmtx_core1 registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_INTMTX_CORE1    (BIT(5))
-#define TEE_WRITE_REE0_INTMTX_CORE1_M  (TEE_WRITE_REE0_INTMTX_CORE1_V << TEE_WRITE_REE0_INTMTX_CORE1_S)
-#define TEE_WRITE_REE0_INTMTX_CORE1_V  0x00000001U
-#define TEE_WRITE_REE0_INTMTX_CORE1_S  5
-/** TEE_WRITE_REE1_INTMTX_CORE1 : R/W; bitpos: [6]; default: 0;
- *  Configures intmtx_core1 registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_INTMTX_CORE1    (BIT(6))
-#define TEE_WRITE_REE1_INTMTX_CORE1_M  (TEE_WRITE_REE1_INTMTX_CORE1_V << TEE_WRITE_REE1_INTMTX_CORE1_S)
-#define TEE_WRITE_REE1_INTMTX_CORE1_V  0x00000001U
-#define TEE_WRITE_REE1_INTMTX_CORE1_S  6
-/** TEE_WRITE_REE2_INTMTX_CORE1 : R/W; bitpos: [7]; default: 0;
- *  Configures intmtx_core1 registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_INTMTX_CORE1    (BIT(7))
-#define TEE_WRITE_REE2_INTMTX_CORE1_M  (TEE_WRITE_REE2_INTMTX_CORE1_V << TEE_WRITE_REE2_INTMTX_CORE1_S)
-#define TEE_WRITE_REE2_INTMTX_CORE1_V  0x00000001U
-#define TEE_WRITE_REE2_INTMTX_CORE1_S  7
-
-/** TEE_APB_ADC_CTRL_REG register
- *  apb_adc read/write control register
- */
-#define TEE_APB_ADC_CTRL_REG (DR_REG_TEE_BASE + 0xd0)
-/** TEE_READ_TEE_APB_ADC : R/W; bitpos: [0]; default: 1;
- *  Configures apb_adc registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_APB_ADC    (BIT(0))
-#define TEE_READ_TEE_APB_ADC_M  (TEE_READ_TEE_APB_ADC_V << TEE_READ_TEE_APB_ADC_S)
-#define TEE_READ_TEE_APB_ADC_V  0x00000001U
-#define TEE_READ_TEE_APB_ADC_S  0
-/** TEE_READ_REE0_APB_ADC : R/W; bitpos: [1]; default: 0;
- *  Configures apb_adc registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_APB_ADC    (BIT(1))
-#define TEE_READ_REE0_APB_ADC_M  (TEE_READ_REE0_APB_ADC_V << TEE_READ_REE0_APB_ADC_S)
-#define TEE_READ_REE0_APB_ADC_V  0x00000001U
-#define TEE_READ_REE0_APB_ADC_S  1
-/** TEE_READ_REE1_APB_ADC : R/W; bitpos: [2]; default: 0;
- *  Configures apb_adc registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_APB_ADC    (BIT(2))
-#define TEE_READ_REE1_APB_ADC_M  (TEE_READ_REE1_APB_ADC_V << TEE_READ_REE1_APB_ADC_S)
-#define TEE_READ_REE1_APB_ADC_V  0x00000001U
-#define TEE_READ_REE1_APB_ADC_S  2
-/** TEE_READ_REE2_APB_ADC : R/W; bitpos: [3]; default: 0;
- *  Configures apb_adc registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_APB_ADC    (BIT(3))
-#define TEE_READ_REE2_APB_ADC_M  (TEE_READ_REE2_APB_ADC_V << TEE_READ_REE2_APB_ADC_S)
-#define TEE_READ_REE2_APB_ADC_V  0x00000001U
-#define TEE_READ_REE2_APB_ADC_S  3
-/** TEE_WRITE_TEE_APB_ADC : R/W; bitpos: [4]; default: 1;
- *  Configures apb_adc registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_APB_ADC    (BIT(4))
-#define TEE_WRITE_TEE_APB_ADC_M  (TEE_WRITE_TEE_APB_ADC_V << TEE_WRITE_TEE_APB_ADC_S)
-#define TEE_WRITE_TEE_APB_ADC_V  0x00000001U
-#define TEE_WRITE_TEE_APB_ADC_S  4
-/** TEE_WRITE_REE0_APB_ADC : R/W; bitpos: [5]; default: 0;
- *  Configures apb_adc registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_APB_ADC    (BIT(5))
-#define TEE_WRITE_REE0_APB_ADC_M  (TEE_WRITE_REE0_APB_ADC_V << TEE_WRITE_REE0_APB_ADC_S)
-#define TEE_WRITE_REE0_APB_ADC_V  0x00000001U
-#define TEE_WRITE_REE0_APB_ADC_S  5
-/** TEE_WRITE_REE1_APB_ADC : R/W; bitpos: [6]; default: 0;
- *  Configures apb_adc registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_APB_ADC    (BIT(6))
-#define TEE_WRITE_REE1_APB_ADC_M  (TEE_WRITE_REE1_APB_ADC_V << TEE_WRITE_REE1_APB_ADC_S)
-#define TEE_WRITE_REE1_APB_ADC_V  0x00000001U
-#define TEE_WRITE_REE1_APB_ADC_S  6
-/** TEE_WRITE_REE2_APB_ADC : R/W; bitpos: [7]; default: 0;
- *  Configures apb_adc registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_APB_ADC    (BIT(7))
-#define TEE_WRITE_REE2_APB_ADC_M  (TEE_WRITE_REE2_APB_ADC_V << TEE_WRITE_REE2_APB_ADC_S)
-#define TEE_WRITE_REE2_APB_ADC_V  0x00000001U
-#define TEE_WRITE_REE2_APB_ADC_S  7
-
-/** TEE_TIMERGROUP0_CTRL_REG register
- *  timergroup0 read/write control register
- */
-#define TEE_TIMERGROUP0_CTRL_REG (DR_REG_TEE_BASE + 0xd4)
-/** TEE_READ_TEE_TIMERGROUP0 : R/W; bitpos: [0]; default: 1;
- *  Configures timergroup0 registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_TIMERGROUP0    (BIT(0))
-#define TEE_READ_TEE_TIMERGROUP0_M  (TEE_READ_TEE_TIMERGROUP0_V << TEE_READ_TEE_TIMERGROUP0_S)
-#define TEE_READ_TEE_TIMERGROUP0_V  0x00000001U
-#define TEE_READ_TEE_TIMERGROUP0_S  0
-/** TEE_READ_REE0_TIMERGROUP0 : R/W; bitpos: [1]; default: 0;
- *  Configures timergroup0 registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_TIMERGROUP0    (BIT(1))
-#define TEE_READ_REE0_TIMERGROUP0_M  (TEE_READ_REE0_TIMERGROUP0_V << TEE_READ_REE0_TIMERGROUP0_S)
-#define TEE_READ_REE0_TIMERGROUP0_V  0x00000001U
-#define TEE_READ_REE0_TIMERGROUP0_S  1
-/** TEE_READ_REE1_TIMERGROUP0 : R/W; bitpos: [2]; default: 0;
- *  Configures timergroup0 registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_TIMERGROUP0    (BIT(2))
-#define TEE_READ_REE1_TIMERGROUP0_M  (TEE_READ_REE1_TIMERGROUP0_V << TEE_READ_REE1_TIMERGROUP0_S)
-#define TEE_READ_REE1_TIMERGROUP0_V  0x00000001U
-#define TEE_READ_REE1_TIMERGROUP0_S  2
-/** TEE_READ_REE2_TIMERGROUP0 : R/W; bitpos: [3]; default: 0;
- *  Configures timergroup0 registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_TIMERGROUP0    (BIT(3))
-#define TEE_READ_REE2_TIMERGROUP0_M  (TEE_READ_REE2_TIMERGROUP0_V << TEE_READ_REE2_TIMERGROUP0_S)
-#define TEE_READ_REE2_TIMERGROUP0_V  0x00000001U
-#define TEE_READ_REE2_TIMERGROUP0_S  3
-/** TEE_WRITE_TEE_TIMERGROUP0 : R/W; bitpos: [4]; default: 1;
- *  Configures timergroup0 registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_TIMERGROUP0    (BIT(4))
-#define TEE_WRITE_TEE_TIMERGROUP0_M  (TEE_WRITE_TEE_TIMERGROUP0_V << TEE_WRITE_TEE_TIMERGROUP0_S)
-#define TEE_WRITE_TEE_TIMERGROUP0_V  0x00000001U
-#define TEE_WRITE_TEE_TIMERGROUP0_S  4
-/** TEE_WRITE_REE0_TIMERGROUP0 : R/W; bitpos: [5]; default: 0;
- *  Configures timergroup0 registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_TIMERGROUP0    (BIT(5))
-#define TEE_WRITE_REE0_TIMERGROUP0_M  (TEE_WRITE_REE0_TIMERGROUP0_V << TEE_WRITE_REE0_TIMERGROUP0_S)
-#define TEE_WRITE_REE0_TIMERGROUP0_V  0x00000001U
-#define TEE_WRITE_REE0_TIMERGROUP0_S  5
-/** TEE_WRITE_REE1_TIMERGROUP0 : R/W; bitpos: [6]; default: 0;
- *  Configures timergroup0 registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_TIMERGROUP0    (BIT(6))
-#define TEE_WRITE_REE1_TIMERGROUP0_M  (TEE_WRITE_REE1_TIMERGROUP0_V << TEE_WRITE_REE1_TIMERGROUP0_S)
-#define TEE_WRITE_REE1_TIMERGROUP0_V  0x00000001U
-#define TEE_WRITE_REE1_TIMERGROUP0_S  6
-/** TEE_WRITE_REE2_TIMERGROUP0 : R/W; bitpos: [7]; default: 0;
- *  Configures timergroup0 registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_TIMERGROUP0    (BIT(7))
-#define TEE_WRITE_REE2_TIMERGROUP0_M  (TEE_WRITE_REE2_TIMERGROUP0_V << TEE_WRITE_REE2_TIMERGROUP0_S)
-#define TEE_WRITE_REE2_TIMERGROUP0_V  0x00000001U
-#define TEE_WRITE_REE2_TIMERGROUP0_S  7
-
-/** TEE_TIMERGROUP1_CTRL_REG register
- *  timergroup1 read/write control register
- */
-#define TEE_TIMERGROUP1_CTRL_REG (DR_REG_TEE_BASE + 0xd8)
-/** TEE_READ_TEE_TIMERGROUP1 : R/W; bitpos: [0]; default: 1;
- *  Configures timergroup1 registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_TIMERGROUP1    (BIT(0))
-#define TEE_READ_TEE_TIMERGROUP1_M  (TEE_READ_TEE_TIMERGROUP1_V << TEE_READ_TEE_TIMERGROUP1_S)
-#define TEE_READ_TEE_TIMERGROUP1_V  0x00000001U
-#define TEE_READ_TEE_TIMERGROUP1_S  0
-/** TEE_READ_REE0_TIMERGROUP1 : R/W; bitpos: [1]; default: 0;
- *  Configures timergroup1 registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_TIMERGROUP1    (BIT(1))
-#define TEE_READ_REE0_TIMERGROUP1_M  (TEE_READ_REE0_TIMERGROUP1_V << TEE_READ_REE0_TIMERGROUP1_S)
-#define TEE_READ_REE0_TIMERGROUP1_V  0x00000001U
-#define TEE_READ_REE0_TIMERGROUP1_S  1
-/** TEE_READ_REE1_TIMERGROUP1 : R/W; bitpos: [2]; default: 0;
- *  Configures timergroup1 registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_TIMERGROUP1    (BIT(2))
-#define TEE_READ_REE1_TIMERGROUP1_M  (TEE_READ_REE1_TIMERGROUP1_V << TEE_READ_REE1_TIMERGROUP1_S)
-#define TEE_READ_REE1_TIMERGROUP1_V  0x00000001U
-#define TEE_READ_REE1_TIMERGROUP1_S  2
-/** TEE_READ_REE2_TIMERGROUP1 : R/W; bitpos: [3]; default: 0;
- *  Configures timergroup1 registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_TIMERGROUP1    (BIT(3))
-#define TEE_READ_REE2_TIMERGROUP1_M  (TEE_READ_REE2_TIMERGROUP1_V << TEE_READ_REE2_TIMERGROUP1_S)
-#define TEE_READ_REE2_TIMERGROUP1_V  0x00000001U
-#define TEE_READ_REE2_TIMERGROUP1_S  3
-/** TEE_WRITE_TEE_TIMERGROUP1 : R/W; bitpos: [4]; default: 1;
- *  Configures timergroup1 registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_TIMERGROUP1    (BIT(4))
-#define TEE_WRITE_TEE_TIMERGROUP1_M  (TEE_WRITE_TEE_TIMERGROUP1_V << TEE_WRITE_TEE_TIMERGROUP1_S)
-#define TEE_WRITE_TEE_TIMERGROUP1_V  0x00000001U
-#define TEE_WRITE_TEE_TIMERGROUP1_S  4
-/** TEE_WRITE_REE0_TIMERGROUP1 : R/W; bitpos: [5]; default: 0;
- *  Configures timergroup1 registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_TIMERGROUP1    (BIT(5))
-#define TEE_WRITE_REE0_TIMERGROUP1_M  (TEE_WRITE_REE0_TIMERGROUP1_V << TEE_WRITE_REE0_TIMERGROUP1_S)
-#define TEE_WRITE_REE0_TIMERGROUP1_V  0x00000001U
-#define TEE_WRITE_REE0_TIMERGROUP1_S  5
-/** TEE_WRITE_REE1_TIMERGROUP1 : R/W; bitpos: [6]; default: 0;
- *  Configures timergroup1 registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_TIMERGROUP1    (BIT(6))
-#define TEE_WRITE_REE1_TIMERGROUP1_M  (TEE_WRITE_REE1_TIMERGROUP1_V << TEE_WRITE_REE1_TIMERGROUP1_S)
-#define TEE_WRITE_REE1_TIMERGROUP1_V  0x00000001U
-#define TEE_WRITE_REE1_TIMERGROUP1_S  6
-/** TEE_WRITE_REE2_TIMERGROUP1 : R/W; bitpos: [7]; default: 0;
- *  Configures timergroup1 registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_TIMERGROUP1    (BIT(7))
-#define TEE_WRITE_REE2_TIMERGROUP1_M  (TEE_WRITE_REE2_TIMERGROUP1_V << TEE_WRITE_REE2_TIMERGROUP1_S)
-#define TEE_WRITE_REE2_TIMERGROUP1_V  0x00000001U
-#define TEE_WRITE_REE2_TIMERGROUP1_S  7
-
-/** TEE_SYSTIMER_CTRL_REG register
- *  systimer read/write control register
- */
-#define TEE_SYSTIMER_CTRL_REG (DR_REG_TEE_BASE + 0xdc)
-/** TEE_READ_TEE_SYSTIMER : R/W; bitpos: [0]; default: 1;
- *  Configures systimer registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_SYSTIMER    (BIT(0))
-#define TEE_READ_TEE_SYSTIMER_M  (TEE_READ_TEE_SYSTIMER_V << TEE_READ_TEE_SYSTIMER_S)
-#define TEE_READ_TEE_SYSTIMER_V  0x00000001U
-#define TEE_READ_TEE_SYSTIMER_S  0
-/** TEE_READ_REE0_SYSTIMER : R/W; bitpos: [1]; default: 0;
- *  Configures systimer registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_SYSTIMER    (BIT(1))
-#define TEE_READ_REE0_SYSTIMER_M  (TEE_READ_REE0_SYSTIMER_V << TEE_READ_REE0_SYSTIMER_S)
-#define TEE_READ_REE0_SYSTIMER_V  0x00000001U
-#define TEE_READ_REE0_SYSTIMER_S  1
-/** TEE_READ_REE1_SYSTIMER : R/W; bitpos: [2]; default: 0;
- *  Configures systimer registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_SYSTIMER    (BIT(2))
-#define TEE_READ_REE1_SYSTIMER_M  (TEE_READ_REE1_SYSTIMER_V << TEE_READ_REE1_SYSTIMER_S)
-#define TEE_READ_REE1_SYSTIMER_V  0x00000001U
-#define TEE_READ_REE1_SYSTIMER_S  2
-/** TEE_READ_REE2_SYSTIMER : R/W; bitpos: [3]; default: 0;
- *  Configures systimer registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_SYSTIMER    (BIT(3))
-#define TEE_READ_REE2_SYSTIMER_M  (TEE_READ_REE2_SYSTIMER_V << TEE_READ_REE2_SYSTIMER_S)
-#define TEE_READ_REE2_SYSTIMER_V  0x00000001U
-#define TEE_READ_REE2_SYSTIMER_S  3
-/** TEE_WRITE_TEE_SYSTIMER : R/W; bitpos: [4]; default: 1;
- *  Configures systimer registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_SYSTIMER    (BIT(4))
-#define TEE_WRITE_TEE_SYSTIMER_M  (TEE_WRITE_TEE_SYSTIMER_V << TEE_WRITE_TEE_SYSTIMER_S)
-#define TEE_WRITE_TEE_SYSTIMER_V  0x00000001U
-#define TEE_WRITE_TEE_SYSTIMER_S  4
-/** TEE_WRITE_REE0_SYSTIMER : R/W; bitpos: [5]; default: 0;
- *  Configures systimer registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_SYSTIMER    (BIT(5))
-#define TEE_WRITE_REE0_SYSTIMER_M  (TEE_WRITE_REE0_SYSTIMER_V << TEE_WRITE_REE0_SYSTIMER_S)
-#define TEE_WRITE_REE0_SYSTIMER_V  0x00000001U
-#define TEE_WRITE_REE0_SYSTIMER_S  5
-/** TEE_WRITE_REE1_SYSTIMER : R/W; bitpos: [6]; default: 0;
- *  Configures systimer registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_SYSTIMER    (BIT(6))
-#define TEE_WRITE_REE1_SYSTIMER_M  (TEE_WRITE_REE1_SYSTIMER_V << TEE_WRITE_REE1_SYSTIMER_S)
-#define TEE_WRITE_REE1_SYSTIMER_V  0x00000001U
-#define TEE_WRITE_REE1_SYSTIMER_S  6
-/** TEE_WRITE_REE2_SYSTIMER : R/W; bitpos: [7]; default: 0;
- *  Configures systimer registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_SYSTIMER    (BIT(7))
-#define TEE_WRITE_REE2_SYSTIMER_M  (TEE_WRITE_REE2_SYSTIMER_V << TEE_WRITE_REE2_SYSTIMER_S)
-#define TEE_WRITE_REE2_SYSTIMER_V  0x00000001U
-#define TEE_WRITE_REE2_SYSTIMER_S  7
-
-/** TEE_MISC_CTRL_REG register
- *  misc read/write control register
- */
-#define TEE_MISC_CTRL_REG (DR_REG_TEE_BASE + 0xe0)
-/** TEE_READ_TEE_MISC : R/W; bitpos: [0]; default: 1;
- *  Configures misc registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_MISC    (BIT(0))
-#define TEE_READ_TEE_MISC_M  (TEE_READ_TEE_MISC_V << TEE_READ_TEE_MISC_S)
-#define TEE_READ_TEE_MISC_V  0x00000001U
-#define TEE_READ_TEE_MISC_S  0
-/** TEE_READ_REE0_MISC : R/W; bitpos: [1]; default: 0;
- *  Configures misc registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_MISC    (BIT(1))
-#define TEE_READ_REE0_MISC_M  (TEE_READ_REE0_MISC_V << TEE_READ_REE0_MISC_S)
-#define TEE_READ_REE0_MISC_V  0x00000001U
-#define TEE_READ_REE0_MISC_S  1
-/** TEE_READ_REE1_MISC : R/W; bitpos: [2]; default: 0;
- *  Configures misc registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_MISC    (BIT(2))
-#define TEE_READ_REE1_MISC_M  (TEE_READ_REE1_MISC_V << TEE_READ_REE1_MISC_S)
-#define TEE_READ_REE1_MISC_V  0x00000001U
-#define TEE_READ_REE1_MISC_S  2
-/** TEE_READ_REE2_MISC : R/W; bitpos: [3]; default: 0;
- *  Configures misc registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_MISC    (BIT(3))
-#define TEE_READ_REE2_MISC_M  (TEE_READ_REE2_MISC_V << TEE_READ_REE2_MISC_S)
-#define TEE_READ_REE2_MISC_V  0x00000001U
-#define TEE_READ_REE2_MISC_S  3
-/** TEE_WRITE_TEE_MISC : R/W; bitpos: [4]; default: 1;
- *  Configures misc registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_MISC    (BIT(4))
-#define TEE_WRITE_TEE_MISC_M  (TEE_WRITE_TEE_MISC_V << TEE_WRITE_TEE_MISC_S)
-#define TEE_WRITE_TEE_MISC_V  0x00000001U
-#define TEE_WRITE_TEE_MISC_S  4
-/** TEE_WRITE_REE0_MISC : R/W; bitpos: [5]; default: 0;
- *  Configures misc registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_MISC    (BIT(5))
-#define TEE_WRITE_REE0_MISC_M  (TEE_WRITE_REE0_MISC_V << TEE_WRITE_REE0_MISC_S)
-#define TEE_WRITE_REE0_MISC_V  0x00000001U
-#define TEE_WRITE_REE0_MISC_S  5
-/** TEE_WRITE_REE1_MISC : R/W; bitpos: [6]; default: 0;
- *  Configures misc registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_MISC    (BIT(6))
-#define TEE_WRITE_REE1_MISC_M  (TEE_WRITE_REE1_MISC_V << TEE_WRITE_REE1_MISC_S)
-#define TEE_WRITE_REE1_MISC_V  0x00000001U
-#define TEE_WRITE_REE1_MISC_S  6
-/** TEE_WRITE_REE2_MISC : R/W; bitpos: [7]; default: 0;
- *  Configures misc registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_MISC    (BIT(7))
-#define TEE_WRITE_REE2_MISC_M  (TEE_WRITE_REE2_MISC_V << TEE_WRITE_REE2_MISC_S)
-#define TEE_WRITE_REE2_MISC_V  0x00000001U
-#define TEE_WRITE_REE2_MISC_S  7
-
-/** TEE_SRC_CTRL_REG register
- *  src read/write control register
- */
-#define TEE_SRC_CTRL_REG (DR_REG_TEE_BASE + 0xe4)
-/** TEE_READ_TEE_SRC : R/W; bitpos: [0]; default: 1;
- *  Configures src registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_SRC    (BIT(0))
-#define TEE_READ_TEE_SRC_M  (TEE_READ_TEE_SRC_V << TEE_READ_TEE_SRC_S)
-#define TEE_READ_TEE_SRC_V  0x00000001U
-#define TEE_READ_TEE_SRC_S  0
-/** TEE_READ_REE0_SRC : R/W; bitpos: [1]; default: 0;
- *  Configures src registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_SRC    (BIT(1))
-#define TEE_READ_REE0_SRC_M  (TEE_READ_REE0_SRC_V << TEE_READ_REE0_SRC_S)
-#define TEE_READ_REE0_SRC_V  0x00000001U
-#define TEE_READ_REE0_SRC_S  1
-/** TEE_READ_REE1_SRC : R/W; bitpos: [2]; default: 0;
- *  Configures src registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_SRC    (BIT(2))
-#define TEE_READ_REE1_SRC_M  (TEE_READ_REE1_SRC_V << TEE_READ_REE1_SRC_S)
-#define TEE_READ_REE1_SRC_V  0x00000001U
-#define TEE_READ_REE1_SRC_S  2
-/** TEE_READ_REE2_SRC : R/W; bitpos: [3]; default: 0;
- *  Configures src registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_SRC    (BIT(3))
-#define TEE_READ_REE2_SRC_M  (TEE_READ_REE2_SRC_V << TEE_READ_REE2_SRC_S)
-#define TEE_READ_REE2_SRC_V  0x00000001U
-#define TEE_READ_REE2_SRC_S  3
-/** TEE_WRITE_TEE_SRC : R/W; bitpos: [4]; default: 1;
- *  Configures src registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_SRC    (BIT(4))
-#define TEE_WRITE_TEE_SRC_M  (TEE_WRITE_TEE_SRC_V << TEE_WRITE_TEE_SRC_S)
-#define TEE_WRITE_TEE_SRC_V  0x00000001U
-#define TEE_WRITE_TEE_SRC_S  4
-/** TEE_WRITE_REE0_SRC : R/W; bitpos: [5]; default: 0;
- *  Configures src registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_SRC    (BIT(5))
-#define TEE_WRITE_REE0_SRC_M  (TEE_WRITE_REE0_SRC_V << TEE_WRITE_REE0_SRC_S)
-#define TEE_WRITE_REE0_SRC_V  0x00000001U
-#define TEE_WRITE_REE0_SRC_S  5
-/** TEE_WRITE_REE1_SRC : R/W; bitpos: [6]; default: 0;
- *  Configures src registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_SRC    (BIT(6))
-#define TEE_WRITE_REE1_SRC_M  (TEE_WRITE_REE1_SRC_V << TEE_WRITE_REE1_SRC_S)
-#define TEE_WRITE_REE1_SRC_V  0x00000001U
-#define TEE_WRITE_REE1_SRC_S  6
-/** TEE_WRITE_REE2_SRC : R/W; bitpos: [7]; default: 0;
- *  Configures src registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_SRC    (BIT(7))
-#define TEE_WRITE_REE2_SRC_M  (TEE_WRITE_REE2_SRC_V << TEE_WRITE_REE2_SRC_S)
-#define TEE_WRITE_REE2_SRC_V  0x00000001U
-#define TEE_WRITE_REE2_SRC_S  7
-
-/** TEE_USB_OTG_FS_CORE_CTRL_REG register
- *  usb_otg_fs_core read/write control register
- */
-#define TEE_USB_OTG_FS_CORE_CTRL_REG (DR_REG_TEE_BASE + 0xe8)
-/** TEE_READ_TEE_USB_OTG_FS_CORE : R/W; bitpos: [0]; default: 1;
- *  Configures usb_otg_fs_core registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_USB_OTG_FS_CORE    (BIT(0))
-#define TEE_READ_TEE_USB_OTG_FS_CORE_M  (TEE_READ_TEE_USB_OTG_FS_CORE_V << TEE_READ_TEE_USB_OTG_FS_CORE_S)
-#define TEE_READ_TEE_USB_OTG_FS_CORE_V  0x00000001U
-#define TEE_READ_TEE_USB_OTG_FS_CORE_S  0
-/** TEE_READ_REE0_USB_OTG_FS_CORE : R/W; bitpos: [1]; default: 0;
- *  Configures usb_otg_fs_core registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_USB_OTG_FS_CORE    (BIT(1))
-#define TEE_READ_REE0_USB_OTG_FS_CORE_M  (TEE_READ_REE0_USB_OTG_FS_CORE_V << TEE_READ_REE0_USB_OTG_FS_CORE_S)
-#define TEE_READ_REE0_USB_OTG_FS_CORE_V  0x00000001U
-#define TEE_READ_REE0_USB_OTG_FS_CORE_S  1
-/** TEE_READ_REE1_USB_OTG_FS_CORE : R/W; bitpos: [2]; default: 0;
- *  Configures usb_otg_fs_core registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_USB_OTG_FS_CORE    (BIT(2))
-#define TEE_READ_REE1_USB_OTG_FS_CORE_M  (TEE_READ_REE1_USB_OTG_FS_CORE_V << TEE_READ_REE1_USB_OTG_FS_CORE_S)
-#define TEE_READ_REE1_USB_OTG_FS_CORE_V  0x00000001U
-#define TEE_READ_REE1_USB_OTG_FS_CORE_S  2
-/** TEE_READ_REE2_USB_OTG_FS_CORE : R/W; bitpos: [3]; default: 0;
- *  Configures usb_otg_fs_core registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_USB_OTG_FS_CORE    (BIT(3))
-#define TEE_READ_REE2_USB_OTG_FS_CORE_M  (TEE_READ_REE2_USB_OTG_FS_CORE_V << TEE_READ_REE2_USB_OTG_FS_CORE_S)
-#define TEE_READ_REE2_USB_OTG_FS_CORE_V  0x00000001U
-#define TEE_READ_REE2_USB_OTG_FS_CORE_S  3
-/** TEE_WRITE_TEE_USB_OTG_FS_CORE : R/W; bitpos: [4]; default: 1;
- *  Configures usb_otg_fs_core registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_USB_OTG_FS_CORE    (BIT(4))
-#define TEE_WRITE_TEE_USB_OTG_FS_CORE_M  (TEE_WRITE_TEE_USB_OTG_FS_CORE_V << TEE_WRITE_TEE_USB_OTG_FS_CORE_S)
-#define TEE_WRITE_TEE_USB_OTG_FS_CORE_V  0x00000001U
-#define TEE_WRITE_TEE_USB_OTG_FS_CORE_S  4
-/** TEE_WRITE_REE0_USB_OTG_FS_CORE : R/W; bitpos: [5]; default: 0;
- *  Configures usb_otg_fs_core registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_USB_OTG_FS_CORE    (BIT(5))
-#define TEE_WRITE_REE0_USB_OTG_FS_CORE_M  (TEE_WRITE_REE0_USB_OTG_FS_CORE_V << TEE_WRITE_REE0_USB_OTG_FS_CORE_S)
-#define TEE_WRITE_REE0_USB_OTG_FS_CORE_V  0x00000001U
-#define TEE_WRITE_REE0_USB_OTG_FS_CORE_S  5
-/** TEE_WRITE_REE1_USB_OTG_FS_CORE : R/W; bitpos: [6]; default: 0;
- *  Configures usb_otg_fs_core registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_USB_OTG_FS_CORE    (BIT(6))
-#define TEE_WRITE_REE1_USB_OTG_FS_CORE_M  (TEE_WRITE_REE1_USB_OTG_FS_CORE_V << TEE_WRITE_REE1_USB_OTG_FS_CORE_S)
-#define TEE_WRITE_REE1_USB_OTG_FS_CORE_V  0x00000001U
-#define TEE_WRITE_REE1_USB_OTG_FS_CORE_S  6
-/** TEE_WRITE_REE2_USB_OTG_FS_CORE : R/W; bitpos: [7]; default: 0;
- *  Configures usb_otg_fs_core registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_USB_OTG_FS_CORE    (BIT(7))
-#define TEE_WRITE_REE2_USB_OTG_FS_CORE_M  (TEE_WRITE_REE2_USB_OTG_FS_CORE_V << TEE_WRITE_REE2_USB_OTG_FS_CORE_S)
-#define TEE_WRITE_REE2_USB_OTG_FS_CORE_V  0x00000001U
-#define TEE_WRITE_REE2_USB_OTG_FS_CORE_S  7
-
-/** TEE_USB_OTG_FS_PHY_CTRL_REG register
- *  usb_otg_fs_phy read/write control register
- */
-#define TEE_USB_OTG_FS_PHY_CTRL_REG (DR_REG_TEE_BASE + 0xec)
-/** TEE_READ_TEE_USB_OTG_FS_PHY : R/W; bitpos: [0]; default: 1;
- *  Configures usb_otg_fs_phy registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_USB_OTG_FS_PHY    (BIT(0))
-#define TEE_READ_TEE_USB_OTG_FS_PHY_M  (TEE_READ_TEE_USB_OTG_FS_PHY_V << TEE_READ_TEE_USB_OTG_FS_PHY_S)
-#define TEE_READ_TEE_USB_OTG_FS_PHY_V  0x00000001U
-#define TEE_READ_TEE_USB_OTG_FS_PHY_S  0
-/** TEE_READ_REE0_USB_OTG_FS_PHY : R/W; bitpos: [1]; default: 0;
- *  Configures usb_otg_fs_phy registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_USB_OTG_FS_PHY    (BIT(1))
-#define TEE_READ_REE0_USB_OTG_FS_PHY_M  (TEE_READ_REE0_USB_OTG_FS_PHY_V << TEE_READ_REE0_USB_OTG_FS_PHY_S)
-#define TEE_READ_REE0_USB_OTG_FS_PHY_V  0x00000001U
-#define TEE_READ_REE0_USB_OTG_FS_PHY_S  1
-/** TEE_READ_REE1_USB_OTG_FS_PHY : R/W; bitpos: [2]; default: 0;
- *  Configures usb_otg_fs_phy registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_USB_OTG_FS_PHY    (BIT(2))
-#define TEE_READ_REE1_USB_OTG_FS_PHY_M  (TEE_READ_REE1_USB_OTG_FS_PHY_V << TEE_READ_REE1_USB_OTG_FS_PHY_S)
-#define TEE_READ_REE1_USB_OTG_FS_PHY_V  0x00000001U
-#define TEE_READ_REE1_USB_OTG_FS_PHY_S  2
-/** TEE_READ_REE2_USB_OTG_FS_PHY : R/W; bitpos: [3]; default: 0;
- *  Configures usb_otg_fs_phy registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_USB_OTG_FS_PHY    (BIT(3))
-#define TEE_READ_REE2_USB_OTG_FS_PHY_M  (TEE_READ_REE2_USB_OTG_FS_PHY_V << TEE_READ_REE2_USB_OTG_FS_PHY_S)
-#define TEE_READ_REE2_USB_OTG_FS_PHY_V  0x00000001U
-#define TEE_READ_REE2_USB_OTG_FS_PHY_S  3
-/** TEE_WRITE_TEE_USB_OTG_FS_PHY : R/W; bitpos: [4]; default: 1;
- *  Configures usb_otg_fs_phy registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_USB_OTG_FS_PHY    (BIT(4))
-#define TEE_WRITE_TEE_USB_OTG_FS_PHY_M  (TEE_WRITE_TEE_USB_OTG_FS_PHY_V << TEE_WRITE_TEE_USB_OTG_FS_PHY_S)
-#define TEE_WRITE_TEE_USB_OTG_FS_PHY_V  0x00000001U
-#define TEE_WRITE_TEE_USB_OTG_FS_PHY_S  4
-/** TEE_WRITE_REE0_USB_OTG_FS_PHY : R/W; bitpos: [5]; default: 0;
- *  Configures usb_otg_fs_phy registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_USB_OTG_FS_PHY    (BIT(5))
-#define TEE_WRITE_REE0_USB_OTG_FS_PHY_M  (TEE_WRITE_REE0_USB_OTG_FS_PHY_V << TEE_WRITE_REE0_USB_OTG_FS_PHY_S)
-#define TEE_WRITE_REE0_USB_OTG_FS_PHY_V  0x00000001U
-#define TEE_WRITE_REE0_USB_OTG_FS_PHY_S  5
-/** TEE_WRITE_REE1_USB_OTG_FS_PHY : R/W; bitpos: [6]; default: 0;
- *  Configures usb_otg_fs_phy registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_USB_OTG_FS_PHY    (BIT(6))
-#define TEE_WRITE_REE1_USB_OTG_FS_PHY_M  (TEE_WRITE_REE1_USB_OTG_FS_PHY_V << TEE_WRITE_REE1_USB_OTG_FS_PHY_S)
-#define TEE_WRITE_REE1_USB_OTG_FS_PHY_V  0x00000001U
-#define TEE_WRITE_REE1_USB_OTG_FS_PHY_S  6
-/** TEE_WRITE_REE2_USB_OTG_FS_PHY : R/W; bitpos: [7]; default: 0;
- *  Configures usb_otg_fs_phy registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_USB_OTG_FS_PHY    (BIT(7))
-#define TEE_WRITE_REE2_USB_OTG_FS_PHY_M  (TEE_WRITE_REE2_USB_OTG_FS_PHY_V << TEE_WRITE_REE2_USB_OTG_FS_PHY_S)
-#define TEE_WRITE_REE2_USB_OTG_FS_PHY_V  0x00000001U
-#define TEE_WRITE_REE2_USB_OTG_FS_PHY_S  7
-
-/** TEE_PVT_MONITOR_CTRL_REG register
- *  pvt_monitor read/write control register
- */
-#define TEE_PVT_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0xf0)
-/** TEE_READ_TEE_PVT_MONITOR : R/W; bitpos: [0]; default: 1;
- *  Configures pvt_monitor registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_PVT_MONITOR    (BIT(0))
-#define TEE_READ_TEE_PVT_MONITOR_M  (TEE_READ_TEE_PVT_MONITOR_V << TEE_READ_TEE_PVT_MONITOR_S)
-#define TEE_READ_TEE_PVT_MONITOR_V  0x00000001U
-#define TEE_READ_TEE_PVT_MONITOR_S  0
-/** TEE_READ_REE0_PVT_MONITOR : R/W; bitpos: [1]; default: 0;
- *  Configures pvt_monitor registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_PVT_MONITOR    (BIT(1))
-#define TEE_READ_REE0_PVT_MONITOR_M  (TEE_READ_REE0_PVT_MONITOR_V << TEE_READ_REE0_PVT_MONITOR_S)
-#define TEE_READ_REE0_PVT_MONITOR_V  0x00000001U
-#define TEE_READ_REE0_PVT_MONITOR_S  1
-/** TEE_READ_REE1_PVT_MONITOR : R/W; bitpos: [2]; default: 0;
- *  Configures pvt_monitor registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_PVT_MONITOR    (BIT(2))
-#define TEE_READ_REE1_PVT_MONITOR_M  (TEE_READ_REE1_PVT_MONITOR_V << TEE_READ_REE1_PVT_MONITOR_S)
-#define TEE_READ_REE1_PVT_MONITOR_V  0x00000001U
-#define TEE_READ_REE1_PVT_MONITOR_S  2
-/** TEE_READ_REE2_PVT_MONITOR : R/W; bitpos: [3]; default: 0;
- *  Configures pvt_monitor registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_PVT_MONITOR    (BIT(3))
-#define TEE_READ_REE2_PVT_MONITOR_M  (TEE_READ_REE2_PVT_MONITOR_V << TEE_READ_REE2_PVT_MONITOR_S)
-#define TEE_READ_REE2_PVT_MONITOR_V  0x00000001U
-#define TEE_READ_REE2_PVT_MONITOR_S  3
-/** TEE_WRITE_TEE_PVT_MONITOR : R/W; bitpos: [4]; default: 1;
- *  Configures pvt_monitor registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_PVT_MONITOR    (BIT(4))
-#define TEE_WRITE_TEE_PVT_MONITOR_M  (TEE_WRITE_TEE_PVT_MONITOR_V << TEE_WRITE_TEE_PVT_MONITOR_S)
-#define TEE_WRITE_TEE_PVT_MONITOR_V  0x00000001U
-#define TEE_WRITE_TEE_PVT_MONITOR_S  4
-/** TEE_WRITE_REE0_PVT_MONITOR : R/W; bitpos: [5]; default: 0;
- *  Configures pvt_monitor registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_PVT_MONITOR    (BIT(5))
-#define TEE_WRITE_REE0_PVT_MONITOR_M  (TEE_WRITE_REE0_PVT_MONITOR_V << TEE_WRITE_REE0_PVT_MONITOR_S)
-#define TEE_WRITE_REE0_PVT_MONITOR_V  0x00000001U
-#define TEE_WRITE_REE0_PVT_MONITOR_S  5
-/** TEE_WRITE_REE1_PVT_MONITOR : R/W; bitpos: [6]; default: 0;
- *  Configures pvt_monitor registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_PVT_MONITOR    (BIT(6))
-#define TEE_WRITE_REE1_PVT_MONITOR_M  (TEE_WRITE_REE1_PVT_MONITOR_V << TEE_WRITE_REE1_PVT_MONITOR_S)
-#define TEE_WRITE_REE1_PVT_MONITOR_V  0x00000001U
-#define TEE_WRITE_REE1_PVT_MONITOR_S  6
-/** TEE_WRITE_REE2_PVT_MONITOR : R/W; bitpos: [7]; default: 0;
- *  Configures pvt_monitor registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_PVT_MONITOR    (BIT(7))
-#define TEE_WRITE_REE2_PVT_MONITOR_M  (TEE_WRITE_REE2_PVT_MONITOR_V << TEE_WRITE_REE2_PVT_MONITOR_S)
-#define TEE_WRITE_REE2_PVT_MONITOR_V  0x00000001U
-#define TEE_WRITE_REE2_PVT_MONITOR_S  7
-
-/** TEE_PCNT_CTRL_REG register
- *  pcnt read/write control register
- */
-#define TEE_PCNT_CTRL_REG (DR_REG_TEE_BASE + 0xf4)
-/** TEE_READ_TEE_PCNT : R/W; bitpos: [0]; default: 1;
- *  Configures pcnt registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_PCNT    (BIT(0))
-#define TEE_READ_TEE_PCNT_M  (TEE_READ_TEE_PCNT_V << TEE_READ_TEE_PCNT_S)
-#define TEE_READ_TEE_PCNT_V  0x00000001U
-#define TEE_READ_TEE_PCNT_S  0
-/** TEE_READ_REE0_PCNT : R/W; bitpos: [1]; default: 0;
- *  Configures pcnt registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_PCNT    (BIT(1))
-#define TEE_READ_REE0_PCNT_M  (TEE_READ_REE0_PCNT_V << TEE_READ_REE0_PCNT_S)
-#define TEE_READ_REE0_PCNT_V  0x00000001U
-#define TEE_READ_REE0_PCNT_S  1
-/** TEE_READ_REE1_PCNT : R/W; bitpos: [2]; default: 0;
- *  Configures pcnt registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_PCNT    (BIT(2))
-#define TEE_READ_REE1_PCNT_M  (TEE_READ_REE1_PCNT_V << TEE_READ_REE1_PCNT_S)
-#define TEE_READ_REE1_PCNT_V  0x00000001U
-#define TEE_READ_REE1_PCNT_S  2
-/** TEE_READ_REE2_PCNT : R/W; bitpos: [3]; default: 0;
- *  Configures pcnt registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_PCNT    (BIT(3))
-#define TEE_READ_REE2_PCNT_M  (TEE_READ_REE2_PCNT_V << TEE_READ_REE2_PCNT_S)
-#define TEE_READ_REE2_PCNT_V  0x00000001U
-#define TEE_READ_REE2_PCNT_S  3
-/** TEE_WRITE_TEE_PCNT : R/W; bitpos: [4]; default: 1;
- *  Configures pcnt registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_PCNT    (BIT(4))
-#define TEE_WRITE_TEE_PCNT_M  (TEE_WRITE_TEE_PCNT_V << TEE_WRITE_TEE_PCNT_S)
-#define TEE_WRITE_TEE_PCNT_V  0x00000001U
-#define TEE_WRITE_TEE_PCNT_S  4
-/** TEE_WRITE_REE0_PCNT : R/W; bitpos: [5]; default: 0;
- *  Configures pcnt registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_PCNT    (BIT(5))
-#define TEE_WRITE_REE0_PCNT_M  (TEE_WRITE_REE0_PCNT_V << TEE_WRITE_REE0_PCNT_S)
-#define TEE_WRITE_REE0_PCNT_V  0x00000001U
-#define TEE_WRITE_REE0_PCNT_S  5
-/** TEE_WRITE_REE1_PCNT : R/W; bitpos: [6]; default: 0;
- *  Configures pcnt registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_PCNT    (BIT(6))
-#define TEE_WRITE_REE1_PCNT_M  (TEE_WRITE_REE1_PCNT_V << TEE_WRITE_REE1_PCNT_S)
-#define TEE_WRITE_REE1_PCNT_V  0x00000001U
-#define TEE_WRITE_REE1_PCNT_S  6
-/** TEE_WRITE_REE2_PCNT : R/W; bitpos: [7]; default: 0;
- *  Configures pcnt registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_PCNT    (BIT(7))
-#define TEE_WRITE_REE2_PCNT_M  (TEE_WRITE_REE2_PCNT_V << TEE_WRITE_REE2_PCNT_S)
-#define TEE_WRITE_REE2_PCNT_V  0x00000001U
-#define TEE_WRITE_REE2_PCNT_S  7
-
-/** TEE_IOMUX_CTRL_REG register
- *  iomux read/write control register
- */
-#define TEE_IOMUX_CTRL_REG (DR_REG_TEE_BASE + 0xf8)
-/** TEE_READ_TEE_IOMUX : R/W; bitpos: [0]; default: 1;
- *  Configures iomux registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_IOMUX    (BIT(0))
-#define TEE_READ_TEE_IOMUX_M  (TEE_READ_TEE_IOMUX_V << TEE_READ_TEE_IOMUX_S)
-#define TEE_READ_TEE_IOMUX_V  0x00000001U
-#define TEE_READ_TEE_IOMUX_S  0
-/** TEE_READ_REE0_IOMUX : R/W; bitpos: [1]; default: 0;
- *  Configures iomux registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_IOMUX    (BIT(1))
-#define TEE_READ_REE0_IOMUX_M  (TEE_READ_REE0_IOMUX_V << TEE_READ_REE0_IOMUX_S)
-#define TEE_READ_REE0_IOMUX_V  0x00000001U
-#define TEE_READ_REE0_IOMUX_S  1
-/** TEE_READ_REE1_IOMUX : R/W; bitpos: [2]; default: 0;
- *  Configures iomux registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_IOMUX    (BIT(2))
-#define TEE_READ_REE1_IOMUX_M  (TEE_READ_REE1_IOMUX_V << TEE_READ_REE1_IOMUX_S)
-#define TEE_READ_REE1_IOMUX_V  0x00000001U
-#define TEE_READ_REE1_IOMUX_S  2
-/** TEE_READ_REE2_IOMUX : R/W; bitpos: [3]; default: 0;
- *  Configures iomux registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_IOMUX    (BIT(3))
-#define TEE_READ_REE2_IOMUX_M  (TEE_READ_REE2_IOMUX_V << TEE_READ_REE2_IOMUX_S)
-#define TEE_READ_REE2_IOMUX_V  0x00000001U
-#define TEE_READ_REE2_IOMUX_S  3
-/** TEE_WRITE_TEE_IOMUX : R/W; bitpos: [4]; default: 1;
- *  Configures iomux registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_IOMUX    (BIT(4))
-#define TEE_WRITE_TEE_IOMUX_M  (TEE_WRITE_TEE_IOMUX_V << TEE_WRITE_TEE_IOMUX_S)
-#define TEE_WRITE_TEE_IOMUX_V  0x00000001U
-#define TEE_WRITE_TEE_IOMUX_S  4
-/** TEE_WRITE_REE0_IOMUX : R/W; bitpos: [5]; default: 0;
- *  Configures iomux registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_IOMUX    (BIT(5))
-#define TEE_WRITE_REE0_IOMUX_M  (TEE_WRITE_REE0_IOMUX_V << TEE_WRITE_REE0_IOMUX_S)
-#define TEE_WRITE_REE0_IOMUX_V  0x00000001U
-#define TEE_WRITE_REE0_IOMUX_S  5
-/** TEE_WRITE_REE1_IOMUX : R/W; bitpos: [6]; default: 0;
- *  Configures iomux registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_IOMUX    (BIT(6))
-#define TEE_WRITE_REE1_IOMUX_M  (TEE_WRITE_REE1_IOMUX_V << TEE_WRITE_REE1_IOMUX_S)
-#define TEE_WRITE_REE1_IOMUX_V  0x00000001U
-#define TEE_WRITE_REE1_IOMUX_S  6
-/** TEE_WRITE_REE2_IOMUX : R/W; bitpos: [7]; default: 0;
- *  Configures iomux registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_IOMUX    (BIT(7))
-#define TEE_WRITE_REE2_IOMUX_M  (TEE_WRITE_REE2_IOMUX_V << TEE_WRITE_REE2_IOMUX_S)
-#define TEE_WRITE_REE2_IOMUX_V  0x00000001U
-#define TEE_WRITE_REE2_IOMUX_S  7
-
-/** TEE_PSRAM_MEM_MONITOR_CTRL_REG register
- *  psram_mem_monitor read/write control register
- */
-#define TEE_PSRAM_MEM_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0xfc)
-/** TEE_READ_TEE_PSRAM_MEM_MONITOR : R/W; bitpos: [0]; default: 1;
- *  Configures psram_mem_monitor registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_PSRAM_MEM_MONITOR    (BIT(0))
-#define TEE_READ_TEE_PSRAM_MEM_MONITOR_M  (TEE_READ_TEE_PSRAM_MEM_MONITOR_V << TEE_READ_TEE_PSRAM_MEM_MONITOR_S)
-#define TEE_READ_TEE_PSRAM_MEM_MONITOR_V  0x00000001U
-#define TEE_READ_TEE_PSRAM_MEM_MONITOR_S  0
-/** TEE_READ_REE0_PSRAM_MEM_MONITOR : R/W; bitpos: [1]; default: 0;
- *  Configures psram_mem_monitor registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_PSRAM_MEM_MONITOR    (BIT(1))
-#define TEE_READ_REE0_PSRAM_MEM_MONITOR_M  (TEE_READ_REE0_PSRAM_MEM_MONITOR_V << TEE_READ_REE0_PSRAM_MEM_MONITOR_S)
-#define TEE_READ_REE0_PSRAM_MEM_MONITOR_V  0x00000001U
-#define TEE_READ_REE0_PSRAM_MEM_MONITOR_S  1
-/** TEE_READ_REE1_PSRAM_MEM_MONITOR : R/W; bitpos: [2]; default: 0;
- *  Configures psram_mem_monitor registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_PSRAM_MEM_MONITOR    (BIT(2))
-#define TEE_READ_REE1_PSRAM_MEM_MONITOR_M  (TEE_READ_REE1_PSRAM_MEM_MONITOR_V << TEE_READ_REE1_PSRAM_MEM_MONITOR_S)
-#define TEE_READ_REE1_PSRAM_MEM_MONITOR_V  0x00000001U
-#define TEE_READ_REE1_PSRAM_MEM_MONITOR_S  2
-/** TEE_READ_REE2_PSRAM_MEM_MONITOR : R/W; bitpos: [3]; default: 0;
- *  Configures psram_mem_monitor registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_PSRAM_MEM_MONITOR    (BIT(3))
-#define TEE_READ_REE2_PSRAM_MEM_MONITOR_M  (TEE_READ_REE2_PSRAM_MEM_MONITOR_V << TEE_READ_REE2_PSRAM_MEM_MONITOR_S)
-#define TEE_READ_REE2_PSRAM_MEM_MONITOR_V  0x00000001U
-#define TEE_READ_REE2_PSRAM_MEM_MONITOR_S  3
-/** TEE_WRITE_TEE_PSRAM_MEM_MONITOR : R/W; bitpos: [4]; default: 1;
- *  Configures psram_mem_monitor registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR    (BIT(4))
-#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR_M  (TEE_WRITE_TEE_PSRAM_MEM_MONITOR_V << TEE_WRITE_TEE_PSRAM_MEM_MONITOR_S)
-#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR_V  0x00000001U
-#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR_S  4
-/** TEE_WRITE_REE0_PSRAM_MEM_MONITOR : R/W; bitpos: [5]; default: 0;
- *  Configures psram_mem_monitor registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR    (BIT(5))
-#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR_M  (TEE_WRITE_REE0_PSRAM_MEM_MONITOR_V << TEE_WRITE_REE0_PSRAM_MEM_MONITOR_S)
-#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR_V  0x00000001U
-#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR_S  5
-/** TEE_WRITE_REE1_PSRAM_MEM_MONITOR : R/W; bitpos: [6]; default: 0;
- *  Configures psram_mem_monitor registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR    (BIT(6))
-#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR_M  (TEE_WRITE_REE1_PSRAM_MEM_MONITOR_V << TEE_WRITE_REE1_PSRAM_MEM_MONITOR_S)
-#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR_V  0x00000001U
-#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR_S  6
-/** TEE_WRITE_REE2_PSRAM_MEM_MONITOR : R/W; bitpos: [7]; default: 0;
- *  Configures psram_mem_monitor registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR    (BIT(7))
-#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_M  (TEE_WRITE_REE2_PSRAM_MEM_MONITOR_V << TEE_WRITE_REE2_PSRAM_MEM_MONITOR_S)
-#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_V  0x00000001U
-#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_S  7
-
-/** TEE_MEM_ACS_MONITOR_CTRL_REG register
- *  mem_acs_monitor read/write control register
- */
-#define TEE_MEM_ACS_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0x100)
-/** TEE_READ_TEE_MEM_ACS_MONITOR : R/W; bitpos: [0]; default: 1;
- *  Configures mem_acs_monitor registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_MEM_ACS_MONITOR    (BIT(0))
-#define TEE_READ_TEE_MEM_ACS_MONITOR_M  (TEE_READ_TEE_MEM_ACS_MONITOR_V << TEE_READ_TEE_MEM_ACS_MONITOR_S)
-#define TEE_READ_TEE_MEM_ACS_MONITOR_V  0x00000001U
-#define TEE_READ_TEE_MEM_ACS_MONITOR_S  0
-/** TEE_READ_REE0_MEM_ACS_MONITOR : R/W; bitpos: [1]; default: 0;
- *  Configures mem_acs_monitor registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_MEM_ACS_MONITOR    (BIT(1))
-#define TEE_READ_REE0_MEM_ACS_MONITOR_M  (TEE_READ_REE0_MEM_ACS_MONITOR_V << TEE_READ_REE0_MEM_ACS_MONITOR_S)
-#define TEE_READ_REE0_MEM_ACS_MONITOR_V  0x00000001U
-#define TEE_READ_REE0_MEM_ACS_MONITOR_S  1
-/** TEE_READ_REE1_MEM_ACS_MONITOR : R/W; bitpos: [2]; default: 0;
- *  Configures mem_acs_monitor registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_MEM_ACS_MONITOR    (BIT(2))
-#define TEE_READ_REE1_MEM_ACS_MONITOR_M  (TEE_READ_REE1_MEM_ACS_MONITOR_V << TEE_READ_REE1_MEM_ACS_MONITOR_S)
-#define TEE_READ_REE1_MEM_ACS_MONITOR_V  0x00000001U
-#define TEE_READ_REE1_MEM_ACS_MONITOR_S  2
-/** TEE_READ_REE2_MEM_ACS_MONITOR : R/W; bitpos: [3]; default: 0;
- *  Configures mem_acs_monitor registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_MEM_ACS_MONITOR    (BIT(3))
-#define TEE_READ_REE2_MEM_ACS_MONITOR_M  (TEE_READ_REE2_MEM_ACS_MONITOR_V << TEE_READ_REE2_MEM_ACS_MONITOR_S)
-#define TEE_READ_REE2_MEM_ACS_MONITOR_V  0x00000001U
-#define TEE_READ_REE2_MEM_ACS_MONITOR_S  3
-/** TEE_WRITE_TEE_MEM_ACS_MONITOR : R/W; bitpos: [4]; default: 1;
- *  Configures mem_acs_monitor registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_MEM_ACS_MONITOR    (BIT(4))
-#define TEE_WRITE_TEE_MEM_ACS_MONITOR_M  (TEE_WRITE_TEE_MEM_ACS_MONITOR_V << TEE_WRITE_TEE_MEM_ACS_MONITOR_S)
-#define TEE_WRITE_TEE_MEM_ACS_MONITOR_V  0x00000001U
-#define TEE_WRITE_TEE_MEM_ACS_MONITOR_S  4
-/** TEE_WRITE_REE0_MEM_ACS_MONITOR : R/W; bitpos: [5]; default: 0;
- *  Configures mem_acs_monitor registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_MEM_ACS_MONITOR    (BIT(5))
-#define TEE_WRITE_REE0_MEM_ACS_MONITOR_M  (TEE_WRITE_REE0_MEM_ACS_MONITOR_V << TEE_WRITE_REE0_MEM_ACS_MONITOR_S)
-#define TEE_WRITE_REE0_MEM_ACS_MONITOR_V  0x00000001U
-#define TEE_WRITE_REE0_MEM_ACS_MONITOR_S  5
-/** TEE_WRITE_REE1_MEM_ACS_MONITOR : R/W; bitpos: [6]; default: 0;
- *  Configures mem_acs_monitor registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_MEM_ACS_MONITOR    (BIT(6))
-#define TEE_WRITE_REE1_MEM_ACS_MONITOR_M  (TEE_WRITE_REE1_MEM_ACS_MONITOR_V << TEE_WRITE_REE1_MEM_ACS_MONITOR_S)
-#define TEE_WRITE_REE1_MEM_ACS_MONITOR_V  0x00000001U
-#define TEE_WRITE_REE1_MEM_ACS_MONITOR_S  6
-/** TEE_WRITE_REE2_MEM_ACS_MONITOR : R/W; bitpos: [7]; default: 0;
- *  Configures mem_acs_monitor registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_MEM_ACS_MONITOR    (BIT(7))
-#define TEE_WRITE_REE2_MEM_ACS_MONITOR_M  (TEE_WRITE_REE2_MEM_ACS_MONITOR_V << TEE_WRITE_REE2_MEM_ACS_MONITOR_S)
-#define TEE_WRITE_REE2_MEM_ACS_MONITOR_V  0x00000001U
-#define TEE_WRITE_REE2_MEM_ACS_MONITOR_S  7
-
-/** TEE_HP_SYSTEM_REG_CTRL_REG register
- *  hp_system_reg read/write control register
- */
-#define TEE_HP_SYSTEM_REG_CTRL_REG (DR_REG_TEE_BASE + 0x104)
-/** TEE_READ_TEE_HP_SYSTEM_REG : R/W; bitpos: [0]; default: 1;
- *  Configures hp_system_reg registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_HP_SYSTEM_REG    (BIT(0))
-#define TEE_READ_TEE_HP_SYSTEM_REG_M  (TEE_READ_TEE_HP_SYSTEM_REG_V << TEE_READ_TEE_HP_SYSTEM_REG_S)
-#define TEE_READ_TEE_HP_SYSTEM_REG_V  0x00000001U
-#define TEE_READ_TEE_HP_SYSTEM_REG_S  0
-/** TEE_READ_REE0_HP_SYSTEM_REG : R/W; bitpos: [1]; default: 0;
- *  Configures hp_system_reg registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_HP_SYSTEM_REG    (BIT(1))
-#define TEE_READ_REE0_HP_SYSTEM_REG_M  (TEE_READ_REE0_HP_SYSTEM_REG_V << TEE_READ_REE0_HP_SYSTEM_REG_S)
-#define TEE_READ_REE0_HP_SYSTEM_REG_V  0x00000001U
-#define TEE_READ_REE0_HP_SYSTEM_REG_S  1
-/** TEE_READ_REE1_HP_SYSTEM_REG : R/W; bitpos: [2]; default: 0;
- *  Configures hp_system_reg registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_HP_SYSTEM_REG    (BIT(2))
-#define TEE_READ_REE1_HP_SYSTEM_REG_M  (TEE_READ_REE1_HP_SYSTEM_REG_V << TEE_READ_REE1_HP_SYSTEM_REG_S)
-#define TEE_READ_REE1_HP_SYSTEM_REG_V  0x00000001U
-#define TEE_READ_REE1_HP_SYSTEM_REG_S  2
-/** TEE_READ_REE2_HP_SYSTEM_REG : R/W; bitpos: [3]; default: 0;
- *  Configures hp_system_reg registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_HP_SYSTEM_REG    (BIT(3))
-#define TEE_READ_REE2_HP_SYSTEM_REG_M  (TEE_READ_REE2_HP_SYSTEM_REG_V << TEE_READ_REE2_HP_SYSTEM_REG_S)
-#define TEE_READ_REE2_HP_SYSTEM_REG_V  0x00000001U
-#define TEE_READ_REE2_HP_SYSTEM_REG_S  3
-/** TEE_WRITE_TEE_HP_SYSTEM_REG : R/W; bitpos: [4]; default: 1;
- *  Configures hp_system_reg registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_HP_SYSTEM_REG    (BIT(4))
-#define TEE_WRITE_TEE_HP_SYSTEM_REG_M  (TEE_WRITE_TEE_HP_SYSTEM_REG_V << TEE_WRITE_TEE_HP_SYSTEM_REG_S)
-#define TEE_WRITE_TEE_HP_SYSTEM_REG_V  0x00000001U
-#define TEE_WRITE_TEE_HP_SYSTEM_REG_S  4
-/** TEE_WRITE_REE0_HP_SYSTEM_REG : R/W; bitpos: [5]; default: 0;
- *  Configures hp_system_reg registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_HP_SYSTEM_REG    (BIT(5))
-#define TEE_WRITE_REE0_HP_SYSTEM_REG_M  (TEE_WRITE_REE0_HP_SYSTEM_REG_V << TEE_WRITE_REE0_HP_SYSTEM_REG_S)
-#define TEE_WRITE_REE0_HP_SYSTEM_REG_V  0x00000001U
-#define TEE_WRITE_REE0_HP_SYSTEM_REG_S  5
-/** TEE_WRITE_REE1_HP_SYSTEM_REG : R/W; bitpos: [6]; default: 0;
- *  Configures hp_system_reg registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_HP_SYSTEM_REG    (BIT(6))
-#define TEE_WRITE_REE1_HP_SYSTEM_REG_M  (TEE_WRITE_REE1_HP_SYSTEM_REG_V << TEE_WRITE_REE1_HP_SYSTEM_REG_S)
-#define TEE_WRITE_REE1_HP_SYSTEM_REG_V  0x00000001U
-#define TEE_WRITE_REE1_HP_SYSTEM_REG_S  6
-/** TEE_WRITE_REE2_HP_SYSTEM_REG : R/W; bitpos: [7]; default: 0;
- *  Configures hp_system_reg registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_HP_SYSTEM_REG    (BIT(7))
-#define TEE_WRITE_REE2_HP_SYSTEM_REG_M  (TEE_WRITE_REE2_HP_SYSTEM_REG_V << TEE_WRITE_REE2_HP_SYSTEM_REG_S)
-#define TEE_WRITE_REE2_HP_SYSTEM_REG_V  0x00000001U
-#define TEE_WRITE_REE2_HP_SYSTEM_REG_S  7
-
-/** TEE_PCR_REG_CTRL_REG register
- *  pcr_reg read/write control register
- */
-#define TEE_PCR_REG_CTRL_REG (DR_REG_TEE_BASE + 0x108)
-/** TEE_READ_TEE_PCR_REG : R/W; bitpos: [0]; default: 1;
- *  Configures pcr_reg registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_PCR_REG    (BIT(0))
-#define TEE_READ_TEE_PCR_REG_M  (TEE_READ_TEE_PCR_REG_V << TEE_READ_TEE_PCR_REG_S)
-#define TEE_READ_TEE_PCR_REG_V  0x00000001U
-#define TEE_READ_TEE_PCR_REG_S  0
-/** TEE_READ_REE0_PCR_REG : R/W; bitpos: [1]; default: 0;
- *  Configures pcr_reg registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_PCR_REG    (BIT(1))
-#define TEE_READ_REE0_PCR_REG_M  (TEE_READ_REE0_PCR_REG_V << TEE_READ_REE0_PCR_REG_S)
-#define TEE_READ_REE0_PCR_REG_V  0x00000001U
-#define TEE_READ_REE0_PCR_REG_S  1
-/** TEE_READ_REE1_PCR_REG : R/W; bitpos: [2]; default: 0;
- *  Configures pcr_reg registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_PCR_REG    (BIT(2))
-#define TEE_READ_REE1_PCR_REG_M  (TEE_READ_REE1_PCR_REG_V << TEE_READ_REE1_PCR_REG_S)
-#define TEE_READ_REE1_PCR_REG_V  0x00000001U
-#define TEE_READ_REE1_PCR_REG_S  2
-/** TEE_READ_REE2_PCR_REG : R/W; bitpos: [3]; default: 0;
- *  Configures pcr_reg registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_PCR_REG    (BIT(3))
-#define TEE_READ_REE2_PCR_REG_M  (TEE_READ_REE2_PCR_REG_V << TEE_READ_REE2_PCR_REG_S)
-#define TEE_READ_REE2_PCR_REG_V  0x00000001U
-#define TEE_READ_REE2_PCR_REG_S  3
-/** TEE_WRITE_TEE_PCR_REG : R/W; bitpos: [4]; default: 1;
- *  Configures pcr_reg registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_PCR_REG    (BIT(4))
-#define TEE_WRITE_TEE_PCR_REG_M  (TEE_WRITE_TEE_PCR_REG_V << TEE_WRITE_TEE_PCR_REG_S)
-#define TEE_WRITE_TEE_PCR_REG_V  0x00000001U
-#define TEE_WRITE_TEE_PCR_REG_S  4
-/** TEE_WRITE_REE0_PCR_REG : R/W; bitpos: [5]; default: 0;
- *  Configures pcr_reg registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_PCR_REG    (BIT(5))
-#define TEE_WRITE_REE0_PCR_REG_M  (TEE_WRITE_REE0_PCR_REG_V << TEE_WRITE_REE0_PCR_REG_S)
-#define TEE_WRITE_REE0_PCR_REG_V  0x00000001U
-#define TEE_WRITE_REE0_PCR_REG_S  5
-/** TEE_WRITE_REE1_PCR_REG : R/W; bitpos: [6]; default: 0;
- *  Configures pcr_reg registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_PCR_REG    (BIT(6))
-#define TEE_WRITE_REE1_PCR_REG_M  (TEE_WRITE_REE1_PCR_REG_V << TEE_WRITE_REE1_PCR_REG_S)
-#define TEE_WRITE_REE1_PCR_REG_V  0x00000001U
-#define TEE_WRITE_REE1_PCR_REG_S  6
-/** TEE_WRITE_REE2_PCR_REG : R/W; bitpos: [7]; default: 0;
- *  Configures pcr_reg registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_PCR_REG    (BIT(7))
-#define TEE_WRITE_REE2_PCR_REG_M  (TEE_WRITE_REE2_PCR_REG_V << TEE_WRITE_REE2_PCR_REG_S)
-#define TEE_WRITE_REE2_PCR_REG_V  0x00000001U
-#define TEE_WRITE_REE2_PCR_REG_S  7
-
-/** TEE_MSPI_CTRL_REG register
- *  mspi read/write control register
- */
-#define TEE_MSPI_CTRL_REG (DR_REG_TEE_BASE + 0x10c)
-/** TEE_READ_TEE_MSPI : R/W; bitpos: [0]; default: 1;
- *  Configures mspi registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_MSPI    (BIT(0))
-#define TEE_READ_TEE_MSPI_M  (TEE_READ_TEE_MSPI_V << TEE_READ_TEE_MSPI_S)
-#define TEE_READ_TEE_MSPI_V  0x00000001U
-#define TEE_READ_TEE_MSPI_S  0
-/** TEE_READ_REE0_MSPI : R/W; bitpos: [1]; default: 0;
- *  Configures mspi registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_MSPI    (BIT(1))
-#define TEE_READ_REE0_MSPI_M  (TEE_READ_REE0_MSPI_V << TEE_READ_REE0_MSPI_S)
-#define TEE_READ_REE0_MSPI_V  0x00000001U
-#define TEE_READ_REE0_MSPI_S  1
-/** TEE_READ_REE1_MSPI : R/W; bitpos: [2]; default: 0;
- *  Configures mspi registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_MSPI    (BIT(2))
-#define TEE_READ_REE1_MSPI_M  (TEE_READ_REE1_MSPI_V << TEE_READ_REE1_MSPI_S)
-#define TEE_READ_REE1_MSPI_V  0x00000001U
-#define TEE_READ_REE1_MSPI_S  2
-/** TEE_READ_REE2_MSPI : R/W; bitpos: [3]; default: 0;
- *  Configures mspi registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_MSPI    (BIT(3))
-#define TEE_READ_REE2_MSPI_M  (TEE_READ_REE2_MSPI_V << TEE_READ_REE2_MSPI_S)
-#define TEE_READ_REE2_MSPI_V  0x00000001U
-#define TEE_READ_REE2_MSPI_S  3
-/** TEE_WRITE_TEE_MSPI : R/W; bitpos: [4]; default: 1;
- *  Configures mspi registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_MSPI    (BIT(4))
-#define TEE_WRITE_TEE_MSPI_M  (TEE_WRITE_TEE_MSPI_V << TEE_WRITE_TEE_MSPI_S)
-#define TEE_WRITE_TEE_MSPI_V  0x00000001U
-#define TEE_WRITE_TEE_MSPI_S  4
-/** TEE_WRITE_REE0_MSPI : R/W; bitpos: [5]; default: 0;
- *  Configures mspi registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_MSPI    (BIT(5))
-#define TEE_WRITE_REE0_MSPI_M  (TEE_WRITE_REE0_MSPI_V << TEE_WRITE_REE0_MSPI_S)
-#define TEE_WRITE_REE0_MSPI_V  0x00000001U
-#define TEE_WRITE_REE0_MSPI_S  5
-/** TEE_WRITE_REE1_MSPI : R/W; bitpos: [6]; default: 0;
- *  Configures mspi registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_MSPI    (BIT(6))
-#define TEE_WRITE_REE1_MSPI_M  (TEE_WRITE_REE1_MSPI_V << TEE_WRITE_REE1_MSPI_S)
-#define TEE_WRITE_REE1_MSPI_V  0x00000001U
-#define TEE_WRITE_REE1_MSPI_S  6
-/** TEE_WRITE_REE2_MSPI : R/W; bitpos: [7]; default: 0;
- *  Configures mspi registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_MSPI    (BIT(7))
-#define TEE_WRITE_REE2_MSPI_M  (TEE_WRITE_REE2_MSPI_V << TEE_WRITE_REE2_MSPI_S)
-#define TEE_WRITE_REE2_MSPI_V  0x00000001U
-#define TEE_WRITE_REE2_MSPI_S  7
-
-/** TEE_HP_APM_CTRL_REG register
- *  hp_apm read/write control register
- */
-#define TEE_HP_APM_CTRL_REG (DR_REG_TEE_BASE + 0x110)
-/** TEE_READ_TEE_HP_APM : R/W; bitpos: [0]; default: 1;
- *  Configures hp_apm registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_HP_APM    (BIT(0))
-#define TEE_READ_TEE_HP_APM_M  (TEE_READ_TEE_HP_APM_V << TEE_READ_TEE_HP_APM_S)
-#define TEE_READ_TEE_HP_APM_V  0x00000001U
-#define TEE_READ_TEE_HP_APM_S  0
-/** TEE_READ_REE0_HP_APM : HRO; bitpos: [1]; default: 0;
- *  Configures hp_apm registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_HP_APM    (BIT(1))
-#define TEE_READ_REE0_HP_APM_M  (TEE_READ_REE0_HP_APM_V << TEE_READ_REE0_HP_APM_S)
-#define TEE_READ_REE0_HP_APM_V  0x00000001U
-#define TEE_READ_REE0_HP_APM_S  1
-/** TEE_READ_REE1_HP_APM : HRO; bitpos: [2]; default: 0;
- *  Configures hp_apm registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_HP_APM    (BIT(2))
-#define TEE_READ_REE1_HP_APM_M  (TEE_READ_REE1_HP_APM_V << TEE_READ_REE1_HP_APM_S)
-#define TEE_READ_REE1_HP_APM_V  0x00000001U
-#define TEE_READ_REE1_HP_APM_S  2
-/** TEE_READ_REE2_HP_APM : HRO; bitpos: [3]; default: 0;
- *  Configures hp_apm registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_HP_APM    (BIT(3))
-#define TEE_READ_REE2_HP_APM_M  (TEE_READ_REE2_HP_APM_V << TEE_READ_REE2_HP_APM_S)
-#define TEE_READ_REE2_HP_APM_V  0x00000001U
-#define TEE_READ_REE2_HP_APM_S  3
-/** TEE_WRITE_TEE_HP_APM : R/W; bitpos: [4]; default: 1;
- *  Configures hp_apm registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_HP_APM    (BIT(4))
-#define TEE_WRITE_TEE_HP_APM_M  (TEE_WRITE_TEE_HP_APM_V << TEE_WRITE_TEE_HP_APM_S)
-#define TEE_WRITE_TEE_HP_APM_V  0x00000001U
-#define TEE_WRITE_TEE_HP_APM_S  4
-/** TEE_WRITE_REE0_HP_APM : HRO; bitpos: [5]; default: 0;
- *  Configures hp_apm registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_HP_APM    (BIT(5))
-#define TEE_WRITE_REE0_HP_APM_M  (TEE_WRITE_REE0_HP_APM_V << TEE_WRITE_REE0_HP_APM_S)
-#define TEE_WRITE_REE0_HP_APM_V  0x00000001U
-#define TEE_WRITE_REE0_HP_APM_S  5
-/** TEE_WRITE_REE1_HP_APM : HRO; bitpos: [6]; default: 0;
- *  Configures hp_apm registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_HP_APM    (BIT(6))
-#define TEE_WRITE_REE1_HP_APM_M  (TEE_WRITE_REE1_HP_APM_V << TEE_WRITE_REE1_HP_APM_S)
-#define TEE_WRITE_REE1_HP_APM_V  0x00000001U
-#define TEE_WRITE_REE1_HP_APM_S  6
-/** TEE_WRITE_REE2_HP_APM : HRO; bitpos: [7]; default: 0;
- *  Configures hp_apm registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_HP_APM    (BIT(7))
-#define TEE_WRITE_REE2_HP_APM_M  (TEE_WRITE_REE2_HP_APM_V << TEE_WRITE_REE2_HP_APM_S)
-#define TEE_WRITE_REE2_HP_APM_V  0x00000001U
-#define TEE_WRITE_REE2_HP_APM_S  7
-
-/** TEE_CPU_APM_CTRL_REG register
- *  cpu_apm read/write control register
- */
-#define TEE_CPU_APM_CTRL_REG (DR_REG_TEE_BASE + 0x114)
-/** TEE_READ_TEE_CPU_APM : R/W; bitpos: [0]; default: 1;
- *  Configures cpu_apm registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_CPU_APM    (BIT(0))
-#define TEE_READ_TEE_CPU_APM_M  (TEE_READ_TEE_CPU_APM_V << TEE_READ_TEE_CPU_APM_S)
-#define TEE_READ_TEE_CPU_APM_V  0x00000001U
-#define TEE_READ_TEE_CPU_APM_S  0
-/** TEE_READ_REE0_CPU_APM : HRO; bitpos: [1]; default: 0;
- *  Configures cpu_apm registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_CPU_APM    (BIT(1))
-#define TEE_READ_REE0_CPU_APM_M  (TEE_READ_REE0_CPU_APM_V << TEE_READ_REE0_CPU_APM_S)
-#define TEE_READ_REE0_CPU_APM_V  0x00000001U
-#define TEE_READ_REE0_CPU_APM_S  1
-/** TEE_READ_REE1_CPU_APM : HRO; bitpos: [2]; default: 0;
- *  Configures cpu_apm registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_CPU_APM    (BIT(2))
-#define TEE_READ_REE1_CPU_APM_M  (TEE_READ_REE1_CPU_APM_V << TEE_READ_REE1_CPU_APM_S)
-#define TEE_READ_REE1_CPU_APM_V  0x00000001U
-#define TEE_READ_REE1_CPU_APM_S  2
-/** TEE_READ_REE2_CPU_APM : HRO; bitpos: [3]; default: 0;
- *  Configures cpu_apm registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_CPU_APM    (BIT(3))
-#define TEE_READ_REE2_CPU_APM_M  (TEE_READ_REE2_CPU_APM_V << TEE_READ_REE2_CPU_APM_S)
-#define TEE_READ_REE2_CPU_APM_V  0x00000001U
-#define TEE_READ_REE2_CPU_APM_S  3
-/** TEE_WRITE_TEE_CPU_APM : R/W; bitpos: [4]; default: 1;
- *  Configures cpu_apm registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_CPU_APM    (BIT(4))
-#define TEE_WRITE_TEE_CPU_APM_M  (TEE_WRITE_TEE_CPU_APM_V << TEE_WRITE_TEE_CPU_APM_S)
-#define TEE_WRITE_TEE_CPU_APM_V  0x00000001U
-#define TEE_WRITE_TEE_CPU_APM_S  4
-/** TEE_WRITE_REE0_CPU_APM : HRO; bitpos: [5]; default: 0;
- *  Configures cpu_apm registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_CPU_APM    (BIT(5))
-#define TEE_WRITE_REE0_CPU_APM_M  (TEE_WRITE_REE0_CPU_APM_V << TEE_WRITE_REE0_CPU_APM_S)
-#define TEE_WRITE_REE0_CPU_APM_V  0x00000001U
-#define TEE_WRITE_REE0_CPU_APM_S  5
-/** TEE_WRITE_REE1_CPU_APM : HRO; bitpos: [6]; default: 0;
- *  Configures cpu_apm registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_CPU_APM    (BIT(6))
-#define TEE_WRITE_REE1_CPU_APM_M  (TEE_WRITE_REE1_CPU_APM_V << TEE_WRITE_REE1_CPU_APM_S)
-#define TEE_WRITE_REE1_CPU_APM_V  0x00000001U
-#define TEE_WRITE_REE1_CPU_APM_S  6
-/** TEE_WRITE_REE2_CPU_APM : HRO; bitpos: [7]; default: 0;
- *  Configures cpu_apm registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_CPU_APM    (BIT(7))
-#define TEE_WRITE_REE2_CPU_APM_M  (TEE_WRITE_REE2_CPU_APM_V << TEE_WRITE_REE2_CPU_APM_S)
-#define TEE_WRITE_REE2_CPU_APM_V  0x00000001U
-#define TEE_WRITE_REE2_CPU_APM_S  7
-
-/** TEE_TEE_CTRL_REG register
- *  tee read/write control register
- */
-#define TEE_TEE_CTRL_REG (DR_REG_TEE_BASE + 0x118)
-/** TEE_READ_TEE_TEE : R/W; bitpos: [0]; default: 1;
- *  Configures tee registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_TEE    (BIT(0))
-#define TEE_READ_TEE_TEE_M  (TEE_READ_TEE_TEE_V << TEE_READ_TEE_TEE_S)
-#define TEE_READ_TEE_TEE_V  0x00000001U
-#define TEE_READ_TEE_TEE_S  0
-/** TEE_READ_REE0_TEE : HRO; bitpos: [1]; default: 0;
- *  Configures tee registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_TEE    (BIT(1))
-#define TEE_READ_REE0_TEE_M  (TEE_READ_REE0_TEE_V << TEE_READ_REE0_TEE_S)
-#define TEE_READ_REE0_TEE_V  0x00000001U
-#define TEE_READ_REE0_TEE_S  1
-/** TEE_READ_REE1_TEE : HRO; bitpos: [2]; default: 0;
- *  Configures tee registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_TEE    (BIT(2))
-#define TEE_READ_REE1_TEE_M  (TEE_READ_REE1_TEE_V << TEE_READ_REE1_TEE_S)
-#define TEE_READ_REE1_TEE_V  0x00000001U
-#define TEE_READ_REE1_TEE_S  2
-/** TEE_READ_REE2_TEE : HRO; bitpos: [3]; default: 0;
- *  Configures tee registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_TEE    (BIT(3))
-#define TEE_READ_REE2_TEE_M  (TEE_READ_REE2_TEE_V << TEE_READ_REE2_TEE_S)
-#define TEE_READ_REE2_TEE_V  0x00000001U
-#define TEE_READ_REE2_TEE_S  3
-/** TEE_WRITE_TEE_TEE : R/W; bitpos: [4]; default: 1;
- *  Configures tee registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_TEE    (BIT(4))
-#define TEE_WRITE_TEE_TEE_M  (TEE_WRITE_TEE_TEE_V << TEE_WRITE_TEE_TEE_S)
-#define TEE_WRITE_TEE_TEE_V  0x00000001U
-#define TEE_WRITE_TEE_TEE_S  4
-/** TEE_WRITE_REE0_TEE : HRO; bitpos: [5]; default: 0;
- *  Configures tee registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_TEE    (BIT(5))
-#define TEE_WRITE_REE0_TEE_M  (TEE_WRITE_REE0_TEE_V << TEE_WRITE_REE0_TEE_S)
-#define TEE_WRITE_REE0_TEE_V  0x00000001U
-#define TEE_WRITE_REE0_TEE_S  5
-/** TEE_WRITE_REE1_TEE : HRO; bitpos: [6]; default: 0;
- *  Configures tee registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_TEE    (BIT(6))
-#define TEE_WRITE_REE1_TEE_M  (TEE_WRITE_REE1_TEE_V << TEE_WRITE_REE1_TEE_S)
-#define TEE_WRITE_REE1_TEE_V  0x00000001U
-#define TEE_WRITE_REE1_TEE_S  6
-/** TEE_WRITE_REE2_TEE : HRO; bitpos: [7]; default: 0;
- *  Configures tee registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_TEE    (BIT(7))
-#define TEE_WRITE_REE2_TEE_M  (TEE_WRITE_REE2_TEE_V << TEE_WRITE_REE2_TEE_S)
-#define TEE_WRITE_REE2_TEE_V  0x00000001U
-#define TEE_WRITE_REE2_TEE_S  7
-
-/** TEE_KM_CTRL_REG register
- *  crypt read/write control register
- */
-#define TEE_KM_CTRL_REG (DR_REG_TEE_BASE + 0x11c)
-/** TEE_READ_TEE_KM : R/W; bitpos: [0]; default: 1;
- *  Configures km registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_KM    (BIT(0))
-#define TEE_READ_TEE_KM_M  (TEE_READ_TEE_KM_V << TEE_READ_TEE_KM_S)
-#define TEE_READ_TEE_KM_V  0x00000001U
-#define TEE_READ_TEE_KM_S  0
-/** TEE_READ_REE0_KM : R/W; bitpos: [1]; default: 0;
- *  Configures km registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_KM    (BIT(1))
-#define TEE_READ_REE0_KM_M  (TEE_READ_REE0_KM_V << TEE_READ_REE0_KM_S)
-#define TEE_READ_REE0_KM_V  0x00000001U
-#define TEE_READ_REE0_KM_S  1
-/** TEE_READ_REE1_KM : R/W; bitpos: [2]; default: 0;
- *  Configures km registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_KM    (BIT(2))
-#define TEE_READ_REE1_KM_M  (TEE_READ_REE1_KM_V << TEE_READ_REE1_KM_S)
-#define TEE_READ_REE1_KM_V  0x00000001U
-#define TEE_READ_REE1_KM_S  2
-/** TEE_READ_REE2_KM : R/W; bitpos: [3]; default: 0;
- *  Configures km registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_KM    (BIT(3))
-#define TEE_READ_REE2_KM_M  (TEE_READ_REE2_KM_V << TEE_READ_REE2_KM_S)
-#define TEE_READ_REE2_KM_V  0x00000001U
-#define TEE_READ_REE2_KM_S  3
-/** TEE_WRITE_TEE_KM : R/W; bitpos: [4]; default: 1;
- *  Configures km registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_KM    (BIT(4))
-#define TEE_WRITE_TEE_KM_M  (TEE_WRITE_TEE_KM_V << TEE_WRITE_TEE_KM_S)
-#define TEE_WRITE_TEE_KM_V  0x00000001U
-#define TEE_WRITE_TEE_KM_S  4
-/** TEE_WRITE_REE0_KM : R/W; bitpos: [5]; default: 0;
- *  Configures km registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_KM    (BIT(5))
-#define TEE_WRITE_REE0_KM_M  (TEE_WRITE_REE0_KM_V << TEE_WRITE_REE0_KM_S)
-#define TEE_WRITE_REE0_KM_V  0x00000001U
-#define TEE_WRITE_REE0_KM_S  5
-/** TEE_WRITE_REE1_KM : R/W; bitpos: [6]; default: 0;
- *  Configures km registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_KM    (BIT(6))
-#define TEE_WRITE_REE1_KM_M  (TEE_WRITE_REE1_KM_V << TEE_WRITE_REE1_KM_S)
-#define TEE_WRITE_REE1_KM_V  0x00000001U
-#define TEE_WRITE_REE1_KM_S  6
-/** TEE_WRITE_REE2_KM : R/W; bitpos: [7]; default: 0;
- *  Configures km registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_KM    (BIT(7))
-#define TEE_WRITE_REE2_KM_M  (TEE_WRITE_REE2_KM_V << TEE_WRITE_REE2_KM_S)
-#define TEE_WRITE_REE2_KM_V  0x00000001U
-#define TEE_WRITE_REE2_KM_S  7
-
-/** TEE_CRYPT_CTRL_REG register
- *  crypt read/write control register
- */
-#define TEE_CRYPT_CTRL_REG (DR_REG_TEE_BASE + 0x120)
-/** TEE_READ_TEE_CRYPT : R/W; bitpos: [0]; default: 1;
- *  Configures crypt registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_CRYPT    (BIT(0))
-#define TEE_READ_TEE_CRYPT_M  (TEE_READ_TEE_CRYPT_V << TEE_READ_TEE_CRYPT_S)
-#define TEE_READ_TEE_CRYPT_V  0x00000001U
-#define TEE_READ_TEE_CRYPT_S  0
-/** TEE_READ_REE0_CRYPT : R/W; bitpos: [1]; default: 0;
- *  Configures crypt registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_CRYPT    (BIT(1))
-#define TEE_READ_REE0_CRYPT_M  (TEE_READ_REE0_CRYPT_V << TEE_READ_REE0_CRYPT_S)
-#define TEE_READ_REE0_CRYPT_V  0x00000001U
-#define TEE_READ_REE0_CRYPT_S  1
-/** TEE_READ_REE1_CRYPT : R/W; bitpos: [2]; default: 0;
- *  Configures crypt registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_CRYPT    (BIT(2))
-#define TEE_READ_REE1_CRYPT_M  (TEE_READ_REE1_CRYPT_V << TEE_READ_REE1_CRYPT_S)
-#define TEE_READ_REE1_CRYPT_V  0x00000001U
-#define TEE_READ_REE1_CRYPT_S  2
-/** TEE_READ_REE2_CRYPT : R/W; bitpos: [3]; default: 0;
- *  Configures crypt registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_CRYPT    (BIT(3))
-#define TEE_READ_REE2_CRYPT_M  (TEE_READ_REE2_CRYPT_V << TEE_READ_REE2_CRYPT_S)
-#define TEE_READ_REE2_CRYPT_V  0x00000001U
-#define TEE_READ_REE2_CRYPT_S  3
-/** TEE_WRITE_TEE_CRYPT : R/W; bitpos: [4]; default: 1;
- *  Configures crypt registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_CRYPT    (BIT(4))
-#define TEE_WRITE_TEE_CRYPT_M  (TEE_WRITE_TEE_CRYPT_V << TEE_WRITE_TEE_CRYPT_S)
-#define TEE_WRITE_TEE_CRYPT_V  0x00000001U
-#define TEE_WRITE_TEE_CRYPT_S  4
-/** TEE_WRITE_REE0_CRYPT : R/W; bitpos: [5]; default: 0;
- *  Configures crypt registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_CRYPT    (BIT(5))
-#define TEE_WRITE_REE0_CRYPT_M  (TEE_WRITE_REE0_CRYPT_V << TEE_WRITE_REE0_CRYPT_S)
-#define TEE_WRITE_REE0_CRYPT_V  0x00000001U
-#define TEE_WRITE_REE0_CRYPT_S  5
-/** TEE_WRITE_REE1_CRYPT : R/W; bitpos: [6]; default: 0;
- *  Configures crypt registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_CRYPT    (BIT(6))
-#define TEE_WRITE_REE1_CRYPT_M  (TEE_WRITE_REE1_CRYPT_V << TEE_WRITE_REE1_CRYPT_S)
-#define TEE_WRITE_REE1_CRYPT_V  0x00000001U
-#define TEE_WRITE_REE1_CRYPT_S  6
-/** TEE_WRITE_REE2_CRYPT : R/W; bitpos: [7]; default: 0;
- *  Configures crypt registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_CRYPT    (BIT(7))
-#define TEE_WRITE_REE2_CRYPT_M  (TEE_WRITE_REE2_CRYPT_V << TEE_WRITE_REE2_CRYPT_S)
-#define TEE_WRITE_REE2_CRYPT_V  0x00000001U
-#define TEE_WRITE_REE2_CRYPT_S  7
-
-/** TEE_CORE0_TRACE_CTRL_REG register
- *  core0_trace read/write control register
- */
-#define TEE_CORE0_TRACE_CTRL_REG (DR_REG_TEE_BASE + 0x124)
-/** TEE_READ_TEE_CORE0_TRACE : R/W; bitpos: [0]; default: 1;
- *  Configures core0_trace registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_CORE0_TRACE    (BIT(0))
-#define TEE_READ_TEE_CORE0_TRACE_M  (TEE_READ_TEE_CORE0_TRACE_V << TEE_READ_TEE_CORE0_TRACE_S)
-#define TEE_READ_TEE_CORE0_TRACE_V  0x00000001U
-#define TEE_READ_TEE_CORE0_TRACE_S  0
-/** TEE_READ_REE0_CORE0_TRACE : R/W; bitpos: [1]; default: 0;
- *  Configures core0_trace registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_CORE0_TRACE    (BIT(1))
-#define TEE_READ_REE0_CORE0_TRACE_M  (TEE_READ_REE0_CORE0_TRACE_V << TEE_READ_REE0_CORE0_TRACE_S)
-#define TEE_READ_REE0_CORE0_TRACE_V  0x00000001U
-#define TEE_READ_REE0_CORE0_TRACE_S  1
-/** TEE_READ_REE1_CORE0_TRACE : R/W; bitpos: [2]; default: 0;
- *  Configures core0_trace registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_CORE0_TRACE    (BIT(2))
-#define TEE_READ_REE1_CORE0_TRACE_M  (TEE_READ_REE1_CORE0_TRACE_V << TEE_READ_REE1_CORE0_TRACE_S)
-#define TEE_READ_REE1_CORE0_TRACE_V  0x00000001U
-#define TEE_READ_REE1_CORE0_TRACE_S  2
-/** TEE_READ_REE2_CORE0_TRACE : R/W; bitpos: [3]; default: 0;
- *  Configures core0_trace registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_CORE0_TRACE    (BIT(3))
-#define TEE_READ_REE2_CORE0_TRACE_M  (TEE_READ_REE2_CORE0_TRACE_V << TEE_READ_REE2_CORE0_TRACE_S)
-#define TEE_READ_REE2_CORE0_TRACE_V  0x00000001U
-#define TEE_READ_REE2_CORE0_TRACE_S  3
-/** TEE_WRITE_TEE_CORE0_TRACE : R/W; bitpos: [4]; default: 1;
- *  Configures core0_trace registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_CORE0_TRACE    (BIT(4))
-#define TEE_WRITE_TEE_CORE0_TRACE_M  (TEE_WRITE_TEE_CORE0_TRACE_V << TEE_WRITE_TEE_CORE0_TRACE_S)
-#define TEE_WRITE_TEE_CORE0_TRACE_V  0x00000001U
-#define TEE_WRITE_TEE_CORE0_TRACE_S  4
-/** TEE_WRITE_REE0_CORE0_TRACE : R/W; bitpos: [5]; default: 0;
- *  Configures core0_trace registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_CORE0_TRACE    (BIT(5))
-#define TEE_WRITE_REE0_CORE0_TRACE_M  (TEE_WRITE_REE0_CORE0_TRACE_V << TEE_WRITE_REE0_CORE0_TRACE_S)
-#define TEE_WRITE_REE0_CORE0_TRACE_V  0x00000001U
-#define TEE_WRITE_REE0_CORE0_TRACE_S  5
-/** TEE_WRITE_REE1_CORE0_TRACE : R/W; bitpos: [6]; default: 0;
- *  Configures core0_trace registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_CORE0_TRACE    (BIT(6))
-#define TEE_WRITE_REE1_CORE0_TRACE_M  (TEE_WRITE_REE1_CORE0_TRACE_V << TEE_WRITE_REE1_CORE0_TRACE_S)
-#define TEE_WRITE_REE1_CORE0_TRACE_V  0x00000001U
-#define TEE_WRITE_REE1_CORE0_TRACE_S  6
-/** TEE_WRITE_REE2_CORE0_TRACE : R/W; bitpos: [7]; default: 0;
- *  Configures core0_trace registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_CORE0_TRACE    (BIT(7))
-#define TEE_WRITE_REE2_CORE0_TRACE_M  (TEE_WRITE_REE2_CORE0_TRACE_V << TEE_WRITE_REE2_CORE0_TRACE_S)
-#define TEE_WRITE_REE2_CORE0_TRACE_V  0x00000001U
-#define TEE_WRITE_REE2_CORE0_TRACE_S  7
-
-/** TEE_CORE1_TRACE_CTRL_REG register
- *  core1_trace read/write control register
- */
-#define TEE_CORE1_TRACE_CTRL_REG (DR_REG_TEE_BASE + 0x128)
-/** TEE_READ_TEE_CORE1_TRACE : R/W; bitpos: [0]; default: 1;
- *  Configures core1_trace registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_CORE1_TRACE    (BIT(0))
-#define TEE_READ_TEE_CORE1_TRACE_M  (TEE_READ_TEE_CORE1_TRACE_V << TEE_READ_TEE_CORE1_TRACE_S)
-#define TEE_READ_TEE_CORE1_TRACE_V  0x00000001U
-#define TEE_READ_TEE_CORE1_TRACE_S  0
-/** TEE_READ_REE0_CORE1_TRACE : R/W; bitpos: [1]; default: 0;
- *  Configures core1_trace registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_CORE1_TRACE    (BIT(1))
-#define TEE_READ_REE0_CORE1_TRACE_M  (TEE_READ_REE0_CORE1_TRACE_V << TEE_READ_REE0_CORE1_TRACE_S)
-#define TEE_READ_REE0_CORE1_TRACE_V  0x00000001U
-#define TEE_READ_REE0_CORE1_TRACE_S  1
-/** TEE_READ_REE1_CORE1_TRACE : R/W; bitpos: [2]; default: 0;
- *  Configures core1_trace registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_CORE1_TRACE    (BIT(2))
-#define TEE_READ_REE1_CORE1_TRACE_M  (TEE_READ_REE1_CORE1_TRACE_V << TEE_READ_REE1_CORE1_TRACE_S)
-#define TEE_READ_REE1_CORE1_TRACE_V  0x00000001U
-#define TEE_READ_REE1_CORE1_TRACE_S  2
-/** TEE_READ_REE2_CORE1_TRACE : R/W; bitpos: [3]; default: 0;
- *  Configures core1_trace registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_CORE1_TRACE    (BIT(3))
-#define TEE_READ_REE2_CORE1_TRACE_M  (TEE_READ_REE2_CORE1_TRACE_V << TEE_READ_REE2_CORE1_TRACE_S)
-#define TEE_READ_REE2_CORE1_TRACE_V  0x00000001U
-#define TEE_READ_REE2_CORE1_TRACE_S  3
-/** TEE_WRITE_TEE_CORE1_TRACE : R/W; bitpos: [4]; default: 1;
- *  Configures core1_trace registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_CORE1_TRACE    (BIT(4))
-#define TEE_WRITE_TEE_CORE1_TRACE_M  (TEE_WRITE_TEE_CORE1_TRACE_V << TEE_WRITE_TEE_CORE1_TRACE_S)
-#define TEE_WRITE_TEE_CORE1_TRACE_V  0x00000001U
-#define TEE_WRITE_TEE_CORE1_TRACE_S  4
-/** TEE_WRITE_REE0_CORE1_TRACE : R/W; bitpos: [5]; default: 0;
- *  Configures core1_trace registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_CORE1_TRACE    (BIT(5))
-#define TEE_WRITE_REE0_CORE1_TRACE_M  (TEE_WRITE_REE0_CORE1_TRACE_V << TEE_WRITE_REE0_CORE1_TRACE_S)
-#define TEE_WRITE_REE0_CORE1_TRACE_V  0x00000001U
-#define TEE_WRITE_REE0_CORE1_TRACE_S  5
-/** TEE_WRITE_REE1_CORE1_TRACE : R/W; bitpos: [6]; default: 0;
- *  Configures core1_trace registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_CORE1_TRACE    (BIT(6))
-#define TEE_WRITE_REE1_CORE1_TRACE_M  (TEE_WRITE_REE1_CORE1_TRACE_V << TEE_WRITE_REE1_CORE1_TRACE_S)
-#define TEE_WRITE_REE1_CORE1_TRACE_V  0x00000001U
-#define TEE_WRITE_REE1_CORE1_TRACE_S  6
-/** TEE_WRITE_REE2_CORE1_TRACE : R/W; bitpos: [7]; default: 0;
- *  Configures core1_trace registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_CORE1_TRACE    (BIT(7))
-#define TEE_WRITE_REE2_CORE1_TRACE_M  (TEE_WRITE_REE2_CORE1_TRACE_V << TEE_WRITE_REE2_CORE1_TRACE_S)
-#define TEE_WRITE_REE2_CORE1_TRACE_V  0x00000001U
-#define TEE_WRITE_REE2_CORE1_TRACE_S  7
-
-/** TEE_CPU_BUS_MONITOR_CTRL_REG register
- *  cpu_bus_monitor read/write control register
- */
-#define TEE_CPU_BUS_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0x12c)
-/** TEE_READ_TEE_CPU_BUS_MONITOR : R/W; bitpos: [0]; default: 1;
- *  Configures cpu_bus_monitor registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_CPU_BUS_MONITOR    (BIT(0))
-#define TEE_READ_TEE_CPU_BUS_MONITOR_M  (TEE_READ_TEE_CPU_BUS_MONITOR_V << TEE_READ_TEE_CPU_BUS_MONITOR_S)
-#define TEE_READ_TEE_CPU_BUS_MONITOR_V  0x00000001U
-#define TEE_READ_TEE_CPU_BUS_MONITOR_S  0
-/** TEE_READ_REE0_CPU_BUS_MONITOR : R/W; bitpos: [1]; default: 0;
- *  Configures cpu_bus_monitor registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_CPU_BUS_MONITOR    (BIT(1))
-#define TEE_READ_REE0_CPU_BUS_MONITOR_M  (TEE_READ_REE0_CPU_BUS_MONITOR_V << TEE_READ_REE0_CPU_BUS_MONITOR_S)
-#define TEE_READ_REE0_CPU_BUS_MONITOR_V  0x00000001U
-#define TEE_READ_REE0_CPU_BUS_MONITOR_S  1
-/** TEE_READ_REE1_CPU_BUS_MONITOR : R/W; bitpos: [2]; default: 0;
- *  Configures cpu_bus_monitor registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_CPU_BUS_MONITOR    (BIT(2))
-#define TEE_READ_REE1_CPU_BUS_MONITOR_M  (TEE_READ_REE1_CPU_BUS_MONITOR_V << TEE_READ_REE1_CPU_BUS_MONITOR_S)
-#define TEE_READ_REE1_CPU_BUS_MONITOR_V  0x00000001U
-#define TEE_READ_REE1_CPU_BUS_MONITOR_S  2
-/** TEE_READ_REE2_CPU_BUS_MONITOR : R/W; bitpos: [3]; default: 0;
- *  Configures cpu_bus_monitor registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_CPU_BUS_MONITOR    (BIT(3))
-#define TEE_READ_REE2_CPU_BUS_MONITOR_M  (TEE_READ_REE2_CPU_BUS_MONITOR_V << TEE_READ_REE2_CPU_BUS_MONITOR_S)
-#define TEE_READ_REE2_CPU_BUS_MONITOR_V  0x00000001U
-#define TEE_READ_REE2_CPU_BUS_MONITOR_S  3
-/** TEE_WRITE_TEE_CPU_BUS_MONITOR : R/W; bitpos: [4]; default: 1;
- *  Configures cpu_bus_monitor registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_CPU_BUS_MONITOR    (BIT(4))
-#define TEE_WRITE_TEE_CPU_BUS_MONITOR_M  (TEE_WRITE_TEE_CPU_BUS_MONITOR_V << TEE_WRITE_TEE_CPU_BUS_MONITOR_S)
-#define TEE_WRITE_TEE_CPU_BUS_MONITOR_V  0x00000001U
-#define TEE_WRITE_TEE_CPU_BUS_MONITOR_S  4
-/** TEE_WRITE_REE0_CPU_BUS_MONITOR : R/W; bitpos: [5]; default: 0;
- *  Configures cpu_bus_monitor registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_CPU_BUS_MONITOR    (BIT(5))
-#define TEE_WRITE_REE0_CPU_BUS_MONITOR_M  (TEE_WRITE_REE0_CPU_BUS_MONITOR_V << TEE_WRITE_REE0_CPU_BUS_MONITOR_S)
-#define TEE_WRITE_REE0_CPU_BUS_MONITOR_V  0x00000001U
-#define TEE_WRITE_REE0_CPU_BUS_MONITOR_S  5
-/** TEE_WRITE_REE1_CPU_BUS_MONITOR : R/W; bitpos: [6]; default: 0;
- *  Configures cpu_bus_monitor registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_CPU_BUS_MONITOR    (BIT(6))
-#define TEE_WRITE_REE1_CPU_BUS_MONITOR_M  (TEE_WRITE_REE1_CPU_BUS_MONITOR_V << TEE_WRITE_REE1_CPU_BUS_MONITOR_S)
-#define TEE_WRITE_REE1_CPU_BUS_MONITOR_V  0x00000001U
-#define TEE_WRITE_REE1_CPU_BUS_MONITOR_S  6
-/** TEE_WRITE_REE2_CPU_BUS_MONITOR : R/W; bitpos: [7]; default: 0;
- *  Configures cpu_bus_monitor registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_CPU_BUS_MONITOR    (BIT(7))
-#define TEE_WRITE_REE2_CPU_BUS_MONITOR_M  (TEE_WRITE_REE2_CPU_BUS_MONITOR_V << TEE_WRITE_REE2_CPU_BUS_MONITOR_S)
-#define TEE_WRITE_REE2_CPU_BUS_MONITOR_V  0x00000001U
-#define TEE_WRITE_REE2_CPU_BUS_MONITOR_S  7
-
-/** TEE_INTPRI_REG_CTRL_REG register
- *  intpri_reg read/write control register
- */
-#define TEE_INTPRI_REG_CTRL_REG (DR_REG_TEE_BASE + 0x130)
-/** TEE_READ_TEE_INTPRI_REG : R/W; bitpos: [0]; default: 1;
- *  Configures intpri_reg registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_INTPRI_REG    (BIT(0))
-#define TEE_READ_TEE_INTPRI_REG_M  (TEE_READ_TEE_INTPRI_REG_V << TEE_READ_TEE_INTPRI_REG_S)
-#define TEE_READ_TEE_INTPRI_REG_V  0x00000001U
-#define TEE_READ_TEE_INTPRI_REG_S  0
-/** TEE_READ_REE0_INTPRI_REG : R/W; bitpos: [1]; default: 0;
- *  Configures intpri_reg registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_INTPRI_REG    (BIT(1))
-#define TEE_READ_REE0_INTPRI_REG_M  (TEE_READ_REE0_INTPRI_REG_V << TEE_READ_REE0_INTPRI_REG_S)
-#define TEE_READ_REE0_INTPRI_REG_V  0x00000001U
-#define TEE_READ_REE0_INTPRI_REG_S  1
-/** TEE_READ_REE1_INTPRI_REG : R/W; bitpos: [2]; default: 0;
- *  Configures intpri_reg registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_INTPRI_REG    (BIT(2))
-#define TEE_READ_REE1_INTPRI_REG_M  (TEE_READ_REE1_INTPRI_REG_V << TEE_READ_REE1_INTPRI_REG_S)
-#define TEE_READ_REE1_INTPRI_REG_V  0x00000001U
-#define TEE_READ_REE1_INTPRI_REG_S  2
-/** TEE_READ_REE2_INTPRI_REG : R/W; bitpos: [3]; default: 0;
- *  Configures intpri_reg registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_INTPRI_REG    (BIT(3))
-#define TEE_READ_REE2_INTPRI_REG_M  (TEE_READ_REE2_INTPRI_REG_V << TEE_READ_REE2_INTPRI_REG_S)
-#define TEE_READ_REE2_INTPRI_REG_V  0x00000001U
-#define TEE_READ_REE2_INTPRI_REG_S  3
-/** TEE_WRITE_TEE_INTPRI_REG : R/W; bitpos: [4]; default: 1;
- *  Configures intpri_reg registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_INTPRI_REG    (BIT(4))
-#define TEE_WRITE_TEE_INTPRI_REG_M  (TEE_WRITE_TEE_INTPRI_REG_V << TEE_WRITE_TEE_INTPRI_REG_S)
-#define TEE_WRITE_TEE_INTPRI_REG_V  0x00000001U
-#define TEE_WRITE_TEE_INTPRI_REG_S  4
-/** TEE_WRITE_REE0_INTPRI_REG : R/W; bitpos: [5]; default: 0;
- *  Configures intpri_reg registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_INTPRI_REG    (BIT(5))
-#define TEE_WRITE_REE0_INTPRI_REG_M  (TEE_WRITE_REE0_INTPRI_REG_V << TEE_WRITE_REE0_INTPRI_REG_S)
-#define TEE_WRITE_REE0_INTPRI_REG_V  0x00000001U
-#define TEE_WRITE_REE0_INTPRI_REG_S  5
-/** TEE_WRITE_REE1_INTPRI_REG : R/W; bitpos: [6]; default: 0;
- *  Configures intpri_reg registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_INTPRI_REG    (BIT(6))
-#define TEE_WRITE_REE1_INTPRI_REG_M  (TEE_WRITE_REE1_INTPRI_REG_V << TEE_WRITE_REE1_INTPRI_REG_S)
-#define TEE_WRITE_REE1_INTPRI_REG_V  0x00000001U
-#define TEE_WRITE_REE1_INTPRI_REG_S  6
-/** TEE_WRITE_REE2_INTPRI_REG : R/W; bitpos: [7]; default: 0;
- *  Configures intpri_reg registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_INTPRI_REG    (BIT(7))
-#define TEE_WRITE_REE2_INTPRI_REG_M  (TEE_WRITE_REE2_INTPRI_REG_V << TEE_WRITE_REE2_INTPRI_REG_S)
-#define TEE_WRITE_REE2_INTPRI_REG_V  0x00000001U
-#define TEE_WRITE_REE2_INTPRI_REG_S  7
-
-/** TEE_CACHE_CFG_CTRL_REG register
- *  cache_cfg read/write control register
- */
-#define TEE_CACHE_CFG_CTRL_REG (DR_REG_TEE_BASE + 0x134)
-/** TEE_READ_TEE_CACHE_CFG : R/W; bitpos: [0]; default: 1;
- *  Configures cache_cfg registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_CACHE_CFG    (BIT(0))
-#define TEE_READ_TEE_CACHE_CFG_M  (TEE_READ_TEE_CACHE_CFG_V << TEE_READ_TEE_CACHE_CFG_S)
-#define TEE_READ_TEE_CACHE_CFG_V  0x00000001U
-#define TEE_READ_TEE_CACHE_CFG_S  0
-/** TEE_READ_REE0_CACHE_CFG : R/W; bitpos: [1]; default: 0;
- *  Configures cache_cfg registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_CACHE_CFG    (BIT(1))
-#define TEE_READ_REE0_CACHE_CFG_M  (TEE_READ_REE0_CACHE_CFG_V << TEE_READ_REE0_CACHE_CFG_S)
-#define TEE_READ_REE0_CACHE_CFG_V  0x00000001U
-#define TEE_READ_REE0_CACHE_CFG_S  1
-/** TEE_READ_REE1_CACHE_CFG : R/W; bitpos: [2]; default: 0;
- *  Configures cache_cfg registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_CACHE_CFG    (BIT(2))
-#define TEE_READ_REE1_CACHE_CFG_M  (TEE_READ_REE1_CACHE_CFG_V << TEE_READ_REE1_CACHE_CFG_S)
-#define TEE_READ_REE1_CACHE_CFG_V  0x00000001U
-#define TEE_READ_REE1_CACHE_CFG_S  2
-/** TEE_READ_REE2_CACHE_CFG : R/W; bitpos: [3]; default: 0;
- *  Configures cache_cfg registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_CACHE_CFG    (BIT(3))
-#define TEE_READ_REE2_CACHE_CFG_M  (TEE_READ_REE2_CACHE_CFG_V << TEE_READ_REE2_CACHE_CFG_S)
-#define TEE_READ_REE2_CACHE_CFG_V  0x00000001U
-#define TEE_READ_REE2_CACHE_CFG_S  3
-/** TEE_WRITE_TEE_CACHE_CFG : R/W; bitpos: [4]; default: 1;
- *  Configures cache_cfg registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_CACHE_CFG    (BIT(4))
-#define TEE_WRITE_TEE_CACHE_CFG_M  (TEE_WRITE_TEE_CACHE_CFG_V << TEE_WRITE_TEE_CACHE_CFG_S)
-#define TEE_WRITE_TEE_CACHE_CFG_V  0x00000001U
-#define TEE_WRITE_TEE_CACHE_CFG_S  4
-/** TEE_WRITE_REE0_CACHE_CFG : R/W; bitpos: [5]; default: 0;
- *  Configures cache_cfg registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_CACHE_CFG    (BIT(5))
-#define TEE_WRITE_REE0_CACHE_CFG_M  (TEE_WRITE_REE0_CACHE_CFG_V << TEE_WRITE_REE0_CACHE_CFG_S)
-#define TEE_WRITE_REE0_CACHE_CFG_V  0x00000001U
-#define TEE_WRITE_REE0_CACHE_CFG_S  5
-/** TEE_WRITE_REE1_CACHE_CFG : R/W; bitpos: [6]; default: 0;
- *  Configures cache_cfg registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_CACHE_CFG    (BIT(6))
-#define TEE_WRITE_REE1_CACHE_CFG_M  (TEE_WRITE_REE1_CACHE_CFG_V << TEE_WRITE_REE1_CACHE_CFG_S)
-#define TEE_WRITE_REE1_CACHE_CFG_V  0x00000001U
-#define TEE_WRITE_REE1_CACHE_CFG_S  6
-/** TEE_WRITE_REE2_CACHE_CFG : R/W; bitpos: [7]; default: 0;
- *  Configures cache_cfg registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_CACHE_CFG    (BIT(7))
-#define TEE_WRITE_REE2_CACHE_CFG_M  (TEE_WRITE_REE2_CACHE_CFG_V << TEE_WRITE_REE2_CACHE_CFG_S)
-#define TEE_WRITE_REE2_CACHE_CFG_V  0x00000001U
-#define TEE_WRITE_REE2_CACHE_CFG_S  7
-
-/** TEE_MODEM_CTRL_REG register
- *  modem read/write control register
- */
-#define TEE_MODEM_CTRL_REG (DR_REG_TEE_BASE + 0x138)
-/** TEE_READ_TEE_MODEM : R/W; bitpos: [0]; default: 1;
- *  Configures modem registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_MODEM    (BIT(0))
-#define TEE_READ_TEE_MODEM_M  (TEE_READ_TEE_MODEM_V << TEE_READ_TEE_MODEM_S)
-#define TEE_READ_TEE_MODEM_V  0x00000001U
-#define TEE_READ_TEE_MODEM_S  0
-/** TEE_READ_REE0_MODEM : R/W; bitpos: [1]; default: 0;
- *  Configures modem registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_MODEM    (BIT(1))
-#define TEE_READ_REE0_MODEM_M  (TEE_READ_REE0_MODEM_V << TEE_READ_REE0_MODEM_S)
-#define TEE_READ_REE0_MODEM_V  0x00000001U
-#define TEE_READ_REE0_MODEM_S  1
-/** TEE_READ_REE1_MODEM : R/W; bitpos: [2]; default: 0;
- *  Configures modem registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_MODEM    (BIT(2))
-#define TEE_READ_REE1_MODEM_M  (TEE_READ_REE1_MODEM_V << TEE_READ_REE1_MODEM_S)
-#define TEE_READ_REE1_MODEM_V  0x00000001U
-#define TEE_READ_REE1_MODEM_S  2
-/** TEE_READ_REE2_MODEM : R/W; bitpos: [3]; default: 0;
- *  Configures modem registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_MODEM    (BIT(3))
-#define TEE_READ_REE2_MODEM_M  (TEE_READ_REE2_MODEM_V << TEE_READ_REE2_MODEM_S)
-#define TEE_READ_REE2_MODEM_V  0x00000001U
-#define TEE_READ_REE2_MODEM_S  3
-/** TEE_WRITE_TEE_MODEM : R/W; bitpos: [4]; default: 1;
- *  Configures modem registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_MODEM    (BIT(4))
-#define TEE_WRITE_TEE_MODEM_M  (TEE_WRITE_TEE_MODEM_V << TEE_WRITE_TEE_MODEM_S)
-#define TEE_WRITE_TEE_MODEM_V  0x00000001U
-#define TEE_WRITE_TEE_MODEM_S  4
-/** TEE_WRITE_REE0_MODEM : R/W; bitpos: [5]; default: 0;
- *  Configures modem registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_MODEM    (BIT(5))
-#define TEE_WRITE_REE0_MODEM_M  (TEE_WRITE_REE0_MODEM_V << TEE_WRITE_REE0_MODEM_S)
-#define TEE_WRITE_REE0_MODEM_V  0x00000001U
-#define TEE_WRITE_REE0_MODEM_S  5
-/** TEE_WRITE_REE1_MODEM : R/W; bitpos: [6]; default: 0;
- *  Configures modem registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_MODEM    (BIT(6))
-#define TEE_WRITE_REE1_MODEM_M  (TEE_WRITE_REE1_MODEM_V << TEE_WRITE_REE1_MODEM_S)
-#define TEE_WRITE_REE1_MODEM_V  0x00000001U
-#define TEE_WRITE_REE1_MODEM_S  6
-/** TEE_WRITE_REE2_MODEM : R/W; bitpos: [7]; default: 0;
- *  Configures modem registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_MODEM    (BIT(7))
-#define TEE_WRITE_REE2_MODEM_M  (TEE_WRITE_REE2_MODEM_V << TEE_WRITE_REE2_MODEM_S)
-#define TEE_WRITE_REE2_MODEM_V  0x00000001U
-#define TEE_WRITE_REE2_MODEM_S  7
-
-/** TEE_ZERO_DET_CTRL_REG register
- *  zero_det read/write control register
- */
-#define TEE_ZERO_DET_CTRL_REG (DR_REG_TEE_BASE + 0x13c)
-/** TEE_READ_TEE_ZERO_DET : R/W; bitpos: [0]; default: 1;
- *  Configures zero_det registers read permission in tee mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_TEE_ZERO_DET    (BIT(0))
-#define TEE_READ_TEE_ZERO_DET_M  (TEE_READ_TEE_ZERO_DET_V << TEE_READ_TEE_ZERO_DET_S)
-#define TEE_READ_TEE_ZERO_DET_V  0x00000001U
-#define TEE_READ_TEE_ZERO_DET_S  0
-/** TEE_READ_REE0_ZERO_DET : R/W; bitpos: [1]; default: 0;
- *  Configures zero_det registers read permission in ree0 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE0_ZERO_DET    (BIT(1))
-#define TEE_READ_REE0_ZERO_DET_M  (TEE_READ_REE0_ZERO_DET_V << TEE_READ_REE0_ZERO_DET_S)
-#define TEE_READ_REE0_ZERO_DET_V  0x00000001U
-#define TEE_READ_REE0_ZERO_DET_S  1
-/** TEE_READ_REE1_ZERO_DET : R/W; bitpos: [2]; default: 0;
- *  Configures zero_det registers read permission in ree1 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE1_ZERO_DET    (BIT(2))
-#define TEE_READ_REE1_ZERO_DET_M  (TEE_READ_REE1_ZERO_DET_V << TEE_READ_REE1_ZERO_DET_S)
-#define TEE_READ_REE1_ZERO_DET_V  0x00000001U
-#define TEE_READ_REE1_ZERO_DET_S  2
-/** TEE_READ_REE2_ZERO_DET : R/W; bitpos: [3]; default: 0;
- *  Configures zero_det registers read permission in ree2 mode.
- *  0: can not be read
- *  1: can be read
- */
-#define TEE_READ_REE2_ZERO_DET    (BIT(3))
-#define TEE_READ_REE2_ZERO_DET_M  (TEE_READ_REE2_ZERO_DET_V << TEE_READ_REE2_ZERO_DET_S)
-#define TEE_READ_REE2_ZERO_DET_V  0x00000001U
-#define TEE_READ_REE2_ZERO_DET_S  3
-/** TEE_WRITE_TEE_ZERO_DET : R/W; bitpos: [4]; default: 1;
- *  Configures zero_det registers write permission in tee mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_TEE_ZERO_DET    (BIT(4))
-#define TEE_WRITE_TEE_ZERO_DET_M  (TEE_WRITE_TEE_ZERO_DET_V << TEE_WRITE_TEE_ZERO_DET_S)
-#define TEE_WRITE_TEE_ZERO_DET_V  0x00000001U
-#define TEE_WRITE_TEE_ZERO_DET_S  4
-/** TEE_WRITE_REE0_ZERO_DET : R/W; bitpos: [5]; default: 0;
- *  Configures zero_det registers write permission in ree0 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE0_ZERO_DET    (BIT(5))
-#define TEE_WRITE_REE0_ZERO_DET_M  (TEE_WRITE_REE0_ZERO_DET_V << TEE_WRITE_REE0_ZERO_DET_S)
-#define TEE_WRITE_REE0_ZERO_DET_V  0x00000001U
-#define TEE_WRITE_REE0_ZERO_DET_S  5
-/** TEE_WRITE_REE1_ZERO_DET : R/W; bitpos: [6]; default: 0;
- *  Configures zero_det registers write permission in ree1 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE1_ZERO_DET    (BIT(6))
-#define TEE_WRITE_REE1_ZERO_DET_M  (TEE_WRITE_REE1_ZERO_DET_V << TEE_WRITE_REE1_ZERO_DET_S)
-#define TEE_WRITE_REE1_ZERO_DET_V  0x00000001U
-#define TEE_WRITE_REE1_ZERO_DET_S  6
-/** TEE_WRITE_REE2_ZERO_DET : R/W; bitpos: [7]; default: 0;
- *  Configures zero_det registers write permission in ree2 mode.
- *  0: can not be write
- *  1: can be write
- */
-#define TEE_WRITE_REE2_ZERO_DET    (BIT(7))
-#define TEE_WRITE_REE2_ZERO_DET_M  (TEE_WRITE_REE2_ZERO_DET_V << TEE_WRITE_REE2_ZERO_DET_S)
-#define TEE_WRITE_REE2_ZERO_DET_V  0x00000001U
-#define TEE_WRITE_REE2_ZERO_DET_S  7
-
-/** TEE_BUS_ERR_CONF_REG register
- *  Clock gating register
- */
-#define TEE_BUS_ERR_CONF_REG (DR_REG_TEE_BASE + 0xff0)
-/** TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether return error response to cpu when access blocked
- *  0: disable error response
- *  1: enable error response
- */
-#define TEE_BUS_ERR_RESP_EN    (BIT(0))
-#define TEE_BUS_ERR_RESP_EN_M  (TEE_BUS_ERR_RESP_EN_V << TEE_BUS_ERR_RESP_EN_S)
-#define TEE_BUS_ERR_RESP_EN_V  0x00000001U
-#define TEE_BUS_ERR_RESP_EN_S  0
-
-/** TEE_CLOCK_GATE_REG register
- *  Clock gating register
- */
-#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0xff8)
-/** TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Configures whether to keep the clock always on.
- *  0: enable automatic clock gating
- *  1: keep the clock always on
- */
-#define TEE_CLK_EN    (BIT(0))
-#define TEE_CLK_EN_M  (TEE_CLK_EN_V << TEE_CLK_EN_S)
-#define TEE_CLK_EN_V  0x00000001U
-#define TEE_CLK_EN_S  0
-
-/** TEE_DATE_REG register
- *  Version control register
- */
-#define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc)
-/** TEE_DATE : R/W; bitpos: [27:0]; default: 37818480;
- *  Version control register
- */
-#define TEE_DATE    0x0FFFFFFFU
-#define TEE_DATE_M  (TEE_DATE_V << TEE_DATE_S)
-#define TEE_DATE_V  0x0FFFFFFFU
-#define TEE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h4/register/hw_ver_beta5/soc/tee_struct.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/tee_struct.h
deleted file mode 100644
index 97af4f6d27..0000000000
--- a/components/soc/esp32h4/register/hw_ver_beta5/soc/tee_struct.h
+++ /dev/null
@@ -1,2940 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0 OR MIT
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Tee mode control register */
-/** Type of mn_mode_ctrl register
- *  TEE mode control register
- */
-typedef union {
-    struct {
-        /** mn_mode : R/W; bitpos: [1:0]; default: 0;
-         *  Configures Mn security level mode.
-         *  0: tee_mode
-         *  1: ree_mode0
-         *  2: ree_mode1
-         *  3: ree_mode2
-         */
-        uint32_t mn_mode:2;
-        /** mn_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m0 tee configuration
-         */
-        uint32_t mn_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_mn_mode_ctrl_reg_t;
-
-
-/** Group: read write control register */
-/** Type of gpspi0_ctrl register
- *  gpspi0 read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_gpspi0 : R/W; bitpos: [0]; default: 1;
-         *  Configures gpspi0 registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_gpspi0:1;
-        /** read_ree0_gpspi0 : R/W; bitpos: [1]; default: 0;
-         *  Configures gpspi0 registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_gpspi0:1;
-        /** read_ree1_gpspi0 : R/W; bitpos: [2]; default: 0;
-         *  Configures gpspi0 registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_gpspi0:1;
-        /** read_ree2_gpspi0 : R/W; bitpos: [3]; default: 0;
-         *  Configures gpspi0 registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_gpspi0:1;
-        /** write_tee_gpspi0 : R/W; bitpos: [4]; default: 1;
-         *  Configures gpspi0 registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_gpspi0:1;
-        /** write_ree0_gpspi0 : R/W; bitpos: [5]; default: 0;
-         *  Configures gpspi0 registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_gpspi0:1;
-        /** write_ree1_gpspi0 : R/W; bitpos: [6]; default: 0;
-         *  Configures gpspi0 registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_gpspi0:1;
-        /** write_ree2_gpspi0 : R/W; bitpos: [7]; default: 0;
-         *  Configures gpspi0 registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_gpspi0:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_gpspi0_ctrl_reg_t;
-
-/** Type of gpspi1_ctrl register
- *  gpspi1 read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_gpspi1 : R/W; bitpos: [0]; default: 1;
-         *  Configures gpspi1 registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_gpspi1:1;
-        /** read_ree0_gpspi1 : R/W; bitpos: [1]; default: 0;
-         *  Configures gpspi1 registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_gpspi1:1;
-        /** read_ree1_gpspi1 : R/W; bitpos: [2]; default: 0;
-         *  Configures gpspi1 registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_gpspi1:1;
-        /** read_ree2_gpspi1 : R/W; bitpos: [3]; default: 0;
-         *  Configures gpspi1 registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_gpspi1:1;
-        /** write_tee_gpspi1 : R/W; bitpos: [4]; default: 1;
-         *  Configures gpspi1 registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_gpspi1:1;
-        /** write_ree0_gpspi1 : R/W; bitpos: [5]; default: 0;
-         *  Configures gpspi1 registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_gpspi1:1;
-        /** write_ree1_gpspi1 : R/W; bitpos: [6]; default: 0;
-         *  Configures gpspi1 registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_gpspi1:1;
-        /** write_ree2_gpspi1 : R/W; bitpos: [7]; default: 0;
-         *  Configures gpspi1 registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_gpspi1:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_gpspi1_ctrl_reg_t;
-
-/** Type of uart0_ctrl register
- *  uart0 read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_uart0 : R/W; bitpos: [0]; default: 1;
-         *  Configures uart0 registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_uart0:1;
-        /** read_ree0_uart0 : R/W; bitpos: [1]; default: 0;
-         *  Configures uart0 registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_uart0:1;
-        /** read_ree1_uart0 : R/W; bitpos: [2]; default: 0;
-         *  Configures uart0 registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_uart0:1;
-        /** read_ree2_uart0 : R/W; bitpos: [3]; default: 0;
-         *  Configures uart0 registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_uart0:1;
-        /** write_tee_uart0 : R/W; bitpos: [4]; default: 1;
-         *  Configures uart0 registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_uart0:1;
-        /** write_ree0_uart0 : R/W; bitpos: [5]; default: 0;
-         *  Configures uart0 registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_uart0:1;
-        /** write_ree1_uart0 : R/W; bitpos: [6]; default: 0;
-         *  Configures uart0 registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_uart0:1;
-        /** write_ree2_uart0 : R/W; bitpos: [7]; default: 0;
-         *  Configures uart0 registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_uart0:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_uart0_ctrl_reg_t;
-
-/** Type of uart1_ctrl register
- *  uart1 read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_uart1 : R/W; bitpos: [0]; default: 1;
-         *  Configures uart1 registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_uart1:1;
-        /** read_ree0_uart1 : R/W; bitpos: [1]; default: 0;
-         *  Configures uart1 registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_uart1:1;
-        /** read_ree1_uart1 : R/W; bitpos: [2]; default: 0;
-         *  Configures uart1 registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_uart1:1;
-        /** read_ree2_uart1 : R/W; bitpos: [3]; default: 0;
-         *  Configures uart1 registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_uart1:1;
-        /** write_tee_uart1 : R/W; bitpos: [4]; default: 1;
-         *  Configures uart1 registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_uart1:1;
-        /** write_ree0_uart1 : R/W; bitpos: [5]; default: 0;
-         *  Configures uart1 registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_uart1:1;
-        /** write_ree1_uart1 : R/W; bitpos: [6]; default: 0;
-         *  Configures uart1 registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_uart1:1;
-        /** write_ree2_uart1 : R/W; bitpos: [7]; default: 0;
-         *  Configures uart1 registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_uart1:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_uart1_ctrl_reg_t;
-
-/** Type of uhci_ctrl register
- *  uhci read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_uhci : R/W; bitpos: [0]; default: 1;
-         *  Configures uhci registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_uhci:1;
-        /** read_ree0_uhci : R/W; bitpos: [1]; default: 0;
-         *  Configures uhci registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_uhci:1;
-        /** read_ree1_uhci : R/W; bitpos: [2]; default: 0;
-         *  Configures uhci registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_uhci:1;
-        /** read_ree2_uhci : R/W; bitpos: [3]; default: 0;
-         *  Configures uhci registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_uhci:1;
-        /** write_tee_uhci : R/W; bitpos: [4]; default: 1;
-         *  Configures uhci registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_uhci:1;
-        /** write_ree0_uhci : R/W; bitpos: [5]; default: 0;
-         *  Configures uhci registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_uhci:1;
-        /** write_ree1_uhci : R/W; bitpos: [6]; default: 0;
-         *  Configures uhci registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_uhci:1;
-        /** write_ree2_uhci : R/W; bitpos: [7]; default: 0;
-         *  Configures uhci registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_uhci:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_uhci_ctrl_reg_t;
-
-/** Type of i2c0_ctrl register
- *  i2c0 read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_i2c0 : R/W; bitpos: [0]; default: 1;
-         *  Configures i2c0 registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_i2c0:1;
-        /** read_ree0_i2c0 : R/W; bitpos: [1]; default: 0;
-         *  Configures i2c0 registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_i2c0:1;
-        /** read_ree1_i2c0 : R/W; bitpos: [2]; default: 0;
-         *  Configures i2c0 registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_i2c0:1;
-        /** read_ree2_i2c0 : R/W; bitpos: [3]; default: 0;
-         *  Configures i2c0 registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_i2c0:1;
-        /** write_tee_i2c0 : R/W; bitpos: [4]; default: 1;
-         *  Configures i2c0 registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_i2c0:1;
-        /** write_ree0_i2c0 : R/W; bitpos: [5]; default: 0;
-         *  Configures i2c0 registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_i2c0:1;
-        /** write_ree1_i2c0 : R/W; bitpos: [6]; default: 0;
-         *  Configures i2c0 registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_i2c0:1;
-        /** write_ree2_i2c0 : R/W; bitpos: [7]; default: 0;
-         *  Configures i2c0 registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_i2c0:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_i2c0_ctrl_reg_t;
-
-/** Type of i2c1_ctrl register
- *  i2c1 read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_i2c1 : R/W; bitpos: [0]; default: 1;
-         *  Configures i2c1 registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_i2c1:1;
-        /** read_ree0_i2c1 : R/W; bitpos: [1]; default: 0;
-         *  Configures i2c1 registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_i2c1:1;
-        /** read_ree1_i2c1 : R/W; bitpos: [2]; default: 0;
-         *  Configures i2c1 registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_i2c1:1;
-        /** read_ree2_i2c1 : R/W; bitpos: [3]; default: 0;
-         *  Configures i2c1 registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_i2c1:1;
-        /** write_tee_i2c1 : R/W; bitpos: [4]; default: 1;
-         *  Configures i2c1 registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_i2c1:1;
-        /** write_ree0_i2c1 : R/W; bitpos: [5]; default: 0;
-         *  Configures i2c1 registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_i2c1:1;
-        /** write_ree1_i2c1 : R/W; bitpos: [6]; default: 0;
-         *  Configures i2c1 registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_i2c1:1;
-        /** write_ree2_i2c1 : R/W; bitpos: [7]; default: 0;
-         *  Configures i2c1 registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_i2c1:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_i2c1_ctrl_reg_t;
-
-/** Type of i2s_ctrl register
- *  i2s read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_i2s : R/W; bitpos: [0]; default: 1;
-         *  Configures i2s registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_i2s:1;
-        /** read_ree0_i2s : R/W; bitpos: [1]; default: 0;
-         *  Configures i2s registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_i2s:1;
-        /** read_ree1_i2s : R/W; bitpos: [2]; default: 0;
-         *  Configures i2s registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_i2s:1;
-        /** read_ree2_i2s : R/W; bitpos: [3]; default: 0;
-         *  Configures i2s registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_i2s:1;
-        /** write_tee_i2s : R/W; bitpos: [4]; default: 1;
-         *  Configures i2s registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_i2s:1;
-        /** write_ree0_i2s : R/W; bitpos: [5]; default: 0;
-         *  Configures i2s registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_i2s:1;
-        /** write_ree1_i2s : R/W; bitpos: [6]; default: 0;
-         *  Configures i2s registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_i2s:1;
-        /** write_ree2_i2s : R/W; bitpos: [7]; default: 0;
-         *  Configures i2s registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_i2s:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_i2s_ctrl_reg_t;
-
-/** Type of parl_io_ctrl register
- *  parl_io read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_parl_io : R/W; bitpos: [0]; default: 1;
-         *  Configures parl_io registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_parl_io:1;
-        /** read_ree0_parl_io : R/W; bitpos: [1]; default: 0;
-         *  Configures parl_io registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_parl_io:1;
-        /** read_ree1_parl_io : R/W; bitpos: [2]; default: 0;
-         *  Configures parl_io registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_parl_io:1;
-        /** read_ree2_parl_io : R/W; bitpos: [3]; default: 0;
-         *  Configures parl_io registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_parl_io:1;
-        /** write_tee_parl_io : R/W; bitpos: [4]; default: 1;
-         *  Configures parl_io registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_parl_io:1;
-        /** write_ree0_parl_io : R/W; bitpos: [5]; default: 0;
-         *  Configures parl_io registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_parl_io:1;
-        /** write_ree1_parl_io : R/W; bitpos: [6]; default: 0;
-         *  Configures parl_io registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_parl_io:1;
-        /** write_ree2_parl_io : R/W; bitpos: [7]; default: 0;
-         *  Configures parl_io registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_parl_io:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_parl_io_ctrl_reg_t;
-
-/** Type of pwm0_ctrl register
- *  pwm0 read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_pwm0 : R/W; bitpos: [0]; default: 1;
-         *  Configures pwm0 registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_pwm0:1;
-        /** read_ree0_pwm0 : R/W; bitpos: [1]; default: 0;
-         *  Configures pwm0 registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_pwm0:1;
-        /** read_ree1_pwm0 : R/W; bitpos: [2]; default: 0;
-         *  Configures pwm0 registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_pwm0:1;
-        /** read_ree2_pwm0 : R/W; bitpos: [3]; default: 0;
-         *  Configures pwm0 registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_pwm0:1;
-        /** write_tee_pwm0 : R/W; bitpos: [4]; default: 1;
-         *  Configures pwm0 registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_pwm0:1;
-        /** write_ree0_pwm0 : R/W; bitpos: [5]; default: 0;
-         *  Configures pwm0 registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_pwm0:1;
-        /** write_ree1_pwm0 : R/W; bitpos: [6]; default: 0;
-         *  Configures pwm0 registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_pwm0:1;
-        /** write_ree2_pwm0 : R/W; bitpos: [7]; default: 0;
-         *  Configures pwm0 registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_pwm0:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_pwm0_ctrl_reg_t;
-
-/** Type of pwm1_ctrl register
- *  pwm1 read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_pwm1 : R/W; bitpos: [0]; default: 1;
-         *  Configures pwm1 registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_pwm1:1;
-        /** read_ree0_pwm1 : R/W; bitpos: [1]; default: 0;
-         *  Configures pwm1 registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_pwm1:1;
-        /** read_ree1_pwm1 : R/W; bitpos: [2]; default: 0;
-         *  Configures pwm1 registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_pwm1:1;
-        /** read_ree2_pwm1 : R/W; bitpos: [3]; default: 0;
-         *  Configures pwm1 registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_pwm1:1;
-        /** write_tee_pwm1 : R/W; bitpos: [4]; default: 1;
-         *  Configures pwm1 registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_pwm1:1;
-        /** write_ree0_pwm1 : R/W; bitpos: [5]; default: 0;
-         *  Configures pwm1 registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_pwm1:1;
-        /** write_ree1_pwm1 : R/W; bitpos: [6]; default: 0;
-         *  Configures pwm1 registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_pwm1:1;
-        /** write_ree2_pwm1 : R/W; bitpos: [7]; default: 0;
-         *  Configures pwm1 registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_pwm1:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_pwm1_ctrl_reg_t;
-
-/** Type of ledc_ctrl register
- *  ledc read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_ledc : R/W; bitpos: [0]; default: 1;
-         *  Configures ledc registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_ledc:1;
-        /** read_ree0_ledc : R/W; bitpos: [1]; default: 0;
-         *  Configures ledc registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_ledc:1;
-        /** read_ree1_ledc : R/W; bitpos: [2]; default: 0;
-         *  Configures ledc registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_ledc:1;
-        /** read_ree2_ledc : R/W; bitpos: [3]; default: 0;
-         *  Configures ledc registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_ledc:1;
-        /** write_tee_ledc : R/W; bitpos: [4]; default: 1;
-         *  Configures ledc registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_ledc:1;
-        /** write_ree0_ledc : R/W; bitpos: [5]; default: 0;
-         *  Configures ledc registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_ledc:1;
-        /** write_ree1_ledc : R/W; bitpos: [6]; default: 0;
-         *  Configures ledc registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_ledc:1;
-        /** write_ree2_ledc : R/W; bitpos: [7]; default: 0;
-         *  Configures ledc registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_ledc:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_ledc_ctrl_reg_t;
-
-/** Type of can_ctrl register
- *  can read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_can : R/W; bitpos: [0]; default: 1;
-         *  Configures can registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_can:1;
-        /** read_ree0_can : R/W; bitpos: [1]; default: 0;
-         *  Configures can registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_can:1;
-        /** read_ree1_can : R/W; bitpos: [2]; default: 0;
-         *  Configures can registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_can:1;
-        /** read_ree2_can : R/W; bitpos: [3]; default: 0;
-         *  Configures can registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_can:1;
-        /** write_tee_can : R/W; bitpos: [4]; default: 1;
-         *  Configures can registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_can:1;
-        /** write_ree0_can : R/W; bitpos: [5]; default: 0;
-         *  Configures can registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_can:1;
-        /** write_ree1_can : R/W; bitpos: [6]; default: 0;
-         *  Configures can registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_can:1;
-        /** write_ree2_can : R/W; bitpos: [7]; default: 0;
-         *  Configures can registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_can:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_can_ctrl_reg_t;
-
-/** Type of usb_serial_jtag_ctrl register
- *  usb_serial_jtag read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_usb_serial_jtag : R/W; bitpos: [0]; default: 1;
-         *  Configures usb_serial_jtag registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_usb_serial_jtag:1;
-        /** read_ree0_usb_serial_jtag : R/W; bitpos: [1]; default: 0;
-         *  Configures usb_serial_jtag registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_usb_serial_jtag:1;
-        /** read_ree1_usb_serial_jtag : R/W; bitpos: [2]; default: 0;
-         *  Configures usb_serial_jtag registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_usb_serial_jtag:1;
-        /** read_ree2_usb_serial_jtag : R/W; bitpos: [3]; default: 0;
-         *  Configures usb_serial_jtag registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_usb_serial_jtag:1;
-        /** write_tee_usb_serial_jtag : R/W; bitpos: [4]; default: 1;
-         *  Configures usb_serial_jtag registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_usb_serial_jtag:1;
-        /** write_ree0_usb_serial_jtag : R/W; bitpos: [5]; default: 0;
-         *  Configures usb_serial_jtag registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_usb_serial_jtag:1;
-        /** write_ree1_usb_serial_jtag : R/W; bitpos: [6]; default: 0;
-         *  Configures usb_serial_jtag registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_usb_serial_jtag:1;
-        /** write_ree2_usb_serial_jtag : R/W; bitpos: [7]; default: 0;
-         *  Configures usb_serial_jtag registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_usb_serial_jtag:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_usb_serial_jtag_ctrl_reg_t;
-
-/** Type of rmt_ctrl register
- *  rmt read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_rmt : R/W; bitpos: [0]; default: 1;
-         *  Configures rmt registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_rmt:1;
-        /** read_ree0_rmt : R/W; bitpos: [1]; default: 0;
-         *  Configures rmt registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_rmt:1;
-        /** read_ree1_rmt : R/W; bitpos: [2]; default: 0;
-         *  Configures rmt registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_rmt:1;
-        /** read_ree2_rmt : R/W; bitpos: [3]; default: 0;
-         *  Configures rmt registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_rmt:1;
-        /** write_tee_rmt : R/W; bitpos: [4]; default: 1;
-         *  Configures rmt registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_rmt:1;
-        /** write_ree0_rmt : R/W; bitpos: [5]; default: 0;
-         *  Configures rmt registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_rmt:1;
-        /** write_ree1_rmt : R/W; bitpos: [6]; default: 0;
-         *  Configures rmt registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_rmt:1;
-        /** write_ree2_rmt : R/W; bitpos: [7]; default: 0;
-         *  Configures rmt registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_rmt:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_rmt_ctrl_reg_t;
-
-/** Type of gdma_ctrl register
- *  gdma read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_gdma : R/W; bitpos: [0]; default: 1;
-         *  Configures gdma registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_gdma:1;
-        /** read_ree0_gdma : R/W; bitpos: [1]; default: 0;
-         *  Configures gdma registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_gdma:1;
-        /** read_ree1_gdma : R/W; bitpos: [2]; default: 0;
-         *  Configures gdma registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_gdma:1;
-        /** read_ree2_gdma : R/W; bitpos: [3]; default: 0;
-         *  Configures gdma registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_gdma:1;
-        /** write_tee_gdma : R/W; bitpos: [4]; default: 1;
-         *  Configures gdma registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_gdma:1;
-        /** write_ree0_gdma : R/W; bitpos: [5]; default: 0;
-         *  Configures gdma registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_gdma:1;
-        /** write_ree1_gdma : R/W; bitpos: [6]; default: 0;
-         *  Configures gdma registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_gdma:1;
-        /** write_ree2_gdma : R/W; bitpos: [7]; default: 0;
-         *  Configures gdma registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_gdma:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_gdma_ctrl_reg_t;
-
-/** Type of regdma_ctrl register
- *  regdma read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_regdma : R/W; bitpos: [0]; default: 1;
-         *  Configures regdma registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_regdma:1;
-        /** read_ree0_regdma : R/W; bitpos: [1]; default: 0;
-         *  Configures regdma registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_regdma:1;
-        /** read_ree1_regdma : R/W; bitpos: [2]; default: 0;
-         *  Configures regdma registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_regdma:1;
-        /** read_ree2_regdma : R/W; bitpos: [3]; default: 0;
-         *  Configures regdma registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_regdma:1;
-        /** write_tee_regdma : R/W; bitpos: [4]; default: 1;
-         *  Configures regdma registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_regdma:1;
-        /** write_ree0_regdma : R/W; bitpos: [5]; default: 0;
-         *  Configures regdma registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_regdma:1;
-        /** write_ree1_regdma : R/W; bitpos: [6]; default: 0;
-         *  Configures regdma registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_regdma:1;
-        /** write_ree2_regdma : R/W; bitpos: [7]; default: 0;
-         *  Configures regdma registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_regdma:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_regdma_ctrl_reg_t;
-
-/** Type of etm_ctrl register
- *  etm read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_etm : R/W; bitpos: [0]; default: 1;
-         *  Configures etm registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_etm:1;
-        /** read_ree0_etm : R/W; bitpos: [1]; default: 0;
-         *  Configures etm registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_etm:1;
-        /** read_ree1_etm : R/W; bitpos: [2]; default: 0;
-         *  Configures etm registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_etm:1;
-        /** read_ree2_etm : R/W; bitpos: [3]; default: 0;
-         *  Configures etm registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_etm:1;
-        /** write_tee_etm : R/W; bitpos: [4]; default: 1;
-         *  Configures etm registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_etm:1;
-        /** write_ree0_etm : R/W; bitpos: [5]; default: 0;
-         *  Configures etm registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_etm:1;
-        /** write_ree1_etm : R/W; bitpos: [6]; default: 0;
-         *  Configures etm registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_etm:1;
-        /** write_ree2_etm : R/W; bitpos: [7]; default: 0;
-         *  Configures etm registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_etm:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_etm_ctrl_reg_t;
-
-/** Type of intmtx_core0_ctrl register
- *  intmtx_core0 read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_intmtx_core0 : R/W; bitpos: [0]; default: 1;
-         *  Configures intmtx_core0 registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_intmtx_core0:1;
-        /** read_ree0_intmtx_core0 : R/W; bitpos: [1]; default: 0;
-         *  Configures intmtx_core0 registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_intmtx_core0:1;
-        /** read_ree1_intmtx_core0 : R/W; bitpos: [2]; default: 0;
-         *  Configures intmtx_core0 registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_intmtx_core0:1;
-        /** read_ree2_intmtx_core0 : R/W; bitpos: [3]; default: 0;
-         *  Configures intmtx_core0 registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_intmtx_core0:1;
-        /** write_tee_intmtx_core0 : R/W; bitpos: [4]; default: 1;
-         *  Configures intmtx_core0 registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_intmtx_core0:1;
-        /** write_ree0_intmtx_core0 : R/W; bitpos: [5]; default: 0;
-         *  Configures intmtx_core0 registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_intmtx_core0:1;
-        /** write_ree1_intmtx_core0 : R/W; bitpos: [6]; default: 0;
-         *  Configures intmtx_core0 registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_intmtx_core0:1;
-        /** write_ree2_intmtx_core0 : R/W; bitpos: [7]; default: 0;
-         *  Configures intmtx_core0 registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_intmtx_core0:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_intmtx_core0_ctrl_reg_t;
-
-/** Type of intmtx_core1_ctrl register
- *  intmtx_core1 read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_intmtx_core1 : R/W; bitpos: [0]; default: 1;
-         *  Configures intmtx_core1 registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_intmtx_core1:1;
-        /** read_ree0_intmtx_core1 : R/W; bitpos: [1]; default: 0;
-         *  Configures intmtx_core1 registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_intmtx_core1:1;
-        /** read_ree1_intmtx_core1 : R/W; bitpos: [2]; default: 0;
-         *  Configures intmtx_core1 registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_intmtx_core1:1;
-        /** read_ree2_intmtx_core1 : R/W; bitpos: [3]; default: 0;
-         *  Configures intmtx_core1 registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_intmtx_core1:1;
-        /** write_tee_intmtx_core1 : R/W; bitpos: [4]; default: 1;
-         *  Configures intmtx_core1 registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_intmtx_core1:1;
-        /** write_ree0_intmtx_core1 : R/W; bitpos: [5]; default: 0;
-         *  Configures intmtx_core1 registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_intmtx_core1:1;
-        /** write_ree1_intmtx_core1 : R/W; bitpos: [6]; default: 0;
-         *  Configures intmtx_core1 registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_intmtx_core1:1;
-        /** write_ree2_intmtx_core1 : R/W; bitpos: [7]; default: 0;
-         *  Configures intmtx_core1 registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_intmtx_core1:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_intmtx_core1_ctrl_reg_t;
-
-/** Type of apb_adc_ctrl register
- *  apb_adc read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_apb_adc : R/W; bitpos: [0]; default: 1;
-         *  Configures apb_adc registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_apb_adc:1;
-        /** read_ree0_apb_adc : R/W; bitpos: [1]; default: 0;
-         *  Configures apb_adc registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_apb_adc:1;
-        /** read_ree1_apb_adc : R/W; bitpos: [2]; default: 0;
-         *  Configures apb_adc registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_apb_adc:1;
-        /** read_ree2_apb_adc : R/W; bitpos: [3]; default: 0;
-         *  Configures apb_adc registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_apb_adc:1;
-        /** write_tee_apb_adc : R/W; bitpos: [4]; default: 1;
-         *  Configures apb_adc registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_apb_adc:1;
-        /** write_ree0_apb_adc : R/W; bitpos: [5]; default: 0;
-         *  Configures apb_adc registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_apb_adc:1;
-        /** write_ree1_apb_adc : R/W; bitpos: [6]; default: 0;
-         *  Configures apb_adc registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_apb_adc:1;
-        /** write_ree2_apb_adc : R/W; bitpos: [7]; default: 0;
-         *  Configures apb_adc registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_apb_adc:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_apb_adc_ctrl_reg_t;
-
-/** Type of timergroup0_ctrl register
- *  timergroup0 read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_timergroup0 : R/W; bitpos: [0]; default: 1;
-         *  Configures timergroup0 registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_timergroup0:1;
-        /** read_ree0_timergroup0 : R/W; bitpos: [1]; default: 0;
-         *  Configures timergroup0 registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_timergroup0:1;
-        /** read_ree1_timergroup0 : R/W; bitpos: [2]; default: 0;
-         *  Configures timergroup0 registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_timergroup0:1;
-        /** read_ree2_timergroup0 : R/W; bitpos: [3]; default: 0;
-         *  Configures timergroup0 registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_timergroup0:1;
-        /** write_tee_timergroup0 : R/W; bitpos: [4]; default: 1;
-         *  Configures timergroup0 registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_timergroup0:1;
-        /** write_ree0_timergroup0 : R/W; bitpos: [5]; default: 0;
-         *  Configures timergroup0 registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_timergroup0:1;
-        /** write_ree1_timergroup0 : R/W; bitpos: [6]; default: 0;
-         *  Configures timergroup0 registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_timergroup0:1;
-        /** write_ree2_timergroup0 : R/W; bitpos: [7]; default: 0;
-         *  Configures timergroup0 registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_timergroup0:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_timergroup0_ctrl_reg_t;
-
-/** Type of timergroup1_ctrl register
- *  timergroup1 read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_timergroup1 : R/W; bitpos: [0]; default: 1;
-         *  Configures timergroup1 registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_timergroup1:1;
-        /** read_ree0_timergroup1 : R/W; bitpos: [1]; default: 0;
-         *  Configures timergroup1 registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_timergroup1:1;
-        /** read_ree1_timergroup1 : R/W; bitpos: [2]; default: 0;
-         *  Configures timergroup1 registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_timergroup1:1;
-        /** read_ree2_timergroup1 : R/W; bitpos: [3]; default: 0;
-         *  Configures timergroup1 registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_timergroup1:1;
-        /** write_tee_timergroup1 : R/W; bitpos: [4]; default: 1;
-         *  Configures timergroup1 registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_timergroup1:1;
-        /** write_ree0_timergroup1 : R/W; bitpos: [5]; default: 0;
-         *  Configures timergroup1 registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_timergroup1:1;
-        /** write_ree1_timergroup1 : R/W; bitpos: [6]; default: 0;
-         *  Configures timergroup1 registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_timergroup1:1;
-        /** write_ree2_timergroup1 : R/W; bitpos: [7]; default: 0;
-         *  Configures timergroup1 registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_timergroup1:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_timergroup1_ctrl_reg_t;
-
-/** Type of systimer_ctrl register
- *  systimer read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_systimer : R/W; bitpos: [0]; default: 1;
-         *  Configures systimer registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_systimer:1;
-        /** read_ree0_systimer : R/W; bitpos: [1]; default: 0;
-         *  Configures systimer registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_systimer:1;
-        /** read_ree1_systimer : R/W; bitpos: [2]; default: 0;
-         *  Configures systimer registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_systimer:1;
-        /** read_ree2_systimer : R/W; bitpos: [3]; default: 0;
-         *  Configures systimer registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_systimer:1;
-        /** write_tee_systimer : R/W; bitpos: [4]; default: 1;
-         *  Configures systimer registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_systimer:1;
-        /** write_ree0_systimer : R/W; bitpos: [5]; default: 0;
-         *  Configures systimer registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_systimer:1;
-        /** write_ree1_systimer : R/W; bitpos: [6]; default: 0;
-         *  Configures systimer registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_systimer:1;
-        /** write_ree2_systimer : R/W; bitpos: [7]; default: 0;
-         *  Configures systimer registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_systimer:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_systimer_ctrl_reg_t;
-
-/** Type of misc_ctrl register
- *  misc read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_misc : R/W; bitpos: [0]; default: 1;
-         *  Configures misc registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_misc:1;
-        /** read_ree0_misc : R/W; bitpos: [1]; default: 0;
-         *  Configures misc registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_misc:1;
-        /** read_ree1_misc : R/W; bitpos: [2]; default: 0;
-         *  Configures misc registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_misc:1;
-        /** read_ree2_misc : R/W; bitpos: [3]; default: 0;
-         *  Configures misc registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_misc:1;
-        /** write_tee_misc : R/W; bitpos: [4]; default: 1;
-         *  Configures misc registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_misc:1;
-        /** write_ree0_misc : R/W; bitpos: [5]; default: 0;
-         *  Configures misc registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_misc:1;
-        /** write_ree1_misc : R/W; bitpos: [6]; default: 0;
-         *  Configures misc registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_misc:1;
-        /** write_ree2_misc : R/W; bitpos: [7]; default: 0;
-         *  Configures misc registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_misc:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_misc_ctrl_reg_t;
-
-/** Type of src_ctrl register
- *  src read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_src : R/W; bitpos: [0]; default: 1;
-         *  Configures src registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_src:1;
-        /** read_ree0_src : R/W; bitpos: [1]; default: 0;
-         *  Configures src registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_src:1;
-        /** read_ree1_src : R/W; bitpos: [2]; default: 0;
-         *  Configures src registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_src:1;
-        /** read_ree2_src : R/W; bitpos: [3]; default: 0;
-         *  Configures src registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_src:1;
-        /** write_tee_src : R/W; bitpos: [4]; default: 1;
-         *  Configures src registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_src:1;
-        /** write_ree0_src : R/W; bitpos: [5]; default: 0;
-         *  Configures src registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_src:1;
-        /** write_ree1_src : R/W; bitpos: [6]; default: 0;
-         *  Configures src registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_src:1;
-        /** write_ree2_src : R/W; bitpos: [7]; default: 0;
-         *  Configures src registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_src:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_src_ctrl_reg_t;
-
-/** Type of usb_otg_fs_core_ctrl register
- *  usb_otg_fs_core read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_usb_otg_fs_core : R/W; bitpos: [0]; default: 1;
-         *  Configures usb_otg_fs_core registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_usb_otg_fs_core:1;
-        /** read_ree0_usb_otg_fs_core : R/W; bitpos: [1]; default: 0;
-         *  Configures usb_otg_fs_core registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_usb_otg_fs_core:1;
-        /** read_ree1_usb_otg_fs_core : R/W; bitpos: [2]; default: 0;
-         *  Configures usb_otg_fs_core registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_usb_otg_fs_core:1;
-        /** read_ree2_usb_otg_fs_core : R/W; bitpos: [3]; default: 0;
-         *  Configures usb_otg_fs_core registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_usb_otg_fs_core:1;
-        /** write_tee_usb_otg_fs_core : R/W; bitpos: [4]; default: 1;
-         *  Configures usb_otg_fs_core registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_usb_otg_fs_core:1;
-        /** write_ree0_usb_otg_fs_core : R/W; bitpos: [5]; default: 0;
-         *  Configures usb_otg_fs_core registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_usb_otg_fs_core:1;
-        /** write_ree1_usb_otg_fs_core : R/W; bitpos: [6]; default: 0;
-         *  Configures usb_otg_fs_core registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_usb_otg_fs_core:1;
-        /** write_ree2_usb_otg_fs_core : R/W; bitpos: [7]; default: 0;
-         *  Configures usb_otg_fs_core registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_usb_otg_fs_core:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_usb_otg_fs_core_ctrl_reg_t;
-
-/** Type of usb_otg_fs_phy_ctrl register
- *  usb_otg_fs_phy read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_usb_otg_fs_phy : R/W; bitpos: [0]; default: 1;
-         *  Configures usb_otg_fs_phy registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_usb_otg_fs_phy:1;
-        /** read_ree0_usb_otg_fs_phy : R/W; bitpos: [1]; default: 0;
-         *  Configures usb_otg_fs_phy registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_usb_otg_fs_phy:1;
-        /** read_ree1_usb_otg_fs_phy : R/W; bitpos: [2]; default: 0;
-         *  Configures usb_otg_fs_phy registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_usb_otg_fs_phy:1;
-        /** read_ree2_usb_otg_fs_phy : R/W; bitpos: [3]; default: 0;
-         *  Configures usb_otg_fs_phy registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_usb_otg_fs_phy:1;
-        /** write_tee_usb_otg_fs_phy : R/W; bitpos: [4]; default: 1;
-         *  Configures usb_otg_fs_phy registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_usb_otg_fs_phy:1;
-        /** write_ree0_usb_otg_fs_phy : R/W; bitpos: [5]; default: 0;
-         *  Configures usb_otg_fs_phy registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_usb_otg_fs_phy:1;
-        /** write_ree1_usb_otg_fs_phy : R/W; bitpos: [6]; default: 0;
-         *  Configures usb_otg_fs_phy registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_usb_otg_fs_phy:1;
-        /** write_ree2_usb_otg_fs_phy : R/W; bitpos: [7]; default: 0;
-         *  Configures usb_otg_fs_phy registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_usb_otg_fs_phy:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_usb_otg_fs_phy_ctrl_reg_t;
-
-/** Type of pvt_monitor_ctrl register
- *  pvt_monitor read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_pvt_monitor : R/W; bitpos: [0]; default: 1;
-         *  Configures pvt_monitor registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_pvt_monitor:1;
-        /** read_ree0_pvt_monitor : R/W; bitpos: [1]; default: 0;
-         *  Configures pvt_monitor registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_pvt_monitor:1;
-        /** read_ree1_pvt_monitor : R/W; bitpos: [2]; default: 0;
-         *  Configures pvt_monitor registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_pvt_monitor:1;
-        /** read_ree2_pvt_monitor : R/W; bitpos: [3]; default: 0;
-         *  Configures pvt_monitor registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_pvt_monitor:1;
-        /** write_tee_pvt_monitor : R/W; bitpos: [4]; default: 1;
-         *  Configures pvt_monitor registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_pvt_monitor:1;
-        /** write_ree0_pvt_monitor : R/W; bitpos: [5]; default: 0;
-         *  Configures pvt_monitor registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_pvt_monitor:1;
-        /** write_ree1_pvt_monitor : R/W; bitpos: [6]; default: 0;
-         *  Configures pvt_monitor registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_pvt_monitor:1;
-        /** write_ree2_pvt_monitor : R/W; bitpos: [7]; default: 0;
-         *  Configures pvt_monitor registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_pvt_monitor:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_pvt_monitor_ctrl_reg_t;
-
-/** Type of pcnt_ctrl register
- *  pcnt read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_pcnt : R/W; bitpos: [0]; default: 1;
-         *  Configures pcnt registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_pcnt:1;
-        /** read_ree0_pcnt : R/W; bitpos: [1]; default: 0;
-         *  Configures pcnt registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_pcnt:1;
-        /** read_ree1_pcnt : R/W; bitpos: [2]; default: 0;
-         *  Configures pcnt registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_pcnt:1;
-        /** read_ree2_pcnt : R/W; bitpos: [3]; default: 0;
-         *  Configures pcnt registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_pcnt:1;
-        /** write_tee_pcnt : R/W; bitpos: [4]; default: 1;
-         *  Configures pcnt registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_pcnt:1;
-        /** write_ree0_pcnt : R/W; bitpos: [5]; default: 0;
-         *  Configures pcnt registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_pcnt:1;
-        /** write_ree1_pcnt : R/W; bitpos: [6]; default: 0;
-         *  Configures pcnt registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_pcnt:1;
-        /** write_ree2_pcnt : R/W; bitpos: [7]; default: 0;
-         *  Configures pcnt registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_pcnt:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_pcnt_ctrl_reg_t;
-
-/** Type of iomux_ctrl register
- *  iomux read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_iomux : R/W; bitpos: [0]; default: 1;
-         *  Configures iomux registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_iomux:1;
-        /** read_ree0_iomux : R/W; bitpos: [1]; default: 0;
-         *  Configures iomux registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_iomux:1;
-        /** read_ree1_iomux : R/W; bitpos: [2]; default: 0;
-         *  Configures iomux registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_iomux:1;
-        /** read_ree2_iomux : R/W; bitpos: [3]; default: 0;
-         *  Configures iomux registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_iomux:1;
-        /** write_tee_iomux : R/W; bitpos: [4]; default: 1;
-         *  Configures iomux registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_iomux:1;
-        /** write_ree0_iomux : R/W; bitpos: [5]; default: 0;
-         *  Configures iomux registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_iomux:1;
-        /** write_ree1_iomux : R/W; bitpos: [6]; default: 0;
-         *  Configures iomux registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_iomux:1;
-        /** write_ree2_iomux : R/W; bitpos: [7]; default: 0;
-         *  Configures iomux registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_iomux:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_iomux_ctrl_reg_t;
-
-/** Type of psram_mem_monitor_ctrl register
- *  psram_mem_monitor read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_psram_mem_monitor : R/W; bitpos: [0]; default: 1;
-         *  Configures psram_mem_monitor registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_psram_mem_monitor:1;
-        /** read_ree0_psram_mem_monitor : R/W; bitpos: [1]; default: 0;
-         *  Configures psram_mem_monitor registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_psram_mem_monitor:1;
-        /** read_ree1_psram_mem_monitor : R/W; bitpos: [2]; default: 0;
-         *  Configures psram_mem_monitor registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_psram_mem_monitor:1;
-        /** read_ree2_psram_mem_monitor : R/W; bitpos: [3]; default: 0;
-         *  Configures psram_mem_monitor registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_psram_mem_monitor:1;
-        /** write_tee_psram_mem_monitor : R/W; bitpos: [4]; default: 1;
-         *  Configures psram_mem_monitor registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_psram_mem_monitor:1;
-        /** write_ree0_psram_mem_monitor : R/W; bitpos: [5]; default: 0;
-         *  Configures psram_mem_monitor registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_psram_mem_monitor:1;
-        /** write_ree1_psram_mem_monitor : R/W; bitpos: [6]; default: 0;
-         *  Configures psram_mem_monitor registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_psram_mem_monitor:1;
-        /** write_ree2_psram_mem_monitor : R/W; bitpos: [7]; default: 0;
-         *  Configures psram_mem_monitor registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_psram_mem_monitor:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_psram_mem_monitor_ctrl_reg_t;
-
-/** Type of mem_acs_monitor_ctrl register
- *  mem_acs_monitor read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_mem_acs_monitor : R/W; bitpos: [0]; default: 1;
-         *  Configures mem_acs_monitor registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_mem_acs_monitor:1;
-        /** read_ree0_mem_acs_monitor : R/W; bitpos: [1]; default: 0;
-         *  Configures mem_acs_monitor registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_mem_acs_monitor:1;
-        /** read_ree1_mem_acs_monitor : R/W; bitpos: [2]; default: 0;
-         *  Configures mem_acs_monitor registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_mem_acs_monitor:1;
-        /** read_ree2_mem_acs_monitor : R/W; bitpos: [3]; default: 0;
-         *  Configures mem_acs_monitor registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_mem_acs_monitor:1;
-        /** write_tee_mem_acs_monitor : R/W; bitpos: [4]; default: 1;
-         *  Configures mem_acs_monitor registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_mem_acs_monitor:1;
-        /** write_ree0_mem_acs_monitor : R/W; bitpos: [5]; default: 0;
-         *  Configures mem_acs_monitor registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_mem_acs_monitor:1;
-        /** write_ree1_mem_acs_monitor : R/W; bitpos: [6]; default: 0;
-         *  Configures mem_acs_monitor registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_mem_acs_monitor:1;
-        /** write_ree2_mem_acs_monitor : R/W; bitpos: [7]; default: 0;
-         *  Configures mem_acs_monitor registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_mem_acs_monitor:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_mem_acs_monitor_ctrl_reg_t;
-
-/** Type of hp_system_reg_ctrl register
- *  hp_system_reg read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_hp_system_reg : R/W; bitpos: [0]; default: 1;
-         *  Configures hp_system_reg registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_hp_system_reg:1;
-        /** read_ree0_hp_system_reg : R/W; bitpos: [1]; default: 0;
-         *  Configures hp_system_reg registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_hp_system_reg:1;
-        /** read_ree1_hp_system_reg : R/W; bitpos: [2]; default: 0;
-         *  Configures hp_system_reg registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_hp_system_reg:1;
-        /** read_ree2_hp_system_reg : R/W; bitpos: [3]; default: 0;
-         *  Configures hp_system_reg registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_hp_system_reg:1;
-        /** write_tee_hp_system_reg : R/W; bitpos: [4]; default: 1;
-         *  Configures hp_system_reg registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_hp_system_reg:1;
-        /** write_ree0_hp_system_reg : R/W; bitpos: [5]; default: 0;
-         *  Configures hp_system_reg registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_hp_system_reg:1;
-        /** write_ree1_hp_system_reg : R/W; bitpos: [6]; default: 0;
-         *  Configures hp_system_reg registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_hp_system_reg:1;
-        /** write_ree2_hp_system_reg : R/W; bitpos: [7]; default: 0;
-         *  Configures hp_system_reg registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_hp_system_reg:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_hp_system_reg_ctrl_reg_t;
-
-/** Type of pcr_reg_ctrl register
- *  pcr_reg read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_pcr_reg : R/W; bitpos: [0]; default: 1;
-         *  Configures pcr_reg registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_pcr_reg:1;
-        /** read_ree0_pcr_reg : R/W; bitpos: [1]; default: 0;
-         *  Configures pcr_reg registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_pcr_reg:1;
-        /** read_ree1_pcr_reg : R/W; bitpos: [2]; default: 0;
-         *  Configures pcr_reg registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_pcr_reg:1;
-        /** read_ree2_pcr_reg : R/W; bitpos: [3]; default: 0;
-         *  Configures pcr_reg registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_pcr_reg:1;
-        /** write_tee_pcr_reg : R/W; bitpos: [4]; default: 1;
-         *  Configures pcr_reg registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_pcr_reg:1;
-        /** write_ree0_pcr_reg : R/W; bitpos: [5]; default: 0;
-         *  Configures pcr_reg registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_pcr_reg:1;
-        /** write_ree1_pcr_reg : R/W; bitpos: [6]; default: 0;
-         *  Configures pcr_reg registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_pcr_reg:1;
-        /** write_ree2_pcr_reg : R/W; bitpos: [7]; default: 0;
-         *  Configures pcr_reg registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_pcr_reg:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_pcr_reg_ctrl_reg_t;
-
-/** Type of mspi_ctrl register
- *  mspi read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_mspi : R/W; bitpos: [0]; default: 1;
-         *  Configures mspi registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_mspi:1;
-        /** read_ree0_mspi : R/W; bitpos: [1]; default: 0;
-         *  Configures mspi registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_mspi:1;
-        /** read_ree1_mspi : R/W; bitpos: [2]; default: 0;
-         *  Configures mspi registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_mspi:1;
-        /** read_ree2_mspi : R/W; bitpos: [3]; default: 0;
-         *  Configures mspi registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_mspi:1;
-        /** write_tee_mspi : R/W; bitpos: [4]; default: 1;
-         *  Configures mspi registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_mspi:1;
-        /** write_ree0_mspi : R/W; bitpos: [5]; default: 0;
-         *  Configures mspi registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_mspi:1;
-        /** write_ree1_mspi : R/W; bitpos: [6]; default: 0;
-         *  Configures mspi registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_mspi:1;
-        /** write_ree2_mspi : R/W; bitpos: [7]; default: 0;
-         *  Configures mspi registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_mspi:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_mspi_ctrl_reg_t;
-
-/** Type of hp_apm_ctrl register
- *  hp_apm read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_hp_apm : R/W; bitpos: [0]; default: 1;
-         *  Configures hp_apm registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_hp_apm:1;
-        /** read_ree0_hp_apm : HRO; bitpos: [1]; default: 0;
-         *  Configures hp_apm registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_hp_apm:1;
-        /** read_ree1_hp_apm : HRO; bitpos: [2]; default: 0;
-         *  Configures hp_apm registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_hp_apm:1;
-        /** read_ree2_hp_apm : HRO; bitpos: [3]; default: 0;
-         *  Configures hp_apm registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_hp_apm:1;
-        /** write_tee_hp_apm : R/W; bitpos: [4]; default: 1;
-         *  Configures hp_apm registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_hp_apm:1;
-        /** write_ree0_hp_apm : HRO; bitpos: [5]; default: 0;
-         *  Configures hp_apm registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_hp_apm:1;
-        /** write_ree1_hp_apm : HRO; bitpos: [6]; default: 0;
-         *  Configures hp_apm registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_hp_apm:1;
-        /** write_ree2_hp_apm : HRO; bitpos: [7]; default: 0;
-         *  Configures hp_apm registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_hp_apm:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_hp_apm_ctrl_reg_t;
-
-/** Type of cpu_apm_ctrl register
- *  cpu_apm read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_cpu_apm : R/W; bitpos: [0]; default: 1;
-         *  Configures cpu_apm registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_cpu_apm:1;
-        /** read_ree0_cpu_apm : HRO; bitpos: [1]; default: 0;
-         *  Configures cpu_apm registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_cpu_apm:1;
-        /** read_ree1_cpu_apm : HRO; bitpos: [2]; default: 0;
-         *  Configures cpu_apm registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_cpu_apm:1;
-        /** read_ree2_cpu_apm : HRO; bitpos: [3]; default: 0;
-         *  Configures cpu_apm registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_cpu_apm:1;
-        /** write_tee_cpu_apm : R/W; bitpos: [4]; default: 1;
-         *  Configures cpu_apm registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_cpu_apm:1;
-        /** write_ree0_cpu_apm : HRO; bitpos: [5]; default: 0;
-         *  Configures cpu_apm registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_cpu_apm:1;
-        /** write_ree1_cpu_apm : HRO; bitpos: [6]; default: 0;
-         *  Configures cpu_apm registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_cpu_apm:1;
-        /** write_ree2_cpu_apm : HRO; bitpos: [7]; default: 0;
-         *  Configures cpu_apm registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_cpu_apm:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_cpu_apm_ctrl_reg_t;
-
-/** Type of tee_ctrl register
- *  tee read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_tee : R/W; bitpos: [0]; default: 1;
-         *  Configures tee registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_tee:1;
-        /** read_ree0_tee : HRO; bitpos: [1]; default: 0;
-         *  Configures tee registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_tee:1;
-        /** read_ree1_tee : HRO; bitpos: [2]; default: 0;
-         *  Configures tee registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_tee:1;
-        /** read_ree2_tee : HRO; bitpos: [3]; default: 0;
-         *  Configures tee registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_tee:1;
-        /** write_tee_tee : R/W; bitpos: [4]; default: 1;
-         *  Configures tee registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_tee:1;
-        /** write_ree0_tee : HRO; bitpos: [5]; default: 0;
-         *  Configures tee registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_tee:1;
-        /** write_ree1_tee : HRO; bitpos: [6]; default: 0;
-         *  Configures tee registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_tee:1;
-        /** write_ree2_tee : HRO; bitpos: [7]; default: 0;
-         *  Configures tee registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_tee:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_tee_ctrl_reg_t;
-
-/** Type of km_ctrl register
- *  crypt read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_km : R/W; bitpos: [0]; default: 1;
-         *  Configures km registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_km:1;
-        /** read_ree0_km : R/W; bitpos: [1]; default: 0;
-         *  Configures km registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_km:1;
-        /** read_ree1_km : R/W; bitpos: [2]; default: 0;
-         *  Configures km registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_km:1;
-        /** read_ree2_km : R/W; bitpos: [3]; default: 0;
-         *  Configures km registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_km:1;
-        /** write_tee_km : R/W; bitpos: [4]; default: 1;
-         *  Configures km registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_km:1;
-        /** write_ree0_km : R/W; bitpos: [5]; default: 0;
-         *  Configures km registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_km:1;
-        /** write_ree1_km : R/W; bitpos: [6]; default: 0;
-         *  Configures km registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_km:1;
-        /** write_ree2_km : R/W; bitpos: [7]; default: 0;
-         *  Configures km registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_km:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_km_ctrl_reg_t;
-
-/** Type of crypt_ctrl register
- *  crypt read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_crypt : R/W; bitpos: [0]; default: 1;
-         *  Configures crypt registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_crypt:1;
-        /** read_ree0_crypt : R/W; bitpos: [1]; default: 0;
-         *  Configures crypt registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_crypt:1;
-        /** read_ree1_crypt : R/W; bitpos: [2]; default: 0;
-         *  Configures crypt registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_crypt:1;
-        /** read_ree2_crypt : R/W; bitpos: [3]; default: 0;
-         *  Configures crypt registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_crypt:1;
-        /** write_tee_crypt : R/W; bitpos: [4]; default: 1;
-         *  Configures crypt registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_crypt:1;
-        /** write_ree0_crypt : R/W; bitpos: [5]; default: 0;
-         *  Configures crypt registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_crypt:1;
-        /** write_ree1_crypt : R/W; bitpos: [6]; default: 0;
-         *  Configures crypt registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_crypt:1;
-        /** write_ree2_crypt : R/W; bitpos: [7]; default: 0;
-         *  Configures crypt registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_crypt:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_crypt_ctrl_reg_t;
-
-/** Type of core0_trace_ctrl register
- *  core0_trace read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_core0_trace : R/W; bitpos: [0]; default: 1;
-         *  Configures core0_trace registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_core0_trace:1;
-        /** read_ree0_core0_trace : R/W; bitpos: [1]; default: 0;
-         *  Configures core0_trace registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_core0_trace:1;
-        /** read_ree1_core0_trace : R/W; bitpos: [2]; default: 0;
-         *  Configures core0_trace registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_core0_trace:1;
-        /** read_ree2_core0_trace : R/W; bitpos: [3]; default: 0;
-         *  Configures core0_trace registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_core0_trace:1;
-        /** write_tee_core0_trace : R/W; bitpos: [4]; default: 1;
-         *  Configures core0_trace registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_core0_trace:1;
-        /** write_ree0_core0_trace : R/W; bitpos: [5]; default: 0;
-         *  Configures core0_trace registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_core0_trace:1;
-        /** write_ree1_core0_trace : R/W; bitpos: [6]; default: 0;
-         *  Configures core0_trace registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_core0_trace:1;
-        /** write_ree2_core0_trace : R/W; bitpos: [7]; default: 0;
-         *  Configures core0_trace registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_core0_trace:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_core0_trace_ctrl_reg_t;
-
-/** Type of core1_trace_ctrl register
- *  core1_trace read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_core1_trace : R/W; bitpos: [0]; default: 1;
-         *  Configures core1_trace registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_core1_trace:1;
-        /** read_ree0_core1_trace : R/W; bitpos: [1]; default: 0;
-         *  Configures core1_trace registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_core1_trace:1;
-        /** read_ree1_core1_trace : R/W; bitpos: [2]; default: 0;
-         *  Configures core1_trace registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_core1_trace:1;
-        /** read_ree2_core1_trace : R/W; bitpos: [3]; default: 0;
-         *  Configures core1_trace registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_core1_trace:1;
-        /** write_tee_core1_trace : R/W; bitpos: [4]; default: 1;
-         *  Configures core1_trace registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_core1_trace:1;
-        /** write_ree0_core1_trace : R/W; bitpos: [5]; default: 0;
-         *  Configures core1_trace registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_core1_trace:1;
-        /** write_ree1_core1_trace : R/W; bitpos: [6]; default: 0;
-         *  Configures core1_trace registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_core1_trace:1;
-        /** write_ree2_core1_trace : R/W; bitpos: [7]; default: 0;
-         *  Configures core1_trace registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_core1_trace:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_core1_trace_ctrl_reg_t;
-
-/** Type of cpu_bus_monitor_ctrl register
- *  cpu_bus_monitor read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_cpu_bus_monitor : R/W; bitpos: [0]; default: 1;
-         *  Configures cpu_bus_monitor registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_cpu_bus_monitor:1;
-        /** read_ree0_cpu_bus_monitor : R/W; bitpos: [1]; default: 0;
-         *  Configures cpu_bus_monitor registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_cpu_bus_monitor:1;
-        /** read_ree1_cpu_bus_monitor : R/W; bitpos: [2]; default: 0;
-         *  Configures cpu_bus_monitor registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_cpu_bus_monitor:1;
-        /** read_ree2_cpu_bus_monitor : R/W; bitpos: [3]; default: 0;
-         *  Configures cpu_bus_monitor registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_cpu_bus_monitor:1;
-        /** write_tee_cpu_bus_monitor : R/W; bitpos: [4]; default: 1;
-         *  Configures cpu_bus_monitor registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_cpu_bus_monitor:1;
-        /** write_ree0_cpu_bus_monitor : R/W; bitpos: [5]; default: 0;
-         *  Configures cpu_bus_monitor registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_cpu_bus_monitor:1;
-        /** write_ree1_cpu_bus_monitor : R/W; bitpos: [6]; default: 0;
-         *  Configures cpu_bus_monitor registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_cpu_bus_monitor:1;
-        /** write_ree2_cpu_bus_monitor : R/W; bitpos: [7]; default: 0;
-         *  Configures cpu_bus_monitor registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_cpu_bus_monitor:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_cpu_bus_monitor_ctrl_reg_t;
-
-/** Type of intpri_reg_ctrl register
- *  intpri_reg read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_intpri_reg : R/W; bitpos: [0]; default: 1;
-         *  Configures intpri_reg registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_intpri_reg:1;
-        /** read_ree0_intpri_reg : R/W; bitpos: [1]; default: 0;
-         *  Configures intpri_reg registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_intpri_reg:1;
-        /** read_ree1_intpri_reg : R/W; bitpos: [2]; default: 0;
-         *  Configures intpri_reg registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_intpri_reg:1;
-        /** read_ree2_intpri_reg : R/W; bitpos: [3]; default: 0;
-         *  Configures intpri_reg registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_intpri_reg:1;
-        /** write_tee_intpri_reg : R/W; bitpos: [4]; default: 1;
-         *  Configures intpri_reg registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_intpri_reg:1;
-        /** write_ree0_intpri_reg : R/W; bitpos: [5]; default: 0;
-         *  Configures intpri_reg registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_intpri_reg:1;
-        /** write_ree1_intpri_reg : R/W; bitpos: [6]; default: 0;
-         *  Configures intpri_reg registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_intpri_reg:1;
-        /** write_ree2_intpri_reg : R/W; bitpos: [7]; default: 0;
-         *  Configures intpri_reg registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_intpri_reg:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_intpri_reg_ctrl_reg_t;
-
-/** Type of cache_cfg_ctrl register
- *  cache_cfg read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_cache_cfg : R/W; bitpos: [0]; default: 1;
-         *  Configures cache_cfg registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_cache_cfg:1;
-        /** read_ree0_cache_cfg : R/W; bitpos: [1]; default: 0;
-         *  Configures cache_cfg registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_cache_cfg:1;
-        /** read_ree1_cache_cfg : R/W; bitpos: [2]; default: 0;
-         *  Configures cache_cfg registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_cache_cfg:1;
-        /** read_ree2_cache_cfg : R/W; bitpos: [3]; default: 0;
-         *  Configures cache_cfg registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_cache_cfg:1;
-        /** write_tee_cache_cfg : R/W; bitpos: [4]; default: 1;
-         *  Configures cache_cfg registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_cache_cfg:1;
-        /** write_ree0_cache_cfg : R/W; bitpos: [5]; default: 0;
-         *  Configures cache_cfg registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_cache_cfg:1;
-        /** write_ree1_cache_cfg : R/W; bitpos: [6]; default: 0;
-         *  Configures cache_cfg registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_cache_cfg:1;
-        /** write_ree2_cache_cfg : R/W; bitpos: [7]; default: 0;
-         *  Configures cache_cfg registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_cache_cfg:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_cache_cfg_ctrl_reg_t;
-
-/** Type of modem_ctrl register
- *  modem read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_modem : R/W; bitpos: [0]; default: 1;
-         *  Configures modem registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_modem:1;
-        /** read_ree0_modem : R/W; bitpos: [1]; default: 0;
-         *  Configures modem registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_modem:1;
-        /** read_ree1_modem : R/W; bitpos: [2]; default: 0;
-         *  Configures modem registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_modem:1;
-        /** read_ree2_modem : R/W; bitpos: [3]; default: 0;
-         *  Configures modem registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_modem:1;
-        /** write_tee_modem : R/W; bitpos: [4]; default: 1;
-         *  Configures modem registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_modem:1;
-        /** write_ree0_modem : R/W; bitpos: [5]; default: 0;
-         *  Configures modem registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_modem:1;
-        /** write_ree1_modem : R/W; bitpos: [6]; default: 0;
-         *  Configures modem registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_modem:1;
-        /** write_ree2_modem : R/W; bitpos: [7]; default: 0;
-         *  Configures modem registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_modem:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_modem_ctrl_reg_t;
-
-/** Type of zero_det_ctrl register
- *  zero_det read/write control register
- */
-typedef union {
-    struct {
-        /** read_tee_zero_det : R/W; bitpos: [0]; default: 1;
-         *  Configures zero_det registers read permission in tee mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_tee_zero_det:1;
-        /** read_ree0_zero_det : R/W; bitpos: [1]; default: 0;
-         *  Configures zero_det registers read permission in ree0 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree0_zero_det:1;
-        /** read_ree1_zero_det : R/W; bitpos: [2]; default: 0;
-         *  Configures zero_det registers read permission in ree1 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree1_zero_det:1;
-        /** read_ree2_zero_det : R/W; bitpos: [3]; default: 0;
-         *  Configures zero_det registers read permission in ree2 mode.
-         *  0: can not be read
-         *  1: can be read
-         */
-        uint32_t read_ree2_zero_det:1;
-        /** write_tee_zero_det : R/W; bitpos: [4]; default: 1;
-         *  Configures zero_det registers write permission in tee mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_tee_zero_det:1;
-        /** write_ree0_zero_det : R/W; bitpos: [5]; default: 0;
-         *  Configures zero_det registers write permission in ree0 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree0_zero_det:1;
-        /** write_ree1_zero_det : R/W; bitpos: [6]; default: 0;
-         *  Configures zero_det registers write permission in ree1 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree1_zero_det:1;
-        /** write_ree2_zero_det : R/W; bitpos: [7]; default: 0;
-         *  Configures zero_det registers write permission in ree2 mode.
-         *  0: can not be write
-         *  1: can be write
-         */
-        uint32_t write_ree2_zero_det:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} tee_zero_det_ctrl_reg_t;
-
-
-/** Group: config register */
-/** Type of bus_err_conf register
- *  Clock gating register
- */
-typedef union {
-    struct {
-        /** bus_err_resp_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether return error response to cpu when access blocked
-         *  0: disable error response
-         *  1: enable error response
-         */
-        uint32_t bus_err_resp_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} tee_bus_err_conf_reg_t;
-
-
-/** Group: clock gating register */
-/** Type of clock_gate register
- *  Clock gating register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  Configures whether to keep the clock always on.
-         *  0: enable automatic clock gating
-         *  1: keep the clock always on
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} tee_clock_gate_reg_t;
-
-
-/** Group: Version control register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 37818480;
-         *  Version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} tee_date_reg_t;
-
-
-typedef struct {
-    volatile tee_mn_mode_ctrl_reg_t mn_mode_ctrl[32];
-    volatile tee_gpspi0_ctrl_reg_t gpspi0_ctrl;
-    volatile tee_gpspi1_ctrl_reg_t gpspi1_ctrl;
-    volatile tee_uart0_ctrl_reg_t uart0_ctrl;
-    volatile tee_uart1_ctrl_reg_t uart1_ctrl;
-    volatile tee_uhci_ctrl_reg_t uhci_ctrl;
-    volatile tee_i2c0_ctrl_reg_t i2c0_ctrl;
-    volatile tee_i2c1_ctrl_reg_t i2c1_ctrl;
-    volatile tee_i2s_ctrl_reg_t i2s_ctrl;
-    volatile tee_parl_io_ctrl_reg_t parl_io_ctrl;
-    volatile tee_pwm0_ctrl_reg_t pwm0_ctrl;
-    volatile tee_pwm1_ctrl_reg_t pwm1_ctrl;
-    volatile tee_ledc_ctrl_reg_t ledc_ctrl;
-    volatile tee_can_ctrl_reg_t can_ctrl;
-    volatile tee_usb_serial_jtag_ctrl_reg_t usb_serial_jtag_ctrl;
-    volatile tee_rmt_ctrl_reg_t rmt_ctrl;
-    volatile tee_gdma_ctrl_reg_t gdma_ctrl;
-    volatile tee_regdma_ctrl_reg_t regdma_ctrl;
-    volatile tee_etm_ctrl_reg_t etm_ctrl;
-    volatile tee_intmtx_core0_ctrl_reg_t intmtx_core0_ctrl;
-    volatile tee_intmtx_core1_ctrl_reg_t intmtx_core1_ctrl;
-    volatile tee_apb_adc_ctrl_reg_t apb_adc_ctrl;
-    volatile tee_timergroup0_ctrl_reg_t timergroup0_ctrl;
-    volatile tee_timergroup1_ctrl_reg_t timergroup1_ctrl;
-    volatile tee_systimer_ctrl_reg_t systimer_ctrl;
-    volatile tee_misc_ctrl_reg_t misc_ctrl;
-    volatile tee_src_ctrl_reg_t src_ctrl;
-    volatile tee_usb_otg_fs_core_ctrl_reg_t usb_otg_fs_core_ctrl;
-    volatile tee_usb_otg_fs_phy_ctrl_reg_t usb_otg_fs_phy_ctrl;
-    volatile tee_pvt_monitor_ctrl_reg_t pvt_monitor_ctrl;
-    volatile tee_pcnt_ctrl_reg_t pcnt_ctrl;
-    volatile tee_iomux_ctrl_reg_t iomux_ctrl;
-    volatile tee_psram_mem_monitor_ctrl_reg_t psram_mem_monitor_ctrl;
-    volatile tee_mem_acs_monitor_ctrl_reg_t mem_acs_monitor_ctrl;
-    volatile tee_hp_system_reg_ctrl_reg_t hp_system_reg_ctrl;
-    volatile tee_pcr_reg_ctrl_reg_t pcr_reg_ctrl;
-    volatile tee_mspi_ctrl_reg_t mspi_ctrl;
-    volatile tee_hp_apm_ctrl_reg_t hp_apm_ctrl;
-    volatile tee_cpu_apm_ctrl_reg_t cpu_apm_ctrl;
-    volatile tee_tee_ctrl_reg_t tee_ctrl;
-    volatile tee_km_ctrl_reg_t km_ctrl;
-    volatile tee_crypt_ctrl_reg_t crypt_ctrl;
-    volatile tee_core0_trace_ctrl_reg_t core0_trace_ctrl;
-    volatile tee_core1_trace_ctrl_reg_t core1_trace_ctrl;
-    volatile tee_cpu_bus_monitor_ctrl_reg_t cpu_bus_monitor_ctrl;
-    volatile tee_intpri_reg_ctrl_reg_t intpri_reg_ctrl;
-    volatile tee_cache_cfg_ctrl_reg_t cache_cfg_ctrl;
-    volatile tee_modem_ctrl_reg_t modem_ctrl;
-    volatile tee_zero_det_ctrl_reg_t zero_det_ctrl;
-    uint32_t reserved_140[940];
-    volatile tee_bus_err_conf_reg_t bus_err_conf;
-    uint32_t reserved_ff4;
-    volatile tee_clock_gate_reg_t clock_gate;
-    volatile tee_date_reg_t date;
-} tee_dev_t;
-
-extern tee_dev_t TEE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/cpu_apm_reg.h b/components/soc/esp32h4/register/soc/cpu_apm_reg.h
similarity index 100%
rename from components/soc/esp32h4/register/hw_ver_mp/soc/cpu_apm_reg.h
rename to components/soc/esp32h4/register/soc/cpu_apm_reg.h
diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/cpu_apm_struct.h b/components/soc/esp32h4/register/soc/cpu_apm_struct.h
similarity index 100%
rename from components/soc/esp32h4/register/hw_ver_mp/soc/cpu_apm_struct.h
rename to components/soc/esp32h4/register/soc/cpu_apm_struct.h
diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_reg.h b/components/soc/esp32h4/register/soc/interrupt_matrix_reg.h
similarity index 100%
rename from components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_reg.h
rename to components/soc/esp32h4/register/soc/interrupt_matrix_reg.h
diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_struct.h b/components/soc/esp32h4/register/soc/interrupt_matrix_struct.h
similarity index 100%
rename from components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_struct.h
rename to components/soc/esp32h4/register/soc/interrupt_matrix_struct.h
diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/pmu_reg.h b/components/soc/esp32h4/register/soc/pmu_reg.h
similarity index 100%
rename from components/soc/esp32h4/register/hw_ver_mp/soc/pmu_reg.h
rename to components/soc/esp32h4/register/soc/pmu_reg.h
diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/pmu_struct.h b/components/soc/esp32h4/register/soc/pmu_struct.h
similarity index 100%
rename from components/soc/esp32h4/register/hw_ver_mp/soc/pmu_struct.h
rename to components/soc/esp32h4/register/soc/pmu_struct.h
diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/tee_reg.h b/components/soc/esp32h4/register/soc/tee_reg.h
similarity index 100%
rename from components/soc/esp32h4/register/hw_ver_mp/soc/tee_reg.h
rename to components/soc/esp32h4/register/soc/tee_reg.h
diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/tee_struct.h b/components/soc/esp32h4/register/soc/tee_struct.h
similarity index 100%
rename from components/soc/esp32h4/register/hw_ver_mp/soc/tee_struct.h
rename to components/soc/esp32h4/register/soc/tee_struct.h