diff --git a/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c b/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c
index cc887628f2..e220e0e116 100644
--- a/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c
+++ b/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -103,8 +103,8 @@ esp_err_t esp_lcd_new_dsi_bus(const esp_lcd_dsi_bus_config_t *bus_config, esp_lc
 
     // initialize the DSI operation mode: command mode
     mipi_dsi_host_ll_enable_video_mode(hal->host, false);
-    // place the clock lane in low power mode, we will switch to high speed mode later when DPI stream is ready
-    mipi_dsi_host_ll_set_clock_lane_state(hal->host, MIPI_DSI_LL_CLOCK_LANE_STATE_LP);
+    // set clock lane state: force HS keeps clock in high-speed mode continuously, auto lets the DSI host manage transitions
+    mipi_dsi_host_ll_set_clock_lane_state(hal->host, bus_config->flags.clock_lane_force_hs ? MIPI_DSI_LL_CLOCK_LANE_STATE_HS : MIPI_DSI_LL_CLOCK_LANE_STATE_AUTO);
     // Set the time that is required by the clock and data lanes to go from high-speed to low-power and from low-power to high-speed
     mipi_dsi_phy_ll_set_switch_time(hal->host, 50, 104, 46, 128);
 
diff --git a/components/esp_lcd/dsi/esp_lcd_panel_dpi.c b/components/esp_lcd/dsi/esp_lcd_panel_dpi.c
index 74c95b4a71..f9e2585ba8 100644
--- a/components/esp_lcd/dsi/esp_lcd_panel_dpi.c
+++ b/components/esp_lcd/dsi/esp_lcd_panel_dpi.c
@@ -464,8 +464,6 @@ static esp_err_t dpi_panel_init(esp_lcd_panel_t *panel)
 
     // enable the video mode
     mipi_dsi_host_ll_enable_video_mode(hal->host, true);
-    // switch the clock lane to high speed mode
-    mipi_dsi_host_ll_set_clock_lane_state(hal->host, MIPI_DSI_LL_CLOCK_LANE_STATE_AUTO);
 
     // enable the DPI output of the DSI bridge
     mipi_dsi_brg_ll_enable_dpi_output(hal->bridge, true);
diff --git a/components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h b/components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h
index d0c1594f20..efc2b39550 100644
--- a/components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h
+++ b/components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h
@@ -24,6 +24,10 @@ typedef struct {
     uint8_t num_data_lanes;                  /*!< Number of data lanes, if set to 0, the driver will fallback to use maximum number of lanes */
     mipi_dsi_phy_pllref_clock_source_t phy_clk_src; /*!< The clock source for the PHY PLL */
     float lane_bit_rate_mbps;                /*!< Lane bit rate in Mbps */
+    /// Extra configuration flags for MIPI DSI bus
+    struct extra_dsi_bus_flags {
+        uint32_t clock_lane_force_hs: 1;     /*!< Force the clock lane to high speed mode */
+    } flags;                                 /*!< Extra configuration flags */
 } esp_lcd_dsi_bus_config_t;
 
 /**